From 715cce65b889214a728dd44759204316aff29006 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:42 -0500 Subject: Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_NAND_DBW_8 CONFIG_SYS_NAND_DBW_16 Note that all instances of the code check for CONFIG_SYS_NAND_DBW_16 being defined, and then "else" to CONFIG_SYS_NAND_DBW_8 whereas all of the configs set CONFIG_SYS_NAND_DBW_8. So we introduce CONFIG_SYS_NAND_DBW_16 as an option. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- include/configs/at91sam9260ek.h | 1 - include/configs/at91sam9261ek.h | 1 - include/configs/at91sam9263ek.h | 1 - include/configs/at91sam9m10g45ek.h | 1 - include/configs/at91sam9rlek.h | 1 - include/configs/at91sam9x5ek.h | 1 - include/configs/corvus.h | 1 - include/configs/ethernut5.h | 1 - include/configs/gardena-smart-gateway-at91sam.h | 1 - include/configs/meesc.h | 1 - include/configs/pm9261.h | 1 - include/configs/pm9263.h | 1 - include/configs/pm9g45.h | 1 - include/configs/smartweb.h | 1 - include/configs/snapper9g45.h | 1 - include/configs/taurus.h | 1 - 16 files changed, 16 deletions(-) (limited to 'include') diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index d51da9d5067..60b47379e5e 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -44,7 +44,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 5dc8f21a853..d80a686e9ee 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -25,7 +25,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD22 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) /* our CLE is AD21 */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index d31a7742a17..89a8e43e1e0 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -151,7 +151,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 01085476a43..55edd706ead 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -21,7 +21,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index c60c248b747..0a512c217f8 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -26,7 +26,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 71a2863bfc2..b8a14d571d6 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -28,7 +28,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 0596afbf9fa..3e7c0c0d883 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -38,7 +38,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 22647abee0d..a18920d3f09 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -38,7 +38,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index 52b9fe2b171..3d62efb38ff 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -23,7 +23,6 @@ /* NAND flash */ #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 9f913fad168..30267e29a12 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -53,7 +53,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND # define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ -# define CONFIG_SYS_NAND_DBW_8 # define CONFIG_SYS_NAND_MASK_ALE (1 << 21) # define CONFIG_SYS_NAND_MASK_CLE (1 << 22) # define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 278f1b5cc62..6a89fb1fa9a 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -130,7 +130,6 @@ /* NAND flash */ #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD22 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) /* our CLE is AD21 */ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 7c23206a300..c56db4d793d 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -147,7 +147,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index 35fd5256836..7d3a326deaf 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -26,7 +26,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index a77215d19be..c8f5816fed9 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -55,7 +55,6 @@ /* NAND flash settings */ #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index c56fb378312..6aba1d3194c 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -31,7 +31,6 @@ /* NAND Flash */ #define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 45780d9a4ea..ca9616d8af5 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -55,7 +55,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -- cgit v1.3.1 From 50493dd1f9f56097721c043fb7bd55c4cb2cc5e4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:43 -0500 Subject: Remove unused symbols This commit removes the following unused symbols: CONFIG_SYS_NAND_DDR_LAW CONFIG_SYS_NAND_ECCSTEPS CONFIG_SYS_NAND_ECCTOTAL CONFIG_SYS_NAND_ENABLE_PIN_SPL CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES CONFIG_SYS_NAND_U_BOOT_RELOC_SP Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- include/configs/P1010RDB.h | 2 -- include/configs/T102xRDB.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/colibri_imx7.h | 1 - include/configs/da850evm.h | 4 ---- include/configs/omapl138_lcdk.h | 4 ---- include/configs/siemens-am33x-common.h | 4 ---- include/configs/smartweb.h | 1 - include/configs/taurus.h | 1 - 12 files changed, 22 deletions(-) (limited to 'include') diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index addb306d57f..3448766d8e5 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -235,8 +235,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NAND_FTIM3 0x0 #endif -#define CONFIG_SYS_NAND_DDR_LAW 11 - /* Set up IFC registers for boot location NOR/NAND */ #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 62c4177f309..4b2327d3232 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -234,7 +234,6 @@ FTIM2_NAND_TWHRE(0x1e)) #define CONFIG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index ad8037e7a8c..e7d82bf4118 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -210,7 +210,6 @@ FTIM2_NAND_TWHRE(0x1e)) #define CONFIG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 2dcaeda78b8..08195505b1d 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -198,7 +198,6 @@ FTIM2_NAND_TWHRE(0x1e)) #define CONFIG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 223c8567517..75d9200d568 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -174,7 +174,6 @@ FTIM2_NAND_TWHRE(0x1e)) #define CONFIG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 12edfdd68db..d79789af0e1 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -231,7 +231,6 @@ FTIM2_NAND_TWHRE(0x1e)) #define CONFIG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 7380440ae7a..5c7a9f2e69f 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -167,7 +167,6 @@ #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND /* NAND stuff */ #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES #endif /* USB Configs */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 281cbe37f9d..262a79be015 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -117,10 +117,6 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ - CONFIG_SYS_NAND_U_BOOT_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_NAND_ECCPOS { \ 24, 25, 26, 27, 28, \ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 41039302415..4b24d614e1a 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -116,10 +116,6 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ - CONFIG_SYS_NAND_U_BOOT_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_NAND_ECCPOS { \ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 87da5e4232c..dd247d2fd98 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -59,10 +59,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ECCSTEPS 4 -#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ - CONFIG_SYS_NAND_ECCSTEPS) - #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE /* diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index c8f5816fed9..538aad9a7bb 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -92,7 +92,6 @@ /* Defines for SPL */ -#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE diff --git a/include/configs/taurus.h b/include/configs/taurus.h index ca9616d8af5..5ab087da8bd 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -126,7 +126,6 @@ /* Defines for SPL */ -#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -- cgit v1.3.1 From 60db32502c7f5d54c4cd4e485b95204166a83678 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:44 -0500 Subject: Convert CONFIG_SYS_NAND_HW_ECC_OOBFIRST to Kconfig This converts the following to Kconfig: CONFIG_SYS_NAND_HW_ECC_OOBFIRST Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 4 ---- configs/da850evm_nand_defconfig | 1 + configs/omapl138_lcdk_defconfig | 1 + drivers/mtd/nand/raw/Kconfig | 5 +++++ include/configs/da850evm.h | 1 - include/configs/omapl138_lcdk.h | 1 - 6 files changed, 7 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/README b/README index d75c3fbc859..4309d933866 100644 --- a/README +++ b/README @@ -1378,10 +1378,6 @@ The following options need to be configured: CONFIG_SYS_NAND_U_BOOT_START Entry point in loaded image to jump to - CONFIG_SYS_NAND_HW_ECC_OOBFIRST - Define this if you need to first read the OOB and then the - data. This is used, for example, on davinci platforms. - CONFIG_SPL_RAM_DEVICE Support for running image already present in ram, in SPL binary diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 30454a3787a..84563b2a3c7 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -87,6 +87,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y +CONFIG_SYS_NAND_HW_ECC_OOBFIRST=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 51c78dc51ad..a067c017794 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -84,6 +84,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y +CONFIG_SYS_NAND_HW_ECC_OOBFIRST=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 48a7507c643..49b7a4b04bb 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -712,6 +712,11 @@ config SPL_NAND_SIMPLE help Support for NAND boot using simple NAND drivers that expose the cmd_ctrl() interface. + +config SYS_NAND_HW_ECC_OOBFIRST + bool "In SPL, read the OOB first and then the data from NAND" + depends on SPL_NAND_SIMPLE + endif endif # if NAND diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 262a79be015..abf5db934c5 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -113,7 +113,6 @@ #define CONFIG_SYS_NAND_MASK_CLE 0x10 #define CONFIG_SYS_NAND_MASK_ALE 0x8 #undef CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 4b24d614e1a..184360f7e90 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -111,7 +111,6 @@ #define CONFIG_SYS_NAND_MASK_CLE 0x10 #define CONFIG_SYS_NAND_MASK_ALE 0x8 #undef CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 -- cgit v1.3.1 From 41fa8f471d41fd42a249e3f24e5ecb2fa8f1b1d4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:45 -0500 Subject: Convert CONFIG_SYS_NAND_HW_ECC to Kconfig This converts the following to Kconfig: CONFIG_SYS_NAND_HW_ECC Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- configs/da850evm_nand_defconfig | 1 - configs/k2e_evm_defconfig | 1 - configs/k2e_hs_evm_defconfig | 1 - configs/k2hk_evm_defconfig | 1 - configs/k2hk_hs_evm_defconfig | 1 - configs/k2l_evm_defconfig | 1 - configs/k2l_hs_evm_defconfig | 1 - configs/omapl138_lcdk_defconfig | 1 - drivers/mtd/nand/raw/Kconfig | 14 +++++++++++++- drivers/mtd/nand/raw/davinci_nand.c | 7 +++---- include/configs/da850evm.h | 1 - include/configs/omapl138_lcdk.h | 1 - 12 files changed, 16 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 84563b2a3c7..a7aaf46ea51 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -86,7 +86,6 @@ CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_SYS_NAND_HW_ECC_OOBFIRST=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_PAGE_COUNT=0x40 diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 9bf2e862b06..977348e73fc 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -79,7 +79,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index afa4dc1b419..afba285ffb2 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -54,7 +54,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index cbf948f578e..6c4563912b5 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -79,7 +79,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 2480547a51c..33624badae0 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -54,7 +54,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index f4c8c5e233a..e28054bcc72 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -79,7 +79,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 051cd234818..8f8bb549130 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -57,7 +57,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index a067c017794..ff3b5f0857b 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -83,7 +83,6 @@ CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_SYS_NAND_HW_ECC_OOBFIRST=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_PAGE_COUNT=0x40 diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 49b7a4b04bb..0e428418b25 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -148,9 +148,21 @@ config NAND_DAVINCI Enable this driver for NAND flash controllers available in TI Davinci and Keystone2 platforms +choice + prompt "Type of ECC used on NAND" + default SYS_NAND_4BIT_HW_ECC_OOBFIRST + depends on NAND_DAVINCI + +config SYS_NAND_HW_ECC + bool "Use 1-bit HW ECC" + config SYS_NAND_4BIT_HW_ECC_OOBFIRST bool "Use 4-bit HW ECC with OOB at the front" - depends on NAND_DAVINCI + +config SYS_NAND_SOFT_ECC + bool "Use software ECC" + +endchoice config KEYSTONE_RBL_NAND depends on ARCH_KEYSTONE diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index 9158d94de25..54aed136388 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -766,10 +766,7 @@ static void davinci_nand_init(struct nand_chip *nand) nand->ecc.calculate = nand_davinci_calculate_ecc; nand->ecc.correct = nand_davinci_correct_data; nand->ecc.hwctl = nand_davinci_enable_hwecc; -#else - nand->ecc.mode = NAND_ECC_SOFT; -#endif /* CONFIG_SYS_NAND_HW_ECC */ -#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#elif defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST) nand->ecc.mode = NAND_ECC_HW_OOB_FIRST; nand->ecc.size = 512; nand->ecc.bytes = 10; @@ -778,6 +775,8 @@ static void davinci_nand_init(struct nand_chip *nand) nand->ecc.correct = nand_davinci_4bit_correct_data; nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc; nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst; +#elif defined(CONFIG_SYS_NAND_SOFT_ECC) + nand->ecc.mode = NAND_ECC_SOFT; #endif /* Set address of hardware control function */ nand->cmd_ctrl = nand_davinci_hwcontrol; diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index abf5db934c5..11f104bcb86 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -112,7 +112,6 @@ #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE #define CONFIG_SYS_NAND_MASK_CLE 0x10 #define CONFIG_SYS_NAND_MASK_ALE 0x8 -#undef CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 184360f7e90..233e7b4ee53 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -110,7 +110,6 @@ #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE #define CONFIG_SYS_NAND_MASK_CLE 0x10 #define CONFIG_SYS_NAND_MASK_ALE 0x8 -#undef CONFIG_SYS_NAND_HW_ECC #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 -- cgit v1.3.1 From b41641d52efa242b38fbe5f976331005e329487a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:46 -0500 Subject: mtd: nand: raw: atmel_nand: Use ATMEL_BASE_ECC directly This is the only driver, and only one platform makes use of, setting CONFIG_SYS_NAND_ECC_BASE. Reference ATMEL_BASE_ECC directly in this case. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- drivers/mtd/nand/raw/atmel_nand.c | 18 +++++++++--------- include/configs/snapper9g45.h | 1 - 2 files changed, 9 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index 61bfd175be4..a541af6db4a 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -1012,13 +1012,13 @@ static int atmel_nand_calculate(struct mtd_info *mtd, unsigned int ecc_value; /* get the first 2 ECC bytes */ - ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR); + ecc_value = ecc_readl(ATMEL_BASE_ECC, PR); ecc_code[0] = ecc_value & 0xFF; ecc_code[1] = (ecc_value >> 8) & 0xFF; /* get the last 2 ECC bytes */ - ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY; + ecc_value = ecc_readl(ATMEL_BASE_ECC, NPR) & ATMEL_ECC_NPARITY; ecc_code[2] = ecc_value & 0xFF; ecc_code[3] = (ecc_value >> 8) & 0xFF; @@ -1101,16 +1101,16 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, unsigned int ecc_word, ecc_bit; /* get the status from the Status Register */ - ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR); + ecc_status = ecc_readl(ATMEL_BASE_ECC, SR); /* if there's no error */ if (likely(!(ecc_status & ATMEL_ECC_RECERR))) return 0; /* get error bit offset (4 bits) */ - ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR; + ecc_bit = ecc_readl(ATMEL_BASE_ECC, PR) & ATMEL_ECC_BITADDR; /* get word address (12 bits) */ - ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR; + ecc_word = ecc_readl(ATMEL_BASE_ECC, PR) & ATMEL_ECC_WORDADDR; ecc_word >>= 4; /* if there are multiple errors */ @@ -1180,22 +1180,22 @@ int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd) switch (mtd->writesize) { case 512: nand->ecc.layout = &atmel_oobinfo_small; - ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, + ecc_writel(ATMEL_BASE_ECC, MR, ATMEL_ECC_PAGESIZE_528); break; case 1024: nand->ecc.layout = &atmel_oobinfo_large; - ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, + ecc_writel(ATMEL_BASE_ECC, MR, ATMEL_ECC_PAGESIZE_1056); break; case 2048: nand->ecc.layout = &atmel_oobinfo_large; - ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, + ecc_writel(ATMEL_BASE_ECC, MR, ATMEL_ECC_PAGESIZE_2112); break; case 4096: nand->ecc.layout = &atmel_oobinfo_large; - ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, + ecc_writel(ATMEL_BASE_ECC, MR, ATMEL_ECC_PAGESIZE_4224); break; default: diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 6aba1d3194c..29462c526ec 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -29,7 +29,6 @@ /* Mem test settings */ /* NAND Flash */ -#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ -- cgit v1.3.1 From 4d3495deb653ad4e50051e846667eaad8257e1f9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:47 -0500 Subject: Convert CONFIG_SYS_NAND_MAX_OOBFREE et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_NAND_MAX_OOBFREE CONFIG_SYS_NAND_MAX_ECCPOS Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- configs/CHIP_pro_defconfig | 1 + configs/Nintendo_NES_Classic_Edition_defconfig | 1 + configs/am3517_evm_defconfig | 2 ++ configs/ls1088aqds_defconfig | 2 ++ configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088aqds_qspi_defconfig | 2 ++ configs/ls1088aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1088aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1088aqds_tfa_defconfig | 2 ++ configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_qspi_defconfig | 2 ++ configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_sdcard_qspi_defconfig | 2 ++ configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_tfa_defconfig | 2 ++ configs/ls2080aqds_SECURE_BOOT_defconfig | 2 ++ configs/ls2080aqds_defconfig | 2 ++ configs/ls2080aqds_nand_defconfig | 2 ++ configs/ls2080aqds_qspi_defconfig | 2 ++ configs/ls2080aqds_sdcard_defconfig | 2 ++ configs/ls2080ardb_SECURE_BOOT_defconfig | 2 ++ configs/ls2080ardb_defconfig | 2 ++ configs/ls2080ardb_nand_defconfig | 2 ++ configs/ls2088aqds_tfa_defconfig | 2 ++ configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls2088ardb_tfa_defconfig | 2 ++ configs/omap35_logic_defconfig | 2 ++ configs/omap35_logic_somlv_defconfig | 2 ++ configs/omap3_logic_defconfig | 2 ++ configs/omap3_logic_somlv_defconfig | 2 ++ doc/README.nand | 10 ---------- drivers/mtd/Kconfig | 18 ++++++++++++++++++ include/configs/T4240RDB.h | 2 -- include/configs/am3517_evm.h | 2 -- include/configs/ls1088aqds.h | 3 --- include/configs/ls1088ardb.h | 3 --- include/configs/ls2080aqds.h | 3 --- include/configs/ls2080ardb.h | 3 --- include/configs/omap3_logic.h | 2 -- include/configs/sunxi-common.h | 4 ---- 40 files changed, 76 insertions(+), 32 deletions(-) (limited to 'include') diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 0e7d5e7c96f..2f558454e81 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0x100 +CONFIG_SYS_NAND_MAX_ECCPOS=1664 CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 CONFIG_CONS_INDEX=2 diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig index 94060ab107a..1b7a4574083 100644 --- a/configs/Nintendo_NES_Classic_Edition_defconfig +++ b/configs/Nintendo_NES_Classic_Edition_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 +CONFIG_SYS_NAND_MAX_ECCPOS=1664 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_ELDO2_VOLT=1800 CONFIG_CONS_INDEX=5 diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 45332e2d60f..0839d366cfd 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -81,6 +81,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=56 CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y CONFIG_DRIVER_TI_EMAC_USE_RMII=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index 1e865909aa1..8556c003555 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -83,6 +83,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index cfe15406e8d..d4f2268041f 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -69,6 +69,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_EON=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 4e0e7c302a3..af63278bb3c 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -72,6 +72,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_EON=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 0a7541d5e68..6b42170ffbd 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -104,6 +104,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index d9f27816ebf..dedefb3a0a3 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -92,6 +92,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_EON=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index cce2d9ab195..60f26f01830 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -91,6 +91,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_EON=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index 4c46384a6f8..a819ebfefff 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -72,6 +72,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 796264502da..c5697533381 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -75,6 +75,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 504db136968..2b96382f248 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -95,6 +95,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 8053bc17bb0..42636353840 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -95,6 +95,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 7ba59404810..2e812943fd3 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -71,6 +71,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index ff5784bf6c5..9c12f2be9ce 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -77,6 +77,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 8899fd930f0..817ae8d728b 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -74,6 +74,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index a9f52ae5a1f..b3e75847cca 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -77,6 +77,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 0b70e7b02b8..effcd33629b 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -91,6 +91,8 @@ CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 648a5390507..eb57948414d 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -71,6 +71,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index 318822bd83d..e5702b81592 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -85,6 +85,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 8ae8b52f6a8..face1e05320 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -76,6 +76,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index d548bcab3f1..ba6f5090d47 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -79,6 +79,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index a49fe87f71d..50002900303 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -100,6 +100,8 @@ CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000 +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 4c1e7421bf3..9c6012460b3 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -88,6 +88,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 93be74d00cd..dc9a47463f4 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -81,6 +81,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index c2bf451dd90..36109856809 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -88,6 +88,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index 93daa460baf..84e267da584 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -80,6 +80,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=56 CONFIG_SMC911X=y CONFIG_SMC911X_32_BIT=y CONFIG_PINCTRL=y diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index de33825d13d..471e0556fa8 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -88,6 +88,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=56 CONFIG_SMC911X=y CONFIG_SMC911X_32_BIT=y CONFIG_PINCTRL=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index e2c6dfcf48c..67db3afd7fc 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -79,6 +79,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=56 CONFIG_SMC911X=y CONFIG_SMC911X_32_BIT=y CONFIG_PINCTRL=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index 3237c4280a8..e18cbaa5c18 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -89,6 +89,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=56 CONFIG_SMC911X=y CONFIG_SMC911X_32_BIT=y CONFIG_PINCTRL=y diff --git a/doc/README.nand b/doc/README.nand index d1ce30768b9..a3c3ab4b950 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -99,16 +99,6 @@ Configuration Options: CONFIG_CMD_NAND_TORTURE Enables the torture command (see description of this command below). - CONFIG_SYS_NAND_MAX_ECCPOS - If specified, overrides the maximum number of ECC bytes - supported. Useful for reducing image size, especially with SPL. - This must be at least 48 if nand_base.c is used. - - CONFIG_SYS_NAND_MAX_OOBFREE - If specified, overrides the maximum number of free OOB regions - supported. Useful for reducing image size, especially with SPL. - This must be at least 2 if nand_base.c is used. - CONFIG_SYS_NAND_MAX_CHIPS The maximum number of NAND chips per device to be supported. diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index fcdb450f77a..d8e2dec0a8d 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -212,6 +212,24 @@ config SYS_MAX_FLASH_BANKS_DETECT source "drivers/mtd/nand/Kconfig" +config SYS_NAND_MAX_OOBFREE + int "Maximum number of free OOB regions supported" + depends on SAMSUNG_ONENAND || MTD_RAW_NAND + range 2 32 + default 32 + help + Set the maximum number of free OOB regions supported. Useful for + reducing image size, especially with SPL. + +config SYS_NAND_MAX_ECCPOS + int "Maximum number of ECC bytes supported" + depends on SAMSUNG_ONENAND || MTD_RAW_NAND + range 48 2147483647 + default 680 + help + Set the maximum number of ECC bytes supported. Useful for reducing + image size, especially with SPL. + config SYS_NAND_MAX_CHIPS int "NAND max chips" depends on MTD_RAW_NAND || CMD_ONENAND || TARGET_S5PC210_UNIVERSAL || \ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index d79789af0e1..cfd9cb3e7c8 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -197,8 +197,6 @@ + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} /* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 #define CONFIG_SYS_NAND_BASE 0xff800000 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index e0f5f2b0440..2eb7a51ce2e 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -25,8 +25,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 13 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE /* NAND block size is 128 KiB. Synchronize these values with * corresponding Device Tree entries in Linux: diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index d50b76b89ae..3a2fba6b04e 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -69,9 +69,6 @@ #endif #endif -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - #define CONFIG_SYS_NAND_CSPR_EXT (0x0) #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 4edf40b0b72..e2ae3026c29 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -53,9 +53,6 @@ #endif #endif -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - #define CONFIG_SYS_NAND_CSPR_EXT (0x0) #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 1fa4aa3734d..e6019870d8a 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -70,9 +70,6 @@ CONFIG_SYS_FLASH_BASE + 0x40000000} #endif -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - #define CONFIG_SYS_NAND_CSPR_EXT (0x0) #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index e1c66c5dcc0..382d516c08b 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -67,9 +67,6 @@ CONFIG_SYS_FLASH_BASE + 0x40000000} #endif -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - #define CONFIG_SYS_NAND_CSPR_EXT (0x0) #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 442a3cad220..7c0bdcbb115 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -26,8 +26,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 13 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 #endif /* Environment information */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 720768629d6..d9e4c8b699f 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -71,10 +71,6 @@ #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ -#ifdef CONFIG_NAND_SUNXI -#define CONFIG_SYS_NAND_MAX_ECCPOS 1664 -#endif - /* mmc config */ #define CONFIG_MMC_SUNXI_SLOT 0 -- cgit v1.3.1 From 1a792803d8905373bc04bbc2a4dc7d0d1ecdd967 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:48 -0500 Subject: Convert CONFIG_SYS_NAND_NO_SUBPAGE_WRITE to Kconfig This converts the following to Kconfig: CONFIG_SYS_NAND_NO_SUBPAGE_WRITE Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 5 ----- configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + drivers/mtd/nand/raw/Kconfig | 4 ++++ include/configs/ti_armv7_keystone2.h | 1 - 9 files changed, 10 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/README b/README index 4309d933866..f24decf5e43 100644 --- a/README +++ b/README @@ -1806,11 +1806,6 @@ Low Level (hardware related) configuration options: If defined, the x86 reset vector code is included. This is not needed when U-Boot is running from Coreboot. -- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE - Option to disable subpage write in NAND driver - driver that uses this: - drivers/mtd/nand/raw/davinci_nand.c - Freescale QE/FMAN Firmware Support: ----------------------------------- diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 977348e73fc..25007793b3a 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -78,6 +78,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index afba285ffb2..6c8a284e7c7 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 6c4563912b5..fec29f2c911 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -78,6 +78,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 33624badae0..f6ac484f2e8 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index e28054bcc72..bb91aa3534a 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -78,6 +78,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 8f8bb549130..d10965a70fc 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 0e428418b25..3585031ddfa 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -41,6 +41,10 @@ config SYS_NAND_USE_FLASH_BBT help Enable the BBT (Bad Block Table) usage. +config SYS_NAND_NO_SUBPAGE_WRITE + bool "Disable subpage write support" + depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD + config NAND_ATMEL bool "Support Atmel NAND controller" select SYS_NAND_SELF_INIT diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 6c01ab813e5..b8b4b28b3d6 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -68,7 +68,6 @@ #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } -#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE #define DFU_ALT_INFO_MMC \ "dfu_alt_info_mmc=" \ -- cgit v1.3.1 From a9f03760c1b85cda153723c5dc5d7ad0a64a5acc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:49 -0500 Subject: Convert CONFIG_SYS_NAND_PAGE_2K et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_NAND_PAGE_2K CONFIG_SYS_NAND_PAGE_4K Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + drivers/mtd/nand/raw/Kconfig | 13 +++++++++++++ include/configs/da850evm.h | 1 - include/configs/k2e_evm.h | 3 --- include/configs/k2g_evm.h | 3 --- include/configs/k2hk_evm.h | 3 --- include/configs/k2l_evm.h | 3 --- include/configs/omapl138_lcdk.h | 1 - 9 files changed, 15 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index bb91aa3534a..13d612ac3fb 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -80,6 +80,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y +CONFIG_SYS_NAND_PAGE_4K=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index d10965a70fc..59ec3a6346f 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -58,6 +58,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y +CONFIG_SYS_NAND_PAGE_4K=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 3585031ddfa..5483efeb39b 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -168,6 +168,19 @@ config SYS_NAND_SOFT_ECC endchoice +choice + prompt "NAND page size" + depends on NAND_DAVINCI + default SYS_NAND_PAGE_2K + +config SYS_NAND_PAGE_2K + bool "Page size is 2K" + +config SYS_NAND_PAGE_4K + bool "Page size is 4K" + +endchoice + config KEYSTONE_RBL_NAND depends on ARCH_KEYSTONE def_bool y diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 11f104bcb86..5a5c65da16c 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -107,7 +107,6 @@ * Flash & Environment */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_PAGE_2K #define CONFIG_SYS_NAND_CS 3 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE #define CONFIG_SYS_NAND_MASK_CLE 0x10 diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 9b25c349822..bbc58be511e 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -36,9 +36,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 9 diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index 887fda90d6a..bb91751d5d9 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -50,9 +50,6 @@ "get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\ "name_fs=arago-base-tisdk-image-k2g-evm.cpio\0" -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 2 diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index cfc34c7da6d..68cbe98b553 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -36,9 +36,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - /* Network */ #define CONFIG_KSNET_NETCP_V1_0 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 65988fff06e..a18158a7eb3 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -36,9 +36,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_4K - /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 233e7b4ee53..d9f70c75323 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -105,7 +105,6 @@ * Flash & Environment */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_PAGE_2K #define CONFIG_SYS_NAND_CS 3 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE #define CONFIG_SYS_NAND_MASK_CLE 0x10 -- cgit v1.3.1 From 0cd03259644dcb967fcd6b31c3a92984125a1fe3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:50 -0500 Subject: Convert CONFIG_SYS_NAND_SIZE to Kconfig This converts the following to Kconfig: CONFIG_SYS_NAND_SIZE Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- drivers/mtd/nand/raw/Kconfig | 5 +++++ include/configs/M5329EVB.h | 1 - include/configs/M5373EVB.h | 1 - include/configs/m53menlo.h | 6 ------ include/configs/smartweb.h | 1 - include/configs/taurus.h | 1 - 6 files changed, 5 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 5483efeb39b..eb37b627599 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -461,6 +461,11 @@ config NAND_MXC This enables the NAND driver for the NAND flash controller on the i.MX27 / i.MX31 / i.MX5 processors. +config SYS_NAND_SIZE + int "Size of NAND in kilobytes" + depends on NAND_MXC && SPL_NAND_SUPPORT + default 268435456 + config NAND_MXS bool "MXS NAND support" depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 47ea51c5072..a39fe5f28a8 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -94,7 +94,6 @@ #ifdef CONFIG_CMD_NAND # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE -# define CONFIG_SYS_NAND_SIZE 1 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 #endif diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index a2e36cc8673..f0734712eaa 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -95,7 +95,6 @@ #endif # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE -# define CONFIG_SYS_NAND_SIZE 1 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index a20b41bdf07..36522419172 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -85,12 +85,6 @@ /* Watchdog */ -/* - * NAND SPL - */ - -#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) - /* * Extra Environments */ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 538aad9a7bb..5460c12a17e 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -96,7 +96,6 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_SIZE (SZ_256M) #define CONFIG_SYS_NAND_ECCSIZE 256 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 5ab087da8bd..f130c630dde 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -130,7 +130,6 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M) #define CONFIG_SYS_NAND_ECCSIZE 256 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ -- cgit v1.3.1 From 4e5909450ec2acafb3d2e5b9714251ae67e0f0e0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:51 -0500 Subject: global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 10 ++-- arch/arm/include/asm/arch-lpc32xx/config.h | 8 +-- arch/arm/include/asm/ti-common/davinci_nand.h | 8 +-- arch/arm/mach-kirkwood/include/mach/config.h | 2 +- arch/arm/mach-omap2/mem-common.c | 2 +- arch/powerpc/cpu/mpc83xx/elbc/elbc.h | 20 +++---- arch/powerpc/cpu/mpc83xx/spl_minimal.c | 10 ++-- board/atmel/at91sam9260ek/at91sam9260ek.c | 4 +- board/atmel/at91sam9261ek/at91sam9261ek.c | 4 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 4 +- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 4 +- board/atmel/at91sam9rlek/at91sam9rlek.c | 4 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 4 +- board/atmel/sam9x60ek/sam9x60ek.c | 4 +- board/bluewater/gurnard/gurnard.c | 8 +-- board/calao/usb_a9263/usb_a9263.c | 8 +-- board/egnite/ethernut5/ethernut5.c | 6 +- board/esd/meesc/meesc.c | 4 +- board/freescale/common/p_corenet/law.c | 4 +- board/freescale/common/p_corenet/tlb.c | 4 +- board/freescale/ls1043aqds/ls1043aqds.c | 32 +++++----- board/freescale/ls1043ardb/ls1043ardb.c | 34 +++++------ board/freescale/ls1046aqds/ls1046aqds.c | 32 +++++----- board/freescale/ls1088a/ls1088a.c | 32 +++++----- board/freescale/p1010rdb/law.c | 2 +- board/freescale/p1010rdb/spl_minimal.c | 6 +- board/freescale/p1010rdb/tlb.c | 2 +- board/freescale/p1_p2_rdb_pc/law.c | 4 +- board/freescale/p1_p2_rdb_pc/spl_minimal.c | 6 +- board/freescale/p1_p2_rdb_pc/tlb.c | 4 +- board/freescale/t102xrdb/law.c | 4 +- board/freescale/t102xrdb/tlb.c | 4 +- board/freescale/t104xrdb/law.c | 4 +- board/freescale/t104xrdb/tlb.c | 4 +- board/freescale/t208xqds/law.c | 4 +- board/freescale/t208xqds/tlb.c | 4 +- board/freescale/t208xrdb/law.c | 4 +- board/freescale/t208xrdb/tlb.c | 4 +- board/freescale/t4rdb/law.c | 4 +- board/freescale/t4rdb/tlb.c | 4 +- board/gardena/smart-gateway-at91sam/spl.c | 4 +- board/keymile/kmcent2/law.c | 2 +- board/keymile/kmcent2/tlb.c | 2 +- board/ronetix/pm9261/pm9261.c | 4 +- board/ronetix/pm9263/pm9263.c | 4 +- board/ronetix/pm9g45/pm9g45.c | 6 +- board/siemens/corvus/board.c | 8 +-- board/siemens/smartweb/smartweb.c | 8 +-- board/siemens/taurus/taurus.c | 10 ++-- board/socrates/nand.c | 2 +- common/spl/spl_nand.c | 8 +-- doc/README.arm-relocation | 8 +-- doc/README.omap3 | 6 +- doc/board/ti/am335x_evm.rst | 2 +- drivers/mtd/nand/raw/am335x_spl_bch.c | 12 ++-- drivers/mtd/nand/raw/atmel_nand.c | 40 ++++++------- drivers/mtd/nand/raw/davinci_nand.c | 14 ++--- drivers/mtd/nand/raw/denali_spl.c | 4 +- drivers/mtd/nand/raw/fsl_elbc_nand.c | 6 +- drivers/mtd/nand/raw/fsl_elbc_spl.c | 12 ++-- drivers/mtd/nand/raw/fsl_ifc_nand.c | 6 +- drivers/mtd/nand/raw/fsl_ifc_spl.c | 20 +++---- drivers/mtd/nand/raw/fsmc_nand.c | 2 +- drivers/mtd/nand/raw/kmeter1_nand.c | 4 +- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 22 +++---- drivers/mtd/nand/raw/mxc_nand.c | 6 +- drivers/mtd/nand/raw/mxc_nand_spl.c | 8 +-- drivers/mtd/nand/raw/nand.c | 6 +- drivers/mtd/nand/raw/nand_spl_load.c | 6 +- drivers/mtd/nand/raw/nand_spl_simple.c | 16 ++--- drivers/mtd/nand/raw/omap_gpmc.c | 2 +- drivers/mtd/nand/raw/vf610_nfc.c | 2 +- include/configs/M5329EVB.h | 4 +- include/configs/M5373EVB.h | 4 +- include/configs/MCR3000.h | 2 +- include/configs/MPC837XERDB.h | 2 +- include/configs/P1010RDB.h | 78 ++++++++++++------------- include/configs/P2041RDB.h | 12 ++-- include/configs/T102xRDB.h | 64 ++++++++++---------- include/configs/T104xRDB.h | 62 ++++++++++---------- include/configs/T208xQDS.h | 60 +++++++++---------- include/configs/T208xRDB.h | 60 +++++++++---------- include/configs/T4240RDB.h | 54 ++++++++--------- include/configs/am335x_evm.h | 6 +- include/configs/am335x_guardian.h | 6 +- include/configs/am335x_igep003x.h | 6 +- include/configs/am3517_evm.h | 8 +-- include/configs/am43xx_evm.h | 6 +- include/configs/at91sam9260ek.h | 10 ++-- include/configs/at91sam9261ek.h | 10 ++-- include/configs/at91sam9263ek.h | 10 ++-- include/configs/at91sam9m10g45ek.h | 18 +++--- include/configs/at91sam9n12ek.h | 10 ++-- include/configs/at91sam9rlek.h | 10 ++-- include/configs/at91sam9x5ek.h | 10 ++-- include/configs/baltos.h | 8 +-- include/configs/chiliboard.h | 6 +- include/configs/cm_fx6.h | 2 +- include/configs/cm_t43.h | 6 +- include/configs/colibri-imx6ull.h | 4 +- include/configs/colibri_imx7.h | 2 +- include/configs/corvus.h | 22 +++---- include/configs/da850evm.h | 20 +++---- include/configs/devkit3250.h | 10 ++-- include/configs/devkit8000.h | 8 +-- include/configs/dra7xx_evm.h | 6 +- include/configs/etamin.h | 18 +++--- include/configs/ethernut5.h | 8 +-- include/configs/gardena-smart-gateway-at91sam.h | 16 ++--- include/configs/imx27lite-common.h | 2 +- include/configs/imx6-engicam.h | 4 +- include/configs/imx6_logic.h | 4 +- include/configs/imx6ulz_smm_m2.h | 2 +- include/configs/imx8mn_bsh_smm_s2.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/km/km-mpc83xx.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 42 ++++++------- include/configs/kmcent2.h | 38 ++++++------ include/configs/kmcoge5ne.h | 2 +- include/configs/ls1021aqds.h | 60 +++++++++---------- include/configs/ls1043a_common.h | 4 +- include/configs/ls1043aqds.h | 72 +++++++++++------------ include/configs/ls1043ardb.h | 72 +++++++++++------------ include/configs/ls1046a_common.h | 4 +- include/configs/ls1046afrwy.h | 38 ++++++------ include/configs/ls1046aqds.h | 72 +++++++++++------------ include/configs/ls1046ardb.h | 38 ++++++------ include/configs/ls1088a_common.h | 4 +- include/configs/ls1088aqds.h | 66 ++++++++++----------- include/configs/ls1088ardb.h | 34 +++++------ include/configs/ls2080a_common.h | 8 +-- include/configs/ls2080aqds.h | 54 ++++++++--------- include/configs/ls2080ardb.h | 54 ++++++++--------- include/configs/m53menlo.h | 4 +- include/configs/meesc.h | 10 ++-- include/configs/mx6sabreauto.h | 2 +- include/configs/mx6sxsabreauto.h | 2 +- include/configs/mx7dsabresd.h | 2 +- include/configs/mxs.h | 2 +- include/configs/mys_6ulx.h | 2 +- include/configs/npi_imx6ull.h | 2 +- include/configs/omap3_beagle.h | 6 +- include/configs/omap3_evm.h | 6 +- include/configs/omap3_igep00x0.h | 6 +- include/configs/omap3_logic.h | 6 +- include/configs/omapl138_lcdk.h | 20 +++---- include/configs/p1_p2_rdb_pc.h | 26 ++++----- include/configs/pcl063.h | 2 +- include/configs/pcl063_ull.h | 2 +- include/configs/phycore_am335x_r2.h | 6 +- include/configs/pm9261.h | 10 ++-- include/configs/pm9263.h | 10 ++-- include/configs/pm9g45.h | 18 +++--- include/configs/presidio_asic.h | 4 +- include/configs/sam9x60ek.h | 10 ++-- include/configs/sama5d2_ptc_ek.h | 6 +- include/configs/sama5d3_xplained.h | 6 +- include/configs/sama5d3xek.h | 6 +- include/configs/sama5d4_xplained.h | 6 +- include/configs/sama5d4ek.h | 6 +- include/configs/siemens-am33x-common.h | 10 ++-- include/configs/smartweb.h | 22 +++---- include/configs/snapper9g45.h | 10 ++-- include/configs/socfpga_common.h | 4 +- include/configs/socrates.h | 2 +- include/configs/taurus.h | 22 +++---- include/configs/ti816x_evm.h | 8 +-- include/configs/ti_armv7_common.h | 2 +- include/configs/ti_armv7_keystone2.h | 10 ++-- include/configs/ti_armv7_omap.h | 4 +- include/configs/ti_omap3_common.h | 2 +- include/configs/uniphier.h | 4 +- include/configs/usb_a9263.h | 10 ++-- include/configs/vf610twr.h | 2 +- include/configs/work_92105.h | 6 +- 175 files changed, 1106 insertions(+), 1106 deletions(-) (limited to 'include') diff --git a/README b/README index f24decf5e43..f5407576276 100644 --- a/README +++ b/README @@ -1364,18 +1364,18 @@ The following options need to be configured: CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT, CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS, - CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE, - CONFIG_SYS_NAND_ECCBYTES + CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE, + CFG_SYS_NAND_ECCBYTES Defines the size and behavior of the NAND that SPL uses to read U-Boot - CONFIG_SYS_NAND_U_BOOT_DST + CFG_SYS_NAND_U_BOOT_DST Location in memory to load U-Boot to - CONFIG_SYS_NAND_U_BOOT_SIZE + CFG_SYS_NAND_U_BOOT_SIZE Size of image to load - CONFIG_SYS_NAND_U_BOOT_START + CFG_SYS_NAND_U_BOOT_START Entry point in loaded image to jump to CONFIG_SPL_RAM_DEVICE diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index dc414c7d845..5dd90b47f93 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -32,17 +32,17 @@ #define NAND_SMALL_BLOCK_PAGE_SIZE 0x200 #if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ +#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } #elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } +#define CFG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } #else #error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" #endif -#define CONFIG_SYS_NAND_ECCSIZE 0x100 -#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCSIZE 0x100 +#define CFG_SYS_NAND_ECCBYTES 3 #endif /* CONFIG_NAND_LPC32XX_SLC */ /* NOR Flash */ diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h index a4cc27e920d..38a1a6ea0d7 100644 --- a/arch/arm/include/asm/ti-common/davinci_nand.h +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -18,13 +18,13 @@ #define MASK_CLE 0x10 #define MASK_ALE 0x08 -#ifdef CONFIG_SYS_NAND_MASK_CLE +#ifdef CFG_SYS_NAND_MASK_CLE #undef MASK_CLE -#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE +#define MASK_CLE CFG_SYS_NAND_MASK_CLE #endif -#ifdef CONFIG_SYS_NAND_MASK_ALE +#ifdef CFG_SYS_NAND_MASK_ALE #undef MASK_ALE -#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE +#define MASK_ALE CFG_SYS_NAND_MASK_ALE #endif struct davinci_emif_regs { diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index d877be119fc..ae1f6fee531 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -35,7 +35,7 @@ */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ +#define CFG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ #define NAND_ALLOW_ERASE_ALL 1 #endif diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c index 2dcf0cf9c37..803dc7fb71d 100644 --- a/arch/arm/mach-omap2/mem-common.c +++ b/arch/arm/mach-omap2/mem-common.c @@ -135,7 +135,7 @@ void set_gpmc_cs0(int flash_type) #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND) case MTD_DEV_TYPE_NAND: gpmc_regs = gpmc_regs_nand; - base = CONFIG_SYS_NAND_BASE; + base = CFG_SYS_NAND_BASE; size = GPMC_SIZE_16M; break; #endif diff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h index e795cd10cb9..b0b9a1e99e2 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h +++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h @@ -1,16 +1,16 @@ #if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM #endif diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index d8f6cfe2b4a..8fcf20854ed 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -71,16 +71,16 @@ void cpu_init_f (volatile immap_t * im) * has been determined */ -#if defined(CONFIG_SYS_NAND_BR_PRELIM) \ - && defined(CONFIG_SYS_NAND_OR_PRELIM) \ +#if defined(CFG_SYS_NAND_BR_PRELIM) \ + && defined(CFG_SYS_NAND_OR_PRELIM) \ && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \ && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); + set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM); im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; #else -#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined +#error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined #endif } diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index a9ea9b558a9..d2c6ada6683 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -56,10 +56,10 @@ static void at91sam9260ek_nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 0c53325ba71..2992353199f 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -78,10 +78,10 @@ static void at91sam9261ek_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOC); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 3e232aa87fb..b2b70930805 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -69,10 +69,10 @@ static void at91sam9263ek_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOCDE); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 3af70971f34..2f3a772b81f 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -63,10 +63,10 @@ void at91sam9m10g45ek_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOC); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index f05ee322d09..bca7c8d9af5 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -64,10 +64,10 @@ static void at91sam9rlek_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOD); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */ at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */ diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index b5af35bc7e5..817aa2fef70 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -65,9 +65,9 @@ static void at91sam9x5ek_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOCD); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 7035fab8788..786de18f8c6 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -36,9 +36,9 @@ static void sam9x60ek_nand_hw_init(void) at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */ at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */ /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c index f547ce3cc21..35c74ba9dd2 100644 --- a/board/bluewater/gurnard/gurnard.c +++ b/board/bluewater/gurnard/gurnard.c @@ -100,16 +100,16 @@ static int gurnard_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); - ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy"); + ret = gpio_request(CFG_SYS_NAND_READY_PIN, "nand_rdy"); if (ret) return ret; - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + gpio_direction_input(CFG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce"); + ret = gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand_ce"); if (ret) return ret; - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); return 0; } diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c index c0a5c518ca8..c89ad0bfe3d 100644 --- a/board/calao/usb_a9263/usb_a9263.c +++ b/board/calao/usb_a9263/usb_a9263.c @@ -54,12 +54,12 @@ static void usb_a9263_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOCDE); /* Configure RDY/BSY */ - gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy"); - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + gpio_request(CFG_SYS_NAND_READY_PIN, "NAND ready/busy"); + gpio_direction_input(CFG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable"); - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_request(CFG_SYS_NAND_ENABLE_PIN, "NAND enable"); + gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index 559fdd2f646..a5d79d8e3e1 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -117,11 +117,11 @@ static void ethernut5_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); -#ifdef CONFIG_SYS_NAND_READY_PIN +#ifdef CFG_SYS_NAND_READY_PIN /* Ready pin is optional. */ - at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_pio_input(CFG_SYS_NAND_READY_PIN, 1); #endif - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index a3eee63e375..98043b020c5 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -84,10 +84,10 @@ static void meesc_nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + gpio_direction_input(CFG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif /* CONFIG_CMD_NAND */ diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 603384ac4f9..8951fae32d3 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -28,8 +28,8 @@ struct law_entry law_table[] = { /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif }; diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index c0ab1a5fd14..ef46353a367 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -135,13 +135,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_4M, 1), #endif -#ifdef CONFIG_SYS_NAND_BASE +#ifdef CFG_SYS_NAND_BASE /* * *I*G - NAND * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for nand. */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_1M, 1), #endif diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index b02f649910f..481d3a5d9bd 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -84,15 +84,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { @@ -113,15 +113,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 799900e9c94..7f321281988 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -47,15 +47,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { @@ -76,15 +76,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { @@ -355,7 +355,7 @@ void nand_fixup(void) return; /* Change NAND Flash PGS/SPRZ configuration */ - csor = CONFIG_SYS_NAND_CSOR; + csor = CFG_SYS_NAND_CSOR; if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K; diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index dfdc9f06ab1..de6828673b5 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -68,15 +68,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { @@ -97,15 +97,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index ae81740dc36..b70c198188b 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -73,15 +73,15 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { @@ -105,15 +105,15 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c index debf571482b..2dcee79b3ae 100644 --- a/board/freescale/p1010rdb/law.c +++ b/board/freescale/p1010rdb/law.c @@ -10,7 +10,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index a262d5ca4af..9cd46c96641 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -22,9 +22,9 @@ void board_init_f(ulong bootflag) u32 plat_ratio; ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; -#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM); #endif /* initialize selected port with appropriate baud rate */ diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 7992666e930..aa7517a74d8 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -68,7 +68,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 6bdfb356eed..8f3f4840e60 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -13,8 +13,8 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), #endif }; diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index e467c7adc19..2fd8a287433 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -21,9 +21,9 @@ void board_init_f(ulong bootflag) u32 plat_ratio; ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; -#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM); #endif /* initialize selected port with appropriate baud rate */ diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 65cedd42a0d..85d41327aa2 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -67,9 +67,9 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#ifdef CONFIG_SYS_NAND_BASE +#ifdef CFG_SYS_NAND_BASE /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), #endif diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c index 04a4239797c..850ece0110e 100644 --- a/board/freescale/t102xrdb/law.c +++ b/board/freescale/t102xrdb/law.c @@ -23,8 +23,8 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), #endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), #endif }; diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c index 97080eb95e5..8fdff7576fe 100644 --- a/board/freescale/t102xrdb/tlb.c +++ b/board/freescale/t102xrdb/tlb.c @@ -88,8 +88,8 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_4M, 1), #endif -#ifdef CONFIG_SYS_NAND_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, +#ifdef CFG_SYS_NAND_BASE + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), #endif diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c index 0f6b71a8c22..2f00d801069 100644 --- a/board/freescale/t104xrdb/law.c +++ b/board/freescale/t104xrdb/law.c @@ -23,8 +23,8 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), #endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), #endif }; diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 9dcba7933ff..8a3d67449c2 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -101,13 +101,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_4M, 1), #endif -#ifdef CONFIG_SYS_NAND_BASE +#ifdef CFG_SYS_NAND_BASE /* * *I*G - NAND * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for nand. */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), #endif diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c index 40fdcf61c05..f97467e8445 100644 --- a/board/freescale/t208xqds/law.c +++ b/board/freescale/t208xqds/law.c @@ -25,8 +25,8 @@ struct law_entry law_table[] = { /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), #endif }; diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index 1e501da363d..f27faf5d243 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -116,13 +116,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif -#ifdef CONFIG_SYS_NAND_BASE +#ifdef CFG_SYS_NAND_BASE /* * *I*G - NAND * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for nand. */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c index d3b263f59d9..3ff4c773d59 100644 --- a/board/freescale/t208xrdb/law.c +++ b/board/freescale/t208xrdb/law.c @@ -25,8 +25,8 @@ struct law_entry law_table[] = { /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), #endif }; diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index 542ab1e034f..da03aadb173 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -116,13 +116,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif -#ifdef CONFIG_SYS_NAND_BASE +#ifdef CFG_SYS_NAND_BASE /* * *I*G - NAND * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for nand. */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c index 038f60565f7..438589604f1 100644 --- a/board/freescale/t4rdb/law.c +++ b/board/freescale/t4rdb/law.c @@ -22,8 +22,8 @@ struct law_entry law_table[] = { /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), #endif }; diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index b927dd8484f..059449af1ed 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -98,13 +98,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif -#ifdef CONFIG_SYS_NAND_BASE +#ifdef CFG_SYS_NAND_BASE /* * *I*G - NAND * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for nand. */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif diff --git a/board/gardena/smart-gateway-at91sam/spl.c b/board/gardena/smart-gateway-at91sam/spl.c index 3ab6760df73..2807c4e3114 100644 --- a/board/gardena/smart-gateway-at91sam/spl.c +++ b/board/gardena/smart-gateway-at91sam/spl.c @@ -53,10 +53,10 @@ static void at91sam9x5ek_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOCD); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ diff --git a/board/keymile/kmcent2/law.c b/board/keymile/kmcent2/law.c index aa0f29f44fc..b04a8e20dce 100644 --- a/board/keymile/kmcent2/law.c +++ b/board/keymile/kmcent2/law.c @@ -14,7 +14,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC), /* other application LAW are not used in u-boot */ diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c index dbd3b9b064c..095fc7e9614 100644 --- a/board/keymile/kmcent2/tlb.c +++ b/board/keymile/kmcent2/tlb.c @@ -76,7 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 9, BOOKE_PAGESZ_4M, 1), /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), /* QRIO */ diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index fe52c7c1764..07febe69dc7 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -66,10 +66,10 @@ static void pm9261_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOC); /* Configure RDY/BSY */ - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + gpio_direction_input(CFG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */ diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 84926cdc689..76f62ddde91 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -62,10 +62,10 @@ static void pm9263_nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + gpio_direction_input(CFG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 8d5825c7f13..23b55e3e030 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -65,13 +65,13 @@ static void pm9g45_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOC); -#ifdef CONFIG_SYS_NAND_READY_PIN +#ifdef CFG_SYS_NAND_READY_PIN /* Configure RDY/BSY */ - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + gpio_direction_input(CFG_SYS_NAND_READY_PIN); #endif /* Enable NandFlash */ - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index 90fece7f958..d87628097d0 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -40,8 +40,8 @@ DECLARE_GLOBAL_DATA_PTR; static void corvus_request_gpio(void) { - gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena"); - gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy"); + gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena"); + gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy"); gpio_request(AT91_PIN_PD7, "d0"); gpio_request(AT91_PIN_PD8, "d1"); gpio_request(AT91_PIN_PA12, "d2"); @@ -110,8 +110,8 @@ static void corvus_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOA); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); } #if defined(CONFIG_SPL_BUILD) diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index d500a6214d5..ce6c877959a 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -42,8 +42,8 @@ DECLARE_GLOBAL_DATA_PTR; static void smartweb_request_gpio(void) { - gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena"); - gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy"); + gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena"); + gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy"); gpio_request(AT91_PIN_PA26, "ena PHY"); } @@ -72,10 +72,10 @@ static void smartweb_nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); } static void smartweb_macb_hw_init(void) diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 6c44afb4487..47d3f6aef22 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR; static void taurus_request_gpio(void) { - gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena"); - gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy"); + gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena"); + gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy"); gpio_request(AT91_PIN_PA25, "ena PHY"); } @@ -73,10 +73,10 @@ static void taurus_nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #if defined(CONFIG_SPL_BUILD) @@ -149,7 +149,7 @@ void spl_board_init(void) } else { puts("erase spi flash sector 0\n"); spi_flash_erase(flash, 0, - CONFIG_SYS_NAND_U_BOOT_SIZE); + CFG_SYS_NAND_U_BOOT_SIZE); } } } diff --git a/board/socrates/nand.c b/board/socrates/nand.c index 9b7ffee83a4..b1e38c511e5 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -6,7 +6,7 @@ #include -#if defined(CONFIG_SYS_NAND_BASE) +#if defined(CFG_SYS_NAND_BASE) #include #include #include diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 25a38be65ed..dc45204fc0e 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -26,12 +26,12 @@ static int spl_nand_load_image(struct spl_image_info *spl_image, nand_init(); printf("Loading U-Boot from 0x%08x (size 0x%08x) to 0x%08x\n", - CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, - CONFIG_SYS_NAND_U_BOOT_DST); + CONFIG_SYS_NAND_U_BOOT_OFFS, CFG_SYS_NAND_U_BOOT_SIZE, + CFG_SYS_NAND_U_BOOT_DST); nand_spl_load_image(spl_nand_get_uboot_raw_page(), - CONFIG_SYS_NAND_U_BOOT_SIZE, - (void *)CONFIG_SYS_NAND_U_BOOT_DST); + CFG_SYS_NAND_U_BOOT_SIZE, + (void *)CFG_SYS_NAND_U_BOOT_DST); spl_set_header_raw_uboot(spl_image); nand_deselect(); diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation index 6bb4e178474..69882a76a36 100644 --- a/doc/README.arm-relocation +++ b/doc/README.arm-relocation @@ -53,8 +53,8 @@ c) end executes this code d) this initialize CPU, RAM, ... and copy itself to RAM (this bin must fit in one page, so board_init_f() don;t fit in it ... ) -e) there it copy u-boot to CONFIG_SYS_NAND_U_BOOT_DST and - starts this image @ CONFIG_SYS_NAND_U_BOOT_START +e) there it copy u-boot to CFG_SYS_NAND_U_BOOT_DST and + starts this image @ CFG_SYS_NAND_U_BOOT_START f) u-boot code steps through board_init_f() and calculates the relocation address and copy itself to it @@ -86,8 +86,8 @@ Relocation with SPL (example for the tx25 booting from NAND Flash): - The First page contains u-boot code from drivers/mtd/nand/raw/mxc_nand_spl.c which inits the dram, cpu registers, reloacte itself to CONFIG_SPL_TEXT_BASE and loads - the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution - @CONFIG_SYS_NAND_U_BOOT_START + the "real" u-boot to CFG_SYS_NAND_U_BOOT_DST and starts execution + @CFG_SYS_NAND_U_BOOT_START - This u-boot does no RAM init, nor CPU register setup. Just look where it has to copy and relocate itself to this address. If diff --git a/doc/README.omap3 b/doc/README.omap3 index 208714ad658..3a1ac8101d6 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -146,11 +146,11 @@ implementation for OMAP3 works for you so the u-boot version should also. When you require the SPL to read with BCH8 there are two more configs to change: - * CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in + * CFG_SYS_NAND_ECCPOS (must be the same as .eccpos in GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in arch/arm/include/asm/arch-omap3/omap_gpmc.h) - * CONFIG_SYS_NAND_ECCSIZE must be 512 - * CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup + * CFG_SYS_NAND_ECCSIZE must be 512 + * CFG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup Acknowledgements ================ diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst index a90f32da7ae..0b230cf7c75 100644 --- a/doc/board/ti/am335x_evm.rst +++ b/doc/board/ti/am335x_evm.rst @@ -54,7 +54,7 @@ Step-1: Building u-boot for NAND boot CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block - CONFIG_SYS_NAND_ECCPOS ECC map for NAND page + CFG_SYS_NAND_ECCPOS ECC map for NAND page CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand) Step-2: Flashing NAND via MMC/SD diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c index 83590a63cca..6ab3f1f42c5 100644 --- a/drivers/mtd/nand/raw/am335x_spl_bch.c +++ b/drivers/mtd/nand/raw/am335x_spl_bch.c @@ -16,13 +16,13 @@ #include #include -static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; +static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS; static struct mtd_info *mtd; static struct nand_chip nand_chip; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ - CONFIG_SYS_NAND_ECCSIZE) -#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES) + CFG_SYS_NAND_ECCSIZE) +#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES) /* @@ -155,8 +155,8 @@ static int nand_read_page(int block, int page, void *dst) u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; int i; - int eccsize = CONFIG_SYS_NAND_ECCSIZE; - int eccbytes = CONFIG_SYS_NAND_ECCBYTES; + int eccsize = CFG_SYS_NAND_ECCSIZE; + int eccbytes = CFG_SYS_NAND_ECCBYTES; int eccsteps = ECCSTEPS; uint8_t *p = dst; uint32_t data_pos = 0; @@ -207,7 +207,7 @@ void nand_init(void) */ mtd = nand_to_mtd(&nand_chip); nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = - (void __iomem *)CONFIG_SYS_NAND_BASE; + (void __iomem *)CFG_SYS_NAND_BASE; board_nand_init(&nand_chip); if (nand_chip.select_chip) diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index a541af6db4a..9fbb0b57cf1 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -1227,16 +1227,16 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd, if (ctrl & NAND_CTRL_CHANGE) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE - | CONFIG_SYS_NAND_MASK_CLE); + IO_ADDR_W &= ~(CFG_SYS_NAND_MASK_ALE + | CFG_SYS_NAND_MASK_CLE); if (ctrl & NAND_CLE) - IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE; + IO_ADDR_W |= CFG_SYS_NAND_MASK_CLE; if (ctrl & NAND_ALE) - IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE; + IO_ADDR_W |= CFG_SYS_NAND_MASK_ALE; -#ifdef CONFIG_SYS_NAND_ENABLE_PIN - at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN, +#ifdef CFG_SYS_NAND_ENABLE_PIN + at91_set_gpio_value(CFG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE)); #endif this->IO_ADDR_W = (void *) IO_ADDR_W; @@ -1246,10 +1246,10 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd, writeb(cmd, this->IO_ADDR_W); } -#ifdef CONFIG_SYS_NAND_READY_PIN +#ifdef CFG_SYS_NAND_READY_PIN static int at91_nand_ready(struct mtd_info *mtd) { - return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN); + return at91_get_gpio_value(CFG_SYS_NAND_READY_PIN); } #endif @@ -1314,10 +1314,10 @@ static int nand_is_bad_block(int block) } #ifdef CONFIG_SPL_NAND_ECC -static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; +static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ - CONFIG_SYS_NAND_ECCSIZE) -#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES) + CFG_SYS_NAND_ECCSIZE) +#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES) static int nand_read_page(int block, int page, void *dst) { @@ -1325,8 +1325,8 @@ static int nand_read_page(int block, int page, void *dst) u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; - int eccsize = CONFIG_SYS_NAND_ECCSIZE; - int eccbytes = CONFIG_SYS_NAND_ECCBYTES; + int eccsize = CFG_SYS_NAND_ECCSIZE; + int eccbytes = CFG_SYS_NAND_ECCBYTES; int eccsteps = ECCSTEPS; int i; uint8_t *p = dst; @@ -1415,7 +1415,7 @@ int board_nand_init(struct nand_chip *nand) nand->read_buf = nand_read_buf; #endif nand->cmd_ctrl = at91_nand_hwcontrol; -#ifdef CONFIG_SYS_NAND_READY_PIN +#ifdef CFG_SYS_NAND_READY_PIN nand->dev_ready = at91_nand_ready; #else nand->dev_ready = at91_nand_wait_ready; @@ -1439,8 +1439,8 @@ void nand_init(void) mtd = nand_to_mtd(&nand_chip); mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE; mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE; - nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE; - nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; + nand_chip.IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE; + nand_chip.IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE; board_nand_init(&nand_chip); #ifdef CONFIG_SPL_NAND_ECC @@ -1464,11 +1464,11 @@ void nand_deselect(void) #else -#ifndef CONFIG_SYS_NAND_BASE_LIST -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#ifndef CFG_SYS_NAND_BASE_LIST +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; -static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST; +static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST; int atmel_nand_chip_init(int devnum, ulong base_addr) { @@ -1487,7 +1487,7 @@ int atmel_nand_chip_init(int devnum, ulong base_addr) nand->options = NAND_BUSWIDTH_16; #endif nand->cmd_ctrl = at91_nand_hwcontrol; -#ifdef CONFIG_SYS_NAND_READY_PIN +#ifdef CFG_SYS_NAND_READY_PIN nand->dev_ready = at91_nand_ready; #endif nand->chip_delay = 75; diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index 54aed136388..e4e144bd7c8 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -170,7 +170,7 @@ static u_int32_t nand_davinci_readecc(struct mtd_info *mtd) u_int32_t ecc = 0; ecc = __raw_readl(&(davinci_emif_regs->nandfecc[ - CONFIG_SYS_NAND_CS - 2])); + CFG_SYS_NAND_CS - 2])); return ecc; } @@ -183,8 +183,8 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) nand_davinci_readecc(mtd); val = __raw_readl(&davinci_emif_regs->nandfcr); - val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); - val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_1BIT_ECC_START(CFG_SYS_NAND_CS); __raw_writel(val, &davinci_emif_regs->nandfcr); } @@ -486,8 +486,8 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) */ val = __raw_readl(&davinci_emif_regs->nandfcr); val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK; - val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); - val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CFG_SYS_NAND_CS); val |= DAVINCI_NANDFCR_4BIT_ECC_START; __raw_writel(val, &davinci_emif_regs->nandfcr); break; @@ -794,8 +794,8 @@ static int davinci_nand_probe(struct udevice *dev) struct mtd_info *mtd = nand_to_mtd(nand); int ret; - nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE; - nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; + nand->IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE; + nand->IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE; davinci_nand_init(nand); diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c index f72142817e7..690279c9976 100644 --- a/drivers/mtd/nand/raw/denali_spl.c +++ b/drivers/mtd/nand/raw/denali_spl.c @@ -25,9 +25,9 @@ #define BANK(x) ((x) << 24) static void __iomem *denali_flash_mem = - (void __iomem *)CONFIG_SYS_NAND_DATA_BASE; + (void __iomem *)CFG_SYS_NAND_DATA_BASE; static void __iomem *denali_flash_reg = - (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; + (void __iomem *)CFG_SYS_NAND_REGS_BASE; static const int flash_bank; static int page_size, oob_size, pages_per_block; diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index 4f0acd7c89b..7853c3f74e2 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -819,12 +819,12 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, struct udevice *dev) #ifndef CONFIG_NAND_FSL_ELBC_DT -#ifndef CONFIG_SYS_NAND_BASE_LIST -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#ifndef CFG_SYS_NAND_BASE_LIST +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] = - CONFIG_SYS_NAND_BASE_LIST; + CFG_SYS_NAND_BASE_LIST; void board_nand_init(void) { diff --git a/drivers/mtd/nand/raw/fsl_elbc_spl.c b/drivers/mtd/nand/raw/fsl_elbc_spl.c index e55b40f8f13..26aaab08e89 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_spl.c +++ b/drivers/mtd/nand/raw/fsl_elbc_spl.c @@ -46,8 +46,8 @@ static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) #endif { fsl_lbc_t *regs = LBC_BASE_ADDR; - uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; - const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS; + uchar *buf = (uchar *)CFG_SYS_NAND_BASE; + const int large = CFG_SYS_NAND_OR_PRELIM & OR_FCM_PGS; const int block_shift = large ? 17 : 14; const int block_size = 1 << block_shift; const int page_size = large ? 2048 : 512; @@ -143,8 +143,8 @@ void nand_boot(void) * Load U-Boot image from NAND into RAM */ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_U_BOOT_SIZE, - (void *)CONFIG_SYS_NAND_U_BOOT_DST); + CFG_SYS_NAND_U_BOOT_SIZE, + (void *)CFG_SYS_NAND_U_BOOT_DST); #ifdef CONFIG_NAND_ENV_DST nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, @@ -161,13 +161,13 @@ void nand_boot(void) * Clean d-cache and invalidate i-cache, to * make sure that no stale data is executed. */ - flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); + flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE); #endif puts("transfering control\n"); /* * Jump to U-Boot image */ - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + uboot = (void *)CFG_SYS_NAND_U_BOOT_START; (*uboot)(); } diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c index e5ff937872e..59de3256405 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_nand.c +++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c @@ -1053,12 +1053,12 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) return 0; } -#ifndef CONFIG_SYS_NAND_BASE_LIST -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#ifndef CFG_SYS_NAND_BASE_LIST +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] = - CONFIG_SYS_NAND_BASE_LIST; + CFG_SYS_NAND_BASE_LIST; void board_nand_init(void) { diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index 4d11922a650..7d4b77dd11d 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -110,7 +110,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) { struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR; struct fsl_ifc_runtime *ifc = NULL; - uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; + uchar *buf = (uchar *)CFG_SYS_NAND_BASE; int page_size; int port_size; int pages_per_blk; @@ -129,8 +129,8 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) ifc = runtime_regs_address(); /* Get NAND Flash configuration */ - csor = CONFIG_SYS_NAND_CSOR; - cspr = CONFIG_SYS_NAND_CSPR; + csor = CFG_SYS_NAND_CSOR; + cspr = CFG_SYS_NAND_CSPR; port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8; @@ -250,8 +250,8 @@ void nand_boot(void) * Load U-Boot image from NAND into RAM */ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_U_BOOT_SIZE, - (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); + CFG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CFG_SYS_NAND_U_BOOT_DST); #ifdef CONFIG_NAND_ENV_DST nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, @@ -270,7 +270,7 @@ void nand_boot(void) * Clean d-cache and invalidate i-cache, to * make sure that no stale data is executed. */ - flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); + flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE); #endif #ifdef CONFIG_CHAIN_OF_TRUST @@ -279,11 +279,11 @@ void nand_boot(void) * calculate U-boot header address using U-boot header size. */ #define CONFIG_U_BOOT_HDR_ADDR \ - ((CONFIG_SYS_NAND_U_BOOT_START + \ - CONFIG_SYS_NAND_U_BOOT_SIZE) - \ + ((CFG_SYS_NAND_U_BOOT_START + \ + CFG_SYS_NAND_U_BOOT_SIZE) - \ CONFIG_U_BOOT_HDR_SIZE) spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR, - CONFIG_SYS_NAND_U_BOOT_START); + CFG_SYS_NAND_U_BOOT_START); /* * In case of failure in validation, spl_validate_uboot would * not return back in case of Production environment with ITS=1. @@ -293,7 +293,7 @@ void nand_boot(void) */ #endif - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + uboot = (void *)CFG_SYS_NAND_U_BOOT_START; uboot(); } diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c index a92c6252a5d..d795864949c 100644 --- a/drivers/mtd/nand/raw/fsmc_nand.c +++ b/drivers/mtd/nand/raw/fsmc_nand.c @@ -427,7 +427,7 @@ int fsmc_nand_init(struct nand_chip *nand) nand->ecc.hwctl = fsmc_enable_hwecc; nand->cmd_ctrl = fsmc_nand_hwcontrol; nand->IO_ADDR_R = nand->IO_ADDR_W = - (void __iomem *)CONFIG_SYS_NAND_BASE; + (void __iomem *)CFG_SYS_NAND_BASE; nand->badblockbits = 7; mtd = nand_to_mtd(nand); diff --git a/drivers/mtd/nand/raw/kmeter1_nand.c b/drivers/mtd/nand/raw/kmeter1_nand.c index b838164bf2e..84564b2f70a 100644 --- a/drivers/mtd/nand/raw/kmeter1_nand.c +++ b/drivers/mtd/nand/raw/kmeter1_nand.c @@ -10,8 +10,8 @@ #include #include -#define CONFIG_NAND_MODE_REG (void *)(CONFIG_SYS_NAND_BASE + 0x20000) -#define CONFIG_NAND_DATA_REG (void *)(CONFIG_SYS_NAND_BASE + 0x30000) +#define CONFIG_NAND_MODE_REG (void *)(CFG_SYS_NAND_BASE + 0x20000) +#define CONFIG_NAND_DATA_REG (void *)(CFG_SYS_NAND_BASE + 0x30000) #define read_mode() in_8(CONFIG_NAND_MODE_REG) #define write_mode(val) out_8(CONFIG_NAND_MODE_REG, val) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index 3d6cb1dc635..f4f1b22f5e2 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -84,7 +84,7 @@ static struct nand_ecclayout lpc32xx_nand_oob_16 = { }; #if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) -#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) +#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CFG_SYS_NAND_ECCSIZE) /* * DMA Descriptors @@ -187,7 +187,7 @@ static void lpc32xx_nand_dma_configure(struct nand_chip *chip, DMAC_CHAN_DEST_AHB1; /* CTRL descriptor entry for reading/writing Data */ - ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) | + ctrl = (CFG_SYS_NAND_ECCSIZE / 4) | DMAC_CHAN_SRC_BURST_4 | DMAC_CHAN_DEST_BURST_4 | DMAC_CHAN_SRC_WIDTH_32 | @@ -241,7 +241,7 @@ static void lpc32xx_nand_dma_configure(struct nand_chip *chip, * 2. X'fer 64 bytes of Spare area from Flash to Memory. */ - for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) { + for (i = 0; i < size/CFG_SYS_NAND_ECCSIZE; i++) { dmalist_cur = &dmalist[i * 2]; dmalist_cur_ecc = &dmalist[(i * 2) + 1]; @@ -337,9 +337,9 @@ static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf, static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count) { int i; - for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES); - i += CONFIG_SYS_NAND_ECCBYTES) { - u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES]; + for (i = 0; i < (count * CFG_SYS_NAND_ECCBYTES); + i += CFG_SYS_NAND_ECCBYTES) { + u32 ce = ecc[i / CFG_SYS_NAND_ECCBYTES]; ce = ~(ce << 2) & 0xFFFFFF; spare[i+2] = (u8)(ce & 0xFF); ce >>= 8; spare[i+1] = (u8)(ce & 0xFF); ce >>= 8; @@ -386,9 +386,9 @@ int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat, u16 data_offset = 0; for (i = 0 ; i < ECCSTEPS ; i++) { - r += CONFIG_SYS_NAND_ECCBYTES; - c += CONFIG_SYS_NAND_ECCBYTES; - data_offset += CONFIG_SYS_NAND_ECCSIZE; + r += CFG_SYS_NAND_ECCBYTES; + c += CFG_SYS_NAND_ECCBYTES; + data_offset += CFG_SYS_NAND_ECCSIZE; ret1 = nand_correct_data(mtd, dat + data_offset, r, c); if (ret1 < 0) @@ -568,8 +568,8 @@ int board_nand_init(struct nand_chip *lpc32xx_chip) * These values are predefined * for both small and large page NAND flash devices. */ - lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE; - lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; + lpc32xx_chip->ecc.size = CFG_SYS_NAND_ECCSIZE; + lpc32xx_chip->ecc.bytes = CFG_SYS_NAND_ECCBYTES; lpc32xx_chip->ecc.strength = 1; if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE) diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index 2b8a132a5fc..fa903e324c5 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -50,7 +50,7 @@ static struct mxc_nand_host *host = &mxc_host; /* OOB placement block for use with hardware ecc generation */ #if defined(MXC_NFC_V1) -#ifndef CONFIG_SYS_NAND_LARGEPAGE +#ifndef CFG_SYS_NAND_LARGEPAGE static struct nand_ecclayout nand_hw_eccoob = { .eccbytes = 5, .eccpos = {6, 7, 8, 9, 10}, @@ -69,7 +69,7 @@ static struct nand_ecclayout nand_hw_eccoob2k = { }; #endif #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) -#ifndef CONFIG_SYS_NAND_LARGEPAGE +#ifndef CFG_SYS_NAND_LARGEPAGE static struct nand_ecclayout nand_hw_eccoob = { .eccbytes = 9, .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, @@ -1219,7 +1219,7 @@ int board_nand_init(struct nand_chip *this) if (is_16bit_nand()) this->options |= NAND_BUSWIDTH_16; -#ifdef CONFIG_SYS_NAND_LARGEPAGE +#ifdef CFG_SYS_NAND_LARGEPAGE host->pagesize_2k = 1; this->ecc.layout = &nand_hw_eccoob2k; #else diff --git a/drivers/mtd/nand/raw/mxc_nand_spl.c b/drivers/mtd/nand/raw/mxc_nand_spl.c index 0fea307ea46..309e75d01e5 100644 --- a/drivers/mtd/nand/raw/mxc_nand_spl.c +++ b/drivers/mtd/nand/raw/mxc_nand_spl.c @@ -332,14 +332,14 @@ __used void nand_boot(void) __attribute__((noreturn)) void (*uboot)(void); /* - * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must + * CONFIG_SYS_NAND_U_BOOT_OFFS and CFG_SYS_NAND_U_BOOT_SIZE must * be aligned to full pages */ if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_U_BOOT_SIZE, - (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) { + CFG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CFG_SYS_NAND_U_BOOT_DST)) { /* Copy from NAND successful, start U-Boot */ - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + uboot = (void *)CFG_SYS_NAND_U_BOOT_START; uboot(); } else { /* Unrecoverable error when copying from NAND */ diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c index 14bca12024b..eacd99c4e27 100644 --- a/drivers/mtd/nand/raw/nand.c +++ b/drivers/mtd/nand/raw/nand.c @@ -11,8 +11,8 @@ #include #include -#ifndef CONFIG_SYS_NAND_BASE_LIST -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#ifndef CFG_SYS_NAND_BASE_LIST +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif int nand_curr_device = -1; @@ -21,7 +21,7 @@ static struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE]; #if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT) static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; -static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST; +static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST; #endif static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8]; diff --git a/drivers/mtd/nand/raw/nand_spl_load.c b/drivers/mtd/nand/raw/nand_spl_load.c index ecd373e054b..7ac9bf4d120 100644 --- a/drivers/mtd/nand/raw/nand_spl_load.c +++ b/drivers/mtd/nand/raw/nand_spl_load.c @@ -20,8 +20,8 @@ void nand_boot(void) * Load U-Boot image from NAND into RAM */ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_U_BOOT_SIZE, - (void *)CONFIG_SYS_NAND_U_BOOT_DST); + CFG_SYS_NAND_U_BOOT_SIZE, + (void *)CFG_SYS_NAND_U_BOOT_DST); #ifdef CONFIG_NAND_ENV_DST nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, @@ -36,6 +36,6 @@ void nand_boot(void) /* * Jump to U-Boot image */ - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + uboot = (void *)CFG_SYS_NAND_U_BOOT_START; (*uboot)(); } diff --git a/drivers/mtd/nand/raw/nand_spl_simple.c b/drivers/mtd/nand/raw/nand_spl_simple.c index 727861c8f7e..2f3af9edd4c 100644 --- a/drivers/mtd/nand/raw/nand_spl_simple.c +++ b/drivers/mtd/nand/raw/nand_spl_simple.c @@ -10,13 +10,13 @@ #include #include -static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; +static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS; static struct mtd_info *mtd; static struct nand_chip nand_chip; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ - CONFIG_SYS_NAND_ECCSIZE) -#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES) + CFG_SYS_NAND_ECCSIZE) +#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES) #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512) @@ -139,8 +139,8 @@ static int nand_read_page(int block, int page, uchar *dst) u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; int i; - int eccsize = CONFIG_SYS_NAND_ECCSIZE; - int eccbytes = CONFIG_SYS_NAND_ECCBYTES; + int eccsize = CFG_SYS_NAND_ECCSIZE; + int eccbytes = CFG_SYS_NAND_ECCBYTES; int eccsteps = ECCSTEPS; uint8_t *p = dst; @@ -170,8 +170,8 @@ static int nand_read_page(int block, int page, void *dst) u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; int i; - int eccsize = CONFIG_SYS_NAND_ECCSIZE; - int eccbytes = CONFIG_SYS_NAND_ECCBYTES; + int eccsize = CFG_SYS_NAND_ECCSIZE; + int eccbytes = CFG_SYS_NAND_ECCBYTES; int eccsteps = ECCSTEPS; uint8_t *p = dst; @@ -212,7 +212,7 @@ void nand_init(void) */ mtd = nand_to_mtd(&nand_chip); nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = - (void __iomem *)CONFIG_SYS_NAND_BASE; + (void __iomem *)CFG_SYS_NAND_BASE; board_nand_init(&nand_chip); #ifdef CONFIG_SPL_NAND_SOFTECC diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 8b9ff4de189..b7d261d8ce1 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -407,7 +407,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le cnt = PREFETCH_STATUS_FIFO_CNT(cnt); for (i = 0; i < cnt / 4; i++) { - *buf++ = readl(CONFIG_SYS_NAND_BASE); + *buf++ = readl(CFG_SYS_NAND_BASE); len -= 4; } } while (len); diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c index 13fd631cb40..d4b40e810f0 100644 --- a/drivers/mtd/nand/raw/vf610_nfc.c +++ b/drivers/mtd/nand/raw/vf610_nfc.c @@ -812,7 +812,7 @@ void board_nand_init(void) return; } - nfc->regs = (void __iomem *)CONFIG_SYS_NAND_BASE; + nfc->regs = (void __iomem *)CFG_SYS_NAND_BASE; err = vf610_nfc_nand_init(nfc, 0); if (err) printf("VF610 NAND init failed (err %d)\n", err); diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index a39fe5f28a8..fc21af56ec7 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -93,8 +93,8 @@ #endif #ifdef CONFIG_CMD_NAND -# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE -# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE +# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 #endif diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index f0734712eaa..f7c09a2333c 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -94,8 +94,8 @@ # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif -# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE -# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE +# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index b0809332bb5..a5518d3d50f 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -82,6 +82,6 @@ /* Ethernet configuration part */ /* NAND configuration part */ -#define CONFIG_SYS_NAND_BASE 0x0C000000 +#define CFG_SYS_NAND_BASE 0x0C000000 #endif /* __CONFIG_H */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index bb93c287441..c4cde1cc512 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -141,7 +141,7 @@ /* * NAND Flash on the Local Bus */ -#define CONFIG_SYS_NAND_BASE 0xE0600000 +#define CFG_SYS_NAND_BASE 0xE0600000 /* Vitesse 7385 */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 3448766d8e5..3288969ce8c 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -36,18 +36,18 @@ #ifdef CONFIG_MTD_RAW_NAND #ifdef CONFIG_NXP_ESBC -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) +#define CFG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) +#define CFG_SYS_NAND_U_BOOT_START 0x00200000 #else #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CFG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CFG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CFG_SYS_NAND_U_BOOT_START (0x11000000) #elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 +#define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CFG_SYS_NAND_U_BOOT_DST 0xD0000000 +#define CFG_SYS_NAND_U_BOOT_START 0xD0000000 #endif #endif #endif @@ -167,23 +167,23 @@ extern unsigned long get_sdram_size(void); /* CFI for NOR Flash */ /* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CFG_SYS_NAND_BASE 0xff800000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull +#define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull #else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE #endif #define CONFIG_MTD_PARTITION -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) #if defined(CONFIG_TARGET_P1010RDB_PA) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ @@ -192,7 +192,7 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ #elif defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -201,49 +201,49 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ #endif -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_TARGET_P1010RDB_PA) /* NAND Flash Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ +#define CFG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0C) | \ FTIM0_NAND_TWCHT(0x04) | \ FTIM0_NAND_TWH(0x05) -#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ +#define CFG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ FTIM1_NAND_TWBE(0x1d) | \ FTIM1_NAND_TRR(0x07) | \ FTIM1_NAND_TRP(0x0c) -#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ +#define CFG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ FTIM2_NAND_TREH(0x05) | \ FTIM2_NAND_TWHRE(0x0f) -#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) +#define CFG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) #elif defined(CONFIG_TARGET_P1010RDB_PB) /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 #endif /* Set up IFC registers for boot location NOR/NAND */ #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR @@ -259,13 +259,13 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif /* CPLD on IFC */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 08c1bccb2b7..b9311fc5e4f 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -111,22 +111,22 @@ /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BASE 0xffa00000 +#define CFG_SYS_NAND_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#define CFG_SYS_NAND_BASE_PHYS 0xfffa00000ull #else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE #endif -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE} /* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | (2< /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* APBH DMA is required for NAND support */ /* Ethernet */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index f0fbbe2870b..9061eba6686 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -22,9 +22,9 @@ #endif /* NAND support */ -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index d7e181b942a..afe8badd650 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -122,8 +122,8 @@ #ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND /* NAND stuff */ -/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */ -#define CONFIG_SYS_NAND_BASE -1 +/* used to initialize CFG_SYS_NAND_BASE_LIST which is unused */ +#define CFG_SYS_NAND_BASE -1 #endif /* USB Configs */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 5c7a9f2e69f..f9bf849ae98 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -166,7 +166,7 @@ #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 #endif /* USB Configs */ diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 3e7c0c0d883..9d44e6723e2 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -37,13 +37,13 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8 #endif /* DFU class support */ @@ -53,13 +53,13 @@ /* Defines for SPL */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ +#define CFG_SYS_NAND_ECCSIZE 256 +#define CFG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 5a5c65da16c..f8ba4e82819 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -107,21 +107,21 @@ * Flash & Environment */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 -#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#define CONFIG_SYS_NAND_ECCPOS { \ +#define CFG_SYS_NAND_CS 3 +#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CFG_SYS_NAND_MASK_CLE 0x10 +#define CFG_SYS_NAND_MASK_ALE 0x8 +#define CFG_SYS_NAND_U_BOOT_SIZE 0x40000 +#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000 +#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST +#define CFG_SYS_NAND_ECCPOS { \ 24, 25, 26, 27, 28, \ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 59, 60, 61, 62, 63 } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 10 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 10 #endif #ifdef CONFIG_MTD_NOR_FLASH diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 42366123cb1..5244b9cf5cc 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -35,8 +35,8 @@ /* * NAND controller */ -#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE SLC_NAND_BASE +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } /* * NAND chip timings @@ -79,10 +79,10 @@ */ /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_TEXT_BASE */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 +#define CFG_SYS_NAND_U_BOOT_SIZE 0x60000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE /* See common/spl/spl.c spl_set_header_raw_uboot() */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index d45115bdf68..46410595c2b 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -100,12 +100,12 @@ /* Defines for SPL */ /* NAND boot config */ -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ +#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 +#define CFG_SYS_NAND_U_BOOT_SIZE 0x200000 #endif /* __CONFIG_H */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 6cf716e293d..93201be485d 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -75,15 +75,15 @@ #ifdef CONFIG_MTD_RAW_NAND /* NAND: device related configs */ /* NAND: driver related configs */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ 34, 35, 36, 37, 38, 39, 40, 41, \ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 #endif /* !CONFIG_MTD_RAW_NAND */ /* Parallel NOR Support */ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 75322a37322..6cae663cb8a 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -14,10 +14,10 @@ #include "siemens-am33x-common.h" /* NAND specific changes for etamin due to different page size */ -#undef CONFIG_SYS_NAND_ECCPOS +#undef CFG_SYS_NAND_ECCPOS #define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ @@ -40,14 +40,14 @@ 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ } -#undef CONFIG_SYS_NAND_ECCSIZE -#undef CONFIG_SYS_NAND_ECCBYTES -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 26 +#undef CFG_SYS_NAND_ECCSIZE +#undef CFG_SYS_NAND_ECCBYTES +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 26 -#define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */ -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ - CONFIG_SYS_NAND_BASE2} +#define CFG_SYS_NAND_BASE2 (0x18000000) /* physical address */ +#define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE, \ + CFG_SYS_NAND_BASE2} #define DDR_PLL_FREQ 303 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index a18920d3f09..f19e12d9090 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -37,12 +37,12 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) #endif /* JFFS2 */ diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index 3d62efb38ff..ba098316e08 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -22,13 +22,13 @@ #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ /* NAND flash */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +#define CFG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE BIT(22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 +#define CFG_SYS_NAND_MASK_CLE BIT(22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5 /* SPL */ @@ -37,8 +37,8 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_SIZE 0xa0000 +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE #endif diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 232f7868cc2..974dff8f6f4 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -96,7 +96,7 @@ * NAND */ #define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 -#define CONFIG_SYS_NAND_BASE 0xd8000000 +#define CFG_SYS_NAND_BASE 0xd8000000 #define CONFIG_MXC_NAND_HWECC /* diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index f52367cc1a0..e430efad42e 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -126,8 +126,8 @@ /* NAND */ #ifdef CONFIG_NAND_MXS -# define CONFIG_SYS_NAND_BASE 0x40000000 -# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +# define CFG_SYS_NAND_BASE 0x40000000 +# define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE /* MTD device */ #endif diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 008fc079a65..7760c8c418a 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -116,8 +116,8 @@ /* Environment organization */ /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE /* USB Configs */ #ifdef CONFIG_CMD_USB diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index 46a96f1f828..d42eb750d01 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -72,6 +72,6 @@ /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CFG_SYS_NAND_BASE 0x20000000 #endif diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h index a2323bd6716..a768ff35510 100644 --- a/include/configs/imx8mn_bsh_smm_s2.h +++ b/include/configs/imx8mn_bsh_smm_s2.h @@ -44,6 +44,6 @@ /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CFG_SYS_NAND_BASE 0x20000000 #endif /* __IMX8MN_BSH_SMM_S2_H */ diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 5be46090a14..8f2b474817d 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -166,7 +166,7 @@ #ifdef CONFIG_NAND_MXS /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CFG_SYS_NAND_BASE 0x20000000 #endif /* CONFIG_NAND_MXS */ #endif /* __IMX8MP_RSB3720_H */ diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 181ed1b8fae..a658cbc07c2 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -59,7 +59,7 @@ #if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE #endif /* diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 0613b77e966..d883b188ce3 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -77,17 +77,17 @@ #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 /* NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x68000000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x68000000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_TE | \ CSPR_MSEL_NAND | \ CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \ | CSOR_NAND_ECC_DEC_EN \ | CSOR_NAND_ECC_MODE_4 \ | CSOR_NAND_RAL_3 \ @@ -97,29 +97,29 @@ | CSOR_NAND_TRHZ_40 \ | CSOR_NAND_BCTLD) -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ FTIM0_NAND_TWP(0x8) | \ FTIM0_NAND_TWCHT(0x3) | \ FTIM0_NAND_TWH(0x5)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ FTIM1_NAND_TWBE(0x1e) | \ FTIM1_NAND_TRR(0x6) | \ FTIM1_NAND_TRP(0x8)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ FTIM2_NAND_TREH(0x5) | \ FTIM2_NAND_TWHRE(0x3c)) -#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) - -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) + +#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 + +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } /* QRIO FPGA Definitions */ #define CONFIG_SYS_QRIO_BASE 0x70000000 diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 2e1459e3e4f..51ee6865533 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -231,18 +231,18 @@ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} /* NAND Flash on IFC CS1*/ -#define CONFIG_SYS_NAND_BASE 0xfa000000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#define CFG_SYS_NAND_BASE 0xfa000000 +#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE) -#define CONFIG_SYS_NAND_CSPR_EXT (0x0f) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \ +#define CFG_SYS_NAND_CSPR_EXT (0x0f) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \ CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\ 0x00000010 | /* drive TE high */\ CSPR_MSEL_NAND | /* MSEL = NAND */\ CSPR_V) /* valid */ -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */ -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \ CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */ \ CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \ CSOR_NAND_RAL_3 | /* RAL = 3Bytes */ \ @@ -253,30 +253,30 @@ CSOR_NAND_BCTLD) /**/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ FTIM0_NAND_TWP(0x8) | \ FTIM0_NAND_TWCHT(0x3) | \ FTIM0_NAND_TWH(0x5)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ FTIM1_NAND_TWBE(0x1e) | \ FTIM1_NAND_TRR(0x6) | \ FTIM1_NAND_TRP(0x8)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ FTIM2_NAND_TREH(0x5) | \ FTIM2_NAND_TWHRE(0x3c)) -#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) +#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 /* More NAND Flash Params */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } /* QRIO on IFC CS2 */ #define CONFIG_SYS_QRIO_BASE 0xfb000000 diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index d6b60d8139a..b9540298747 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -12,7 +12,7 @@ #define CONFIG_NAND_ECC_BCH #define CONFIG_NAND_KMETER1 #define NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ +#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 926c85805b7..7d89b538952 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -11,9 +11,9 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_SIZE (400 << 10) +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #endif @@ -70,17 +70,17 @@ * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -88,20 +88,20 @@ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif /* @@ -156,14 +156,14 @@ #endif #if defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK @@ -205,14 +205,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 8c19468141a..47367845a07 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -59,8 +59,8 @@ /* NAND SPL */ #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index d207e475fc0..21263705c80 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -79,17 +79,17 @@ * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -97,25 +97,25 @@ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #endif #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) +#define CFG_SYS_NAND_U_BOOT_SIZE (640 << 10) #endif #if defined(CONFIG_TFABOOT) || \ @@ -188,14 +188,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK @@ -206,14 +206,14 @@ #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK @@ -255,14 +255,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 206de7e1380..51667f20258 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -51,16 +51,16 @@ * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -68,24 +68,24 @@ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) +#define CFG_SYS_NAND_U_BOOT_SIZE (1024 << 10) #endif /* @@ -126,24 +126,24 @@ #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR @@ -163,14 +163,14 @@ #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif #endif diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 7e1a724387e..07ec2c95637 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -59,8 +59,8 @@ /* NAND SPL */ #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #endif /* GPIO */ diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 48408f28583..8402eac4184 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -14,16 +14,16 @@ * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -31,31 +31,31 @@ | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE /* IFC Timing Params */ -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 /* EEPROM */ #define I2C_RETIMER_ADDR 0x18 diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 037d462b5df..d51209c60f2 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -95,17 +95,17 @@ * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -113,25 +113,25 @@ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #endif #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10) #endif #if defined(CONFIG_TFABOOT) || \ @@ -204,14 +204,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK @@ -222,14 +222,14 @@ #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK @@ -271,14 +271,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 769349336af..0df68915989 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -19,16 +19,16 @@ #define CONFIG_SYS_UBOOT_BASE 0x40100000 #endif -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -36,20 +36,20 @@ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE /* @@ -78,14 +78,14 @@ #define CONFIG_SYS_CPLD_FTIM3 0x0 /* IFC Timing Params */ -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 73e4ac3e3d4..dec661d6b19 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -88,8 +88,8 @@ unsigned long long get_qixis_addr(void); #define QIXIS_BASE_PHYS_EARLY 0xC000000 -#define CONFIG_SYS_NAND_BASE 0x530000000ULL -#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 +#define CFG_SYS_NAND_BASE 0x530000000ULL +#define CFG_SYS_NAND_BASE_PHYS 0x30000000 /* MC firmware */ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 3a2fba6b04e..ae452075ac0 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -69,14 +69,14 @@ #endif #endif -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -85,20 +85,20 @@ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 @@ -174,14 +174,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL @@ -193,14 +193,14 @@ #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 #else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL @@ -230,14 +230,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index e2ae3026c29..2ca1384c231 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -53,14 +53,14 @@ #endif #endif -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -69,20 +69,20 @@ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 @@ -132,14 +132,14 @@ #if defined(CONFIG_TFABOOT) || \ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 53a3af1baac..d8997208e97 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -81,8 +81,8 @@ unsigned long long get_qixis_addr(void); #define QIXIS_SDID_MASK 0x07 #define QIXIS_ESDHC_NO_ADAPTER 0x7 -#define CONFIG_SYS_NAND_BASE 0x530000000ULL -#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 +#define CFG_SYS_NAND_BASE 0x530000000ULL +#define CFG_SYS_NAND_BASE_PHYS 0x30000000 /* MC firmware */ /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ @@ -129,8 +129,8 @@ unsigned long long get_qixis_addr(void); " 0x580e00000 \0" #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#define CFG_SYS_NAND_U_BOOT_DST 0x80400000 +#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST #endif #include diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index e6019870d8a..d9e11cc1917 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -70,14 +70,14 @@ CONFIG_SYS_FLASH_BASE + 0x40000000} #endif -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -86,20 +86,20 @@ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #define QIXIS_LBMAP_SWITCH 0x06 @@ -163,16 +163,16 @@ #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 + +#define CFG_SYS_NAND_U_BOOT_SIZE (640 * 1024) #endif #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT @@ -194,14 +194,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 382d516c08b..086c46902c8 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -67,14 +67,14 @@ CONFIG_SYS_FLASH_BASE + 0x40000000} #endif -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -83,20 +83,20 @@ | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ FTIM0_NAND_TWP(0x30) | \ FTIM0_NAND_TWCHT(0x0e) | \ FTIM0_NAND_TWH(0x14)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ FTIM1_NAND_TWBE(0xab) | \ FTIM1_NAND_TRR(0x1c) | \ FTIM1_NAND_TRP(0x30)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ FTIM2_NAND_TREH(0x14) | \ FTIM2_NAND_TWHRE(0x3c)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #define QIXIS_LBMAP_SWITCH 0x06 @@ -146,16 +146,16 @@ #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 + +#define CFG_SYS_NAND_U_BOOT_SIZE (512 * 1024) #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY @@ -166,14 +166,14 @@ #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif #endif #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 36522419172..1734f323f92 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -44,10 +44,10 @@ * NAND */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI +#define CFG_SYS_NAND_BASE NFC_BASE_ADDR_AXI #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR -#define CONFIG_SYS_NAND_LARGEPAGE +#define CFG_SYS_NAND_LARGEPAGE #define CONFIG_MXC_NAND_HWECC #endif diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 30267e29a12..cd3910ee4ba 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -52,11 +52,11 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND -# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ -# define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -# define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) -# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) +# define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ +# define CFG_SYS_NAND_MASK_ALE (1 << 21) +# define CFG_SYS_NAND_MASK_CLE (1 << 22) +# define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) +# define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) #endif /* hw-controller addresses */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 61570b7af53..8176566f3f6 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -36,7 +36,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* DMA stuff, needed for GPMI/MXS NAND support */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 0d9764e3b4c..a41e428eb8a 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -86,7 +86,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* DMA stuff, needed for GPMI/MXS NAND support */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 2a97d2fac46..af176583814 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -93,7 +93,7 @@ */ #ifdef CONFIG_NAND_MXS /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* DMA stuff, needed for GPMI/MXS NAND support */ #endif diff --git a/include/configs/mxs.h b/include/configs/mxs.h index e8610386f04..9d6b3d40484 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -83,7 +83,7 @@ /* NAND */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x60000000 +#define CFG_SYS_NAND_BASE 0x60000000 #endif /* OCOTP */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index a777305ec76..e18d16cc99c 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -30,7 +30,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index ccc203f5f24..2a528850829 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -31,7 +31,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index d46ca337d5f..0890f51eff2 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -21,10 +21,10 @@ /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ +#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 3 /* NAND: SPL falcon mode configs */ #endif /* CONFIG_MTD_RAW_NAND */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 77629d7fc1e..6eec955e88f 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -26,10 +26,10 @@ /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ +#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 3 #endif /* CONFIG_MTD_RAW_NAND */ #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 97f47ea5b71..10f6ba63601 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -70,14 +70,14 @@ #define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) /* NAND config */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ 34, 35, 36, 37, 38, 39, 40, 41, \ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 #endif /* __IGEP00X0_H */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 7c0bdcbb115..6001037ae88 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -17,15 +17,15 @@ /* Board NAND Info. */ #ifdef CONFIG_MTD_RAW_NAND /* NAND devices */ -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ +#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 52, 53, 54, 55, 56} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 13 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 13 #endif /* Environment information */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index d9f70c75323..81ca68de9bc 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -105,21 +105,21 @@ * Flash & Environment */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 +#define CFG_SYS_NAND_CS 3 +#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CFG_SYS_NAND_MASK_CLE 0x10 +#define CFG_SYS_NAND_MASK_ALE 0x8 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC -#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K -#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#define CONFIG_SYS_NAND_ECCPOS { \ +#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K +#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000 +#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST +#define CFG_SYS_NAND_ECCPOS { \ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 10 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 10 #endif /* diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 778bf5112af..38f360b53ca 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -98,13 +98,13 @@ #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CFG_SYS_NAND_U_BOOT_SIZE (832 << 10) +#define CFG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CFG_SYS_NAND_U_BOOT_START (0x11000000) #elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CFG_SYS_NAND_U_BOOT_DST 0xf8f80000 +#define CFG_SYS_NAND_U_BOOT_START 0xf8f80000 #endif /* not CONFIG_TPL_BUILD */ #endif @@ -207,22 +207,22 @@ /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CFG_SYS_NAND_BASE 0xff800000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull +#define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull #else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE #endif -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | (2< Date: Wed, 16 Nov 2022 13:10:26 -0500 Subject: powerpc: Rename CONFIG_NS16550_MIN_FUNCTIONS This symbol is specific to the PowerPC SPL implementation, so rename this to reflect that it's in SPL and used / tested there, so that we can then safely migrate it to Kconfig. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 2 +- drivers/serial/ns16550.c | 8 ++++---- drivers/serial/serial_ns16550.c | 4 ++-- include/configs/P1010RDB.h | 4 +--- include/configs/p1_p2_rdb_pc.h | 4 +--- scripts/config_whitelist.txt | 2 +- 6 files changed, 10 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/README b/README index f5407576276..f71832b689e 100644 --- a/README +++ b/README @@ -1619,7 +1619,7 @@ use the "saveenv" command to store a valid environment. - CONFIG_SYS_FAULT_MII_ADDR: MII address of the PHY to check for the Ethernet link state. -- CONFIG_NS16550_MIN_FUNCTIONS: +- CONFIG_SPL_NS16550_MIN_FUNCTIONS: Define this if you desire to only have use of the NS16550_init and NS16550_putc functions for the serial driver located at drivers/serial/ns16550.c. This option is useful for saving diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 7592979cab5..5a693d2f02a 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -272,7 +272,7 @@ void ns16550_init(struct ns16550 *com_port, int baud_divisor) #endif } -#ifndef CONFIG_NS16550_MIN_FUNCTIONS +#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) void ns16550_reinit(struct ns16550 *com_port, int baud_divisor) { serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); @@ -281,7 +281,7 @@ void ns16550_reinit(struct ns16550 *com_port, int baud_divisor) serial_out(ns16550_getfcr(com_port), &com_port->fcr); ns16550_setbrg(com_port, baud_divisor); } -#endif /* CONFIG_NS16550_MIN_FUNCTIONS */ +#endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */ void ns16550_putc(struct ns16550 *com_port, char c) { @@ -299,7 +299,7 @@ void ns16550_putc(struct ns16550 *com_port, char c) schedule(); } -#ifndef CONFIG_NS16550_MIN_FUNCTIONS +#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) char ns16550_getc(struct ns16550 *com_port) { while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) { @@ -317,7 +317,7 @@ int ns16550_tstc(struct ns16550 *com_port) return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0; } -#endif /* CONFIG_NS16550_MIN_FUNCTIONS */ +#endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */ #ifdef CONFIG_DEBUG_UART_NS16550 diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index 97b6a4ff40d..76aa1e5afb4 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -11,7 +11,7 @@ #include #include -#ifndef CONFIG_NS16550_MIN_FUNCTIONS +#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) DECLARE_GLOBAL_DATA_PTR; @@ -251,4 +251,4 @@ void ns16550_serial_initialize(void) #endif } -#endif /* !CONFIG_NS16550_MIN_FUNCTIONS */ +#endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 154bf584f29..9afd834f9fa 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -325,9 +325,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif +#define CONFIG_SPL_NS16550_MIN_FUNCTIONS #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 38f360b53ca..838c62c6711 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -322,9 +322,7 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif +#define CONFIG_SPL_NS16550_MIN_FUNCTIONS #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c0f55e41a50..3e717bb72ad 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -186,7 +186,6 @@ CONFIG_NETMASK CONFIG_NEVER_ASSERT_ODT_TO_CPU CONFIG_NOBQFMAN CONFIG_NORBOOT -CONFIG_NS16550_MIN_FUNCTIONS CONFIG_NUM_DSP_CPUS CONFIG_ODROID_REV_AIN CONFIG_OTHBOOTARGS @@ -278,6 +277,7 @@ CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET +CONFIG_SPL_NS16550_MIN_FUNCTIONS CONFIG_SRIO1 CONFIG_SRIO2 CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET -- cgit v1.3.1 From 9591b63531fa5a34698ee7bb3800af6c4ea6ba2f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 09:39:03 -0500 Subject: Convert CONFIG_SYS_NS16550_MEM32 et al to Kconfig This converts the following to Kconfig: CONFIG_SPL_NS16550_MIN_FUNCTIONS CONFIG_SYS_NS16550_MEM32 CONFIG_SYS_NS16550_PORT_MAPPED CONFIG_SYS_NS16550_REG_SIZE CONFIG_SYS_NS16550_SERIAL To do this we also introduce CONFIG_SPL_SYS_NS16550_SERIAL so that platforms can enable the legacy driver here for SPL. Signed-off-by: Tom Rini --- README | 7 --- arch/arm/include/asm/arch-bcmcygnus/configs.h | 4 -- arch/arm/include/asm/arch-bcmnsp/configs.h | 3 -- configs/10m50_defconfig | 1 + configs/MPC837XERDB_defconfig | 2 +- configs/MPC8548CDS_36BIT_defconfig | 2 +- configs/MPC8548CDS_defconfig | 2 +- configs/MPC8548CDS_legacy_defconfig | 2 +- configs/P1010RDB-PA_36BIT_NAND_defconfig | 3 +- configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 +- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 +- configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 +- configs/P1010RDB-PA_NAND_defconfig | 3 +- configs/P1010RDB-PA_NOR_defconfig | 2 +- configs/P1010RDB-PA_SDCARD_defconfig | 2 +- configs/P1010RDB-PA_SPIFLASH_defconfig | 2 +- configs/P1010RDB-PB_36BIT_NAND_defconfig | 3 +- configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 +- configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 +- configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 +- configs/P1010RDB-PB_NAND_defconfig | 3 +- configs/P1010RDB-PB_NOR_defconfig | 2 +- configs/P1010RDB-PB_SDCARD_defconfig | 2 +- configs/P1010RDB-PB_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +- configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 2 +- configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PC_36BIT_defconfig | 2 +- configs/P1020RDB-PC_NAND_defconfig | 3 +- configs/P1020RDB-PC_SDCARD_defconfig | 2 +- configs/P1020RDB-PC_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PC_defconfig | 2 +- configs/P1020RDB-PD_NAND_defconfig | 3 +- configs/P1020RDB-PD_SDCARD_defconfig | 2 +- configs/P1020RDB-PD_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PD_defconfig | 2 +- configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +- configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 2 +- configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 +- configs/P2020RDB-PC_36BIT_defconfig | 2 +- configs/P2020RDB-PC_NAND_defconfig | 3 +- configs/P2020RDB-PC_SDCARD_defconfig | 2 +- configs/P2020RDB-PC_SPIFLASH_defconfig | 2 +- configs/P2020RDB-PC_defconfig | 2 +- configs/P2041RDB_NAND_defconfig | 2 +- configs/P2041RDB_SDCARD_defconfig | 2 +- configs/P2041RDB_SPIFLASH_defconfig | 2 +- configs/P2041RDB_defconfig | 2 +- configs/SBx81LIFKW_defconfig | 3 +- configs/SBx81LIFXCAT_defconfig | 3 +- configs/T1024RDB_NAND_defconfig | 2 +- configs/T1024RDB_SDCARD_defconfig | 2 +- configs/T1024RDB_SPIFLASH_defconfig | 2 +- configs/T1024RDB_defconfig | 2 +- configs/T1042D4RDB_NAND_defconfig | 2 +- configs/T1042D4RDB_SDCARD_defconfig | 2 +- configs/T1042D4RDB_SPIFLASH_defconfig | 2 +- configs/T1042D4RDB_defconfig | 2 +- configs/T2080QDS_NAND_defconfig | 2 +- configs/T2080QDS_SDCARD_defconfig | 2 +- configs/T2080QDS_SECURE_BOOT_defconfig | 2 +- configs/T2080QDS_SPIFLASH_defconfig | 2 +- configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 +- configs/T2080QDS_defconfig | 2 +- configs/T2080RDB_NAND_defconfig | 2 +- configs/T2080RDB_SDCARD_defconfig | 2 +- configs/T2080RDB_SPIFLASH_defconfig | 2 +- configs/T2080RDB_defconfig | 2 +- configs/T2080RDB_revD_NAND_defconfig | 2 +- configs/T2080RDB_revD_SDCARD_defconfig | 2 +- configs/T2080RDB_revD_SPIFLASH_defconfig | 2 +- configs/T2080RDB_revD_defconfig | 2 +- configs/T4240RDB_SDCARD_defconfig | 2 +- configs/T4240RDB_defconfig | 2 +- configs/am43xx_evm_qspiboot_defconfig | 2 +- configs/am43xx_hs_evm_qspi_defconfig | 2 +- configs/axs101_defconfig | 1 + configs/axs103_defconfig | 1 + configs/bayleybay_defconfig | 1 + configs/bcm7260_defconfig | 3 +- configs/bcm7445_defconfig | 3 +- configs/cherryhill_defconfig | 1 + configs/chromebit_mickey_defconfig | 1 + configs/chromebook_bob_defconfig | 1 + configs/chromebook_coral_defconfig | 1 + configs/chromebook_jerry_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + configs/chromebook_link64_defconfig | 1 + configs/chromebook_link_defconfig | 1 + configs/chromebook_minnie_defconfig | 1 + configs/chromebook_samus_defconfig | 1 + configs/chromebook_samus_tpl_defconfig | 1 + configs/chromebook_speedy_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + ...conga-qeval20-qa3-e3845-internal-uart_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/coreboot64_defconfig | 1 + configs/coreboot_defconfig | 1 + configs/cougarcanyon2_defconfig | 1 + configs/crownbay_defconfig | 1 + configs/d2net_v2_defconfig | 3 +- configs/dns325_defconfig | 3 +- configs/dockstar_defconfig | 3 +- configs/dreamplug_defconfig | 3 +- configs/ds109_defconfig | 3 +- configs/eaidk-610-rk3399_defconfig | 1 + configs/efi-x86_payload32_defconfig | 1 + configs/efi-x86_payload64_defconfig | 1 + configs/elgin-rv1108_defconfig | 1 + configs/evb-px30_defconfig | 1 + configs/evb-px5_defconfig | 1 + configs/evb-rk3036_defconfig | 1 + configs/evb-rk3128_defconfig | 1 + configs/evb-rk3229_defconfig | 1 + configs/evb-rk3288_defconfig | 1 + configs/evb-rk3308_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + configs/evb-rk3399_defconfig | 1 + configs/evb-rk3568_defconfig | 1 + configs/evb-rv1108_defconfig | 1 + configs/ficus-rk3399_defconfig | 1 + configs/firefly-px30_defconfig | 1 + configs/firefly-rk3288_defconfig | 1 + configs/firefly-rk3399_defconfig | 1 + configs/geekbox_defconfig | 1 + configs/goflexhome_defconfig | 3 +- configs/guruplug_defconfig | 3 +- configs/hsdk_4xd_defconfig | 1 + configs/hsdk_defconfig | 1 + configs/ib62x0_defconfig | 3 +- configs/iconnect_defconfig | 3 +- configs/inetspace_v2_defconfig | 3 +- configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2g_evm_defconfig | 1 + configs/k2g_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + configs/khadas-edge-captain-rk3399_defconfig | 1 + configs/khadas-edge-rk3399_defconfig | 1 + configs/khadas-edge-v-rk3399_defconfig | 1 + configs/kylin-rk3036_defconfig | 1 + configs/leez-rk3399_defconfig | 1 + configs/lion-rk3368_defconfig | 1 + configs/ls1012a2g5rdb_qspi_defconfig | 2 +- configs/ls1012a2g5rdb_tfa_defconfig | 2 +- configs/ls1012afrdm_qspi_defconfig | 2 +- configs/ls1012afrdm_tfa_defconfig | 2 +- configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1012afrwy_qspi_defconfig | 2 +- configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012afrwy_tfa_defconfig | 2 +- configs/ls1012aqds_qspi_defconfig | 2 +- configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012aqds_tfa_defconfig | 2 +- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_qspi_defconfig | 2 +- configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_tfa_defconfig | 2 +- configs/ls1021aiot_qspi_defconfig | 2 +- configs/ls1021aiot_sdcard_defconfig | 2 +- configs/ls1021aqds_nand_defconfig | 2 +- configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021aqds_qspi_defconfig | 2 +- configs/ls1021aqds_sdcard_ifc_defconfig | 2 +- configs/ls1021aqds_sdcard_qspi_defconfig | 2 +- configs/ls1021atsn_qspi_defconfig | 2 +- configs/ls1021atsn_sdcard_defconfig | 2 +- configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_qspi_defconfig | 2 +- .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_sdcard_ifc_defconfig | 2 +- configs/ls1021atwr_sdcard_qspi_defconfig | 2 +- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028aqds_tfa_defconfig | 2 +- configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028ardb_tfa_defconfig | 2 +- configs/ls1043aqds_defconfig | 2 +- configs/ls1043aqds_nand_defconfig | 2 +- configs/ls1043aqds_nor_ddr3_defconfig | 2 +- configs/ls1043aqds_qspi_defconfig | 2 +- configs/ls1043aqds_sdcard_ifc_defconfig | 2 +- configs/ls1043aqds_sdcard_qspi_defconfig | 2 +- configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043aqds_tfa_defconfig | 2 +- configs/ls1043ardb_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_defconfig | 2 +- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_nand_defconfig | 2 +- configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_sdcard_defconfig | 2 +- configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_tfa_defconfig | 2 +- configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046afrwy_tfa_defconfig | 2 +- configs/ls1046aqds_SECURE_BOOT_defconfig | 2 +- configs/ls1046aqds_defconfig | 2 +- configs/ls1046aqds_nand_defconfig | 2 +- configs/ls1046aqds_qspi_defconfig | 2 +- configs/ls1046aqds_sdcard_ifc_defconfig | 2 +- configs/ls1046aqds_sdcard_qspi_defconfig | 2 +- configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046aqds_tfa_defconfig | 2 +- configs/ls1046ardb_emmc_defconfig | 2 +- configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_qspi_defconfig | 2 +- configs/ls1046ardb_qspi_spl_defconfig | 2 +- configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_sdcard_defconfig | 2 +- configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_tfa_defconfig | 2 +- configs/ls1088aqds_defconfig | 2 +- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088aqds_qspi_defconfig | 2 +- configs/ls1088aqds_sdcard_ifc_defconfig | 2 +- configs/ls1088aqds_sdcard_qspi_defconfig | 2 +- configs/ls1088aqds_tfa_defconfig | 2 +- configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_qspi_defconfig | 2 +- .../ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_sdcard_qspi_defconfig | 2 +- configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_tfa_defconfig | 2 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 2 +- configs/ls2080aqds_defconfig | 2 +- configs/ls2080aqds_nand_defconfig | 2 +- configs/ls2080aqds_qspi_defconfig | 2 +- configs/ls2080aqds_sdcard_defconfig | 2 +- configs/ls2080ardb_SECURE_BOOT_defconfig | 2 +- configs/ls2080ardb_defconfig | 2 +- configs/ls2080ardb_nand_defconfig | 2 +- configs/ls2081ardb_defconfig | 2 +- configs/ls2088aqds_tfa_defconfig | 2 +- configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls2088ardb_qspi_defconfig | 2 +- configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls2088ardb_tfa_defconfig | 2 +- configs/malta64_defconfig | 1 + configs/malta64el_defconfig | 1 + configs/malta_defconfig | 1 + configs/maltael_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/miqi-rk3288_defconfig | 1 + configs/mk808_defconfig | 1 + configs/nanopc-t4-rk3399_defconfig | 1 + configs/nanopi-m4-2gb-rk3399_defconfig | 1 + configs/nanopi-m4-rk3399_defconfig | 1 + configs/nanopi-m4b-rk3399_defconfig | 1 + configs/nanopi-neo4-rk3399_defconfig | 1 + configs/nanopi-r2s-rk3328_defconfig | 1 + configs/nanopi-r4s-rk3399_defconfig | 1 + configs/nas220_defconfig | 3 +- configs/net2big_v2_defconfig | 3 +- configs/netspace_lite_v2_defconfig | 3 +- configs/netspace_max_v2_defconfig | 3 +- configs/netspace_mini_v2_defconfig | 3 +- configs/netspace_v2_defconfig | 3 +- configs/nsa310s_defconfig | 3 +- configs/odroid-go2_defconfig | 1 + configs/omap4_panda_defconfig | 2 +- configs/omap4_sdp4430_defconfig | 2 +- configs/omap5_uevm_defconfig | 2 +- configs/openrd_base_defconfig | 3 +- configs/openrd_client_defconfig | 3 +- configs/openrd_ultimate_defconfig | 3 +- configs/orangepi-rk3399_defconfig | 1 + configs/phycore-rk3288_defconfig | 1 + configs/pinebook-pro-rk3399_defconfig | 1 + configs/pogo_e02_defconfig | 3 +- configs/pogo_v4_defconfig | 3 +- configs/popmetal-rk3288_defconfig | 1 + configs/puma-rk3399_defconfig | 1 + configs/px30-core-ctouch2-of10-px30_defconfig | 1 + configs/px30-core-ctouch2-px30_defconfig | 1 + configs/px30-core-edimm2.2-px30_defconfig | 1 + configs/qemu-x86_64_defconfig | 1 + configs/qemu-x86_defconfig | 1 + configs/roc-cc-rk3308_defconfig | 1 + configs/roc-cc-rk3328_defconfig | 1 + configs/roc-pc-mezzanine-rk3399_defconfig | 1 + configs/roc-pc-rk3399_defconfig | 1 + configs/rock-pi-4-rk3399_defconfig | 1 + configs/rock-pi-4c-rk3399_defconfig | 1 + configs/rock-pi-e-rk3328_defconfig | 1 + configs/rock-pi-n10-rk3399pro_defconfig | 1 + configs/rock-pi-n8-rk3288_defconfig | 1 + configs/rock2_defconfig | 1 + configs/rock64-rk3328_defconfig | 1 + configs/rock960-rk3399_defconfig | 1 + configs/rock_defconfig | 1 + configs/rockpro64-rk3399_defconfig | 1 + configs/sheep-rk3368_defconfig | 1 + configs/sheevaplug_defconfig | 3 +- configs/slimbootloader_defconfig | 1 + configs/socfpga_agilex_atf_defconfig | 1 + configs/socfpga_agilex_defconfig | 1 + configs/socfpga_agilex_vab_defconfig | 1 + configs/socfpga_arria10_defconfig | 1 + configs/socfpga_chameleonv3_defconfig | 1 + configs/socfpga_n5x_atf_defconfig | 1 + configs/socfpga_n5x_defconfig | 1 + configs/socfpga_n5x_vab_defconfig | 1 + configs/socfpga_stratix10_atf_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + configs/som-db5800-som-6867_defconfig | 1 + configs/ten64_tfa_defconfig | 2 +- ...eadorable-x86-conga-qa3-e3845-pcie-x4_defconfig | 1 + configs/theadorable-x86-conga-qa3-e3845_defconfig | 1 + configs/ti816x_evm_defconfig | 2 +- configs/tinker-rk3288_defconfig | 1 + configs/tinker-s-rk3288_defconfig | 1 + configs/vyasa-rk3288_defconfig | 1 + configs/xtfpga_defconfig | 3 +- drivers/serial/Kconfig | 54 ++++++++++++++++++---- drivers/serial/Makefile | 2 +- include/configs/10m50_devboard.h | 1 - include/configs/MPC837XERDB.h | 2 - include/configs/MPC8548CDS.h | 2 - include/configs/P1010RDB.h | 3 -- include/configs/P2041RDB.h | 2 - include/configs/SBx81LIFKW.h | 2 - include/configs/SBx81LIFXCAT.h | 2 - include/configs/T102xRDB.h | 2 - include/configs/T104xRDB.h | 2 - include/configs/T208xQDS.h | 2 - include/configs/T208xRDB.h | 2 - include/configs/T4240RDB.h | 2 - include/configs/am43xx_evm.h | 4 -- include/configs/ax25-ae350.h | 4 -- include/configs/axs10x.h | 2 - include/configs/bcmstb.h | 2 - include/configs/bur_am335x_common.h | 2 - include/configs/chromebook_coral.h | 3 -- include/configs/cm_t43.h | 4 -- include/configs/dfi-bt700.h | 1 - include/configs/galileo.h | 1 - include/configs/gardena-smart-gateway-mt7688.h | 2 - include/configs/hsdk-4xd.h | 2 - include/configs/hsdk.h | 2 - include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/kmcent2.h | 2 - include/configs/legoev3.h | 1 - include/configs/linkit-smart-7688.h | 2 - include/configs/ls1012a_common.h | 2 - include/configs/ls1021aiot.h | 2 - include/configs/ls1021aqds.h | 4 -- include/configs/ls1021atsn.h | 4 -- include/configs/ls1021atwr.h | 4 -- include/configs/ls1028a_common.h | 2 - include/configs/ls1043a_common.h | 2 - include/configs/ls1046a_common.h | 2 - include/configs/ls1088a_common.h | 2 - include/configs/ls2080a_common.h | 2 - include/configs/malta.h | 1 - include/configs/mt7621.h | 2 - include/configs/mt7628.h | 2 - include/configs/mt8183.h | 3 -- include/configs/mt8516.h | 3 -- include/configs/mv-common.h | 2 - include/configs/nokia_rx51.h | 1 - include/configs/p1_p2_rdb_pc.h | 3 -- include/configs/px30_common.h | 2 - include/configs/rk3308_common.h | 2 - include/configs/rockchip-common.h | 2 - include/configs/siemens-am33x-common.h | 1 - include/configs/sniper.h | 5 -- include/configs/socfpga_arria10_socdk.h | 1 - include/configs/socfpga_chameleonv3.h | 1 - include/configs/socfpga_soc64_common.h | 1 - include/configs/sunxi-common.h | 2 - include/configs/tb100.h | 1 - include/configs/theadorable-x86-dfi-bt700.h | 1 - include/configs/ti814x_evm.h | 2 - include/configs/ti816x_evm.h | 2 - include/configs/ti_am335x_common.h | 6 --- include/configs/ti_armv7_keystone2.h | 1 - include/configs/ti_omap3_common.h | 4 -- include/configs/ti_omap4_common.h | 2 - include/configs/ti_omap5_common.h | 4 -- include/configs/vocore2.h | 2 - include/configs/x530.h | 2 - include/configs/x86-common.h | 1 - include/configs/xtfpga.h | 2 - include/ns16550.h | 2 +- 386 files changed, 397 insertions(+), 369 deletions(-) (limited to 'include') diff --git a/README b/README index f71832b689e..9086207954e 100644 --- a/README +++ b/README @@ -1619,13 +1619,6 @@ use the "saveenv" command to store a valid environment. - CONFIG_SYS_FAULT_MII_ADDR: MII address of the PHY to check for the Ethernet link state. -- CONFIG_SPL_NS16550_MIN_FUNCTIONS: - Define this if you desire to only have use of the NS16550_init - and NS16550_putc functions for the serial driver located at - drivers/serial/ns16550.c. This option is useful for saving - space for already greatly restricted images, including but not - limited to NAND_SPL configurations. - - CONFIG_DISPLAY_BOARDINFO Display information about the board that U-Boot is running on when U-Boot starts up. The board function checkboard() is called diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index 327c0e06977..0c7262352d5 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -11,10 +11,6 @@ /* uArchitecture specifics */ /* Serial Info */ -/* Post pad 3 bytes after each reg addr */ -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_SYS_NS16550_CLK 100000000 #define CONFIG_SYS_NS16550_CLK_DIV 54 #define CONFIG_SYS_NS16550_COM3 0x18023000 diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h index 05fa9b9612d..44699476b08 100644 --- a/arch/arm/include/asm/arch-bcmnsp/configs.h +++ b/arch/arm/include/asm/arch-bcmnsp/configs.h @@ -11,9 +11,6 @@ /* uArchitecture specifics */ /* Serial Info */ -/* no padding */ -#define CONFIG_SYS_NS16550_REG_SIZE 1 - #define CONFIG_SYS_NS16550_CLK 0x03b9aca0 #define CONFIG_SYS_NS16550_COM1 0x18000300 diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig index dd88d10274c..28966e0d0a4 100644 --- a/configs/10m50_defconfig +++ b/configs/10m50_defconfig @@ -47,5 +47,6 @@ CONFIG_PHY_GIGE=y CONFIG_ALTERA_TSE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_TIMER=y CONFIG_ALTERA_TIMER=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 675b2de151c..7054333d737 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -206,7 +206,7 @@ CONFIG_DM_ETH_PHY=y CONFIG_RGMII=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_FSL=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index e5c45a1bffa..85b055a93ff 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -85,5 +85,5 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_ADDR_MAP=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 85ec76a5971..0d21b893d8b 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -84,4 +84,4 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 852ac9a6eeb..b01919ec675 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -84,4 +84,4 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index e15ca5ea2b5..a3d9a8b4b76 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -129,7 +129,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index dcf74f5d6af..2ca02503993 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -93,7 +93,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 230c6d02831..5d57aa3ba4b 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -114,7 +114,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 982420db74c..a13b48c20ec 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -116,7 +116,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index b3af4450d00..a9c7652fab0 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -128,7 +128,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 537d8bf576b..a0277d0aa61 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -92,7 +92,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index dd9120970ba..f43a5a0c542 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -113,7 +113,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index ff7cfa24615..ef52f948827 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -115,7 +115,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index a61f4d017a6..2b2744dd74e 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -132,7 +132,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 92a7e096693..29b7d848095 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -95,7 +95,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 84e2d3c587a..98164d2bade 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -116,7 +116,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index b883b81e0cd..d74fbecfaa1 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -118,7 +118,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 7f7870d82c5..efd0a7eb896 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -131,7 +131,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 3e16470608e..44e98b9520f 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -94,7 +94,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index e985f8cd75d..9c650437660 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -115,7 +115,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 9f4ae14e0b2..4b967352f4d 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -117,7 +117,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 3f93b318c92..b65e6518787 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -142,7 +142,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 3b3cf1ee7a5..034a971bc8b 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -124,7 +124,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index aba5b9cedd4..9476c28e98b 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -126,7 +126,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index ce0ba0e3757..ecd5e978c8b 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -104,7 +104,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index f3fc4c82a54..80f4d22518c 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -141,7 +141,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 25eb5d5da74..50fc0c124e8 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -123,7 +123,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 054320f356c..dafb430e4c0 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -125,7 +125,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index aae886b75c4..411b4f05a44 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -103,7 +103,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index cc02fe6a8ac..8b0b6e4e680 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -144,7 +144,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index dc82da81b81..6a17f085a7f 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -126,7 +126,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 7b80edeeeb9..2738b208f16 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -128,7 +128,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 5fecb668473..fdd7703f72c 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -106,7 +106,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 9162774ad70..5904aa54b29 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -147,7 +147,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index fd143b610b9..938148df93a 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -129,7 +129,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index edb8b9958ea..c4a41c4c0eb 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -131,7 +131,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index b1dbca6e7ea..a4ed8fb39cd 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -109,7 +109,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 1269d22f90c..9b4ca39d34f 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -146,7 +146,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index b5394d05b7f..a6d98b42ce1 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -128,7 +128,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 431ca31302c..b3e4a1f0d0e 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -130,7 +130,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 1ee46f9fbe9..f1a9c058caa 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -108,7 +108,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 2ba56664462..0eec5089332 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -98,7 +98,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0x100000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 9a2796fc7fc..f9f4c31ddb6 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -93,7 +93,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0xD2000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 8cb00d5d316..6a974370088 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -95,7 +95,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0x110000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index c0bd16bd61f..1725a8a5a9c 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -90,7 +90,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index 73ef73c484e..fa7c35b9ef7 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -63,7 +63,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 9fa0fda84f2..125871301e3 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -61,7 +61,8 @@ CONFIG_MV88E61XX_FIXED_PORTS=0x300 CONFIG_PHY_FIXED=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 2aada043e83..f21c53d59f1 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -129,7 +129,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x200000 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index e5661b0b605..6f9f5a2603a 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -123,7 +123,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 320f22e348e..76a59604f2f 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -126,7 +126,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 1f571b6e6fa..a4825909e7a 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -98,7 +98,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0xEFE00000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 4088d40de30..1aa0e9eec17 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -129,7 +129,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x380000 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 5a6f9a8d248..ba1820e93a2 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -123,7 +123,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 2d03b4eb142..98cd9b71e03 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -126,7 +126,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 8f283fa8fd2..f6301a57cfd 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -98,7 +98,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0xEFF10000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index beb0259488d..dd7473ef7fd 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -136,7 +136,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 7ee5fb4f476..364aab58477 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -130,7 +130,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index c050e310c8f..c6710a0413c 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -104,7 +104,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 0ff651ae688..a705542eea7 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -133,7 +133,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 98065da77d6..d6d6ec0fbf0 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -93,7 +93,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 88e943d4d0d..802213de2b9 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -105,7 +105,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 23f6ee6e431..a881488dbea 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -136,7 +136,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index c2d95c10ab0..562a79955c4 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -130,7 +130,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 2194ff6c517..00018033a35 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -133,7 +133,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 7f57b004d57..0cb359de947 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -104,7 +104,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index 5d4573a7f9d..cbe1bb4e3f6 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -138,7 +138,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 7ca9a8b036e..80a2c003e6a 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -132,7 +132,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index 39fcd2dad39..99bee8e5ead 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -135,7 +135,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index 8d1011d06c5..aa6a053209e 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -106,7 +106,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 9b082674d60..b445b6bde1f 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -119,7 +119,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 662edc32c61..a807ac83474 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -94,7 +94,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index 0b759c8c2c4..fc6cad59cf4 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -53,7 +53,7 @@ CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y CONFIG_USB=y diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig index 68a96518878..08cac404c6e 100644 --- a/configs/am43xx_hs_evm_qspi_defconfig +++ b/configs/am43xx_hs_evm_qspi_defconfig @@ -55,7 +55,7 @@ CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y CONFIG_USB=y diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index a5436db7ac7..85a70c0996b 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -56,6 +56,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 7fbec63c58f..00d43e24c5a 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -56,6 +56,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 5f43f4c0ee9..90a734fcdad 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -59,6 +59,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig index 920e8828460..f8e0327d8f5 100644 --- a/configs/bcm7260_defconfig +++ b/configs/bcm7260_defconfig @@ -40,5 +40,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCMSTB=y CONFIG_MTD=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 # CONFIG_EFI_LOADER is not set diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index b44eabaa425..81433b02cbc 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -44,7 +44,8 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_BCMSTB_SPI=y diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index 06987ab8286..321121e3f72 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -50,6 +50,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_RTL8169=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 59ae29a80e0..2240988dd0d 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -94,6 +94,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 3d2f40fb955..d768e11db51 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -92,6 +92,7 @@ CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index 45905c6792b..a38b3b78c08 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -102,6 +102,7 @@ CONFIG_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SOUND_DA7219=y CONFIG_SOUND_I8254=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index ffa8070cb39..150dba14086 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -97,6 +97,7 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_SOUND=y CONFIG_I2S=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index e8ec8855dda..94d14d012da 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -93,6 +93,7 @@ CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index b645cba9070..570c4e82a47 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -79,6 +79,7 @@ CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SPL_DM_RTC=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_TPM_TIS_LPC=y CONFIG_USB_STORAGE=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 541b7fadead..43cf53045b4 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -68,6 +68,7 @@ CONFIG_SYS_I2C_INTEL=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SPI=y CONFIG_TPM_TIS_LPC=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index ca453ac8b9d..08e1e5be415 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -96,6 +96,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_ROCKCHIP=y diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index 27bf046f991..aa3d6f2b9d1 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -70,6 +70,7 @@ CONFIG_SYS_I2C_DW=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_SOUND_RT5677=y diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index e9222648758..77735739b82 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -91,6 +91,7 @@ CONFIG_CROS_EC_LPC=y # CONFIG_SPL_PINCTRL is not set # CONFIG_TPL_PINCTRL is not set CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_SOUND_RT5677=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 92018fb78ee..d5aaee9dde1 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -95,6 +95,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index b78e98c2045..e83f2dfe7f3 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -59,6 +59,7 @@ CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_RTL8169=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_TPM_TIS_LPC=y CONFIG_USB_STORAGE=y diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 0d904675f73..31979f32bc5 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -69,6 +69,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 6fed3f2ecda..18d58bec201 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 20c0c181696..e4da59bae92 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -61,6 +61,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index d8c5be66ad7..e297494663e 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -55,6 +55,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 094b21666e1..203eff8e165 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -53,6 +53,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 4521172f42b..cb0f0d7c8d0 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -57,6 +57,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_SPI=y diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index 5eea1ec9a72..71c57ed5aba 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -66,7 +66,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index 16a866f6b47..6c35f31a29d 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -59,7 +59,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index 6c805f41568..a17d01f3fd2 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -55,7 +55,8 @@ CONFIG_MTD_RAW_NAND=y CONFIG_PHY_MARVELL=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 86fe0692a0a..6deb05575c1 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -62,7 +62,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index 93aef472b54..9088fffb25e 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -56,7 +56,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index 5abdadf2d56..c364c9ecc8d 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig index 83f532d6e54..8d1fc22eb93 100644 --- a/configs/efi-x86_payload32_defconfig +++ b/configs/efi-x86_payload32_defconfig @@ -52,6 +52,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y # CONFIG_GZIP is not set CONFIG_EFI=y CONFIG_EFI_STUB=y diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig index 28aaff69e97..89e6d1febc8 100644 --- a/configs/efi-x86_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -52,6 +52,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y # CONFIG_GZIP is not set CONFIG_EFI=y CONFIG_EFI_STUB=y diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig index 1f4ca01c50f..36f57d58128 100644 --- a/configs/elgin-rv1108_defconfig +++ b/configs/elgin-rv1108_defconfig @@ -48,6 +48,7 @@ CONFIG_PINCTRL_ROCKCHIP_RV1108=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 6bc777c51c1..bb6f21b2e63 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -101,6 +101,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index f41c7580b4c..2e3bff8cf04 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -78,6 +78,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_PANIC_HANG=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 8ef40d847c7..289f47f4ae8 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -55,6 +55,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y # CONFIG_SPL_DM_SERIAL is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y # CONFIG_SPL_SYSRESET is not set CONFIG_USB=y diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index ce10750857e..06a044b9349 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -46,6 +46,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index f8ca1f6597b..33202e48fe7 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -72,6 +72,7 @@ CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_GADGET=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 7c0b856ca56..8f8d34c7038 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -81,6 +81,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index 8502fcc51e6..0aeaf01d9a7 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -74,6 +74,7 @@ CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 9421845b037..8a6d19a1769 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -88,6 +88,7 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index e7da9c4e5ff..3050fd59922 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -61,6 +61,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index db3acf5be53..7374ee42fb1 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -63,5 +63,6 @@ CONFIG_SPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 5de5de465cb..aab32231116 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -42,6 +42,7 @@ CONFIG_PINCTRL=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index d48dcc1a0ec..3aee6b64713 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -55,6 +55,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 1f91118426e..2a6d2edbab0 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_DM_RESET=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 63c53a0248f..26967a67cc9 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -78,6 +78,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index a37870628c6..54751725328 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -61,6 +61,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig index 1d7832b9591..c23d0549a4a 100644 --- a/configs/geekbox_defconfig +++ b/configs/geekbox_defconfig @@ -27,5 +27,6 @@ CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index 6fdb3ea6800..8ee11833095 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -62,7 +62,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index 794cf4b23d7..1889743f081 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -61,7 +61,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/hsdk_4xd_defconfig b/configs/hsdk_4xd_defconfig index 8c6ad5a0d17..bba40672685 100644 --- a/configs/hsdk_4xd_defconfig +++ b/configs/hsdk_4xd_defconfig @@ -60,6 +60,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index 9543c785bba..4715f9d9d7d 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 9290cb7af68..beee58962a5 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -59,7 +59,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index ce5a089d327..f536dd3bcb5 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -59,7 +59,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 42f812c31f0..1fa1a5afa78 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -66,7 +66,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 25007793b3a..96bcba6e94f 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -92,6 +92,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index 6c8a284e7c7..0d1c97dd4b0 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -67,6 +67,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 6182101f119..bded0978802 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -96,6 +96,7 @@ CONFIG_KEYSTONE_USB_PHY=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index fd169c3e957..a851d850822 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -70,6 +70,7 @@ CONFIG_NOP_PHY=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index fec29f2c911..b0069fd60b0 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -92,6 +92,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index f6ac484f2e8..9ca26ae61f5 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -67,6 +67,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 13d612ac3fb..153abb7eb93 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -93,6 +93,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 59ec3a6346f..2990a702d99 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -71,6 +71,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index dff05223084..754fd4e3c6d 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -56,6 +56,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 5a8b69c0f94..7518f7f2ede 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -55,6 +55,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index f54a610a274..4c4301a9e7c 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -56,6 +56,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 1ad635daa98..646f0086c6e 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -60,6 +60,7 @@ CONFIG_PINCTRL=y CONFIG_DM_REGULATOR_FIXED=y # CONFIG_SPL_DM_SERIAL is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y # CONFIG_SPL_SYSRESET is not set CONFIG_USB=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index a8326f03a23..5a958ee36a3 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 1ace7b795a0..ee401b763d9 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -97,6 +97,7 @@ CONFIG_TPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index dbb0ce0221f..b551f5bdee0 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -60,7 +60,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index a8b4ce2bab9..21ccc555739 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -58,7 +58,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 1a4fc999db7..f1c9169a72d 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -58,7 +58,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index 7e9076a1f99..f40ede127b5 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -56,7 +56,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index 7bfe1f7cae5..ff5e323d57c 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -61,7 +61,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index 2327d892437..3b073241e45 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -64,7 +64,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 250440a70ac..238886d0dfd 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -59,7 +59,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index f1600c4005b..ccd8fb9801f 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -62,7 +62,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index e4a26dc0ab2..fcef5e5d5bb 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -85,7 +85,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index c9fa1099303..c2996a1372e 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -75,7 +75,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 773a3e6b2b6..a1709f4525b 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -84,7 +84,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index c9f0635de17..3639b4dd93d 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -65,7 +65,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index c1c21cb187c..4fc7b387346 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -67,7 +67,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 503fe95c88d..f162111d0be 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -63,7 +63,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 727d10ffaaa..cc640461cf4 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -64,7 +64,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 72129a70a8c..e6cd6a7d19c 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -68,7 +68,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index c67f329f92e..d5d33544570 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -98,7 +98,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0xf40000 CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 14aa19fe726..c3c6678bb49 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -130,7 +130,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 2f1b41f0686..40228acaa89 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -96,7 +96,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 1c38d99dfca..ebf6fdb463c 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -84,7 +84,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 4a642f4a6c2..07d52c249d0 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -127,7 +127,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 1b5d8229c66..6834a696b63 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -112,7 +112,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 877a771b51c..e5e732a5086 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -69,7 +69,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 9695164a93f..29dc23e179e 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -96,7 +96,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 290d53f852c..86060806fe4 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -80,7 +80,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index b3a93179c22..ed7e91e9b5f 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -77,7 +77,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index cb3d1580d35..f84f4dd6609 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -112,7 +112,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index c53827c6376..40a0ea70325 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -111,7 +111,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 46ab9a26f0f..621a0238d44 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -105,7 +105,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 753583d47b4..525c7df6d0f 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -86,7 +86,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index b5e243bc0e9..dde204eaa0d 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -92,7 +92,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index fad07863db5..b8df245025f 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -80,7 +80,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 20354f7e86b..5b1cf988cf0 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -86,7 +86,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 9b3c77fe56b..a7e9583c735 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -99,7 +99,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 29cbac31354..774d41308ba 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -130,7 +130,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 21bb036ee8c..f759baf36db 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -100,7 +100,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index fd7f3bb69b3..e7dbf41b972 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -89,7 +89,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 14931f72197..627abc81c9c 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -127,7 +127,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 22844636e27..f4dcbd4a926 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -115,7 +115,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index b75c75230fc..307fbfcbb7d 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -98,7 +98,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 21199b9d068..667fc2123a2 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -107,7 +107,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index df227d80371..7d980c3c469 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -86,7 +86,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 0e2fa0284dc..b345d13caa0 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -89,7 +89,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 6b9971f138a..d4546348bbd 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -110,7 +110,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 0aa046a425b..f0f8cbf34e0 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -117,7 +117,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index a6c33de3971..529cd93bd24 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -110,7 +110,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index ddf280a5628..bfe9260d1b7 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -115,7 +115,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index 7ca5457c2d2..391e95a48d5 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -84,7 +84,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index 5fe6bae3a1b..2ebde25bd93 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -90,7 +90,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index 7d9f5330016..0df5b85869b 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -67,7 +67,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 03e944fa7a1..a095bbcb82e 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -76,7 +76,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index e9cf20d5f74..2bf8a949256 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -98,7 +98,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 0e2f4094f79..5fe73bc8ac7 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -101,7 +101,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 75851ad390d..7c8a1e70fad 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -130,7 +130,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 552bb43f7a1..937581536af 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -91,7 +91,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 312464484da..4d3c0580a1b 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -130,7 +130,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 344899ef6f2..480ab037953 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -118,7 +118,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 0a363533ff2..a0d57b19354 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -99,7 +99,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 26fc4592a96..e08af4d1a2c 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -109,7 +109,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index d9c716ebabd..1a09fdadd3b 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -111,7 +111,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index 61b7244ff22..346a954760f 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -86,7 +86,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 05115ea71e4..4361cd223db 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -90,7 +90,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index ac2cede0d3d..560362695ff 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -119,7 +119,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 6074b6b3142..cdcfa63bf45 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -109,7 +109,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 07b077767ac..e0442390db0 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -111,7 +111,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 2432154f77b..da6c2431bf7 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -79,7 +79,7 @@ CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 0aa2792c3c4..f9aab31acff 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -85,7 +85,7 @@ CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index 8556c003555..aecd74d15b9 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -101,7 +101,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index d4f2268041f..8d1fc5f2041 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -93,7 +93,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index af63278bb3c..7c6e6b7637c 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -96,7 +96,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 6b42170ffbd..64296dbe0b2 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -121,7 +121,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index dedefb3a0a3..2b4712e07e3 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -116,7 +116,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 60f26f01830..c8ab5723539 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -118,7 +118,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index a819ebfefff..18213e5cc5c 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -89,7 +89,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index c5697533381..eb88cec6e02 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -92,7 +92,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 2b96382f248..33aedcfbd20 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -111,7 +111,7 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 42636353840..db28ae196f6 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -112,7 +112,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 2e812943fd3..0ec80be2ea6 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -90,7 +90,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 9c12f2be9ce..27323be4089 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -96,7 +96,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 817ae8d728b..f66f5298366 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -96,7 +96,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index b3e75847cca..d601c083e28 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -99,7 +99,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index effcd33629b..e2b6044d1fa 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -112,7 +112,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index eb57948414d..8abd58d53eb 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -92,7 +92,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index e5702b81592..389b32b2d6d 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -106,7 +106,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index face1e05320..e4d15dda14d 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -94,7 +94,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index ba6f5090d47..4030fd4693b 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -97,7 +97,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 50002900303..b6e154b78b5 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -116,7 +116,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index 58bae66baa0..fc43c535b5c 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -86,7 +86,7 @@ CONFIG_RTC_PCF8563=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 9c6012460b3..09df15154e7 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -112,7 +112,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 6e1fe901ff4..8cdfe5cc0bd 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -82,7 +82,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 8441814f13f..84c9f152665 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -89,7 +89,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index dc9a47463f4..3ac03305c7a 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -100,7 +100,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 36109856809..41891d83ace 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -108,7 +108,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig index 054c5e6d618..b635c651aae 100644 --- a/configs/malta64_defconfig +++ b/configs/malta64_defconfig @@ -45,3 +45,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig index 55f624bbeeb..243213cb819 100644 --- a/configs/malta64el_defconfig +++ b/configs/malta64el_defconfig @@ -47,3 +47,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/malta_defconfig b/configs/malta_defconfig index 53762a94e2a..ed41e298f44 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -44,3 +44,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index 8b86d74dc41..63e5fcb6a5c 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -46,3 +46,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 66f3036313c..52ed763424a 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -65,6 +65,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_RTL8169=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 0811e70dcef..9346cafc64c 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -75,6 +75,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig index 403a84befdc..7ba8338add5 100644 --- a/configs/mk808_defconfig +++ b/configs/mk808_defconfig @@ -99,6 +99,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_SYSRESET=y CONFIG_TIMER=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 03fa857996c..8fad8c643f2 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -55,6 +55,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index 67ca98563b5..c5f13c060be 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index afa51bc8fa3..b6a604b6943 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index d02eb1851a7..767befe2d2c 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index d2d9bf91c56..383ec1f39ee 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 82264de9088..40d3117b4f0 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -91,6 +91,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index 2185f87d7d0..40a45a0f4bb 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -52,6 +52,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index 9cebc704ce9..0590fc95c47 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -63,7 +63,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index c10e1a50139..b3278142c83 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -67,7 +67,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 75907e05c57..dfdb06b2378 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -67,7 +67,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index db08ca57633..995c0ccb1b7 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -67,7 +67,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index dda3b6b5f93..877a39cfa7c 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -65,7 +65,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 21534c59fde..24f7d8b4bce 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -67,7 +67,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index afa0cad0418..e7d6ffd9259 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -53,7 +53,8 @@ CONFIG_MTD_RAW_NAND=y CONFIG_PHY_MARVELL=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_UBIFS_SILENCE_MSG=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 4705f61e424..33adcc952cf 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -104,6 +104,7 @@ CONFIG_DM_RESET=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig index 2c4e26c290a..0cae1c61508 100644 --- a/configs/omap4_panda_defconfig +++ b/configs/omap4_panda_defconfig @@ -46,7 +46,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OMAP3=y diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig index 2315a84285e..e15c6d5cb13 100644 --- a/configs/omap4_sdp4430_defconfig +++ b/configs/omap4_sdp4430_defconfig @@ -43,7 +43,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_OMAP3=y CONFIG_USB_GADGET=y diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index bd0ede759cb..d12199766ad 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -56,7 +56,7 @@ CONFIG_PALMAS_POWER=y CONFIG_SCSI=y CONFIG_SCSI_AHCI_PLAT=y CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_DWC3=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index c2e879c9bde..45bd307a1c4 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -61,6 +61,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index 01bfaed978b..9c9f6c463d6 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -62,6 +62,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index 7c641038178..fbcdf4b3630 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -62,6 +62,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 39245e8784b..0980d815696 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 8a274187d09..0632a928bc0 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -78,6 +78,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 528b7bb69f2..dfbf5e70f4a 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -80,6 +80,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index d0071f3af52..116e5d0ed3e 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -55,7 +55,8 @@ CONFIG_MTD_RAW_NAND=y CONFIG_PHY_MARVELL=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig index 3b08cb7b1d1..018c2f50331 100644 --- a/configs/pogo_v4_defconfig +++ b/configs/pogo_v4_defconfig @@ -74,7 +74,8 @@ CONFIG_PCI=y CONFIG_PCI_MVEBU=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index f6c49da574c..91123784b54 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -75,6 +75,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index c2b0b39c7b2..9a5be3e9139 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -92,6 +92,7 @@ CONFIG_DM_RESET=y CONFIG_DM_RTC=y CONFIG_RTC_ISL1208=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index 9175c7c85ae..9c36750bde0 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index 0aa7cca7b8b..db1ceaa31f3 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index d731b968788..d2cca48304d 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 8433b5734f6..0f4811e5d7a 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -70,6 +70,7 @@ CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y CONFIG_SPL_DM_RTC=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index f82f628d5bb..a8222122fc9 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -50,6 +50,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 670211e2e9d..0a029c4098f 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -74,6 +74,7 @@ CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 7f1259d82c1..8172ed0ad22 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -95,6 +95,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 3cdcc729f85..6827c98ed9f 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -71,6 +71,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index e03442afa46..cf4a58de1c5 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -68,6 +68,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 83721cedf3d..54a400405be 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -62,6 +62,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index ac9a3f98306..e74ba07e446 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -62,6 +62,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index c0c1ebf3402..0ffb073f313 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -96,6 +96,7 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index fcb3a681ca0..2443f292469 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -63,6 +63,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig index 4ed98c0a511..18c6d1b9225 100644 --- a/configs/rock-pi-n8-rk3288_defconfig +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -74,6 +74,7 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 38a5f3a80c0..54d01456b1e 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -77,6 +77,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index e75011bee5f..73a4f06eb9b 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -92,6 +92,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 6ed5ef868e5..f2c914f41f5 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock_defconfig b/configs/rock_defconfig index bd6183ba5b8..26638405bf7 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -63,6 +63,7 @@ CONFIG_REGULATOR_ACT8846=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_SYSRESET=y CONFIG_TIMER=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index ba48d021f4f..5b8d678f6bb 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -79,6 +79,7 @@ CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig index 01f104a97d0..40cd91c045c 100644 --- a/configs/sheep-rk3368_defconfig +++ b/configs/sheep-rk3368_defconfig @@ -29,5 +29,6 @@ CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 52f5aba8cab..79f36c03604 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -65,7 +65,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig index b6b9f88c00b..f5d16f64d73 100644 --- a/configs/slimbootloader_defconfig +++ b/configs/slimbootloader_defconfig @@ -31,5 +31,6 @@ CONFIG_SYSCON=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_CONSOLE_SCROLL_LINES=5 # CONFIG_GZIP is not set diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig index 68440926c07..9269eccf17a 100644 --- a/configs/socfpga_agilex_atf_defconfig +++ b/configs/socfpga_agilex_atf_defconfig @@ -82,6 +82,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index de9ebd07226..48fb0672232 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -75,6 +75,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index 7642498ea9c..da4545effff 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -83,6 +83,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 08ae6c502b4..4e2dc0c9857 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -62,6 +62,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig index 478efc59ea9..00c4cf30089 100644 --- a/configs/socfpga_chameleonv3_defconfig +++ b/configs/socfpga_chameleonv3_defconfig @@ -29,6 +29,7 @@ CONFIG_FS_LOADER=y CONFIG_SPL_FS_LOADER=y CONFIG_MMC_DW=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_DESIGNWARE_APB_TIMER=y diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig index 0feda3b04f7..4d856d535a3 100644 --- a/configs/socfpga_n5x_atf_defconfig +++ b/configs/socfpga_n5x_atf_defconfig @@ -81,6 +81,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index fa19f555f20..1056932cd35 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -72,6 +72,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index 12e8ebf0138..a6714b265e1 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -82,6 +82,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index 5ee9f5ff9da..e0e6b2d0461 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -83,6 +83,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index f689105695c..919863270f8 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -80,6 +80,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index 5d401e6c2d7..5b724697123 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -60,6 +60,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/ten64_tfa_defconfig b/configs/ten64_tfa_defconfig index 48b2ffc7521..0209f62d2f5 100644 --- a/configs/ten64_tfa_defconfig +++ b/configs/ten64_tfa_defconfig @@ -81,7 +81,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_RX8025=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index 22544c0913a..440c170c6b1 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index 8741ecbb2d7..b91c3b13547 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -64,6 +64,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig index 47dbf342776..bab7b29bf89 100644 --- a/configs/ti816x_evm_defconfig +++ b/configs/ti816x_evm_defconfig @@ -77,6 +77,6 @@ CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000 CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y # CONFIG_USE_PRIVATE_LIBGCC is not set diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 85d94a6ea89..5976a84491e 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -83,6 +83,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 7dfbad80838..078f829c2df 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -83,6 +83,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index cbae60f9876..0c9d61b8053 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -83,6 +83,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig index 31483296802..c58514669dd 100644 --- a/configs/xtfpga_defconfig +++ b/configs/xtfpga_defconfig @@ -45,6 +45,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=1027 CONFIG_PHYLIB=y CONFIG_ETHOC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SYSRESET=y CONFIG_OF_LIBFDT=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index de02e08a299..4978a65715b 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -720,6 +720,17 @@ config PIC32_SERIAL help Support for the UART found on Microchip PIC32 SoC's. +config SYS_NS16550_SERIAL + bool "NS16550 UART or compatible legacy driver" + depends on !DM_SERIAL + select SYS_NS16550 + +config SPL_SYS_NS16550_SERIAL + bool "NS16550 UART or compatible legacy driver in SPL" + depends on SPL && !SPL_DM_SERIAL + default y if SYS_NS16550_SERIAL || ARCH_SUNXI || ARCH_OMAP2PLUS + select SYS_NS16550 + config SYS_NS16550 bool "NS16550 UART or compatible" help @@ -732,25 +743,52 @@ config SYS_NS16550 config NS16550_DYNAMIC bool "Allow NS16550 to be configured at runtime" + depends on SYS_NS16550 default y if SYS_COREBOOT || SYS_SLIMBOOTLOADER help Enable this option to allow device-tree control of the driver. Normally this driver is controlled by the following options: - CONFIG_SYS_NS16550_PORT_MAPPED - indicates that port I/O is used for - access. If not enabled, then the UART is memory-mapped. - CONFIG_SYS_NS16550_MEM32 - if memory-mapped, indicates that 32-bit - access should be used (instead of 8-bit) - CONFIG_SYS_NS16550_REG_SIZE - indicates register width and also - endianness. If positive, big-endian access is used. If negative, - little-endian is used. - It is not a good practice for a driver to be statically configured, since it prevents the same driver being used for different types of UARTs in a system. This option avoids this problem at the cost of a slightly increased code size. +config SYS_NS16550_MEM32 + bool "If memory-mapped, 32bit access is needed for ns16550 register access" + depends on SYS_NS16550 + help + If enabled, if memory-mapped, indicates that 32-bit access should be + used (instead of 8-bit) for register access. + +config SYS_NS16550_PORT_MAPPED + bool "Port I/O is used for ns16550 register access" + depends on SYS_NS16550 + help + If enabled, port I/O is used for ns16550 register access. If not + enabled, then the UART is memory-mapped. + +config SYS_NS16550_REG_SIZE + int "ns16550 register width and endianness" + depends on SYS_NS16550_SERIAL || SPL_SYS_NS16550_SERIAL + range -4 4 + default -4 if ARCH_OMAP2PLUS || ARCH_SUNXI + default 1 + help + Indicates register width and also endianness. If positive, big-endian + access is used. If negative, little-endian is used. + +config SPL_NS16550_MIN_FUNCTIONS + bool "Only provide NS16550_init and NS16550_putc in SPL" + depends on SPL_SYS_NS16550_SERIAL && PPC + help + Enable this if you desire to only have use of the NS16550_init and + NS16550_putc functions for the serial driver located at + drivers/serial/ns16550.c. This option is useful for saving space for + already greatly restricted images, including but not limited to + NAND_SPL configurations. + config INTEL_MID_SERIAL bool "Intel MID platform UART support" depends on DM_SERIAL && OF_CONTROL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index eb7b8f23ee9..45cf94c74c6 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,7 +25,7 @@ ifdef CONFIG_DM_SERIAL obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o else obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o -obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o +obj-$(CONFIG_$(SPL_)SYS_NS16550_SERIAL) += serial_ns16550.o endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index afd7cc89bf8..719caf7b0c3 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -15,7 +15,6 @@ /* * SERIAL */ -#define CONFIG_SYS_NS16550_MEM32 /* * Flash diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index c4cde1cc512..b8cbdc36754 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -151,8 +151,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b241939fc38..dba15dae749 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -235,8 +235,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 9afd834f9fa..fd721f30b3a 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -322,10 +322,7 @@ extern unsigned long get_sdram_size(void); /* Serial Port */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SPL_NS16550_MIN_FUNCTIONS #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b9311fc5e4f..173f6205e08 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -163,8 +163,6 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 9629d735a27..c99e6ba781a 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -12,8 +12,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 67e42b94c11..8b43fe0c993 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -12,8 +12,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 978cc6714ec..7cb10b205db 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -294,8 +294,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index f26e9d6e869..3fa2d01dcc2 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -267,8 +267,6 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 62f07108126..c5a28fadb00 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -269,8 +269,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 0616f8a86df..795120c02a8 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -229,8 +229,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 2eb4e73efa9..e3cbc649fa1 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -89,8 +89,6 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index a0951fbf623..b61c8005c33 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -15,10 +15,6 @@ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_CLK 48000000 -#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_SERIAL -#endif /* I2C Configuration */ diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index cf5125fdfa6..7224bd8d1f4 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -33,10 +33,6 @@ /* * Serial console configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#endif #define CONFIG_SYS_NS16550_CLK 19660800 /* Init Stack Pointer */ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index f2357b5785a..c0429ae15c4 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -26,9 +26,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33333333 -#define CONFIG_SYS_NS16550_MEM32 /* * Ethernet PHY configuration diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 5aa720da3d7..481baff11d9 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -97,8 +97,6 @@ extern phys_addr_t prior_stage_fdt_address; */ #define V_NS16550_CLK 81000000 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index a6de28a42b2..773ce3f6a6f 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -14,8 +14,6 @@ /* legacy #defines for non DM bur-board */ #ifndef CONFIG_DM -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 diff --git a/include/configs/chromebook_coral.h b/include/configs/chromebook_coral.h index 0eeea80b32f..d14c1d445b2 100644 --- a/include/configs/chromebook_coral.h +++ b/include/configs/chromebook_coral.h @@ -18,7 +18,4 @@ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" -#define CONFIG_SYS_NS16550_MEM32 -#undef CONFIG_SYS_NS16550_PORT_MAPPED - #endif /* __CONFIG_H */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 9061eba6686..0641d5c0a23 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -14,12 +14,8 @@ #include /* Serial support */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_COM1 0x44e09000 -#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif /* NAND support */ #define CFG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index 4297047e8ce..52f2d50118a 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -14,7 +14,6 @@ #ifndef CONFIG_INTERNAL_UART /* Use BayTrail internal HS UART which is memory-mapped */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED #endif #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ diff --git a/include/configs/galileo.h b/include/configs/galileo.h index 545408a4baa..472f236b9b6 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -13,7 +13,6 @@ #include /* ns16550 UART is memory-mapped in Quark SoC */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 965fa87c657..0d61724db8c 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -20,9 +20,7 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 0xb0000c00 #endif diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index 4af845ea9c2..bfc0fa5c442 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -28,9 +28,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33330000 -#define CONFIG_SYS_NS16550_MEM32 /* * Ethernet PHY configuration diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 0ce65e7755e..ce3cb20732d 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -27,9 +27,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33330000 -#define CONFIG_SYS_NS16550_MEM32 /* * Ethernet PHY configuration diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index cc8c37ec0bf..7acdb0fa038 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -148,7 +148,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK get_serial_clock() /* diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 16fd6d562d4..30ba6065253 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -330,8 +330,6 @@ * Retain non-DM serial port for debug purposes. */ #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) #endif diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index f0ae9248af3..5434c4f7679 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -36,7 +36,6 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 9eedd47c07e..b9c853d7dfe 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -20,9 +20,7 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM3 0xb0000e00 #endif diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 77f84e1c9ea..148598fab46 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -26,8 +26,6 @@ /* GPIO */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_HWCONFIG diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 885774f63d4..3f2dfa640c9 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -47,8 +47,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() /* diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 6b23134ecc9..bd2f74c1262 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -227,10 +227,6 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index fce91192dff..8c43f652ab6 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -60,10 +60,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() /* I2C */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 1ac59a2d459..06830f401a3 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -145,10 +145,6 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 43dbeea1b3b..7dd5649005b 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -28,8 +28,6 @@ /* I2C */ /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) /* Miscellaneous configurable options */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 47367845a07..2fc06c1dd2d 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -40,8 +40,6 @@ #define CPU_RELEASE_ADDR secondary_boot_addr /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) /* SD boot SPL */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 07ec2c95637..40b4cb964d1 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -40,8 +40,6 @@ #define CPU_RELEASE_ADDR secondary_boot_addr /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) /* SD boot SPL */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index dec661d6b19..5668e07d135 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -45,8 +45,6 @@ /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) /* diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index d8997208e97..895c566fea2 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -37,8 +37,6 @@ /* I2C */ /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) /* diff --git a/include/configs/malta.h b/include/configs/malta.h index 30c2e41eec5..2dd34ea7313 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -33,7 +33,6 @@ /* * Serial driver */ -#define CONFIG_SYS_NS16550_PORT_MAPPED /* * Flash configuration diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 9b1ba3655e8..1f733d112dd 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -22,9 +22,7 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 50000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 0xbe000c00 #endif diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index 43527017d84..da16e3b21a4 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -14,9 +14,7 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 0xb0000c00 #endif diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index c93d70ddf1a..eaffe0bf4c9 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -12,9 +12,6 @@ #include -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_COM1 0x11005200 #define CONFIG_SYS_NS16550_CLK 26000000 diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index 7228f3e4288..347598868bb 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -12,9 +12,6 @@ #include -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_COM1 0x11005000 #define CONFIG_SYS_NS16550_CLK 26000000 diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 6d4fff3820c..4f1067c23bb 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -32,10 +32,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 99a020c3c71..310bdde7cb5 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -40,7 +40,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 838c62c6711..065820689ca 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -319,10 +319,7 @@ * shorted - index 1 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SPL_NS16550_MIN_FUNCTIONS #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 49d1878ebdd..8b151ef1883 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -8,8 +8,6 @@ #include "rockchip-common.h" -#define CONFIG_SYS_NS16550_MEM32 - /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ #define CONFIG_IRAM_BASE 0xff020000 diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 200b34b35ba..263d1bd180c 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -8,8 +8,6 @@ #include "rockchip-common.h" -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_IRAM_BASE 0xfff80000 #define CONFIG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 4c964cc3770..1f6b82f2d02 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -7,8 +7,6 @@ #define _ROCKCHIP_COMMON_H_ #include -#define CONFIG_SYS_NS16550_MEM32 - /* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */ #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index d071f590f10..5765f2ccb5e 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -38,7 +38,6 @@ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 #define CONFIG_SYS_NS16550_COM4 0x481a6000 diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 0187fca5f0d..c29bc448eed 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -52,11 +52,6 @@ * Serial */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif - #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index f712928d3c8..49883ea7a3c 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -18,7 +18,6 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} /* diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h index 75d2081fac8..7012097276c 100644 --- a/include/configs/socfpga_chameleonv3.h +++ b/include/configs/socfpga_chameleonv3.h @@ -17,7 +17,6 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 86cc3771ba5..029f898b64f 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -76,7 +76,6 @@ * Serial / UART configurations */ #define CONFIG_SYS_NS16550_CLK 100000000 -#define CONFIG_SYS_NS16550_MEM32 /* * SDMMC configurations diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index d9e4c8b699f..1ed0a262bc6 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -16,7 +16,6 @@ #include /* Serial & console */ -#define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ #ifdef CONFIG_MACH_SUNIV /* suniv doesn't have apb2 and uart is connected to apb1 */ @@ -25,7 +24,6 @@ #define CONFIG_SYS_NS16550_CLK 24000000 #endif #ifndef CONFIG_DM_SERIAL -# define CONFIG_SYS_NS16550_REG_SIZE -4 # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE # define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 16bdc39b750..38a43b726f0 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -19,7 +19,6 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 166666666 /* diff --git a/include/configs/theadorable-x86-dfi-bt700.h b/include/configs/theadorable-x86-dfi-bt700.h index bb3186e2192..663a49e7b6c 100644 --- a/include/configs/theadorable-x86-dfi-bt700.h +++ b/include/configs/theadorable-x86-dfi-bt700.h @@ -13,7 +13,6 @@ #include /* Use BayTrail internal HS UART which is memory-mapped */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED /* Set the board specific parameters */ #define DEF_ENV_TFTPDIR "theadorable-x86-dfi" diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 97166e010f7..60632c58c67 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -77,8 +77,6 @@ #define CONFIG_SYS_TIMERBASE 0x4802E000 /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index efd3a0db04e..f2dbe3544a5 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -30,8 +30,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 5d5df6b1019..fb017771688 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -17,12 +17,6 @@ #include /* NS16550 Configuration */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif -#endif #define CONFIG_SYS_NS16550_CLK 48000000 /* diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index a4a45fad9dc..aaeea77281b 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -34,7 +34,6 @@ #define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) /* UART Configuration */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 6cc443c8e9c..80d2a011f0f 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -27,10 +27,6 @@ /* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif /* !CONFIG_DM_SERIAL */ #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 0568946fc82..eb930341c3a 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -29,8 +29,6 @@ */ #define CONFIG_SYS_NS16550_CLK 48000000 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM3 UART3_BASE #endif diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 24bbf9e7c2c..a1efb57f1b0 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -30,10 +30,6 @@ * Hardware drivers */ #define CONFIG_SYS_NS16550_CLK 48000000 -#if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif /* * Environment setup diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 6f36d6964b9..84e5ba39f14 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -19,9 +19,7 @@ #define CONFIG_SYS_UBOOT_BASE 0 /* Serial SPL */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM3 0xb0000e00 /* RAM */ diff --git a/include/configs/x530.h b/include/configs/x530.h index 0add626e81a..318e3680a6e 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -13,10 +13,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 8e22d6e5d87..f76c1f8be0f 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -21,7 +21,6 @@ /*----------------------------------------------------------------------- * Serial Configuration */ -#define CONFIG_SYS_NS16550_PORT_MAPPED /* * Miscellaneous configurable options diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 58d01f4bb42..7090fcef680 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -127,8 +127,6 @@ /* Serial Driver Info */ /*====================*/ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ diff --git a/include/ns16550.h b/include/ns16550.h index 3d9002d9f15..0ee5c4d6de7 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -26,7 +26,7 @@ #include -#ifdef CONFIG_DM_SERIAL +#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_SYS_NS16550_REG_SIZE) /* * For driver model we always use one byte per register, and sort out the * differences in the driver -- cgit v1.3.1 From 91092132bac0ae768beb76c12ef8be732ea6ba3a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:28 -0500 Subject: global: Move remaining CONFIG_SYS_NS16550_* to CFG_SYS_NS16550_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +- arch/arm/include/asm/arch-bcmcygnus/configs.h | 6 +- arch/arm/include/asm/arch-bcmnsp/configs.h | 4 +- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 8 +-- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 +- arch/arm/include/asm/arch-lpc32xx/config.h | 4 +- arch/arm/include/asm/arch-ls102xa/config.h | 4 +- arch/arm/mach-davinci/da850_lowlevel.c | 6 +- arch/arm/mach-davinci/spl.c | 4 +- arch/arm/mach-keystone/init.c | 4 +- arch/arm/mach-lpc32xx/devices.c | 8 +-- arch/arm/mach-omap2/am33xx/board.c | 32 +++++------ arch/arm/mach-tegra/board.c | 4 +- arch/powerpc/cpu/mpc85xx/fdt.c | 12 ++-- arch/powerpc/include/asm/config.h | 2 +- board/Synology/ds109/ds109.c | 10 ++-- board/eets/pdu001/mux.c | 12 ++-- board/emulation/qemu-ppce500/qemu-ppce500.c | 2 +- board/freescale/p1010rdb/p1010rdb.c | 2 +- board/freescale/p1010rdb/spl.c | 2 +- board/freescale/p1010rdb/spl_minimal.c | 6 +- board/freescale/p1_p2_rdb_pc/spl.c | 2 +- board/freescale/p1_p2_rdb_pc/spl_minimal.c | 6 +- board/freescale/t102xrdb/spl.c | 2 +- board/freescale/t104xrdb/spl.c | 2 +- board/freescale/t208xqds/spl.c | 2 +- board/freescale/t208xrdb/spl.c | 2 +- board/freescale/t4rdb/spl.c | 2 +- board/nokia/rx51/rx51.c | 4 +- drivers/serial/Kconfig | 2 +- drivers/serial/ns16550.c | 8 +-- drivers/serial/serial_mtk.c | 40 +++++++------- drivers/serial/serial_ns16550.c | 64 +++++++++++----------- drivers/serial/serial_omap.c | 6 +- include/configs/MPC837XERDB.h | 6 +- include/configs/MPC8548CDS.h | 6 +- include/configs/P1010RDB.h | 6 +- include/configs/P2041RDB.h | 10 ++-- include/configs/SBx81LIFKW.h | 4 +- include/configs/SBx81LIFXCAT.h | 4 +- include/configs/T102xRDB.h | 10 ++-- include/configs/T104xRDB.h | 10 ++-- include/configs/T208xQDS.h | 10 ++-- include/configs/T208xRDB.h | 10 ++-- include/configs/T4240RDB.h | 10 ++-- include/configs/am335x_evm.h | 12 ++-- include/configs/am335x_guardian.h | 12 ++-- include/configs/am335x_igep003x.h | 2 +- include/configs/am335x_shc.h | 12 ++-- include/configs/am335x_sl50.h | 12 ++-- include/configs/am43xx_evm.h | 4 +- include/configs/am57xx_evm.h | 6 +- include/configs/ap143.h | 2 +- include/configs/ap152.h | 2 +- include/configs/apalis-tk1.h | 2 +- include/configs/apalis_t30.h | 2 +- include/configs/ax25-ae350.h | 2 +- include/configs/axs10x.h | 2 +- include/configs/baltos.h | 12 ++-- include/configs/bcm7260.h | 2 +- include/configs/bcm7445.h | 2 +- include/configs/bcm_ns3.h | 2 +- include/configs/bcmstb.h | 2 +- include/configs/beaver.h | 2 +- include/configs/bur_am335x_common.h | 4 +- include/configs/cardhu.h | 2 +- include/configs/cei-tk1-som.h | 2 +- include/configs/chiliboard.h | 12 ++-- include/configs/ci20.h | 2 +- include/configs/cm_t43.h | 4 +- include/configs/colibri_t20.h | 2 +- include/configs/colibri_t30.h | 2 +- include/configs/da850evm.h | 2 +- include/configs/dalmore.h | 2 +- include/configs/dra7xx_evm.h | 6 +- include/configs/gardena-smart-gateway-mt7688.h | 4 +- include/configs/harmony.h | 4 +- include/configs/hsdk-4xd.h | 2 +- include/configs/hsdk.h | 2 +- include/configs/jetson-tk1.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/kmcent2.h | 4 +- include/configs/kontron_sl28.h | 2 +- include/configs/legoev3.h | 2 +- include/configs/linkit-smart-7688.h | 4 +- include/configs/ls1012a_common.h | 2 +- include/configs/ls1021aiot.h | 2 +- include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atsn.h | 2 +- include/configs/ls1021atwr.h | 2 +- include/configs/ls1028a_common.h | 2 +- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- include/configs/ls1088a_common.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/medcom-wide.h | 2 +- include/configs/mt7621.h | 4 +- include/configs/mt7628.h | 4 +- include/configs/mt8183.h | 4 +- include/configs/mt8516.h | 4 +- include/configs/mv-common.h | 4 +- include/configs/nokia_rx51.h | 4 +- include/configs/nyan-big.h | 2 +- include/configs/omap5_uevm.h | 2 +- include/configs/omapl138_lcdk.h | 2 +- include/configs/p1_p2_rdb_pc.h | 6 +- include/configs/paz00.h | 2 +- include/configs/pdu001.h | 12 ++-- include/configs/plutux.h | 2 +- include/configs/seaboard.h | 2 +- include/configs/siemens-am33x-common.h | 6 +- include/configs/sniper.h | 4 +- include/configs/socfpga_soc64_common.h | 2 +- include/configs/sunxi-common.h | 14 ++--- include/configs/tb100.h | 2 +- include/configs/tec-ng.h | 2 +- include/configs/tec.h | 2 +- include/configs/tegra-common.h | 2 +- include/configs/ti814x_evm.h | 4 +- include/configs/ti816x_evm.h | 4 +- include/configs/ti_am335x_common.h | 2 +- include/configs/ti_armv7_keystone2.h | 8 +-- include/configs/ti_omap3_common.h | 8 +-- include/configs/ti_omap4_common.h | 4 +- include/configs/ti_omap5_common.h | 2 +- include/configs/tplink_wdr4300.h | 2 +- include/configs/trimslice.h | 2 +- include/configs/vcoreiii.h | 2 +- include/configs/venice2.h | 2 +- include/configs/ventana.h | 2 +- include/configs/vocore2.h | 4 +- include/configs/x530.h | 4 +- include/configs/xtfpga.h | 4 +- 134 files changed, 347 insertions(+), 347 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index c01cebbf985..0e7d5fa06dc 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -125,7 +125,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); + "clock-frequency", CFG_SYS_NS16550_CLK, 1); #endif sysclk_path = fdt_get_alias(blob, "sysclk"); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index ee734577fca..4f91db49eeb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -646,7 +646,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "fsl,ns16550", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); + "clock-frequency", CFG_SYS_NS16550_CLK, 1); #endif do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index 0c7262352d5..fd8dad394ad 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -11,8 +11,8 @@ /* uArchitecture specifics */ /* Serial Info */ -#define CONFIG_SYS_NS16550_CLK 100000000 -#define CONFIG_SYS_NS16550_CLK_DIV 54 -#define CONFIG_SYS_NS16550_COM3 0x18023000 +#define CFG_SYS_NS16550_CLK 100000000 +#define CFG_SYS_NS16550_CLK_DIV 54 +#define CFG_SYS_NS16550_COM3 0x18023000 #endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h index 44699476b08..0d4baf3c007 100644 --- a/arch/arm/include/asm/arch-bcmnsp/configs.h +++ b/arch/arm/include/asm/arch-bcmnsp/configs.h @@ -11,7 +11,7 @@ /* uArchitecture specifics */ /* Serial Info */ -#define CONFIG_SYS_NS16550_CLK 0x03b9aca0 -#define CONFIG_SYS_NS16550_COM1 0x18000300 +#define CFG_SYS_NS16550_CLK 0x03b9aca0 +#define CFG_SYS_NS16550_COM1 0x18000300 #endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index e8bd8d27136..aef61587334 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -26,10 +26,10 @@ #define CFG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) #define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CFG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index f1ffb2327d6..bad18d778aa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -35,8 +35,8 @@ #ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) #endif -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 #define CFG_SYS_FSL_TIMER_ADDR 0x023e0000 #define CFG_SYS_FSL_PMU_CLTBENR (CFG_SYS_FSL_PMU_ADDR + \ diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 5dd90b47f93..6de431f6bbb 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -19,8 +19,8 @@ #endif #endif -#if !defined(CONFIG_SYS_NS16550_CLK) -#define CONFIG_SYS_NS16550_CLK 13000000 +#if !defined(CFG_SYS_NS16550_CLK) +#define CFG_SYS_NS16550_CLK 13000000 #endif #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index e85918eb7ec..033341dbfb6 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -30,8 +30,8 @@ #define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) #define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CFG_SYS_FSL_SEC_OFFSET 0x00700000 diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 759c93747c7..2319ac6d563 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -290,8 +290,8 @@ int arch_cpu_init(void) board_gpio_init(); #if !CONFIG_IS_ENABLED(DM_SERIAL) - ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + ns16550_init((struct ns16550 *)(CFG_SYS_NS16550_COM1), + CFG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); #endif /* * Fix Power and Emulation Management Register @@ -299,7 +299,7 @@ int arch_cpu_init(void) */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), -#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) +#if (CFG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) &davinci_uart0_ctrl_regs->pwremu_mgmt); #else &davinci_uart2_ctrl_regs->pwremu_mgmt); diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c index 54aff78894a..5f5b9ebbf97 100644 --- a/arch/arm/mach-davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c @@ -27,9 +27,9 @@ void puts(const char *str) void putc(char c) { if (c == '\n') - ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), '\r'); + ns16550_putc((struct ns16550 *)(CFG_SYS_NS16550_COM1), '\r'); - ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), c); + ns16550_putc((struct ns16550 *)(CFG_SYS_NS16550_COM1), c); } #endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */ diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index 5b95f605001..1954e69e9f0 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -185,8 +185,8 @@ int arch_cpu_init(void) * driver doesn't handle this. */ #ifndef CONFIG_DM_SERIAL - ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM2), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + ns16550_init((struct ns16550 *)(CFG_SYS_NS16550_COM2), + CFG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); #endif return 0; diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c index 0a4fef295a3..3fcf8facb41 100644 --- a/arch/arm/mach-lpc32xx/devices.c +++ b/arch/arm/mach-lpc32xx/devices.c @@ -44,13 +44,13 @@ void lpc32xx_uart_init(unsigned int uart_id) #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_plat lpc32xx_uart[] = { { .base = UART3_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, { .base = UART4_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, { .base = UART5_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, { .base = UART6_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, }; #if defined(CONFIG_LPC32XX_HSUART) diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index f393ff91441..44d5214a3df 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -87,29 +87,29 @@ int dram_init_banksize(void) #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_plat am33xx_serial[] = { - { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, -# ifdef CONFIG_SYS_NS16550_COM2 - { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, -# ifdef CONFIG_SYS_NS16550_COM3 - { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, - { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, - { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, - { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM1, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, +# ifdef CFG_SYS_NS16550_COM2 + { .base = CFG_SYS_NS16550_COM2, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, +# ifdef CFG_SYS_NS16550_COM3 + { .base = CFG_SYS_NS16550_COM3, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM4, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM5, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM6, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, # endif # endif }; U_BOOT_DRVINFOS(am33xx_uarts) = { { "ns16550_serial", &am33xx_serial[0] }, -# ifdef CONFIG_SYS_NS16550_COM2 +# ifdef CFG_SYS_NS16550_COM2 { "ns16550_serial", &am33xx_serial[1] }, -# ifdef CONFIG_SYS_NS16550_COM3 +# ifdef CFG_SYS_NS16550_COM3 { "ns16550_serial", &am33xx_serial[2] }, { "ns16550_serial", &am33xx_serial[3] }, { "ns16550_serial", &am33xx_serial[4] }, diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 95d6555a0d2..f8b61a2b3e3 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -259,9 +259,9 @@ void board_init_uart_f(void) #if !CONFIG_IS_ENABLED(OF_CONTROL) static struct ns16550_plat ns16550_com1_pdata = { - .base = CONFIG_SYS_NS16550_COM1, + .base = CFG_SYS_NS16550_COM1, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }; diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 1161938d304..6dd61caf1c4 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -649,7 +649,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); + "clock-frequency", CFG_SYS_NS16550_CLK, 1); #endif #ifdef CONFIG_FSL_CORENET @@ -751,7 +751,7 @@ static void msg(const char *name, uint64_t uaddr, uint64_t daddr) * This function compares several CONFIG_xxx macros that contain physical * addresses with the corresponding nodes in the device tree, to see if * the physical addresses are all correct. For example, if - * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address + * CFG_SYS_NS16550_COM1 is defined, then it contains the virtual address * of the first UART. We convert this to a physical address and compare * that with the physical address of the first ns16550-compatible node * in the device tree. If they don't match, then we display a warning. @@ -796,15 +796,15 @@ int ft_verify_fdt(void *fdt) */ aliases = fdt_path_offset(fdt, "/aliases"); if (aliases > 0) { -#ifdef CONFIG_SYS_NS16550_COM1 +#ifdef CFG_SYS_NS16550_COM1 if (!fdt_verify_alias_address(fdt, aliases, "serial0", - CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) + CCSR_VIRT_TO_PHYS(CFG_SYS_NS16550_COM1))) return 0; #endif -#ifdef CONFIG_SYS_NS16550_COM2 +#ifdef CFG_SYS_NS16550_COM2 if (!fdt_verify_alias_address(fdt, aliases, "serial1", - CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) + CCSR_VIRT_TO_PHYS(CFG_SYS_NS16550_COM2))) return 0; #endif } diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 79fe567b587..b0ad7d7aa72 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -52,7 +52,7 @@ * TODO: Convert this to a clock driver exists that can give us the UART * clock here. */ -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() #endif #endif /* _ASM_CONFIG_H_ */ diff --git a/board/Synology/ds109/ds109.c b/board/Synology/ds109/ds109.c index 9e7f6ac6c79..5c3f46e23f4 100644 --- a/board/Synology/ds109/ds109.c +++ b/board/Synology/ds109/ds109.c @@ -101,17 +101,17 @@ int board_init(void) #include #define SOFTWARE_SHUTDOWN 0x31 #define SOFTWARE_REBOOT 0x43 -#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE +#define CFG_SYS_NS16550_COM2 KW_UART1_BASE void reset_misc(void) { int b_d; printf("Synology reset..."); udelay(50000); - b_d = ns16550_calc_divisor((struct ns16550 *)CONFIG_SYS_NS16550_COM2, - CONFIG_SYS_NS16550_CLK, 9600); - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM2, b_d); - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM2, + b_d = ns16550_calc_divisor((struct ns16550 *)CFG_SYS_NS16550_COM2, + CFG_SYS_NS16550_CLK, 9600); + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM2, b_d); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM2, SOFTWARE_REBOOT); } diff --git a/board/eets/pdu001/mux.c b/board/eets/pdu001/mux.c index f0f9e262ebd..886fef60b0a 100644 --- a/board/eets/pdu001/mux.c +++ b/board/eets/pdu001/mux.c @@ -92,22 +92,22 @@ void enable_uart5_pin_mux(void) void enable_uart_pin_mux(u32 addr) { switch (addr) { - case CONFIG_SYS_NS16550_COM1: + case CFG_SYS_NS16550_COM1: enable_uart0_pin_mux(); break; - case CONFIG_SYS_NS16550_COM2: + case CFG_SYS_NS16550_COM2: enable_uart1_pin_mux(); break; - case CONFIG_SYS_NS16550_COM3: + case CFG_SYS_NS16550_COM3: enable_uart2_pin_mux(); break; - case CONFIG_SYS_NS16550_COM4: + case CFG_SYS_NS16550_COM4: enable_uart3_pin_mux(); break; - case CONFIG_SYS_NS16550_COM5: + case CFG_SYS_NS16550_COM5: enable_uart4_pin_mux(); break; - case CONFIG_SYS_NS16550_COM6: + case CFG_SYS_NS16550_COM6: enable_uart5_pin_mux(); break; } diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index 99edaa3b421..a4254250bbf 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -343,7 +343,7 @@ void *board_fdt_blob_setup(int *err) return get_fdt_virt(); } -/* See CONFIG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */ +/* See CFG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */ int get_serial_clock(void) { return get_bus_freq(0); diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index c39df462e3b..ab3b2e3e69b 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -587,7 +587,7 @@ void fdt_disable_uart1(void *blob) int nodeoff; nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550", - CONFIG_SYS_NS16550_COM2); + CFG_SYS_NS16550_COM2); if (nodeoff > 0) { fdt_status_disabled(blob, nodeoff); diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index 0db11f4c5f7..9bf948cb5c9 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -45,7 +45,7 @@ void board_init_f(ulong bootflag) plat_ratio >>= 1; gd->bus_clk = get_board_sys_clk() * plat_ratio; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, gd->bus_clk / 16 / CONFIG_BAUDRATE); #ifdef CONFIG_SPL_MMC_BOOT diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index 9cd46c96641..8f0dec4c0ab 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -32,7 +32,7 @@ void board_init_f(ulong bootflag) plat_ratio >>= 1; gd->bus_clk = get_board_sys_clk() * plat_ratio; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, gd->bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); @@ -54,9 +54,9 @@ void board_init_r(gd_t *gd, ulong dest_addr) void putc(char c) { if (c == '\n') - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r'); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, '\r'); - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, c); } void puts(const char *str) diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index e7d4428d7c2..6c3f82849e3 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -57,7 +57,7 @@ void board_init_f(ulong bootflag) bus_clk = get_board_sys_clk() * plat_ratio; gd->bus_clk = bus_clk; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, bus_clk / 16 / CONFIG_BAUDRATE); #ifdef CONFIG_SPL_MMC_BOOT puts("\nSD boot...\n"); diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index 2fd8a287433..f9e0b5b25ab 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -31,7 +31,7 @@ void board_init_f(ulong bootflag) plat_ratio >>= 1; gd->bus_clk = get_board_sys_clk() * plat_ratio; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, gd->bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); @@ -52,9 +52,9 @@ void board_init_r(gd_t *gd, ulong dest_addr) void putc(char c) { if (c == '\n') - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r'); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, '\r'); - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, c); } void puts(const char *str) diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index 3ba94fecaa2..9faf259af74 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -73,7 +73,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; ccb_clk = sys_clk * plat_ratio / 2; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, ccb_clk / 16 / CONFIG_BAUDRATE); #if defined(CONFIG_SPL_MMC_BOOT) diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index c7fb4272c63..66a142b3ad0 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -72,7 +72,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; uart_clk = sys_clk * plat_ratio / 2; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, uart_clk / 16 / CONFIG_BAUDRATE); relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c index 8b68329b986..8866be54a66 100644 --- a/board/freescale/t208xqds/spl.c +++ b/board/freescale/t208xqds/spl.c @@ -82,7 +82,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; ccb_clk = sys_clk * plat_ratio / 2; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, ccb_clk / 16 / CONFIG_BAUDRATE); #if defined(CONFIG_SPL_MMC_BOOT) diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c index 3f9b1faa853..130cb8847c0 100644 --- a/board/freescale/t208xrdb/spl.c +++ b/board/freescale/t208xrdb/spl.c @@ -42,7 +42,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; ccb_clk = sys_clk * plat_ratio / 2; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, ccb_clk / 16 / CONFIG_BAUDRATE); #if defined(CONFIG_SPL_MMC_BOOT) diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c index 72d3b80b19b..779457d2964 100644 --- a/board/freescale/t4rdb/spl.c +++ b/board/freescale/t4rdb/spl.c @@ -51,7 +51,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; ccb_clk = sys_clk * plat_ratio / 2; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, ccb_clk / 16 / CONFIG_BAUDRATE); puts("\nSD boot...\n"); diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index c1b4b91b607..fa95886fa3b 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -795,9 +795,9 @@ U_BOOT_DRVINFOS(rx51_kp) = { }; static const struct ns16550_plat rx51_serial = { - .base = CONFIG_SYS_NS16550_COM3, + .base = CFG_SYS_NS16550_COM3, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 4978a65715b..14b0febd1a5 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -737,7 +737,7 @@ config SYS_NS16550 Support NS16550 UART or compatible. This can be enabled in the device tree with the correct input clock frequency. If the input clock frequency is not defined in the device tree, the macro - CONFIG_SYS_NS16550_CLK defined in a legacy board header file will + CFG_SYS_NS16550_CLK defined in a legacy board header file will be used. It can be a constant or a function to get clock, eg, get_serial_clock(). diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 5a693d2f02a..772dd6fef8f 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -92,8 +92,8 @@ static inline int serial_in_shift(void *addr, int shift) #if CONFIG_IS_ENABLED(DM_SERIAL) -#ifndef CONFIG_SYS_NS16550_CLK -#define CONFIG_SYS_NS16550_CLK 0 +#ifndef CFG_SYS_NS16550_CLK +#define CFG_SYS_NS16550_CLK 0 #endif /* @@ -567,9 +567,9 @@ int ns16550_serial_of_to_plat(struct udevice *dev) if (!plat->clock) plat->clock = dev_read_u32_default(dev, "clock-frequency", - CONFIG_SYS_NS16550_CLK); + CFG_SYS_NS16550_CLK); if (!plat->clock) - plat->clock = CONFIG_SYS_NS16550_CLK; + plat->clock = CFG_SYS_NS16550_CLK; if (!plat->clock) { debug("ns16550 clock not defined\n"); return -EINVAL; diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index 03b9e86bfc2..6fb4cb65c29 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -284,8 +284,8 @@ DECLARE_GLOBAL_DATA_PTR; #define DECLARE_HSUART_PRIV(port) \ static struct mtk_serial_priv mtk_hsuart##port = { \ - .regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \ - .fixed_clk_rate = CONFIG_SYS_NS16550_CLK \ + .regs = (struct mtk_serial_regs *)CFG_SYS_NS16550_COM##port, \ + .fixed_clk_rate = CFG_SYS_NS16550_CLK \ }; #define DECLARE_HSUART_FUNCTIONS(port) \ @@ -356,36 +356,36 @@ DECLARE_GLOBAL_DATA_PTR; #error "Invalid console index value." #endif -#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1) +#if CONFIG_CONS_INDEX == 1 && !defined(CFG_SYS_NS16550_COM1) #error "Console port 1 defined but not configured." -#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2) +#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_SYS_NS16550_COM2) #error "Console port 2 defined but not configured." -#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3) +#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_SYS_NS16550_COM3) #error "Console port 3 defined but not configured." -#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4) +#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_SYS_NS16550_COM4) #error "Console port 4 defined but not configured." -#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5) +#elif CONFIG_CONS_INDEX == 5 && !defined(CFG_SYS_NS16550_COM5) #error "Console port 5 defined but not configured." -#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6) +#elif CONFIG_CONS_INDEX == 6 && !defined(CFG_SYS_NS16550_COM6) #error "Console port 6 defined but not configured." #endif -#if defined(CONFIG_SYS_NS16550_COM1) +#if defined(CFG_SYS_NS16550_COM1) DECLARE_HSUART(1, "mtk-hsuart0"); #endif -#if defined(CONFIG_SYS_NS16550_COM2) +#if defined(CFG_SYS_NS16550_COM2) DECLARE_HSUART(2, "mtk-hsuart1"); #endif -#if defined(CONFIG_SYS_NS16550_COM3) +#if defined(CFG_SYS_NS16550_COM3) DECLARE_HSUART(3, "mtk-hsuart2"); #endif -#if defined(CONFIG_SYS_NS16550_COM4) +#if defined(CFG_SYS_NS16550_COM4) DECLARE_HSUART(4, "mtk-hsuart3"); #endif -#if defined(CONFIG_SYS_NS16550_COM5) +#if defined(CFG_SYS_NS16550_COM5) DECLARE_HSUART(5, "mtk-hsuart4"); #endif -#if defined(CONFIG_SYS_NS16550_COM6) +#if defined(CFG_SYS_NS16550_COM6) DECLARE_HSUART(6, "mtk-hsuart5"); #endif @@ -410,22 +410,22 @@ __weak struct serial_device *default_serial_console(void) void mtk_serial_initialize(void) { -#if defined(CONFIG_SYS_NS16550_COM1) +#if defined(CFG_SYS_NS16550_COM1) serial_register(&mtk_hsuart1_device); #endif -#if defined(CONFIG_SYS_NS16550_COM2) +#if defined(CFG_SYS_NS16550_COM2) serial_register(&mtk_hsuart2_device); #endif -#if defined(CONFIG_SYS_NS16550_COM3) +#if defined(CFG_SYS_NS16550_COM3) serial_register(&mtk_hsuart3_device); #endif -#if defined(CONFIG_SYS_NS16550_COM4) +#if defined(CFG_SYS_NS16550_COM4) serial_register(&mtk_hsuart4_device); #endif -#if defined(CONFIG_SYS_NS16550_COM5) +#if defined(CFG_SYS_NS16550_COM5) serial_register(&mtk_hsuart5_device); #endif -#if defined(CONFIG_SYS_NS16550_COM6) +#if defined(CFG_SYS_NS16550_COM6) serial_register(&mtk_hsuart6_device); #endif } diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index 76aa1e5afb4..4014f682040 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -20,17 +20,17 @@ DECLARE_GLOBAL_DATA_PTR; #error "Invalid console index value." #endif -#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1) +#if CONFIG_CONS_INDEX == 1 && !defined(CFG_SYS_NS16550_COM1) #error "Console port 1 defined but not configured." -#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2) +#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_SYS_NS16550_COM2) #error "Console port 2 defined but not configured." -#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3) +#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_SYS_NS16550_COM3) #error "Console port 3 defined but not configured." -#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4) +#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_SYS_NS16550_COM4) #error "Console port 4 defined but not configured." -#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5) +#elif CONFIG_CONS_INDEX == 5 && !defined(CFG_SYS_NS16550_COM5) #error "Console port 5 defined but not configured." -#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6) +#elif CONFIG_CONS_INDEX == 6 && !defined(CFG_SYS_NS16550_COM6) #error "Console port 6 defined but not configured." #endif @@ -38,33 +38,33 @@ DECLARE_GLOBAL_DATA_PTR; * the array is 0 based. */ static struct ns16550 *serial_ports[6] = { -#ifdef CONFIG_SYS_NS16550_COM1 - (struct ns16550 *)CONFIG_SYS_NS16550_COM1, +#ifdef CFG_SYS_NS16550_COM1 + (struct ns16550 *)CFG_SYS_NS16550_COM1, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM2 - (struct ns16550 *)CONFIG_SYS_NS16550_COM2, +#ifdef CFG_SYS_NS16550_COM2 + (struct ns16550 *)CFG_SYS_NS16550_COM2, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM3 - (struct ns16550 *)CONFIG_SYS_NS16550_COM3, +#ifdef CFG_SYS_NS16550_COM3 + (struct ns16550 *)CFG_SYS_NS16550_COM3, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM4 - (struct ns16550 *)CONFIG_SYS_NS16550_COM4, +#ifdef CFG_SYS_NS16550_COM4 + (struct ns16550 *)CFG_SYS_NS16550_COM4, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM5 - (struct ns16550 *)CONFIG_SYS_NS16550_COM5, +#ifdef CFG_SYS_NS16550_COM5 + (struct ns16550 *)CFG_SYS_NS16550_COM5, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM6 - (struct ns16550 *)CONFIG_SYS_NS16550_COM6 +#ifdef CFG_SYS_NS16550_COM6 + (struct ns16550 *)CFG_SYS_NS16550_COM6 #else NULL #endif @@ -78,7 +78,7 @@ static struct ns16550 *serial_ports[6] = { { \ int clock_divisor; \ clock_divisor = ns16550_calc_divisor(serial_ports[port-1], \ - CONFIG_SYS_NS16550_CLK, gd->baudrate); \ + CFG_SYS_NS16550_CLK, gd->baudrate); \ ns16550_init(serial_ports[port - 1], clock_divisor); \ return 0 ; \ } \ @@ -144,7 +144,7 @@ static void _serial_setbrg(const int port) { int clock_divisor; - clock_divisor = ns16550_calc_divisor(PORT, CONFIG_SYS_NS16550_CLK, + clock_divisor = ns16550_calc_divisor(PORT, CFG_SYS_NS16550_CLK, gd->baudrate); ns16550_reinit(PORT, clock_divisor); } @@ -179,32 +179,32 @@ serial_setbrg_dev(unsigned int dev_index) _serial_setbrg(dev_index); } -#if defined(CONFIG_SYS_NS16550_COM1) +#if defined(CFG_SYS_NS16550_COM1) DECLARE_ESERIAL_FUNCTIONS(1); struct serial_device eserial1_device = INIT_ESERIAL_STRUCTURE(1, "eserial0"); #endif -#if defined(CONFIG_SYS_NS16550_COM2) +#if defined(CFG_SYS_NS16550_COM2) DECLARE_ESERIAL_FUNCTIONS(2); struct serial_device eserial2_device = INIT_ESERIAL_STRUCTURE(2, "eserial1"); #endif -#if defined(CONFIG_SYS_NS16550_COM3) +#if defined(CFG_SYS_NS16550_COM3) DECLARE_ESERIAL_FUNCTIONS(3); struct serial_device eserial3_device = INIT_ESERIAL_STRUCTURE(3, "eserial2"); #endif -#if defined(CONFIG_SYS_NS16550_COM4) +#if defined(CFG_SYS_NS16550_COM4) DECLARE_ESERIAL_FUNCTIONS(4); struct serial_device eserial4_device = INIT_ESERIAL_STRUCTURE(4, "eserial3"); #endif -#if defined(CONFIG_SYS_NS16550_COM5) +#if defined(CFG_SYS_NS16550_COM5) DECLARE_ESERIAL_FUNCTIONS(5); struct serial_device eserial5_device = INIT_ESERIAL_STRUCTURE(5, "eserial4"); #endif -#if defined(CONFIG_SYS_NS16550_COM6) +#if defined(CFG_SYS_NS16550_COM6) DECLARE_ESERIAL_FUNCTIONS(6); struct serial_device eserial6_device = INIT_ESERIAL_STRUCTURE(6, "eserial5"); @@ -231,22 +231,22 @@ __weak struct serial_device *default_serial_console(void) void ns16550_serial_initialize(void) { -#if defined(CONFIG_SYS_NS16550_COM1) +#if defined(CFG_SYS_NS16550_COM1) serial_register(&eserial1_device); #endif -#if defined(CONFIG_SYS_NS16550_COM2) +#if defined(CFG_SYS_NS16550_COM2) serial_register(&eserial2_device); #endif -#if defined(CONFIG_SYS_NS16550_COM3) +#if defined(CFG_SYS_NS16550_COM3) serial_register(&eserial3_device); #endif -#if defined(CONFIG_SYS_NS16550_COM4) +#if defined(CFG_SYS_NS16550_COM4) serial_register(&eserial4_device); #endif -#if defined(CONFIG_SYS_NS16550_COM5) +#if defined(CFG_SYS_NS16550_COM5) serial_register(&eserial5_device); #endif -#if defined(CONFIG_SYS_NS16550_COM6) +#if defined(CFG_SYS_NS16550_COM6) serial_register(&eserial6_device); #endif } diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c index e9ff61a0bac..904f7d21bf0 100644 --- a/drivers/serial/serial_omap.c +++ b/drivers/serial/serial_omap.c @@ -15,8 +15,8 @@ #include #include -#ifndef CONFIG_SYS_NS16550_CLK -#define CONFIG_SYS_NS16550_CLK 0 +#ifndef CFG_SYS_NS16550_CLK +#define CFG_SYS_NS16550_CLK 0 #endif #ifdef CONFIG_DEBUG_UART_OMAP @@ -128,7 +128,7 @@ static int omap_serial_of_to_plat(struct udevice *dev) if (!plat->clock) plat->clock = dev_read_u32_default(dev, "clock-frequency", - CONFIG_SYS_NS16550_CLK); + CFG_SYS_NS16550_CLK); if (!plat->clock) { debug("omap serial clock not defined\n"); return -EINVAL; diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index b8cbdc36754..059885ecb54 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -151,13 +151,13 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CFG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) /* SERDES */ #define CONFIG_FSL_SERDES diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index dba15dae749..bde8fa8df4d 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -235,13 +235,13 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CFG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) /* * I2C diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index fd721f30b3a..05c097759f6 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -322,13 +322,13 @@ extern unsigned long get_sdram_size(void); /* Serial Port */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CFG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) /* I2C */ #define I2C_PCA9557_ADDR1 0x18 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 173f6205e08..132786a4236 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -163,15 +163,15 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index c99e6ba781a..824190a4123 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -12,8 +12,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE +#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_COM1 KW_UART0_BASE /* * Serial Port configuration diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 8b43fe0c993..e67da1fe1dc 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -12,8 +12,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE +#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_COM1 KW_UART0_BASE /* * Serial Port configuration diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 7cb10b205db..b8f3d70e595 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -294,15 +294,15 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 3fa2d01dcc2..777a64eceee 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -267,15 +267,15 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index c5a28fadb00..710f105cfad 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -269,13 +269,13 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* * I2C diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 795120c02a8..4c60364f7e7 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -229,13 +229,13 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* * I2C diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index e3cbc649fa1..ba4a989fc5f 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -89,15 +89,15 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 13b1ff3bce6..25d9c96e164 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -158,12 +158,12 @@ #endif /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* PMIC support */ #define CONFIG_POWER_TPS65910 diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index cb649b598fe..7c5e7ce475e 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -83,12 +83,12 @@ #define CONSOLE_COLOR_RED 0x001F /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ #ifdef CONFIG_MTD_RAW_NAND #define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h index b7b1cb0cfe1..abd868c1453 100644 --- a/include/configs/am335x_igep003x.h +++ b/include/configs/am335x_igep003x.h @@ -88,7 +88,7 @@ "echo WARNING: Could not determine device tree to use; fi; \0" /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ /* Ethernet support */ diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 08bae9b886f..452887d6995 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -136,11 +136,11 @@ #endif /* Regular Boot */ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ #endif /* ! __CONFIG_AM335X_SHC_H */ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index 7df5f140551..4af9edafca8 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -36,12 +36,12 @@ BOOTENV /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* PMIC support */ #define CONFIG_POWER_TPS65910 diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index b61c8005c33..4ff8528cf8a 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -14,7 +14,7 @@ #include /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000 /* I2C Configuration */ @@ -41,7 +41,7 @@ #define V_SCLK (V_OSCK) /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ #ifndef CONFIG_SPL_BUILD /* USB Device Firmware Update support */ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index d8b0531673f..c3b6a3fbda2 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -16,9 +16,9 @@ #define CONFIG_IODELAY_RECALIBRATION -#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ -#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ #define CONFIG_SYS_OMAP_ABE_SYSCK diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 0eed8db23bd..3114cf0c4fb 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -14,7 +14,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK 25000000 +#define CFG_SYS_NS16550_CLK 25000000 /* Miscellaneous configurable options */ diff --git a/include/configs/ap152.h b/include/configs/ap152.h index 71247111190..f0674456fd0 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -14,7 +14,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK 25000000 +#define CFG_SYS_NS16550_CLK 25000000 /* Miscellaneous configurable options */ diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 6a4092a83e2..f0a02ae1795 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -14,7 +14,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define FDT_MODULE "apalis-v1.2" #define FDT_MODULE_V1_0 "apalis" diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 84bd88f835a..4f00b3bad3f 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -21,7 +21,7 @@ * Apalis UART4: NVIDIA UARTC */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index 7224bd8d1f4..e3b6956eb5a 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -33,7 +33,7 @@ /* * Serial console configuration */ -#define CONFIG_SYS_NS16550_CLK 19660800 +#define CFG_SYS_NS16550_CLK 19660800 /* Init Stack Pointer */ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index c0429ae15c4..1932713f453 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -26,7 +26,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_CLK 33333333 +#define CFG_SYS_NS16550_CLK 33333333 /* * Ethernet PHY configuration diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 31f107a465c..f29729d09ba 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -181,12 +181,12 @@ /*DFUARGS*/ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* PMIC support */ #define CONFIG_POWER_TPS65910 diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h index 1bae49e15f3..cba109b74a9 100644 --- a/include/configs/bcm7260.h +++ b/include/configs/bcm7260.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_NS16550_COM1 0xf040c000 +#define CFG_SYS_NS16550_COM1 0xf040c000 #define CONFIG_SYS_INIT_RAM_ADDR 0x10200000 diff --git a/include/configs/bcm7445.h b/include/configs/bcm7445.h index 4b41dc220b1..a07f1b7ad0f 100644 --- a/include/configs/bcm7445.h +++ b/include/configs/bcm7445.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_NS16550_COM1 0xf040ab00 +#define CFG_SYS_NS16550_COM1 0xf040ab00 #define CONFIG_SYS_INIT_RAM_ADDR 0x80200000 diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index 795de469384..76189a4d31f 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -26,7 +26,7 @@ /* 12MB Malloc size */ /* console configuration */ -#define CONFIG_SYS_NS16550_CLK 25000000 +#define CFG_SYS_NS16550_CLK 25000000 /* * Increase max uncompressed/gunzip size, keeping size same as EMMC linux diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 481baff11d9..9f51b9ca59d 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -97,7 +97,7 @@ extern phys_addr_t prior_stage_fdt_address; */ #define V_NS16550_CLK 81000000 -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK /* * Serial console configuration. diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 1d51bb4e4c4..6b5f650811b 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -18,7 +18,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* SPI */ #define CONFIG_TEGRA_SLINK_CTRLS 6 diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 773ce3f6a6f..1bf6baf75c2 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -14,8 +14,8 @@ /* legacy #defines for non DM bur-board */ #ifndef CONFIG_DM -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x44e09000 #endif /* CONFIG_DM */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index f3416b534b2..35c5a4f1226 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -22,7 +22,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* SPI */ #define CONFIG_TEGRA_SLINK_CTRLS 6 diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index 0672b7dbbe9..55e2d744c4a 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -20,7 +20,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* SPI */ #define CONFIG_SPI_FLASH_SIZE (4 << 20) diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index bfa076b5cc9..1e5154af0a1 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -97,12 +97,12 @@ NANDARGS /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* SPL */ diff --git a/include/configs/ci20.h b/include/configs/ci20.h index 63dac1d4a79..b7511adc09a 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -15,7 +15,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 /* NS16550-ish UARTs */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000 /* Ethernet: davicom DM9000 */ #define CONFIG_DM9000_BASE 0xb6000000 diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 0641d5c0a23..8f058213e9e 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -14,8 +14,8 @@ #include /* Serial support */ -#define CONFIG_SYS_NS16550_CLK 48000000 -#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CFG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_COM1 0x44e09000 /* NAND support */ #define CFG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index b758086b86d..2ba3c3bc87d 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -13,7 +13,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_TEGRA_UARTA_SDIO1 -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* NAND support */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index c9d384e2bdb..ffed71a2e82 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -22,7 +22,7 @@ * Colibri UART-C: NVIDIA UARTB */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index f8ba4e82819..4f0188dd19e 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -94,7 +94,7 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index e03a24adca4..24cf554649b 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -15,7 +15,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 93201be485d..e1d18a77830 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -27,9 +27,9 @@ #elif (CONFIG_CONS_INDEX == 3) #define CONSOLEDEV "ttyS2" #endif -#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ -#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ #define CONFIG_SYS_OMAP_ABE_SYSCK diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 0d61724db8c..a1400eba1ad 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -20,8 +20,8 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_COM1 0xb0000c00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM1 0xb0000c00 #endif /* UART */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h index fe4b02c0ce2..211dab4d233 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -17,10 +17,10 @@ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: keyboard satellite board UART, default */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #ifdef CONFIG_TEGRA_ENABLE_UARTA /* UARTA: debug board UART */ -#define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE #endif /* NAND support */ diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index bfc0fa5c442..1d7b171da75 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -28,7 +28,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_CLK 33330000 +#define CFG_SYS_NS16550_CLK 33330000 /* * Ethernet PHY configuration diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index ce3cb20732d..9e092e16ea0 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -27,7 +27,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_CLK 33330000 +#define CFG_SYS_NS16550_CLK 33330000 /* * Ethernet PHY configuration diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 69aa55f86c5..b846889541c 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 7acdb0fa038..57b0fc90697 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -148,7 +148,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() /* * I2C diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 30ba6065253..e6e54fba898 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -330,8 +330,8 @@ * Retain non-DM serial port for debug purposes. */ #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) #endif #ifndef __ASSEMBLY__ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 38860bfd5ca..7ed1f153c23 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -35,7 +35,7 @@ #define CONFIG_MALLOC_F_ADDR CFG_SYS_FSL_OCRAM_BASE /* serial port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) /* SPL */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 5434c4f7679..1f642fbecc3 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -36,7 +36,7 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index b9c853d7dfe..28372d41590 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -20,8 +20,8 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_COM3 0xb0000e00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM3 0xb0000e00 #endif diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 148598fab46..b57eb52d148 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -26,7 +26,7 @@ /* GPIO */ -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 3f2dfa640c9..3579f9c8437 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -47,7 +47,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() /* * I2C diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index bd2f74c1262..45665115f66 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -227,7 +227,7 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() #endif /* diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 8c43f652ab6..1e2db12a83f 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -60,7 +60,7 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() /* I2C */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 06830f401a3..323feb6e333 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -145,7 +145,7 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() #endif /* diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 7dd5649005b..587f23be587 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -28,7 +28,7 @@ /* I2C */ /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) /* Miscellaneous configurable options */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 2fc06c1dd2d..6fc509af232 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -40,7 +40,7 @@ #define CPU_RELEASE_ADDR secondary_boot_addr /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock()) /* SD boot SPL */ #ifdef CONFIG_SD_BOOT diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 40b4cb964d1..8a3c87c6abd 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -40,7 +40,7 @@ #define CPU_RELEASE_ADDR secondary_boot_addr /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock()) /* SD boot SPL */ #ifdef CONFIG_SD_BOOT diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 5668e07d135..2117b081168 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -45,7 +45,7 @@ /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) /* * During booting, IFC is mapped at the region of 0x30000000. diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 895c566fea2..c79a50795b8 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -37,7 +37,7 @@ /* I2C */ /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock()) /* * During booting, IFC is mapped at the region of 0x30000000. diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index b90a84da8ad..a8d8d8b09e0 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 1f733d112dd..e09e9c82eb8 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -22,8 +22,8 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_CLK 50000000 -#define CONFIG_SYS_NS16550_COM1 0xbe000c00 +#define CFG_SYS_NS16550_CLK 50000000 +#define CFG_SYS_NS16550_COM1 0xbe000c00 #endif /* Serial common */ diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index da16e3b21a4..bb12ebfe4fd 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -14,8 +14,8 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_COM1 0xb0000c00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM1 0xb0000c00 #endif /* Serial common */ diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index eaffe0bf4c9..3da7619d78d 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -12,8 +12,8 @@ #include -#define CONFIG_SYS_NS16550_COM1 0x11005200 -#define CONFIG_SYS_NS16550_CLK 26000000 +#define CFG_SYS_NS16550_COM1 0x11005200 +#define CFG_SYS_NS16550_CLK 26000000 /* Environment settings */ #include diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index 347598868bb..0f7981a5661 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -12,8 +12,8 @@ #include -#define CONFIG_SYS_NS16550_COM1 0x11005000 -#define CONFIG_SYS_NS16550_CLK 26000000 +#define CFG_SYS_NS16550_COM1 0x11005000 +#define CFG_SYS_NS16550_CLK 26000000 /* Environment settings */ #include diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 4f1067c23bb..e870fc810cb 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -32,9 +32,9 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE +#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif #if defined(CONFIG_ARMADA_38X) && !defined(CONFIG_SYS_BAUDRATE_TABLE) diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 310bdde7cb5..2623f99f8d0 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -40,12 +40,12 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK /* * select serial console configuration */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index c59e1032439..baa452156ec 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* SPI */ #define CONFIG_SPI_FLASH_SIZE (4 << 20) diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index cce5556fe26..883cc0b99c9 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -28,7 +28,7 @@ #include -#define CONFIG_SYS_NS16550_COM3 UART3_BASE +#define CFG_SYS_NS16550_COM3 UART3_BASE /* MMC ENV related defines */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 81ca68de9bc..2b47d4ca376 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -91,7 +91,7 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 065820689ca..9fc22f0a6cb 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -319,13 +319,13 @@ * shorted - index 1 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CFG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) /* I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) diff --git a/include/configs/paz00.h b/include/configs/paz00.h index c12f4d0937d..a945f4e9b28 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -17,7 +17,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index ed3201aa3c4..71807837673 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -50,11 +50,11 @@ "\0" /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_NS16550_COM2 UART1_BASE -#define CONFIG_SYS_NS16550_COM3 UART2_BASE -#define CONFIG_SYS_NS16550_COM4 UART3_BASE -#define CONFIG_SYS_NS16550_COM5 UART4_BASE -#define CONFIG_SYS_NS16550_COM6 UART5_BASE +#define CFG_SYS_NS16550_COM1 UART0_BASE +#define CFG_SYS_NS16550_COM2 UART1_BASE +#define CFG_SYS_NS16550_COM3 UART2_BASE +#define CFG_SYS_NS16550_COM4 UART3_BASE +#define CFG_SYS_NS16550_COM5 UART4_BASE +#define CFG_SYS_NS16550_COM6 UART5_BASE #endif /* ! __CONFIG_PDU001_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 09f0ed9b9a1..99db59c489e 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index c7f03a1e754..4887747968f 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -22,7 +22,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 5765f2ccb5e..c9dd7509cb2 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -38,9 +38,9 @@ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x44e09000 -#define CONFIG_SYS_NS16550_COM4 0x481a6000 +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x44e09000 +#define CFG_SYS_NS16550_COM4 0x481a6000 /* I2C Configuration */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index c29bc448eed..6054fa42c1a 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -52,8 +52,8 @@ * Serial */ -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CFG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ 115200 } diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 029f898b64f..2b2d78b8c8e 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -75,7 +75,7 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_CLK 100000000 +#define CFG_SYS_NS16550_CLK 100000000 /* * SDMMC configurations diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 1ed0a262bc6..cd2a74fb52d 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -19,16 +19,16 @@ /* ns16550 reg in the low bits of cpu reg */ #ifdef CONFIG_MACH_SUNIV /* suniv doesn't have apb2 and uart is connected to apb1 */ -#define CONFIG_SYS_NS16550_CLK 100000000 +#define CFG_SYS_NS16550_CLK 100000000 #else -#define CONFIG_SYS_NS16550_CLK 24000000 +#define CFG_SYS_NS16550_CLK 24000000 #endif #ifndef CONFIG_DM_SERIAL -# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE -# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE -# define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE -# define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE -# define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE +# define CFG_SYS_NS16550_COM1 SUNXI_UART0_BASE +# define CFG_SYS_NS16550_COM2 SUNXI_UART1_BASE +# define CFG_SYS_NS16550_COM3 SUNXI_UART2_BASE +# define CFG_SYS_NS16550_COM4 SUNXI_UART3_BASE +# define CFG_SYS_NS16550_COM5 SUNXI_R_UART_BASE #endif /* CPU */ diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 38a43b726f0..92ee920346b 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -19,7 +19,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_CLK 166666666 +#define CFG_SYS_NS16550_CLK 166666666 /* * Even though the board houses Realtek RTL8211E PHY diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index f8e741ab6fc..09879663701 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -14,7 +14,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/tec.h b/include/configs/tec.h index 2377b47e054..ddf753da4a9 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 2915db7f8bf..92df457e818 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -26,7 +26,7 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK #ifdef CONFIG_ARM64 #define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 60632c58c67..9614fe686f6 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -77,8 +77,8 @@ #define CONFIG_SYS_TIMERBASE 0x4802E000 /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ /* CPU */ diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index f2dbe3544a5..1bd2a1874b8 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -30,8 +30,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ /* allow overwriting serial config and ethaddr */ diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index fb017771688..00eb329faa8 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -17,7 +17,7 @@ #include /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000 /* * SPL related defines. The Public RAM memory map the ROM defines the diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index aaeea77281b..119b4c0410c 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -34,13 +34,13 @@ #define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) /* UART Configuration */ -#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE -#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE +#define CFG_SYS_NS16550_COM1 KS2_UART0_BASE +#define CFG_SYS_NS16550_COM2 KS2_UART1_BASE #ifndef CONFIG_SOC_K2G -#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6) +#define CFG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6) #else -#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2 +#define CFG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2 #endif /* SPI Configuration */ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 80d2a011f0f..d282c3956e0 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -26,15 +26,15 @@ /* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} /* Select serial console configuration */ #ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 -#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CFG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CFG_SYS_NS16550_COM2 OMAP34XX_UART2 +#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 #endif /* Physical Memory Map */ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index eb930341c3a..ce50e35d8d4 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -27,9 +27,9 @@ /* * Hardware drivers */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_COM3 UART3_BASE +#define CFG_SYS_NS16550_COM3 UART3_BASE #endif /* TWL6030 */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index a1efb57f1b0..c49c177390b 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -29,7 +29,7 @@ /* * Hardware drivers */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000 /* * Environment setup diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index b14726ad234..22d783c325b 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -14,7 +14,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_CLK 40000000 /* * Command diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index b562d44a13b..e4cbc7da843 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_TEGRA_UARTA_GPU -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* SPI */ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 02ddc6fb6e0..338d8af8fb3 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -12,7 +12,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ +#define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ) diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 03aa7adcc0d..b2dc04a975a 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 0bd5a1e8522..f7a507768ec 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -15,7 +15,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 84e5ba39f14..2107bec6587 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -19,8 +19,8 @@ #define CONFIG_SYS_UBOOT_BASE 0 /* Serial SPL */ -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_COM3 0xb0000e00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM3 0xb0000e00 /* RAM */ diff --git a/include/configs/x530.h b/include/configs/x530.h index 318e3680a6e..a0162cab219 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -13,9 +13,9 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE +#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif /* diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 7090fcef680..b93451cbe07 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -127,10 +127,10 @@ /* Serial Driver Info */ /*====================*/ -#define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ +#define CFG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ -#define CONFIG_SYS_NS16550_CLK get_board_sys_clk() +#define CFG_SYS_NS16550_CLK get_board_sys_clk() /*======================*/ /* Ethernet Driver Info */ -- cgit v1.3.1 From cdc5ed8f1f2add27105151ecf61a07c5d4c3684a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:29 -0500 Subject: global: Move remaining CONFIG_SYS_NUM_* to CFG_SYS_NUM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 4 +- arch/arm/include/asm/arch-fsl-layerscape/config.h | 12 ++-- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 +- arch/powerpc/cpu/mpc85xx/fdt.c | 4 +- arch/powerpc/cpu/mpc85xx/liodn.c | 6 +- arch/powerpc/cpu/mpc85xx/p2041_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 4 +- arch/powerpc/cpu/mpc85xx/p5040_ids.c | 4 +- arch/powerpc/cpu/mpc85xx/speed.c | 6 +- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 4 +- arch/powerpc/include/asm/config_mpc85xx.h | 80 +++++++++++----------- arch/powerpc/include/asm/fsl_portals.h | 2 +- board/freescale/ls1043aqds/eth.c | 2 +- board/freescale/ls1043ardb/eth.c | 2 +- board/freescale/ls1046aqds/eth.c | 2 +- board/freescale/ls1046ardb/eth.c | 2 +- board/freescale/p2041rdb/eth.c | 2 +- board/freescale/t102xrdb/eth_t102xrdb.c | 4 +- board/freescale/t104xrdb/eth.c | 2 +- board/freescale/t208xqds/eth_t208xqds.c | 4 +- board/freescale/t4rdb/eth.c | 12 ++-- board/freescale/t4rdb/t4rdb.h | 8 +-- cmd/i2c.c | 6 +- drivers/i2c/i2c_core.c | 6 +- drivers/misc/fsl_portals.c | 2 +- drivers/net/fm/fm.c | 2 +- drivers/net/fm/fm.h | 4 +- drivers/net/fm/init.c | 48 ++++++------- include/configs/P2041RDB.h | 2 +- include/configs/T102xRDB.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- include/configs/km/km-mpc83xx.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/kmcent2.h | 2 +- include/e500.h | 2 +- include/fm_eth.h | 6 +- include/i2c.h | 2 +- 43 files changed, 138 insertions(+), 138 deletions(-) (limited to 'include') diff --git a/README b/README index 9086207954e..efb1d37df9a 100644 --- a/README +++ b/README @@ -923,7 +923,7 @@ The following options need to be configured: with a list of GPIO LEDs that have inverted polarity. - I2C Support: - CONFIG_SYS_NUM_I2C_BUSES + CFG_SYS_NUM_I2C_BUSES Hold the number of i2c buses you want to use. CONFIG_SYS_I2C_DIRECT_BUS @@ -940,7 +940,7 @@ The following options need to be configured: hold a list of buses you want to use, only used if CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and - CONFIG_SYS_NUM_I2C_BUSES = 9: + CFG_SYS_NUM_I2C_BUSES = 9: CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index ff752c21b14..0669222fed7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -209,9 +209,9 @@ /* SoC related */ #ifdef CONFIG_ARCH_LS1043A -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 7 -#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 7 +#define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE @@ -255,9 +255,9 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #elif defined(CONFIG_ARCH_LS1046A) -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 8 +#define CFG_SYS_NUM_FM1_10GEC 2 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index aef61587334..c11018d7329 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -160,7 +160,7 @@ struct sys_info { unsigned long freq_localbus; unsigned long freq_cga_m2; #ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; + unsigned long freq_fman[CFG_SYS_NUM_FMAN]; #endif unsigned long freq_qman; }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index bad18d778aa..a4e971ebbd7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -306,7 +306,7 @@ struct sys_info { unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; + unsigned long freq_fman[CFG_SYS_NUM_FMAN]; #endif #ifdef CONFIG_SYS_DPAA_QBMAN unsigned long freq_qman; diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 49a1aac42b5..b0363c9c102 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -264,7 +264,7 @@ int checkcpu (void) #endif #ifdef CONFIG_SYS_DPAA_FMAN - for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { + for (i = 0; i < CFG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freq_fman[i])); } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 47bea512c92..2c320b202ea 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -162,7 +162,7 @@ void disable_cpc_sram(void) cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR; - for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { /* find and disable LAW of SRAM */ struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); @@ -232,7 +232,7 @@ void enable_cpc(void) have_hwconfig = true; } - for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { if (have_hwconfig) { sprintf(cpc_subarg, "cpc%u", i + 1); cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); @@ -273,7 +273,7 @@ static void invalidate_cpc(void) int i; cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR; - for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { /* skip CPC when it used as all SRAM */ if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) continue; diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 6dd61caf1c4..32348b4e147 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -167,7 +167,7 @@ static inline void ft_fixup_l3cache(void *blob, int off) cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR; u32 cfg0 = in_be32(&cpc->cpccfg0); - size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; + size = CPC_CFG0_SZ_K(cfg0) * 1024 * CFG_SYS_NUM_CPC; num_ways = CPC_CFG0_NUM_WAYS(cfg0); line_size = CPC_CFG0_LINE_SZ(cfg0); num_sets = size / (line_size * num_ways); @@ -469,7 +469,7 @@ static void ft_fixup_dpaa_clks(void *blob) ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET, sysinfo.freq_fman[0]); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET, sysinfo.freq_fman[1]); #endif diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 9ad48d440f9..abc14fae4ec 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -104,7 +104,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev, fm = (void *)CFG_SYS_FSL_FM1_ADDR; break; -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) case FSL_HW_PORTAL_FMAN2: fm = (void *)CFG_SYS_FSL_FM2_ADDR; break; @@ -201,7 +201,7 @@ void set_liodns(void) setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl, fman1_liodn_tbl_sz); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) set_fman_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz); setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl, fman2_liodn_tbl_sz); @@ -373,7 +373,7 @@ void fdt_fixup_liodn(void *blob) fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz); #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_liodn_tbl_fman(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) fdt_fixup_liodn_tbl_fman(blob, fman2_liodn_tbl, fman2_liodn_tbl_sz); #endif #endif diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 8a833466782..2b790868e12 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -66,7 +66,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 2, 12), SET_FMAN_RX_1G_LIODN(1, 3, 13), SET_FMAN_RX_1G_LIODN(1, 4, 14), -#if (CONFIG_SYS_NUM_FM1_10GEC == 1) +#if (CFG_SYS_NUM_FM1_10GEC == 1) SET_FMAN_RX_10G_LIODN(1, 0, 15), #endif }; diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index 5b766f1d517..ba54b0310a7 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -62,7 +62,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 16), SET_FMAN_RX_1G_LIODN(2, 1, 17), @@ -101,7 +101,7 @@ struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106), #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64), #endif #endif diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index e3d163af9eb..6f11c81aba5 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -57,7 +57,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 17), SET_FMAN_RX_1G_LIODN(2, 1, 18), @@ -101,7 +101,7 @@ struct liodn_id_table liodn_bases[] = { #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), #endif -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(160), #endif #ifdef CONFIG_SYS_FSL_RAID_ENGINE diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 31d04819276..e2bdc2f9f11 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -406,7 +406,7 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_fman[0] = sys_info->freq_systembus / 2; break; } -#if (CONFIG_SYS_NUM_FMAN) == 2 +#if (CFG_SYS_NUM_FMAN) == 2 #ifdef CONFIG_SYS_FM2_CLK #define FM2_CLK_SEL 0x00000038 #define FM2_CLK_SHIFT 3 @@ -440,7 +440,7 @@ void get_sys_info(sys_info_t *sys_info) break; } #endif -#endif /* CONFIG_SYS_NUM_FMAN == 2 */ +#endif /* CFG_SYS_NUM_FMAN == 2 */ #else sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; #endif @@ -491,7 +491,7 @@ void get_sys_info(sys_info_t *sys_info) } else { sys_info->freq_fman[0] = sys_info->freq_systembus / 2; } -#if (CONFIG_SYS_NUM_FMAN) == 2 +#if (CFG_SYS_NUM_FMAN) == 2 if (rcw_tmp & FM2_CLK_SEL) { if (rcw_tmp & HWA_ASYNC_DIV) sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 172dbdbe464..8fe4e96a114 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -122,7 +122,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_10G_LIODN(1, 1, 95), }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 88), SET_FMAN_RX_1G_LIODN(2, 1, 89), @@ -175,7 +175,7 @@ struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(1069), #endif #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 25d1b486174..2edf0d6f83c 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -41,8 +41,8 @@ #define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_ARCH_P1023) -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 2 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 2 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 @@ -65,9 +65,9 @@ #define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 @@ -75,9 +75,9 @@ #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_P3041) -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 @@ -85,11 +85,11 @@ #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ -#define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM2_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CFG_SYS_NUM_FMAN 2 +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM2_DTSEC 4 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 @@ -98,11 +98,11 @@ #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 #elif defined(CONFIG_ARCH_P5040) -#define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_DTSEC 5 -#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CFG_SYS_NUM_FMAN 2 +#define CFG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FM2_DTSEC 5 +#define CFG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 @@ -119,21 +119,21 @@ #elif defined(CONFIG_ARCH_T4240) #ifdef CONFIG_ARCH_T4240 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_NUM_FM2_DTSEC 8 -#define CONFIG_SYS_NUM_FM2_10GEC 2 +#define CFG_SYS_NUM_FM1_DTSEC 8 +#define CFG_SYS_NUM_FM1_10GEC 2 +#define CFG_SYS_NUM_FM2_DTSEC 8 +#define CFG_SYS_NUM_FM2_10GEC 2 #else -#define CONFIG_SYS_NUM_FM1_DTSEC 6 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_DTSEC 8 -#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CFG_SYS_NUM_FM1_DTSEC 6 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FM2_DTSEC 8 +#define CFG_SYS_NUM_FM2_10GEC 1 #endif #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 #define CFG_SYS_FSL_SRDS_3 #define CFG_SYS_FSL_SRDS_4 -#define CONFIG_SYS_NUM_FMAN 2 +#define CFG_SYS_NUM_FMAN 2 #define CONFIG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 3 @@ -146,7 +146,7 @@ #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 -#define CONFIG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 @@ -155,23 +155,23 @@ #define CONFIG_MAX_DSP_CPUS 12 #define CONFIG_NUM_DSP_CPUS 6 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } -#define CONFIG_SYS_NUM_FM1_DTSEC 6 -#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CFG_SYS_NUM_FM1_DTSEC 6 +#define CFG_SYS_NUM_FM1_10GEC 2 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #else #define CONFIG_MAX_DSP_CPUS 2 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 0 +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM1_10GEC 0 #endif #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_PME_PLAT_CLK_DIV 2 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -186,9 +186,9 @@ #elif defined(CONFIG_ARCH_T1024) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 0 @@ -200,12 +200,12 @@ #define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_FSL_SRDS_1 #if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 4 +#define CFG_SYS_NUM_FM1_DTSEC 8 +#define CFG_SYS_NUM_FM1_10GEC 4 #define CONFIG_SYS_FSL_SRDS_2 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index b1fd6bd5cef..54ef4fb6295 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -11,7 +11,7 @@ enum fsl_dpaa_dev { FSL_HW_PORTAL_SEC, #ifdef CONFIG_SYS_DPAA_FMAN FSL_HW_PORTAL_FMAN1, -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) FSL_HW_PORTAL_FMAN2, #endif #endif diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index 6783ebebb59..645c56c73d5 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -427,7 +427,7 @@ int board_eth_init(struct bd_info *bis) break; } - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c index 00ff6028e69..3cae2a08677 100644 --- a/board/freescale/ls1043ardb/eth.c +++ b/board/freescale/ls1043ardb/eth.c @@ -62,7 +62,7 @@ int board_eth_init(struct bd_info *bis) } dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) fm_info_set_mdio(i, dev); /* 10GBase-R on lane A, MAC 9 */ diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index 88265a39948..926bd74ddc6 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -349,7 +349,7 @@ int board_eth_init(struct bd_info *bis) /* SGMII on slot 4, MAC 2 */ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c index 04fa57f81b2..af70d107734 100644 --- a/board/freescale/ls1046ardb/eth.c +++ b/board/freescale/ls1046ardb/eth.c @@ -64,7 +64,7 @@ int board_eth_init(struct bd_info *bis) } dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) fm_info_set_mdio(i, dev); /* 10GBase-R on lane A, MAC 9 */ diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 23fd619ceed..23ec32b7f97 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -162,7 +162,7 @@ int board_eth_init(struct bd_info *bis) fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index be42efa5c76..ed6b36339f7 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -85,7 +85,7 @@ int board_eth_init(struct bd_info *bis) break; } - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_RGMII: @@ -112,7 +112,7 @@ int board_eth_init(struct bd_info *bis) } } - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index bb6641b88a9..5ce24b40964 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -39,7 +39,7 @@ int board_eth_init(struct bd_info *bis) /* * Program on board RGMII, SGMII PHY addresses. */ - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 555985b6f25..62261f50ea9 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -625,7 +625,7 @@ int board_eth_init(struct bd_info *bis) break; } - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { @@ -673,7 +673,7 @@ int board_eth_init(struct bd_info *bis) } } - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index 4041b3d9ac4..241ee5a4a25 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -81,7 +81,7 @@ int board_eth_init(struct bd_info *bis) fm_disable_port(FM1_DTSEC5); fm_disable_port(FM1_DTSEC6); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: @@ -93,7 +93,7 @@ int board_eth_init(struct bd_info *bis) } } - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); @@ -104,7 +104,7 @@ int board_eth_init(struct bd_info *bis) } } -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { /* SGMII && 10GBase-R */ fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); @@ -121,7 +121,7 @@ int board_eth_init(struct bd_info *bis) fm_disable_port(FM2_DTSEC5); fm_disable_port(FM2_DTSEC6); - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CFG_SYS_NUM_FM2_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: @@ -133,7 +133,7 @@ int board_eth_init(struct bd_info *bis) } } - for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { + for (i = FM2_10GEC1; i < FM2_10GEC1 + CFG_SYS_NUM_FM2_10GEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); @@ -143,7 +143,7 @@ int board_eth_init(struct bd_info *bis) break; } } -#endif /* CONFIG_SYS_NUM_FMAN */ +#endif /* CFG_SYS_NUM_FMAN */ cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/t4rdb/t4rdb.h b/board/freescale/t4rdb/t4rdb.h index 06779f552fa..bb3ce216d7d 100644 --- a/board/freescale/t4rdb/t4rdb.h +++ b/board/freescale/t4rdb/t4rdb.h @@ -6,10 +6,10 @@ #ifndef __T4RDB_H__ #define __T4RDB_H__ -#undef CONFIG_SYS_NUM_FM1_DTSEC -#undef CONFIG_SYS_NUM_FM2_DTSEC -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM2_DTSEC 4 +#undef CFG_SYS_NUM_FM1_DTSEC +#undef CFG_SYS_NUM_FM2_DTSEC +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM2_DTSEC 4 #define CORTINA_FW_ADDR_IFCNOR 0xefe00000 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000 diff --git a/cmd/i2c.c b/cmd/i2c.c index e196a73efa6..7b84378f7cd 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -1697,7 +1697,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, #else int i; - for (i = 0; i < CONFIG_SYS_NUM_I2C_BUSES; i++) { + for (i = 0; i < CFG_SYS_NUM_I2C_BUSES; i++) { printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name); #ifndef CONFIG_SYS_I2C_DIRECT_BUS int j; @@ -1730,7 +1730,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, } show_bus(bus); #else - if (i >= CONFIG_SYS_NUM_I2C_BUSES) { + if (i >= CFG_SYS_NUM_I2C_BUSES) { printf("Invalid bus %d\n", i); return -1; } @@ -1788,7 +1788,7 @@ static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc, } else { bus_no = dectoul(argv[1], NULL); #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) - if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) { + if (bus_no >= CFG_SYS_NUM_I2C_BUSES) { printf("Invalid bus %d\n", bus_no); return -1; } diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 09f91e674d4..c3f6a1251f1 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -34,7 +34,7 @@ struct i2c_adapter *i2c_get_adapter(int index) } #if !defined(CONFIG_SYS_I2C_DIRECT_BUS) -struct i2c_bus_hose i2c_bus[CONFIG_SYS_NUM_I2C_BUSES] = +struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] = CONFIG_SYS_I2C_BUSES; #endif @@ -173,7 +173,7 @@ static int i2c_mux_disconnect_all(void) */ static void i2c_init_bus(unsigned int bus_no, int speed, int slaveaddr) { - if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) + if (bus_no >= CFG_SYS_NUM_I2C_BUSES) return; I2C_ADAP->init(I2C_ADAP, speed, slaveaddr); @@ -238,7 +238,7 @@ int i2c_set_bus_num(unsigned int bus) return 0; #ifndef CONFIG_SYS_I2C_DIRECT_BUS - if (bus >= CONFIG_SYS_NUM_I2C_BUSES) + if (bus >= CFG_SYS_NUM_I2C_BUSES) return -1; #endif diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c index 30a9409e5ab..9c4b4d7e46d 100644 --- a/drivers/misc/fsl_portals.c +++ b/drivers/misc/fsl_portals.c @@ -257,7 +257,7 @@ defined(CONFIG_ARCH_LS1046A) #endif #ifdef CONFIG_SYS_DPAA_FMAN - for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) { + for (j = 0; j < CFG_SYS_NUM_FMAN; j++) { char name[] = "fman@0"; name[sizeof(name) - 2] = '0' + j; diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 9b6dbe2882f..1d3b7aa0583 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -26,7 +26,7 @@ #include #endif -struct fm_muram muram[CONFIG_SYS_NUM_FMAN]; +struct fm_muram muram[CFG_SYS_NUM_FMAN]; void *fm_muram_base(int fm_idx) { diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h index 2379b3a11ca..3d9cc5ca069 100644 --- a/drivers/net/fm/fm.h +++ b/drivers/net/fm/fm.h @@ -15,11 +15,11 @@ #define OH_PORT_ID_BASE 0x01 #define MAX_NUM_OH_PORT 7 #define RX_PORT_1G_BASE 0x08 -#define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC +#define MAX_NUM_RX_PORT_1G CFG_SYS_NUM_FM1_DTSEC #define RX_PORT_10G_BASE 0x10 #define RX_PORT_10G_BASE2 0x08 #define TX_PORT_1G_BASE 0x28 -#define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC +#define MAX_NUM_TX_PORT_1G CFG_SYS_NUM_FM1_DTSEC #define TX_PORT_10G_BASE 0x30 #define TX_PORT_10G_BASE2 0x28 #define MIIM_TIMEOUT 0xFFFF diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 34f3816e65a..8443cbb6b65 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -19,70 +19,70 @@ #ifndef CONFIG_DM_ETH struct fm_eth_info fm_info[] = { -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 1) +#if (CFG_SYS_NUM_FM1_DTSEC >= 1) FM_DTSEC_INFO_INITIALIZER(1, 1), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 2) +#if (CFG_SYS_NUM_FM1_DTSEC >= 2) FM_DTSEC_INFO_INITIALIZER(1, 2), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 3) +#if (CFG_SYS_NUM_FM1_DTSEC >= 3) FM_DTSEC_INFO_INITIALIZER(1, 3), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 4) +#if (CFG_SYS_NUM_FM1_DTSEC >= 4) FM_DTSEC_INFO_INITIALIZER(1, 4), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 5) +#if (CFG_SYS_NUM_FM1_DTSEC >= 5) FM_DTSEC_INFO_INITIALIZER(1, 5), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 6) +#if (CFG_SYS_NUM_FM1_DTSEC >= 6) FM_DTSEC_INFO_INITIALIZER(1, 6), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 7) +#if (CFG_SYS_NUM_FM1_DTSEC >= 7) FM_DTSEC_INFO_INITIALIZER(1, 9), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 8) +#if (CFG_SYS_NUM_FM1_DTSEC >= 8) FM_DTSEC_INFO_INITIALIZER(1, 10), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 1) +#if (CFG_SYS_NUM_FM2_DTSEC >= 1) FM_DTSEC_INFO_INITIALIZER(2, 1), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 2) +#if (CFG_SYS_NUM_FM2_DTSEC >= 2) FM_DTSEC_INFO_INITIALIZER(2, 2), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 3) +#if (CFG_SYS_NUM_FM2_DTSEC >= 3) FM_DTSEC_INFO_INITIALIZER(2, 3), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4) +#if (CFG_SYS_NUM_FM2_DTSEC >= 4) FM_DTSEC_INFO_INITIALIZER(2, 4), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5) +#if (CFG_SYS_NUM_FM2_DTSEC >= 5) FM_DTSEC_INFO_INITIALIZER(2, 5), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 6) +#if (CFG_SYS_NUM_FM2_DTSEC >= 6) FM_DTSEC_INFO_INITIALIZER(2, 6), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 7) +#if (CFG_SYS_NUM_FM2_DTSEC >= 7) FM_DTSEC_INFO_INITIALIZER(2, 9), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 8) +#if (CFG_SYS_NUM_FM2_DTSEC >= 8) FM_DTSEC_INFO_INITIALIZER(2, 10), #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 1) +#if (CFG_SYS_NUM_FM1_10GEC >= 1) FM_TGEC_INFO_INITIALIZER(1, 1), #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 2) +#if (CFG_SYS_NUM_FM1_10GEC >= 2) FM_TGEC_INFO_INITIALIZER(1, 2), #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 3) +#if (CFG_SYS_NUM_FM1_10GEC >= 3) FM_TGEC_INFO_INITIALIZER2(1, 3), #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 4) +#if (CFG_SYS_NUM_FM1_10GEC >= 4) FM_TGEC_INFO_INITIALIZER2(1, 4), #endif -#if (CONFIG_SYS_NUM_FM2_10GEC >= 1) +#if (CFG_SYS_NUM_FM2_10GEC >= 1) FM_TGEC_INFO_INITIALIZER(2, 1), #endif -#if (CONFIG_SYS_NUM_FM2_10GEC >= 2) +#if (CFG_SYS_NUM_FM2_10GEC >= 2) FM_TGEC_INFO_INITIALIZER(2, 2), #endif }; @@ -101,7 +101,7 @@ int fm_standard_init(struct bd_info *bis) fm_eth_initialize(reg, &fm_info[i]); } -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) reg = (void *)CFG_SYS_FSL_FM2_ADDR; if (fm_init_common(1, reg)) return 0; @@ -276,7 +276,7 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) || ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) || ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC2))) -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) || ((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1))) || ((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2))) || diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 132786a4236..6b83b021f77 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -30,7 +30,7 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index b8f3d70e595..c4fed68273b 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -15,7 +15,7 @@ /* High Level Configuration Options */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL #define RESET_VECTOR_OFFSET 0x27FFC diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 777a64eceee..1eec9454210 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -58,7 +58,7 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS /* * These can be toggled for performance analysis, otherwise use default. diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 710f105cfad..42a0926329e 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -22,7 +22,7 @@ /* High Level Configuration Options */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL #define RESET_VECTOR_OFFSET 0x27FFC diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 4c60364f7e7..941efdc243f 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -17,7 +17,7 @@ /* High Level Configuration Options */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL #define RESET_VECTOR_OFFSET 0x27FFC diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index ba4a989fc5f..5969854796e 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -39,7 +39,7 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS /* * These can be toggled for performance analysis, otherwise use default. diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index a658cbc07c2..ab0d0a721af 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -50,7 +50,7 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } /* I2C */ -#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CFG_SYS_NUM_I2C_BUSES 4 #define CONFIG_SYS_I2C_MAX_HOPS 1 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 57b0fc90697..ad9853ab6b3 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -156,7 +156,7 @@ #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_NUM_I2C_BUSES 3 +#define CFG_SYS_NUM_I2C_BUSES 3 #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x0 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index e6e54fba898..7af65737ff0 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -136,7 +136,7 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS /* Environment in parallel NOR-Flash */ #define CONFIG_ENV_TOTAL_SIZE 0x040000 diff --git a/include/e500.h b/include/e500.h index 255f46bf1e5..9f68a834c2f 100644 --- a/include/e500.h +++ b/include/e500.h @@ -19,7 +19,7 @@ typedef struct unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; + unsigned long freq_fman[CFG_SYS_NUM_FMAN]; #endif #ifdef CONFIG_SYS_DPAA_QBMAN unsigned long freq_qman; diff --git a/include/fm_eth.h b/include/fm_eth.h index 7475b515073..aeb640925ee 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -56,7 +56,7 @@ enum fm_eth_type { #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfc000) #endif #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000) -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfc000) #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfd000) #endif @@ -102,7 +102,7 @@ enum fm_eth_type { offsetof(struct ccsr_fman, memac[n-1]),\ } #else -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) #define FM_TGEC_INFO_INITIALIZER(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \ @@ -131,7 +131,7 @@ enum fm_eth_type { #endif #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 3) +#if (CFG_SYS_NUM_FM1_10GEC >= 3) #define FM_TGEC_INFO_INITIALIZER2(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ diff --git a/include/i2c.h b/include/i2c.h index e0ee94e5504..c07e60b04bd 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -637,7 +637,7 @@ void i2c_early_init_f(void); /* no muxes used bus = i2c adapters */ #define CONFIG_SYS_I2C_DIRECT_BUS 1 #define CONFIG_SYS_I2C_MAX_HOPS 0 -#define CONFIG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) +#define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) #else /* we use i2c muxes */ #undef CONFIG_SYS_I2C_DIRECT_BUS -- cgit v1.3.1 From 3408d96e6cec9dac16fce1a32a522c5de8a182ae Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:31 -0500 Subject: Remove unused symbols This commit removes the following unused symbols: CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_PAXE_BASE CONFIG_SYS_PCCNT CONFIG_SYS_PCDAT CONFIG_SYS_PCDDR CONFIG_SYS_PCI1_ADDR CONFIG_SYS_PCI2_ADDR CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_SIZE CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_SIZE CONFIG_SYS_PCIE3_ADDR CONFIG_SYS_PCIE4_ADDR CONFIG_SYS_PCIE3_IO_PHYS CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE4_IO_PHYS CONFIG_SYS_PCIE4_IO_VIRT CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_SP_CENA_SIZE CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_SATA CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_SGMII_REFCLK_MHZ CONFIG_SYS_SGMII_LINERATE_MHZ CONFIG_SYS_SGMII_RATESCALE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI1_BASE CONFIG_SYS_SH_SDHI2_BASE CONFIG_SYS_SH_SDHI3_BASE CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT CONFIG_SYS_VCXK_BASE CONFIG_SYS_VCXK_DEFAULT_LINEALIGN CONFIG_SYS_VCXK_DOUBLEBUFFERED CONFIG_SYS_VCXK_ENABLE_DDR CONFIG_SYS_VCXK_ENABLE_PIN CONFIG_SYS_VCXK_ENABLE_PORT CONFIG_SYS_VCXK_INVERT_DDR CONFIG_SYS_VCXK_INVERT_PIN CONFIG_SYS_VCXK_INVERT_PORT CONFIG_SYS_VCXK_REQUEST_DDR CONFIG_SYS_VCXK_REQUEST_PIN CONFIG_SYS_VCXK_REQUEST_PORT CONFIG_SYS_VSC7385_BR_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 --- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 -- arch/arm/mach-rmobile/include/mach/r8a7790.h | 3 --- arch/arm/mach-rmobile/include/mach/r8a7791.h | 2 -- arch/arm/mach-rmobile/include/mach/r8a7793.h | 2 -- arch/arm/mach-rmobile/include/mach/r8a7794.h | 2 -- arch/arm/mach-rmobile/include/mach/rcar-base.h | 9 ------- arch/powerpc/include/asm/immap_85xx.h | 8 ------ include/configs/M5282EVB.h | 6 ----- include/configs/MPC8548CDS.h | 5 ---- include/configs/P2041RDB.h | 4 --- include/configs/T102xRDB.h | 4 --- include/configs/T104xRDB.h | 6 ----- include/configs/T208xQDS.h | 5 ---- include/configs/T208xRDB.h | 5 ---- include/configs/T4240RDB.h | 5 ---- include/configs/aristainetos2.h | 2 -- include/configs/eb_cpu5282.h | 30 ---------------------- include/configs/highbank.h | 5 ---- include/configs/km/km-mpc8360.h | 1 - include/configs/km/km-mpc83xx.h | 1 - include/configs/ls1012a2g5rdb.h | 4 --- include/configs/ls1012a_common.h | 4 --- include/configs/ls1043aqds.h | 4 --- include/configs/ls1046a_common.h | 5 ---- include/configs/p1_p2_rdb_pc.h | 6 ----- include/configs/phycore_am335x_r2.h | 6 ----- include/configs/r2dplus.h | 5 ---- include/configs/socrates.h | 8 ++---- include/configs/ti814x_evm.h | 2 -- include/configs/ti_armv7_keystone2.h | 5 ---- 31 files changed, 2 insertions(+), 157 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index c11018d7329..85ac5eb2813 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -35,7 +35,6 @@ #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) @@ -56,9 +55,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index a4e971ebbd7..59488a04e40 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -194,8 +194,6 @@ /* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) -#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000) #define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000) diff --git a/arch/arm/mach-rmobile/include/mach/r8a7790.h b/arch/arm/mach-rmobile/include/mach/r8a7790.h index ef74d59fed4..28669e3c771 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7790.h @@ -24,9 +24,6 @@ #define MSTP11_BITS 0x00000000 /* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 #define R8A7790_CUT_ES2X 2 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7791.h b/arch/arm/mach-rmobile/include/mach/r8a7791.h index 681d1ea524b..37d134c5bf2 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7791.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7791.h @@ -14,8 +14,6 @@ */ /* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 #define DBSC3_1_QOS_R0_BASE 0xE67A1000 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7793.h b/arch/arm/mach-rmobile/include/mach/r8a7793.h index 31433c36930..85f59d97712 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7793.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7793.h @@ -15,8 +15,6 @@ */ /* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 #define DBSC3_1_QOS_R0_BASE 0xE67A1000 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7794.h b/arch/arm/mach-rmobile/include/mach/r8a7794.h index 3baa4237c26..2bd6e469c81 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7794.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7794.h @@ -24,8 +24,6 @@ #define MSTP11_BITS 0x000001C0 /* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 #define R8A7794_CUT_ES2 2 diff --git a/arch/arm/mach-rmobile/include/mach/rcar-base.h b/arch/arm/mach-rmobile/include/mach/rcar-base.h index 4c98dffa073..e422e9100a8 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-base.h +++ b/arch/arm/mach-rmobile/include/mach/rcar-base.h @@ -70,15 +70,6 @@ #define SMSTPCR10 0xE6150998 #define SMSTPCR11 0xE615099C -/* RCAR-I2C */ -#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 -#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 -#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000 -#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000 - -/* SDHI */ -#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 - #define S3C_BASE 0xE6784000 #define S3C_INT_BASE 0xE6784A00 #define S3C_MEDIA_BASE 0xE6784B00 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index c9ced5474c2..78c0d054965 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2662,18 +2662,10 @@ struct ccsr_pman { #define CONFIG_SYS_PAMU_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET) -#define CONFIG_SYS_PCI1_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET) -#define CONFIG_SYS_PCI2_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI2_OFFSET) #define CONFIG_SYS_PCIE1_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET) #define CONFIG_SYS_PCIE2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET) -#define CONFIG_SYS_PCIE3_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE3_OFFSET) -#define CONFIG_SYS_PCIE4_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE4_OFFSET) #define CONFIG_SYS_SFP_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET) diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index e191dc615bc..925d26eaf10 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -130,13 +130,7 @@ #define CONFIG_SYS_PBDDR 0x0000000 #define CONFIG_SYS_PBDAT 0x0000000 -#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 - #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 #define CONFIG_SYS_PEHLPAR 0xC0 #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index bde8fa8df4d..c29e63c54ed 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -256,21 +256,16 @@ */ #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull #else #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #endif -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 6b83b021f77..c8329810786 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -248,8 +248,6 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 @@ -276,9 +274,7 @@ #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index c4fed68273b..e21639a6951 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -349,8 +349,6 @@ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull #endif #endif /* CONFIG_PCI */ @@ -391,9 +389,7 @@ #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 1eec9454210..a3d04882f0d 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -325,16 +325,12 @@ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull #endif /* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull #endif #endif /* CONFIG_PCI */ @@ -364,9 +360,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 42a0926329e..72052be78a9 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -359,13 +359,10 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN @@ -385,9 +382,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 941efdc243f..c798e4487a4 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -313,13 +313,10 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN @@ -339,9 +336,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 5969854796e..5777df8e507 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -121,13 +121,10 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull /* * Miscellaneous configurable options @@ -337,9 +334,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 1f2b3b58ca6..35e8840a92a 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -30,8 +30,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN - #ifdef CONFIG_IMX_HAB #define HAB_EXTRA_SETTINGS \ "hab_check_addr=" \ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index aaa2ef039d9..80a820c913b 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -137,13 +137,7 @@ #define CONFIG_SYS_PBDDR 0x0000000 #define CONFIG_SYS_PBDAT 0x0000000 -#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 - #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 #define CONFIG_SYS_PASPAR 0x0F0F #define CONFIG_SYS_PEHLPAR 0xC0 @@ -160,29 +154,5 @@ #define CONFIG_I2C_RTC_ADDR 0x68 #endif -/*----------------------------------------------------------------------- - * VIDEO configuration - */ - -#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 -#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 -#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE - -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 - -#define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 - -#define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 - -#define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE -#define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE -#define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 - #endif /* _CONFIG_M5282EVB_H */ /*---------------------------------------------------------------------*/ diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 5e2b50bbac1..a7d21a76dba 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -14,11 +14,6 @@ * Miscellaneous configurable options */ -/* Environment data setup -*/ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ - #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h index 92e046d02d7..fb43fb81bc0 100644 --- a/include/configs/km/km-mpc8360.h +++ b/include/configs/km/km-mpc8360.h @@ -72,4 +72,3 @@ * PAXE on the local bus CS3 */ #define CONFIG_SYS_PAXE_BASE 0xA0000000 -#define CONFIG_SYS_PAXE_SIZE 256 diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index ab0d0a721af..7d36a25dc23 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -8,7 +8,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index f0248e64646..196e024b57e 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -11,10 +11,6 @@ /* DDR */ #define CONFIG_SYS_SDRAM_SIZE 0x40000000 -/* SATA */ - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index b57eb52d148..809f9ae8c8d 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -18,10 +18,6 @@ /*SPI device */ #define CFG_SYS_FSL_QSPI_BASE 0x40000000 -/* SATA */ - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - /* I2C */ /* GPIO */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 3b51cb8f174..87751f786c8 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -35,10 +35,6 @@ #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB #endif -/* SATA */ - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - /* * IFC Definitions */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 8a3c87c6abd..3934fbbb41d 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -65,11 +65,6 @@ /* I2C */ -/* SATA */ -#ifndef SPL_NO_SATA -#define CONFIG_SYS_SATA AHCI_BASE_ADDR -#endif - /* FMan ucode */ #ifndef SPL_NO_FMAN #define CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 9fc22f0a6cb..44e608536fe 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -279,12 +279,6 @@ #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE #endif -#define CONFIG_SYS_VSC7385_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ - OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) - /* The size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE_SIZE 8192 #endif diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index c5817b010f8..43a60825b57 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -97,10 +97,4 @@ #endif /* !CONFIG_MTD_RAW_NAND */ -/* CPU */ - -#ifdef CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#endif - #endif /* ! __CONFIG_PHYCORE_AM335x_R2_H */ diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index ac39e11a99e..406ee6282c5 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -18,9 +18,4 @@ #define CONFIG_SYS_FLASH_BASE (0xA0000000) #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -/* - * SuperH Clock setting - */ -#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ - #endif /* __CONFIG_H */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 388a4e42efb..9b106fc1c97 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -109,12 +109,8 @@ * Memory space is mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "TSEC0" diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 9614fe686f6..fc78077014b 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -84,8 +84,6 @@ /* Defines for SPL */ -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 - /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM * 64 bytes before this address should be set aside for u-boot.img's diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 119b4c0410c..65abb187d96 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -46,11 +46,6 @@ /* SPI Configuration */ #define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) -/* Network Configuration */ -#define CONFIG_SYS_SGMII_REFCLK_MHZ 312 -#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 -#define CONFIG_SYS_SGMII_RATESCALE 2 - /* Keystone net */ #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE -- cgit v1.3.1 From 789bb9537a4427798e3e28ff0c6be2c27454315f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:32 -0500 Subject: Convert CONFIG_SYS_OMAP_ABE_SYSCK to Kconfig This converts the following to Kconfig: CONFIG_SYS_OMAP_ABE_SYSCK Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/arm/mach-omap2/Kconfig | 3 +++ arch/arm/mach-omap2/omap5/Kconfig | 1 + include/configs/am57xx_evm.h | 2 -- include/configs/dra7xx_evm.h | 2 -- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 78317e474db..3bf97205226 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -144,6 +144,9 @@ config SYS_MPUCLK help Defines the MPU clock speed (in MHz). +config SYS_OMAP_ABE_SYSCK + bool + config TI_SECURE_EMIF_REGION_START hex "Reserved EMIF region start address" depends on TI_SECURE_DEVICE diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 4c2f990b287..18a66764224 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -2,6 +2,7 @@ if OMAP54XX config DRA7XX bool + select SYS_OMAP_ABE_SYSCK help DRA7xx is an OMAP based SOC with Dual Core A-15s. diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index c3b6a3fbda2..84555f3b13d 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -20,8 +20,6 @@ #define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#define CONFIG_SYS_OMAP_ABE_SYSCK - #ifndef CONFIG_SPL_BUILD #define DFUARGS \ "dfu_bufsiz=0x10000\0" \ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index e1d18a77830..bb335a0a473 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -31,8 +31,6 @@ #define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#define CONFIG_SYS_OMAP_ABE_SYSCK - #ifndef CONFIG_SPL_BUILD #define DFUARGS \ "dfu_bufsiz=0x10000\0" \ -- cgit v1.3.1 From ecc8d425fd50d894dd0a06796c17030ef4a7942f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:33 -0500 Subject: global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/arm/cpu/armv7/ls102xa/cpu.c | 16 ++++---- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 46 +++++++++++----------- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 24 +++++------ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 10 ++--- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 34 ++++++++-------- arch/arm/include/asm/arch-ls102xa/config.h | 24 +++++------ arch/m68k/include/asm/immap.h | 8 ++-- arch/powerpc/cpu/mpc83xx/pcie.c | 10 ++--- arch/powerpc/cpu/mpc85xx/liodn.c | 2 +- arch/powerpc/include/asm/fsl_pci.h | 32 +++++++-------- arch/powerpc/include/asm/immap_85xx.h | 4 +- board/freescale/common/p_corenet/tlb.c | 12 +++--- board/freescale/mpc8548cds/tlb.c | 6 +-- board/freescale/p1010rdb/tlb.c | 4 +- board/freescale/p1_p2_rdb_pc/tlb.c | 4 +- board/freescale/t102xrdb/tlb.c | 4 +- board/freescale/t104xrdb/tlb.c | 4 +- board/freescale/t208xqds/tlb.c | 10 ++--- board/freescale/t208xrdb/tlb.c | 10 ++--- board/freescale/t4rdb/tlb.c | 12 +++--- board/keymile/kmcent2/tlb.c | 4 +- board/socrates/tlb.c | 4 +- common/fdt_support.c | 4 +- drivers/pci/pci_auto.c | 8 ++-- drivers/pci/pcie_fsl.c | 16 ++++---- drivers/pci/pcie_fsl.h | 12 +++--- drivers/pci/pcie_layerscape.h | 16 ++++---- drivers/pci/pcie_layerscape_ep.c | 6 +-- drivers/pci/pcie_layerscape_gen4.c | 6 +-- drivers/pci/pcie_layerscape_gen4.h | 8 ++-- include/configs/MPC837XERDB.h | 18 ++++----- include/configs/MPC8548CDS.h | 24 +++++------ include/configs/P1010RDB.h | 24 +++++------ include/configs/P2041RDB.h | 20 +++++----- include/configs/T102xRDB.h | 20 +++++----- include/configs/T104xRDB.h | 24 +++++------ include/configs/T208xQDS.h | 24 +++++------ include/configs/T208xRDB.h | 24 +++++------ include/configs/T4240RDB.h | 24 +++++------ include/configs/kmcent2.h | 8 ++-- include/configs/p1_p2_rdb_pc.h | 24 +++++------ include/configs/socrates.h | 4 +- 42 files changed, 299 insertions(+), 299 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index d530e0655bc..d09c21d5d9b 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -168,18 +168,18 @@ static void mmu_setup(void) /* Level 1 has 512 entries */ for (i = 0; i < 512; i++) { /* Mapping for PCIe 1 */ - if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR && - va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR + - CONFIG_SYS_PCIE_MMAP_SIZE)) + if (va_start >= CFG_SYS_PCIE1_VIRT_ADDR && + va_start < (CFG_SYS_PCIE1_VIRT_ADDR + + CFG_SYS_PCIE_MMAP_SIZE)) set_pgsection(level1_table, i, - CONFIG_SYS_PCIE1_PHYS_BASE + va_start, + CFG_SYS_PCIE1_PHYS_BASE + va_start, MT_DEVICE_MEM); /* Mapping for PCIe 2 */ - else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR && - va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR + - CONFIG_SYS_PCIE_MMAP_SIZE)) + else if (va_start >= CFG_SYS_PCIE2_VIRT_ADDR && + va_start < (CFG_SYS_PCIE2_VIRT_ADDR + + CFG_SYS_PCIE_MMAP_SIZE)) set_pgsection(level1_table, i, - CONFIG_SYS_PCIE2_PHYS_BASE + va_start, + CFG_SYS_PCIE2_PHYS_BASE + va_start, MT_DEVICE_MEM); else set_pgsection(level1_table, i, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index c11341a1d38..ef71e2cf2bc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -257,26 +257,26 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, + { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR, + CFG_SYS_PCIE1_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, + { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR, + CFG_SYS_PCIE2_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR, + CFG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, #endif -#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR - { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, +#ifdef CFG_SYS_PCIE4_PHYS_ADDR + { CFG_SYS_PCIE4_PHYS_ADDR, CFG_SYS_PCIE4_PHYS_ADDR, + CFG_SYS_PCIE4_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -368,19 +368,19 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, + { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR, + CFG_SYS_PCIE1_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, + { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR, + CFG_SYS_PCIE2_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR, + CFG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -477,25 +477,25 @@ static void fix_pcie_mmu_map(void) (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) { for (i = 0; i < ARRAY_SIZE(final_map); i++) { switch (final_map[i].phys) { - case CONFIG_SYS_PCIE1_PHYS_ADDR: + case CFG_SYS_PCIE1_PHYS_ADDR: final_map[i].phys = 0x2000000000ULL; final_map[i].virt = 0x2000000000ULL; final_map[i].size = 0x800000000ULL; break; - case CONFIG_SYS_PCIE2_PHYS_ADDR: + case CFG_SYS_PCIE2_PHYS_ADDR: final_map[i].phys = 0x2800000000ULL; final_map[i].virt = 0x2800000000ULL; final_map[i].size = 0x800000000ULL; break; -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - case CONFIG_SYS_PCIE3_PHYS_ADDR: +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + case CFG_SYS_PCIE3_PHYS_ADDR: final_map[i].phys = 0x3000000000ULL; final_map[i].virt = 0x3000000000ULL; final_map[i].size = 0x800000000ULL; break; #endif -#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR - case CONFIG_SYS_PCIE4_PHYS_ADDR: +#ifdef CFG_SYS_PCIE4_PHYS_ADDR + case CFG_SYS_PCIE4_PHYS_ADDR: final_map[i].phys = 0x3800000000ULL; final_map[i].virt = 0x3800000000ULL; final_map[i].size = 0x800000000ULL; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 4db479140ea..20f96713871 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -35,17 +35,17 @@ #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 #ifdef CONFIG_ARCH_LS2080A -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE1_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE2_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE3_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE4_PHYS_SIZE 0x200000000 #else -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 -#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#ifndef CFG_SYS_PCIE3_PHYS_SIZE +#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000 #endif -#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE4_PHYS_SIZE 0x800000000 #define SYS_PCIE5_PHYS_SIZE 0x800000000 #define SYS_PCIE6_PHYS_SIZE 0x800000000 #endif @@ -83,9 +83,9 @@ #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000 #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 85ac5eb2813..64dc7c88b7f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -33,8 +33,8 @@ #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) @@ -90,9 +90,9 @@ #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) #define QMAN_CQSIDR_REG 0x20a80 -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL /* LUT registers */ #ifdef CONFIG_ARCH_LS1012A #define PCIE_LUT_BASE 0xC0000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 59488a04e40..cd112402e0c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -192,35 +192,35 @@ /* PCIe */ -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000) #define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000) #endif #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL -#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL +#define CFG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL #define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL #define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL #elif CONFIG_ARCH_LS1088A -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL #elif CONFIG_ARCH_LS1028A -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL /* this is used by integrated PCI on LS1028, includes ECAM and register space */ -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL +#define CFG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL #else -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL -#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL +#define CFG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL #endif /* Device Configuration */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 033341dbfb6..62026bda9e2 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -55,22 +55,22 @@ #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) - -#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL -#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL -#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL -#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ +#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) + +#define CFG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL +#define CFG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL +#define CFG_SYS_PCIE1_VIRT_ADDR 0x24000000UL +#define CFG_SYS_PCIE2_VIRT_ADDR 0x34000000UL +#define CFG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ /* * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. */ -#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ - CONFIG_SYS_PCIE1_VIRT_ADDR) -#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ - CONFIG_SYS_PCIE2_VIRT_ADDR) +#define CFG_SYS_PCIE1_PHYS_ADDR (CFG_SYS_PCIE1_PHYS_BASE + \ + CFG_SYS_PCIE1_VIRT_ADDR) +#define CFG_SYS_PCIE2_PHYS_ADDR (CFG_SYS_PCIE2_PHYS_BASE + \ + CFG_SYS_PCIE2_VIRT_ADDR) /* SATA */ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index ead62cd0387..f2eb6fcb463 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -337,10 +337,10 @@ #define CONFIG_SYS_NUM_IRQS (128) #ifdef CONFIG_PCI -#define CONFIG_SYS_PCI_BAR0 (0x40000000) -#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) -#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_BAR0 (0x40000000) +#define CFG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) +#define CFG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) #endif #endif /* CONFIG_M547x */ diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index d2b6b05bdaf..47ca74c5c35 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -24,13 +24,13 @@ static struct { u32 size; } mpc83xx_pcie_cfg_space[] = { { - .base = CONFIG_SYS_PCIE1_CFG_BASE, - .size = CONFIG_SYS_PCIE1_CFG_SIZE, + .base = CFG_SYS_PCIE1_CFG_BASE, + .size = CFG_SYS_PCIE1_CFG_SIZE, }, -#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE) +#if defined(CFG_SYS_PCIE2_CFG_BASE) && defined(CFG_SYS_PCIE2_CFG_SIZE) { - .base = CONFIG_SYS_PCIE2_CFG_BASE, - .size = CONFIG_SYS_PCIE2_CFG_SIZE, + .base = CFG_SYS_PCIE2_CFG_BASE, + .size = CFG_SYS_PCIE2_CFG_SIZE, }, #endif }; diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index abc14fae4ec..d5df02d39d8 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -387,7 +387,7 @@ void fdt_fixup_liodn(void *blob) fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz); #endif - ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR; + ccsr_pcix_t *pcix = (ccsr_pcix_t *)CFG_SYS_PCIE1_ADDR; int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0; if (pci_ver >= 0x0204) { diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 06f9bfb8ac7..809ab1d4187 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -193,35 +193,35 @@ int fsl_pcie_init_board(int busno); #define SET_STD_PCI_INFO(x, num) \ { \ - x.regs = CONFIG_SYS_PCI##num##_ADDR; \ - x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \ - x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \ - x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \ - x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \ - x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \ - x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \ + x.regs = CFG_SYS_PCI##num##_ADDR; \ + x.mem_bus = CFG_SYS_PCI##num##_MEM_BUS; \ + x.mem_phys = CFG_SYS_PCI##num##_MEM_PHYS; \ + x.mem_size = CFG_SYS_PCI##num##_MEM_SIZE; \ + x.io_bus = CFG_SYS_PCI##num##_IO_BUS; \ + x.io_phys = CFG_SYS_PCI##num##_IO_PHYS; \ + x.io_size = CFG_SYS_PCI##num##_IO_SIZE; \ x.law = LAW_TRGT_IF_PCI_##num; \ x.pci_num = num; \ } #define SET_STD_PCIE_INFO(x, num) \ { \ - x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ - x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \ - x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \ - x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \ - x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \ - x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \ - x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \ + x.regs = CFG_SYS_PCIE##num##_ADDR; \ + x.mem_bus = CFG_SYS_PCIE##num##_MEM_BUS; \ + x.mem_phys = CFG_SYS_PCIE##num##_MEM_PHYS; \ + x.mem_size = CFG_SYS_PCIE##num##_MEM_SIZE; \ + x.io_bus = CFG_SYS_PCIE##num##_IO_BUS; \ + x.io_phys = CFG_SYS_PCIE##num##_IO_PHYS; \ + x.io_size = CFG_SYS_PCIE##num##_IO_SIZE; \ x.law = LAW_TRGT_IF_PCIE_##num; \ x.pci_num = num; \ } #define __FT_FSL_PCI_SETUP(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR) + ft_fsl_pci_setup(blob, compat, CFG_SYS_PCI##num##_ADDR) #define __FT_FSL_PCIE_SETUP(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR) + ft_fsl_pci_setup(blob, compat, CFG_SYS_PCIE##num##_ADDR) #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1) #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 78c0d054965..9ae698743ee 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2662,9 +2662,9 @@ struct ccsr_pman { #define CONFIG_SYS_PAMU_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET) -#define CONFIG_SYS_PCIE1_ADDR \ +#define CFG_SYS_PCIE1_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET) -#define CONFIG_SYS_PCIE2_ADDR \ +#define CFG_SYS_PCIE2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET) #define CONFIG_SYS_SFP_ADDR \ diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index ef46353a367..4cdef89bf0e 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -91,23 +91,23 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 2, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x40000000, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x50000000, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index 8d1e5fee936..9c8e9486008 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 4: * PCI and PCIe MEM 1G Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_VIRT, CFG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_1G, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 5: * PCI1 IO 1M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCI1_IO_VIRT, CFG_SYS_PCI1_IO_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 6: * PCIe IO 1M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), }; diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index aa7517a74d8..5e1fa70bca5 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -52,12 +52,12 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_PCI /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256K, 1), #endif diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 85d41327aa2..4cc5e01f578 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -45,12 +45,12 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_PCI /* *I*G* - PCI memory 1.5G */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI I/O effective: 192K */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1), #endif diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c index 8fdff7576fe..74744c8ab0a 100644 --- a/board/freescale/t102xrdb/tlb.c +++ b/board/freescale/t102xrdb/tlb.c @@ -54,12 +54,12 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1), diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 8a3d67449c2..905e4771c91 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -67,12 +67,12 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1), diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index f27faf5d243..9160674b94f 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -66,28 +66,28 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifndef CONFIG_SPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_512M, 1), /* *I*G* - PCIe 2, 0xa0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE2_MEM_VIRT, CFG_SYS_PCIE2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCIe 3, 0xb0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT, CFG_SYS_PCIE3_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCIe 4, 0xc0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256K, 1), diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index da03aadb173..69e58e7e973 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -66,28 +66,28 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifndef CONFIG_SPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_512M, 1), /* *I*G* - PCIe 2, 0xa0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE2_MEM_VIRT, CFG_SYS_PCIE2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCIe 3, 0xb0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT, CFG_SYS_PCIE3_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCIe 4, 0xc0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256K, 1), diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index 059449af1ed..c57af3046f9 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -52,23 +52,23 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x50000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c index 095fc7e9614..0f6dc6063ab 100644 --- a/board/keymile/kmcent2/tlb.c +++ b/board/keymile/kmcent2/tlb.c @@ -46,12 +46,12 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 2, BOOKE_PAGESZ_128M, 1), /* *I*G* - PCI1 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI1 I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1), diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index de80c3c0e57..1ab403d145e 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_PHYS, CFG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -49,7 +49,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_PHYS + 0x10000000, CFG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), diff --git a/common/fdt_support.c b/common/fdt_support.c index ebebffc7890..dbceec6f2dc 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -739,7 +739,7 @@ int fdt_delete_disabled_nodes(void *blob) } #ifdef CONFIG_PCI -#define CONFIG_SYS_PCI_NR_INBOUND_WIN 4 +#define CFG_SYS_PCI_NR_INBOUND_WIN 4 #define FDT_PCI_PREFETCH (0x40000000) #define FDT_PCI_MEM32 (0x02000000) @@ -751,7 +751,7 @@ int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) { int addrcell, sizecell, len, r; u32 *dma_range; /* sized based on pci addr cells, size-cells, & address-cells */ - u32 dma_ranges[(3 + 2 + 2) * CONFIG_SYS_PCI_NR_INBOUND_WIN]; + u32 dma_ranges[(3 + 2 + 2) * CFG_SYS_PCI_NR_INBOUND_WIN]; addrcell = fdt_getprop_u32_default(blob, "/", "#address-cells", 1); sizecell = fdt_getprop_u32_default(blob, "/", "#size-cells", 1); diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index c7968926a17..14fd3bbf679 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -16,9 +16,9 @@ #include #include "pci_internal.h" -/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ -#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE -#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 +/* the user can define CFG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ +#ifndef CFG_SYS_PCI_CACHE_LINE_SIZE +#define CFG_SYS_PCI_CACHE_LINE_SIZE 8 #endif static void dm_pciauto_setup_device(struct udevice *dev, @@ -178,7 +178,7 @@ static void dm_pciauto_setup_device(struct udevice *dev, dm_pci_write_config16(dev, PCI_COMMAND, cmdstat); dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE, - CONFIG_SYS_PCI_CACHE_LINE_SIZE); + CFG_SYS_PCI_CACHE_LINE_SIZE); dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80); } diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index a8f8c31bef8..4600652f2b1 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -343,8 +343,8 @@ static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie) static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie) { - phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; - pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; + phys_addr_t phys_start = CFG_SYS_PCI_MEMORY_PHYS; + pci_addr_t bus_start = CFG_SYS_PCI_MEMORY_BUS; u64 sz = min((u64)gd->ram_size, (1ull << 32)); pci_size_t pci_sz; int idx; @@ -367,8 +367,8 @@ static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie) sz = 2ull << __ilog2_u64(sz); fsl_pcie_setup_inbound_win(pcie, idx--, true, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI_MEMORY_BUS, sz); + CFG_SYS_PCI_MEMORY_PHYS, + CFG_SYS_PCI_MEMORY_BUS, sz); #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) /* * On 64-bit capable systems, set up a mapping for all of DRAM @@ -380,12 +380,12 @@ static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie) pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n", - (u64)CONFIG_SYS_PCI64_MEMORY_BUS, - (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz); + (u64)CFG_SYS_PCI64_MEMORY_BUS, + (u64)CFG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz); fsl_pcie_setup_inbound_win(pcie, idx--, true, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz); + CFG_SYS_PCI_MEMORY_PHYS, + CFG_SYS_PCI64_MEMORY_BUS, pci_sz); #endif return 0; diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index 70c5f4e4cff..ba84a232b83 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -28,16 +28,16 @@ #define DBI_RO_WR_EN 0x8bc -#ifndef CONFIG_SYS_PCI_MEMORY_BUS -#define CONFIG_SYS_PCI_MEMORY_BUS 0 +#ifndef CFG_SYS_PCI_MEMORY_BUS +#define CFG_SYS_PCI_MEMORY_BUS 0 #endif -#ifndef CONFIG_SYS_PCI_MEMORY_PHYS -#define CONFIG_SYS_PCI_MEMORY_PHYS 0 +#ifndef CFG_SYS_PCI_MEMORY_PHYS +#define CFG_SYS_PCI_MEMORY_PHYS 0 #endif -#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) -#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024) +#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CFG_SYS_PCI64_MEMORY_BUS) +#define CFG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024) #endif #define PEX_CSR0_LTSSM_MASK 0xFC diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 8cdf516d9fa..a52774179e2 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -13,20 +13,20 @@ #include #include -#ifndef CONFIG_SYS_PCI_MEMORY_BUS -#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE +#ifndef CFG_SYS_PCI_MEMORY_BUS +#define CFG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE #endif -#ifndef CONFIG_SYS_PCI_MEMORY_PHYS -#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE +#ifndef CFG_SYS_PCI_MEMORY_PHYS +#define CFG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE #endif -#ifndef CONFIG_SYS_PCI_MEMORY_SIZE -#define CONFIG_SYS_PCI_MEMORY_SIZE SZ_4G +#ifndef CFG_SYS_PCI_MEMORY_SIZE +#define CFG_SYS_PCI_MEMORY_SIZE SZ_4G #endif -#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE -#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR +#ifndef CFG_SYS_PCI_EP_MEMORY_BASE +#define CFG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR #endif #define PCIE_PHYS_SIZE 0x200000000 diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index f2813aeef67..ff26a5cd9be 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -72,7 +72,7 @@ static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf) u32 vf_flag = 0; u64 phys = 0; - phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M; + phys = CFG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M; phys = ALIGN(phys, PCIE_BAR0_SIZE); /* ATU 0 : INBOUND : map BAR0 */ @@ -117,8 +117,8 @@ static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf) /* ATU: OUTBOUND : map MEM */ ls_pcie_atu_outbound_set(pcie, pf, PCIE_ATU_TYPE_MEM, (u64)pcie_ep->addr_res.start + - pf * CONFIG_SYS_PCI_MEMORY_SIZE, - 0, CONFIG_SYS_PCI_MEMORY_SIZE); + pf * CFG_SYS_PCI_MEMORY_SIZE, + 0, CFG_SYS_PCI_MEMORY_SIZE); } /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */ diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c index 6ecdd6af408..021c975869f 100644 --- a/drivers/pci/pcie_layerscape_gen4.c +++ b/drivers/pci/pcie_layerscape_gen4.c @@ -333,7 +333,7 @@ static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf) if ((!pcie->sriov_support && pf > LS_G4_PF0) || pf > LS_G4_PF1) return; - phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf; + phys = CFG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf; for (bar = 0; bar < PF_BAR_NUM; bar++) { ls_pcie_g4_ep_inbound_win_set(pcie, pf, bar, phys); phys += PCIE_BAR_SIZE; @@ -342,8 +342,8 @@ static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf) /* OUTBOUND: map MEM */ ls_pcie_g4_outbound_win_set(pcie, pf, PAB_AXI_TYPE_MEM, pcie->cfg_res.start + - CONFIG_SYS_PCI_MEMORY_SIZE * pf, 0x0, - CONFIG_SYS_PCI_MEMORY_SIZE); + CFG_SYS_PCI_MEMORY_SIZE * pf, 0x0, + CFG_SYS_PCI_MEMORY_SIZE); val = ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf)); val &= ~FUNC_NUM_PCIE_MASK; diff --git a/drivers/pci/pcie_layerscape_gen4.h b/drivers/pci/pcie_layerscape_gen4.h index 483eb538b5c..805c23a7da0 100644 --- a/drivers/pci/pcie_layerscape_gen4.h +++ b/drivers/pci/pcie_layerscape_gen4.h @@ -11,12 +11,12 @@ #include #include -#ifndef CONFIG_SYS_PCI_MEMORY_SIZE -#define CONFIG_SYS_PCI_MEMORY_SIZE (4 * 1024 * 1024 * 1024ULL) +#ifndef CFG_SYS_PCI_MEMORY_SIZE +#define CFG_SYS_PCI_MEMORY_SIZE (4 * 1024 * 1024 * 1024ULL) #endif -#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE -#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR +#ifndef CFG_SYS_PCI_EP_MEMORY_BASE +#define CFG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR #endif #define PCIE_PF_NUM 2 diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 059885ecb54..0e70b2853b2 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -177,15 +177,15 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 - -#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 +#define CFG_SYS_PCIE1_CFG_BASE 0xA0000000 +#define CFG_SYS_PCIE1_CFG_SIZE 0x08000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xA8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xB8000000 + +#define CFG_SYS_PCIE2_CFG_BASE 0xC0000000 +#define CFG_SYS_PCIE2_CFG_SIZE 0x08000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xC8000000 +#define CFG_SYS_PCIE2_IO_PHYS 0xD8000000 /* * TSEC diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index c29e63c54ed..c59a37646f4 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -254,31 +254,31 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCI1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCI1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCI1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CFG_SYS_PCI1_IO_VIRT 0xe2000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull +#define CFG_SYS_PCI1_IO_PHYS 0xfe2000000ull #else -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CFG_SYS_PCI1_IO_PHYS 0xe2000000 #endif #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 +#define CFG_SYS_PCIE1_IO_VIRT 0xe3000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull +#define CFG_SYS_PCIE1_IO_PHYS 0xfe3000000ull #else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xe3000000 #endif #endif diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 05c097759f6..f87e7597ad0 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -68,31 +68,31 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CFG_SYS_PCIE1_IO_VIRT 0xffc00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull +#define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#define CFG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif /* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CFG_SYS_PCIE2_IO_VIRT 0xffc10000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull #else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#define CFG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif #endif diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index c8329810786..e996dbaa4de 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -234,20 +234,20 @@ */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull /* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull /* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e21639a6951..6d6e334bf00 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -331,24 +331,24 @@ #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #endif #endif /* CONFIG_PCI */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index a3d04882f0d..423ba816170 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -307,30 +307,30 @@ #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #endif /* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull +#define CFG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc30000000ull #endif #endif /* CONFIG_PCI */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 72052be78a9..2efc2eb95c4 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -345,24 +345,24 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull /* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull /* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull +#define CFG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index c798e4487a4..ca8bfac0c69 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -299,24 +299,24 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull /* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull /* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull +#define CFG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 5777df8e507..091920dccfe 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -107,24 +107,24 @@ */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull /* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull /* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CFG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc60000000ull /* * Miscellaneous configurable options diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 7af65737ff0..1df90def673 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -346,10 +346,10 @@ int get_scl(void); * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull #define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 44e608536fe..6e8ac1b98df 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -343,31 +343,31 @@ */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CFG_SYS_PCIE2_IO_VIRT 0xffc10000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull #else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#define CFG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif /* controller 1, Slot 2, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CFG_SYS_PCIE1_IO_VIRT 0xffc00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull +#define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#define CFG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif #endif /* CONFIG_PCI */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 9b106fc1c97..a60ac6d1a3c 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -109,8 +109,8 @@ * Memory space is mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CFG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCI1_IO_PHYS 0xE2000000 #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "TSEC0" -- cgit v1.3.1 From 2db82bf2bd8fa5de2b55ad7c4c1c0afa58f171c2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:34 -0500 Subject: Convert CONFIG_SYS_PMAN et al to Kconfig This converts the following to Kconfig: CONFIG_NOBQFMAN CONFIG_SYS_DPAA_DCE CONFIG_SYS_DPAA_FMAN CONFIG_SYS_DPAA_PME CONFIG_SYS_DPAA_RMAN CONFIG_SYS_PMAN Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/Kconfig.nxp | 3 ++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 ++ .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 8 ++--- arch/arm/cpu/armv8/fsl-layerscape/icid.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/Kconfig | 35 ++++++++++++++++++++++ include/configs/P2041RDB.h | 4 --- include/configs/T102xRDB.h | 2 -- include/configs/T104xRDB.h | 3 -- include/configs/T208xQDS.h | 6 ---- include/configs/T208xRDB.h | 6 ---- include/configs/T4240RDB.h | 6 ---- include/configs/kmcent2.h | 3 -- include/configs/ls1043a_common.h | 1 - include/configs/ls1046a_common.h | 1 - 16 files changed, 45 insertions(+), 41 deletions(-) (limited to 'include') diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index 8c5a6f63a9a..805fe934a1f 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -251,3 +251,6 @@ config QIXIS_I2C_ACCESS config HAS_FSL_DR_USB def_bool y depends on USB_EHCI_HCD && PPC + +config SYS_DPAA_FMAN + bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index ebca11d1741..2862257e1f2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -69,6 +69,7 @@ config ARCH_LS1043A select GICV2 select HAS_FSL_XHCI_USB if USB_HOST select SKIP_LOWLEVEL_INIT + select SYS_DPAA_FMAN select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -106,6 +107,7 @@ config ARCH_LS1046A select GICV2 select HAS_FSL_XHCI_USB if USB_HOST select SKIP_LOWLEVEL_INIT + select SYS_DPAA_FMAN select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 6440ce714fd..f18407b6d3b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -24,11 +24,7 @@ void get_sys_info(struct sys_info *sys_info) /* rcw_tmp is needed to get FMAN clock, or to get cluster group A * mux 2 clock for LS1043A/LS1046A. */ -#if defined(CONFIG_SYS_DPAA_FMAN) || \ - defined(CONFIG_ARCH_LS1046A) || \ - defined(CONFIG_ARCH_LS1043A) - u32 rcw_tmp; -#endif + __maybe_unused u32 rcw_tmp; struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR); unsigned int cpu; const u8 core_cplx_pll[8] = { @@ -96,7 +92,7 @@ void get_sys_info(struct sys_info *sys_info) #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) rcw_tmp = in_be32(&gur->rcwsr[7]); switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) { case 2: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index e972603f24f..ad20d71717b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -41,7 +41,7 @@ void set_icids(void) /* setup general icid offsets */ set_icid(icid_tbl, icid_tbl_sz); -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz); #endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c index 3bd993bebfb..4880a313ea6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -59,7 +59,7 @@ struct icid_id_table icid_tbl[] = { int icid_tbl_sz = ARRAY_SIZE(icid_tbl); -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) struct fman_icid_id_table fman_icid_tbl[] = { /* port id, icid */ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index abd847b5be0..e47d3af85e0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -58,7 +58,7 @@ struct icid_id_table icid_tbl[] = { int icid_tbl_sz = ARRAY_SIZE(icid_tbl); -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) struct fman_icid_id_table fman_icid_tbl[] = { /* port id, icid */ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 24d3f1f20c2..f2361560e9a 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -252,6 +252,8 @@ config TARGET_KMCENT2 bool "Support kmcent2" select VENDOR_KM select FSL_CORENET + select SYS_DPAA_FMAN + select SYS_DPAA_PME select SYS_L3_SIZE_256KB endchoice @@ -618,6 +620,9 @@ config ARCH_P2041 select E500MC select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN + select SYS_DPAA_PME + select SYS_DPAA_RMAN select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 select SYS_FSL_ERRATUM_A005275 @@ -762,6 +767,7 @@ config ARCH_T1024 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008109 @@ -792,6 +798,8 @@ config ARCH_T1040 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN + select SYS_DPAA_PME select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 @@ -822,6 +830,8 @@ config ARCH_T1042 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN + select SYS_DPAA_PME select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 @@ -851,6 +861,10 @@ config ARCH_T2080 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_DCE if !NOBQFMAN + select SYS_DPAA_FMAN if !NOBQFMAN + select SYS_DPAA_PME if !NOBQFMAN + select SYS_DPAA_RMAN if !NOBQFMAN select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 @@ -871,6 +885,7 @@ config ARCH_T2080 select SYS_FSL_SRIO_LIODN select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select SYS_FSL_USB_DUAL_PHY_ENABLE + select SYS_PMAN if !NOBQFMAN select SYS_PPC64 select FSL_IFC imply CMD_SATA @@ -886,6 +901,10 @@ config ARCH_T4240 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_DCE if !NOBQFMAN + select SYS_DPAA_FMAN if !NOBQFMAN + select SYS_DPAA_PME if !NOBQFMAN + select SYS_DPAA_RMAN if !NOBQFMAN select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004468 select SYS_FSL_ERRATUM_A005871 @@ -907,6 +926,7 @@ config ARCH_T4240 select SYS_FSL_SRIO_LIODN select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select SYS_FSL_USB_DUAL_PHY_ENABLE + select SYS_PMAN if !NOBQFMAN select SYS_PPC64 select FSL_IFC imply CMD_SATA @@ -947,6 +967,9 @@ config E6500 help Enable PowerPC E6500 core +config NOBQFMAN + bool + config FSL_LAW bool help @@ -1019,6 +1042,15 @@ config SYS_CCSRBAR_DEFAULT if changed by pre-boot regime. The value here must match the current value in SoC. If not sure, do not change. +config SYS_DPAA_PME + bool + +config SYS_DPAA_DCE + bool + +config SYS_DPAA_RMAN + bool + config A003399_NOR_WORKAROUND bool help @@ -1195,6 +1227,9 @@ config FSL_PCIE_DISABLE_ASPM config FSL_PCIE_RESET bool +config SYS_PMAN + bool + config SYS_FSL_RAID_ENGINE bool diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index e996dbaa4de..8c7b877bfb9 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -36,7 +36,6 @@ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ #define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_SYS_DPAA_RMAN /* RMan */ #ifndef __ASSEMBLY__ #include @@ -281,9 +280,6 @@ #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME - #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 6d6e334bf00..154b2f174af 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -395,8 +395,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 423ba816170..847cf65b409 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -366,9 +366,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_FMAN_ENET diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 2efc2eb95c4..b49c2647768 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -388,12 +388,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN /* RMan */ #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index ca8bfac0c69..aae41a33925 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -342,12 +342,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN /* RMan */ #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 091920dccfe..9dc45e397f9 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -340,12 +340,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 1df90def673..c8423fdfb0a 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -372,9 +372,6 @@ int get_scl(void); #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME - /* Qman / Bman */ /* RGMII (FM1@DTESC5) is local managemant interface */ #define CONFIG_SYS_RGMII2_PHY_ADDR 0x11 diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 6fc509af232..df6338298b4 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -103,7 +103,6 @@ /* FMan ucode */ #ifndef SPL_NO_FMAN -#define CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #endif diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 3934fbbb41d..b09588f4796 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -67,7 +67,6 @@ /* FMan ucode */ #ifndef SPL_NO_FMAN -#define CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #endif -- cgit v1.3.1 From f16b1a6c0082fc29371776096986d56c21851565 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:35 -0500 Subject: spl: Migrate SYS_SATA_FAT_BOOT_PARTITION to Kconfig This moves SYS_SATA_FAT_BOOT_PARTITION to Kconfig and enforces the current default via Kconfig rather than C code. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- common/spl/Kconfig | 5 +++++ common/spl/spl_sata.c | 4 ---- include/configs/imx6_spl.h | 5 ----- 3 files changed, 5 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/common/spl/Kconfig b/common/spl/Kconfig index fef01bdd7da..c6da4a403e9 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1232,6 +1232,11 @@ config SPL_SATA expense and power consumption. This enables loading from SATA using a configured device. +config SYS_SATA_FAT_BOOT_PARTITION + int "Partition on the SATA disk to load U-Boot from" + depends on SPL_SATA && SPL_FS_FAT + default 1 + config SPL_SATA_RAW_U_BOOT_USE_SECTOR bool "SATA raw mode: by sector" depends on SPL_SATA diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c index 9ae02730685..12397f0ae17 100644 --- a/common/spl/spl_sata.c +++ b/common/spl/spl_sata.c @@ -17,10 +17,6 @@ #include #include -#ifndef CONFIG_SYS_SATA_FAT_BOOT_PARTITION -#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 -#endif - #ifndef CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR /* Dummy value to make the compiler happy */ #define CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR 0x100 diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 3afe418b67d..f34988fdd74 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -10,11 +10,6 @@ /* MMC support */ -/* SATA support */ -#if defined(CONFIG_SPL_SATA) -#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 -#endif - #endif #endif -- cgit v1.3.1 From aec118ebe63f7f0ab60916f9906fb3cb680abf7a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:36 -0500 Subject: imx6/imx7: Remove now empty imx6_spl.h and imx7_spl.h There are now no flags being set in these files, so remove them. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- include/configs/apalis_imx6.h | 4 ---- include/configs/brppt2.h | 5 ----- include/configs/cl-som-imx7.h | 3 --- include/configs/cm_fx6.h | 3 --- include/configs/colibri_imx6.h | 4 ---- include/configs/dart_6ul.h | 3 --- include/configs/dh_imx6.h | 3 --- include/configs/display5.h | 2 -- include/configs/el6x_common.h | 4 ---- include/configs/embestmx6boards.h | 6 ------ include/configs/ge_b1x5v2.h | 2 -- include/configs/gw_ventana.h | 1 - include/configs/imx6-engicam.h | 5 ----- include/configs/imx6_logic.h | 4 ---- include/configs/imx6_spl.h | 15 --------------- include/configs/imx6dl-mamoj.h | 3 --- include/configs/imx6q-bosch-acc.h | 1 - include/configs/imx6ulz_smm_m2.h | 3 --- include/configs/imx7-cm.h | 3 --- include/configs/imx7_spl.h | 19 ------------------- include/configs/kontron-sl-mx6ul.h | 3 --- include/configs/kp_imx6q_tpc.h | 3 --- include/configs/liteboard.h | 3 --- include/configs/mccmon6.h | 2 -- include/configs/mx6cuboxi.h | 2 -- include/configs/mx6memcal.h | 1 - include/configs/mx6sabreauto.h | 4 ---- include/configs/mx6sabresd.h | 4 ---- include/configs/mx6slevk.h | 4 ---- include/configs/mx6sxsabresd.h | 4 ---- include/configs/mx6ul_14x14_evk.h | 3 --- include/configs/mys_6ulx.h | 3 --- include/configs/novena.h | 3 --- include/configs/npi_imx6ull.h | 3 --- include/configs/opos6uldev.h | 4 ---- include/configs/pcl063.h | 3 --- include/configs/pcl063_ull.h | 3 --- include/configs/pcm058.h | 4 ---- include/configs/pico-imx6.h | 8 -------- include/configs/pico-imx6ul.h | 7 ------- include/configs/pico-imx7d.h | 8 -------- include/configs/somlabs_visionsom_6ull.h | 4 ---- include/configs/tqma6.h | 7 ------- include/configs/udoo.h | 2 -- include/configs/udoo_neo.h | 2 -- include/configs/vining_2000.h | 4 ---- include/configs/wandboard.h | 2 -- include/configs/xpress.h | 3 --- 48 files changed, 196 deletions(-) delete mode 100644 include/configs/imx6_spl.h delete mode 100644 include/configs/imx7_spl.h (limited to 'include') diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 192c9cf0c30..30d32d27e3d 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -15,10 +15,6 @@ #include #include -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 0c7fe5f3abb..bdedf7ea2d7 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -86,9 +86,4 @@ BUR_COMMON_ENV \ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -/* SPL */ -#ifdef CONFIG_SPL -#include "imx6_spl.h" - -#endif /* CONFIG_SPL */ #endif /* __CONFIG_BRPP2_IMX6_H */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index cbf85341a64..fc45e597f6d 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -101,7 +101,4 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* SPL */ -#include "imx7_spl.h" - #endif /* __CONFIG_H */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 2cb09fa30da..25443629e20 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -143,9 +143,6 @@ /* misc */ -/* SPL */ -#include "imx6_spl.h" - /* Display */ #define CONFIG_IMX_HDMI diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 14fdf5b50e6..68d923c1ae1 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -15,10 +15,6 @@ #include #include -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index 6079596caec..b944d50663c 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -10,9 +10,6 @@ #include #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - /* NAND pin conflicts with usdhc2 */ #ifdef CONFIG_CMD_NAND #define CFG_SYS_FSL_USDHC_NUM 1 diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 54b2192b4a8..e694dd7551a 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -21,9 +21,6 @@ * 0x12_0000-0x1f_ffff ... UNUSED */ -/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ - /* Miscellaneous configurable options */ /* MMC Configs */ diff --git a/include/configs/display5.h b/include/configs/display5.h index eb65f17cbe4..0e5ecab9feb 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -34,8 +34,6 @@ #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 #define CONFIG_SYS_SPI_ARGS_SIZE 0x10000 -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART5_BASE /* I2C Configs */ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index affe20a1019..16d2648e11f 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -12,10 +12,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 555239b8e81..a4891ddbc4f 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -49,12 +49,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -/* RiOTboard */ - -#endif - /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, * 1M script, 1M pxe and the ramdisk at the end */ #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 176f80bb09b..c862f15ee2b 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -12,8 +12,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - /* PWM */ #define CONFIG_IMX6_PWM_PER_CLK 66000000 diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index a9ef35ebeb6..645ca162a35 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -13,7 +13,6 @@ /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ #include "mx6_common.h" /* Serial */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index e430efad42e..b8eb5c82cf7 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -142,9 +142,4 @@ # define CONFIG_IMX_VIDEO_SKIP #endif -/* SPL */ -#ifdef CONFIG_SPL -# include "imx6_spl.h" -#endif - #endif /* __IMX6_ENGICAM_CONFIG_H */ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 7760c8c418a..6b822e72505 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -11,10 +11,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #include "mx6_common.h" /* MMC Configs */ diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h deleted file mode 100644 index f34988fdd74..00000000000 --- a/include/configs/imx6_spl.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Gateworks Corporation - * Author: Tim Harvey - */ -#ifndef __IMX6_SPL_CONFIG_H -#define __IMX6_SPL_CONFIG_H - -#ifdef CONFIG_SPL - -/* MMC support */ - -#endif - -#endif diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index 909453cd66f..f7f8f33ed89 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -59,7 +59,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* SPL */ -#include "imx6_spl.h" - #endif /* __IMX6DL_MAMOJ_CONFIG_H */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 5025ad9d9f2..15171d7ad67 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -91,7 +91,6 @@ /* SPL */ #ifdef CONFIG_SPL -#include "imx6_spl.h" #ifdef CONFIG_SPL_BUILD #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index d42eb750d01..70b4b84215d 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -12,9 +12,6 @@ #include #include -/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART4_BASE #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index caa6a11d407..c6db5e943ee 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -83,7 +83,4 @@ #define CONFIG_USBD_HS -/* SPL */ -#include "imx7_spl.h" - #endif /* __CONFIG_H */ diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h deleted file mode 100644 index 362b98075f0..00000000000 --- a/include/configs/imx7_spl.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * SPL definitions for the i.MX7 SPL - * - * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com - * - * Author: Uri Mashiach - */ - -#ifndef __IMX7_SPL_CONFIG_H -#define __IMX7_SPL_CONFIG_H - -#ifdef CONFIG_SPL - -/* MMC support */ - -#endif /* CONFIG_SPL */ - -#endif /* __IMX7_SPL_CONFIG_H */ diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index d3447a80ca5..b3e1fc2a864 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -11,9 +11,6 @@ #include #include "mx6_common.h" -#ifdef CONFIG_SPL_BUILD -#include "imx6_spl.h" -#endif /* RAM */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 1823a793988..b0e49ad6df0 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -12,9 +12,6 @@ #include "mx6_common.h" -/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ - /* Miscellaneous configurable options */ /* FEC ethernet */ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index a784002158b..1d51b87b68b 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -13,9 +13,6 @@ #include #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 69ca7c52753..f9f0825f6f8 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -9,8 +9,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) /* diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index bc90b9563ad..1db4d6c01b1 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -11,8 +11,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index ad53f17d671..a6cefab5508 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -11,7 +11,6 @@ /* SPL */ #include "mx6_common.h" -#include "imx6_spl.h" #ifdef CONFIG_SERIAL_CONSOLE_UART1 #if defined(CONFIG_MX6SL) diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 8176566f3f6..3fdf829e968 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -8,10 +8,6 @@ #ifndef __MX6SABREAUTO_CONFIG_H #define __MX6SABREAUTO_CONFIG_H -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 49cd1512dc5..0d06b6dc467 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -8,10 +8,6 @@ #ifndef __MX6SABRESD_CONFIG_H #define __MX6SABRESD_CONFIG_H -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 26b97bd3f2e..ca1d077437b 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -10,10 +10,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* MMC Configs */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 83779f09bfc..c655671ee1b 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -12,10 +12,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE #ifdef CONFIG_IMX_BOOTAUX diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index d0e3d3f0284..65f0a5c9966 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -15,9 +15,6 @@ #define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) -/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index e18d16cc99c..273f938554d 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -10,9 +10,6 @@ #include #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - #define CFG_SYS_FSL_USDHC_NUM 1 /* Console configs */ diff --git a/include/configs/novena.h b/include/configs/novena.h index f2a04ca6185..9dc05d80ec2 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -34,9 +34,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ - /* I2C */ #define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 2a528850829..ea407c9f6f1 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -10,9 +10,6 @@ #include #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - #define CFG_SYS_FSL_USDHC_NUM 1 /* Console configs */ diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 3e551e13aa6..b3cdd2f1ebe 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -10,10 +10,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - /* Miscellaneous configurable options */ #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index bc04c508218..6267dc729ab 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -11,9 +11,6 @@ #include #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - /* * There is a bug in some i.MX6UL processors that results in the initial * portion of OCRAM being unavailable when booting from (at least) an SD diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 817fabfb97c..e13b5df0fab 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -13,9 +13,6 @@ #include #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - #define CFG_SYS_FSL_USDHC_NUM 2 /* Environment settings */ diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 01190904cf6..14cbfde28bf 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -6,10 +6,6 @@ #ifndef __PCM058_CONFIG_H #define __PCM058_CONFIG_H -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #include "mx6_common.h" #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 687133b9bdd..f95beeb214a 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -10,14 +10,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index d4f58b6a7b0..85772ba6e83 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -12,13 +12,6 @@ #include #include "mx6_common.h" #include -#include "imx6_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#endif /* Network support */ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 159bf4c68ca..b3a38d8a940 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -10,14 +10,6 @@ #include "mx7_common.h" -#include "imx7_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#endif - #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR /* MMC Config */ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 49672dfe7c3..dcb88a3a730 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -13,10 +13,6 @@ #include "mx6_common.h" #include -/* SPL options */ -#include "imx6_spl.h" - - /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 2c589158952..a65ebfb4dea 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -11,13 +11,6 @@ #include #include -/* SPL */ -/* #if defined(CONFIG_SPL_BUILD) */ -/* common IMX6 SPL configuration */ -#include "imx6_spl.h" - -/* #endif */ - /* place code in last 4 MiB of RAM */ #include "mx6_common.h" diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 8af5151c503..268c737e7eb 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -10,8 +10,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART2_BASE /* MMC Configuration */ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 093e2e8dae7..147224806fc 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -12,8 +12,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index a4484fd3f8c..a0846b3f7c9 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -10,10 +10,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 91c1f4b3b51..b4c757fd921 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -10,8 +10,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index fc8ec3204b1..7d0402feead 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -10,9 +10,6 @@ #include "mx6_common.h" #include -/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR /* MMC Configs */ -- cgit v1.3.1 From aa6e94deabb45154cea07ad44c4a5c047bca078b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:37 -0500 Subject: global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 2 +- arch/arc/lib/cache.c | 4 +- arch/arc/lib/cpu.c | 2 +- arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 +-- arch/arm/dts/rockchip-optee.dtsi | 4 +- arch/arm/include/asm/emif.h | 2 +- arch/arm/include/asm/iproc-common/configs.h | 2 +- arch/arm/mach-aspeed/ast2500/board_common.c | 2 +- arch/arm/mach-aspeed/ast2600/board_common.c | 2 +- arch/arm/mach-at91/arm920t/lowlevel_init.S | 48 +++++++++++----------- arch/arm/mach-at91/arm926ejs/lowlevel_init.S | 48 +++++++++++----------- arch/arm/mach-davinci/misc.c | 4 +- arch/arm/mach-exynos/dmc_init_ddr3.c | 2 +- arch/arm/mach-imx/imx8m/soc.c | 2 +- arch/arm/mach-imx/imx8ulp/soc.c | 2 +- arch/arm/mach-imx/mx6/litesom.c | 2 +- arch/arm/mach-imx/mx6/opos6ul.c | 2 +- arch/arm/mach-imx/spl.c | 2 +- arch/arm/mach-k3/common.c | 2 +- arch/arm/mach-k3/r5_mpu.c | 2 +- arch/arm/mach-keystone/ddr3.c | 2 +- arch/arm/mach-mediatek/mt7623/init.c | 4 +- arch/arm/mach-mediatek/mt7981/init.c | 2 +- arch/arm/mach-mediatek/mt7986/init.c | 2 +- arch/arm/mach-mvebu/alleycat5/cpu.c | 6 +-- arch/arm/mach-mvebu/arm64-common.c | 2 +- arch/arm/mach-mvebu/armada8k/dram.c | 2 +- arch/arm/mach-omap2/am33xx/board.c | 6 +-- arch/arm/mach-omap2/emif-common.c | 8 ++-- arch/arm/mach-omap2/sec-common.c | 4 +- arch/arm/mach-owl/soc.c | 2 +- arch/arm/mach-rockchip/sdram.c | 16 ++++---- arch/arm/mach-socfpga/board.c | 2 +- arch/arm/mach-sunxi/dram_helpers.c | 8 ++-- arch/arm/mach-sunxi/dram_suniv.c | 20 ++++----- arch/arm/mach-sunxi/dram_sunxi_dw.c | 6 +-- arch/arm/mach-tegra/board2.c | 4 +- arch/arm/mach-zynq/cpu.c | 2 +- arch/m68k/cpu/mcf532x/speed.c | 2 +- arch/m68k/include/asm/immap.h | 4 +- arch/m68k/lib/traps.c | 2 +- arch/mips/lib/traps.c | 2 +- arch/mips/mach-jz47xx/jz4780/jz4780.c | 2 +- arch/mips/mach-mscc/cpu.c | 8 ++-- arch/mips/mach-mscc/dram.c | 2 +- arch/mips/mach-mscc/include/mach/ddr.h | 2 +- arch/mips/mach-mtmips/mt7621/spl/start.S | 2 +- arch/mips/mach-octeon/dram.c | 2 +- arch/nios2/cpu/cpu.c | 2 +- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/mp.c | 2 +- arch/powerpc/cpu/mpc8xxx/pamu_table.c | 2 +- arch/powerpc/lib/bootm.c | 2 +- arch/sandbox/cpu/state.c | 2 +- arch/sandbox/dts/sandbox.dts | 2 +- arch/sandbox/dts/sandbox64.dts | 2 +- arch/sh/cpu/u-boot.lds | 2 +- arch/sh/lib/board.c | 4 +- arch/sh/lib/bootm.c | 2 +- arch/xtensa/cpu/cpu.c | 2 +- board/BuR/brppt1/board.c | 2 +- board/BuS/eb_cpu5282/eb_cpu5282.c | 20 ++++----- board/CZ.NIC/turris_mox/turris_mox.c | 2 +- board/Marvell/mvebu_alleycat-5/board.c | 2 +- board/Marvell/mvebu_armada-37xx/board.c | 2 +- board/Marvell/mvebu_armada-8k/board.c | 2 +- board/Marvell/octeontx/board.c | 2 +- board/Marvell/octeontx2/board.c | 2 +- board/Marvell/octeontx2_cn913x/board.c | 2 +- board/armltd/integrator/integrator.c | 6 +-- board/armltd/vexpress/vexpress_common.c | 2 +- board/astro/mcf5373l/mcf5373l.c | 12 +++--- board/atmel/at91sam9260ek/at91sam9260ek.c | 6 +-- board/atmel/at91sam9261ek/at91sam9261ek.c | 6 +-- board/atmel/at91sam9263ek/at91sam9263ek.c | 6 +-- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 6 +-- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 6 +-- board/atmel/at91sam9rlek/at91sam9rlek.c | 6 +-- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 6 +-- board/atmel/sam9x60ek/sam9x60ek.c | 6 +-- .../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 6 +-- board/atmel/sama5d2_icp/sama5d2_icp.c | 6 +-- board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c | 6 +-- board/atmel/sama5d3_xplained/sama5d3_xplained.c | 6 +-- board/atmel/sama5d3xek/sama5d3xek.c | 6 +-- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 6 +-- board/atmel/sama5d4ek/sama5d4ek.c | 6 +-- board/atmel/sama7g5ek/sama7g5ek.c | 6 +-- board/bluewater/gurnard/gurnard.c | 6 +-- board/bosch/guardian/board.c | 2 +- board/bosch/shc/board.c | 2 +- board/broadcom/bcm_ep/board.c | 8 ++-- board/calao/usb_a9263/usb_a9263.c | 6 +-- board/cobra5272/cobra5272.c | 2 +- board/compulab/cm_t43/cm_t43.c | 2 +- board/compulab/cm_t43/spl.c | 4 +- board/cssi/MCR3000/MCR3000.c | 2 +- board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c | 4 +- board/eets/pdu001/board.c | 2 +- board/egnite/ethernut5/ethernut5.c | 6 +-- board/emulation/qemu-arm/qemu-arm.c | 2 +- board/esd/meesc/meesc.c | 2 +- board/freescale/common/arm_sleep.c | 2 +- board/freescale/common/mpc85xx_sleep.c | 2 +- board/freescale/ls1012afrdm/ls1012afrdm.c | 4 +- board/freescale/ls1012aqds/ls1012aqds.c | 4 +- board/freescale/ls1012ardb/ls1012ardb.c | 4 +- board/freescale/ls1021aqds/ddr.c | 2 +- board/freescale/ls1021atsn/ls1021atsn.c | 2 +- board/freescale/ls1021atwr/ls1021atwr.c | 2 +- board/freescale/m5208evbe/m5208evbe.c | 26 ++++++------ board/freescale/m5235evb/m5235evb.c | 8 ++-- board/freescale/m5249evb/m5249evb.c | 2 +- board/freescale/m5253demo/m5253demo.c | 6 +-- board/freescale/m5272c3/m5272c3.c | 2 +- board/freescale/m5275evb/m5275evb.c | 18 ++++---- board/freescale/m5282evb/m5282evb.c | 8 ++-- board/freescale/m53017evb/README | 2 +- board/freescale/m53017evb/m53017evb.c | 26 ++++++------ board/freescale/m5329evb/m5329evb.c | 24 +++++------ board/freescale/m5373evb/README | 2 +- board/freescale/m5373evb/m5373evb.c | 24 +++++------ board/freescale/mpc837xerdb/mpc837xerdb.c | 6 +-- board/freescale/mx51evk/mx51evk.c | 2 +- board/freescale/p1_p2_rdb_pc/ddr.c | 2 +- board/friendlyarm/nanopi2/board.c | 8 ++-- board/gardena/smart-gateway-at91sam/board.c | 6 +-- board/gdsys/mpc8308/sdram.c | 6 +-- board/grinn/chiliboard/board.c | 2 +- board/imgtec/boston/ddr.c | 2 +- board/imgtec/malta/lowlevel_init.S | 4 +- board/imgtec/malta/malta.c | 2 +- board/imgtec/xilfpga/xilfpga.c | 2 +- board/inversepath/usbarmory/usbarmory.c | 2 +- board/isee/igep003x/board.c | 2 +- board/keymile/common/common.c | 4 +- board/keymile/km83xx/km83xx.c | 6 +-- board/keymile/pg-wcom-ls102xa/ddr.c | 2 +- board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 2 +- board/l+g/vinco/vinco.c | 6 +-- board/mediatek/mt7622/mt7622_rfb.c | 2 +- board/mediatek/mt7623/mt7623_rfb.c | 2 +- board/mediatek/mt7629/mt7629_rfb.c | 2 +- board/mediatek/mt8518/mt8518_ap1.c | 2 +- board/mscc/jr2/jr2.c | 2 +- board/mscc/luton/luton.c | 2 +- board/mscc/ocelot/ocelot.c | 2 +- board/mscc/serval/serval.c | 2 +- board/mscc/servalt/servalt.c | 2 +- board/phytec/phycore_am335x_r2/board.c | 4 +- board/phytium/pomelo/pomelo.c | 2 +- board/renesas/alt/alt.c | 2 +- board/renesas/blanche/blanche.c | 2 +- board/renesas/gose/gose.c | 2 +- board/renesas/grpeach/grpeach.c | 2 +- board/renesas/koelsch/koelsch.c | 2 +- board/renesas/lager/lager.c | 2 +- board/renesas/porter/porter.c | 2 +- board/renesas/silk/silk.c | 2 +- board/renesas/stout/stout.c | 2 +- board/ronetix/pm9g45/pm9g45.c | 10 ++--- board/samsung/arndale/arndale.c | 4 +- board/samsung/common/board.c | 4 +- board/sandbox/sandbox.c | 4 +- board/siemens/common/board.c | 2 +- board/siemens/corvus/board.c | 6 +-- board/siemens/iot2050/board.c | 2 +- board/siemens/smartweb/smartweb.c | 6 +-- board/siemens/taurus/taurus.c | 10 ++--- board/sipeed/maix/maix.c | 2 +- board/socrates/sdram.c | 4 +- board/softing/vining_fpga/socfpga.c | 2 +- board/solidrun/mx6cuboxi/mx6cuboxi.c | 4 +- board/sysam/amcore/amcore.c | 6 +-- board/sysam/stmark2/stmark2.c | 2 +- board/tbs/tbs2910/tbs2910.c | 2 +- board/tcl/sl50/board.c | 2 +- board/ti/am335x/board.c | 2 +- board/ti/am43xx/board.c | 2 +- board/ti/am57xx/board.c | 2 +- board/ti/am65x/evm.c | 4 +- board/ti/dra7xx/evm.c | 2 +- board/ti/j721e/evm.c | 4 +- board/ti/j721s2/evm.c | 4 +- board/ti/ks2_evm/board.c | 12 +++--- board/ti/ti816x/evm.c | 2 +- board/timll/devkit3250/devkit3250.c | 6 +-- board/toradex/apalis_imx6/apalis_imx6.c | 2 +- board/toradex/colibri_imx6/colibri_imx6.c | 2 +- board/vscom/baltos/board.c | 2 +- board/work-microwave/work_92105/work_92105.c | 6 +-- board/xilinx/zynq/board.c | 6 +-- board/xilinx/zynqmp/zynqmp.c | 8 ++-- boot/image-board.c | 4 +- cmd/ti/ddr3.c | 18 ++++---- common/board_f.c | 8 ++-- doc/arch/m68k.rst | 16 ++++---- doc/arch/nios2.rst | 4 +- drivers/ddr/fsl/arm_ddr_gen3.c | 2 +- drivers/ddr/fsl/fsl_ddr_gen4.c | 2 +- drivers/ddr/fsl/main.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 2 +- drivers/ddr/marvell/axp/ddr3_axp.h | 4 +- drivers/pci/Kconfig | 2 +- drivers/pci/pci-rcar-gen2.c | 4 +- drivers/pci/pci_sh7751.c | 6 +-- drivers/pci/pcie_dw_mvebu.c | 4 +- drivers/pci/pcie_layerscape.h | 4 +- drivers/ram/aspeed/sdram_ast2500.c | 4 +- drivers/ram/aspeed/sdram_ast2600.c | 6 +-- drivers/ram/mediatek/ddr3-mt7629.c | 12 +++--- drivers/ram/octeon/octeon_ddr.c | 2 +- drivers/ram/rockchip/dmc-rk3368.c | 12 +++--- drivers/ram/rockchip/sdram_common.c | 34 +++++++-------- drivers/ram/rockchip/sdram_px30.c | 2 +- drivers/ram/rockchip/sdram_rk3066.c | 14 +++---- drivers/ram/rockchip/sdram_rk3128.c | 2 +- drivers/ram/rockchip/sdram_rk3188.c | 14 +++---- drivers/ram/rockchip/sdram_rk322x.c | 24 +++++------ drivers/ram/rockchip/sdram_rk3288.c | 14 +++---- drivers/ram/rockchip/sdram_rk3308.c | 2 +- drivers/ram/rockchip/sdram_rk3328.c | 2 +- drivers/ram/rockchip/sdram_rk3399.c | 2 +- drivers/ram/rockchip/sdram_rk3568.c | 2 +- drivers/usb/host/ehci-rmobile.c | 4 +- drivers/video/sunxi/sunxi_display.c | 4 +- include/configs/10m50_devboard.h | 4 +- include/configs/3c120_devboard.h | 4 +- include/configs/M5208EVBE.h | 22 +++++----- include/configs/M5235EVB.h | 12 +++--- include/configs/M5249EVB.h | 12 +++--- include/configs/M5253DEMO.h | 12 +++--- include/configs/M5272C3.h | 12 +++--- include/configs/M5275EVB.h | 12 +++--- include/configs/M5282EVB.h | 12 +++--- include/configs/M53017EVB.h | 22 +++++----- include/configs/M5329EVB.h | 22 +++++----- include/configs/M5373EVB.h | 22 +++++----- include/configs/MCR3000.h | 4 +- include/configs/MPC837XERDB.h | 4 +- include/configs/MPC8548CDS.h | 2 +- include/configs/P1010RDB.h | 4 +- include/configs/P2041RDB.h | 4 +- include/configs/SBx81LIFKW.h | 2 +- include/configs/SBx81LIFXCAT.h | 2 +- include/configs/T102xRDB.h | 6 +-- include/configs/T104xRDB.h | 4 +- include/configs/T208xQDS.h | 4 +- include/configs/T208xRDB.h | 4 +- include/configs/T4240RDB.h | 4 +- include/configs/am62x_evm.h | 2 +- include/configs/am64x_evm.h | 2 +- include/configs/am65x_evm.h | 2 +- include/configs/amcore.h | 4 +- include/configs/ap121.h | 2 +- include/configs/ap143.h | 2 +- include/configs/ap152.h | 2 +- include/configs/apalis-imx8.h | 2 +- include/configs/apalis_imx6.h | 2 +- include/configs/arbel.h | 4 +- include/configs/aristainetos2.h | 2 +- include/configs/aspeed-common.h | 2 +- include/configs/astro_mcf5373l.h | 12 +++--- include/configs/at91sam9260ek.h | 4 +- include/configs/at91sam9261ek.h | 4 +- include/configs/at91sam9263ek.h | 28 ++++++------- include/configs/at91sam9m10g45ek.h | 4 +- include/configs/at91sam9n12ek.h | 4 +- include/configs/at91sam9rlek.h | 4 +- include/configs/at91sam9x5ek.h | 4 +- include/configs/ax25-ae350.h | 2 +- include/configs/axs10x.h | 4 +- include/configs/bcm947622.h | 2 +- include/configs/bcm94908.h | 2 +- include/configs/bcm94912.h | 2 +- include/configs/bcm963138.h | 2 +- include/configs/bcm963146.h | 2 +- include/configs/bcm963148.h | 2 +- include/configs/bcm963158.h | 2 +- include/configs/bcm963178.h | 2 +- include/configs/bcm96756.h | 2 +- include/configs/bcm96813.h | 2 +- include/configs/bcm96846.h | 2 +- include/configs/bcm96855.h | 2 +- include/configs/bcm96856.h | 2 +- include/configs/bcm96858.h | 2 +- include/configs/bcm96878.h | 2 +- include/configs/bcm_ns3.h | 2 +- include/configs/bcmstb.h | 2 +- include/configs/bitmain_antminer_s9.h | 4 +- include/configs/bk4r1.h | 2 +- include/configs/bmips_bcm3380.h | 2 +- include/configs/bmips_bcm6318.h | 2 +- include/configs/bmips_bcm63268.h | 2 +- include/configs/bmips_bcm6328.h | 2 +- include/configs/bmips_bcm6338.h | 2 +- include/configs/bmips_bcm6348.h | 2 +- include/configs/bmips_bcm6358.h | 2 +- include/configs/bmips_bcm6362.h | 2 +- include/configs/bmips_bcm6368.h | 2 +- include/configs/bmips_bcm6838.h | 2 +- include/configs/boston.h | 4 +- include/configs/brppt2.h | 2 +- include/configs/bur_am335x_common.h | 2 +- include/configs/capricorn-common.h | 2 +- include/configs/cgtqmx8.h | 2 +- include/configs/ci20.h | 2 +- include/configs/cl-som-imx7.h | 2 +- include/configs/cm_fx6.h | 2 +- include/configs/cobra5272.h | 12 +++--- include/configs/colibri-imx6ull.h | 2 +- include/configs/colibri-imx8x.h | 2 +- include/configs/colibri_imx6.h | 2 +- include/configs/colibri_imx7.h | 2 +- include/configs/colibri_vf.h | 2 +- include/configs/corstone1000.h | 2 +- include/configs/corvus.h | 4 +- include/configs/da850evm.h | 2 +- include/configs/dart_6ul.h | 2 +- include/configs/devkit3250.h | 4 +- include/configs/dh_imx6.h | 2 +- include/configs/display5.h | 2 +- include/configs/dragonboard410c.h | 2 +- include/configs/dragonboard820c.h | 2 +- include/configs/durian.h | 2 +- include/configs/ea-lpc3250devkitv2.h | 2 +- include/configs/eb_cpu5282.h | 14 +++---- include/configs/el6x_common.h | 2 +- include/configs/embestmx6boards.h | 2 +- include/configs/emsdp.h | 4 +- include/configs/espresso7420.h | 2 +- include/configs/ethernut5.h | 4 +- include/configs/exynos5-common.h | 16 ++++---- include/configs/exynos5250-common.h | 2 +- include/configs/exynos7420-common.h | 16 ++++---- include/configs/exynos78x0-common.h | 26 ++++++------ include/configs/gardena-smart-gateway-at91sam.h | 4 +- include/configs/gardena-smart-gateway-mt7688.h | 2 +- include/configs/gazerbeam.h | 6 +-- include/configs/ge_b1x5v2.h | 2 +- include/configs/ge_bx50v3.h | 2 +- include/configs/grpeach.h | 4 +- include/configs/gw_ventana.h | 2 +- include/configs/gxp.h | 2 +- include/configs/highbank.h | 2 +- include/configs/hikey.h | 2 +- include/configs/hikey960.h | 2 +- include/configs/hsdk-4xd.h | 4 +- include/configs/hsdk.h | 4 +- include/configs/imgtec_xilfpga.h | 4 +- include/configs/imx27lite-common.h | 2 +- include/configs/imx6-engicam.h | 2 +- include/configs/imx6_logic.h | 2 +- include/configs/imx6dl-mamoj.h | 2 +- include/configs/imx6q-bosch-acc.h | 2 +- include/configs/imx6ulz_smm_m2.h | 2 +- include/configs/imx7-cm.h | 2 +- include/configs/imx8mm-cl-iot-gate.h | 2 +- include/configs/imx8mm_beacon.h | 2 +- include/configs/imx8mm_data_modul_edm_sbc.h | 2 +- include/configs/imx8mm_evk.h | 2 +- include/configs/imx8mm_icore_mx8mm.h | 2 +- include/configs/imx8mm_venice.h | 2 +- include/configs/imx8mn_beacon.h | 2 +- include/configs/imx8mn_bsh_smm_s2_common.h | 2 +- include/configs/imx8mn_evk.h | 2 +- include/configs/imx8mn_var_som.h | 2 +- include/configs/imx8mn_venice.h | 2 +- include/configs/imx8mp_dhcom_pdk2.h | 2 +- include/configs/imx8mp_evk.h | 2 +- include/configs/imx8mp_icore_mx8mp.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/imx8mp_venice.h | 2 +- include/configs/imx8mq_cm.h | 2 +- include/configs/imx8mq_evk.h | 2 +- include/configs/imx8mq_phanbell.h | 2 +- include/configs/imx8qm_mek.h | 2 +- include/configs/imx8qm_rom7720.h | 2 +- include/configs/imx8qxp_mek.h | 2 +- include/configs/imx8ulp_evk.h | 2 +- include/configs/imx93_evk.h | 2 +- include/configs/integrator-common.h | 2 +- include/configs/iot_devkit.h | 14 +++---- include/configs/j721e_evm.h | 2 +- include/configs/j721s2_evm.h | 2 +- include/configs/km/km-mpc83xx.h | 4 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/kmcent2.h | 4 +- include/configs/kontron-sl-mx6ul.h | 2 +- include/configs/kontron-sl-mx8mm.h | 2 +- include/configs/kontron_pitx_imx8m.h | 2 +- include/configs/kontron_sl28.h | 2 +- include/configs/kp_imx53.h | 2 +- include/configs/kp_imx6q_tpc.h | 2 +- include/configs/legoev3.h | 2 +- include/configs/librem5.h | 2 +- include/configs/linkit-smart-7688.h | 2 +- include/configs/liteboard.h | 2 +- include/configs/ls1012a2g5rdb.h | 2 +- include/configs/ls1012a_common.h | 2 +- include/configs/ls1012afrdm.h | 2 +- include/configs/ls1012aqds.h | 2 +- include/configs/ls1012ardb.h | 2 +- include/configs/ls1021aiot.h | 2 +- include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atsn.h | 2 +- include/configs/ls1021atwr.h | 2 +- include/configs/ls1028a_common.h | 2 +- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- include/configs/ls1088a_common.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/lx2160a_common.h | 4 +- include/configs/m53menlo.h | 2 +- include/configs/malta.h | 6 +-- include/configs/maxbcm.h | 2 +- include/configs/mccmon6.h | 2 +- include/configs/meerkat96.h | 2 +- include/configs/meesc.h | 4 +- include/configs/meson64.h | 2 +- include/configs/microchip_mpfs_icicle.h | 2 +- include/configs/msc_sm2s_imx8mp.h | 2 +- include/configs/mt7620.h | 2 +- include/configs/mt7621.h | 2 +- include/configs/mt7622.h | 2 +- include/configs/mt7623.h | 2 +- include/configs/mt7628.h | 2 +- include/configs/mt7629.h | 2 +- include/configs/mt7981.h | 2 +- include/configs/mt7986.h | 2 +- include/configs/mt8518.h | 4 +- include/configs/mv-common.h | 2 +- include/configs/mvebu_alleycat-5.h | 2 +- include/configs/mvebu_armada-37xx.h | 2 +- include/configs/mvebu_armada-8k.h | 2 +- include/configs/mx23_olinuxino.h | 2 +- include/configs/mx23evk.h | 2 +- include/configs/mx28evk.h | 2 +- include/configs/mx51evk.h | 2 +- include/configs/mx53cx9020.h | 2 +- include/configs/mx53loco.h | 2 +- include/configs/mx53ppd.h | 2 +- include/configs/mx6cuboxi.h | 2 +- include/configs/mx6memcal.h | 2 +- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/mx6sllevk.h | 2 +- include/configs/mx6sxsabreauto.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/mx6ul_14x14_evk.h | 2 +- include/configs/mx6ullevk.h | 2 +- include/configs/mx7dsabresd.h | 2 +- include/configs/mx7ulp_com.h | 2 +- include/configs/mx7ulp_evk.h | 2 +- include/configs/mys_6ulx.h | 2 +- include/configs/nitrogen6x.h | 2 +- include/configs/nokia_rx51.h | 4 +- include/configs/novena.h | 2 +- include/configs/npi_imx6ull.h | 2 +- include/configs/nsim.h | 4 +- include/configs/o4-imx6ull-nano.h | 2 +- include/configs/octeon_common.h | 2 +- include/configs/octeontx2_common.h | 2 +- include/configs/octeontx_common.h | 2 +- include/configs/odroid.h | 4 +- include/configs/odroid_xu3.h | 2 +- include/configs/omapl138_lcdk.h | 2 +- include/configs/openpiton-riscv64.h | 2 +- include/configs/opos6uldev.h | 2 +- include/configs/origen.h | 4 +- include/configs/owl-common.h | 2 +- include/configs/p1_p2_rdb_pc.h | 8 ++-- include/configs/pcl063.h | 2 +- include/configs/pcl063_ull.h | 2 +- include/configs/pcm052.h | 2 +- include/configs/pcm058.h | 2 +- include/configs/peach-pi.h | 2 +- include/configs/peach-pit.h | 2 +- include/configs/phycore_imx8mm.h | 2 +- include/configs/phycore_imx8mp.h | 2 +- include/configs/pic32mzdask.h | 2 +- include/configs/pico-imx6.h | 2 +- include/configs/pico-imx6ul.h | 2 +- include/configs/pico-imx7d.h | 2 +- include/configs/pico-imx8mq.h | 2 +- include/configs/pm9261.h | 26 ++++++------ include/configs/pm9263.h | 26 ++++++------ include/configs/pm9g45.h | 4 +- include/configs/poleg.h | 2 +- include/configs/pomelo.h | 2 +- include/configs/presidio_asic.h | 2 +- include/configs/px30_common.h | 2 +- include/configs/qemu-arm.h | 2 +- include/configs/qemu-ppce500.h | 2 +- include/configs/qemu-riscv.h | 2 +- include/configs/r2dplus.h | 4 +- include/configs/rcar-gen2-common.h | 4 +- include/configs/rcar-gen3-common.h | 4 +- include/configs/rk3036_common.h | 2 +- include/configs/rk3066_common.h | 2 +- include/configs/rk3128_common.h | 2 +- include/configs/rk3188_common.h | 2 +- include/configs/rk322x_common.h | 2 +- include/configs/rk3288_common.h | 2 +- include/configs/rk3308_common.h | 2 +- include/configs/rk3328_common.h | 2 +- include/configs/rk3368_common.h | 2 +- include/configs/rk3399_common.h | 2 +- include/configs/rk3568_common.h | 2 +- include/configs/rpi.h | 4 +- include/configs/rv1108_common.h | 2 +- include/configs/s5p4418_nanopi2.h | 4 +- include/configs/s5p_goni.h | 4 +- include/configs/s5pc210_universal.h | 4 +- include/configs/sam9x60_curiosity.h | 4 +- include/configs/sam9x60ek.h | 4 +- include/configs/sama5d27_wlsom1_ek.h | 4 +- include/configs/sama5d2_icp.h | 4 +- include/configs/sama5d2_ptc_ek.h | 4 +- include/configs/sama5d3_xplained.h | 4 +- include/configs/sama5d3xek.h | 4 +- include/configs/sama5d4_xplained.h | 4 +- include/configs/sama5d4ek.h | 4 +- include/configs/sama7g5ek.h | 4 +- include/configs/sandbox.h | 4 +- include/configs/siemens-am33x-common.h | 2 +- include/configs/sifive-unleashed.h | 2 +- include/configs/sifive-unmatched.h | 2 +- include/configs/sipeed-maix.h | 4 +- include/configs/smartweb.h | 4 +- include/configs/smdk5420.h | 2 +- include/configs/smdkc100.h | 4 +- include/configs/smdkv310.h | 10 ++--- include/configs/smegw01.h | 2 +- include/configs/snapper9g45.h | 4 +- include/configs/sniper.h | 2 +- include/configs/socfpga_common.h | 2 +- include/configs/socfpga_soc64_common.h | 2 +- include/configs/socrates.h | 4 +- include/configs/somlabs_visionsom_6ull.h | 2 +- include/configs/stih410-b2260.h | 2 +- include/configs/stm32mp13_common.h | 2 +- include/configs/stm32mp15_common.h | 2 +- include/configs/stmark2.h | 14 +++---- include/configs/stv0991.h | 2 +- include/configs/sunxi-common.h | 8 ++-- include/configs/synquacer.h | 2 +- include/configs/taurus.h | 4 +- include/configs/tb100.h | 4 +- include/configs/tbs2910.h | 2 +- include/configs/tegra-common.h | 2 +- include/configs/theadorable.h | 2 +- include/configs/thunderx_88xx.h | 4 +- include/configs/ti814x_evm.h | 2 +- include/configs/ti816x_evm.h | 2 +- include/configs/ti_armv7_common.h | 2 +- include/configs/total_compute.h | 2 +- include/configs/tplink_wdr4300.h | 2 +- include/configs/tqma6.h | 2 +- include/configs/trats.h | 4 +- include/configs/trats2.h | 4 +- include/configs/turris_mox.h | 2 +- include/configs/udoo.h | 2 +- include/configs/udoo_neo.h | 2 +- include/configs/usb_a9263.h | 4 +- include/configs/usbarmory.h | 2 +- include/configs/vcoreiii.h | 8 ++-- include/configs/verdin-imx8mm.h | 2 +- include/configs/verdin-imx8mp.h | 2 +- include/configs/vexpress_aemv8.h | 2 +- include/configs/vexpress_common.h | 2 +- include/configs/vf610twr.h | 2 +- include/configs/vinco.h | 4 +- include/configs/vining_2000.h | 2 +- include/configs/vocore2.h | 2 +- include/configs/wandboard.h | 2 +- include/configs/warp7.h | 2 +- include/configs/work_92105.h | 4 +- include/configs/xea.h | 2 +- include/configs/xenguest_arm64.h | 2 +- include/configs/xilinx_zynqmp_mini_nand.h | 4 +- include/configs/xpress.h | 2 +- include/configs/xtfpga.h | 10 ++--- include/init.h | 4 +- include/system-constants.h | 2 +- post/drivers/memory.c | 2 +- test/dm/remoteproc.c | 6 +-- 589 files changed, 1197 insertions(+), 1197 deletions(-) (limited to 'include') diff --git a/README b/README index 5ab042a2def..b095937121b 100644 --- a/README +++ b/README @@ -1441,7 +1441,7 @@ Configuration Settings: the RAM base is not zero, or RAM is divided into banks, this variable needs to be recalcuated to get the address. -- CONFIG_SYS_SDRAM_BASE: +- CFG_SYS_SDRAM_BASE: Physical start address of SDRAM. _Must_ be 0 here. - CONFIG_SYS_FLASH_BASE: diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 4c696cb53a4..d97a5787424 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -476,9 +476,9 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) static void arc_ioc_setup(void) { /* IOC Aperture start is equal to DDR start */ - unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; + unsigned int ap_base = CFG_SYS_SDRAM_BASE; /* IOC Aperture size is equal to DDR size */ - long ap_size = CONFIG_SYS_SDRAM_SIZE; + long ap_size = CFG_SYS_SDRAM_SIZE; /* Unsupported configuration. See [ NOTE 2 ] for more details. */ if (!slc_exists()) diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c index 6b215206a27..15678579618 100644 --- a/arch/arc/lib/cpu.c +++ b/arch/arc/lib/cpu.c @@ -20,7 +20,7 @@ int arch_cpu_init(void) timer_init(); gd->cpu_clk = get_board_sys_clk(); - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; cache_init(); diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index b4d113dc1e0..954fa5f8b45 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -29,7 +29,7 @@ */ static void __secure ls1_save_ddr_head(void) { - const char *src = (const char *)CONFIG_SYS_SDRAM_BASE; + const char *src = (const char *)CFG_SYS_SDRAM_BASE; char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN); struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; int i; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index ef71e2cf2bc..bbaa91f0e10 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1441,7 +1441,7 @@ int dram_init_banksize(void) } #endif - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; @@ -1571,7 +1571,7 @@ void update_early_mmu_table(void) if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { mmu_change_region_attr( - CONFIG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_BASE, gd->ram_size, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | @@ -1579,7 +1579,7 @@ void update_early_mmu_table(void) PTE_TYPE_VALID); } else { mmu_change_region_attr( - CONFIG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_BASE, CONFIG_SYS_DDR_BLOCK1_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | diff --git a/arch/arm/dts/rockchip-optee.dtsi b/arch/arm/dts/rockchip-optee.dtsi index 328ba908450..d84c10cf436 100644 --- a/arch/arm/dts/rockchip-optee.dtsi +++ b/arch/arm/dts/rockchip-optee.dtsi @@ -32,8 +32,8 @@ arch = "arm"; os = "tee"; compression = "none"; - load = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>; - entry = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>; + load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; + entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; blob-ext { filename = "tee.bin"; diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 35424345bf0..2141a4581c7 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -583,7 +583,7 @@ (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\ (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\ (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\ - (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) + (CFG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) #define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h index 4733c0793c3..c63c27dac7e 100644 --- a/arch/arm/include/asm/iproc-common/configs.h +++ b/arch/arm/include/asm/iproc-common/configs.h @@ -12,6 +12,6 @@ #define CONFIG_IPROC /* Memory Info */ -#define CONFIG_SYS_SDRAM_BASE 0x61000000 +#define CFG_SYS_SDRAM_BASE 0x61000000 #endif /* __IPROC_COMMON_CONFIGS_H */ diff --git a/arch/arm/mach-aspeed/ast2500/board_common.c b/arch/arm/mach-aspeed/ast2500/board_common.c index aca20022312..bae10271844 100644 --- a/arch/arm/mach-aspeed/ast2500/board_common.c +++ b/arch/arm/mach-aspeed/ast2500/board_common.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/arch/arm/mach-aspeed/ast2600/board_common.c b/arch/arm/mach-aspeed/ast2600/board_common.c index 82ff21908f2..dc6cdc35d15 100644 --- a/arch/arm/mach-aspeed/ast2600/board_common.c +++ b/arch/arm/mach-aspeed/ast2600/board_common.c @@ -54,7 +54,7 @@ int board_init(void) int i = 0, rc; struct udevice *dev; - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; while (1) { rc = uclass_get_device(UCLASS_MISC, i++, &dev); diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S index 57e51c81059..3b91a0cba33 100644 --- a/arch/arm/mach-at91/arm920t/lowlevel_init.S +++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S @@ -114,38 +114,38 @@ SMRDATA1: .word CONFIG_SYS_SDRC_CR_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL1 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM1 - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM1 + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL SMRDATA1E: /* SMRDATA1 is 176 bytes long */ #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S index c51eee2f17e..ecfe589e455 100644 --- a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S +++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S @@ -201,38 +201,38 @@ SMRDATA1: .word CONFIG_SYS_SDRC_MDR_VAL .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL1 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL1 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL3 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL4 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL5 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL6 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL7 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL8 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL9 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL2 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL3 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL4 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL5 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL6 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL7 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL8 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL9 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL4 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL10 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL10 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL5 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL11 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL11 .word AT91_ASM_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL12 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL12 /* User reset enable*/ .word AT91_ASM_RSTC_MR .word CONFIG_SYS_RSTC_RMR_VAL diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 73fdd1f2432..42078b39f8a 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -26,14 +26,14 @@ int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, + (void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c index fa867f27f30..cad8ccc5315 100644 --- a/arch/arm/mach-exynos/dmc_init_ddr3.c +++ b/arch/arm/mach-exynos/dmc_init_ddr3.c @@ -236,7 +236,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) * better have similar timings, since there's only a single adjustment that is * shared by both chips). */ -const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE; +const unsigned int test_addr = CFG_SYS_SDRAM_BASE; /* Test pattern with which RAM will be tested */ static const unsigned int test_pattern[] = { diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index a4863281e36..8050406613d 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -178,7 +178,7 @@ static unsigned int imx8m_find_dram_entry_in_mem_map(void) int i; for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++) - if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE) + if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE) return i; hang(); /* Entry not found, this must never happen. */ diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 802cb0e2ba8..5d95fb89a61 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -373,7 +373,7 @@ static unsigned int imx8ulp_find_dram_entry_in_mem_map(void) int i; for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++) - if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE) + if (imx8ulp_arm64_mem_map[i].phys == CFG_SYS_SDRAM_BASE) return i; hang(); /* Entry not found, this must never happen. */ diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c index 699a3dc317f..2ba3245e226 100644 --- a/arch/arm/mach-imx/mx6/litesom.c +++ b/arch/arm/mach-imx/mx6/litesom.c @@ -172,7 +172,7 @@ static void spl_dram_init(void) * Get actual RAM size, so we can adjust DDR row size for <512M * memories */ - ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M); + ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M); if (ram_size < SZ_512M) { mem_ddr.rowaddr = 14; mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c index e9d78740a15..38ead8ace20 100644 --- a/arch/arm/mach-imx/mx6/opos6ul.c +++ b/arch/arm/mach-imx/mx6/opos6ul.c @@ -44,7 +44,7 @@ static int setup_fec(void) int board_init(void) { /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_FEC_MXC setup_fec(); diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 6b8f4115c4e..cb9801b7a13 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -349,7 +349,7 @@ void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = imx_ddr_size(); return 0; diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 227706e8dca..d5e1f8e2e78 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -561,7 +561,7 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) void spl_enable_dcache(void) { #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) - phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; + phys_addr_t ram_top = CFG_SYS_SDRAM_BASE; dram_init(); diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c index 3d2ff6775a3..2aec96277e6 100644 --- a/arch/arm/mach-k3/r5_mpu.c +++ b/arch/arm/mach-k3/r5_mpu.c @@ -24,7 +24,7 @@ struct mpu_region_config k3_mpu_regions[16] = { O_I_WB_RD_WR_ALLOC, REGION_8MB}, /* U-Boot's code area marking it as WB and Write allocate */ - {CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW, + {CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, REGION_2GB}, /* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */ {0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 53117c2695c..ea7d0b903cf 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -318,7 +318,7 @@ void ddr3_init_ecc(u32 base, u32 ddr3_size) } ddr3_ecc_init_range(base); - ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size); + ddr3_reset_data(CFG_SYS_SDRAM_BASE, ddr3_size); /* mapping DDR3 ECC system interrupt from CIC2 to GIC */ #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c index 5d837e05971..988b057e598 100644 --- a/arch/arm/mach-mediatek/mt7623/init.c +++ b/arch/arm/mach-mediatek/mt7623/init.c @@ -25,7 +25,7 @@ int dram_init(void) { u32 i; - if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) && + if (((size_t)preloader_param >= CFG_SYS_SDRAM_BASE) && ((size_t)preloader_param % sizeof(size_t) == 0) && preloader_param->magic == BOOT_ARGUMENT_MAGIC && preloader_param->dram_rank_num <= @@ -35,7 +35,7 @@ int dram_init(void) for (i = 0; i < preloader_param->dram_rank_num; i++) gd->ram_size += preloader_param->dram_rank_size[i]; } else { - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, SZ_2G); } diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c index a8955064e03..d8b10f03580 100644 --- a/arch/arm/mach-mediatek/mt7981/init.c +++ b/arch/arm/mach-mediatek/mt7981/init.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G); return 0; } diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c index cf89e63e80a..fb74b2f34d7 100644 --- a/arch/arm/mach-mediatek/mt7986/init.c +++ b/arch/arm/mach-mediatek/mt7986/init.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G); return 0; } diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index cc7f9794c54..8204d962751 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -21,8 +21,8 @@ DECLARE_GLOBAL_DATA_PTR; static struct mm_region ac5_mem_map[] = { { /* RAM */ - .phys = CONFIG_SYS_SDRAM_BASE, - .virt = CONFIG_SYS_SDRAM_BASE, + .phys = CFG_SYS_SDRAM_BASE, + .virt = CFG_SYS_SDRAM_BASE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, @@ -102,7 +102,7 @@ int alleycat5_dram_init_banksize(void) /* * Config single DRAM bank */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index e3098a7ca87..2c94f899f37 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - unsigned long top = CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE); + unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE); return (gd->ram_top > top) ? top : gd->ram_top; } diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c index bab375e18ac..6c801bfa1db 100644 --- a/arch/arm/mach-mvebu/armada8k/dram.c +++ b/arch/arm/mach-mvebu/armada8k/dram.c @@ -38,7 +38,7 @@ int a8k_dram_init_banksize(void) */ phys_size_t max_bank0_size = SZ_4G - SZ_1G; - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size <= max_bank0_size) { gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 44d5214a3df..86755d6d954 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -72,14 +72,14 @@ int dram_init(void) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, + (void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; @@ -520,7 +520,7 @@ void board_init_f(ulong dummy) sdram_init(); /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, + (void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); } #endif diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index 312f868fbc7..a6a97af37d7 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -389,7 +389,7 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) /* Set region1 memory with 0 */ rgn_start = (regs->emif_ecc_address_range_1 & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; - rgn = rgn_start + CONFIG_SYS_SDRAM_BASE; + rgn = rgn_start + CFG_SYS_SDRAM_BASE; size = (regs->emif_ecc_address_range_1 & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start; @@ -400,7 +400,7 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) /* Set region2 memory with 0 */ rgn_start = (regs->emif_ecc_address_range_2 & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; - rgn = rgn_start + CONFIG_SYS_SDRAM_BASE; + rgn = rgn_start + CFG_SYS_SDRAM_BASE; size = (regs->emif_ecc_address_range_2 & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start; @@ -1340,7 +1340,7 @@ void dmm_init(u32 base) mapped_size = 0; section_cnt = 3; - sys_addr = CONFIG_SYS_SDRAM_BASE; + sys_addr = CFG_SYS_SDRAM_BASE; emif1_size = get_emif_mem_size(EMIF1_BASE); emif2_size = get_emif_mem_size(EMIF2_BASE); debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); @@ -1568,7 +1568,7 @@ void sdram_init(void) size_prog = log_2_n_round_down(size_prog); size_prog = (1 << size_prog); - size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + size_detect = get_ram_size((long *)CFG_SYS_SDRAM_BASE, size_prog); /* Compare with the size programmed */ if (size_detect != size_prog) { diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 0551bc125e8..0f9b915ea3d 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -198,11 +198,11 @@ u32 get_sec_mem_start(void) */ if (sec_mem_start == 0) sec_mem_start = - (CONFIG_SYS_SDRAM_BASE + ( + (CFG_SYS_SDRAM_BASE + ( #if defined(CONFIG_OMAP54XX) omap_sdram_size() #else - get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + get_ram_size((void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE) #endif - sec_mem_size)); diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index 4baef2eed3e..f0f46f2dcb7 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -50,7 +50,7 @@ int dram_init(void) /* This is called after dram_init() so use get_ram_size result */ int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 12f1d7ee563..e086c47f3c0 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -37,7 +37,7 @@ struct tos_parameter_t { int dram_init_banksize(void) { - size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE), + size_t top = min((unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE), (unsigned long)(gd->ram_top)); #ifdef CONFIG_ARM64 @@ -48,26 +48,26 @@ int dram_init_banksize(void) #ifdef CONFIG_SPL_OPTEE_IMAGE struct tos_parameter_t *tos_parameter; - tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE + + tos_parameter = (struct tos_parameter_t *)(CFG_SYS_SDRAM_BASE + TRUST_PARAMETER_OFFSET); if (tos_parameter->tee_mem.flags == 1) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr - - CONFIG_SYS_SDRAM_BASE; + - CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + tos_parameter->tee_mem.size; gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; } else { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x8400000; /* Reserve 32M for OPTEE with TA */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE + gd->bd->bi_dram[0].size + 0x2000000; gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; } #else - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; #endif #endif @@ -207,7 +207,7 @@ int dram_init(void) phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; + unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; return (gd->ram_top > top) ? top : gd->ram_top; } diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index b49006c6c8a..09e09192fba 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -46,7 +46,7 @@ void s_init(void) { int board_init(void) { /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index 2c873192e60..cdf2750f1c5 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -33,11 +33,11 @@ void mctl_await_completion(u32 *reg, u32 mask, u32 val) bool mctl_mem_matches(u32 offset) { /* Try to write different values to RAM at two addresses */ - writel(0, CONFIG_SYS_SDRAM_BASE); - writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); + writel(0, CFG_SYS_SDRAM_BASE); + writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset); dsb(); /* Check if the same value is actually observed when reading back */ - return readl(CONFIG_SYS_SDRAM_BASE) == - readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); + return readl(CFG_SYS_SDRAM_BASE) == + readl((ulong)CFG_SYS_SDRAM_BASE + offset); } #endif diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c index 56c2d557ff1..3aa3ce76272 100644 --- a/arch/arm/mach-sunxi/dram_suniv.c +++ b/arch/arm/mach-sunxi/dram_suniv.c @@ -175,9 +175,9 @@ static int sdr_readpipe_scan(void) u32 k = 0; for (k = 0; k < 32; k++) - writel(k, CONFIG_SYS_SDRAM_BASE + 4 * k); + writel(k, CFG_SYS_SDRAM_BASE + 4 * k); for (k = 0; k < 32; k++) { - if (readl(CONFIG_SYS_SDRAM_BASE + 4 * k) != k) + if (readl(CFG_SYS_SDRAM_BASE + 4 * k) != k) return 0; } return 1; @@ -266,11 +266,11 @@ static u32 dram_get_dram_size(struct dram_para *para) dram_para_setup(para); dram_scan_readpipe(para); for (i = 0; i < 32; i++) { - *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11; - *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22; + *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11; + *((u8 *)(CFG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22; } for (i = 0; i < 32; i++) { - val1 = *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)); + val1 = *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)); if (val1 == 0x22) count++; } @@ -283,11 +283,11 @@ static u32 dram_get_dram_size(struct dram_para *para) para->row_width = rowflag; dram_para_setup(para); if (colflag == 10) { - addr1 = CONFIG_SYS_SDRAM_BASE + 0x400000; - addr2 = CONFIG_SYS_SDRAM_BASE + 0xc00000; + addr1 = CFG_SYS_SDRAM_BASE + 0x400000; + addr2 = CFG_SYS_SDRAM_BASE + 0xc00000; } else { - addr1 = CONFIG_SYS_SDRAM_BASE + 0x200000; - addr2 = CONFIG_SYS_SDRAM_BASE + 0x600000; + addr1 = CFG_SYS_SDRAM_BASE + 0x200000; + addr2 = CFG_SYS_SDRAM_BASE + 0x600000; } for (i = 0; i < 32; i++) { *((u8 *)(addr1 + i)) = 0x33; @@ -319,7 +319,7 @@ static u32 dram_get_dram_size(struct dram_para *para) static void simple_dram_check(void) { - volatile u32 *dram = (u32 *)CONFIG_SYS_SDRAM_BASE; + volatile u32 *dram = (u32 *)CFG_SYS_SDRAM_BASE; int i; for (i = 0; i < 0x40; i++) diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 9107b114df5..4af5922f334 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -711,7 +711,7 @@ static unsigned long mctl_calc_rank_size(struct rank_para *rank) */ static void mctl_r40_detect_rank_count(struct dram_para *para) { - ulong rank1_base = (ulong) CONFIG_SYS_SDRAM_BASE + + ulong rank1_base = (ulong) CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]); struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; @@ -744,10 +744,10 @@ static void mctl_r40_detect_rank_count(struct dram_para *para) static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para) { - mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE, ¶->ranks[0]); + mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE, ¶->ranks[0]); if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) { - mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]); + mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]); } } diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 82d3d335028..54bbd8a776e 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -370,7 +370,7 @@ int dram_init_banksize(void) /* fall back to default DRAM bank size computation */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); #ifdef CONFIG_PCI @@ -412,5 +412,5 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) /* fall back to default usable RAM computation */ - return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); + return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); } diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index ac595ee0a27..3b6518c71c9 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -54,7 +54,7 @@ int arch_cpu_init(void) writel(0x757BDF0D, &devcfg_base->unlock); writel(0xFFFFFFFF, &devcfg_base->rom_shadow); -#if (CONFIG_SYS_SDRAM_BASE == 0) +#if (CFG_SYS_SDRAM_BASE == 0) /* remap DDR to zero, FILTERSTART */ writel(0, &scu_base->filter_start); diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c index e2985792d96..dac2229f72e 100644 --- a/arch/m68k/cpu/mcf532x/speed.c +++ b/arch/m68k/cpu/mcf532x/speed.c @@ -239,7 +239,7 @@ int clock_pll(int fsys, int flags) * software workaround for SDRAM opeartion after exiting LIMP * mode errata */ - out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE); + out_be32(sdram_workaround, CFG_SYS_SDRAM_BASE); #endif /* wait for DQS logic to relock */ diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index f2eb6fcb463..672aa0bb14e 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -338,9 +338,9 @@ #ifdef CONFIG_PCI #define CFG_SYS_PCI_BAR0 (0x40000000) -#define CFG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE) #define CFG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) -#define CFG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE) #endif #endif /* CONFIG_M547x */ diff --git a/arch/m68k/lib/traps.c b/arch/m68k/lib/traps.c index 0c2c1a99655..28fe803928e 100644 --- a/arch/m68k/lib/traps.c +++ b/arch/m68k/lib/traps.c @@ -62,7 +62,7 @@ static void trap_init(ulong value) { int arch_initr_trap(void) { - trap_init(CONFIG_SYS_SDRAM_BASE); + trap_init(CFG_SYS_SDRAM_BASE); return 0; } diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 7577fdd25d7..7a682f256a6 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -135,7 +135,7 @@ void trap_restore(void) int arch_initr_trap(void) { - trap_init(CONFIG_SYS_SDRAM_BASE); + trap_init(CFG_SYS_SDRAM_BASE); return 0; } diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c index cff98b0a770..15d1eff2ba7 100644 --- a/arch/mips/mach-jz47xx/jz4780/jz4780.c +++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c @@ -78,7 +78,7 @@ void board_init_f(ulong dummy) phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - return CONFIG_SYS_SDRAM_BASE + (256 * 1024 * 1024); + return CFG_SYS_SDRAM_BASE + (256 * 1024 * 1024); } int print_cpuinfo(void) diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c index 5bc31006aa1..d484eb92c41 100644 --- a/arch/mips/mach-mscc/cpu.c +++ b/arch/mips/mach-mscc/cpu.c @@ -17,16 +17,16 @@ DECLARE_GLOBAL_DATA_PTR; -#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M +#if CFG_SYS_SDRAM_SIZE <= SZ_64M #define MSCC_RAM_TLB_SIZE SZ_64M #define MSCC_ATTRIB2 MMU_REGIO_INVAL -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M +#elif CFG_SYS_SDRAM_SIZE <= SZ_128M #define MSCC_RAM_TLB_SIZE SZ_64M #define MSCC_ATTRIB2 MMU_REGIO_RW -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M +#elif CFG_SYS_SDRAM_SIZE <= SZ_256M #define MSCC_RAM_TLB_SIZE SZ_256M #define MSCC_ATTRIB2 MMU_REGIO_INVAL -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M +#elif CFG_SYS_SDRAM_SIZE <= SZ_512M #define MSCC_RAM_TLB_SIZE SZ_256M #define MSCC_ATTRIB2 MMU_REGIO_RW #else diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c index c53a4202e0d..f7fbd33cc4b 100644 --- a/arch/mips/mach-mscc/dram.c +++ b/arch/mips/mach-mscc/dram.c @@ -67,6 +67,6 @@ int print_cpuinfo(void) int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index d52eabbd2b1..75fb3ca00d2 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -13,7 +13,7 @@ #include #define MIPS_VCOREIII_MEMORY_DDR3 -#define MIPS_VCOREIII_DDR_SIZE CONFIG_SYS_SDRAM_SIZE +#define MIPS_VCOREIII_DDR_SIZE CFG_SYS_SDRAM_SIZE #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) /* Serval1 Refboard */ diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S index 3cad3567e72..6b9f253952a 100644 --- a/arch/mips/mach-mtmips/mt7621/spl/start.S +++ b/arch/mips/mach-mtmips/mt7621/spl/start.S @@ -18,7 +18,7 @@ #include "dram.h" #ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ +#define CONFIG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \ CONFIG_SYS_INIT_SP_OFFSET) #endif diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 9c5789b1c8e..85cb084c13f 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -81,7 +81,7 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) { if (IS_ENABLED(CONFIG_RAM_OCTEON)) { /* Map a maximum of 256MiB - return not size but address */ - return CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, + return CFG_SYS_SDRAM_BASE + min(gd->ram_size, UBOOT_RAM_SIZE_MAX); } else { return gd->ram_top; diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 4dd9c10faa5..85544503a5e 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -73,7 +73,7 @@ static int nios_cpu_setup(void *ctx, struct event *event) if (ret) return ret; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #ifndef CONFIG_ROM_STUBS copy_exception_trampoline(); #endif diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index e12043b2609..6d1c6b055c6 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -288,7 +288,7 @@ long int spd_sdram() /* * Set up LAWBAR for all of DDR. */ - ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; + ecm->bar = CFG_SYS_SDRAM_BASE & 0xfffff000; ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); debug("DDR:bar=0x%08x\n", ecm->bar); debug("DDR:ar=0x%08x\n", ecm->ar); diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index b0363c9c102..6acd31d2847 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -424,7 +424,7 @@ int dram_init(void) defined(CONFIG_ARCH_QEMU_E500) gd->ram_size = fsl_ddr_sdram_size(); #else - gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = (phys_size_t)CFG_SYS_SDRAM_SIZE * 1024 * 1024; #endif return 0; diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index f109ecb9ff7..44f8ed8a19a 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -195,7 +195,7 @@ u32 determine_mp_bootpg(unsigned int *pagesize) /* use last 4K of mapped memory */ bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? CONFIG_MAX_MEM_MAPPED : gd->ram_size) + - CONFIG_SYS_SDRAM_BASE - 4096; + CFG_SYS_SDRAM_BASE - 4096; if (pagesize) *pagesize = 4096; diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index d917e9dfb62..71496ab294d 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -16,7 +16,7 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) int j; tbl->start_addr[i] = - (uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE); + (uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE); tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED)); tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 8ae8d8a3e7d..1df0822e9d7 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -126,7 +126,7 @@ void arch_lmb_reserve(struct lmb *lmb) #ifdef DEBUG if (((u64)bootmap_base + bootm_size) > - (CONFIG_SYS_SDRAM_BASE + (u64)gd->ram_size)) + (CFG_SYS_SDRAM_BASE + (u64)gd->ram_size)) puts("WARNING: bootm_low + bootm_size exceed total memory\n"); if ((bootmap_base + bootm_size) > get_effective_memsize()) puts("WARNING: bootm_low + bootm_size exceed eff. memory\n"); diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index a681e472ab6..dd7978cfced 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -448,7 +448,7 @@ int state_init(void) { state = &main_state; - state->ram_size = CONFIG_SYS_SDRAM_SIZE; + state->ram_size = CFG_SYS_SDRAM_SIZE; state->ram_buf = os_malloc(state->ram_size); if (!state->ram_buf) { printf("Out of memory\n"); diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 2051207f0ba..88b57bfb7e5 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -25,7 +25,7 @@ }; memory { - reg = <0 CONFIG_SYS_SDRAM_SIZE>; + reg = <0 CFG_SYS_SDRAM_SIZE>; }; reserved-memory { diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts index 3eb04570891..a9cd7908f83 100644 --- a/arch/sandbox/dts/sandbox64.dts +++ b/arch/sandbox/dts/sandbox64.dts @@ -21,7 +21,7 @@ }; memory { - reg = /bits/ 64 <0 CONFIG_SYS_SDRAM_SIZE>; + reg = /bits/ 64 <0 CFG_SYS_SDRAM_SIZE>; }; reserved-memory { diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds index 85ee547b4aa..d360eea7eba 100644 --- a/arch/sh/cpu/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -18,7 +18,7 @@ OUTPUT_ARCH(sh) MEMORY { - ram : ORIGIN = CONFIG_SYS_SDRAM_BASE, LENGTH = CONFIG_SYS_SDRAM_SIZE + ram : ORIGIN = CFG_SYS_SDRAM_BASE, LENGTH = CFG_SYS_SDRAM_SIZE } ENTRY(_start) diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 3fa093a02ea..b31fa6d7031 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -11,8 +11,8 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index a5fad6c46c7..b205e5e3db1 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -88,7 +88,7 @@ int do_bootm_linux(int flag, int argc, char *const argv[], set_sh_linux_param((unsigned long)param + ORIG_ROOT_DEV, 0x0200); set_sh_linux_param((unsigned long)param + LOADER_TYPE, 0x0001); set_sh_linux_param((unsigned long)param + INITRD_START, - GET_INITRD_START(images->rd_start, CONFIG_SYS_SDRAM_BASE)); + GET_INITRD_START(images->rd_start, CFG_SYS_SDRAM_BASE)); set_sh_linux_param((unsigned long)param + INITRD_SIZE, images->rd_end - images->rd_start); } diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c index a09e103fc1d..98d9753b7e3 100644 --- a/arch/xtensa/cpu/cpu.c +++ b/arch/xtensa/cpu/cpu.c @@ -45,7 +45,7 @@ int print_cpuinfo(void) int arch_cpu_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c index c8dc186cddf..36945bbdccf 100644 --- a/board/BuR/brppt1/board.c +++ b/board/BuR/brppt1/board.c @@ -150,7 +150,7 @@ int board_init(void) #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c index 2b08930af6f..f9a37e7215c 100644 --- a/board/BuS/eb_cpu5282/eb_cpu5282.c +++ b/board/BuS/eb_cpu5282/eb_cpu5282.c @@ -40,8 +40,8 @@ int dram_init(void) MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 | MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4); asm (" nop"); -#ifdef CONFIG_SYS_SDRAM_BASE0 - MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE0)| +#ifdef CFG_SYS_SDRAM_BASE0 + MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE0)| MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) | MCFSDRAMC_DACR_PS_32; asm (" nop"); @@ -54,7 +54,7 @@ int dram_init(void) for (i = 0; i < 10; i++) asm (" nop"); - *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0) = 0xA5A5A5A5; + *(unsigned long *)(CFG_SYS_SDRAM_BASE0) = 0xA5A5A5A5; asm (" nop"); MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; asm (" nop"); @@ -65,12 +65,12 @@ int dram_init(void) MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; asm (" nop"); /* write SDRAM mode register */ - *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5; + *(unsigned long *)(CFG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5; asm (" nop"); - size += CONFIG_SYS_SDRAM_SIZE0 * 1024 * 1024; + size += CFG_SYS_SDRAM_SIZE0 * 1024 * 1024; #endif -#ifdef CONFIG_SYS_SDRAM_BASE1xx - MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1) +#ifdef CFG_SYS_SDRAM_BASE1xx + MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SYS_SDRAM_BASE1) | MCFSDRAMC_DACR_CASL (1) | MCFSDRAMC_DACR_CBM (3) | MCFSDRAMC_DACR_PS_16; @@ -79,15 +79,15 @@ int dram_init(void) MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP; - *(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5; + *(unsigned short *) (CFG_SYS_SDRAM_BASE1) = 0xA5A5; MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE; for (i = 0; i < 2000; i++) asm (" nop"); MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS; - *(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5; - size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024; + *(unsigned int *) (CFG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5; + size += CFG_SYS_SDRAM_SIZE1 * 1024 * 1024; #endif gd->ram_size = size; diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index ff1c4cb1707..a52a032e4d5 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -139,7 +139,7 @@ int board_fix_fdt(void *blob) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c index 619cd6c6cd3..0c4f8e03b85 100644 --- a/board/Marvell/mvebu_alleycat-5/board.c +++ b/board/Marvell/mvebu_alleycat-5/board.c @@ -7,7 +7,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index c6ecc323bb9..45fe3e5f0bd 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -80,7 +80,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/Marvell/mvebu_armada-8k/board.c b/board/Marvell/mvebu_armada-8k/board.c index 77c7dd7ab0e..a8899af6e5a 100644 --- a/board/Marvell/mvebu_armada-8k/board.c +++ b/board/Marvell/mvebu_armada-8k/board.c @@ -150,7 +150,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/Marvell/octeontx/board.c b/board/Marvell/octeontx/board.c index 059ebf8f172..224653519b9 100644 --- a/board/Marvell/octeontx/board.c +++ b/board/Marvell/octeontx/board.c @@ -63,7 +63,7 @@ int timer_init(void) int dram_init(void) { gd->ram_size = smc_dram_size(0); - gd->ram_size -= CONFIG_SYS_SDRAM_BASE; + gd->ram_size -= CFG_SYS_SDRAM_BASE; mem_map_fill(); return 0; diff --git a/board/Marvell/octeontx2/board.c b/board/Marvell/octeontx2/board.c index 63aa2d61349..e7899f49f0c 100644 --- a/board/Marvell/octeontx2/board.c +++ b/board/Marvell/octeontx2/board.c @@ -105,7 +105,7 @@ int timer_init(void) int dram_init(void) { gd->ram_size = smc_dram_size(0); - gd->ram_size -= CONFIG_SYS_SDRAM_BASE; + gd->ram_size -= CFG_SYS_SDRAM_BASE; mem_map_fill(); diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c index 953e9db9c8e..3d20cfb2fab 100644 --- a/board/Marvell/octeontx2_cn913x/board.c +++ b/board/Marvell/octeontx2_cn913x/board.c @@ -34,7 +34,7 @@ int board_early_init_r(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 4959a7fd6dc..ad02cf16da5 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -137,7 +137,7 @@ int misc_init_r (void) int dram_init (void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; #ifdef CONFIG_CM_SPD_DETECT { extern void dram_query(void); @@ -160,12 +160,12 @@ extern void dram_query(void); * */ sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; - gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + + gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE + REMAPPED_FLASH_SZ, 0x01000000 << sdram_shift); } #else - gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + + gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE + REMAPPED_FLASH_SZ, PHYS_SDRAM_1_SIZE); #endif /* CM_SPD_DETECT */ diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 1c830192653..763131c217e 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -73,7 +73,7 @@ static void flash__init(void) int dram_init(void) { gd->ram_size = - get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); + get_ram_size((long *)CFG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c index 3e2f79a1cf4..43563c41279 100644 --- a/board/astro/mcf5373l/mcf5373l.c +++ b/board/astro/mcf5373l/mcf5373l.c @@ -39,12 +39,12 @@ int dram_init(void) * GPIO configuration for bus should be set correctly from reset, * so we do not care! First, set up address space: at this point, * we should be running from internal SRAM; - * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM, + * so use CFG_SYS_SDRAM_BASE as the base address for SDRAM, * and do not care where it is */ - __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, + __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, &sdp->cs0); - __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, + __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, &sdp->cs1); /* * I am not sure from the data sheet, but it seems burst length @@ -72,7 +72,7 @@ int dram_init(void) */ __raw_writel(0x71462C00, &sdp->ctrl); /* Dummy write to start SDRAM */ - writel(0, CONFIG_SYS_SDRAM_BASE); + writel(0, CFG_SYS_SDRAM_BASE); #endif /* @@ -82,8 +82,8 @@ int dram_init(void) * (Do not rely on the SDCS register(s) being set to 0x00000000 * during reset as stated in the data sheet.) */ - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - 0x80000000 - CONFIG_SYS_SDRAM_BASE); + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, + 0x80000000 - CFG_SYS_SDRAM_BASE); return 0; } diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index d2c6ada6683..b8e02f45903 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -81,7 +81,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND at91sam9260ek_nand_hw_init(); @@ -92,8 +92,8 @@ int board_init(void) int dram_init(void) { gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 2992353199f..eab3a130819 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -156,7 +156,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK; #endif /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND at91sam9261ek_nand_hw_init(); @@ -176,8 +176,8 @@ int board_eth_init(struct bd_info *bis) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index b2b70930805..15f20b62f67 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -95,7 +95,7 @@ int board_init(void) /* arch number of AT91SAM9263EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK; /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND at91sam9263ek_nand_hw_init(); @@ -108,8 +108,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 2f3a772b81f..f53c1cf612d 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -168,7 +168,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK; /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND at91sam9m10g45ek_nand_hw_init(); @@ -181,8 +181,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 546851953a1..a3e294c88fc 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -99,7 +99,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_NAND_ATMEL at91sam9n12ek_nand_hw_init(); @@ -114,8 +114,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index bca7c8d9af5..11725f778b7 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -93,7 +93,7 @@ int board_init(void) /* arch number of AT91SAM9RLEK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK; /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND at91sam9rlek_nand_hw_init(); @@ -104,7 +104,7 @@ int board_init(void) int dram_init(void) { gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 817aa2fef70..ab666b6be34 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -115,7 +115,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK; /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND at91sam9x5ek_nand_hw_init(); @@ -129,8 +129,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 786de18f8c6..a3e35f30666 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -120,7 +120,7 @@ int misc_init_r(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND sam9x60ek_nand_hw_init(); @@ -130,7 +130,7 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 6524867708a..6e41017af17 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -65,7 +65,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; rgb_leds_init(); @@ -84,8 +84,8 @@ int misc_init_r(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index 02077700282..fabe492715a 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -54,7 +54,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; rgb_leds_init(); @@ -63,8 +63,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c index 16e9183f541..854715ea226 100644 --- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c +++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -115,7 +115,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; rgb_leds_init(); @@ -130,8 +130,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index a778f2694df..ce73a801e50 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -94,7 +94,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_NAND_ATMEL sama5d3_xplained_nand_hw_init(); @@ -110,8 +110,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index 008f1db6b0e..660a6b9d583 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -147,7 +147,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_NAND_ATMEL sama5d3xek_nand_hw_init(); @@ -166,8 +166,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 4058594e4de..780aba15ab1 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -121,7 +121,7 @@ int misc_init_r(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_NAND_ATMEL sama5d4_xplained_nand_hw_init(); @@ -135,8 +135,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index ef5a8a0d5cc..2226906a3b3 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -107,7 +107,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_NAND_ATMEL sama5d4ek_nand_hw_init(); @@ -121,8 +121,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c index 7d83e76f9ac..295fd079dcf 100644 --- a/board/atmel/sama7g5ek/sama7g5ek.c +++ b/board/atmel/sama7g5ek/sama7g5ek.c @@ -67,7 +67,7 @@ int misc_init_r(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; board_leds_init(); @@ -76,7 +76,7 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c index 35c74ba9dd2..9b42299b080 100644 --- a/board/bluewater/gurnard/gurnard.c +++ b/board/bluewater/gurnard/gurnard.c @@ -307,7 +307,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260; /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND ret = gurnard_nand_hw_init(); @@ -407,8 +407,8 @@ int board_eth_init(struct bd_info *bis) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c index bdf8d06add8..c31e2c86a2d 100644 --- a/board/bosch/guardian/board.c +++ b/board/bosch/guardian/board.c @@ -182,7 +182,7 @@ int board_init(void) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_MTD_RAW_NAND gpmc_init(); diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c index a7a9775fdf4..e3a9c00e809 100644 --- a/board/bosch/shc/board.c +++ b/board/bosch/shc/board.c @@ -449,7 +449,7 @@ int board_init(void) if (read_eeprom() < 0) puts("EEPROM Content Invalid.\n"); - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND) gpmc_init(); #endif diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c index 6064eb43db1..e91fa40e640 100644 --- a/board/broadcom/bcm_ep/board.c +++ b/board/broadcom/bcm_ep/board.c @@ -26,7 +26,7 @@ int board_init(void) * Address of boot parameters passed to kernel * Use default offset 0x100 */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } @@ -36,14 +36,14 @@ int board_init(void) */ int dram_init(void) { - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c index c89ad0bfe3d..3d31776d484 100644 --- a/board/calao/usb_a9263/usb_a9263.c +++ b/board/calao/usb_a9263/usb_a9263.c @@ -95,7 +95,7 @@ static void usb_a9263_macb_hw_init(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND usb_a9263_nand_hw_init(); @@ -111,8 +111,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c index 3e2418866c7..69a9df94231 100644 --- a/board/cobra5272/cobra5272.c +++ b/board/cobra5272/cobra5272.c @@ -28,7 +28,7 @@ int dram_init(void) /* Dummy write to start SDRAM */ *((volatile unsigned long *) 0) = 0; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; return 0; }; diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c index bcfe1bfaf67..5df378a62e3 100644 --- a/board/compulab/cm_t43/cm_t43.c +++ b/board/compulab/cm_t43/cm_t43.c @@ -45,7 +45,7 @@ int power_init_board(void) int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; gpmc_init(); set_i2c_pin_mux(); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); diff --git a/board/compulab/cm_t43/spl.c b/board/compulab/cm_t43/spl.c index e67bf81ee3a..a6223a477fe 100644 --- a/board/compulab/cm_t43/spl.c +++ b/board/compulab/cm_t43/spl.c @@ -119,7 +119,7 @@ void sdram_init(void) unsigned long ram_size; config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); - ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + ram_size = get_ram_size((long int *)CFG_SYS_SDRAM_BASE, 0x80000000); if (ram_size == 0x80000000 || ram_size == 0x40000000 || ram_size == 0x20000000) @@ -127,7 +127,7 @@ void sdram_init(void) ddr3_emif_regs.sdram_config = 0x638453B2; config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); - ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + ram_size = get_ram_size((long int *)CFG_SYS_SDRAM_BASE, 0x80000000); if (ram_size == 0x08000000) return; diff --git a/board/cssi/MCR3000/MCR3000.c b/board/cssi/MCR3000/MCR3000.c index c20e8714949..e95e04a30a6 100644 --- a/board/cssi/MCR3000/MCR3000.c +++ b/board/cssi/MCR3000/MCR3000.c @@ -114,7 +114,7 @@ int dram_init(void) out_be32(&memctl->memc_mcr, 0x80002038); udelay(200); - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE); return 0; diff --git a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c index 72cf46c749f..2b03e4891d9 100644 --- a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c +++ b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c @@ -29,13 +29,13 @@ board_early_init_f(void) int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x2000; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x2000; return 0; } int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_64M); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_64M); return 0; } diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c index 1054837d434..648d77fd21e 100644 --- a/board/eets/pdu001/board.c +++ b/board/eets/pdu001/board.c @@ -286,7 +286,7 @@ int board_init(void) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index a5d79d8e3e1..913c2ea1664 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -85,8 +85,8 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } @@ -135,7 +135,7 @@ int board_init(void) at91_periph_clk_enable(ATMEL_ID_PIOC); /* Set adress of boot parameters. */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Initialize UARTs and power management. */ ethernut5_power_init(); #ifdef CONFIG_CMD_NAND diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index 16237e29e46..3df3e41c0b2 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -126,7 +126,7 @@ void *board_fdt_blob_setup(int *err) { *err = 0; /* QEMU loads a generated DTB for us at the start of RAM. */ - return (void *)CONFIG_SYS_SDRAM_BASE; + return (void *)CFG_SYS_SDRAM_BASE; } void enable_caches(void) diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 98043b020c5..2304e9e8ec3 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -264,7 +264,7 @@ int board_init(void) meesc_ethercat_hw_init(); /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND meesc_nand_hw_init(); diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index f5bed6c35bb..46ffd817b44 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -61,7 +61,7 @@ static void dp_ddr_restore(void) /* get the address of ddr date from SPARECR3 */ src = (u64 *)in_le32(&scfg->sparecr[2]); - dst = (u64 *)CONFIG_SYS_SDRAM_BASE; + dst = (u64 *)CFG_SYS_SDRAM_BASE; for (i = 0; i < DDR_BUFF_LEN / 8; i++) *dst++ = *src++; diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c index 71922aab4ef..d3323b9ec1e 100644 --- a/board/freescale/common/mpc85xx_sleep.c +++ b/board/freescale/common/mpc85xx_sleep.c @@ -50,7 +50,7 @@ static void dp_ddr_restore(void) /* get the address of ddr date from SPARECR3 */ src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8); - dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8); + dst = (u64 *)(CFG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8); for (i = 0; i < DDR_BUFF_LEN / 8; i++) *dst-- = *src--; diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index bc37c553a5b..f2b8750a3f3 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -102,7 +102,7 @@ int dram_init(void) else gd->ram_size = SYS_SDRAM_SIZE_512; #else - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #endif } return 0; @@ -139,7 +139,7 @@ int dram_init(void) gd->ram_size = SYS_SDRAM_SIZE_512; } #else - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #endif mmdc_init(&mparam); diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 3f70fbc3565..f17a6c186d3 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -66,7 +66,7 @@ int dram_init(void) { gd->ram_size = tfa_get_dram_size(); if (!gd->ram_size) - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } @@ -90,7 +90,7 @@ int dram_init(void) }; mmdc_init(&mparam); - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 456609d9932..62c935e4d3e 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -113,7 +113,7 @@ int dram_init(void) { gd->ram_size = tfa_get_dram_size(); if (!gd->ram_size) - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } @@ -140,7 +140,7 @@ int dram_init(void) mmdc_init(&mparam); #endif - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 66fe1519cc6..4e70acc5a0c 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -192,7 +192,7 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c index 4325439be95..d144f25c623 100644 --- a/board/freescale/ls1021atsn/ls1021atsn.c +++ b/board/freescale/ls1021atsn/ls1021atsn.c @@ -47,7 +47,7 @@ static void ddrmc_init(void) if (is_warm_boot()) { out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); - out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); out_be32(&ddr->init_ext_addr, (1 << 31)); /* DRAM VRef will not be trained */ diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 33027ad0575..8b74d458237 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -162,7 +162,7 @@ void ddrmc_init(void) if (is_warm_boot()) { out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); - out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); out_be32(&ddr->init_ext_addr, (1 << 31)); /* DRAM VRef will not be trained */ diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c index 7bfb4557dd5..6125c9e13aa 100644 --- a/board/freescale/m5208evbe/m5208evbe.c +++ b/board/freescale/m5208evbe/m5208evbe.c @@ -29,7 +29,7 @@ int dram_init(void) sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -37,35 +37,35 @@ int dram_init(void) } i--; - out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); -#ifdef CONFIG_SYS_SDRAM_BASE1 - out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); +#ifdef CFG_SYS_SDRAM_BASE1 + out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i); #endif - out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); udelay(500); /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); asm("nop"); /* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); asm("nop"); /* Issue LEMR */ - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); asm("nop"); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); asm("nop"); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); asm("nop"); out_be32(&sdram->ctrl, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); asm("nop"); udelay(100); diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c index e7c7a94036b..44161a0b0a1 100644 --- a/board/freescale/m5235evb/m5235evb.c +++ b/board/freescale/m5235evb/m5235evb.c @@ -44,7 +44,7 @@ int dram_init(void) GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3)); - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) break; @@ -61,7 +61,7 @@ int dram_init(void) /* Initialize DACR0 */ out_be32(&sdram->dacr0, - SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | + SDRAMC_DARCn_BA(CFG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32); asm("nop"); @@ -80,7 +80,7 @@ int dram_init(void) } /* Write to this block to initiate precharge */ - *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696; + *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xA5A59696; /* Set RE (bit 15) in DACR */ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE); @@ -95,7 +95,7 @@ int dram_init(void) asm("nop"); /* Write to the SDRAM Mode Register */ - *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; + *(u32 *) (CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; } gd->ram_size = dramsize; diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c index 48c00791114..efff0551409 100644 --- a/board/freescale/m5249evb/m5249evb.c +++ b/board/freescale/m5249evb/m5249evb.c @@ -86,7 +86,7 @@ int dram_init(void) mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; return 0; }; diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 85f5f0c0340..179a2a242a8 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -47,7 +47,7 @@ int dram_init(void) __asm__("nop"); /* Initialize DMR0 */ - dramsize = (CONFIG_SYS_SDRAM_SIZE << 20); + dramsize = (CFG_SYS_SDRAM_SIZE << 20); temp = (dramsize - 1) & 0xFFFC0000; mbar_writeLong(MCFSIM_DMR0, temp | 1); __asm__("nop"); @@ -57,7 +57,7 @@ int dram_init(void) __asm__("nop"); /* Write to this block to initiate precharge */ - *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; + *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xa5a5a5a5; mb(); __asm__("nop"); @@ -74,7 +74,7 @@ int dram_init(void) mbar_readLong(MCFSIM_DACR0) | 0x0040); __asm__("nop"); - *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; + *(u32 *) (CFG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; mb(); } diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c index 9580cf2a039..3c20a23385c 100644 --- a/board/freescale/m5272c3/m5272c3.c +++ b/board/freescale/m5272c3/m5272c3.c @@ -30,7 +30,7 @@ int dram_init(void) /* Dummy write to start SDRAM */ *((volatile unsigned long *)0) = 0; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; return 0; }; diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c index 1c4fb7232af..00fa35ca5f7 100644 --- a/board/freescale/m5275evb/m5275evb.c +++ b/board/freescale/m5275evb/m5275evb.c @@ -35,7 +35,7 @@ int dram_init(void) out_be16(&gpio_reg->par_sdram, 0x3FF); /* Set up chip select */ - out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE); + out_be32(&sdp->sdbar0, CFG_SYS_SDRAM_BASE); out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V); /* Set up timing */ @@ -49,34 +49,34 @@ int dram_init(void) setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); /* Dummy write to start SDRAM */ - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; /* Send LEMR */ setbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) | MCF_SDRAMC_SDMR_CMD); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; /* Send LMR */ out_be32(&sdp->sdmr, 0x058d0000); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop sending commands */ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); /* Set precharge */ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop manual precharge, send 2 IREF */ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; out_be32(&sdp->sdmr, 0x018d0000); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop sending commands */ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); @@ -91,7 +91,7 @@ int dram_init(void) | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1) | MCF_SDRAMC_SDCR_DQS_OE(0x3)); - gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; return 0; }; diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c index e1ea9b3a58f..53e0f202101 100644 --- a/board/freescale/m5282evb/m5282evb.c +++ b/board/freescale/m5282evb/m5282evb.c @@ -21,7 +21,7 @@ int dram_init(void) { u32 dramsize, i, dramclk; - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) break; @@ -40,7 +40,7 @@ int dram_init(void) /* Initialize DACR0 */ MCFSDRAMC_DACR0 = (0 - | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE) + | MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE) | MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) | MCFSDRAMC_DACR_PS_32); @@ -62,7 +62,7 @@ int dram_init(void) } /* Write to this block to initiate precharge */ - *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696; + *(u32 *)(CFG_SYS_SDRAM_BASE) = 0xA5A59696; asm("nop"); /* Set RE (bit 15) in DACR */ @@ -79,7 +79,7 @@ int dram_init(void) asm("nop"); /* Write to the SDRAM Mode Register */ - *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; + *(u32 *)(CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; } gd->ram_size = dramsize; diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README index 8a7d8cadf02..0de36a7f747 100644 --- a/board/freescale/m53017evb/README +++ b/board/freescale/m53017evb/README @@ -106,7 +106,7 @@ CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register -CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base +CFG_SYS_SDRAM_BASE -- defines the DRAM Base 2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL =========================================== diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c index c9f89353ce4..76ebc0ab8dc 100644 --- a/board/freescale/m53017evb/m53017evb.c +++ b/board/freescale/m53017evb/m53017evb.c @@ -29,7 +29,7 @@ int dram_init(void) sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -37,35 +37,35 @@ int dram_init(void) } i--; - out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); -#ifdef CONFIG_SYS_SDRAM_BASE1 - out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); +#ifdef CFG_SYS_SDRAM_BASE1 + out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i); #endif - out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); udelay(500); /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); asm("nop"); /* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); asm("nop"); /* Issue LEMR */ - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); asm("nop"); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); asm("nop"); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); asm("nop"); out_be32(&sdram->ctrl, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); asm("nop"); udelay(100); diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index 7a75b04dd0d..b278dbfb485 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -29,7 +29,7 @@ int dram_init(void) sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -37,30 +37,30 @@ int dram_init(void) } i--; - out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); - out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); /* Issue LEMR */ - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); out_be32(&sdram->ctrl, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); udelay(100); diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README index bba54202155..bfbcd5dc81d 100644 --- a/board/freescale/m5373evb/README +++ b/board/freescale/m5373evb/README @@ -105,7 +105,7 @@ CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register -CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base +CFG_SYS_SDRAM_BASE -- defines the DRAM Base 2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL =========================================== diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c index cfa5ca4a477..0e9eec316c2 100644 --- a/board/freescale/m5373evb/m5373evb.c +++ b/board/freescale/m5373evb/m5373evb.c @@ -29,7 +29,7 @@ int dram_init(void) sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -37,30 +37,30 @@ int dram_init(void) } i--; - out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); - out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); /* Issue LEMR */ - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); out_be32(&sdram->ctrl, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); udelay(100); diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 2650d300e38..85d43cccd1a 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -97,10 +97,10 @@ int dram_init(void) int fixed_sdram(void) { immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_SDRAM_SIZE; + u32 msize = CFG_SYS_SDRAM_SIZE; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; @@ -127,7 +127,7 @@ int fixed_sdram(void) im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; udelay(2000); - return CONFIG_SYS_SDRAM_SIZE >> 20; + return CFG_SYS_SDRAM_SIZE >> 20; } #endif /*!CONFIG_SYS_SPD_EEPROM */ diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 46095acedfd..86364acf8ca 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 038e6736ace..f896fd7ccce 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -244,7 +244,7 @@ phys_size_t fixed_sdram(void) printf("Configuring DDR for %s MT/s data rate\n", strmhz(buf, sysinfo.freq_ddrbus)); - ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c index 70e4dfcfa45..954197282e6 100644 --- a/board/friendlyarm/nanopi2/board.c +++ b/board/friendlyarm/nanopi2/board.c @@ -507,7 +507,7 @@ int splash_screen_prepare(void) /* u-boot dram initialize */ int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } @@ -518,10 +518,10 @@ int dram_init_banksize(void) unsigned int reg_val = readl(SCR_USER_SIG6_READ); /* set global data memory */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x00000100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100; - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; /* Number of Row: 14 bits */ if ((reg_val >> 28) == 14) diff --git a/board/gardena/smart-gateway-at91sam/board.c b/board/gardena/smart-gateway-at91sam/board.c index c6eb11e9326..d9dfb256b32 100644 --- a/board/gardena/smart-gateway-at91sam/board.c +++ b/board/gardena/smart-gateway-at91sam/board.c @@ -45,15 +45,15 @@ int board_early_init_f(void) int board_init(void) { /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 47b88043521..4889a6a4f3b 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -34,11 +34,11 @@ DECLARE_GLOBAL_DATA_PTR; static long fixed_sdram(void) { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_SDRAM_SIZE; + u32 msize = CFG_SYS_SDRAM_SIZE; u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_SDRAM_BASE & 0xfffff000); + CFG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); @@ -66,7 +66,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync(); - return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); + return get_ram_size(CFG_SYS_SDRAM_BASE, msize); } int dram_init(void) diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c index 6423c1efb24..b472ca5b94a 100644 --- a/board/grinn/chiliboard/board.c +++ b/board/grinn/chiliboard/board.c @@ -95,7 +95,7 @@ int board_init(void) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; gpmc_init(); return 0; diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c index 5b245cb4473..8532225dc0d 100644 --- a/board/imgtec/boston/ddr.c +++ b/board/imgtec/boston/ddr.c @@ -27,7 +27,7 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) { DECLARE_GLOBAL_DATA_PTR; - if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) { + if (gd->ram_top < CFG_SYS_SDRAM_BASE) { /* 2GB wrapped around to 0 */ return CKSEG0ADDR(256 << 20); } diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S index bed24972f7a..aa910bf1ce1 100644 --- a/board/imgtec/malta/lowlevel_init.S +++ b/board/imgtec/malta/lowlevel_init.S @@ -118,7 +118,7 @@ _msc01: /* setup basic address decode */ PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE) li t1, 0x0 - li t2, -CONFIG_SYS_SDRAM_SIZE + li t2, -CFG_SYS_SDRAM_SIZE sw t1, MSC01_BIU_MCBAS1L_OFS(t0) sw t2, MSC01_BIU_MCMSK1L_OFS(t0) sw t1, MSC01_BIU_MCBAS2L_OFS(t0) @@ -168,7 +168,7 @@ _msc01: sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0) /* setup PCI_BAR0 memory window */ - li t1, -CONFIG_SYS_SDRAM_SIZE + li t1, -CFG_SYS_SDRAM_SIZE sw t1, MSC01_PCI_BAR0_OFS(t0) /* setup PCI to SysCon/CPU translation */ diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 9853a0ba82f..4a72ab5ceca 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -94,7 +94,7 @@ static enum sys_con malta_sys_con(void) int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c index 6a836370e36..71226927211 100644 --- a/board/imgtec/xilfpga/xilfpga.c +++ b/board/imgtec/xilfpga/xilfpga.c @@ -19,7 +19,7 @@ int dram_init(void) { /* MIG IP block is smart and doesn't need SW * to do any init */ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; /* in bytes */ + gd->ram_size = CFG_SYS_SDRAM_SIZE; /* in bytes */ return 0; } diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c index 7dbb3a91432..f3a0de3967b 100644 --- a/board/inversepath/usbarmory/usbarmory.c +++ b/board/inversepath/usbarmory/usbarmory.c @@ -412,7 +412,7 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1 << 30); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 1 << 30); return 0; } diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c index 02ae7df04db..5462a3dea22 100644 --- a/board/isee/igep003x/board.c +++ b/board/isee/igep003x/board.c @@ -185,7 +185,7 @@ int spl_start_uboot(void) */ int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; gpmc_init(); diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index c8138dcf305..0252ada93ff 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -52,7 +52,7 @@ int set_km_env(void) char envval[16]; char *p; - pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - + pnvramaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; sprintf(envval, "0x%x", pnvramaddr); env_set("pnvramaddr", envval); @@ -65,7 +65,7 @@ int set_km_env(void) CONFIG_KM_PNVRAM) / 0x400; env_set_ulong("pram", pram); - varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - + varaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; env_set_hex("varaddr", varaddr); sprintf(envval, "0x%x", varaddr); diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 6a7b8481614..ddd8f7a13e1 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -142,10 +142,10 @@ static int fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); disable_addr_trans(); - msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); + msize = get_ram_size(CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE); enable_addr_trans(); msize /= (1024 * 1024); - if (CONFIG_SYS_SDRAM_SIZE >> 20 != msize) { + if (CFG_SYS_SDRAM_SIZE >> 20 != msize) { for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) @@ -169,7 +169,7 @@ int dram_init(void) return -ENXIO; out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR); + CFG_SYS_SDRAM_BASE & LAWBAR_BAR); msize = fixed_sdram(); #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c index 4ec60f16854..556d39d4d4e 100644 --- a/board/keymile/pg-wcom-ls102xa/ddr.c +++ b/board/keymile/pg-wcom-ls102xa/ddr.c @@ -84,7 +84,7 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 3719bcf7317..1a7fa3fc1e4 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -184,7 +184,7 @@ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { /* Define only 1MiB range for mem_regions at the middle of the RAM */ /* For 1GiB range mem_regions takes approx. 4min */ - *vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1); + *vstart = CFG_SYS_SDRAM_BASE + (gd->ram_size >> 1); *size = 1 << 20; return 0; } diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c index d47c7b5f1eb..b3c176dd59a 100644 --- a/board/l+g/vinco/vinco.c +++ b/board/l+g/vinco/vinco.c @@ -164,7 +164,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #if !CONFIG_IS_ENABLED(DM_SPI) vinco_spi0_hw_init(); @@ -188,8 +188,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c index 0504d6177fd..ff233e920a0 100644 --- a/board/mediatek/mt7622/mt7622_rfb.c +++ b/board/mediatek/mt7622/mt7622_rfb.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/mediatek/mt7623/mt7623_rfb.c b/board/mediatek/mt7623/mt7623_rfb.c index 755e879085c..ec10f77c51e 100644 --- a/board/mediatek/mt7623/mt7623_rfb.c +++ b/board/mediatek/mt7623/mt7623_rfb.c @@ -12,7 +12,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/mediatek/mt7629/mt7629_rfb.c b/board/mediatek/mt7629/mt7629_rfb.c index d1bca6d62ef..55f7696c510 100644 --- a/board/mediatek/mt7629/mt7629_rfb.c +++ b/board/mediatek/mt7629/mt7629_rfb.c @@ -11,7 +11,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/mediatek/mt8518/mt8518_ap1.c b/board/mediatek/mt8518/mt8518_ap1.c index fce5de6767c..2490b15ec78 100644 --- a/board/mediatek/mt8518/mt8518_ap1.c +++ b/board/mediatek/mt8518/mt8518_ap1.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; debug("gd->fdt_blob is %p\n", gd->fdt_blob); return 0; diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c index 6abf08bd24c..84b95be648d 100644 --- a/board/mscc/jr2/jr2.c +++ b/board/mscc/jr2/jr2.c @@ -28,7 +28,7 @@ int board_early_init_r(void) ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE; return 0; } diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c index 76e3f2ebbce..48170b3aa12 100644 --- a/board/mscc/luton/luton.c +++ b/board/mscc/luton/luton.c @@ -29,7 +29,7 @@ int board_early_init_r(void) writel(0, BASE_CFG + ICPU_SW_MODE); /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE; return 0; } diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index 2a75ec281cb..f261346b358 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -77,7 +77,7 @@ int board_early_init_r(void) ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE; return 0; } diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c index 87e79076574..99d5f5be657 100644 --- a/board/mscc/serval/serval.c +++ b/board/mscc/serval/serval.c @@ -22,7 +22,7 @@ int board_early_init_r(void) writel(0, BASE_CFG + ICPU_SW_MODE); /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE; return 0; } diff --git a/board/mscc/servalt/servalt.c b/board/mscc/servalt/servalt.c index bd8c7e8b700..49993168c23 100644 --- a/board/mscc/servalt/servalt.c +++ b/board/mscc/servalt/servalt.c @@ -22,7 +22,7 @@ int board_early_init_r(void) writel(0, BASE_CFG + ICPU_SW_MODE); /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE; return 0; } diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c index d97ebd01512..e84dd251c25 100644 --- a/board/phytec/phycore_am335x_r2/board.c +++ b/board/phytec/phycore_am335x_r2/board.c @@ -166,7 +166,7 @@ void sdram_init(void) 0); /* Detect memory physically present */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); /* Reconfigure memory for actual detected size */ @@ -269,7 +269,7 @@ void set_mux_conf_regs(void) */ int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c index 4fbe1e58358..75d2636bf45 100644 --- a/board/phytium/pomelo/pomelo.c +++ b/board/phytium/pomelo/pomelo.c @@ -24,7 +24,7 @@ int dram_init(void) ddr_init(); gd->mem_clk = 0; - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 0x7b000000); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 0x7b000000); sec_init(); debug("PBF relocate done\n"); diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index 3b60afc59c3..85fbaf0b28b 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -70,7 +70,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c index a36526986ca..ea090575fb2 100644 --- a/board/renesas/blanche/blanche.c +++ b/board/renesas/blanche/blanche.c @@ -312,7 +312,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c index 6197e549c2e..2d1435acff6 100644 --- a/board/renesas/gose/gose.c +++ b/board/renesas/gose/gose.c @@ -78,7 +78,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c index 199ec4a3109..f609e4f0728 100644 --- a/board/renesas/grpeach/grpeach.c +++ b/board/renesas/grpeach/grpeach.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100); return 0; } diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 87607df20d5..c3ebcd3e39f 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -80,7 +80,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 8e24ac013c0..1437875cfa7 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -89,7 +89,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c index 1a3a4c11a17..db1fb4b035f 100644 --- a/board/renesas/porter/porter.c +++ b/board/renesas/porter/porter.c @@ -78,7 +78,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c index 4558070af88..6ecebfe814d 100644 --- a/board/renesas/silk/silk.c +++ b/board/renesas/silk/silk.c @@ -71,7 +71,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/stout/stout.c b/board/renesas/stout/stout.c index 56bdb34329a..f069eccde97 100644 --- a/board/renesas/stout/stout.c +++ b/board/renesas/stout/stout.c @@ -88,7 +88,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; cpld_init(); diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 23b55e3e030..c56582a1948 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -126,7 +126,7 @@ int board_init(void) /* arch number of AT91SAM9M10G45EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_PM9G45; /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND pm9g45_nand_hw_init(); @@ -141,15 +141,15 @@ int board_init(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index 5320c1f2e0a..a992dc68429 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -46,7 +46,7 @@ int dram_init(void) u32 addr; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); } return 0; @@ -64,7 +64,7 @@ int dram_init_banksize(void) u32 addr, size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); gd->bd->bi_dram[i].start = addr; diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 943b498293b..16ce5cb8925 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -122,7 +122,7 @@ int dram_init(void) unsigned long addr; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); } return 0; @@ -134,7 +134,7 @@ int dram_init_banksize(void) unsigned long addr, size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); gd->bd->bi_dram[i].start = addr; diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 4c655dfd495..8b953f9b397 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -115,7 +115,7 @@ enum env_location env_get_location(enum env_operation op, int prio) int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } @@ -173,7 +173,7 @@ int board_late_init(void) int init_addr_map(void) { if (IS_ENABLED(CONFIG_ADDR_MAP)) - addrmap_set_entry(0, 0, CONFIG_SYS_SDRAM_SIZE, 0); + addrmap_set_entry(0, 0, CFG_SYS_SDRAM_SIZE, 0); return 0; } diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 85025f20efa..2efede62aa5 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -85,7 +85,7 @@ int board_init(void) #ifdef CONFIG_MACH_TYPE gd->bd->bi_arch_number = CONFIG_MACH_TYPE; #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_FACTORYSET factoryset_read_eeprom(FACTORYSET_EEPROM_ADDR); diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index d87628097d0..569b86db00a 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -262,7 +262,7 @@ void at91_udp_hw_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* we have to request the gpios again after relocation */ corvus_request_gpio(); @@ -287,8 +287,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index b965ae9fa49..8f4b0eae495 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -146,7 +146,7 @@ int dram_init_banksize(void) dram_init(); /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; /* Bank 1 declares the memory available in the DDR high region */ diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index ce6c877959a..3d0f7341a37 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -167,7 +167,7 @@ int board_init(void) #endif /* Adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; smartweb_nand_hw_init(); smartweb_macb_hw_init(); @@ -177,8 +177,8 @@ int board_init(void) int dram_init(void) { gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 47d3f6aef22..1eee972d49e 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -185,8 +185,8 @@ void mem_init(void) sdramc_configure(AT91_SDRAMC_NC_10); /* Do memtest for 128MB */ - ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); /* * If 32MB or 16MB should be supported check also for @@ -306,7 +306,7 @@ struct at91_udc_data board_udc_data = { int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; taurus_request_gpio(); #ifdef CONFIG_CMD_NAND @@ -326,8 +326,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c index a218278cb34..79e492f0a8e 100644 --- a/board/sipeed/maix/maix.c +++ b/board/sipeed/maix/maix.c @@ -11,7 +11,7 @@ phys_size_t get_effective_memsize(void) { - return CONFIG_SYS_SDRAM_SIZE; + return CFG_SYS_SDRAM_SIZE; } static int sram_init(void) diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index 04527cf79ab..ad49999dc28 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -51,11 +51,11 @@ phys_size_t fixed_sdram(void) asm ("sync; isync; msync"); udelay(1000); - if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) { + if (get_ram_size(0, CFG_SYS_SDRAM_SIZE<<20) == CFG_SYS_SDRAM_SIZE<<20) { /* * OK, size detected -> all done */ - return CONFIG_SYS_SDRAM_SIZE<<20; + return CFG_SYS_SDRAM_SIZE<<20; } return 0; /* nothing found ! */ diff --git a/board/softing/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c index 22992273911..b3f9550742e 100644 --- a/board/softing/vining_fpga/socfpga.c +++ b/board/softing/vining_fpga/socfpga.c @@ -30,7 +30,7 @@ int board_late_init(void) status_led_set(2, CONFIG_LED_STATUS_ON); /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio"); if (!ret) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 8e80ca6e17e..7c44379ec4a 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -107,7 +107,7 @@ int dram_init(void) { u32 max_size = imx_ddr_size(); - gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size_stride_test((u32 *) CFG_SYS_SDRAM_BASE, (u32)max_size); return 0; @@ -288,7 +288,7 @@ int board_init(void) int ret = 0; /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_VIDEO_IPUV3 ret = setup_display(); diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c index beab4e9d188..5426fc4ffd8 100644 --- a/board/sysam/amcore/amcore.c +++ b/board/sysam/amcore/amcore.c @@ -88,7 +88,7 @@ int dram_init(void) */ out_be32(&dc->dacr0, 0x00003304); - dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000; + dramsize = ((CFG_SYS_SDRAM_SIZE)-1) & 0xfffc0000; out_be32(&dc->dmr0, dramsize|1); /* issue a PRECHARGE ALL */ @@ -102,8 +102,8 @@ int dram_init(void) out_be32(&dc->dacr0, 0x0000b344); out_be32((u32 *)0x00000c00, 0xbeaddeed); - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size(CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c index d48da48b69d..475e3edfa62 100644 --- a/board/sysam/stmark2/stmark2.c +++ b/board/sysam/stmark2/stmark2.c @@ -35,7 +35,7 @@ int dram_init(void) * Serial Boot: The dram is already initialized in start.S * only require to return DRAM size */ - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; gd->ram_size = dramsize; diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c index 3a447ca8a93..8d9eedb7523 100644 --- a/board/tbs/tbs2910/tbs2910.c +++ b/board/tbs/tbs2910/tbs2910.c @@ -144,7 +144,7 @@ static const struct boot_mode board_boot_modes[] = { int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_VIDEO_IPUV3 setup_display(); diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c index b7ddc3ba78f..839a692ce85 100644 --- a/board/tcl/sl50/board.c +++ b/board/tcl/sl50/board.c @@ -238,7 +238,7 @@ int board_init(void) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index b97fedddd5e..9e582816115 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -704,7 +704,7 @@ int board_init(void) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND) gpmc_init(); #endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 529129ecc76..d0b7a14e0e9 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -639,7 +639,7 @@ int board_init(void) u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, modena_init0_bw_integer, modena_init0_watermark_0; - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; gpmc_init(); /* diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index cfc825e52a3..652c40f55c4 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -661,7 +661,7 @@ bool am571x_idk_needs_lcd(void) int board_init(void) { gpmc_init(); - gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100); return 0; } diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 34ec3915f3d..b266ccb4b82 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -75,13 +75,13 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) int dram_init_banksize(void) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x80000000; gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; gd->bd->bi_dram[1].size = 0x80000000; gd->ram_size = 0x100000000; #endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index a854d615c1d..1c00e253ffc 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -644,7 +644,7 @@ int dram_init_banksize(void) ram_size = board_ti_get_emif_size(); - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = get_effective_memsize(); if (ram_size > CONFIG_MAX_MEM_MAPPED) { gd->bd->bi_dram[1].start = 0x200000000; diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index d6e431ead0e..d4e672a7acd 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -71,13 +71,13 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) int dram_init_banksize(void) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x80000000; gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; gd->bd->bi_dram[1].size = 0x80000000; gd->ram_size = 0x100000000; #endif diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index e09adc8ad34..4d28582311b 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -60,13 +60,13 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) int dram_init_banksize(void) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x7fffffff; gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; gd->bd->bi_dram[1].size = 0x37fffffff; gd->ram_size = 0x400000000; #endif diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 51e8de4b891..34818736a4f 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -46,7 +46,7 @@ int dram_init(void) ddr3_size = ddr3_init(); - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); #if defined(CONFIG_TI_AEMIF) if (!(board_is_k2g_ice() || board_is_k2g_i1())) @@ -71,7 +71,7 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } @@ -120,7 +120,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* adjust memory start address for LPAE */ if (lpae) { - start[0] -= CONFIG_SYS_SDRAM_BASE; + start[0] -= CFG_SYS_SDRAM_BASE; start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; } @@ -174,11 +174,11 @@ void ft_board_setup_ex(void *blob, struct bd_info *bd) "linux,initrd-end", NULL); if (prop1 && prop2) { initrd_start = __be64_to_cpu(*prop1); - initrd_start -= CONFIG_SYS_SDRAM_BASE; + initrd_start -= CFG_SYS_SDRAM_BASE; initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; initrd_start = __cpu_to_be64(initrd_start); initrd_end = __be64_to_cpu(*prop2); - initrd_end -= CONFIG_SYS_SDRAM_BASE; + initrd_end -= CFG_SYS_SDRAM_BASE; initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; initrd_end = __cpu_to_be64(initrd_end); @@ -221,7 +221,7 @@ void ft_board_setup_ex(void *blob, struct bd_info *bd) *reserve_start = __cpu_to_be64(*reserve_start); size = __cpu_to_be64(*(reserve_start + 1)); if (size) { - *reserve_start -= CONFIG_SYS_SDRAM_BASE; + *reserve_start -= CFG_SYS_SDRAM_BASE; *reserve_start += CONFIG_SYS_LPAE_SDRAM_BASE; *reserve_start = diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c index 2d42af6b809..8c708355d4c 100644 --- a/board/ti/ti816x/evm.c +++ b/board/ti/ti816x/evm.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_MTD_RAW_NAND) gpmc_init(); #endif diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c index 9d4ffb0f979..efef855b3d0 100644 --- a/board/timll/devkit3250/devkit3250.c +++ b/board/timll/devkit3250/devkit3250.c @@ -56,7 +56,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_SYS_FLASH_CFI /* Use 16-bit memory interface for NOR Flash */ @@ -76,8 +76,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 96d0185329d..3c7cfa309c1 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -79,7 +79,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { /* use the DDR controllers configured size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, (ulong)imx_ddr_size()); return 0; diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 475250d8013..65e0e9a156a 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -73,7 +73,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { /* use the DDR controllers configured size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, (ulong)imx_ddr_size()); return 0; diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index 07fe4544718..f335d5b4f4a 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -266,7 +266,7 @@ int board_init(void) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND) gpmc_init(); #endif diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c index 5d12f84cfea..c8e791a4da8 100644 --- a/board/work-microwave/work_92105/work_92105.c +++ b/board/work-microwave/work_92105/work_92105.c @@ -67,15 +67,15 @@ int board_init(void) { reset_periph(); /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 17ee541bd84..df4c4576723 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -105,7 +105,7 @@ int board_late_init(void) return board_late_init_xilinx(); } -#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) +#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE) int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); @@ -123,8 +123,8 @@ int dram_init(void) #else int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); zynq_ddrc_init(); diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 579708d2e0c..e3f70c4caf4 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -236,7 +236,7 @@ unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, return ret; } -#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) +#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE) int dram_init_banksize(void) { int ret; @@ -261,7 +261,7 @@ int dram_init(void) #else int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = get_effective_memsize(); mem_map_fill(); @@ -271,8 +271,8 @@ int dram_init_banksize(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/boot/image-board.c b/boot/image-board.c index 34d1e5f18be..8813be544be 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -116,8 +116,8 @@ ulong env_get_bootm_low(void) return tmp; } -#if defined(CONFIG_SYS_SDRAM_BASE) - return CONFIG_SYS_SDRAM_BASE; +#if defined(CFG_SYS_SDRAM_BASE) + return CFG_SYS_SDRAM_BASE; #elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV) return gd->bd->bi_dram[0].start; #else diff --git a/cmd/ti/ddr3.c b/cmd/ti/ddr3.c index aaaedfe9735..bbd406fc66e 100644 --- a/cmd/ti/ddr3.c +++ b/cmd/ti/ddr3.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_ARCH_KEYSTONE #include -#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE +#define DDR_MIN_ADDR CFG_SYS_SDRAM_BASE #define STACKSIZE (512 << 10) /* 512 KiB */ #define DDR_REMAP_ADDR 0x80000000 @@ -247,9 +247,9 @@ static int is_addr_valid(u32 addr) /* Check in ecc address range 1 */ if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) { start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) - + CONFIG_SYS_SDRAM_BASE; + + CFG_SYS_SDRAM_BASE; end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF + - CONFIG_SYS_SDRAM_BASE; + CFG_SYS_SDRAM_BASE; if ((addr >= start_addr) && (addr <= end_addr)) /* addr within ecc address range 1 */ return 1; @@ -259,9 +259,9 @@ static int is_addr_valid(u32 addr) if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) { range = readl(&emif->emif_ecc_address_range_2); start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) - + CONFIG_SYS_SDRAM_BASE; + + CFG_SYS_SDRAM_BASE; end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF + - CONFIG_SYS_SDRAM_BASE; + CFG_SYS_SDRAM_BASE; if ((addr >= start_addr) && (addr <= end_addr)) /* addr within ecc address range 2 */ return 1; @@ -309,11 +309,11 @@ static int do_ddr_test(struct cmd_tbl *cmdtp, start_addr = hextoul(argv[2], NULL); end_addr = hextoul(argv[3], NULL); - if ((start_addr < CONFIG_SYS_SDRAM_BASE) || - (start_addr > (CONFIG_SYS_SDRAM_BASE + + if ((start_addr < CFG_SYS_SDRAM_BASE) || + (start_addr > (CFG_SYS_SDRAM_BASE + get_effective_memsize() - 1)) || - (end_addr < CONFIG_SYS_SDRAM_BASE) || - (end_addr > (CONFIG_SYS_SDRAM_BASE + + (end_addr < CFG_SYS_SDRAM_BASE) || + (end_addr > (CFG_SYS_SDRAM_BASE + get_effective_memsize() - 1)) || (start_addr >= end_addr)) { puts("Invalid start or end address!\n"); return cmd_usage(cmdtp); diff --git a/common/board_f.c b/common/board_f.c index e6117a7ba5e..aab1130763e 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -329,12 +329,12 @@ __weak int mach_cpu_init(void) /* Get the top of usable RAM */ __weak phys_size_t board_get_usable_ram_top(phys_size_t total_size) { -#if defined(CONFIG_SYS_SDRAM_BASE) && CONFIG_SYS_SDRAM_BASE > 0 +#if defined(CFG_SYS_SDRAM_BASE) && CFG_SYS_SDRAM_BASE > 0 /* * Detect whether we have so much RAM that it goes past the end of our * 32-bit address space. If so, clip the usable RAM so it doesn't. */ - if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) + if (gd->ram_top < CFG_SYS_SDRAM_BASE) /* * Will wrap back to top of 32-bit space when reservations * are made. @@ -369,8 +369,8 @@ static int setup_dest_addr(void) */ gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; #endif -#ifdef CONFIG_SYS_SDRAM_BASE - gd->ram_base = CONFIG_SYS_SDRAM_BASE; +#ifdef CFG_SYS_SDRAM_BASE + gd->ram_base = CFG_SYS_SDRAM_BASE; #endif gd->ram_top = gd->ram_base + get_effective_memsize(); gd->ram_top = board_get_usable_ram_top(gd->mon_len); diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst index 15806dfaee1..584503eb12e 100644 --- a/doc/arch/m68k.rst +++ b/doc/arch/m68k.rst @@ -142,21 +142,21 @@ CONFIG_SYS_CACHE_DCACR: cache-related registers config CONFIG_SYS_CACHE_ACRX: cache-related registers config -CONFIG_SYS_SDRAM_BASE: +CFG_SYS_SDRAM_BASE: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_SIZE: +CFG_SYS_SDRAM_SIZE: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_BASEX: +CFG_SYS_SDRAM_BASEX: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_CFG1: +CFG_SYS_SDRAM_CFG1: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_CFG2: +CFG_SYS_SDRAM_CFG2: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_CTRL: +CFG_SYS_SDRAM_CTRL: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_MODE: +CFG_SYS_SDRAM_MODE: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_EMOD: +CFG_SYS_SDRAM_EMOD: SDRAM config for SDRAM controller-specific registers, please see arch/m68k/cpu//start.S files to see how these options are used. diff --git a/doc/arch/nios2.rst b/doc/arch/nios2.rst index 35defb0af0b..34a75e7fb00 100644 --- a/doc/arch/nios2.rst +++ b/doc/arch/nios2.rst @@ -96,8 +96,8 @@ to 0xDxxx_xxxx. .. code-block:: c - #define CONFIG_SYS_SDRAM_BASE 0xc8000000 - #define CONFIG_SYS_SDRAM_SIZE 0x08000000 + #define CFG_SYS_SDRAM_BASE 0xc8000000 + #define CFG_SYS_SDRAM_SIZE 0x08000000 You will need to change the environment variables location and setting, too. You may change other configs to fit your board. diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index 5e8fb7a89c2..9dada5e1175 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -130,7 +130,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (is_warm_boot()) { ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); - ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); /* DRAM VRef will not be trained */ diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 3c1f7a18912..f8d1468a26f 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -230,7 +230,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (is_warm_boot()) { ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); - ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); /* DRAM VRef will not be trained */ diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index fcff223b4f0..4975dbb821e 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -30,7 +30,7 @@ */ #ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY #ifdef CONFIG_MPC83xx -#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE #else #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE #endif diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 0f2dc243cb8..1c4a1cae4df 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -162,7 +162,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (is_warm_boot()) { out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); - out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); /* DRAM VRef will not be trained */ diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h index a14c766dda7..c40cd768abf 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp.h +++ b/drivers/ddr/marvell/axp/ddr3_axp.h @@ -19,10 +19,10 @@ #define FAR_END_DIMM_ADDR 0x50 #define MAX_DIMM_ADDR 0x60 -#ifndef CONFIG_SYS_SDRAM_SIZE +#ifndef CFG_SYS_SDRAM_SIZE #define SDRAM_CS_SIZE 0xFFFFFFF #else -#define SDRAM_CS_SIZE ((CONFIG_SYS_SDRAM_SIZE >> 10) - 1) +#define SDRAM_CS_SIZE ((CFG_SYS_SDRAM_SIZE >> 10) - 1) #endif #define SDRAM_CS_BASE 0x0 #define SDRAM_DIMM_SIZE 0x80000000 diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 22f4995453e..a3b662fb13d 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -60,7 +60,7 @@ config PCI_MAP_SYSTEM_MEMORY instead of a physical address (e.g. on MIPS). The PCI core will then remap the virtual memory base address to a physical address when adding the PCI region of type PCI_REGION_SYS_MEMORY. - This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is still + This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still being used as virtual address. config PCI_SRIOV diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index dc114027814..b81eb353689 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -191,7 +191,7 @@ static int rcar_gen2_pci_probe(struct udevice *dev) /* AHB-PCI Bridge Communication Registers */ writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG); - writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16, + writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16, priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG); writel(0xf0000000 | RCAR_PCIAHB_PREFETCH16, priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG); @@ -204,7 +204,7 @@ static int rcar_gen2_pci_probe(struct udevice *dev) /* PCI Configuration Registers for AHBPCI */ devad = setup_bus_address(dev, PCI_BDF(0, 0, 0), 0); writel(priv->cfg_base + 0x800, devad + PCI_BASE_ADDRESS_0); - writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1); + writel(CFG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1); writel(0xf0000000, devad + PCI_BASE_ADDRESS_2); writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | PCI_COMMAND_SERR, diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c index d514c040344..c1be56ce7a0 100644 --- a/drivers/pci/pci_sh7751.c +++ b/drivers/pci/pci_sh7751.c @@ -158,9 +158,9 @@ static int sh7751_pci_probe(struct udevice *dev) /* Set up target memory mappings (for external DMA access) */ /* Map both P0 and P2 range to Area 3 RAM for ease of use */ - p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0); - p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0); - p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5); + p4_out(CFG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0); + p4_out(CFG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0); + p4_out(CFG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5); p4_out(0, SH7751_PCILSR1); p4_out(0, SH7751_PCILAR1); diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 99891dce61d..a0b82c78321 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -459,9 +459,9 @@ static void pcie_dw_set_host_bars(const void *regs_base) } /* Set the BAR base and size towards DDR */ - bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf; + bar0 = CFG_SYS_SDRAM_BASE & ~0xf; bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32; - writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0); + writel(CFG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0); reg = ((size >> 20) - 1) << 12; writel(size, regs_base + RESIZABLE_BAR_CTL0); diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index a52774179e2..b7f692f6450 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -14,11 +14,11 @@ #include #ifndef CFG_SYS_PCI_MEMORY_BUS -#define CFG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_PCI_MEMORY_BUS CFG_SYS_SDRAM_BASE #endif #ifndef CFG_SYS_PCI_MEMORY_PHYS -#define CFG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_PCI_MEMORY_PHYS CFG_SYS_SDRAM_BASE #endif #ifndef CFG_SYS_PCI_MEMORY_SIZE diff --git a/drivers/ram/aspeed/sdram_ast2500.c b/drivers/ram/aspeed/sdram_ast2500.c index 141b19b57ac..dc466a88e71 100644 --- a/drivers/ram/aspeed/sdram_ast2500.c +++ b/drivers/ram/aspeed/sdram_ast2500.c @@ -203,7 +203,7 @@ static void ast2500_sdrammc_calc_size(struct dram_info *info) u32 test_pattern = 0xdeadbeef; u32 cap_param = SDRAM_CONF_CAP_1024M; u32 refresh_timing_param = DDR4_TRFC; - const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; + const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset; for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; ram_size >>= 1) { @@ -231,7 +231,7 @@ static void ast2500_sdrammc_calc_size(struct dram_info *info) ((refresh_timing_param & SDRAM_AC_TRFC_MASK) << SDRAM_AC_TRFC_SHIFT)); - info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.base = CFG_SYS_SDRAM_BASE; info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info); clrsetbits_le32(&info->regs->config, (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT), diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index 5d426088be3..a2d7ca82fc0 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -838,7 +838,7 @@ static void ast2600_sdrammc_calc_size(struct dram_info *info) u32 test_pattern = 0xdeadbeef; u32 cap_param = SDRAM_CONF_CAP_2048M; u32 refresh_timing_param = DDR4_TRFC; - const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; + const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset; for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; ram_size >>= 1) { @@ -866,7 +866,7 @@ static void ast2600_sdrammc_calc_size(struct dram_info *info) ((refresh_timing_param & SDRAM_AC_TRFC_MASK) << SDRAM_AC_TRFC_SHIFT)); - info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.base = CFG_SYS_SDRAM_BASE; info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); clrsetbits_le32(&info->regs->config, SDRAM_CONF_CAP_MASK, @@ -1015,7 +1015,7 @@ static void ast2600_sdrammc_update_size(struct dram_info *info) break; } - info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.base = CFG_SYS_SDRAM_BASE; info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); if (0 == (conf & SDRAM_CONF_ECC_SETUP)) diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c index d12a3b4f436..1737fdac970 100644 --- a/drivers/ram/mediatek/ddr3-mt7629.c +++ b/drivers/ram/mediatek/ddr3-mt7629.c @@ -243,17 +243,17 @@ static int mtk_ddr3_rank_size_detect(struct udevice *dev) * and it has maximum addressing region */ - writel(WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE); + writel(WALKING_PATTERN, CFG_SYS_SDRAM_BASE); - if (readl(CONFIG_SYS_SDRAM_BASE) != WALKING_PATTERN) + if (readl(CFG_SYS_SDRAM_BASE) != WALKING_PATTERN) return -EINVAL; for (step = 0; step < 5; step++) { - writel(~WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE + + writel(~WALKING_PATTERN, CFG_SYS_SDRAM_BASE + (WALKING_STEP << step)); - start = readl(CONFIG_SYS_SDRAM_BASE); - test = readl(CONFIG_SYS_SDRAM_BASE + (WALKING_STEP << step)); + start = readl(CFG_SYS_SDRAM_BASE); + test = readl(CFG_SYS_SDRAM_BASE + (WALKING_STEP << step)); if ((test != ~WALKING_PATTERN) || test == start) break; } @@ -727,7 +727,7 @@ static int mtk_ddr3_get_info(struct udevice *dev, struct ram_info *info) struct mtk_ddr3_priv *priv = dev_get_priv(dev); u32 val = readl(priv->emi + EMI_CONA); - info->base = CONFIG_SYS_SDRAM_BASE; + info->base = CFG_SYS_SDRAM_BASE; switch ((val & EMI_COL_ADDR_MASK) >> EMI_COL_ADDR_SHIFT) { case 0: diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c index 42daf068668..bb21078df14 100644 --- a/drivers/ram/octeon/octeon_ddr.c +++ b/drivers/ram/octeon/octeon_ddr.c @@ -2687,7 +2687,7 @@ static int octeon_ddr_probe(struct udevice *dev) if (!mem_mbytes) return -ENODEV; - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = MB(mem_mbytes); /* diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index 69c454a4ba8..6929a7e494e 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -617,12 +617,12 @@ static int sdram_col_row_detect(struct udevice *dev) /* Detect col */ for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + params->chan.bw - 1)); writel(test_pattern, addr); if ((readl(addr) == test_pattern) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } @@ -637,11 +637,11 @@ static int sdram_col_row_detect(struct udevice *dev) /* Detect row*/ for (row = 16; row >= 12; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); writel(test_pattern, addr); if ((readl(addr) == test_pattern) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } diff --git a/drivers/ram/rockchip/sdram_common.c b/drivers/ram/rockchip/sdram_common.c index b3e7421d085..ec46ba54575 100644 --- a/drivers/ram/rockchip/sdram_common.c +++ b/drivers/ram/rockchip/sdram_common.c @@ -220,12 +220,12 @@ int sdram_detect_col(struct sdram_cap_info *cap_info, u32 bw = cap_info->bw; for (col = coltmp; col >= 9; col -= 1) { - writel(0, CONFIG_SYS_SDRAM_BASE); - test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + (1ul << (col + bw - 1ul))); writel(PATTERN, test_addr); if ((readl(test_addr) == PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -245,12 +245,12 @@ int sdram_detect_bank(struct sdram_cap_info *cap_info, u32 bk; u32 bw = cap_info->bw; - test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + (1ul << (coltmp + bktmp + bw - 1ul))); - writel(0, CONFIG_SYS_SDRAM_BASE); + writel(0, CFG_SYS_SDRAM_BASE); writel(PATTERN, test_addr); if ((readl(test_addr) == PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) bk = 3; else bk = 2; @@ -268,12 +268,12 @@ int sdram_detect_bg(struct sdram_cap_info *cap_info, u32 dbw; u32 bw = cap_info->bw; - test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + (1ul << (coltmp + bw + 1ul))); - writel(0, CONFIG_SYS_SDRAM_BASE); + writel(0, CFG_SYS_SDRAM_BASE); writel(PATTERN, test_addr); if ((readl(test_addr) == PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) dbw = 0; else dbw = 1; @@ -337,12 +337,12 @@ int sdram_detect_row(struct sdram_cap_info *cap_info, void __iomem *test_addr; for (row = rowtmp; row > 12; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + (1ul << (row + bktmp + coltmp + bw - 1ul))); writel(PATTERN, test_addr); if ((readl(test_addr) == PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 12) { @@ -363,8 +363,8 @@ int sdram_detect_row_3_4(struct sdram_cap_info *cap_info, u32 row = cap_info->cs0_row; void __iomem *test_addr, *test_addr1; - test_addr = CONFIG_SYS_SDRAM_BASE; - test_addr1 = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + test_addr = CFG_SYS_SDRAM_BASE; + test_addr1 = (void __iomem *)(CFG_SYS_SDRAM_BASE + (0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul))); writel(0, test_addr); @@ -421,15 +421,15 @@ int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type) /* detect cs1 row */ for (row = cap_info->cs0_row; row > 12; row--) { - test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + cs0_cap + (1ul << (row + bktmp + coltmp + bw - 1ul))); - writel(0, CONFIG_SYS_SDRAM_BASE + cs0_cap); + writel(0, CFG_SYS_SDRAM_BASE + cs0_cap); writel(PATTERN, test_addr); if (((readl(test_addr) & byte_mask) == (PATTERN & byte_mask)) && - ((readl(CONFIG_SYS_SDRAM_BASE + cs0_cap) & + ((readl(CFG_SYS_SDRAM_BASE + cs0_cap) & byte_mask) == 0)) { break; } diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c index c024a0cd633..98b2593ac49 100644 --- a/drivers/ram/rockchip/sdram_px30.c +++ b/drivers/ram/rockchip/sdram_px30.c @@ -726,7 +726,7 @@ static int px30_dmc_probe(struct udevice *dev) priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: grf=%p\n", __func__, priv->pmugrf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]); diff --git a/drivers/ram/rockchip/sdram_rk3066.c b/drivers/ram/rockchip/sdram_rk3066.c index 832154ee3af..a2425f22e2c 100644 --- a/drivers/ram/rockchip/sdram_rk3066.c +++ b/drivers/ram/rockchip/sdram_rk3066.c @@ -616,12 +616,12 @@ static int rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, in /* Detect col. */ for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + sdram_params->ch[channel].bw - 1)); writel(TEST_PATTERN, addr); if ((readl(addr) == TEST_PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -638,11 +638,11 @@ static int rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, in rk3066_dmc_move_to_access_state(chan); /* Detect row, max 15, min13 for rk3066 */ for (row = 16; row >= 13; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); writel(TEST_PATTERN, addr); if ((readl(addr) == TEST_PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 12) { @@ -854,7 +854,7 @@ static int rk3066_dmc_probe(struct udevice *dev) if (ret) return ret; } else { - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmu->sys_reg[2]); } diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c index 16cfbf947bd..ded65393806 100644 --- a/drivers/ram/rockchip/sdram_rk3128.c +++ b/drivers/ram/rockchip/sdram_rk3128.c @@ -23,7 +23,7 @@ static int rk3128_dmc_probe(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); debug("%s: grf=%p\n", __func__, priv->grf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->grf->os_reg[1]); diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index be8ba4464d4..272b1b2dce1 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -638,12 +638,12 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel, /* Detect col */ for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + sdram_params->ch[channel].bw - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -660,11 +660,11 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel, move_to_access_state(chan); /* Detect row, max 15,min13 in rk3188*/ for (row = 16; row >= 13; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 12) { @@ -919,7 +919,7 @@ static int rk3188_dmc_probe(struct udevice *dev) if (ret) return ret; #else - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->pmu->sys_reg[2]); #endif diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index cd4234f389e..1b204fb56e6 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -636,12 +636,12 @@ static int dram_cap_detect(struct dram_info *dram, writel(3, &axi_bus->ddrconf); move_to_access_state(dram->chan[0].pctl); for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + bw - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -656,11 +656,11 @@ static int dram_cap_detect(struct dram_info *dram, /* Detect row*/ for (row = 16; row >= 12; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 11) { @@ -672,11 +672,11 @@ static int dram_cap_detect(struct dram_info *dram, sdram_params->ch[0].cs0_row = row; } /* cs detect */ - writel(0, CONFIG_SYS_SDRAM_BASE); - writel(TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30)); - writel(~TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30) + 4); - if ((readl(CONFIG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + writel(0, CFG_SYS_SDRAM_BASE); + writel(TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30)); + writel(~TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30) + 4); + if ((readl(CFG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) && + (readl(CFG_SYS_SDRAM_BASE) == 0)) sdram_params->ch[0].rank = 2; else sdram_params->ch[0].rank = 1; @@ -813,7 +813,7 @@ static int rk322x_dmc_probe(struct udevice *dev) if (ret) return ret; #else - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->grf->os_reg[2]); #endif diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index 227a3cc6a88..83778ad1c2c 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -684,12 +684,12 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel, /* Detect col */ for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + sdram_params->ch[channel].bw - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -705,11 +705,11 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel, move_to_access_state(chan); /* Detect row*/ for (row = 16; row >= 12; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 11) { @@ -1087,7 +1087,7 @@ static int rk3288_dmc_probe(struct udevice *dev) if (ret) return ret; #else - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->pmu->sys_reg[2]); #endif diff --git a/drivers/ram/rockchip/sdram_rk3308.c b/drivers/ram/rockchip/sdram_rk3308.c index 44d7d8a0d9b..10828e80822 100644 --- a/drivers/ram/rockchip/sdram_rk3308.c +++ b/drivers/ram/rockchip/sdram_rk3308.c @@ -21,7 +21,7 @@ static int rk3308_dmc_probe(struct udevice *dev) struct dram_info *priv = dev_get_priv(dev); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->grf->os_reg2); return 0; diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 9c6798f816a..b511c6bf6fe 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -580,7 +580,7 @@ static int rk3328_dmc_probe(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); debug("%s: grf=%p\n", __func__, priv->grf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->grf->os_reg[2]); #endif diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index cbf502bd0e9..136e4ede712 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -3151,7 +3151,7 @@ static int rk3399_dmc_probe(struct udevice *dev) priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: pmugrf = %p\n", __func__, priv->pmugrf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2); #endif diff --git a/drivers/ram/rockchip/sdram_rk3568.c b/drivers/ram/rockchip/sdram_rk3568.c index 0ac4b54eef3..f661615c1b9 100644 --- a/drivers/ram/rockchip/sdram_rk3568.c +++ b/drivers/ram/rockchip/sdram_rk3568.c @@ -21,7 +21,7 @@ static int rk3568_dmc_probe(struct udevice *dev) struct dram_info *priv = dev_get_priv(dev); priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmugrf->pmu_os_reg2); diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c index 130b73dfe49..60525f22867 100644 --- a/drivers/usb/host/ehci-rmobile.c +++ b/drivers/usb/host/ehci-rmobile.c @@ -90,7 +90,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, /* AHB-PCI Bridge Communication Registers */ writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr); - writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH, + writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH, &ahbcom_pci->pciahb_win1_ctr); writel(0xf0000000 | PCIAHB_WIN_PREFETCH, &ahbcom_pci->pciahb_win2_ctr); @@ -103,7 +103,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI, &ahbcom_pci->ahbpci_win1_ctr); writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead); - writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead); + writel(CFG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead); writel(0xf0000000, &ahbconf_pci->win2_basead); writel(SERREN | PERREN | MASTEREN | MEMEN, &ahbconf_pci->cmnd_sts); diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 2ee6212c58d..9110a484821 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -385,7 +385,7 @@ static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode, (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE; setbits_le32(&de_fe->bypass, SUNXI_DE_FE_BYPASS_CSC_BYPASS); - writel(CONFIG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr); + writel(CFG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr); writel(mode->xres * 4, &de_fe->ch0_stride); writel(SUNXI_DE_FE_INPUT_FMT_ARGB8888, &de_fe->input_fmt); writel(SUNXI_DE_FE_OUTPUT_FMT_ARGB8888, &de_fe->output_fmt); @@ -1222,7 +1222,7 @@ static int sunxi_de_probe(struct udevice *dev) EFI_RESERVED_MEMORY_TYPE); #endif - fb_dma_addr = sunxi_display->fb_addr - CONFIG_SYS_SDRAM_BASE; + fb_dma_addr = sunxi_display->fb_addr - CFG_SYS_SDRAM_BASE; if (overscan_offset) { fb_dma_addr += 0x1000 - (overscan_offset & 0xfff); sunxi_display->fb_addr += ALIGN(overscan_offset, 0x1000); diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 719caf7b0c3..3a4fbc6eab8 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -30,8 +30,8 @@ * -The heap is placed below the monitor * -The stack is placed below the heap (&grows down). */ -#define CONFIG_SYS_SDRAM_BASE 0xc8000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0xc8000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_MONITOR_IS_IN_RAM #endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index ad7bd133200..ab889180eed 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -26,8 +26,8 @@ * -The heap is placed below the monitor * -The stack is placed below the heap (&grows down). */ -#define CONFIG_SYS_SDRAM_BASE 0xD0000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0xD0000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_MONITOR_IS_IN_RAM #endif /* __CONFIG_H */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 25c3f22bea1..6dfa3dd0f02 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -60,22 +60,22 @@ /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x43711630 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 -#define CONFIG_SYS_SDRAM_EMOD 0x80010000 -#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x43711630 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1002000 +#define CFG_SYS_SDRAM_EMOD 0x80010000 +#define CFG_SYS_SDRAM_MODE 0x00CD0000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI @@ -100,8 +100,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index f200d706a92..e28662c6e59 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -70,10 +70,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ /* * For booting Linux, the board info and command line data @@ -81,7 +81,7 @@ * the maximum mapped by the Linux kernel during initialization ?? */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -109,8 +109,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DCM | \ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 9ff66d751c6..f1da278d515 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -52,10 +52,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) #if 0 /* test-only */ @@ -67,7 +67,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -90,8 +90,8 @@ #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ CF_ADDRMASK(2) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ CF_CACR_DBWE) diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index f7bfe598a80..bd3c57d1438 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -77,17 +77,17 @@ /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) @@ -117,8 +117,8 @@ #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ CF_ADDRMASK(8) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ CF_CACR_DBWE) diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index dcd83650f22..7c3bc032bfe 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -71,10 +71,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ #define CONFIG_SYS_FLASH_BASE 0xffe00000 /* @@ -82,7 +82,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* * FLASH organization @@ -100,8 +100,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 9012794501a..4eb4abea725 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -73,10 +73,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE /* @@ -84,7 +84,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -101,8 +101,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 925d26eaf10..eda394467e9 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -72,10 +72,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 @@ -85,7 +85,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -105,8 +105,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DBWE | \ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 79a4e6171d2..159993a46bc 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -74,22 +74,22 @@ /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x43711630 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x80010000 -#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x43711630 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1092000 +#define CFG_SYS_SDRAM_EMOD 0x80010000 +#define CFG_SYS_SDRAM_MODE 0x00CD0000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -118,8 +118,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index fc21af56ec7..d7ece639349 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -68,22 +68,22 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x53722730 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x40010000 -#define CONFIG_SYS_SDRAM_MODE 0x018D0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x53722730 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1092000 +#define CFG_SYS_SDRAM_EMOD 0x40010000 +#define CFG_SYS_SDRAM_MODE 0x018D0000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -117,8 +117,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index f7c09a2333c..b2fc6923e0d 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -70,22 +70,22 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x53722730 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x40010000 -#define CONFIG_SYS_SDRAM_MODE 0x018D0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x53722730 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1092000 +#define CFG_SYS_SDRAM_EMOD 0x40010000 +#define CFG_SYS_SDRAM_MODE 0x018D0000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -117,8 +117,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index a5518d3d50f..2e7140cd86a 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -62,8 +62,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) #define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800) -/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */ +#define CFG_SYS_SDRAM_BASE 0x00000000 /* FLASH organization */ #define CONFIG_SYS_FLASH_BASE CONFIG_TEXT_BASE diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 0e70b2853b2..d9627e393d9 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -59,7 +59,7 @@ /* * DDR Setup */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) @@ -69,7 +69,7 @@ /* * Manually set up DDR parameters */ -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | CSCONFIG_ODT_WR_ONLY_CURRENT \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index c59a37646f4..6a51149a949 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -40,7 +40,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f87e7597ad0..21491b9f97c 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -110,9 +110,9 @@ #ifndef __ASSEMBLY__ extern unsigned long get_sdram_size(void); #endif -#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ +#define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 8c7b877bfb9..d7e06d23ec4 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -69,10 +69,10 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x52 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* * Local Bus Definitions diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 824190a4123..417b9ae7b24 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -7,7 +7,7 @@ #define _CONFIG_SBX81LIFKW_H /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* * NS16550 Configuration diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index e67da1fe1dc..87b68227a0d 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -7,7 +7,7 @@ #define _CONFIG_SBX81LIFXCAT_H /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* * NS16550 Configuration diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 154b2f174af..616387f4876 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -116,12 +116,12 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #if defined(CONFIG_TARGET_T1024RDB) #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ #elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_SDRAM_SIZE 2048 +#define CFG_SYS_SDRAM_SIZE 2048 #endif /* diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 847cf65b409..37dfe32e21b 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -88,11 +88,11 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* * IFC Definitions diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index b49c2647768..8f56de40ce8 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -86,8 +86,8 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index aae41a33925..e9db4a224f9 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -81,8 +81,8 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 9dc45e397f9..cc86c9d4a51 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -62,7 +62,7 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* * IFC Definitions @@ -154,7 +154,7 @@ #define SPD_EEPROM_ADDRESS2 0x54 #define SPD_EEPROM_ADDRESS3 0x56 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* * IFC Definitions diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h index 78201adc07f..57f3f37908d 100644 --- a/include/configs/am62x_evm.h +++ b/include/configs/am62x_evm.h @@ -13,7 +13,7 @@ #include /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 #define PARTS_DEFAULT \ /* Linux partitions */ \ diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 140940730d0..25c71f00a20 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -16,7 +16,7 @@ #include /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 #define PARTS_DEFAULT \ /* Linux partitions */ \ diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 0345160787e..0307426e4ab 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -15,7 +15,7 @@ #include /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 #define PARTS_DEFAULT \ /* Linux partitions */ \ diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 2bda66fe033..eba78d3894c 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -33,8 +33,8 @@ /* size of internal SRAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 0x1000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 0x1000000 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* amcore design has flash data bytes wired swapped */ diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 650140bb724..63c7dfc1feb 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 3114cf0c4fb..865aad2a3f9 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 diff --git a/include/configs/ap152.h b/include/configs/ap152.h index f0674456fd0..0464a69e823 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index e2e491bdb0a..cf23837863b 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -63,7 +63,7 @@ /* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ #define CFG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 30d32d27e3d..356d4c35ee2 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -106,7 +106,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/arbel.h b/include/configs/arbel.h index f7deba4f566..ed32e772f8e 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -6,9 +6,9 @@ #ifndef __CONFIG_ARBEL_H #define __CONFIG_ARBEL_H -#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_SDRAM_BASE 0x0 #define CONFIG_SYS_BOOTMAPSZ (20 << 20) -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Default environemnt variables */ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 35e8840a92a..90cf4705f4f 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -406,7 +406,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h index 5c9005805e1..cbd0d6cea01 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h @@ -14,7 +14,7 @@ /* Misc CPU related */ -#define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE +#define CFG_SYS_SDRAM_BASE ASPEED_DRAM_BASE #ifdef CONFIG_PRE_CON_BUF_SZ #define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ) diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 58635df149b..b142ea3c335 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -57,7 +57,7 @@ #define CONFIG_SYS_CLK 80000000 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ /* * Define baudrate for UART1 (console output, tftp, ...) @@ -158,7 +158,7 @@ * (Set up by the startup code) * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* * Chipselect bank definitions @@ -195,8 +195,8 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ - (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ + (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ @@ -213,8 +213,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 574bfe37e9a..0d76f419db5 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -31,8 +31,8 @@ * SDRAM: 1 bank, min 32, max 128 MB * Initialized before u-boot gets started. */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #ifdef CONFIG_AT91SAM9XE diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 2c785ad4264..dcc1cca4791 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -17,8 +17,8 @@ #include /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x04000000 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index bba8574b1c8..aefa9fc60c4 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -23,8 +23,8 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 @@ -100,22 +100,22 @@ /* Memory Device Register -> SDRAM */ #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 3ce264a4a90..08cfee1a4e1 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -15,8 +15,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x70000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0x70000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 5e3ded241fa..76f87c16192 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -14,8 +14,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ /* Misc CPU related */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* DataFlash */ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index b79c8ba5bf8..e1111b6dd38 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -17,8 +17,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 40ea4ed49e8..eb1d1ad60d1 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -20,8 +20,8 @@ */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ /* DataFlash */ diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index e3b6956eb5a..83ac87b10a5 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -28,7 +28,7 @@ (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_0 /* * Serial console configuration diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 1932713f453..6d82712186d 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -20,8 +20,8 @@ */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_512M +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_512M /* * UART configuration diff --git a/include/configs/bcm947622.h b/include/configs/bcm947622.h index d0c46a2c823..b02ed1bfe0e 100644 --- a/include/configs/bcm947622.h +++ b/include/configs/bcm947622.h @@ -6,7 +6,7 @@ #ifndef __BCM947622_H #define __BCM947622_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define COUNTER_FREQUENCY 50000000 #endif diff --git a/include/configs/bcm94908.h b/include/configs/bcm94908.h index 1346ace4bf6..246feb66b29 100644 --- a/include/configs/bcm94908.h +++ b/include/configs/bcm94908.h @@ -6,6 +6,6 @@ #ifndef __BCM94908_H #define __BCM94908_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm94912.h b/include/configs/bcm94912.h index f3d17ddaacf..c428b1ab578 100644 --- a/include/configs/bcm94912.h +++ b/include/configs/bcm94912.h @@ -6,6 +6,6 @@ #ifndef __BCM94912_H #define __BCM94912_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm963138.h b/include/configs/bcm963138.h index 361569a8c5f..f1b68ba6733 100644 --- a/include/configs/bcm963138.h +++ b/include/configs/bcm963138.h @@ -6,7 +6,7 @@ #ifndef __BCM963138_H #define __BCM963138_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_HZ_CLOCK 500000000 #endif diff --git a/include/configs/bcm963146.h b/include/configs/bcm963146.h index edbdfc3c51a..90dfa98311d 100644 --- a/include/configs/bcm963146.h +++ b/include/configs/bcm963146.h @@ -6,6 +6,6 @@ #ifndef __BCM963146_H #define __BCM963146_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm963148.h b/include/configs/bcm963148.h index 5a24cccba10..54f6750c743 100644 --- a/include/configs/bcm963148.h +++ b/include/configs/bcm963148.h @@ -6,6 +6,6 @@ #ifndef __BCM963148_H #define __BCM963148_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm963158.h b/include/configs/bcm963158.h index b15c4111c96..2fdd22d1b0d 100644 --- a/include/configs/bcm963158.h +++ b/include/configs/bcm963158.h @@ -6,6 +6,6 @@ #ifndef __BCM963158_H #define __BCM963158_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm963178.h b/include/configs/bcm963178.h index b25f6a12819..32fc4a5e390 100644 --- a/include/configs/bcm963178.h +++ b/include/configs/bcm963178.h @@ -6,6 +6,6 @@ #ifndef __BCM963178_H #define __BCM963178_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96756.h b/include/configs/bcm96756.h index c8f32672b7d..c69d177da2e 100644 --- a/include/configs/bcm96756.h +++ b/include/configs/bcm96756.h @@ -6,6 +6,6 @@ #ifndef __BCM96756_H #define __BCM96756_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96813.h b/include/configs/bcm96813.h index 5d9e87b693a..37d2d91d96f 100644 --- a/include/configs/bcm96813.h +++ b/include/configs/bcm96813.h @@ -6,6 +6,6 @@ #ifndef __BCM96813_H #define __BCM96813_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96846.h b/include/configs/bcm96846.h index 1d6d5d61669..581fd559856 100644 --- a/include/configs/bcm96846.h +++ b/include/configs/bcm96846.h @@ -6,6 +6,6 @@ #ifndef __BCM96846_H #define __BCM96846_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96855.h b/include/configs/bcm96855.h index 6e420f2c66f..3fb1ab9230c 100644 --- a/include/configs/bcm96855.h +++ b/include/configs/bcm96855.h @@ -6,6 +6,6 @@ #ifndef __BCM96855_H #define __BCM96855_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96856.h b/include/configs/bcm96856.h index a7ae71eeaaf..5f5af321897 100644 --- a/include/configs/bcm96856.h +++ b/include/configs/bcm96856.h @@ -6,6 +6,6 @@ #ifndef __BCM96856_H #define __BCM96856_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96858.h b/include/configs/bcm96858.h index 4e584b41fb3..9a0d89a7519 100644 --- a/include/configs/bcm96858.h +++ b/include/configs/bcm96858.h @@ -6,6 +6,6 @@ #ifndef __BCM96858_H #define __BCM96858_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96878.h b/include/configs/bcm96878.h index 3e23e94ac4b..7702d1f5682 100644 --- a/include/configs/bcm96878.h +++ b/include/configs/bcm96878.h @@ -6,6 +6,6 @@ #ifndef __BCM96878_H #define __BCM96878_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index 76189a4d31f..b5469880fe2 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -15,7 +15,7 @@ #define V2M_BASE 0x80000000 #define PHYS_SDRAM_1 V2M_BASE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* * Initial SP before reloaction is placed at end of first DRAM bank, diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 9f51b9ca59d..9769a714092 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -81,7 +81,7 @@ extern phys_addr_t prior_stage_fdt_address; * MiB. However, BOLT can be configured to allow loading larger * initramfs images, in which case this limitation is eliminated. */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x100000 /* diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h index 829e816ad66..556bfa08ebb 100644 --- a/include/configs/bitmain_antminer_s9.h +++ b/include/configs/bitmain_antminer_s9.h @@ -6,8 +6,8 @@ #ifndef __CONFIG_BITMAIN_ANTMINER_S9_H #define __CONFIG_BITMAIN_ANTMINER_S9_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000 #define CONFIG_EXTRA_ENV_SETTINGS \ "pxefile_addr_r=0x2000000\0" \ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index ca2bc1907e3..a075a5b2f32 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -199,7 +199,7 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (SZ_512M) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h index c328f414201..e40f110cac6 100644 --- a/include/configs/bmips_bcm3380.h +++ b/include/configs/bmips_bcm3380.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index d16d50e5ec2..508317f231e 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index f69c46b11c4..c5bda16d2bc 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index acd021ecadc..32397c26e8a 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h index fa9e5f02a08..18c99727a04 100644 --- a/include/configs/bmips_bcm6338.h +++ b/include/configs/bmips_bcm6338.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index bcf5c874d32..f8d7148d497 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index e31b8bc719e..d564a32ee52 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index 6e707d341b7..f982a4363db 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index bb72c8cb533..11d623c28b2 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h index a1c992b7a6e..30965c85bfa 100644 --- a/include/configs/bmips_bcm6838.h +++ b/include/configs/bmips_bcm6838.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/boston.h b/include/configs/boston.h index a09e831c540..0033a7fb022 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -22,9 +22,9 @@ * Memory map */ #ifdef CONFIG_64BIT -# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +# define CFG_SYS_SDRAM_BASE 0xffffffff80000000 #else -# define CONFIG_SYS_SDRAM_BASE 0x80000000 +# define CFG_SYS_SDRAM_BASE 0x80000000 #endif #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index bdedf7ea2d7..78b2000aa2e 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -76,7 +76,7 @@ BUR_COMMON_ENV \ /* RAM */ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 1bf6baf75c2..f1734aaca7f 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -45,7 +45,7 @@ * always, even when we have more. We always start at 0x80000000, * and we place the initial stack pointer in our SRAM. */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* * Our platforms make use of SPL to initalize the hardware (primarily diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index c4110f84c0b..474ad69d996 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -92,7 +92,7 @@ /* On CCP board, USDHC1 is for eMMC */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 /* DDR3 board total DDR is 1 GB */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index c395384c8d3..6f2b8245b98 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -111,7 +111,7 @@ #define CFG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/ci20.h b/include/configs/ci20.h index b7511adc09a..f268dfd0943 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -11,7 +11,7 @@ /* Memory configuration */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ +#define CFG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 /* NS16550-ish UARTs */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index fc45e597f6d..eb899c45578 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -82,7 +82,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 25443629e20..47c4aacc436 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -21,7 +21,7 @@ /* RAM */ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 52000b58b73..65b9074cd9c 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -30,7 +30,7 @@ */ #define CONFIG_SYS_CLK 66000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ /* --- * Define baudrate for UART1 (console output, tftp, ...) @@ -152,9 +152,9 @@ enter a valid image address in flash */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* *------------------------------------------------------------------------- @@ -162,7 +162,7 @@ enter a valid image address in flash */ *----------------------------------------------------------------------- */ -/* #define CONFIG_SYS_SDRAM_SIZE 16 */ +/* #define CFG_SYS_SDRAM_SIZE 16 */ /* *----------------------------------------------------------------------- @@ -186,8 +186,8 @@ enter a valid image address in flash */ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index afe8badd650..ca8445a3d05 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -116,7 +116,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index d641fbf47e7..6002d8d5c9f 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -96,7 +96,7 @@ /* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ #define CFG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 68d923c1ae1..14278e9ca4f 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -100,7 +100,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index f9bf849ae98..c08095561d8 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -160,7 +160,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 0f6f99d244f..11283071397 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -85,7 +85,7 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (256 * SZ_1M) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h index 8e0230c135e..8aec52d508e 100644 --- a/include/configs/corstone1000.h +++ b/include/configs/corstone1000.h @@ -22,7 +22,7 @@ #define PHYS_SDRAM_1 (V2M_BASE) #define PHYS_SDRAM_1_SIZE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 9d44e6723e2..c7a3e47437b 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -32,8 +32,8 @@ #define CONFIG_USART_ID ATMEL_ID_SYS /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 4f0188dd19e..e2e1cfedbde 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -166,7 +166,7 @@ /* Load U-Boot Image From MMC */ /* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CFG_SYS_SDRAM_BASE 0xc0000000 #include diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index b944d50663c..b16f3d48e38 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -42,7 +42,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_512M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 5244b9cf5cc..c473f3d86eb 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -15,8 +15,8 @@ /* * Memory configurations */ -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_64M +#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CFG_SYS_SDRAM_SIZE SZ_64M /* * DMA diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index e694dd7551a..ddc436d5019 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -72,7 +72,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/display5.h b/include/configs/display5.h index 0e5ecab9feb..0a7428b02ca 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -283,7 +283,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index c37b4c635b2..daf7ecd7975 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -17,7 +17,7 @@ #define PHYS_SDRAM_1 0x80000000 /* Note: 8 MiB (0x86000000 - 0x86800000) are reserved for tz/smem/hyp/rmtfs/rfsa */ #define PHYS_SDRAM_1_SIZE SZ_1G -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Environment */ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h index 1fa5d05e7b4..31cd8536de4 100644 --- a/include/configs/dragonboard820c.h +++ b/include/configs/dragonboard820c.h @@ -19,7 +19,7 @@ #define PHYS_SDRAM_2 0x100000000 #define PHYS_SDRAM_2_SIZE 0x5ea4ffff -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #include diff --git a/include/configs/durian.h b/include/configs/durian.h index 8f0e8be4330..001596c00a4 100644 --- a/include/configs/durian.h +++ b/include/configs/durian.h @@ -11,7 +11,7 @@ /* Sdram Bank #1 Address */ #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_1_SIZE 0x7B000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* BOOT */ diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h index 1d655292d7e..fc1c2aed778 100644 --- a/include/configs/ea-lpc3250devkitv2.h +++ b/include/configs/ea-lpc3250devkitv2.h @@ -13,7 +13,7 @@ /* * RAM */ -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE /* * cmd diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 80a820c913b..80de73d15d5 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -66,13 +66,13 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE0 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE0 0x00000000 +#define CFG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 +#define CFG_SYS_SDRAM_BASE CFG_SYS_SDRAM_BASE0 +#define CFG_SYS_SDRAM_SIZE CFG_SYS_SDRAM_SIZE0 /* * For booting Linux, the board info and command line data @@ -103,8 +103,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DBWE | \ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index 16d2648e11f..d24bc56f34a 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -50,7 +50,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index a4891ddbc4f..e39bb94314f 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -27,7 +27,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h index 60fab0419f5..c2b921e7cb8 100644 --- a/include/configs/emsdp.h +++ b/include/configs/emsdp.h @@ -8,8 +8,8 @@ #include -#define CONFIG_SYS_SDRAM_BASE 0x10000000 -#define CONFIG_SYS_SDRAM_SIZE SZ_16M +#define CFG_SYS_SDRAM_BASE 0x10000000 +#define CFG_SYS_SDRAM_SIZE SZ_16M /* * Environment diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h index 2f067a44248..b4f14a9a589 100644 --- a/include/configs/espresso7420.h +++ b/include/configs/espresso7420.h @@ -10,7 +10,7 @@ #include -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index f19e12d9090..97a8ffb4f61 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -26,8 +26,8 @@ #define CONFIG_SYS_INIT_RAM_SIZE (32 << 10) /* 128MB SDRAM in 1 bank */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE (128 << 20) +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE (128 << 20) /* 512kB on-chip NOR flash */ # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 44f5cb1e83f..dd322c2b3a7 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -29,21 +29,21 @@ #define CONFIG_RD_LVL -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE /* SPI */ diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 8e2f135f934..cc0cf5ecbfb 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_5250_H #define __CONFIG_5250_H -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index a8bef860c2f..cff910c1bd5 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -23,21 +23,21 @@ /* select serial console configuration */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE /* Configuration of ENV Blocks */ diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h index b05846d0b92..68c36dc2fd9 100644 --- a/include/configs/exynos78x0-common.h +++ b/include/configs/exynos78x0-common.h @@ -21,32 +21,32 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600} -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_9 (CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_9 (CFG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_9_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_10 (CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_10 (CFG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_10_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_11 (CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_11 (CFG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_11_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_12 (CFG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE #ifndef MEM_LAYOUT_ENV_SETTINGS diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index ba098316e08..f5353ec79a1 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -18,8 +18,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ /* NAND flash */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index a1400eba1ad..a7557144402 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -7,7 +7,7 @@ #define __CONFIG_GARDENA_SMART_GATEWAY_H /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index fa6f0e63ac5..6cdfe8c4c3c 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -12,9 +12,9 @@ /* * DDR Setup */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +/* TODO: Check: Can this be unified with CFG_SYS_SDRAM_BASE? */ +#define CONFIG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE /* * Memory test diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index c862f15ee2b..85ceaf8ccb1 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -37,7 +37,7 @@ /* Memory */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index d519384d026..1dba2e92fb9 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -94,7 +94,7 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index d2138c220f0..dd6b22de7ba 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -13,8 +13,8 @@ /* Miscellaneous */ /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) /* Network interface */ #define CONFIG_SH_ETHER_USE_PORT 0 diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 645ca162a35..fe00272a1bd 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -53,7 +53,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/gxp.h b/include/configs/gxp.h index e3c97b20d51..2b0b04891cc 100644 --- a/include/configs/gxp.h +++ b/include/configs/gxp.h @@ -10,6 +10,6 @@ #ifndef _GXP_H_ #define _GXP_H_ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #endif diff --git a/include/configs/highbank.h b/include/configs/highbank.h index a7d21a76dba..0d281a3379a 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -14,7 +14,7 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x20000000\0" \ diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 18c1e83aeb4..775f166f1d3 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -24,7 +24,7 @@ /* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/ #define PHYS_SDRAM_1_SIZE 0x3EFFFFFF -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index 973df8e4abc..914c3ad9ef0 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -16,7 +16,7 @@ #define PHYS_SDRAM_1 0x00000000 #define PHYS_SDRAM_1_SIZE 0xC0000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index 1d7b171da75..fcb2dec54ec 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -22,8 +22,8 @@ */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_1G +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_1G /* * UART configuration diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 9e092e16ea0..0ae935208ca 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -21,8 +21,8 @@ */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_1G +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_1G /* * UART configuration diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h index 1fc45f9060b..f1ca28b7ca3 100644 --- a/include/configs/imgtec_xilfpga.h +++ b/include/configs/imgtec_xilfpga.h @@ -21,8 +21,8 @@ */ /* SDRAM Configuration (for final code, data, stack, heap) */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ /*---------------------------------------------------------------------- * Commands diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 974dff8f6f4..594aa4f75e7 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -130,5 +130,5 @@ "upd=run load update\0" \ /* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #endif /* __IMX27LITE_COMMON_CONFIG_H */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index b8eb5c82cf7..d4e2583ee8a 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -109,7 +109,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 6b822e72505..1b08c5e9a7e 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -105,7 +105,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index f7f8f33ed89..a074df5829b 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -55,7 +55,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 15171d7ad67..855af29ec96 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -85,7 +85,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index 70b4b84215d..0a688afe6cd 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -63,7 +63,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index c6db5e943ee..e5118f11580 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -69,7 +69,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 917d567d2ec..e62f9c5462b 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -127,7 +127,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 8e088994580..143da001104 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -74,7 +74,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index dd9f93f35c2..c7669305f59 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -21,7 +21,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */ diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index f1d1c1c9c3d..9937071874f 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -57,7 +57,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index 9cdba70493b..cd47d842ffc 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -41,7 +41,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 065356341fc..58e165c35a7 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -32,7 +32,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 0ae3da12ad3..f532c1052f5 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -78,7 +78,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR) #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index d6959ac95a1..415248eadfc 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -26,7 +26,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #endif /* __IMX8MN_BSH_SMM_S2_COMMON_H */ diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 9c75e3eec15..8857bc7c598 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -49,7 +49,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index a484d913649..628bb5813ff 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -46,7 +46,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */ diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index d5252abb218..a169be35a49 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -26,7 +26,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index bf878251364..62bcef5eecd 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -14,7 +14,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x20000000 /* Minimum 512 MiB DDR */ diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 1b533e2c142..d394762e3bb 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -55,7 +55,7 @@ /* Totally 2GB DDR */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index 7986d20eed1..3e995c97217 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -56,7 +56,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 /* Totally 2GB DDR */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 8f2b474817d..1943a24b79d 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -136,7 +136,7 @@ /* Totally 6GB or 4G DDR */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G) #define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */ diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index b1c213cc89b..7d360583c41 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -26,7 +26,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 4b2107e4057..271376cb9fc 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -50,7 +50,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 2d4c8d78c67..672a9fa7a34 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -56,7 +56,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 1905e538c5b..dd354b0265d 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -88,7 +88,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 7f6d59db3aa..f1f907f3e5a 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -103,7 +103,7 @@ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 67f19bc1922..fe27ac36a3b 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -108,7 +108,7 @@ */ #define CFG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 567351fcad6..19f1dba0470 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -103,7 +103,7 @@ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 7bf0ce784c5..592df2795b1 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -54,7 +54,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index b2814664086..077a4d843dc 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -127,7 +127,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 512e0e61aa7..8d0458d1d63 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -30,7 +30,7 @@ */ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* * FLASH and environment organization diff --git a/include/configs/iot_devkit.h b/include/configs/iot_devkit.h index a2e50c3b8df..5a769e07871 100644 --- a/include/configs/iot_devkit.h +++ b/include/configs/iot_devkit.h @@ -32,12 +32,12 @@ * : : * : Specified explicitly by CONFIG_CUSTOM_SYS_INIT_SP_ADDR * : - * Specified explicitly by CONFIG_SYS_SDRAM_BASE + * Specified explicitly by CFG_SYS_SDRAM_BASE * * NOTES: * - Stack starts from CONFIG_CUSTOM_SYS_INIT_SP_ADDR and grows down, - * i.e. towards CONFIG_SYS_SDRAM_BASE but nothing stops it from crossing - * that CONFIG_SYS_SDRAM_BASE in which case data won't be really saved on + * i.e. towards CFG_SYS_SDRAM_BASE but nothing stops it from crossing + * that CFG_SYS_SDRAM_BASE in which case data won't be really saved on * stack any longer and values popped from stack will contain garbage * leading to unexpected behavior, typically but not limited to: * - "Returning" back to bogus caller function @@ -50,16 +50,16 @@ #define DCCM_BASE 0x80000000 #define DCCM_SIZE SZ_128K -#define CONFIG_SYS_SDRAM_BASE DCCM_BASE -#define CONFIG_SYS_SDRAM_SIZE DCCM_SIZE +#define CFG_SYS_SDRAM_BASE DCCM_BASE +#define CFG_SYS_SDRAM_SIZE DCCM_SIZE #define ROM_BASE CONFIG_SYS_MONITOR_BASE #define ROM_SIZE SZ_256K #define RAM_DATA_BASE SYS_INIT_SP_ADDR -#define RAM_DATA_SIZE CONFIG_SYS_SDRAM_SIZE - \ +#define RAM_DATA_SIZE CFG_SYS_SDRAM_SIZE - \ (SYS_INIT_SP_ADDR - \ - CONFIG_SYS_SDRAM_BASE) - \ + CFG_SYS_SDRAM_BASE) - \ CONFIG_SYS_MALLOC_LEN - \ CONFIG_ENV_SIZE #endif /* _CONFIG_IOT_DEVKIT_H_ */ diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index 9f54f259994..2a0b0c7163a 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -16,7 +16,7 @@ #include /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 /* FLASH Configuration */ #define CONFIG_SYS_FLASH_BASE 0x000000000 diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index 932d7d3c8cb..e690ef95906 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -17,7 +17,7 @@ #include /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 7d36a25dc23..db1daee1363 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -7,7 +7,7 @@ /* * DDR Setup */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) @@ -17,7 +17,7 @@ /* * Manually set up DDR parameters */ -#define CONFIG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */ +#define CFG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */ /* * The reserved memory diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index ad9853ab6b3..b5913ed7000 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -20,7 +20,7 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x54 diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index c8423fdfb0a..dbf038cefa0 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -163,10 +163,10 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x54 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /****************************************************************************** * (PRAM usage) diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index b3e1fc2a864..e2808ec02dc 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -14,7 +14,7 @@ /* RAM */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index a2aedefcec2..73b59517621 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -17,7 +17,7 @@ /* RAM */ #define PHYS_SDRAM DDR_CSD1_BASE_ADDR #define PHYS_SDRAM_SIZE (SZ_4G) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 6acd2f79253..9b452818c1e 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -64,7 +64,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 7ed1f153c23..bbf0761814b 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -21,7 +21,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL /* early stack pointer */ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index c401fd32169..967de66f3c9 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -67,7 +67,7 @@ #define PHYS_SDRAM_1_SIZE (512 * SZ_1M) #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index b0e49ad6df0..de1fc0bfa4c 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -86,7 +86,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 1f642fbecc3..bee064c6f38 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -85,7 +85,7 @@ "bootscript=source ${bootscraddr}\0" /* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CFG_SYS_SDRAM_BASE 0xc0000000 #include diff --git a/include/configs/librem5.h b/include/configs/librem5.h index dbd7d107dae..3a2c508ffac 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -82,7 +82,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB LPDDR4 one Rank */ diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 28372d41590..b9134508853 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -7,7 +7,7 @@ #define __CONFIG_LINKIT_SMART_7688_H /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 1d51b87b68b..d1ebd99ae14 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -87,7 +87,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 196e024b57e..f0a9e9ab315 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -9,7 +9,7 @@ #include "ls1012a_common.h" /* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000 #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 809f9ae8c8d..07124370775 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -12,7 +12,7 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL /*SPI device */ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 674bcbeb758..c19ed2f43ec 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -10,7 +10,7 @@ #include "ls1012a_common.h" /* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 9ad3a120118..54555b34dd4 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -10,7 +10,7 @@ #include "ls1012a_common.h" /* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000 /* * QIXIS Definitions diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 4f77acdaede..d74936d1281 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -10,7 +10,7 @@ #include "ls1012a_common.h" /* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000 /* * I2C IO expander diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 3579f9c8437..49a77fd6b6b 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -42,7 +42,7 @@ #define SDRAM_CFG_BI 0x00000001 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* * Serial Port diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 45665115f66..1f5a80ff085 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -20,7 +20,7 @@ #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 1e2db12a83f..49546066115 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -57,7 +57,7 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* Serial Port */ #define CFG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 323feb6e333..d77224934c0 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -60,7 +60,7 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* * IFC Definitions diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 587f23be587..064c4f069cb 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -15,7 +15,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL /* diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index df6338298b4..e940dff9988 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -34,7 +34,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CPU_RELEASE_ADDR secondary_boot_addr diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index b09588f4796..ce254d8b3f1 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -34,7 +34,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CPU_RELEASE_ADDR secondary_boot_addr diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 2117b081168..f8eaee881d0 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -32,7 +32,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL /* * SMP Definitinos diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index c79a50795b8..21c097ecbbd 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -19,7 +19,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL /* diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 8b2b7479c11..ad85e2de6ed 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -17,8 +17,8 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL -#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE 0x200000000UL +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 1734f323f92..cbdb2fa1357 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -20,7 +20,7 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) diff --git a/include/configs/malta.h b/include/configs/malta.h index 2dd34ea7313..c9aee00cd35 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -22,11 +22,11 @@ */ #ifdef CONFIG_64BIT -# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +# define CFG_SYS_SDRAM_BASE 0xffffffff80000000 #else -# define CONFIG_SYS_SDRAM_BASE 0x80000000 +# define CFG_SYS_SDRAM_BASE 0x80000000 #endif -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index db84302231a..5ad945b5589 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -47,6 +47,6 @@ */ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_SDRAM_SIZE SZ_1G +#define CFG_SYS_SDRAM_SIZE SZ_1G #endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index f9f0825f6f8..8aa3b0cd808 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -214,7 +214,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index c6ce8837474..2422cbf9f0b 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -17,7 +17,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/meesc.h b/include/configs/meesc.h index cd3910ee4ba..2e07886c194 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -44,8 +44,8 @@ #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 726f33c26c2..6331b7615db 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -36,7 +36,7 @@ #define STDIN_CFG "serial" #endif -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 /* ROM USB boot support, auto-execute boot.scr at scriptaddr */ #define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 4c7cfac8af7..3def93d61e8 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -9,7 +9,7 @@ #include -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index bd35378800b..ac5ff9289a5 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -49,7 +49,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ #define PHYS_SDRAM_2 0xc0000000 diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h index c76e1fcaed9..65cd6f5bc4c 100644 --- a/include/configs/mt7620.h +++ b/include/configs/mt7620.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_MT7620_H #define __CONFIG_MT7620_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index e09e9c82eb8..1211bb47488 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_MT7621_H #define __CONFIG_MT7621_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED 0x1c000000 diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index fd8e30acf59..e5d60e1cd2b 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -15,7 +15,7 @@ /* SPL -> Uboot */ #define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* Ethernet */ #define CONFIG_IPADDR 192.168.1.1 diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 73093f94d2b..39a7ba76633 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -21,7 +21,7 @@ #define MMC_SUPPORTS_TUNING /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* This is needed for kernel booting */ #define FDT_HIGH "0xac000000" diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index bb12ebfe4fd..9c5034f5f08 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_MT7628_H #define __CONFIG_MT7628_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_OFFSET 0x80000 diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index 668dc3c4f74..d330adbc01b 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -25,7 +25,7 @@ /* UBoot -> Kernel */ /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* Ethernet */ #define CONFIG_IPADDR 192.168.1.1 diff --git a/include/configs/mt7981.h b/include/configs/mt7981.h index 9f26b0ba7bb..249f0b9662d 100644 --- a/include/configs/mt7981.h +++ b/include/configs/mt7981.h @@ -16,6 +16,6 @@ #define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #endif diff --git a/include/configs/mt7986.h b/include/configs/mt7986.h index 4fbd57a573d..990e411a640 100644 --- a/include/configs/mt7986.h +++ b/include/configs/mt7986.h @@ -16,6 +16,6 @@ #define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #endif diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index 7cabbef9288..8a8bc85ca70 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -10,8 +10,8 @@ #define __MT8518_H /* DRAM definition */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* Uboot definition */ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index e870fc810cb..e45bfd76b6e 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -27,7 +27,7 @@ */ /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* * NS16550 Configuration diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h index 41bdfae6c31..9c4038be8b0 100644 --- a/include/configs/mvebu_alleycat-5.h +++ b/include/configs/mvebu_alleycat-5.h @@ -9,7 +9,7 @@ #include /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x200000000 +#define CFG_SYS_SDRAM_BASE 0x200000000 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 6d3cb99b2df..7641b562219 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -13,7 +13,7 @@ */ /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index 5debd9117c6..358e06fd207 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -12,7 +12,7 @@ #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* auto boot */ diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index dd303a17d61..aa3d7a1a3fc 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -10,7 +10,7 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Status LED */ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 4c0531212ed..f597cdb3056 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -13,7 +13,7 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Extra Environments */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 140f5e98c52..bc8c8933704 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -13,7 +13,7 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* UBI and NAND partitioning */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 95afb350ec3..2229980db37 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -112,7 +112,7 @@ #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 77835639720..e84bac67ef7 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -60,7 +60,7 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 3c9b2ad58ee..9e837a38833 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -95,7 +95,7 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index b26613a2ea8..52ff7b00b43 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -96,7 +96,7 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 1db4d6c01b1..3c4ba095e4e 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -85,7 +85,7 @@ #include /* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index a6cefab5508..9c160c41ece 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -27,7 +27,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index bc9fab12909..711b5a334aa 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -139,7 +139,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index ca1d077437b..3c2621d8c91 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -82,7 +82,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 44a5eeff198..a3a12aeb390 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -82,7 +82,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_2G -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index a41e428eb8a..f0e239fdb6e 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -78,7 +78,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index c655671ee1b..a0f9c537e5d 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -106,7 +106,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 65f0a5c9966..8199b4b8319 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -108,7 +108,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 604923ec2b7..827385c65e2 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -102,7 +102,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index af176583814..c39b3572b84 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -81,7 +81,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index 62e8e629911..362de482f57 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -26,7 +26,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM 0x60000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index e93824928b3..9ef1eea5e61 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -26,7 +26,7 @@ #define PHYS_SDRAM 0x60000000 #define PHYS_SDRAM_SIZE SZ_1G -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 273f938554d..cdd12866ac0 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -22,7 +22,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_256M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index ec5339d930a..9d098113164 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -90,7 +90,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 2623f99f8d0..9ad4f590697 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -161,7 +161,7 @@ * FLASH and environment organization */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 @@ -170,7 +170,7 @@ */ #define SDRAM_SIZE 0x10000000 /* 256 MB */ -#define SDRAM_END (CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE) +#define SDRAM_END (CFG_SYS_SDRAM_BASE + SDRAM_SIZE) #define IMAGE_MAXSIZE 0x1FF800 /* 2 MB - 2 kB */ #define KERNEL_OFFSET 0x40000 /* 256 kB */ diff --git a/include/configs/novena.h b/include/configs/novena.h index 9dc05d80ec2..8d39d75a42b 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -30,7 +30,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index ea407c9f6f1..080c659b6ec 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -23,7 +23,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/nsim.h b/include/configs/nsim.h index d469ef83c24..b930a538640 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -13,8 +13,8 @@ */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_256M +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_256M /* * Console configuration diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index 00f7d871271..5ac951a370a 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -7,7 +7,7 @@ #include "mx6_common.h" #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h index 0fa7490e7de..b475354bbc6 100644 --- a/include/configs/octeon_common.h +++ b/include/configs/octeon_common.h @@ -14,6 +14,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x00180000 #endif -#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +#define CFG_SYS_SDRAM_BASE 0xffffffff80000000 #endif /* __OCTEON_COMMON_H__ */ diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index ab1eb787e70..03d1a8e7b5f 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -10,7 +10,7 @@ /** Maximum size of image supported for bootm (and bootable FIT images) */ /** Memory base address */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_TEXT_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_TEXT_BASE /** Stack starting address */ diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 38f99ab2167..58275ccffa0 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -36,7 +36,7 @@ /** Maximum size of image supported for bootm (and bootable FIT images) */ /** Memory base address */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_TEXT_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_TEXT_BASE /** Stack starting address */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index babd3ca9631..ce8ea583fa1 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -17,9 +17,9 @@ #define CONFIG_SYS_PL310_BASE 0x10502000 #endif -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #include diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 15646297423..d2d7fca5445 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define TZPC_BASE_OFFSET 0x10000 diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 2b47d4ca376..5b0d87a3367 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -154,7 +154,7 @@ /* defines for SPL */ /* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CFG_SYS_SDRAM_BASE 0xc0000000 #include diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h index 3ff8187b5df..5b097e9fef2 100644 --- a/include/configs/openpiton-riscv64.h +++ b/include/configs/openpiton-riscv64.h @@ -14,7 +14,7 @@ #include /* Environment options */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* --------------------------------------------------------------------- * Board boot configuration diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index b3cdd2f1ebe..53889d699b2 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -14,7 +14,7 @@ #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR /* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/origen.h b/include/configs/origen.h index 36aaa7c14fb..6633d541a31 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -11,8 +11,8 @@ #include /* ORIGEN has 4 bank of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ /* Power Down Modes */ diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h index b0233b96b06..8d0311cfb3b 100644 --- a/include/configs/owl-common.h +++ b/include/configs/owl-common.h @@ -11,7 +11,7 @@ #define _OWL_COMMON_CONFIG_H_ /* SDRAM Definitions */ -#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_SDRAM_BASE 0x0 /* Some commands use this as the default load address */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 6e8ac1b98df..14d702e1efe 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -125,13 +125,13 @@ #define SPD_EEPROM_ADDRESS 0x52 #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G +#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G #else -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G +#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G #endif -#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) +#define CFG_SYS_SDRAM_SIZE (1u << (CFG_SYS_SDRAM_SIZE_LAW - 19)) #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* Default settings for DDR3 */ #ifndef CONFIG_TARGET_P2020RDB diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 6267dc729ab..85cedde0988 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -34,7 +34,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_256M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index e13b5df0fab..f7e36f22ce8 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -36,7 +36,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_256M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index a04a03a7e18..586cddf4184 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -118,7 +118,7 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 14cbfde28bf..cf705dcb197 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -15,7 +15,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index 7a8d3c63d44..bfc0011fbf9 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -20,7 +20,7 @@ #include #include -#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_POWER_TPS65090_EC diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 2c749ac2143..09c6b4f8dd5 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -20,7 +20,7 @@ #include #include -#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index c98393b7c75..ac68c933a06 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -64,7 +64,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 49cd9d4b3c6..aedaf806e5e 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -63,7 +63,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 4ea16d6115a..d9abbbc28b3 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -23,7 +23,7 @@ (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE) /* SDRAM Configuration (for final code, data, stack, heap) */ -#define CONFIG_SYS_SDRAM_BASE 0x88000000 +#define CFG_SYS_SDRAM_BASE 0x88000000 /* Memory Test */ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index f95beeb214a..fc2cab960c6 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -91,7 +91,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 85772ba6e83..22b4976d722 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -91,7 +91,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index b3a38d8a940..f5b9eed2bcd 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -93,7 +93,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 17af19d49dc..91baff96386 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -67,7 +67,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */ diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index adb2f43ea4d..3fbddd903a3 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -78,22 +78,22 @@ /* Memory Device Register -> SDRAM */ #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ @@ -160,6 +160,6 @@ "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ "" -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #endif diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 4352a242de3..c1f6334d6a1 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -90,22 +90,22 @@ /* Memory Device Register -> SDRAM */ #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ @@ -184,6 +184,6 @@ "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ "" -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #endif diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index a7deaa32137..4a0a16818ed 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -20,8 +20,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x70000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0x70000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/poleg.h b/include/configs/poleg.h index 05253d59efd..365fdd30c08 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -11,7 +11,7 @@ #endif #define CONFIG_SYS_BOOTMAPSZ (0x30 << 20) -#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_SDRAM_BASE 0x0 /* Default environemnt variables */ #define CONFIG_SERVERIP 192.168.0.1 diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h index 2e206542f8d..1c11685f49e 100644 --- a/include/configs/pomelo.h +++ b/include/configs/pomelo.h @@ -9,7 +9,7 @@ #define __POMELO_CONFIG_H__ /* SDRAM Bank #1 start address */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* SIZE of malloc pool */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index f9decb2a4c2..bee1ef64948 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -36,7 +36,7 @@ #define DDR_BASE 0x00000000 #define PHYS_SDRAM_1 DDR_BASE #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Console I/O Buffer Size */ diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 8b151ef1883..99376155b49 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -14,7 +14,7 @@ #define GICD_BASE 0xff131000 #define GICC_BASE 0xff132000 -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30) diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 535762ecb24..a67af73fd56 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -10,7 +10,7 @@ /* Physical memory map */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* GUIDs for capsule updatable firmware images */ #define QEMU_ARM_UBOOT_IMAGE_GUID \ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 9fc51fdfd76..e7c810957d6 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -31,7 +31,7 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_HWCONFIG diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index d81e5d6c862..72f35cc0542 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -8,7 +8,7 @@ #include -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index 406ee6282c5..f6ee7201eba 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -6,8 +6,8 @@ /* SCIF */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x8C000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE 0x8C000000 +#define CFG_SYS_SDRAM_SIZE 0x04000000 /* Address of u-boot image in Flash */ #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 3a38e0656de..61b9447ea5f 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -17,8 +17,8 @@ /* console */ #define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } -#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) +#define CFG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) +#define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) /* Timer */ #define CONFIG_TMU_TIMER diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 7432cffb5a5..58530725978 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -26,8 +26,8 @@ /* MEMORY */ #define DRAM_RSV_SIZE 0x08000000 -#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) -#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) +#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 6616396777a..b4c19727478 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -10,7 +10,7 @@ #define CONFIG_SYS_HZ_CLOCK 24000000 -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE) diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index 9297184bded..99c86edeaa4 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -11,7 +11,7 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (1024UL << 20UL) #define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 12d4bc65d7e..fac27a7d27c 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -14,7 +14,7 @@ /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_MAX_SIZE 0x80000000 /* usb mass storage */ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 6fe1b2d9a2e..334fb3affa5 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -13,7 +13,7 @@ /* spl size 32kb sram - 2kb bootrom */ -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0x80000000 diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 4fb86b69a8e..6889ba591b3 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -12,7 +12,7 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE 0x80000000 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 81f16edbad6..4aa7e0449db 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -15,7 +15,7 @@ /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0xfe000000 diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 263d1bd180c..4b510b13991 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -10,7 +10,7 @@ #define CONFIG_IRAM_BASE 0xfff80000 -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30) diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 1e214e4ebe1..132b7d0fe9b 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -11,7 +11,7 @@ #define CONFIG_IRAM_BASE 0xff090000 /* FAT sd card locations. */ -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 37e0c1d936c..92cdc1a51fb 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -11,7 +11,7 @@ #include #include -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_IRAM_BASE 0xff8c0000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 2f9aee58197..78f624d31ca 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -21,7 +21,7 @@ /* RAW SD card / eMMC locations. */ /* FAT sd card locations. */ -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000 #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index 15e81523402..d43dc2580e4 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -10,7 +10,7 @@ #define CONFIG_IRAM_BASE 0xfdcc0000 -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000 #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rpi.h b/include/configs/rpi.h index cd8fe8b518b..2c24944d9c3 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -23,7 +23,7 @@ #endif /* Memory layout */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* * The board really has 256M. However, the VC (VideoCore co-processor) shares @@ -31,7 +31,7 @@ * smaller amount of RAM is present in order to avoid stomping on the area * the VC uses. */ -#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CFG_SYS_SDRAM_SIZE SZ_128M /* Devices */ /* LCD */ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 83c3167f38d..76836add302 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -15,7 +15,7 @@ #define CONFIG_SYS_TIMER_BASE 0x10350020 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 /* rockchip ohci host driver */ diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index ae94f0ecc56..e071d4da5e8 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -18,7 +18,7 @@ /*----------------------------------------------------------------------- * System memory Configuration */ -#define CONFIG_SYS_SDRAM_BASE 0x71000000 +#define CFG_SYS_SDRAM_BASE 0x71000000 /* * "(0x40000000 - CONFIG_SYS_RESERVE_MEM_SIZE)" has been used in @@ -55,7 +55,7 @@ * Starting kernel ... * ... */ -#define CONFIG_SYS_SDRAM_SIZE (0xb0000000 - CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_SDRAM_SIZE (0xb0000000 - CFG_SYS_SDRAM_BASE) #define BMP_LOAD_ADDR 0x78000000 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index de4510aa434..ed891ab22a9 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -14,7 +14,7 @@ #include /* get chip and board defs */ /* DRAM Base */ -#define CONFIG_SYS_SDRAM_BASE 0x30000000 +#define CFG_SYS_SDRAM_BASE 0x30000000 /* Text Base */ @@ -114,7 +114,7 @@ "dfu_alt_info=" CONFIG_DFU_ALT "\0" /* Goni has 3 banks of DRAM, but swap the bank */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ #define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */ #define PHYS_SDRAM_2 0x40000000 /* mDDR DMC1 Bank #1 */ #define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in Bank #1 */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 668b52600e8..614d04fda07 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -14,8 +14,8 @@ /* Keep L2 Cache Disabled */ /* Universal has 2 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h index afb1e3d0f10..75302bf5c05 100644 --- a/include/configs/sam9x60_curiosity.h +++ b/include/configs/sam9x60_curiosity.h @@ -17,7 +17,7 @@ #define CONFIG_USART_ID 0 /* ignored in arm */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */ #endif diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 7c5bfdb2e6d..22813d4c544 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -23,8 +23,8 @@ */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index de6c92ed7d4..f826eab9ff2 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -16,8 +16,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* SPL */ diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h index ebdb39273ef..01ed1a3c8e7 100644 --- a/include/configs/sama5d2_icp.h +++ b/include/configs/sama5d2_icp.h @@ -15,8 +15,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 #ifdef CONFIG_SD_BOOT /* u-boot env in sd/mmc card */ diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h index 09cc4dddb2a..2e3c1ea4006 100644 --- a/include/configs/sama5d2_ptc_ek.h +++ b/include/configs/sama5d2_ptc_ek.h @@ -16,8 +16,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* NAND Flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 1c9af9b6759..4b13a101170 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -24,8 +24,8 @@ #define ATMEL_PMC_UHP (1 << 6) /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index afb9b9a2fbf..3f58928565f 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -31,8 +31,8 @@ #endif /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* SerialFlash */ diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 0daadec5536..084cb4def66 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -12,8 +12,8 @@ #include "at91-sama5_common.h" /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index d59899f0baa..cbc1c0f4651 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -12,8 +12,8 @@ #include "at91-sama5_common.h" /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index 3f905bf2d77..68fa31fe76f 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -12,7 +12,7 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x60000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 #endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 0dcb2ebc316..5a7f5e135b5 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -13,8 +13,8 @@ /* Size of our emulated memory */ #define SB_CONCAT(x, y) x ## y #define SB_TO_UL(s) SB_CONCAT(s, UL) -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE \ +#define CFG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_SIZE \ (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20) #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index c9dd7509cb2..31552f4619d 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -33,7 +33,7 @@ /* Physical Memory Map */ #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_DRAM_1 /* Platform/Board specific defs */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index 2e5592cf94d..5ad2124bdda 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -11,7 +11,7 @@ #include -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index 85fab927195..f4b1a16019e 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -11,7 +11,7 @@ #include -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index 7159fc35d52..974531ea0d8 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -8,8 +8,8 @@ #include -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE SZ_8M +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_SIZE SZ_8M #ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 7c8f1676be2..d2bc73a400e 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -45,8 +45,8 @@ * SDRAM: 1 bank, 64 MB, base address 0x20000000 * Already initialized before u-boot gets started. */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M) +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE (64 * SZ_1M) /* * Perform a SDRAM Memtest from the start of SDRAM diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 12c2e1f6159..0392530c0ad 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -14,7 +14,7 @@ #define CONFIG_SMDK5420 /* which is in a SMDK5420 */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index ba562b23780..64963eebe5c 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -16,7 +16,7 @@ /* input clock of PLL: SMDKC100 has 12MHz input clock */ /* DRAM Base */ -#define CONFIG_SYS_SDRAM_BASE 0x30000000 +#define CFG_SYS_SDRAM_BASE 0x30000000 /* Text Base */ @@ -77,7 +77,7 @@ */ /* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE (128 << 20) /* 0x8000000, 128 MB Bank #1 */ /*----------------------------------------------------------------------- diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 0b1f0c5f54c..af0c8200fc2 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -11,7 +11,7 @@ #include "exynos4-common.h" /* High Level Configuration Options */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* Handling Sleep Mode*/ #define S5P_CHECK_SLEEP 0x00000BAD @@ -23,13 +23,13 @@ /* SMDKV310 has 4 bank of DRAM */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE /* FLASH and environment organization */ diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index faa13c65216..44b9109d442 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -38,7 +38,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 7c35c912e59..9b1cb372ece 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -21,8 +21,8 @@ /* CPU */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 -#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CFG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 6054fa42c1a..95516800793 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -32,7 +32,7 @@ * Memory */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* * I2C diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 70a24ed267e..2656c977673 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -38,7 +38,7 @@ * in U-Boot pre-reloc is higher than in SPL. */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* * U-Boot general configurations diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 2b2d78b8c8e..9403e2f4306 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -70,7 +70,7 @@ */ #define PHYS_SDRAM_1 0x0 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 /* * Serial / UART configurations diff --git a/include/configs/socrates.h b/include/configs/socrates.h index a60ac6d1a3c..c628860eac7 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -55,7 +55,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_VERY_BIG_RAM /* I2C addresses of SPD EEPROMs */ @@ -73,7 +73,7 @@ #define CONFIG_SYS_DDR_CONFIG_2 0x04400000 #define CONFIG_SYS_DDR_CONFIG 0xC3008000 #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 -#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ +#define CFG_SYS_SDRAM_SIZE 256 /* in Megs */ /* * Flash on the LocalBus diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index dcb88a3a730..008aa500107 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -53,7 +53,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 1e966a23227..806323e375d 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -11,7 +11,7 @@ /* ram memory-related information */ #define PHYS_SDRAM_1 0x40000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x3E000000 #define CONFIG_SYS_HZ_CLOCK 750000000 /* 750 MHz */ diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index 07a5bfc8a86..d7111493142 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -13,7 +13,7 @@ /* * Configuration of the external SRAM memory used by U-Boot */ -#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE +#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE /* * For booting Linux, use the first 256 MB of memory, since this is diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index b809f9322ad..f78ce41ed85 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -13,7 +13,7 @@ /* * Configuration of the external SRAM memory used by U-Boot */ -#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE +#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE /* * For booting Linux, use the first 256 MB of memory, since this is diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index ba49075ce06..234327e017b 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -56,10 +56,10 @@ /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ #define CONFIG_SYS_DRAM_TEST @@ -75,8 +75,8 @@ * the maximum mapped by the Linux kernel during initialization ?? */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ - (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ + (CFG_SYS_SDRAM_SIZE << 20)) /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -89,8 +89,8 @@ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ CF_CACR_ICINVA | CF_CACR_EUSP) diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 567aa1ffe43..b2dcb6058b1 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -10,7 +10,7 @@ /* ram memory-related information */ #define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x00198000 /* user interface */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index cd2a74fb52d..e1a66f53ff5 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -42,13 +42,13 @@ */ #ifdef CONFIG_MACH_SUN9I #define SDRAM_OFFSET(x) 0x2##x -#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 #elif defined(CONFIG_MACH_SUNIV) #define SDRAM_OFFSET(x) 0x8##x -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #else #define SDRAM_OFFSET(x) 0x4##x -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* V3s do not have enough memory to place code at 0x4a000000 */ #endif @@ -66,7 +66,7 @@ /* FIXME: this may be larger on some SoCs */ #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ -#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ /* mmc config */ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 63d897d090a..daa9bbec88a 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -11,7 +11,7 @@ /* * SDRAM (for initialize) */ -#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ +#define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ #define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */ #define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index dd1fe0af7cd..1aba986e1e6 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -41,8 +41,8 @@ * SDRAM: 1 bank, min 32, max 128 MB * Initialized before u-boot gets started. */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE (128 * SZ_1M) /* * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 92ee920346b..cd1309b3b88 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -13,8 +13,8 @@ */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_128M /* * UART configuration diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 7f197851d0a..2d8bde1cee8 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -13,7 +13,7 @@ /* General configuration */ /* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 92df457e818..7e764b0000b 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -40,7 +40,7 @@ #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 655fcb0011b..76b496303f3 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -68,6 +68,6 @@ /* Defines for SPL */ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_SDRAM_SIZE SZ_2G +#define CFG_SYS_SDRAM_SIZE SZ_2G #endif /* _CONFIG_THEADORABLE_H */ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index cf2efdbe230..1f60b9b4979 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -13,7 +13,7 @@ /* Link Definitions */ /* SMP Spin Table Definitions */ -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#define CPU_RELEASE_ADDR (CFG_SYS_SDRAM_BASE + 0x7fff0) /* PL011 Serial Configuration */ @@ -30,7 +30,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Initial environment variables */ #define UBOOT_IMG_HEAD_SIZE 0x40 diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index fc78077014b..e5b23d2a54c 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -69,7 +69,7 @@ #define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /** * Platform/Board specific defs diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 1bd2a1874b8..4a7c3d5b449 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -20,7 +20,7 @@ #define V_SCLK (V_OSCK >> 1) #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /** * Platform/Board specific defs diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index b289b9e26a0..d54c208ef66 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -64,7 +64,7 @@ * initial stack pointer in our SRAM. Otherwise, we can define * CONFIG_NR_DRAM_BANKS before including this file. */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* If DM_I2C, enable non-DM I2C support */ diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index ab6cd063321..a609aa3a2aa 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -23,7 +23,7 @@ /* Top 48MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x03000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_2 0x8080000000 #define PHYS_SDRAM_2_SIZE 0x180000000 diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 22d783c325b..13789819917 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SDRAM_BASE 0xa0000000 +#define CFG_SYS_SDRAM_BASE 0xa0000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index a65ebfb4dea..f8e3a2d017a 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -268,7 +268,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/trats.h b/include/configs/trats.h index ca318687783..23dcf20c1f4 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -16,8 +16,8 @@ #endif /* TRATS has 4 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ /* Tizen - partitions definitions */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index f324ea7ebeb..9c6433ccfd8 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -17,8 +17,8 @@ #endif /* TRATS2 has 4 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ /* Tizen - partitions definitions */ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index f549f9f7ad0..4ca8eafc914 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -8,7 +8,7 @@ #ifndef _CONFIG_TURRIS_MOX_H #define _CONFIG_TURRIS_MOX_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 268c737e7eb..c1e80b44c85 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -49,7 +49,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 147224806fc..f73092661a1 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -57,7 +57,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 2cdc3fbf737..d2fd23e1d91 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -25,8 +25,8 @@ */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index c381934f31a..e944e78603e 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -60,7 +60,7 @@ #define PHYS_SDRAM CSD0_BASE_ADDR #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 338d8af8fb3..d9e5dfaceaf 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -14,13 +14,13 @@ #define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ) -#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) +#define CFG_SYS_SDRAM_SIZE (128 * SZ_1M) #elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT) -#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M) +#define CFG_SYS_SDRAM_SIZE (256 * SZ_1M) #elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16) -#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M) +#define CFG_SYS_SDRAM_SIZE (512 * SZ_1M) #else #error Unknown DDR size - please add! #endif diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index f513dade6aa..b209d97e5ec 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -60,7 +60,7 @@ /* Environment in eMMC, before config block at the end of 1st "boot sector" */ #endif -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index fea4329d23c..1b9f2ca26f6 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -69,7 +69,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K /* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) #define PHYS_SDRAM_2 0x100000000 diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 0c11b6b3331..9a46d50c6f3 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -96,7 +96,7 @@ /* Top 16MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x01000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO #define PHYS_SDRAM_2 (0x880000000) diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 5d773060d82..ef136c75a83 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -135,7 +135,7 @@ #define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */ /* additions for new relocation code */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Basic environment settings */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 215149af2e0..7b526f725af 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -123,7 +123,7 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (128 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/vinco.h b/include/configs/vinco.h index a1572967618..df0e269b5d2 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -24,8 +24,8 @@ #define CONFIG_SYS_TIMER_COUNTER 0xfc06863c /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x4000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x4000000 /* MMC */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index a0846b3f7c9..7555d97c814 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -23,7 +23,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 2107bec6587..38b940d35ea 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -7,7 +7,7 @@ #define __VOCORE2_CONFIG_H__ /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index b4c757fd921..3acef221327 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -89,7 +89,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/warp7.h b/include/configs/warp7.h index a4b12dc55ed..cba215c379f 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -84,7 +84,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 054eb89d49c..32555c9b6af 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -16,8 +16,8 @@ /* * Memory configurations */ -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CFG_SYS_SDRAM_SIZE SZ_128M #define CONFIG_RTC_DS1374 diff --git a/include/configs/xea.h b/include/configs/xea.h index 19ccf633c40..87f628d4ab8 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -23,7 +23,7 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Extra Environment */ #define CONFIG_HOSTNAME "xea" diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h index 364dae0cd93..612436aeb48 100644 --- a/include/configs/xenguest_arm64.h +++ b/include/configs/xenguest_arm64.h @@ -11,7 +11,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_SYS_SDRAM_BASE +#undef CFG_SYS_SDRAM_BASE #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h index d2c0e91b32e..1b6e26ee396 100644 --- a/include/configs/xilinx_zynqmp_mini_nand.h +++ b/include/configs/xilinx_zynqmp_mini_nand.h @@ -12,7 +12,7 @@ #include -#define CONFIG_SYS_SDRAM_SIZE 0x1000000 -#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_SDRAM_SIZE 0x1000000 +#define CFG_SYS_SDRAM_BASE 0x0 #endif /* __CONFIG_ZYNQMP_MINI_NAND_H */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 7d0402feead..613ed959553 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -21,7 +21,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE (128 << 20) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index b93451cbe07..8739bb24841 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -42,12 +42,12 @@ */ #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 -#define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE +#define CFG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE #else -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 #endif -#define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) +#define CFG_SYS_SDRAM_BASE MEMADDR(0x00000000) /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ @@ -70,12 +70,12 @@ #endif #if defined(CONFIG_MAX_MEM_MAPPED) && \ - CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE + CONFIG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE #define XTENSA_SYS_TEXT_ADDR \ (MEMADDR(CONFIG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) #else #define XTENSA_SYS_TEXT_ADDR \ - (MEMADDR(CONFIG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) + (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) #endif /*==============================*/ diff --git a/include/init.h b/include/init.h index d40d11f33d2..699dc2482c0 100644 --- a/include/init.h +++ b/include/init.h @@ -90,8 +90,8 @@ int dram_init(void); * * If this is not provided, a default implementation will try to set up a * single bank. It will do this if CONFIG_NR_DRAM_BANKS and - * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of - * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to + * CFG_SYS_SDRAM_BASE are set. The bank will have a start address of + * CFG_SYS_SDRAM_BASE and the size will be determined by a call to * get_effective_memsize(). * * Return: 0 if OK, -ve on error diff --git a/include/system-constants.h b/include/system-constants.h index 83b41b384f3..07c3505e8f5 100644 --- a/include/system-constants.h +++ b/include/system-constants.h @@ -12,7 +12,7 @@ #define SYS_INIT_SP_ADDR CONFIG_CUSTOM_SYS_INIT_SP_ADDR #else #ifdef CONFIG_MIPS -#define SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET) +#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET) #else #define SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) diff --git a/post/drivers/memory.c b/post/drivers/memory.c index d249942af06..8deac75ebb0 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -467,7 +467,7 @@ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { struct bd_info *bd = gd->bd; - *vstart = CONFIG_SYS_SDRAM_BASE; + *vstart = CFG_SYS_SDRAM_BASE; *size = (gd->ram_size >= 256 << 20 ? 256 << 20 : gd->ram_size) - (1 << 20); diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c index 1cc07bc8083..b5e9f9ddc98 100644 --- a/test/dm/remoteproc.c +++ b/test/dm/remoteproc.c @@ -208,7 +208,7 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts) * at SDRAM_BASE *device* address (p_paddr field). * Its size is defined by the p_filesz field. */ - phdr->p_paddr = CONFIG_SYS_SDRAM_BASE; + phdr->p_paddr = CFG_SYS_SDRAM_BASE; loaded_firmware_size = phdr->p_filesz; /* @@ -231,7 +231,7 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts) unmap_physmem(loaded_firmware, MAP_NOCACHE); /* Resource table */ - shdr->sh_addr = CONFIG_SYS_SDRAM_BASE; + shdr->sh_addr = CFG_SYS_SDRAM_BASE; rsc_table_size = shdr->sh_size; loaded_rsc_table_paddr = shdr->sh_addr + DEVICE_TO_PHYSICAL_OFFSET; @@ -243,7 +243,7 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts) /* Load and verify */ ut_assertok(rproc_elf32_load_rsc_table(dev, (ulong)valid_elf32, size, &rsc_addr, &rsc_size)); - ut_asserteq(rsc_addr, CONFIG_SYS_SDRAM_BASE); + ut_asserteq(rsc_addr, CFG_SYS_SDRAM_BASE); ut_asserteq(rsc_size, rsc_table_size); ut_asserteq_mem(loaded_firmware, valid_elf32 + shdr->sh_offset, shdr->sh_size); -- cgit v1.3.1 From 3b8dfc42a239cbb1561e7ecbc116b69fb6913355 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:38 -0500 Subject: Convert CONFIG_SYS_TIMER_COUNTS_DOWN to Kconfig This converts the following to Kconfig: CONFIG_SYS_TIMER_COUNTS_DOWN Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/arm/mach-kirkwood/include/mach/config.h | 1 - arch/sh/include/asm/config.h | 1 - configs/alt_defconfig | 1 + configs/bitmain_antminer_s9_defconfig | 1 + configs/blanche_defconfig | 1 + configs/gose_defconfig | 1 + configs/koelsch_defconfig | 1 + configs/lager_defconfig | 1 + configs/porter_defconfig | 1 + configs/r2dplus_defconfig | 1 + configs/silk_defconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_dbm_soc1_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de10_standard_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_is1_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_secu1_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + configs/stout_defconfig | 1 + configs/syzygy_hub_defconfig | 1 + configs/topic_miami_defconfig | 1 + configs/topic_miamilite_defconfig | 1 + configs/topic_miamiplus_defconfig | 1 + configs/vexpress_ca9x4_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/zynq_cse_nand_defconfig | 1 + configs/zynq_cse_nor_defconfig | 1 + configs/zynq_cse_qspi_defconfig | 1 + include/configs/rcar-gen2-common.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/vexpress_common.h | 1 - include/configs/zynq-common.h | 1 - lib/Kconfig | 3 +++ 40 files changed, 36 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index ae1f6fee531..5186f6e4f9a 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -52,7 +52,6 @@ /* Use common timer */ #ifndef CONFIG_TIMER -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK #endif diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h index 09a15da4859..99d8797a549 100644 --- a/arch/sh/include/asm/config.h +++ b/arch/sh/include/asm/config.h @@ -9,7 +9,6 @@ #include /* Timer */ -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4) diff --git a/configs/alt_defconfig b/configs/alt_defconfig index e4d6fc2d2cf..d28cdf4b366 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -105,3 +105,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index cbcbc9b18db..02257176e3e 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -93,4 +93,5 @@ CONFIG_ZYNQ_SERIAL=y # CONFIG_WATCHDOG is not set CONFIG_WDT=y CONFIG_WDT_CDNS=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_EFI_LOADER is not set diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index bed73708074..630a13f9297 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -81,3 +81,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index 55222ebe01f..b918b131d38 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -103,3 +103,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index b4e6baef486..24eff4648ed 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -103,3 +103,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 472d8dafc43..56057e272df 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -105,3 +105,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/porter_defconfig b/configs/porter_defconfig index 83cc54aef90..ca56008cb50 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -103,3 +103,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig index cee9a1ff5c5..4217175345d 100644 --- a/configs/r2dplus_defconfig +++ b/configs/r2dplus_defconfig @@ -57,4 +57,5 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SERIAL_RX_BUFFER=y CONFIG_SCIF_CONSOLE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 9ff9e23ef98..5005e1677fd 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -105,3 +105,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 2951574464b..67c6e74eb84 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 9c3c0f66b2e..ce1a3492992 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -79,3 +79,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index b3ba9ff21e2..01c29a25e34 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -82,3 +82,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 5f5706fbdb2..905afb7d046 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -75,3 +75,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index 1f835bea927..f2a53ba2471 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -72,3 +72,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig index 412b0da0dbd..dbf979ee476 100644 --- a/configs/socfpga_de10_standard_defconfig +++ b/configs/socfpga_de10_standard_defconfig @@ -72,3 +72,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 68a36892fb3..613bf442620 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -60,4 +60,5 @@ CONFIG_SPI=y CONFIG_USB=y CONFIG_USB_DWC2=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_EFI_LOADER is not set diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 3a21bc77a2e..32d7b745207 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -69,3 +69,4 @@ CONFIG_DM_RESET=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 8be8b85c0c2..4d16ec32b61 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -73,3 +73,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index debe22f30ac..7a805df5a34 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -112,4 +112,5 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 31cc03a5fd8..b3de6701f93 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -79,3 +79,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 72a70375360..80a98712f67 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -80,3 +80,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 44e9ba6c884..cbe37d22feb 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -76,3 +76,4 @@ CONFIG_DM_RESET=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 96c0ebbc0cd..cdad36bbfd8 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -116,3 +116,4 @@ CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index 231e22a2a0b..53dce6a1612 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -104,3 +104,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index 179cb522125..aa28a68a865 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index e3ed0b27327..96aa62a7ec1 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index cb156562ba4..41ba8a7487d 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 03d1887cdac..763bd8cccdd 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index 234686eb7b0..70ce13ecccf 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -54,3 +54,4 @@ CONFIG_SMC911X=y CONFIG_SMC911X_32_BIT=y CONFIG_BAUDRATE=38400 CONFIG_CONS_INDEX=0 +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 1db3a2c6352..a4c555dac5c 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -146,6 +146,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y CONFIG_SPL_GZIP=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index 7ca74837aec..74c35f3a4d8 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -78,5 +78,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ZYNQ=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_ARM_DCC=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index 28e9c459817..f1c648a8f9a 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -80,5 +80,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_QUIET_TEST=y CONFIG_ARM_DCC=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 215d5ed5ebf..c623caf5648 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -90,5 +90,6 @@ CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_ARM_DCC=y CONFIG_ZYNQ_QSPI=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 61b9447ea5f..606a0a7ecde 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -22,7 +22,6 @@ /* Timer */ #define CONFIG_TMU_TIMER -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 8) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 2656c977673..7ef7c5da828 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -55,7 +55,6 @@ */ #ifndef CONFIG_TIMER #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) #ifndef CONFIG_SYS_TIMER_RATE #define CONFIG_SYS_TIMER_RATE 25000000 diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index ef136c75a83..de571f63ee1 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -114,7 +114,6 @@ #define CONFIG_SYS_TIMER_RATE 1000000 #define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) -#define CONFIG_SYS_TIMER_COUNTS_DOWN /* PL011 Serial Configuration */ #define CONFIG_PL011_CLOCK 24000000 diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 6574cf92e26..2d6522af81b 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -16,7 +16,6 @@ #define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600 #define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) /* GUIDs for capsule updatable firmware images */ diff --git a/lib/Kconfig b/lib/Kconfig index 6abe1d0a863..c39fc523214 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -15,6 +15,9 @@ config SYS_NUM_ADDR_MAP help Sets the number of entries in the virtual-physical mapping table. +config SYS_TIMER_COUNTS_DOWN + bool "System timer counts down rathe than up" + config PHYSMEM bool "Access to physical memory region (> 4G)" help -- cgit v1.3.1 From 97396cc9ce9963ece8778b3a7c6f918745ef25b2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:39 -0500 Subject: Convert CONFIG_SYS_SRIO et al to Kconfig This converts the following to Kconfig: CONFIG_SRIO1 CONFIG_SRIO2 CONFIG_SRIO_PCIE_BOOT_MASTER CONFIG_SYS_SRIO Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 12 ------------ arch/powerpc/Kconfig | 15 +++++++++++++++ configs/MPC8548CDS_36BIT_defconfig | 2 ++ configs/MPC8548CDS_defconfig | 2 ++ configs/MPC8548CDS_legacy_defconfig | 2 ++ configs/P2041RDB_NAND_defconfig | 4 ++++ configs/P2041RDB_SDCARD_defconfig | 4 ++++ configs/P2041RDB_SPIFLASH_defconfig | 4 ++++ configs/P2041RDB_defconfig | 4 ++++ configs/T2080QDS_NAND_defconfig | 4 ++++ configs/T2080QDS_SDCARD_defconfig | 4 ++++ configs/T2080QDS_SECURE_BOOT_defconfig | 4 ++++ configs/T2080QDS_SPIFLASH_defconfig | 4 ++++ configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 4 ++++ configs/T2080QDS_defconfig | 4 ++++ include/configs/MPC8548CDS.h | 3 --- include/configs/P2041RDB.h | 5 ----- include/configs/T102xRDB.h | 2 -- include/configs/T208xQDS.h | 6 ------ include/configs/T208xRDB.h | 1 - 20 files changed, 61 insertions(+), 29 deletions(-) (limited to 'include') diff --git a/README b/README index b095937121b..bb35a895b75 100644 --- a/README +++ b/README @@ -1686,18 +1686,6 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_OR_TIMING_SDRAM: SDRAM timing -- CONFIG_SYS_SRIO: - Chip has SRIO or not - -- CONFIG_SRIO1: - Board has SRIO 1 port available - -- CONFIG_SRIO2: - Board has SRIO 2 port available - -- CONFIG_SRIO_PCIE_BOOT_MASTER - Board can support master function for Boot from SRIO and PCIE - - CONFIG_SYS_SRIOn_MEM_VIRT: Virtual Address of SRIO port 'n' memory region diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index c355a954537..cf93a7b1dad 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -44,6 +44,21 @@ config SYS_INIT_RAM_LOCK bool "Lock some portion of L1 for initial ram stack" depends on MPC83xx || MPC85xx +config SYS_SRIO + bool "Serial RapidIO support" + +config SRIO1 + bool "Board has SRIO 1 port available" + depends on SYS_SRIO + +config SRIO2 + bool "Board has SRIO 2 port available" + depends on SYS_SRIO + +config SRIO_PCIE_BOOT_MASTER + bool "Board can support master function for Boot from SRIO and PCIE" + depends on SYS_SRIO + source "arch/powerpc/cpu/mpc83xx/Kconfig" source "arch/powerpc/cpu/mpc85xx/Kconfig" source "arch/powerpc/cpu/mpc8xx/Kconfig" diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 85b055a93ff..86a67d7b21f 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 0d21b893d8b..2ac4f266850 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index b01919ec675..faabd7bc045 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 0eec5089332..3d24b1a78c1 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -6,6 +6,10 @@ CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index f9f4c31ddb6..cec55a1412b 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -6,6 +6,10 @@ CONFIG_ENV_OFFSET=0xCF400 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 6a974370088..5fcf1546423 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -7,6 +7,10 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 1725a8a5a9c..ce198e28cb8 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -7,6 +7,10 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index dd7473ef7fd..637842cda21 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -11,6 +11,10 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 364aab58477..35ab9931e71 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -12,6 +12,10 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index c6710a0413c..93b02a5e990 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -4,6 +4,10 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index a705542eea7..7d25bbbb0ba 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -14,6 +14,10 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index d6d6ec0fbf0..2846f63d47f 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -5,6 +5,10 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_ENV_ADDR=0xFFE20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 802213de2b9..a7dc88c0bf9 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -6,6 +6,10 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 6a51149a949..eb75f8b37d5 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -13,9 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ - #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #ifndef __ASSEMBLY__ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index d7e06d23ec4..be8d09f6dd7 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -32,11 +32,6 @@ #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER - #ifndef __ASSEMBLY__ #include #endif diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 616387f4876..f9f9318448b 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -49,8 +49,6 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -/* PCIe Boot - Master */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 8f56de40ce8..acaad1bfc82 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -14,11 +14,6 @@ #include #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#endif /* High Level Configuration Options */ @@ -52,7 +47,6 @@ #endif /* CONFIG_RAMBOOT_PBL */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index e9db4a224f9..7315afa39f8 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -47,7 +47,6 @@ #endif /* CONFIG_RAMBOOT_PBL */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -- cgit v1.3.1 From a322afc9f9b69dd52a9bc72937cd5adc18ea55c7 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:40 -0500 Subject: global: Move remaining CONFIG_*SRIO_* to CFG_* The rest of the unmigrated CONFIG symbols in the SRIO namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/powerpc/cpu/mpc8xxx/law.c | 20 +++++----- arch/powerpc/cpu/mpc8xxx/srio.c | 72 +++++++++++++++++----------------- board/freescale/common/p_corenet/tlb.c | 8 ++-- board/freescale/t208xqds/tlb.c | 8 ++-- board/freescale/t208xrdb/tlb.c | 8 ++-- include/configs/MPC8548CDS.h | 8 ++-- include/configs/P2041RDB.h | 46 +++++++++++----------- include/configs/T102xRDB.h | 38 +++++++++--------- include/configs/T208xQDS.h | 42 ++++++++++---------- include/configs/T208xRDB.h | 42 ++++++++++---------- 10 files changed, 146 insertions(+), 146 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index dd274166c01..35409dc8824 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -309,42 +309,42 @@ void init_laws(void) */ switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) { case 0x0: /* boot from PCIE1 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1); break; case 0x1: /* boot from PCIE2 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2); break; case 0x2: /* boot from PCIE3 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_3); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_3); break; case 0x8: /* boot from SRIO1 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1); break; case 0x9: /* boot from SRIO2 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2); break; diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index c815d19384b..dc1bc0db423 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -240,8 +240,8 @@ void srio_init(void) devdisr = &gur->devdisr; #endif if (is_serdes_configured(SRIO1)) { - set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS, - law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), + set_next_law(CFG_SYS_SRIO1_MEM_PHYS, + law_size_bits(CFG_SYS_SRIO1_MEM_SIZE), LAW_TRGT_IF_RIO_1); srio1_used = 1; #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 @@ -256,8 +256,8 @@ void srio_init(void) #ifdef CONFIG_SRIO2 if (is_serdes_configured(SRIO2)) { - set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS, - law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE), + set_next_law(CFG_SYS_SRIO2_MEM_PHYS, + law_size_bits(CFG_SYS_SRIO2_MEM_SIZE), LAW_TRGT_IF_RIO_2); srio2_used = 1; #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 @@ -301,44 +301,44 @@ void srio_boot_master(int port) /* configure inbound window for slave's u-boot image */ debug("SRIOBOOT - MASTER: Inbound window for slave's image; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, - CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, + CFG_SRIO_PCIE_BOOT_IMAGE_SIZE); out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); + | atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE)); /* configure inbound window for slave's u-boot image */ debug("SRIOBOOT - MASTER: Inbound window for slave's image; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, - CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, + CFG_SRIO_PCIE_BOOT_IMAGE_SIZE); out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); + | atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE)); /* configure inbound window for slave's ucode and ENV */ debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, - (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, - CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); + (u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, + (u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, + CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar, - CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12); + CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar, - CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12); + CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)); + | atmu_size_mask(CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)); } void srio_boot_master_release_slave(int port) @@ -368,11 +368,11 @@ void srio_boot_master_release_slave(int port) if (port - 1) out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowbar, - CONFIG_SYS_SRIO2_MEM_PHYS >> 12); + CFG_SYS_SRIO2_MEM_PHYS >> 12); else out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowbar, - CONFIG_SYS_SRIO1_MEM_PHYS >> 12); + CFG_SYS_SRIO1_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowar, SRIO_OB_ATMU_AR_MAINT @@ -390,12 +390,12 @@ void srio_boot_master_release_slave(int port) if (port - 1) out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowbar, - (CONFIG_SYS_SRIO2_MEM_PHYS + (CFG_SYS_SRIO2_MEM_PHYS + SRIO_MAINT_WIN_SIZE) >> 12); else out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowbar, - (CONFIG_SYS_SRIO1_MEM_PHYS + (CFG_SYS_SRIO1_MEM_PHYS + SRIO_MAINT_WIN_SIZE) >> 12); out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowar, @@ -407,10 +407,10 @@ void srio_boot_master_release_slave(int port) * by the maint-outbound window */ if (port - 1) { - out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET, SRIO_LCSBA1CSR); - while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + while (in_be32((void *)CFG_SYS_SRIO2_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET) != SRIO_LCSBA1CSR) ; @@ -418,15 +418,15 @@ void srio_boot_master_release_slave(int port) * And then set the BRR register * to release slave core */ - out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT + SRIO_MAINT_WIN_SIZE - + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, - CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); + + CFG_SRIO_PCIE_BOOT_BRR_OFFSET, + CFG_SRIO_PCIE_BOOT_RELEASE_MASK); } else { - out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET, SRIO_LCSBA1CSR); - while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + while (in_be32((void *)CFG_SYS_SRIO1_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET) != SRIO_LCSBA1CSR) ; @@ -434,10 +434,10 @@ void srio_boot_master_release_slave(int port) * And then set the BRR register * to release slave core */ - out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT + SRIO_MAINT_WIN_SIZE - + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, - CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); + + CFG_SRIO_PCIE_BOOT_BRR_OFFSET, + CFG_SRIO_PCIE_BOOT_RELEASE_MASK); } debug("SRIOBOOT - MASTER: " "Release slave successfully! Now the slave should start up!\n"); diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 4cdef89bf0e..7302b760662 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -69,8 +69,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the * space is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #else @@ -150,8 +150,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for * fetching ucode and ENV from master */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 17, BOOKE_PAGESZ_1M, 1), #endif diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index 9160674b94f..f2448e86c0d 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -43,8 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the * space is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #else @@ -136,8 +136,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for * fetching ucode and ENV from master */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 18, BOOKE_PAGESZ_1M, 1), #endif diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index 69e58e7e973..45c27c08120 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -43,8 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the * space is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #else @@ -136,8 +136,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for * fetching ucode and ENV from master */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 18, BOOKE_PAGESZ_1M, 1), #endif diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index eb75f8b37d5..25b4fe0c7d4 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -282,13 +282,13 @@ /* * RapidIO MMU */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 +#define CFG_SYS_SRIO1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull +#define CFG_SYS_SRIO1_MEM_PHYS 0xc40000000ull #else -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xc0000000 #endif -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ #if defined(CONFIG_TSEC_ENET) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index be8d09f6dd7..c3ef2163335 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -18,9 +18,9 @@ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif @@ -173,49 +173,49 @@ /* * RapidIO */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull #else -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 +#define CFG_SYS_SRIO2_MEM_PHYS 0xb0000000 #endif -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ /* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* * SRIO_PCIE_BOOT - SLAVE */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) #endif /* diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index f9f9318448b..b567b63980e 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -53,40 +53,40 @@ * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull #else -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 #endif /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull #else -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 #endif -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ /* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* PCIe Boot - Slave */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) /* Set 1M boot space for PCIe boot */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index acaad1bfc82..798822e5031 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -49,9 +49,9 @@ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif @@ -295,39 +295,39 @@ /* * RapidIO */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ /* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* * SRIO_PCIE_BOOT - SLAVE */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) #endif /* diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 7315afa39f8..ea366b671c0 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -49,9 +49,9 @@ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif @@ -254,39 +254,39 @@ /* * RapidIO */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ /* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* * SRIO_PCIE_BOOT - SLAVE */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) #endif /* -- cgit v1.3.1 From 65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:41 -0500 Subject: global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- .checkpatch.conf | 2 +- Kconfig | 6 +- Makefile | 16 +- README | 66 ++-- arch/arm/cpu/arm1176/start.S | 2 +- arch/arm/cpu/arm926ejs/start.S | 2 +- arch/arm/cpu/armv7/arch_timer.c | 6 +- arch/arm/cpu/armv7/ls102xa/cpu.c | 4 +- arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 4 +- arch/arm/cpu/armv7/stv0991/timer.c | 4 +- arch/arm/cpu/armv7m/systick-timer.c | 8 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 54 +-- arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 | 4 +- arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 +- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 +- arch/arm/cpu/armv8/sec_firmware.c | 4 +- arch/arm/include/asm/arch-fsl-layerscape/config.h | 36 +- .../arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 4 +- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 80 ++-- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 10 +- arch/arm/include/asm/arch-lpc32xx/config.h | 4 +- arch/arm/include/asm/arch-ls102xa/config.h | 22 +- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 18 +- .../include/asm/arch-ls102xa/ls102xa_stream_id.h | 4 +- arch/arm/include/asm/arch-mx31/imx-regs.h | 4 +- arch/arm/include/asm/arch-stv0991/stv0991_gpt.h | 2 +- arch/arm/include/asm/arch-sunxi/i2c.h | 2 +- arch/arm/include/asm/global_data.h | 2 +- arch/arm/lib/bdinfo.c | 2 +- arch/arm/lib/cache-pl310.c | 2 +- arch/arm/lib/cache.c | 2 +- arch/arm/lib/vectors.S | 4 +- arch/arm/mach-at91/arm920t/clock.c | 6 +- arch/arm/mach-at91/arm920t/cpu.c | 6 +- arch/arm/mach-at91/arm920t/lowlevel_init.S | 18 +- arch/arm/mach-at91/arm920t/timer.c | 4 +- arch/arm/mach-at91/arm926ejs/clock.c | 6 +- arch/arm/mach-at91/arm926ejs/cpu.c | 6 +- arch/arm/mach-at91/arm926ejs/lowlevel_init.S | 54 +-- arch/arm/mach-at91/armv7/clock.c | 8 +- arch/arm/mach-at91/armv7/cpu.c | 6 +- arch/arm/mach-at91/include/mach/at91sam9260.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9261.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9263.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9g45.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9rl.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 +- arch/arm/mach-at91/include/mach/sam9x60.h | 2 +- arch/arm/mach-at91/include/mach/sama5d2.h | 2 +- arch/arm/mach-at91/include/mach/sama5d3.h | 2 +- arch/arm/mach-at91/include/mach/sama5d4.h | 2 +- arch/arm/mach-at91/spl_at91.c | 12 +- arch/arm/mach-at91/spl_atmel.c | 2 +- arch/arm/mach-davinci/cpu.c | 2 +- arch/arm/mach-davinci/da850_lowlevel.c | 24 +- arch/arm/mach-davinci/timer.c | 4 +- arch/arm/mach-exynos/spl_boot.c | 2 +- arch/arm/mach-imx/image-container.c | 8 +- arch/arm/mach-imx/mx5/lowlevel_init.S | 10 +- arch/arm/mach-k3/config_secure.mk | 2 +- arch/arm/mach-keystone/cmd_mon.c | 2 +- arch/arm/mach-keystone/include/mach/hardware.h | 2 +- arch/arm/mach-kirkwood/include/mach/config.h | 4 +- arch/arm/mach-kirkwood/include/mach/kw88f6192.h | 2 +- arch/arm/mach-kirkwood/include/mach/kw88f6281.h | 2 +- arch/arm/mach-mvebu/cpu.c | 4 +- arch/arm/mach-mvebu/include/mach/soc.h | 10 +- arch/arm/mach-mvebu/lowlevel.S | 4 +- arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c | 2 +- arch/arm/mach-omap2/config_secure.mk | 2 +- arch/arm/mach-omap2/mem-common.c | 12 +- arch/arm/mach-omap2/timer.c | 2 +- arch/arm/mach-orion5x/include/mach/mv88f5182.h | 2 +- arch/arm/mach-orion5x/timer.c | 6 +- arch/arm/mach-rmobile/include/mach/r8a7790.h | 2 +- arch/arm/mach-rmobile/include/mach/r8a7791.h | 2 +- arch/arm/mach-rmobile/include/mach/r8a7792.h | 2 +- arch/arm/mach-rmobile/include/mach/r8a7793.h | 2 +- arch/arm/mach-rmobile/include/mach/r8a7794.h | 2 +- arch/arm/mach-rmobile/timer.c | 8 +- arch/arm/mach-socfpga/misc.c | 2 +- arch/arm/mach-socfpga/misc_arria10.c | 4 +- arch/arm/mach-socfpga/misc_gen5.c | 2 +- arch/arm/mach-socfpga/spl_a10.c | 2 +- arch/arm/mach-socfpga/timer.c | 2 +- arch/arm/mach-u8500/cache.c | 2 +- arch/arm/mach-uniphier/arm32/timer.c | 2 +- arch/arm/mach-versatile/timer.c | 8 +- arch/m68k/cpu/mcf523x/cpu.c | 2 +- arch/m68k/cpu/mcf523x/cpu_init.c | 38 +- arch/m68k/cpu/mcf523x/speed.c | 2 +- arch/m68k/cpu/mcf523x/start.S | 6 +- arch/m68k/cpu/mcf52x2/cpu.c | 10 +- arch/m68k/cpu/mcf52x2/cpu_init.c | 110 +++--- arch/m68k/cpu/mcf52x2/speed.c | 14 +- arch/m68k/cpu/mcf52x2/start.S | 48 +-- arch/m68k/cpu/mcf530x/cpu.c | 2 +- arch/m68k/cpu/mcf530x/cpu_init.c | 48 +-- arch/m68k/cpu/mcf530x/speed.c | 4 +- arch/m68k/cpu/mcf530x/start.S | 10 +- arch/m68k/cpu/mcf532x/cpu.c | 2 +- arch/m68k/cpu/mcf532x/cpu_init.c | 86 ++-- arch/m68k/cpu/mcf532x/speed.c | 2 +- arch/m68k/cpu/mcf532x/start.S | 6 +- arch/m68k/cpu/mcf5445x/cpu_init.c | 38 +- arch/m68k/cpu/mcf5445x/start.S | 46 +-- arch/m68k/include/asm/cache.h | 24 +- arch/m68k/include/asm/immap.h | 32 +- arch/m68k/include/asm/immap_520x.h | 52 +-- arch/m68k/include/asm/immap_5235.h | 72 ++-- arch/m68k/include/asm/immap_5249.h | 14 +- arch/m68k/include/asm/immap_5253.h | 26 +- arch/m68k/include/asm/immap_5271.h | 72 ++-- arch/m68k/include/asm/immap_5272.h | 36 +- arch/m68k/include/asm/immap_5275.h | 76 ++-- arch/m68k/include/asm/immap_5282.h | 72 ++-- arch/m68k/include/asm/immap_5301x.h | 80 ++-- arch/m68k/include/asm/immap_5307.h | 18 +- arch/m68k/include/asm/m5249.h | 16 +- arch/m68k/include/asm/m5271.h | 12 +- arch/m68k/include/asm/m5282.h | 388 +++++++++--------- arch/m68k/lib/bdinfo.c | 4 +- arch/m68k/lib/cache.c | 24 +- arch/mips/mach-mtmips/mt7621/spl/start.S | 2 +- arch/powerpc/cpu/mpc83xx/cpu_init.c | 46 +-- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 14 +- arch/powerpc/cpu/mpc83xx/spl_minimal.c | 8 +- arch/powerpc/cpu/mpc83xx/start.S | 48 +-- arch/powerpc/cpu/mpc83xx/sysio/sysio.h | 8 +- arch/powerpc/cpu/mpc85xx/b4860_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 +- arch/powerpc/cpu/mpc85xx/cpu.c | 18 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 52 +-- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 22 +- arch/powerpc/cpu/mpc85xx/fdt.c | 32 +- arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 2 +- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 14 +- arch/powerpc/cpu/mpc85xx/p2041_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p3041_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p5040_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/release.S | 4 +- arch/powerpc/cpu/mpc85xx/speed.c | 42 +- arch/powerpc/cpu/mpc85xx/spl_minimal.c | 4 +- arch/powerpc/cpu/mpc85xx/start.S | 130 +++--- arch/powerpc/cpu/mpc85xx/t1024_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/t1040_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/t2080_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/tlb.c | 8 +- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 4 +- arch/powerpc/cpu/mpc8xx/start.S | 4 +- arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 8 +- arch/powerpc/cpu/mpc8xxx/pamu_table.c | 8 +- arch/powerpc/include/asm/config_mpc85xx.h | 42 +- arch/powerpc/include/asm/fsl_lbc.h | 2 +- arch/powerpc/include/asm/fsl_liodn.h | 18 +- arch/powerpc/include/asm/fsl_secure_boot.h | 20 +- arch/powerpc/include/asm/immap_83xx.h | 10 +- arch/powerpc/include/asm/immap_85xx.h | 44 +-- arch/powerpc/lib/spl.c | 2 +- arch/sh/include/asm/config.h | 4 +- arch/x86/lib/physmem.c | 2 +- arch/xtensa/include/asm/addrspace.h | 4 +- board/BuS/eb_cpu5282/eb_cpu5282.c | 6 +- board/LaCie/net2big_v2/net2big_v2.c | 12 +- board/Synology/common/legacy.c | 4 +- board/armltd/integrator/timer.c | 14 +- board/armltd/vexpress64/vexpress64.c | 4 +- board/cadence/xtfpga/xtfpga.c | 10 +- board/cavium/thunderx/atf.c | 2 +- board/cavium/thunderx/thunderx.c | 4 +- board/cobra5272/flash.c | 10 +- board/cortina/presidio-asic/lowlevel_init.S | 2 +- board/cortina/presidio-asic/presidio.c | 2 +- board/davinci/da8xxevm/da850evm.c | 16 +- board/egnite/ethernut5/ethernut5.c | 2 +- board/emulation/qemu-ppce500/qemu-ppce500.c | 6 +- board/esd/meesc/meesc.c | 2 +- board/freescale/common/fsl_chain_of_trust.c | 2 +- board/freescale/common/fsl_validate.c | 14 +- board/freescale/common/p_corenet/law.c | 14 +- board/freescale/common/p_corenet/tlb.c | 48 +-- board/freescale/common/qixis.c | 10 +- board/freescale/common/qixis.h | 6 +- board/freescale/ls1012aqds/ls1012aqds.c | 4 +- board/freescale/ls1021aqds/ls1021aqds.c | 2 +- board/freescale/ls1021atwr/ls1021atwr.c | 12 +- board/freescale/ls1043aqds/ls1043aqds.c | 48 +-- board/freescale/ls1043ardb/cpld.c | 4 +- board/freescale/ls1043ardb/ls1043ardb.c | 32 +- board/freescale/ls1046aqds/ls1046aqds.c | 48 +-- board/freescale/ls1046ardb/cpld.c | 4 +- board/freescale/ls1088a/ls1088a.c | 30 +- board/freescale/ls2080aqds/README | 4 +- board/freescale/ls2080aqds/ls2080aqds.c | 2 +- board/freescale/lx2160a/lx2160a.c | 6 +- board/freescale/m5249evb/m5249evb.c | 6 +- board/freescale/m5253demo/flash.c | 18 +- board/freescale/m5253demo/m5253demo.c | 4 +- board/freescale/m53017evb/README | 6 +- board/freescale/m5329evb/nand.c | 2 +- board/freescale/m5373evb/README | 6 +- board/freescale/m5373evb/nand.c | 2 +- board/freescale/mpc837xerdb/mpc837xerdb.c | 28 +- board/freescale/mpc8548cds/law.c | 2 +- board/freescale/mpc8548cds/mpc8548cds.c | 12 +- board/freescale/mpc8548cds/tlb.c | 16 +- board/freescale/mx53loco/mx53loco.c | 4 +- board/freescale/p1010rdb/law.c | 4 +- board/freescale/p1010rdb/p1010rdb.c | 14 +- board/freescale/p1010rdb/spl.c | 2 +- board/freescale/p1010rdb/tlb.c | 30 +- board/freescale/p1_p2_rdb_pc/ddr.c | 56 +-- board/freescale/p1_p2_rdb_pc/law.c | 6 +- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 22 +- board/freescale/p1_p2_rdb_pc/tlb.c | 38 +- board/freescale/p2041rdb/eth.c | 24 +- board/freescale/p2041rdb/p2041rdb.c | 4 +- board/freescale/t102xrdb/cpld.c | 4 +- board/freescale/t102xrdb/ddr.c | 2 +- board/freescale/t102xrdb/law.c | 18 +- board/freescale/t102xrdb/t102xrdb.c | 6 +- board/freescale/t102xrdb/tlb.c | 54 +-- board/freescale/t104xrdb/cpld.c | 6 +- board/freescale/t104xrdb/ddr.c | 2 +- board/freescale/t104xrdb/eth.c | 18 +- board/freescale/t104xrdb/law.c | 18 +- board/freescale/t104xrdb/spl.c | 2 +- board/freescale/t104xrdb/t104xrdb.c | 6 +- board/freescale/t104xrdb/tlb.c | 58 +-- board/freescale/t208xqds/law.c | 14 +- board/freescale/t208xqds/t208xqds.c | 4 +- board/freescale/t208xqds/tlb.c | 46 +-- board/freescale/t208xrdb/cpld.c | 4 +- board/freescale/t208xrdb/law.c | 18 +- board/freescale/t208xrdb/t208xrdb.c | 4 +- board/freescale/t208xrdb/tlb.c | 50 +-- board/freescale/t4rdb/cpld.c | 6 +- board/freescale/t4rdb/law.c | 18 +- board/freescale/t4rdb/t4240rdb.c | 4 +- board/freescale/t4rdb/tlb.c | 50 +-- board/gdsys/mpc8308/sdram.c | 24 +- board/isee/igep00x0/igep00x0.c | 2 +- board/keymile/common/qrio.c | 36 +- board/keymile/km83xx/km83xx.c | 30 +- board/keymile/kmcent2/kmcent2.c | 6 +- board/keymile/kmcent2/law.c | 10 +- board/keymile/kmcent2/tlb.c | 40 +- board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 2 +- board/nokia/rx51/rx51.c | 2 +- board/samsung/goni/onenand.c | 2 +- board/samsung/universal_c210/onenand.c | 2 +- board/siemens/smartweb/smartweb.c | 2 +- board/siemens/taurus/taurus.c | 2 +- board/socrates/law.c | 10 +- board/socrates/sdram.c | 22 +- board/socrates/socrates.c | 10 +- board/socrates/tlb.c | 22 +- board/sysam/amcore/amcore.c | 2 +- board/ti/ks2_evm/board.c | 8 +- board/ti/omap5_uevm/evm.c | 2 +- board/xes/common/fsl_8xxx_misc.c | 4 +- boot/Kconfig | 2 +- boot/image-board.c | 4 +- cmd/date.c | 4 +- cmd/i2c.c | 16 +- common/board_f.c | 4 +- common/board_r.c | 8 +- common/spl/Kconfig.nxp | 4 +- common/spl/spl.c | 6 +- common/spl/spl_fit.c | 2 +- common/spl/spl_nor.c | 2 +- common/spl/spl_spi.c | 8 +- common/spl/spl_ubi.c | 2 +- common/spl/spl_xip.c | 2 +- doc/README.atmel_mci | 4 +- doc/README.cfi | 4 +- doc/README.davinci | 2 +- doc/README.generic_usb_ohci | 2 +- doc/README.mpc85xx | 16 +- doc/README.nand | 2 +- doc/README.serial_multi | 2 +- doc/arch/m68k.rst | 18 +- doc/develop/driver-model/migration.rst | 2 +- doc/device-tree-bindings/video/exynos-dp.txt | 4 +- doc/device-tree-bindings/video/exynos-fb.txt | 10 +- doc/imx/common/imx5.txt | 2 +- doc/usage/environment.rst | 6 +- drivers/bootcount/Kconfig | 2 +- drivers/bootcount/bootcount_i2c.c | 4 +- drivers/clk/at91/compat.c | 2 +- drivers/core/Kconfig | 6 +- drivers/ddr/fsl/main.c | 4 +- drivers/fpga/ACEX1K.c | 6 +- drivers/fpga/cyclon2.c | 6 +- drivers/fpga/spartan2.c | 16 +- drivers/fpga/spartan3.c | 16 +- drivers/fpga/virtex2.c | 28 +- drivers/fpga/zynqpl.c | 14 +- drivers/gpio/pca953x.c | 10 +- drivers/gpio/tca642x.c | 6 +- drivers/i2c/davinci_i2c.c | 2 +- drivers/i2c/fsl_i2c.c | 2 +- drivers/i2c/i2c_core.c | 6 +- drivers/i2c/kona_i2c.c | 2 +- drivers/i2c/mvtwsi.c | 6 +- drivers/i2c/mxc_i2c.c | 4 +- drivers/misc/fsl_ifc.c | 438 ++++++++++----------- drivers/misc/fsl_portals.c | 28 +- drivers/misc/fsl_sec_mon.c | 6 +- drivers/mmc/fsl_esdhc_spl.c | 18 +- drivers/mmc/gen_atmel_mci.c | 8 +- drivers/mmc/sh_sdhi.c | 2 +- drivers/mtd/cfi_flash.c | 32 +- drivers/mtd/nand/raw/fsl_ifc_nand.c | 4 +- drivers/mtd/nand/raw/fsl_ifc_spl.c | 8 +- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 6 +- drivers/mtd/onenand/onenand_spl.c | 6 +- drivers/mtd/onenand/onenand_uboot.c | 2 +- drivers/mtd/spi/fsl_espi_spl.c | 12 +- drivers/mtd/stm32_flash.c | 2 +- drivers/net/fm/eth.c | 2 +- drivers/net/fm/fm.c | 4 +- drivers/net/fm/init.c | 4 +- drivers/net/fsl-mc/dpio/qbman_sys.h | 4 +- drivers/net/fsl-mc/mc.c | 48 +-- drivers/net/fsl_mcdmafec.c | 26 +- drivers/net/mcffec.c | 8 +- drivers/net/qe/uec.h | 14 +- drivers/net/tsec.c | 4 +- drivers/net/vsc7385.c | 12 +- drivers/power/power_dialog.c | 2 +- drivers/qe/uec.h | 14 +- drivers/qe/uec_phy.c | 10 +- drivers/rtc/ds1307.c | 8 +- drivers/rtc/ds1337.c | 4 +- drivers/rtc/ds1374.c | 16 +- drivers/rtc/ds3231.c | 4 +- drivers/rtc/m41t62.c | 10 +- drivers/rtc/max6900.c | 8 +- drivers/rtc/pcf8563.c | 4 +- drivers/rtc/pt7c4338.c | 4 +- drivers/rtc/rs5c372.c | 12 +- drivers/rtc/rx8010sj.c | 12 +- drivers/rtc/x1205.c | 4 +- drivers/serial/serial-uclass.c | 2 +- drivers/serial/serial.c | 4 +- drivers/spi/davinci_spi.c | 4 +- drivers/spi/kirkwood_spi.c | 4 +- drivers/sysreset/sysreset_xtfpga.c | 4 +- drivers/timer/arm_global_timer.c | 2 +- drivers/timer/imx-gpt-timer.c | 10 +- drivers/timer/orion-timer.c | 4 +- drivers/timer/stm32_timer.c | 4 +- drivers/usb/host/ohci-hcd.c | 2 +- drivers/video/imx/ipu_common.c | 6 +- env/Kconfig | 2 +- env/embedded.c | 2 +- include/config_fallbacks.h | 4 +- include/configs/M5208EVBE.h | 42 +- include/configs/M5235EVB.h | 52 +-- include/configs/M5249EVB.h | 66 ++-- include/configs/M5253DEMO.h | 86 ++-- include/configs/M5272C3.h | 48 +-- include/configs/M5275EVB.h | 48 +-- include/configs/M5282EVB.h | 68 ++-- include/configs/M53017EVB.h | 54 +-- include/configs/M5329EVB.h | 56 +-- include/configs/M5373EVB.h | 56 +-- include/configs/MCR3000.h | 8 +- include/configs/MPC837XERDB.h | 60 +-- include/configs/MPC8548CDS.h | 58 +-- include/configs/P1010RDB.h | 146 +++---- include/configs/P2041RDB.h | 132 +++---- include/configs/SBx81LIFKW.h | 4 +- include/configs/SBx81LIFXCAT.h | 4 +- include/configs/T102xRDB.h | 209 +++++----- include/configs/T104xRDB.h | 228 +++++------ include/configs/T208xQDS.h | 226 +++++------ include/configs/T208xRDB.h | 192 ++++----- include/configs/T4240RDB.h | 206 +++++----- include/configs/am335x_evm.h | 4 +- include/configs/am3517_evm.h | 2 +- include/configs/am43xx_evm.h | 4 +- include/configs/am57xx_evm.h | 6 +- include/configs/amcore.h | 44 +-- include/configs/ap121.h | 4 +- include/configs/ap143.h | 4 +- include/configs/ap152.h | 4 +- include/configs/apalis_imx6.h | 4 +- include/configs/arbel.h | 6 +- include/configs/aristainetos2.h | 6 +- include/configs/aspeed-common.h | 8 +- include/configs/astro_mcf5373l.h | 68 ++-- include/configs/at91-sama5_common.h | 4 +- include/configs/at91sam9260ek.h | 12 +- include/configs/at91sam9261ek.h | 10 +- include/configs/at91sam9263ek.h | 56 +-- include/configs/at91sam9m10g45ek.h | 12 +- include/configs/at91sam9n12ek.h | 12 +- include/configs/at91sam9rlek.h | 8 +- include/configs/at91sam9x5ek.h | 12 +- include/configs/ax25-ae350.h | 8 +- include/configs/axs10x.h | 4 +- include/configs/bcm7260.h | 2 +- include/configs/bcm7445.h | 2 +- include/configs/bcm963138.h | 2 +- include/configs/bcmstb.h | 4 +- include/configs/bk4r1.h | 4 +- include/configs/blanche.h | 8 +- include/configs/bmips_bcm3380.h | 2 +- include/configs/bmips_bcm6318.h | 2 +- include/configs/bmips_bcm63268.h | 2 +- include/configs/bmips_bcm6328.h | 2 +- include/configs/bmips_bcm6338.h | 4 +- include/configs/bmips_bcm6348.h | 4 +- include/configs/bmips_bcm6358.h | 4 +- include/configs/bmips_bcm6362.h | 2 +- include/configs/bmips_bcm6368.h | 4 +- include/configs/bmips_bcm6838.h | 2 +- include/configs/bmips_common.h | 2 +- include/configs/boston.h | 2 +- include/configs/brppt2.h | 6 +- include/configs/bur_am335x_common.h | 2 +- include/configs/cgtqmx8.h | 2 +- include/configs/ci20.h | 2 +- include/configs/cl-som-imx7.h | 8 +- include/configs/cm_fx6.h | 6 +- include/configs/cm_t43.h | 4 +- include/configs/cobra5272.h | 48 +-- include/configs/colibri-imx6ull.h | 4 +- include/configs/colibri_imx6.h | 4 +- include/configs/colibri_imx7.h | 4 +- include/configs/colibri_vf.h | 4 +- include/configs/corvus.h | 12 +- include/configs/da850evm.h | 36 +- include/configs/dart_6ul.h | 4 +- include/configs/devkit3250.h | 4 +- include/configs/dh_imx6.h | 4 +- include/configs/display5.h | 10 +- include/configs/dra7xx_evm.h | 10 +- include/configs/draak.h | 4 +- include/configs/dragonboard845c.h | 2 +- include/configs/eb_cpu5282.h | 86 ++-- include/configs/ebisu.h | 4 +- include/configs/edison.h | 2 +- include/configs/el6x_common.h | 4 +- include/configs/embestmx6boards.h | 4 +- include/configs/etamin.h | 2 +- include/configs/ethernut5.h | 16 +- include/configs/evb_ast2500.h | 2 +- include/configs/evb_ast2600.h | 2 +- include/configs/exynos5-dt-common.h | 2 +- include/configs/exynos78x0-common.h | 2 +- include/configs/gardena-smart-gateway-at91sam.h | 12 +- include/configs/gardena-smart-gateway-mt7688.h | 8 +- include/configs/gazerbeam.h | 14 +- include/configs/ge_b1x5v2.h | 4 +- include/configs/ge_bx50v3.h | 6 +- include/configs/gw_ventana.h | 4 +- include/configs/highbank.h | 2 +- include/configs/hikey.h | 2 +- include/configs/hikey960.h | 2 +- include/configs/hsdk-4xd.h | 4 +- include/configs/hsdk.h | 4 +- include/configs/imx27lite-common.h | 2 +- include/configs/imx6-engicam.h | 4 +- include/configs/imx6_logic.h | 4 +- include/configs/imx6dl-mamoj.h | 4 +- include/configs/imx6q-bosch-acc.h | 4 +- include/configs/imx6ulz_smm_m2.h | 4 +- include/configs/imx7-cm.h | 4 +- include/configs/imx8mm-cl-iot-gate.h | 6 +- include/configs/imx8mm_beacon.h | 6 +- include/configs/imx8mm_data_modul_edm_sbc.h | 4 +- include/configs/imx8mm_evk.h | 8 +- include/configs/imx8mm_icore_mx8mm.h | 6 +- include/configs/imx8mm_venice.h | 6 +- include/configs/imx8mn_beacon.h | 6 +- include/configs/imx8mn_bsh_smm_s2_common.h | 6 +- include/configs/imx8mn_evk.h | 6 +- include/configs/imx8mn_var_som.h | 6 +- include/configs/imx8mn_venice.h | 6 +- include/configs/imx8mp_dhcom_pdk2.h | 4 +- include/configs/imx8mp_evk.h | 6 +- include/configs/imx8mp_icore_mx8mp.h | 6 +- include/configs/imx8mp_rsb3720.h | 6 +- include/configs/imx8mp_venice.h | 6 +- include/configs/imx8mq_cm.h | 4 +- include/configs/imx8mq_evk.h | 4 +- include/configs/imx8mq_phanbell.h | 4 +- include/configs/imx8qm_rom7720.h | 2 +- include/configs/imx8ulp_evk.h | 6 +- include/configs/imx93_evk.h | 6 +- include/configs/imxrt1020-evk.h | 2 +- include/configs/imxrt1050-evk.h | 2 +- include/configs/imxrt1170-evk.h | 2 +- include/configs/integrator-common.h | 4 +- include/configs/integratorap.h | 4 +- include/configs/integratorcp.h | 2 +- include/configs/j721e_evm.h | 6 +- include/configs/j721s2_evm.h | 4 +- include/configs/km/keymile-common.h | 2 +- include/configs/km/km-mpc832x.h | 32 +- include/configs/km/km-mpc8360.h | 32 +- include/configs/km/km-mpc83xx.h | 20 +- include/configs/km/pg-wcom-ls102xa.h | 86 ++-- include/configs/kmcent2.h | 204 +++++----- include/configs/kmcoge5ne.h | 6 +- include/configs/kmeter1.h | 2 +- include/configs/kontron-sl-mx6ul.h | 6 +- include/configs/kontron-sl-mx8mm.h | 4 +- include/configs/kontron_pitx_imx8m.h | 4 +- include/configs/kontron_sl28.h | 8 +- include/configs/kp_imx53.h | 4 +- include/configs/kp_imx6q_tpc.h | 4 +- include/configs/lacie_kw.h | 2 +- include/configs/legoev3.h | 10 +- include/configs/librem5.h | 4 +- include/configs/linkit-smart-7688.h | 8 +- include/configs/liteboard.h | 4 +- include/configs/ls1012a_common.h | 6 +- include/configs/ls1012aqds.h | 4 +- include/configs/ls1021aiot.h | 10 +- include/configs/ls1021aqds.h | 174 ++++---- include/configs/ls1021atsn.h | 10 +- include/configs/ls1021atwr.h | 74 ++-- include/configs/ls1028a_common.h | 6 +- include/configs/ls1028aqds.h | 12 +- include/configs/ls1028ardb.h | 10 +- include/configs/ls1043a_common.h | 20 +- include/configs/ls1043aqds.h | 224 +++++------ include/configs/ls1043ardb.h | 146 +++---- include/configs/ls1046a_common.h | 8 +- include/configs/ls1046afrwy.h | 22 +- include/configs/ls1046aqds.h | 236 +++++------ include/configs/ls1046ardb.h | 56 +-- include/configs/ls1088a_common.h | 36 +- include/configs/ls1088aqds.h | 216 +++++----- include/configs/ls1088ardb.h | 80 ++-- include/configs/ls2080a_common.h | 36 +- include/configs/ls2080aqds.h | 158 ++++---- include/configs/ls2080ardb.h | 110 +++--- include/configs/lx2160a_common.h | 40 +- include/configs/lx2160aqds.h | 2 +- include/configs/lx2160ardb.h | 2 +- include/configs/lx2162aqds.h | 2 +- include/configs/m53menlo.h | 10 +- include/configs/malta.h | 6 +- include/configs/mccmon6.h | 14 +- include/configs/meerkat96.h | 4 +- include/configs/meesc.h | 8 +- include/configs/microblaze-generic.h | 4 +- include/configs/msc_sm2s_imx8mp.h | 6 +- include/configs/mt7620.h | 6 +- include/configs/mt7621.h | 6 +- include/configs/mt7622.h | 4 +- include/configs/mt7628.h | 8 +- include/configs/mt7629.h | 2 +- include/configs/mt7981.h | 4 +- include/configs/mt7986.h | 4 +- include/configs/mt8512.h | 2 +- include/configs/mv-common.h | 6 +- include/configs/mvebu_alleycat-5.h | 4 +- include/configs/mvebu_armada-37xx.h | 2 +- include/configs/mvebu_armada-8k.h | 4 +- include/configs/mx51evk.h | 10 +- include/configs/mx53cx9020.h | 4 +- include/configs/mx53loco.h | 6 +- include/configs/mx53ppd.h | 6 +- include/configs/mx6_common.h | 2 +- include/configs/mx6cuboxi.h | 4 +- include/configs/mx6memcal.h | 4 +- include/configs/mx6sabre_common.h | 4 +- include/configs/mx6sabreauto.h | 4 +- include/configs/mx6slevk.h | 4 +- include/configs/mx6sllevk.h | 4 +- include/configs/mx6sxsabreauto.h | 4 +- include/configs/mx6sxsabresd.h | 4 +- include/configs/mx6ul_14x14_evk.h | 4 +- include/configs/mx6ullevk.h | 4 +- include/configs/mx7dsabresd.h | 4 +- include/configs/mx7ulp_com.h | 6 +- include/configs/mx7ulp_evk.h | 6 +- include/configs/mxs.h | 6 +- include/configs/mys_6ulx.h | 4 +- include/configs/nitrogen6x.h | 4 +- include/configs/nokia_rx51.h | 10 +- include/configs/novena.h | 4 +- include/configs/npi_imx6ull.h | 4 +- include/configs/nsim.h | 4 +- include/configs/o4-imx6ull-nano.h | 4 +- include/configs/octeon_common.h | 4 +- include/configs/odroid.h | 2 +- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_igep00x0.h | 4 +- include/configs/omap3_logic.h | 4 +- include/configs/omap5_uevm.h | 4 +- include/configs/omapl138_lcdk.h | 32 +- include/configs/opos6uldev.h | 4 +- include/configs/p1_p2_bootsrc.h | 6 +- include/configs/p1_p2_rdb_pc.h | 164 ++++---- include/configs/pcl063.h | 4 +- include/configs/pcl063_ull.h | 4 +- include/configs/pcm052.h | 4 +- include/configs/pcm058.h | 4 +- include/configs/pg-wcom-expu1.h | 16 +- include/configs/pg-wcom-seli8.h | 16 +- include/configs/phycore_imx8mm.h | 6 +- include/configs/phycore_imx8mp.h | 6 +- include/configs/pic32mzdask.h | 6 +- include/configs/pico-imx6.h | 4 +- include/configs/pico-imx6ul.h | 4 +- include/configs/pico-imx7d.h | 4 +- include/configs/pico-imx8mq.h | 4 +- include/configs/pm9261.h | 52 +-- include/configs/pm9263.h | 56 +-- include/configs/pm9g45.h | 12 +- include/configs/poleg.h | 4 +- include/configs/presidio_asic.h | 16 +- include/configs/qcs404-evb.h | 2 +- include/configs/qemu-ppce500.h | 34 +- include/configs/r2dplus.h | 6 +- include/configs/rcar-gen2-common.h | 6 +- include/configs/rcar-gen3-common.h | 2 +- include/configs/rk3036_common.h | 2 +- include/configs/rk3128_common.h | 2 +- include/configs/rk322x_common.h | 2 +- include/configs/rk3288_common.h | 2 +- include/configs/rpi.h | 6 +- include/configs/rv1108_common.h | 6 +- include/configs/s5p_goni.h | 2 +- include/configs/s5pc210_universal.h | 2 +- include/configs/salvator-x.h | 4 +- include/configs/sam9x60_curiosity.h | 4 +- include/configs/sam9x60ek.h | 4 +- include/configs/sama5d27_som1_ek.h | 4 +- include/configs/sama5d27_wlsom1_ek.h | 4 +- include/configs/sama5d2_icp.h | 4 +- include/configs/sama5d2_ptc_ek.h | 4 +- include/configs/sama5d3xek.h | 2 +- include/configs/sama7g5ek.h | 4 +- include/configs/sandbox.h | 2 +- include/configs/sdm845.h | 2 +- include/configs/siemens-am33x-common.h | 2 +- include/configs/smartweb.h | 18 +- include/configs/smdkc100.h | 2 +- include/configs/smegw01.h | 4 +- include/configs/snapper9g45.h | 8 +- include/configs/sniper.h | 4 +- include/configs/socfpga_arria10_socdk.h | 2 +- include/configs/socfpga_arria5_secu1.h | 4 +- include/configs/socfpga_chameleonv3.h | 2 +- include/configs/socfpga_common.h | 24 +- include/configs/socfpga_soc64_common.h | 4 +- include/configs/socrates.h | 66 ++-- include/configs/somlabs_visionsom_6ull.h | 4 +- include/configs/stemmy.h | 2 +- include/configs/stih410-b2260.h | 4 +- include/configs/stm32f429-discovery.h | 4 +- include/configs/stm32f429-evaluation.h | 6 +- include/configs/stm32f469-discovery.h | 6 +- include/configs/stm32f746-disco.h | 8 +- include/configs/stm32h743-disco.h | 6 +- include/configs/stm32h743-eval.h | 6 +- include/configs/stm32h750-art-pi.h | 6 +- include/configs/stm32mp13_common.h | 2 +- include/configs/stm32mp13_st_common.h | 2 +- include/configs/stm32mp15_common.h | 2 +- include/configs/stm32mp15_st_common.h | 2 +- include/configs/stmark2.h | 42 +- include/configs/stv0991.h | 6 +- include/configs/sunxi-common.h | 4 +- include/configs/synquacer.h | 8 +- include/configs/taurus.h | 18 +- include/configs/tb100.h | 4 +- include/configs/tbs2910.h | 6 +- include/configs/tegra-common.h | 10 +- include/configs/ten64.h | 2 +- include/configs/thunderx_88xx.h | 6 +- include/configs/ti814x_evm.h | 2 +- include/configs/ti816x_evm.h | 2 +- include/configs/ti_am335x_common.h | 2 +- include/configs/ti_armv7_keystone2.h | 8 +- include/configs/ti_omap3_common.h | 4 +- include/configs/ti_omap4_common.h | 4 +- include/configs/ti_omap5_common.h | 2 +- include/configs/total_compute.h | 2 +- include/configs/tplink_wdr4300.h | 4 +- include/configs/tqma6.h | 4 +- include/configs/tqma6_wru4.h | 4 +- include/configs/trats.h | 2 +- include/configs/trats2.h | 2 +- include/configs/turris_mox.h | 2 +- include/configs/udoo.h | 4 +- include/configs/udoo_neo.h | 4 +- include/configs/ulcb.h | 4 +- include/configs/uniphier.h | 6 +- include/configs/usb_a9263.h | 8 +- include/configs/usbarmory.h | 4 +- include/configs/vcoreiii.h | 2 +- include/configs/verdin-imx8mm.h | 6 +- include/configs/verdin-imx8mp.h | 6 +- include/configs/vexpress_aemv8.h | 4 +- include/configs/vexpress_common.h | 18 +- include/configs/vf610twr.h | 4 +- include/configs/vinco.h | 4 +- include/configs/vining_2000.h | 4 +- include/configs/vocore2.h | 6 +- include/configs/wandboard.h | 4 +- include/configs/warp7.h | 4 +- include/configs/work_92105.h | 2 +- include/configs/x530.h | 2 +- include/configs/x86-common.h | 2 +- include/configs/xea.h | 6 +- include/configs/xilinx_versal.h | 2 +- include/configs/xilinx_versal_net.h | 2 +- include/configs/xilinx_zynqmp.h | 8 +- include/configs/xilinx_zynqmp_r5.h | 6 +- include/configs/xpress.h | 4 +- include/configs/xtfpga.h | 40 +- include/configs/zynq-common.h | 20 +- include/configs/zynq_cse.h | 8 +- include/fsl-mc/fsl_mc.h | 2 +- include/fsl_ifc.h | 2 +- include/i2c.h | 16 +- include/mpc85xx.h | 34 +- include/mpc86xx.h | 6 +- include/mtd/cfi_flash.h | 4 +- include/mvebu_mmc.h | 2 +- include/post.h | 4 +- include/spl.h | 2 +- include/system-constants.h | 4 +- include/tca642x.h | 8 +- include/tsec.h | 4 +- lib/time.c | 14 +- post/drivers/memory.c | 4 +- post/tests.c | 8 +- tools/envcrc.c | 6 +- 744 files changed, 5931 insertions(+), 5930 deletions(-) (limited to 'include') diff --git a/.checkpatch.conf b/.checkpatch.conf index 9e40ea060be..c368d414726 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -4,7 +4,7 @@ # Temporary for false positive in checkpatch --ignore COMPLEX_MACRO -# For CONFIG_SYS_I2C_NOPROBES +# For CFG_SYS_I2C_NOPROBES --ignore MULTISTATEMENT_MACRO_USE_DO_WHILE # For simple_strtoul diff --git a/Kconfig b/Kconfig index 67f46467b17..297281e4746 100644 --- a/Kconfig +++ b/Kconfig @@ -264,8 +264,8 @@ config HAS_CUSTOM_SYS_INIT_SP_ADDR default y if TFABOOT help Typically, we use an initial stack pointer address that is calculated - by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the - statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the + by taking the statically defined CFG_SYS_INIT_RAM_ADDR, adding the + statically defined CFG_SYS_INIT_RAM_SIZE and then subtracting the build-time constant of GENERATED_GBL_DATA_SIZE. On MIPS a different but statica calculation is performed. However, some platforms will take a different approach. Say Y here to define the address statically @@ -333,7 +333,7 @@ config SPL_SYS_MALLOC_F_LEN particular needs this to operate, so that it can allocate the initial serial device and any others that are needed. - It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new + It is possible to enable CFG_SYS_SPL_MALLOC_START to start a new malloc() region in SDRAM once it is inited. config TPL_SYS_MALLOC_F_LEN diff --git a/Makefile b/Makefile index de5746399a6..d48f52f2943 100644 --- a/Makefile +++ b/Makefile @@ -1138,10 +1138,10 @@ endif $(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\ $(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG)) $(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY)) - @# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which + @# CFG_SYS_TIMER_RATE has brackets in it for some boards which @# confuses this rule. Use if() to send just a single character which @# is enable to tell 'deprecated' that one of these symbols exists - $(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CONFIG_SYS_TIMER_RATE)$(CONFIG_SYS_TIMER_COUNTER)),x)) + $(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x)) $(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL)) $(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI)) @# Check that this build does not use CONFIG options that we do not @@ -1361,8 +1361,8 @@ u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE # U-Boot entry point, needed for booting of full-blown U-Boot # from the SPL U-Boot version. # -ifndef CONFIG_SYS_UBOOT_START -CONFIG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE) +ifndef CFG_SYS_UBOOT_START +CFG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE) endif # Boards with more complex image requirements can provide an .its source file @@ -1387,7 +1387,7 @@ endif ifdef CONFIG_SPL_LOAD_FIT MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -p $(CONFIG_FIT_EXTERNAL_OFFSET) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \ @@ -1395,10 +1395,10 @@ MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST))) else MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log endif @@ -1429,7 +1429,7 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ UBOOT_BIN := u-boot.bin MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" u-boot.bin.lzma: u-boot.bin FORCE diff --git a/README b/README index bb35a895b75..0a7635d1a24 100644 --- a/README +++ b/README @@ -341,7 +341,7 @@ The following options need to be configured: CFG_SYS_FSL_DDR_SDRAM_BASE_PHY Physical address from the view of DDR controllers. It is the - same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But + same as CFG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs. - MIPS CPU options: @@ -352,7 +352,7 @@ The following options need to be configured: be swapped if a flash programmer is used. - ARM options: - CONFIG_SYS_EXCEPTION_VECTORS_HIGH + CFG_SYS_EXCEPTION_VECTORS_HIGH Select high exception vectors of the ARM core, e.g., do not clear the V bit of the c1 register of CP15. @@ -415,7 +415,7 @@ The following options need to be configured: the defaults discussed just above. - Cache Configuration for ARM: - CONFIG_SYS_PL310_BASE - Physical base address of PL310 + CFG_SYS_PL310_BASE - Physical base address of PL310 controller register space - Serial Ports: @@ -485,7 +485,7 @@ The following options need to be configured: - GPIO Support: CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO - The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of + The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of chip-ngpio pairs that tell the PCA953X driver the number of pins supported by a particular chip. @@ -927,21 +927,21 @@ The following options need to be configured: CONFIG_SYS_I2C_DIRECT_BUS define this, if you don't use i2c muxes on your hardware. - if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can + if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can omit this define. - CONFIG_SYS_I2C_MAX_HOPS + CFG_SYS_I2C_MAX_HOPS define how many muxes are maximal consecutively connected on one i2c bus. If you not use i2c muxes, omit this define. - CONFIG_SYS_I2C_BUSES + CFG_SYS_I2C_BUSES hold a list of buses you want to use, only used if CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example - a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and + a board with CFG_SYS_I2C_MAX_HOPS = 1 and CFG_SYS_NUM_I2C_BUSES = 9: - CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \ + CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \ @@ -1044,7 +1044,7 @@ The following options need to be configured: active. To switch to a different bus, use the 'i2c dev' command. Note that bus numbering is zero-based. - CONFIG_SYS_I2C_NOPROBES + CFG_SYS_I2C_NOPROBES This option specifies a list of I2C devices that will be skipped when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS @@ -1053,16 +1053,16 @@ The following options need to be configured: e.g. #undef CONFIG_I2C_MULTI_BUS - #define CONFIG_SYS_I2C_NOPROBES {0x50,0x68} + #define CFG_SYS_I2C_NOPROBES {0x50,0x68} will skip addresses 0x50 and 0x68 on a board with one I2C bus #define CONFIG_I2C_MULTI_BUS - #define CONFIG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} + #define CFG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 - CONFIG_SYS_RTC_BUS_NUM + CFG_SYS_RTC_BUS_NUM If defined, then this indicates the I2C bus number for the RTC. If not defined, then U-Boot assumes that RTC is on I2C bus 0. @@ -1120,19 +1120,19 @@ The following options need to be configured: configuration if the INIT_B line goes low (which indicated a CRC error). - CONFIG_SYS_FPGA_WAIT_INIT + CFG_SYS_FPGA_WAIT_INIT Maximum time to wait for the INIT_B line to de-assert after PROB_B has been de-asserted during a Virtex II FPGA configuration sequence. The default time is 500 ms. - CONFIG_SYS_FPGA_WAIT_BUSY + CFG_SYS_FPGA_WAIT_BUSY Maximum time to wait for BUSY to de-assert during Virtex II FPGA configuration. The default is 5 ms. - CONFIG_SYS_FPGA_WAIT_CONFIG + CFG_SYS_FPGA_WAIT_CONFIG Time to wait after FPGA configuration. The default is 200 ms. @@ -1429,12 +1429,12 @@ Configuration Settings: - CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to prompt for user input. -- CONFIG_SYS_BAUDRATE_TABLE: +- CFG_SYS_BAUDRATE_TABLE: List of legal baudrate settings for this board. -- CONFIG_SYS_MEM_RESERVE_SECURE +- CFG_SYS_MEM_RESERVE_SECURE Only implemented for ARMv8 for now. - If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory + If defined, the size of CFG_SYS_MEM_RESERVE_SECURE memory is substracted from total RAM and won't be reported to OS. This memory can be used as secure memory. A variable gd->arch.secure_ram is used to track the location. In systems @@ -1444,7 +1444,7 @@ Configuration Settings: - CFG_SYS_SDRAM_BASE: Physical start address of SDRAM. _Must_ be 0 here. -- CONFIG_SYS_FLASH_BASE: +- CFG_SYS_FLASH_BASE: Physical start address of Flash memory. - CONFIG_SYS_MALLOC_LEN: @@ -1468,16 +1468,16 @@ Configuration Settings: boards which do not use the full malloc in SPL (which is enabled with CONFIG_SYS_SPL_MALLOC). -- CONFIG_SYS_BOOTMAPSZ: +- CFG_SYS_BOOTMAPSZ: Maximum size of memory mapped by the startup code of the Linux kernel; all data that must be processed by the Linux kernel (bd_info, boot arguments, FDT blob if used) must be put below this limit, unless "bootm_low" environment variable is defined and non-zero. In such case all data for the Linux kernel must be between "bootm_low" - and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment + and "bootm_low" + CFG_SYS_BOOTMAPSZ. The environment variable "bootm_mapsize" will override the value of - CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined, + CFG_SYS_BOOTMAPSZ. If CFG_SYS_BOOTMAPSZ is undefined, then the value in "bootm_size" will be used instead. - CONFIG_SYS_BOOT_GET_CMDLINE: @@ -1638,11 +1638,11 @@ Low Level (hardware related) configuration options: Default (power-on reset) physical address of CCSR on Freescale PowerPC SOCs. -- CONFIG_SYS_CCSRBAR: +- CFG_SYS_CCSRBAR: Virtual address of CCSR. On a 32-bit build, this is typically the same value as CONFIG_SYS_CCSRBAR_DEFAULT. -- CONFIG_SYS_CCSRBAR_PHYS: +- CFG_SYS_CCSRBAR_PHYS: Physical address of CCSR. CCSR can be relocated to a new physical address, if desired. In this case, this macro should be set to that address. Otherwise, it should be set to the @@ -1650,17 +1650,17 @@ Low Level (hardware related) configuration options: is typically relocated on 36-bit builds. It is recommended that this macro be defined via the _HIGH and _LOW macros: - #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH - * 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW) + #define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH + * 1ull) << 32 | CFG_SYS_CCSRBAR_PHYS_LOW) -- CONFIG_SYS_CCSRBAR_PHYS_HIGH: - Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically +- CFG_SYS_CCSRBAR_PHYS_HIGH: + Bits 33-36 of CFG_SYS_CCSRBAR_PHYS. This value is typically either 0 (32-bit build) or 0xF (36-bit build). This macro is used in assembly code, so it must not contain typecasts or integer size suffixes (e.g. "ULL"). -- CONFIG_SYS_CCSRBAR_PHYS_LOW: - Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is +- CFG_SYS_CCSRBAR_PHYS_LOW: + Lower 32-bits of CFG_SYS_CCSRBAR_PHYS. This macro is used in assembly code, so it must not contain typecasts or integer size suffixes (e.g. "ULL"). @@ -1668,7 +1668,7 @@ Low Level (hardware related) configuration options: DO NOT CHANGE unless you know exactly what you're doing! (11-4) [MPC8xx systems only] -- CONFIG_SYS_INIT_RAM_ADDR: +- CFG_SYS_INIT_RAM_ADDR: Start address of memory area that can be used for initial data and stack; please note that this must be @@ -2737,7 +2737,7 @@ locked as (mis-) used as memory, etc. cause you grief during the initial boot! It is frequently not used. - CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere + CFG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere with your processor/board/system design. The default value you will find in any recent u-boot distribution in walnut.h should work for you. I'd set it to a value larger diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 5a1536539dc..9e76a4a9e0e 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -18,7 +18,7 @@ #include #ifndef CONFIG_SYS_PHY_UBOOT_BASE -#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE +#define CONFIG_SYS_PHY_UBOOT_BASE CFG_SYS_UBOOT_BASE #endif /* diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index aca7793c579..c882bd39eab 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -95,7 +95,7 @@ flush_dcache: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ -#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ #else bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c index d96406f7626..17bd53dae84 100644 --- a/arch/arm/cpu/armv7/arch_timer.c +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SYS_HZ_CLOCK +#ifndef CFG_SYS_HZ_CLOCK static inline u32 read_cntfrq(void) { u32 frq; @@ -29,8 +29,8 @@ int timer_init(void) gd->arch.tbl = 0; gd->arch.tbu = 0; -#ifdef CONFIG_SYS_HZ_CLOCK - gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; +#ifdef CFG_SYS_HZ_CLOCK + gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK; #else gd->arch.timer_rate_hz = read_cntfrq(); #endif diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index d09c21d5d9b..25e4b49c70e 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -313,9 +313,9 @@ int cpu_eth_init(struct bd_info *bis) int arch_cpu_init(void) { - void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *rcpm2_base = - (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); + (void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; u32 state; diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 0e7d5fa06dc..599b7e18ef3 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -183,7 +183,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, - CONFIG_SYS_IFC_ADDR); + CFG_SYS_IFC_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED); #else off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT, diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index 954fa5f8b45..dbb0766a9c6 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -42,7 +42,7 @@ static void __secure ls1_save_ddr_head(void) static void __secure ls1_fsm_setup(void) { - void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR; out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001); @@ -118,7 +118,7 @@ static void __secure ls1_delay(unsigned int loop) static void __secure ls1_start_fsm(void) { - void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR; struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR; diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c index 67764ccf66a..f7cc45772f9 100644 --- a/arch/arm/cpu/armv7/stv0991/timer.c +++ b/arch/arm/cpu/armv7/stv0991/timer.c @@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); #define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) -#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) +#define GPT_RESOLUTION (CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) DECLARE_GLOBAL_DATA_PTR; @@ -67,7 +67,7 @@ void __udelay(unsigned long usec) { ulong tmo; ulong start = get_timer_masked(); - ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100); + ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100); ulong rndoff; rndoff = (usec % 10) ? 1 : 0; diff --git a/arch/arm/cpu/armv7m/systick-timer.c b/arch/arm/cpu/armv7m/systick-timer.c index 556eaf8c74a..c30af4ff7a2 100644 --- a/arch/arm/cpu/armv7m/systick-timer.c +++ b/arch/arm/cpu/armv7m/systick-timer.c @@ -18,7 +18,7 @@ * The number of reference clock ticks that correspond to 10ms is normally * defined in the SysTick Calibration register's TENMS field. However, on some * devices this is wrong, so this driver allows the clock rate to be defined - * using CONFIG_SYS_HZ_CLOCK. + * using CFG_SYS_HZ_CLOCK. */ #include @@ -76,10 +76,10 @@ int timer_init(void) /* * If the TENMS field is inexact or wrong, specify the clock rate using - * CONFIG_SYS_HZ_CLOCK. + * CFG_SYS_HZ_CLOCK. */ -#if defined(CONFIG_SYS_HZ_CLOCK) - gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; +#if defined(CFG_SYS_HZ_CLOCK) + gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK; #else gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100; #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index bbaa91f0e10..99413ef52e2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -114,7 +114,7 @@ static struct mm_region early_map[] = { CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, - { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, + { CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, @@ -130,9 +130,9 @@ static struct mm_region early_map[] = { PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #ifdef CONFIG_FSL_IFC - /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ + /* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, + CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, #endif @@ -391,7 +391,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #endif -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE {}, /* space holder for secure mem */ #endif {}, @@ -445,7 +445,7 @@ static inline void early_mmu_setup(void) if (el == 3) gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE; else - gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; + gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE; gd->arch.tlb_fillptr = gd->arch.tlb_addr; gd->arch.tlb_size = EARLY_PGTABLE_SIZE; @@ -568,7 +568,7 @@ static inline void final_mmu_setup(void) } } -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { if (el == 3) { /* @@ -580,7 +580,7 @@ static inline void final_mmu_setup(void) gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; final_map[index].virt = gd->arch.secure_ram & ~0x3; final_map[index].phys = final_map[index].virt; - final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE; + final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE; final_map[index].attrs = PTE_BLOCK_OUTER_SHARE; gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; tlb_addr_save = gd->arch.tlb_addr; @@ -1323,10 +1323,10 @@ phys_size_t get_effective_memsize(void) ea_size = gd->ram_size; } -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE /* Check if we have enough space for secure memory */ - if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) - ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + if (ea_size > CFG_SYS_MEM_RESERVE_SECURE) + ea_size -= CFG_SYS_MEM_RESERVE_SECURE; else printf("Error: No enough space for secure memory.\n"); #endif @@ -1433,7 +1433,7 @@ int dram_init_banksize(void) * gd->arch.secure_ram should be done to avoid running it repeatedly. */ -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { debug("No need to run again, skip %s\n", __func__); @@ -1442,11 +1442,11 @@ int dram_init_banksize(void) #endif gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE; gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; + CFG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; @@ -1458,17 +1458,17 @@ int dram_init_banksize(void) } else { gd->bd->bi_dram[0].size = gd->ram_size; } -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->bd->bi_dram[0].size > - CONFIG_SYS_MEM_RESERVE_SECURE) { + CFG_SYS_MEM_RESERVE_SECURE) { gd->bd->bi_dram[0].size -= - CONFIG_SYS_MEM_RESERVE_SECURE; + CFG_SYS_MEM_RESERVE_SECURE; gd->arch.secure_ram = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; - gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE; } -#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ +#endif /* CFG_SYS_MEM_RESERVE_SECURE */ #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) /* Assign memory for MC */ @@ -1520,7 +1520,7 @@ int dram_init_banksize(void) } #endif -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE debug("%s is called. gd->ram_size is reduced to %lu\n", __func__, (ulong)gd->ram_size); #endif @@ -1580,7 +1580,7 @@ void update_early_mmu_table(void) } else { mmu_change_region_attr( CFG_SYS_SDRAM_BASE, - CONFIG_SYS_DDR_BLOCK1_SIZE, + CFG_SYS_DDR_BLOCK1_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | @@ -1589,10 +1589,10 @@ void update_early_mmu_table(void) #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" #endif - if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE > + if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE > CONFIG_SYS_DDR_BLOCK2_SIZE) { mmu_change_region_attr( - CONFIG_SYS_DDR_BLOCK2_BASE, + CFG_SYS_DDR_BLOCK2_BASE, CONFIG_SYS_DDR_BLOCK2_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | @@ -1601,7 +1601,7 @@ void update_early_mmu_table(void) mmu_change_region_attr( CONFIG_SYS_DDR_BLOCK3_BASE, gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE - + CFG_SYS_DDR_BLOCK1_SIZE - CONFIG_SYS_DDR_BLOCK2_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | @@ -1611,9 +1611,9 @@ void update_early_mmu_table(void) #endif { mmu_change_region_attr( - CONFIG_SYS_DDR_BLOCK2_BASE, + CFG_SYS_DDR_BLOCK2_BASE, gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE, + CFG_SYS_DDR_BLOCK1_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 index 9119d60ffb3..6f3fe7ca6e0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 @@ -116,10 +116,10 @@ Flash Layout Environment Variables ===================== mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined - the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. + the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. mcmemsize: MC DRAM block size in hex. If this variable is not defined, the value - CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. + CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. mcinitcmd: This environment variable is defined to initiate MC and DPL deployment from the location where it is stored(NOR, NAND, SD, SATA, USB)during diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c index 4880a313ea6..e3c3fc6bfb5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -10,7 +10,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index e47d3af85e0..333d7e2fa21 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -9,7 +9,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 89a6262c128..359cbc04309 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -531,7 +531,7 @@ static void erratum_a010539(void) porsr1 = in_be32(&gur->porsr1); porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; - out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), + out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), porsr1); out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); #endif @@ -643,8 +643,8 @@ void init_pfe_scfg_dcfg_regs(void) out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS | SCFG_RD_QOS1_PFE2_QOS)); - ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); - out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, + ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); + out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, ecccr2 | (unsigned int)DISABLE_PFE_ECC); } #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 3a4b665f244..61fced451eb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -116,7 +116,7 @@ void board_init_f(ulong dummy) #endif dram_init(); #ifdef CONFIG_SPL_FSL_LS_PPA -#ifndef CONFIG_SYS_MEM_RESERVE_SECURE +#ifndef CFG_SYS_MEM_RESERVE_SECURE #error Need secure RAM for PPA #endif /* diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index 540436ba028..c0e8726346f 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -198,7 +198,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img, goto out; } -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE /* * The SEC Firmware must be stored in secure memory. * Append SEC Firmware to secure mmu table. @@ -211,7 +211,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img, sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) + gd->arch.tlb_size; #else -#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support" +#error "The CFG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support" #endif /* Align SEC Firmware base address to 4K */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 0669222fed7..c9c72e32717 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -20,13 +20,13 @@ * Reserve secure memory * To be aligned with MMU block size */ -#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ +#define CFG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */ #ifdef CONFIG_ARCH_LS2080A #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 -#define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CFG_SYS_PAGE_SIZE 0x10000 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) @@ -37,8 +37,8 @@ #define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ /* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -96,7 +96,7 @@ #elif defined(CONFIG_ARCH_LS1088A) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CFG_SYS_PAGE_SIZE 0x10000 #define SRDS_MAX_LANES 4 #define SRDS_BITS_PER_LANE 4 @@ -122,8 +122,8 @@ #define SMMU_BASE 0x05000000 /* GR0 Base */ /* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* DCFG - GUR */ #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ @@ -141,15 +141,15 @@ #endif #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } -#define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CFG_SYS_PAGE_SIZE 0x10000 #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ /* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -192,8 +192,8 @@ #define SMMU_BASE 0x05000000 /* GR0 Base */ /* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* SEC */ @@ -212,8 +212,8 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 7 #define CFG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -251,15 +251,15 @@ #elif defined(CONFIG_ARCH_LS1012A) #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #elif defined(CONFIG_ARCH_LS1046A) #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 8 #define CFG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* SMMU Defintions */ #define SMMU_BASE 0x09000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 9cddb41a89c..d5f63f4a7ed 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -75,7 +75,7 @@ void fdt_fixup_icid(void *blob); #define SET_USB_ICID(usb_num, compat, streamid) \ SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\ - CONFIG_SYS_XHCI_USB##usb_num##_ADDR) + CFG_SYS_XHCI_USB##usb_num##_ADDR) #define SET_SATA_ICID(compat, streamid) \ SET_SCFG_ICID(compat, streamid, sata_icid,\ @@ -142,7 +142,7 @@ extern int fman_icid_tbl_sz; #define SET_USB_ICID(usb_num, compat, streamid) \ SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\ - CONFIG_SYS_XHCI_USB##usb_num##_ADDR) + CFG_SYS_XHCI_USB##usb_num##_ADDR) #define SET_SATA_ICID(sata_num, compat, streamid) \ SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 64dc7c88b7f..9794db04499 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -11,11 +11,11 @@ #include #endif -#define CONFIG_SYS_DCSRBAR 0x20000000 -#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) +#define CFG_SYS_DCSRBAR 0x20000000 +#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00140000) #define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) +#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) #define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) @@ -30,37 +30,37 @@ #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) #define CFG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) #define CFG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) -#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) -#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) -#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) +#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) +#define CFG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) - -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000 -#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ - CONFIG_SYS_BMAN_MEM_BASE) -#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680 +#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) +#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) + +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0x508000000 +#define CFG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ + CFG_SYS_BMAN_MEM_BASE) +#define CFG_SYS_BMAN_MEM_SIZE 0x08000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x10000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x10000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0x3E80 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0x500000000 +#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE +#define CFG_SYS_QMAN_MEM_SIZE 0x08000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x10000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0x3680 #define CFG_SYS_FSL_TIMER_ADDR 0x02b00000 @@ -134,20 +134,20 @@ #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ #define TP_INIT_PER_CLUSTER 4 -#ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR 0x01000000 +#ifndef CFG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0x01000000 #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000 +#ifndef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_LOW 0x01000000 #endif -#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ - CONFIG_SYS_CCSRBAR_PHYS_LOW) +#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CFG_SYS_CCSRBAR_PHYS_LOW) struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index cd112402e0c..ca5e33379ba 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -33,7 +33,7 @@ #define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR #define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000) #ifndef CONFIG_NXP_LSCH3_2 -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) #endif #define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) @@ -67,8 +67,8 @@ #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) -#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) +#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) /* TZ Address Space Controller Definitions */ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ @@ -105,7 +105,7 @@ #define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000) /* SFP */ -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) +#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) /* SEC */ #define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull @@ -173,7 +173,7 @@ #endif /* Security Monitor */ -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) +#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) /* MMU 500 */ #define SMMU_SCR0 (SMMU_BASE + 0x0) diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 6de431f6bbb..3ad78cb1e64 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -23,7 +23,7 @@ #define CFG_SYS_NS16550_CLK 13000000 #endif -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } /* NAND */ @@ -49,7 +49,7 @@ /* USB OHCI */ #if defined(CONFIG_USB_OHCI_LPC32XX) -#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE +#define CFG_SYS_USB_OHCI_REGS_BASE USB_BASE #endif #endif /* _LPC32XX_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 62026bda9e2..6413a307d27 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -11,36 +11,36 @@ #define OCRAM_BASE_S_ADDR 0x10010000 #define OCRAM_S_SIZE 0x00010000 -#define CONFIG_SYS_DCSRBAR 0x20000000 +#define CFG_SYS_DCSRBAR 0x20000000 -#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) -#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000) +#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00220000) +#define SYS_FSL_DCSR_RCPM_ADDR (CFG_SYS_DCSRBAR + 0x00222000) #define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000) #define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) +#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) #define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) #define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) +#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) +#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) #define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) #define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) #define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) -#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CFG_SYS_FSL_SEC_OFFSET 0x00700000 #define CFG_SYS_FSL_JR0_OFFSET 0x00710000 -#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 -#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 +#define CFG_SYS_TSEC1_OFFSET 0x01d10000 +#define CFG_SYS_MDIO1_OFFSET 0x01d24000 -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index b0acf677984..a0c3da7f46d 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -42,24 +42,24 @@ #define DCFG_DCSR_PORCR1 0 -#ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR +#ifndef CFG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR CONFIG_SYS_IMMR #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf #else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR +#ifndef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR #endif -#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ - CONFIG_SYS_CCSRBAR_PHYS_LOW) +#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CFG_SYS_CCSRBAR_PHYS_LOW) struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h index fb5ded89078..acd8c69f694 100644 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h @@ -12,14 +12,14 @@ { .compat = name, \ .id = { idA }, .num_ids = 1, \ .reg_offset = off + CONFIG_SYS_IMMR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ { .compat = name, \ .id = { idA, idB }, .num_ids = 2, \ .reg_offset = off + CONFIG_SYS_IMMR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } /* diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index d5c0ed8e6c2..a0ab3a0e665 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -899,9 +899,9 @@ struct esdc_regs { * Generic timer support */ #ifdef CONFIG_MX31_CLK32 -#define CONFIG_SYS_TIMER_RATE CONFIG_MX31_CLK32 +#define CFG_SYS_TIMER_RATE CONFIG_MX31_CLK32 #else -#define CONFIG_SYS_TIMER_RATE 32768 +#define CFG_SYS_TIMER_RATE 32768 #endif #endif /* __ASM_ARCH_MX31_IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h index 5b12d90d585..eb1ddca6002 100644 --- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h +++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h @@ -36,6 +36,6 @@ struct gpt_regs *const gpt1_regs_ptr = #define GPT_FREE_RUNNING 0xFFFF /* Timer, HZ specific defines */ -#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128) +#define CFG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128) #endif diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index 3525f22e7df..241b44928a9 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -18,6 +18,6 @@ #endif /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ -#define CONFIG_SYS_TCLK 24000000 +#define CFG_SYS_TCLK 24000000 #endif diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index cd6112dfcda..9e746e380a2 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -54,7 +54,7 @@ struct arch_global_data { unsigned long tlb_emerg; #endif #endif -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE #define MEM_RESERVE_SECURE_SECURED 0x1 #define MEM_RESERVE_SECURE_MAINTAINED 0x2 #define MEM_RESERVE_SECURE_ADDR_MASK (~0x3) diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c index 826e09e72c0..5e6eaad968d 100644 --- a/arch/arm/lib/bdinfo.c +++ b/arch/arm/lib/bdinfo.c @@ -29,7 +29,7 @@ void arch_print_bdinfo(void) struct bd_info *bd = gd->bd; bdinfo_print_num_l("arch_number", bd->bi_arch_number); -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) { bdinfo_print_num_ll("Secure ram", gd->arch.secure_ram & diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c index bbaaaa4157a..d05314ee57f 100644 --- a/arch/arm/lib/cache-pl310.c +++ b/arch/arm/lib/cache-pl310.c @@ -11,7 +11,7 @@ #include #include -struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; static void pl310_cache_sync(void) { diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index a2bf2e57b94..1a589c7e2a0 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -152,7 +152,7 @@ __weak int arm_reserve_mmu(void) debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size); -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE /* * Record allocated tlb_addr in case gd->tlb_addr to be overwritten * with location within secure ram. diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index a54c84b062b..7cf7d1636f5 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -83,8 +83,8 @@ */ _start: -#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG - .word CONFIG_SYS_DV_NOR_BOOT_CFG +#ifdef CFG_SYS_DV_NOR_BOOT_CFG + .word CFG_SYS_DV_NOR_BOOT_CFG #endif ARM_VECTORS #endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */ diff --git a/arch/arm/mach-at91/arm920t/clock.c b/arch/arm/mach-at91/arm920t/clock.c index c7440278d8f..09ac66d619d 100644 --- a/arch/arm/mach-at91/arm920t/clock.c +++ b/arch/arm/mach-at91/arm920t/clock.c @@ -26,7 +26,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->arch.main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -107,7 +107,7 @@ int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#ifndef CFG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* * When the bootloader initialized the main oscillator correctly, @@ -120,7 +120,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->arch.main_clk_rate_hz = main_clock; diff --git a/arch/arm/mach-at91/arm920t/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c index 44c079c0fdd..9bf03fd68ec 100644 --- a/arch/arm/mach-at91/arm920t/cpu.c +++ b/arch/arm/mach-at91/arm920t/cpu.c @@ -16,11 +16,11 @@ #include #include -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#ifndef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 0 #endif int arch_cpu_init(void) { - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); } diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S index 3b91a0cba33..6b7d3cbc710 100644 --- a/arch/arm/mach-at91/arm920t/lowlevel_init.S +++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S @@ -94,11 +94,11 @@ SMRDATA: .word AT91_ASM_MC_SMC_CSR0 .word CONFIG_SYS_SMC_CSR0_VAL .word AT91_ASM_PMC_PLLAR - .word CONFIG_SYS_PLLAR_VAL + .word CFG_SYS_PLLAR_VAL .word AT91_ASM_PMC_PLLBR .word CONFIG_SYS_PLLBR_VAL .word AT91_ASM_PMC_MCKR - .word CONFIG_SYS_MCKR_VAL + .word CFG_SYS_MCKR_VAL SMRDATAE: /* here there's a delay */ SMRDATA1: @@ -107,17 +107,17 @@ SMRDATA1: .word AT91_ASM_PIOC_BSR .word CONFIG_SYS_PIOC_BSR_VAL .word AT91_ASM_PIOC_PDR - .word CONFIG_SYS_PIOC_PDR_VAL + .word CFG_SYS_PIOC_PDR_VAL .word AT91_ASM_MC_EBI_CSA .word CONFIG_SYS_EBI_CSA_VAL .word AT91_ASM_MC_SDRAMC_CR - .word CONFIG_SYS_SDRC_CR_VAL + .word CFG_SYS_SDRC_CR_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL + .word CFG_SYS_SDRC_MR_VAL .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL1 + .word CFG_SYS_SDRC_MR_VAL1 .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL .word CFG_SYS_SDRAM @@ -135,15 +135,15 @@ SMRDATA1: .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL2 + .word CFG_SYS_SDRC_MR_VAL2 .word CFG_SYS_SDRAM1 .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL + .word CFG_SYS_SDRC_TR_VAL .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL3 + .word CFG_SYS_SDRC_MR_VAL3 .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL SMRDATA1E: diff --git a/arch/arm/mach-at91/arm920t/timer.c b/arch/arm/mach-at91/arm920t/timer.c index c400e878135..8ef5764e315 100644 --- a/arch/arm/mach-at91/arm920t/timer.c +++ b/arch/arm/mach-at91/arm920t/timer.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; /* the number of clocks per CONFIG_SYS_HZ */ -#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) +#define TIMER_LOAD_VAL (CFG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) int timer_init(void) { @@ -92,7 +92,7 @@ void __udelay(unsigned long usec) u32 endtime; signed long diff; - tmo = CONFIG_SYS_HZ_CLOCK / 1000; + tmo = CFG_SYS_HZ_CLOCK / 1000; tmo *= usec; tmo /= 1000; diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index c68e0c0c3c4..013daf43b74 100644 --- a/arch/arm/mach-at91/arm926ejs/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -26,7 +26,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->arch.main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -115,7 +115,7 @@ int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#ifndef CFG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* * When the bootloader initialized the main oscillator correctly, @@ -128,7 +128,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->arch.main_clk_rate_hz = main_clock; diff --git a/arch/arm/mach-at91/arm926ejs/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c index 761edb6df58..5e84b0a40e1 100644 --- a/arch/arm/mach-at91/arm926ejs/cpu.c +++ b/arch/arm/mach-at91/arm926ejs/cpu.c @@ -15,13 +15,13 @@ #include #include -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#ifndef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 0 #endif int arch_cpu_init(void) { - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); } void arch_preboot_os(void) diff --git a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S index ecfe589e455..e159a74eeac 100644 --- a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S +++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S @@ -21,8 +21,8 @@ #ifdef CONFIG_ATMEL_LEGACY #include #endif -#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL -#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL +#ifndef CFG_SYS_MATRIX_EBICSA_VAL +#define CFG_SYS_MATRIX_EBICSA_VAL CFG_SYS_MATRIX_EBI0CSA_VAL #endif .globl lowlevel_init @@ -67,7 +67,7 @@ POS1: ldr r1, =(AT91_ASM_PMC_MOR) ldr r2, =(AT91_ASM_PMC_SR) /* Main oscillator Enable register PMC_MOR: */ - ldr r0, =CONFIG_SYS_MOR_VAL + ldr r0, =CFG_SYS_MOR_VAL str r0, [r1] /* Reading the PMC Status to detect when the Main Oscillator is enabled */ @@ -85,7 +85,7 @@ MOSCS_Loop: * ---------------------------------------------------------------------------- */ ldr r1, =(AT91_ASM_PMC_PLLAR) - ldr r0, =CONFIG_SYS_PLLAR_VAL + ldr r0, =CFG_SYS_PLLAR_VAL str r0, [r1] /* Reading the PMC Status register to detect when the PLLA is locked */ @@ -105,7 +105,7 @@ MOSCS_Loop1: ldr r1, =(AT91_ASM_PMC_MCKR) /* -Master Clock Controller register PMC_MCKR */ - ldr r0, =CONFIG_SYS_MCKR1_VAL + ldr r0, =CFG_SYS_MCKR1_VAL str r0, [r1] /* Reading the PMC Status to detect when the Master clock is ready */ @@ -116,7 +116,7 @@ MCKRDY_Loop: cmp r3, #AT91_PMC_IXR_MCKRDY bne MCKRDY_Loop - ldr r0, =CONFIG_SYS_MCKR2_VAL + ldr r0, =CFG_SYS_MCKR2_VAL str r0, [r1] /* Reading the PMC Status to detect when the Master clock is ready */ @@ -158,53 +158,53 @@ SDRAM_setup_end: SMRDATA: .word AT91_ASM_WDT_MR - .word CONFIG_SYS_WDTC_WDMR_VAL + .word CFG_SYS_WDTC_WDMR_VAL /* configure PIOx as EBI0 D[16-31] */ #if defined(CONFIG_AT91SAM9263) .word AT91_ASM_PIOD_PDR - .word CONFIG_SYS_PIOD_PDR_VAL1 + .word CFG_SYS_PIOD_PDR_VAL1 .word AT91_ASM_PIOD_PUDR - .word CONFIG_SYS_PIOD_PPUDR_VAL + .word CFG_SYS_PIOD_PPUDR_VAL .word AT91_ASM_PIOD_ASR - .word CONFIG_SYS_PIOD_PPUDR_VAL + .word CFG_SYS_PIOD_PPUDR_VAL #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \ || defined(CONFIG_AT91SAM9G20) .word AT91_ASM_PIOC_PDR - .word CONFIG_SYS_PIOC_PDR_VAL1 + .word CFG_SYS_PIOC_PDR_VAL1 .word AT91_ASM_PIOC_PUDR - .word CONFIG_SYS_PIOC_PPUDR_VAL + .word CFG_SYS_PIOC_PPUDR_VAL #endif .word AT91_ASM_MATRIX_CSA0 - .word CONFIG_SYS_MATRIX_EBICSA_VAL + .word CFG_SYS_MATRIX_EBICSA_VAL /* flash */ .word AT91_ASM_SMC_MODE0 - .word CONFIG_SYS_SMC0_MODE0_VAL + .word CFG_SYS_SMC0_MODE0_VAL .word AT91_ASM_SMC_CYCLE0 - .word CONFIG_SYS_SMC0_CYCLE0_VAL + .word CFG_SYS_SMC0_CYCLE0_VAL .word AT91_ASM_SMC_PULSE0 - .word CONFIG_SYS_SMC0_PULSE0_VAL + .word CFG_SYS_SMC0_PULSE0_VAL .word AT91_ASM_SMC_SETUP0 - .word CONFIG_SYS_SMC0_SETUP0_VAL + .word CFG_SYS_SMC0_SETUP0_VAL SMRDATA1: .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL1 + .word CFG_SYS_SDRC_MR_VAL1 .word AT91_ASM_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL1 + .word CFG_SYS_SDRC_TR_VAL1 .word AT91_ASM_SDRAMC_CR - .word CONFIG_SYS_SDRC_CR_VAL + .word CFG_SYS_SDRC_CR_VAL .word AT91_ASM_SDRAMC_MDR - .word CONFIG_SYS_SDRC_MDR_VAL + .word CFG_SYS_SDRC_MDR_VAL .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL2 + .word CFG_SYS_SDRC_MR_VAL2 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL1 .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL3 + .word CFG_SYS_SDRC_MR_VAL3 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL2 .word CFG_SYS_SDRAM_BASE @@ -222,20 +222,20 @@ SMRDATA1: .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL9 .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL4 + .word CFG_SYS_SDRC_MR_VAL4 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL10 .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL5 + .word CFG_SYS_SDRC_MR_VAL5 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL11 .word AT91_ASM_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL2 + .word CFG_SYS_SDRC_TR_VAL2 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL12 /* User reset enable*/ .word AT91_ASM_RSTC_MR - .word CONFIG_SYS_RSTC_RMR_VAL + .word CFG_SYS_RSTC_RMR_VAL #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP /* MATRIX_MCFG - REMAP all masters */ .word AT91_ASM_MATRIX_MCFG diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index aa6bb6bf31e..6bfa02d1d0a 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -28,7 +28,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->arch.main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -58,7 +58,7 @@ int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#ifndef CFG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* * When the bootloader initialized the main oscillator correctly, @@ -71,7 +71,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->arch.main_clk_rate_hz = main_clock; @@ -271,7 +271,7 @@ u32 at91_get_periph_generated_clk(u32 id) clk_source = regval & AT91_PMC_PCR_GCKCSS; switch (clk_source) { case AT91_PMC_PCR_GCKCSS_SLOW_CLK: - freq = CONFIG_SYS_AT91_SLOW_CLOCK; + freq = CFG_SYS_AT91_SLOW_CLOCK; break; case AT91_PMC_PCR_GCKCSS_MAIN_CLK: freq = gd->arch.main_clk_rate_hz; diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index 9b3753491eb..616621a1f9d 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -18,8 +18,8 @@ #include #include -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#ifndef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 0 #endif int arch_cpu_init(void) @@ -27,7 +27,7 @@ int arch_cpu_init(void) #if defined(CONFIG_CLK_CCF) return 0; #else - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); #endif } diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 2daeb4fef8f..103db269533 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -128,7 +128,7 @@ #define ATMEL_BASE_CS7 0x80000000 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index d5de8d55510..2b252f1e1ed 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -112,7 +112,7 @@ #define ATMEL_BASE_CS7 0x80000000 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index c9fff934da4..0aa1862567c 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h @@ -127,7 +127,7 @@ #define ATMEL_BASE_CS7 0x80000000 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index 588032582b2..22116f375b8 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h @@ -132,7 +132,7 @@ #define ATMEL_BASE_CS7 0x80000000 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index 8f9155c9ea6..b2c074e93ec 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h @@ -112,7 +112,7 @@ #define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */ /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index e3c494c5d5d..0efb4a9f6d6 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -162,7 +162,7 @@ #endif /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c +#define CFG_SYS_TIMER_COUNTER 0xfffffe3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/sam9x60.h b/arch/arm/mach-at91/include/mach/sam9x60.h index c08d19c6917..47c7c7209e3 100644 --- a/arch/arm/mach-at91/include/mach/sam9x60.h +++ b/arch/arm/mach-at91/include/mach/sam9x60.h @@ -140,7 +140,7 @@ #define ATMEL_CPU_NAME get_cpu_name() /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffe4c +#define CFG_SYS_TIMER_COUNTER 0xfffffe4c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index 5ff20e95732..567cdd3cbac 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -238,7 +238,7 @@ #define cpu_is_sama5d2 _cpu_is_sama5d2 /* PIT Timer(PIT_PIIR) */ -#define CONFIG_SYS_TIMER_COUNTER 0xf804803c +#define CFG_SYS_TIMER_COUNTER 0xf804803c #ifndef __ASSEMBLY__ unsigned int get_chip_id(void); diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index 83f18a8148f..9efcf5f4fab 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -185,7 +185,7 @@ #define CPU_HAS_PCR /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c +#define CFG_SYS_TIMER_COUNTER 0xfffffe3c /* * PMECC table in ROM diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h index e2edb6a51b1..9c80286adec 100644 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ b/arch/arm/mach-at91/include/mach/sama5d4.h @@ -217,7 +217,7 @@ (get_extension_chip_id() == ARCH_EXID_SAMA5D44)) /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c +#define CFG_SYS_TIMER_COUNTER 0xfc06863c /* * No PMECC Galois table in ROM diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index ea19ec322e8..dfba9f730c1 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -101,17 +101,17 @@ void board_init_f(ulong dummy) at91_pllicpr_init(0x00); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ - at91_plla_init(CONFIG_SYS_AT91_PLLA); + at91_plla_init(CFG_SYS_AT91_PLLA); /* PCK = PLLA = 2 * MCK */ - at91_mck_init(CONFIG_SYS_MCKR); + at91_mck_init(CFG_SYS_MCKR); /* Switch MCK on PLLA output */ - at91_mck_init(CONFIG_SYS_MCKR_CSS); + at91_mck_init(CFG_SYS_MCKR_CSS); -#if defined(CONFIG_SYS_AT91_PLLB) +#if defined(CFG_SYS_AT91_PLLB) /* Configure PLLB */ - at91_pllb_init(CONFIG_SYS_AT91_PLLB); + at91_pllb_init(CFG_SYS_AT91_PLLB); #endif /* Enable External Reset */ @@ -120,7 +120,7 @@ void board_init_f(ulong dummy) /* Initialize matrix */ matrix_init(); - gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; + gd->arch.mck_rate_hz = CFG_SYS_MASTER_CLOCK; /* * init timer long enough for using in spl. */ diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 217ed12e31e..a30c4f6c075 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -124,7 +124,7 @@ void board_init_f(ulong dummy) /* PMC configuration */ at91_pmc_init(); - at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); matrix_init(); diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c index 0f68f9fe59e..dae60262f5b 100644 --- a/arch/arm/mach-davinci/cpu.c +++ b/arch/arm/mach-davinci/cpu.c @@ -42,7 +42,7 @@ int clk_get(enum davinci_clk_ids id) int pll_out; unsigned int pll_base; - pll_out = CONFIG_SYS_OSCIN_FREQ; + pll_out = CFG_SYS_OSCIN_FREQ; if (id == DAVINCI_AUXCLK_CLKID) goto out; diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 2319ac6d563..08c8f592524 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -185,9 +185,9 @@ static int da850_ddr_setup(void) setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); } setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); - writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); + writel(CFG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); - if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) { + if (CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) { /* DDR2 */ clrbits_le32(&davinci_syscfg1_regs->ddr_slew, (1 << DDR_SLEW_DDR_PDENA_BIT) | @@ -211,19 +211,19 @@ static int da850_ddr_setup(void) * At the same time, set the TIMUNLOCK bit to allow changing * the timing registers */ - tmp = CONFIG_SYS_DA850_DDR2_SDBCR; + tmp = CFG_SYS_DA850_DDR2_SDBCR; tmp &= ~DV_DDR_BOOTUNLOCK; tmp |= DV_DDR_TIMUNLOCK; writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); /* write memory configuration and timing */ - if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) { + if (!(CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) { /* MOBILE DDR only*/ - writel(CONFIG_SYS_DA850_DDR2_SDBCR2, + writel(CFG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2); } - writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); - writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); + writel(CFG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); + writel(CFG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); /* clear the TIMUNLOCK bit and write the value of the CL field */ tmp &= ~DV_DDR_TIMUNLOCK; @@ -233,7 +233,7 @@ static int da850_ddr_setup(void) * LPMODEN and MCLKSTOPEN must be set! * Without this bits set, PSC don;t switch states !! */ - writel(CONFIG_SYS_DA850_DDR2_SDRCR | + writel(CFG_SYS_DA850_DDR2_SDRCR | (1 << DV_DDR_SRCR_LPMODEN_SHIFT) | (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT), &dv_ddr2_regs_ctrl->sdrcr); @@ -246,7 +246,7 @@ static int da850_ddr_setup(void) /* disable self refresh */ clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN); - writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); + writel(CFG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); return 0; } @@ -265,7 +265,7 @@ int arch_cpu_init(void) writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); dv_maskbits(&davinci_syscfg_regs->suspsrc, - CONFIG_SYS_DA850_SYSCFG_SUSPSRC); + CFG_SYS_DA850_SYSCFG_SUSPSRC); /* configure pinmux settings */ if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size)) @@ -273,8 +273,8 @@ int arch_cpu_init(void) #if defined(CONFIG_SYS_DA850_PLL_INIT) /* PLL setup */ - da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM); - da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM); + da850_pll_init(davinci_pllc0_regs, CFG_SYS_DA850_PLL0_PLLM); + da850_pll_init(davinci_pllc1_regs, CFG_SYS_DA850_PLL1_PLLM); #endif /* setup CSn config */ #if defined(CONFIG_SYS_DA850_CS2CFG) diff --git a/arch/arm/mach-davinci/timer.c b/arch/arm/mach-davinci/timer.c index 43e0574901e..83c190b620e 100644 --- a/arch/arm/mach-davinci/timer.c +++ b/arch/arm/mach-davinci/timer.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct davinci_timer * const timer = - (struct davinci_timer *)CONFIG_SYS_TIMERBASE; + (struct davinci_timer *)CFG_SYS_TIMERBASE; #define TIMER_LOAD_VAL 0xffffffff @@ -47,7 +47,7 @@ int timer_init(void) writel(0x0, &timer->tim34); writel(TIMER_LOAD_VAL, &timer->prd34); writel(2 << 22, &timer->tcr); - gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV; + gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK / TIM_CLK_DIV; gd->arch.timer_reset_value = 0; return(0); diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c index f5185390571..553dac75b61 100644 --- a/arch/arm/mach-exynos/spl_boot.c +++ b/arch/arm/mach-exynos/spl_boot.c @@ -141,7 +141,7 @@ static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) { int upto, todo; int i, timeout = 100; - struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE; + struct exynos_spi *regs = (struct exynos_spi *)CFG_SYS_SPI_BASE; set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ /* set the spi1 GPIO */ diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 0e767864822..06ee608c4a4 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -248,13 +248,13 @@ unsigned long spl_nor_get_uboot_base(void) int end; /* Calculate the image set end, - * if it is less than CONFIG_SYS_UBOOT_BASE(0x8281000), - * we use CONFIG_SYS_UBOOT_BASE + * if it is less than CFG_SYS_UBOOT_BASE(0x8281000), + * we use CFG_SYS_UBOOT_BASE * Otherwise, use the calculated address */ end = get_imageset_end((void *)NULL, QSPI_NOR_DEV); - if (end <= CONFIG_SYS_UBOOT_BASE) - end = CONFIG_SYS_UBOOT_BASE; + if (end <= CFG_SYS_UBOOT_BASE) + end = CFG_SYS_UBOOT_BASE; else end = ROUND(end, SZ_1K); diff --git a/arch/arm/mach-imx/mx5/lowlevel_init.S b/arch/arm/mach-imx/mx5/lowlevel_init.S index b42cc3e9e43..6ec38dcfa4e 100644 --- a/arch/arm/mach-imx/mx5/lowlevel_init.S +++ b/arch/arm/mach-imx/mx5/lowlevel_init.S @@ -205,7 +205,7 @@ setup_pll_func: /* Switch peripheral to PLL 3 */ ldr r0, =CCM_BASE_ADDR - ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000010C0 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] ldr r1, =0x13239145 str r1, [r0, #CLKCTL_CBCDR] @@ -215,7 +215,7 @@ setup_pll_func: ldr r0, =CCM_BASE_ADDR ldr r1, =0x19239145 str r1, [r0, #CLKCTL_CBCDR] - ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000020C0 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] setup_pll PLL3_BASE_ADDR, 216 @@ -240,10 +240,10 @@ setup_pll_func: /* setup the rest */ /* Use lp_apm (24MHz) source for perclk */ - ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000020C2 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ - ldr r1, =CONFIG_SYS_CLKTL_CBCDR + ldr r1, =CFG_SYS_CLKTL_CBCDR str r1, [r0, #CLKCTL_CBCDR] /* Restore the default values in the Gate registers */ @@ -378,7 +378,7 @@ ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */ -#if defined(CONFIG_SYS_MAIN_PWR_ON) +#if defined(CFG_SYS_MAIN_PWR_ON) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #1 << 23 diff --git a/arch/arm/mach-k3/config_secure.mk b/arch/arm/mach-k3/config_secure.mk index 9cc1f9eb24f..7bc8af813a6 100644 --- a/arch/arm/mach-k3/config_secure.mk +++ b/arch/arm/mach-k3/config_secure.mk @@ -30,7 +30,7 @@ tispl.bin_HS: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst %,$(obj)/dts/%.dtb_HS,$( $(call if_changed,mkfitimage) MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST))) diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c index 4734e4c7143..dc97bac8550 100644 --- a/arch/arm/mach-keystone/cmd_mon.c +++ b/arch/arm/mach-keystone/cmd_mon.c @@ -23,7 +23,7 @@ static int do_mon_install(struct cmd_tbl *cmdtp, int flag, int argc, if (argc < 2) return CMD_RET_USAGE; - freq = CONFIG_SYS_HZ_CLOCK; + freq = CFG_SYS_HZ_CLOCK; addr = hextoul(argv[1], NULL); diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index 98a8f058df4..424c32a4bee 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -263,7 +263,7 @@ typedef volatile unsigned int *dv_reg_p; /* MSMC segment size shift bits */ #define KS2_MSMC_SEG_SIZE_SHIFT 12 #define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT)) -#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \ +#define KS2_MSMC_DST_SEG_BASE (CFG_SYS_LPAE_SDRAM_BASE >> \ KS2_MSMC_SEG_SIZE_SHIFT) /* Device speed */ diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index 5186f6e4f9a..a2781e25a23 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -52,8 +52,8 @@ /* Use common timer */ #ifndef CONFIG_TIMER -#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) -#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK +#define CFG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) +#define CFG_SYS_TIMER_RATE CFG_SYS_TCLK #endif #endif /* _KW_CONFIG_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h index c44eacfc1b9..d3a3a836576 100644 --- a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h @@ -15,6 +15,6 @@ #define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE /* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ +#define CFG_SYS_TCLK 166000000 /* 166MHz */ #endif /* _CONFIG_KW88F6192_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h index f86cd0bb601..7f8e156a6bd 100644 --- a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h @@ -15,7 +15,7 @@ #define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE /* TCLK Core Clock definition */ -#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \ +#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \ 166666667 : 200000000) #endif /* _ASM_ARCH_KW88F6281_H */ diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 1f8cdf8744e..67ad5e5907b 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -659,7 +659,7 @@ void enable_caches(void) void v7_outer_cache_enable(void) { struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; /* The L2 cache is already disabled at this point */ @@ -691,7 +691,7 @@ void v7_outer_cache_enable(void) void v7_outer_cache_disable(void) { struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 3b9618852c6..e6383d4a86e 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -54,7 +54,7 @@ #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) -#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE +#define CFG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) #define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100)) #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) @@ -146,7 +146,7 @@ #define BOOT_FROM_UART 0x30 #define BOOT_FROM_SPI 0x38 -#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ +#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ 200000000 : 166000000) #elif defined(CONFIG_ARMADA_38X) /* SAR values for Armada 38x */ @@ -169,7 +169,7 @@ #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31 -#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ +#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ 200000000 : 250000000) #elif defined(CONFIG_ARMADA_MSYS) /* SAR values for MSYS */ @@ -188,7 +188,7 @@ #define BOOT_FROM_UART 0x2 #define BOOT_FROM_SPI 0x3 -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ +#define CFG_SYS_TCLK 200000000 /* 200MHz */ #elif defined(CONFIG_ARMADA_XP) /* SAR values for Armada XP */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) @@ -209,7 +209,7 @@ #define BOOT_FROM_UART 0x2 #define BOOT_FROM_SPI 0x3 -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ +#define CFG_SYS_TCLK 250000000 /* 250MHz */ #endif #endif /* _MVEBU_SOC_H */ diff --git a/arch/arm/mach-mvebu/lowlevel.S b/arch/arm/mach-mvebu/lowlevel.S index 60c2072c354..6c9783aa63f 100644 --- a/arch/arm/mach-mvebu/lowlevel.S +++ b/arch/arm/mach-mvebu/lowlevel.S @@ -35,10 +35,10 @@ ENTRY(arch_very_early_init) * Disable L2 cache * * NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG - * but CONFIG_SYS_PL310_BASE is already calculated from base + * but CFG_SYS_PL310_BASE is already calculated from base * address SOC_REGS_PHY_BASE. */ - ldr r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG) + ldr r1, =(CFG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG) ldr r0, [r1, #L2X0_CTRL_OFF] bic r0, #L2X0_CTRL_EN str r0, [r1, #L2X0_CTRL_OFF] diff --git a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c index cba2e342dc2..ed4b1ca5c98 100644 --- a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c +++ b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c @@ -11,7 +11,7 @@ void l2_pl310_init(void); void set_pl310_ctrl(u32 enable) { - struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; writel(enable, &pl310->pl310_ctrl); } diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk index f76262bb0ce..24ddcdb9614 100644 --- a/arch/arm/mach-omap2/config_secure.mk +++ b/arch/arm/mach-omap2/config_secure.mk @@ -102,7 +102,7 @@ u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin FORCE ifdef CONFIG_SPL_LOAD_FIT MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST))) diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c index 803dc7fb71d..19197482aa4 100644 --- a/arch/arm/mach-omap2/mem-common.c +++ b/arch/arm/mach-omap2/mem-common.c @@ -124,11 +124,11 @@ void set_gpmc_cs0(int flash_type) #if defined(CONFIG_NOR) case MTD_DEV_TYPE_NOR: gpmc_regs = gpmc_regs_nor; - base = CONFIG_SYS_FLASH_BASE; - size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : - ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : - ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : - ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : + base = CFG_SYS_FLASH_BASE; + size = (CFG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : + ((CFG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : + ((CFG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : + ((CFG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : GPMC_SIZE_16M))); break; #endif @@ -142,7 +142,7 @@ void set_gpmc_cs0(int flash_type) #if defined(CONFIG_CMD_ONENAND) case MTD_DEV_TYPE_ONENAND: gpmc_regs = gpmc_regs_onenand; - base = CONFIG_SYS_ONENAND_BASE; + base = CFG_SYS_ONENAND_BASE; size = GPMC_SIZE_128M; break; #endif diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 00d91c10136..71fdf5bf487 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; -static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; +static struct gptimer *timer_base = (struct gptimer *)CFG_SYS_TIMERBASE; static ulong get_timer_masked(void); /* diff --git a/arch/arm/mach-orion5x/include/mach/mv88f5182.h b/arch/arm/mach-orion5x/include/mach/mv88f5182.h index 0e9fe0dc51a..ee0aa94bf2c 100644 --- a/arch/arm/mach-orion5x/include/mach/mv88f5182.h +++ b/arch/arm/mach-orion5x/include/mach/mv88f5182.h @@ -18,6 +18,6 @@ #define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE /* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ +#define CFG_SYS_TCLK 166000000 /* 166MHz */ #endif /* _CONFIG_88F5182_H */ diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c index d7ea2e3943f..b373e59e6fe 100644 --- a/arch/arm/mach-orion5x/timer.c +++ b/arch/arm/mach-orion5x/timer.c @@ -74,7 +74,7 @@ struct orion5x_tmr_registers *orion5x_tmr_regs = static inline ulong read_timer(void) { return readl(CNTMR_VAL_REG(UBOOT_CNTR)) - / (CONFIG_SYS_TCLK / 1000); + / (CFG_SYS_TCLK / 1000); } DECLARE_GLOBAL_DATA_PTR; @@ -92,7 +92,7 @@ static ulong get_timer_masked(void) } else { /* we have an overflow ... */ timestamp += lastdec + - (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; + (TIMER_LOAD_VAL / (CFG_SYS_TCLK / 1000)) - now; } lastdec = now; @@ -115,7 +115,7 @@ void __udelay(unsigned long usec) ulong delayticks; current = uboot_cntr_val(); - delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); + delayticks = (usec * (CFG_SYS_TCLK / 1000000)); if (current < delayticks) { delayticks -= current; diff --git a/arch/arm/mach-rmobile/include/mach/r8a7790.h b/arch/arm/mach-rmobile/include/mach/r8a7790.h index 28669e3c771..485ea7e28d1 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7790.h @@ -24,7 +24,7 @@ #define MSTP11_BITS 0x00000000 /* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 4 #define R8A7790_CUT_ES2X 2 #define IS_R8A7790_ES2() \ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7791.h b/arch/arm/mach-rmobile/include/mach/r8a7791.h index 37d134c5bf2..2006ad58a52 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7791.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7791.h @@ -14,7 +14,7 @@ */ /* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 3 #define DBSC3_1_QOS_R0_BASE 0xE67A1000 #define DBSC3_1_QOS_R1_BASE 0xE67A1100 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792.h b/arch/arm/mach-rmobile/include/mach/r8a7792.h index 06db64af6cf..cc1b00db33f 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7792.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7792.h @@ -24,6 +24,6 @@ #define MSTP11_BITS 0x00000008 /* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 1 #endif /* __ASM_ARCH_R8A7792_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7793.h b/arch/arm/mach-rmobile/include/mach/r8a7793.h index 85f59d97712..02f4286ef1a 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7793.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7793.h @@ -15,7 +15,7 @@ */ /* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 3 #define DBSC3_1_QOS_R0_BASE 0xE67A1000 #define DBSC3_1_QOS_R1_BASE 0xE67A1100 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7794.h b/arch/arm/mach-rmobile/include/mach/r8a7794.h index 2bd6e469c81..a2a949d4d61 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7794.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7794.h @@ -24,7 +24,7 @@ #define MSTP11_BITS 0x000001C0 /* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 3 #define R8A7794_CUT_ES2 2 #define IS_R8A7794_ES2() \ diff --git a/arch/arm/mach-rmobile/timer.c b/arch/arm/mach-rmobile/timer.c index ba06535e4c2..293c23b5e25 100644 --- a/arch/arm/mach-rmobile/timer.c +++ b/arch/arm/mach-rmobile/timer.c @@ -40,8 +40,8 @@ static u64 get_time_us(void) { u64 timer = get_cpu_global_timer(); - timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1)); - do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK)); + timer = ((timer << 2) + (CLK2MHZ(CFG_SYS_CPU_CLK) >> 1)); + do_div(timer, CLK2MHZ(CFG_SYS_CPU_CLK)); return timer; } @@ -65,7 +65,7 @@ void __udelay(unsigned long usec) u64 wait; start = get_cpu_global_timer(); - wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2); + wait = (u64)((usec * CLK2MHZ(CFG_SYS_CPU_CLK)) >> 2); do { current = get_cpu_global_timer(); } while ((current - start) < wait); @@ -83,5 +83,5 @@ unsigned long long get_ticks(void) ulong get_tbclk(void) { - return (ulong)(CONFIG_SYS_CPU_CLK >> 2); + return (ulong)(CFG_SYS_CPU_CLK >> 2); } diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 9c19157de71..5b5a81a255d 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -34,7 +34,7 @@ phys_addr_t socfpga_sysmgr_base __section(".data"); #ifdef CONFIG_SYS_L2_PL310 static const struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; #endif struct bsel bsel_str[] = { diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 7ce888d1979..93c9e8b0fb4 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -60,7 +60,7 @@ static Altera_desc altera_fpga[] = { #if defined(CONFIG_SPL_BUILD) static struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; @@ -256,7 +256,7 @@ void dram_bank_mmu_setup(int bank) /* If we're still in OCRAM, don't set the XN bit on it */ if (!(gd->flags & GD_FLG_RELOC)) { set_section_dcache( - CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT, + CFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT, DCACHE_WRITETHROUGH); } diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 4edf4f9b5c1..e7500c16f72 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; static struct scu_registers *scu_regs = diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 2c567edd502..9edbbf4a29c 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; #define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */ -#define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ +#define BOOTROM_SHARED_MEM_ADDR (CFG_SYS_INIT_RAM_ADDR + \ SOCFPGA_PHYS_OCRAM_SIZE - \ BOOTROM_SHARED_MEM_SIZE) #define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438) diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c index a58f1cf9d3a..d9e8c84bfcf 100644 --- a/arch/arm/mach-socfpga/timer.c +++ b/arch/arm/mach-socfpga/timer.c @@ -10,7 +10,7 @@ #define TIMER_LOAD_VAL 0xFFFFFFFF -static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; +static const struct socfpga_timer *timer_base = (void *)CFG_SYS_TIMERBASE; /* * Timer initialization diff --git a/arch/arm/mach-u8500/cache.c b/arch/arm/mach-u8500/cache.c index f9fd4fe7d33..05a91346a89 100644 --- a/arch/arm/mach-u8500/cache.c +++ b/arch/arm/mach-u8500/cache.c @@ -22,7 +22,7 @@ void enable_caches(void) #ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_disable(void) { - struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; /* * Linux expects the L2 cache to be turned off by the bootloader. diff --git a/arch/arm/mach-uniphier/arm32/timer.c b/arch/arm/mach-uniphier/arm32/timer.c index a40bdf17055..58247c2738a 100644 --- a/arch/arm/mach-uniphier/arm32/timer.c +++ b/arch/arm/mach-uniphier/arm32/timer.c @@ -10,7 +10,7 @@ #include "arm-mpcore.h" #define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */ -#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1) +#define PRESCALER ((PERIPHCLK) / (CFG_SYS_TIMER_RATE) - 1) static void *get_global_timer_base(void) { diff --git a/arch/arm/mach-versatile/timer.c b/arch/arm/mach-versatile/timer.c index 739cb2997ad..b471412186d 100644 --- a/arch/arm/mach-versatile/timer.c +++ b/arch/arm/mach-versatile/timer.c @@ -36,9 +36,9 @@ int timer_init (void) ulong tmr_ctrl_val; /* 1st disable the Timer */ - tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); + tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); tmr_ctrl_val &= ~TIMER_ENABLE; - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; /* * The Timer Control Register has one Undefined/Shouldn't Use Bit @@ -52,11 +52,11 @@ int timer_init (void) * Tmr Siz : 16 Bit Counter * Tmr in Wrapping Mode */ - tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); + tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S); - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; return 0; } diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c index e44656db5f2..6d87908965d 100644 --- a/arch/m68k/cpu/mcf523x/cpu.c +++ b/arch/m68k/cpu/mcf523x/cpu.c @@ -92,7 +92,7 @@ int watchdog_init(void) u32 wdog_module = 0; /* set timeout and enable watchdog */ - wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT); wdog_module |= (wdog_module / 8192); out_be16(&wdp->mr, wdog_module); diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c index 87effa71dc3..10be73822fa 100644 --- a/arch/m68k/cpu/mcf523x/cpu_init.c +++ b/arch/m68k/cpu/mcf523x/cpu_init.c @@ -47,36 +47,36 @@ void cpu_init_f(void) out_be16(&wdog->cr, 0); #endif - out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); + out_be32(&scm->rambar, CFG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); /* Port configuration */ out_8(&gpio->par_cs, 0); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL)) + out_be_fbcs_reg(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be_fbcs_reg(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1); - out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be_fbcs_reg(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be_fbcs_reg(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2); - out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); + out_be_fbcs_reg(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be_fbcs_reg(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3); - out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); + out_be_fbcs_reg(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be_fbcs_reg(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) @@ -108,8 +108,8 @@ void cpu_init_f(void) #endif #ifdef CONFIG_SYS_I2C_FSL - CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; + CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR; + CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET; #endif icache_enable(); diff --git a/arch/m68k/cpu/mcf523x/speed.c b/arch/m68k/cpu/mcf523x/speed.c index f41f977d7f5..6b08a12af0b 100644 --- a/arch/m68k/cpu/mcf523x/speed.c +++ b/arch/m68k/cpu/mcf523x/speed.c @@ -29,7 +29,7 @@ int get_clocks(void) while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK)) ; - gd->bus_clk = CONFIG_SYS_CLK; + gd->bus_clk = CFG_SYS_CLK; gd->cpu_clk = (gd->bus_clk * 2); #ifdef CONFIG_SYS_I2C_FSL diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S index 4c9c96d7831..d2a21c3279b 100644 --- a/arch/m68k/cpu/mcf523x/start.S +++ b/arch/m68k/cpu/mcf523x/start.S @@ -91,10 +91,10 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* invalidate and disable cache */ @@ -116,7 +116,7 @@ _start: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c index 8f72ef567fe..d21d82fef75 100644 --- a/arch/m68k/cpu/mcf52x2/cpu.c +++ b/arch/m68k/cpu/mcf52x2/cpu.c @@ -132,11 +132,11 @@ int print_cpuinfo(void) if (cpu_model) printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", - cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK)); + cpu_model, prn, strmhz(buf, CFG_SYS_CLK)); else printf("CPU: Unknown - Freescale ColdFire MCF5271 family" " (PIN: 0x%x) rev. %hu, at %s MHz\n", - pin, prn, strmhz(buf, CONFIG_SYS_CLK)); + pin, prn, strmhz(buf, CFG_SYS_CLK)); return 0; } @@ -284,7 +284,7 @@ int print_cpuinfo(void) char buf[32]; printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CLK)); + strmhz(buf, CFG_SYS_CLK)); return 0; }; #endif /* CONFIG_DISPLAY_CPUINFO */ @@ -370,7 +370,7 @@ int print_cpuinfo(void) char buf[32]; printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CLK)); + strmhz(buf, CFG_SYS_CLK)); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ @@ -394,7 +394,7 @@ int print_cpuinfo(void) unsigned char resetsource = mbar_readLong(SIM_RSR); printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CLK)); + strmhz(buf, CFG_SYS_CLK)); if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { printf("Reset:%s%s\n", diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c index 9d4a10f028d..99eb61f1675 100644 --- a/arch/m68k/cpu/mcf52x2/cpu_init.c +++ b/arch/m68k/cpu/mcf52x2/cpu_init.c @@ -36,31 +36,31 @@ void init_fbcs(void) { fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \ + && defined(CFG_SYS_CS0_CTRL)) + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #else #warning "Chip Select 0 are not initialized/used" #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \ + && defined(CFG_SYS_CS1_CTRL)) + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \ + && defined(CFG_SYS_CS2_CTRL)) + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \ + && defined(CFG_SYS_CS3_CTRL)) + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ && defined(CONFIG_SYS_CS4_CTRL)) @@ -214,9 +214,9 @@ void cpu_init_f(void) init_fbcs(); #ifdef CONFIG_SYS_I2C_FSL - CONFIG_SYS_I2C_PINMUX_REG = - CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; + CFG_SYS_I2C_PINMUX_REG = + CFG_SYS_I2C_PINMUX_REG & CFG_SYS_I2C_PINMUX_CLR; + CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET; #ifdef CONFIG_SYS_I2C2_OFFSET CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR; CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET; @@ -335,21 +335,21 @@ void cpu_init_f(void) * already initialized. */ #ifndef CONFIG_MONITOR_IS_IN_RAM - sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); + sysctrl_t *sysctrl = (sysctrl_t *) (CFG_SYS_MBAR); gpio_t *gpio = (gpio_t *) (MMAP_GPIO); csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); - out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR); - out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR); + out_be16(&sysctrl->sc_scr, CFG_SYS_SCR); + out_be16(&sysctrl->sc_spr, CFG_SYS_SPR); /* Setup Ports: */ - out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT); - out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR); - out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT); - out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT); - out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR); - out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT); - out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT); + out_be32(&gpio->gpio_pacnt, CFG_SYS_PACNT); + out_be16(&gpio->gpio_paddr, CFG_SYS_PADDR); + out_be16(&gpio->gpio_padat, CFG_SYS_PADAT); + out_be32(&gpio->gpio_pbcnt, CFG_SYS_PBCNT); + out_be16(&gpio->gpio_pbddr, CFG_SYS_PBDDR); + out_be16(&gpio->gpio_pbdat, CFG_SYS_PBDAT); + out_be32(&gpio->gpio_pdcnt, CFG_SYS_PDCNT); /* Memory Controller: */ out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM); @@ -472,8 +472,8 @@ void cpu_init_f(void) #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ #ifdef CONFIG_SYS_I2C_FSL - CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; + CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR; + CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET; #endif /* enable instruction cache now */ @@ -560,8 +560,8 @@ void cpu_init_f(void) #ifndef CONFIG_MONITOR_IS_IN_RAM /* Set speed /PLL */ MCFCLOCK_SYNCR = - MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | - MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD); + MCFCLOCK_SYNCR_MFD(CFG_SYS_MFD) | + MCFCLOCK_SYNCR_RFD(CFG_SYS_RFD); while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; MCFGPIO_PBCDPAR = 0xc0; @@ -573,17 +573,17 @@ void cpu_init_f(void) #ifdef CONFIG_SYS_PFPAR MCFGPIO_PFPAR = CONFIG_SYS_PFPAR; #endif -#ifdef CONFIG_SYS_PJPAR - MCFGPIO_PJPAR = CONFIG_SYS_PJPAR; +#ifdef CFG_SYS_PJPAR + MCFGPIO_PJPAR = CFG_SYS_PJPAR; #endif #ifdef CONFIG_SYS_PSDPAR MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR; #endif -#ifdef CONFIG_SYS_PASPAR - MCFGPIO_PASPAR = CONFIG_SYS_PASPAR; +#ifdef CFG_SYS_PASPAR + MCFGPIO_PASPAR = CFG_SYS_PASPAR; #endif -#ifdef CONFIG_SYS_PEHLPAR - MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; +#ifdef CFG_SYS_PEHLPAR + MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR; #endif #ifdef CONFIG_SYS_PQSPAR MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR; @@ -600,15 +600,15 @@ void cpu_init_f(void) #ifdef CONFIG_SYS_PTDPAR MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; #endif -#ifdef CONFIG_SYS_PUAPAR - MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR; +#ifdef CFG_SYS_PUAPAR + MCFGPIO_PUAPAR = CFG_SYS_PUAPAR; #endif #if defined(CONFIG_SYS_DDRD) MCFGPIO_DDRD = CONFIG_SYS_DDRD; #endif -#ifdef CONFIG_SYS_DDRUA - MCFGPIO_DDRUA = CONFIG_SYS_DDRUA; +#ifdef CFG_SYS_DDRUA + MCFGPIO_DDRUA = CFG_SYS_DDRUA; #endif /* FlexBus Chipselect */ @@ -652,10 +652,10 @@ int fecpin_setclear(fec_info_t *info, int setclear) { if (setclear) { MCFGPIO_PASPAR |= 0x0F00; - MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; + MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR; } else { MCFGPIO_PASPAR &= 0xF0FF; - MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR; + MCFGPIO_PEHLPAR &= ~CFG_SYS_PEHLPAR; } return 0; } @@ -678,12 +678,12 @@ void cpu_init_f(void) * which is their primary function. * ~Jeremy */ - mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC); - mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC); - mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN); - mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN); - mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT); - mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT); + mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_SYS_GPIO_FUNC); + mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_SYS_GPIO1_FUNC); + mbar2_writeLong(MCFSIM_GPIO_EN, CFG_SYS_GPIO_EN); + mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_SYS_GPIO1_EN); + mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_SYS_GPIO_OUT); + mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_SYS_GPIO1_OUT); /* * dBug Compliance: diff --git a/arch/m68k/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c index 045908a13d4..6c7628252b5 100644 --- a/arch/m68k/cpu/mcf52x2/speed.c +++ b/arch/m68k/cpu/mcf52x2/speed.c @@ -23,19 +23,19 @@ int get_clocks(void) #if defined(CONFIG_M5208) pll_t *pll = (pll_t *) MMAP_PLL; - out_8(&pll->odr, CONFIG_SYS_PLL_ODR); - out_8(&pll->fdr, CONFIG_SYS_PLL_FDR); + out_8(&pll->odr, CFG_SYS_PLL_ODR); + out_8(&pll->fdr, CFG_SYS_PLL_FDR); #endif #if defined(CONFIG_M5249) || defined(CONFIG_M5253) volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); unsigned long pllcr; -#ifndef CONFIG_SYS_PLL_BYPASS +#ifndef CFG_SYS_PLL_BYPASS #ifdef CONFIG_M5249 /* Setup the PLL to run at the specified speed */ -#ifdef CONFIG_SYS_FAST_CLK +#ifdef CFG_SYS_FAST_CLK pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ #else pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ @@ -43,7 +43,7 @@ int get_clocks(void) #endif /* CONFIG_M5249 */ #ifdef CONFIG_M5253 - pllcr = CONFIG_SYS_PLLCR; + pllcr = CFG_SYS_PLLCR; #endif /* CONFIG_M5253 */ cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ @@ -52,7 +52,7 @@ int get_clocks(void) pllcr ^= 0x00000001; /* Set pll bypass to 1 */ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ udelay(0x20); /* Wait for a lock ... */ -#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */ +#endif /* #ifndef CFG_SYS_PLL_BYPASS */ #endif /* CONFIG_M5249 || CONFIG_M5253 */ @@ -68,7 +68,7 @@ int get_clocks(void) ; #endif - gd->cpu_clk = CONFIG_SYS_CLK; + gd->cpu_clk = CFG_SYS_CLK; #if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ defined(CONFIG_M5271) || defined(CONFIG_M5275) gd->bus_clk = gd->cpu_clk / 2; diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S index 6dddbe76f3a..d48d0192eea 100644 --- a/arch/m68k/cpu/mcf52x2/start.S +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -35,7 +35,7 @@ */ _vectors: .long 0x00000000 /* Flash offset is 0 until we setup CS0 */ -#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) .long _start - CONFIG_TEXT_BASE #else .long _START @@ -81,9 +81,9 @@ _vectors: .text -#if defined(CONFIG_SYS_INT_FLASH_BASE) && \ +#if defined(CFG_SYS_INT_FLASH_BASE) && \ (defined(CONFIG_M5282) || defined(CONFIG_M5281)) -#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */ .long 0xFFFFFFFF /* all sectors protected */ .long 0x00000000 /* supervisor/User restriction */ @@ -100,53 +100,53 @@ _start: #if defined(CONFIG_M5208) /* Initialize RAMBAR: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 #endif #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253) /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.c %d0, %MBAR /*** The 5249 has MBAR2 as well ***/ -#ifdef CONFIG_SYS_MBAR2 +#ifdef CFG_SYS_MBAR2 /* Get MBAR2 address */ - move.l #(CONFIG_SYS_MBAR2 + 1), %d0 + move.l #(CFG_SYS_MBAR2 + 1), %d0 /* Set MBAR2 */ movec %d0, #0xc0e #endif - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0 movec %d0, %RAMBAR0 #endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */ #if defined(CONFIG_M5282) || defined(CONFIG_M5271) /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.l %d0, 0x40000000 /* Initialize RAMBAR1: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1 #if defined(CONFIG_M5282) -#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) /* * Setup code in SRAM to initialize FLASHBAR, * if start from internal Flash */ - move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0 - move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2 + move.l #(_flashbar_setup-CFG_SYS_INT_FLASH_BASE), %a0 + move.l #(_flashbar_setup_end-CFG_SYS_INT_FLASH_BASE), %a1 + move.l #(CFG_SYS_INIT_RAM_ADDR), %a2 _copy_flash: move.l (%a0)+, (%a2)+ cmp.l %a0, %a1 bgt.s _copy_flash - jmp CONFIG_SYS_INIT_RAM_ADDR + jmp CFG_SYS_INIT_RAM_ADDR _flashbar_setup: /* Initialize FLASHBAR: locate internal Flash and validate it */ - move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 + move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0 movec %d0, %FLASHBAR jmp _after_flashbar_copy.L /* Force jump to absolute address */ _flashbar_setup_end: @@ -154,9 +154,9 @@ _flashbar_setup_end: _after_flashbar_copy: #else /* Setup code to initialize FLASHBAR, if start from external Memory */ - move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 + move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0 movec %d0, %FLASHBAR -#endif /* (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */ +#endif /* (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) */ #endif #endif @@ -165,22 +165,22 @@ _after_flashbar_copy: * therefore no VBR to set */ #if !defined(CONFIG_MONITOR_IS_IN_RAM) -#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) - move.l #CONFIG_SYS_INT_FLASH_BASE, %d0 +#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) + move.l #CFG_SYS_INT_FLASH_BASE, %d0 #else - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 #endif movec %d0, %VBR #endif #ifdef CONFIG_M5275 /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.l %d0, 0x40000000 /* movec %d0, %MBAR */ /* Initialize RAMBAR: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1 #endif @@ -195,7 +195,7 @@ _after_flashbar_copy: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c index 0659bf65581..53a25d8362c 100644 --- a/arch/m68k/cpu/mcf530x/cpu.c +++ b/arch/m68k/cpu/mcf530x/cpu.c @@ -33,7 +33,7 @@ int print_cpuinfo(void) char buf[32]; printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CPU_CLK)); + strmhz(buf, CFG_SYS_CPU_CLK)); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c index 83529408eb3..dad47d87ab3 100644 --- a/arch/m68k/cpu/mcf530x/cpu_init.c +++ b/arch/m68k/cpu/mcf530x/cpu_init.c @@ -40,35 +40,35 @@ void init_csm(void) { csm_t *csm = (csm_t *)(MMAP_CSM); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \ - defined(CONFIG_SYS_CS0_CTRL)) - out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK); - out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && \ + defined(CFG_SYS_CS0_CTRL)) + out_be16(&csm->csar0, CFG_SYS_CS0_BASE); + out_be32(&csm->csmr0, CFG_SYS_CS0_MASK); + out_be16(&csm->cscr0, CFG_SYS_CS0_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS0_BASE, csm->csmr0); #else #warning "Chip Select 0 are not initialized/used" #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \ - defined(CONFIG_SYS_CS1_CTRL)) - out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK); - out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1); +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && \ + defined(CFG_SYS_CS1_CTRL)) + out_be16(&csm->csar1, CFG_SYS_CS1_BASE); + out_be32(&csm->csmr1, CFG_SYS_CS1_MASK); + out_be16(&csm->cscr1, CFG_SYS_CS1_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS1_BASE, csm->csmr1); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \ - defined(CONFIG_SYS_CS2_CTRL)) - out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK); - out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && \ + defined(CFG_SYS_CS2_CTRL)) + out_be16(&csm->csar2, CFG_SYS_CS2_BASE); + out_be32(&csm->csmr2, CFG_SYS_CS2_MASK); + out_be16(&csm->cscr2, CFG_SYS_CS2_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS2_BASE, csm->csmr2); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \ - defined(CONFIG_SYS_CS3_CTRL)) - out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK); - out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && \ + defined(CFG_SYS_CS3_CTRL)) + out_be16(&csm->csar3, CFG_SYS_CS3_BASE); + out_be32(&csm->csmr3, CFG_SYS_CS3_MASK); + out_be16(&csm->cscr3, CFG_SYS_CS3_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS3_BASE, csm->csmr3); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \ defined(CONFIG_SYS_CS4_CTRL)) diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c index 03d9abeb182..c8d079016f2 100644 --- a/arch/m68k/cpu/mcf530x/speed.c +++ b/arch/m68k/cpu/mcf530x/speed.c @@ -16,8 +16,8 @@ DECLARE_GLOBAL_DATA_PTR; int get_clocks(void) { #if defined(CONFIG_M5307) - gd->bus_clk = CONFIG_SYS_CLK; - gd->cpu_clk = CONFIG_SYS_CPU_CLK; + gd->bus_clk = CFG_SYS_CLK; + gd->cpu_clk = CFG_SYS_CPU_CLK; #endif return 0; diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S index 644c372bdd2..dbe2b54e410 100644 --- a/arch/m68k/cpu/mcf530x/start.S +++ b/arch/m68k/cpu/mcf530x/start.S @@ -39,7 +39,7 @@ _vectors: /* Flash offset is 0 until we setup CS0 */ .long 0x00000000 #if defined(CONFIG_M5307) && \ - (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) + (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) .long _start - CONFIG_TEXT_BASE #else .long _START @@ -92,10 +92,10 @@ _start: move.w #0x2700,%sr /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.c %d0, %MBAR - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0 move.c %d0, %RAMBAR /* DS 4.8.2 (Cache Organization) invalidate and disable cache */ @@ -110,7 +110,7 @@ _start: * therefore no VBR to set */ #if !defined(CONFIG_MONITOR_IS_IN_RAM) - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR #endif @@ -125,7 +125,7 @@ _start: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c index 1dadffd4ca3..8a48d73475c 100644 --- a/arch/m68k/cpu/mcf532x/cpu.c +++ b/arch/m68k/cpu/mcf532x/cpu.c @@ -131,7 +131,7 @@ int watchdog_init(void) u32 wdog_module = 0; /* set timeout and enable watchdog */ - wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module = ((CFG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); #ifdef CONFIG_M5329 out_be16(&wdp->mr, wdog_module / 8192); #else diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c index 1311f3967c9..844d2cd7600 100644 --- a/arch/m68k/cpu/mcf532x/cpu_init.c +++ b/arch/m68k/cpu/mcf532x/cpu_init.c @@ -37,34 +37,34 @@ void cpu_init_f(void) out_be32(&scm1->pacrf, 0); out_be32(&scm1->pacrg, 0); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \ + && defined(CFG_SYS_CS0_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0); - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \ + && defined(CFG_SYS_CS1_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1); - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \ + && defined(CFG_SYS_CS2_CTRL)) + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \ + && defined(CFG_SYS_CS3_CTRL)) + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ @@ -102,8 +102,8 @@ int cpu_init_r(void) rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); rtcex_t *rtcex = (rtcex_t *) &rtc->extended; - out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT); - out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP); + out_be32(&rtcex->gocu, CFG_SYS_RTC_CNT); + out_be32(&rtcex->gocl, CFG_SYS_RTC_SETUP); #endif #ifdef CONFIG_MCFFEC @@ -236,36 +236,36 @@ void cpu_init_f(void) /* Port configuration */ out_8(&gpio->par_cs, 0); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \ + && defined(CFG_SYS_CS0_CTRL)) + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \ + && defined(CFG_SYS_CS1_CTRL)) /* Latch chipselect */ setbits_8(&gpio->par_cs, GPIO_PAR_CS1); - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \ + && defined(CFG_SYS_CS2_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS2); - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \ + && defined(CFG_SYS_CS3_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS3); - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ @@ -327,7 +327,7 @@ void uart_port_conf(int port) clrbits_8(&gpio->par_feci2c, 0x00ff); setbits_8(&gpio->par_feci2c, GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); -#elif defined(CONFIG_SYS_UART2_ALT3_GPIO) +#elif defined(CFG_SYS_UART2_ALT3_GPIO) clrbits_be16(&gpio->par_ssi, 0x0f00); setbits_be16(&gpio->par_ssi, GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c index dac2229f72e..32ffac08135 100644 --- a/arch/m68k/cpu/mcf532x/speed.c +++ b/arch/m68k/cpu/mcf532x/speed.c @@ -252,7 +252,7 @@ int clock_pll(int fsys, int flags) /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ int get_clocks(void) { - gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000; + gd->bus_clk = clock_pll(CFG_SYS_CLK / 1000, 0) * 1000; gd->cpu_clk = (gd->bus_clk * 3); #ifdef CONFIG_SYS_I2C_FSL diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S index 26728919160..72a2f99b7dd 100644 --- a/arch/m68k/cpu/mcf532x/start.S +++ b/arch/m68k/cpu/mcf532x/start.S @@ -98,11 +98,11 @@ _start: #if !defined(CONFIG_MONITOR_IS_IN_RAM) /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR #endif - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* invalidate and disable cache */ @@ -131,7 +131,7 @@ _start: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index 9b3f9f0fe13..1ce244872f1 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -29,30 +29,30 @@ void init_fbcs(void) fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS; #if !defined(CONFIG_SERIAL_BOOT) -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL)) + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL)) /* Latch chipselect */ - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL)) + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL)) + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) @@ -208,14 +208,14 @@ void cpu_init_f(void) /* FlexBus Chipselect */ init_fbcs(); -#ifdef CONFIG_SYS_CS0_BASE +#ifdef CFG_SYS_CS0_BASE /* * now the flash base address is no longer at 0 (Newer ColdFire family * boot at address 0 instead of 0xFFnn_nnnn). The vector table must * also move to the new location. */ - if (CONFIG_SYS_CS0_BASE != 0) - setvbr(CONFIG_SYS_CS0_BASE); + if (CFG_SYS_CS0_BASE != 0) + setvbr(CFG_SYS_CS0_BASE); #endif icache_enable(); diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index aea8f3090fe..a083c3d45d2 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -27,10 +27,10 @@ #if defined(CONFIG_SERIAL_BOOT) #define ASM_DRAMINIT (asm_dram_init - CONFIG_TEXT_BASE + \ - CONFIG_SYS_INIT_RAM_ADDR) + CFG_SYS_INIT_RAM_ADDR) #define ASM_DRAMINIT_N (asm_dram_init - CONFIG_TEXT_BASE) #define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_TEXT_BASE + \ - CONFIG_SYS_INIT_RAM_ADDR) + CFG_SYS_INIT_RAM_ADDR) #endif .text @@ -123,18 +123,18 @@ asm_dram_init: #ifdef CONFIG_SYS_NAND_BOOT /* for assembly stack */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- #endif #ifdef CONFIG_CF_SBF - move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0 + move.l #CFG_SYS_INIT_RAM_ADDR, %d0 movec %d0, %VBR - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* initialize general use internal ram */ @@ -145,7 +145,7 @@ asm_dram_init: move.l %d0, (%a2) /* invalidate and disable cache */ - move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 + move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0 movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -153,17 +153,17 @@ asm_dram_init: movec %d0, %ACR2 movec %d0, %ACR3 - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- -#ifdef CONFIG_SYS_CS0_BASE +#ifdef CFG_SYS_CS0_BASE /* Must disable global address */ move.l #0xFC008000, %a1 - move.l #(CONFIG_SYS_CS0_BASE), (%a1) + move.l #(CFG_SYS_CS0_BASE), (%a1) move.l #0xFC008008, %a1 - move.l #(CONFIG_SYS_CS0_CTRL), (%a1) + move.l #(CFG_SYS_CS0_CTRL), (%a1) move.l #0xFC008004, %a1 - move.l #(CONFIG_SYS_CS0_MASK), (%a1) + move.l #(CFG_SYS_CS0_MASK), (%a1) #endif #endif /* CONFIG_CF_SBF */ @@ -216,8 +216,8 @@ asm_dspi_init: move.l (%a1)+, %d5 move.l (%a1), %a4 - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0 - move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_SBFHDR_DATA_OFFSET), %a0 + move.l #(CFG_SYS_SBFHDR_SIZE), %d4 move.l #0xFC05C02C, %a1 /* dspi status */ @@ -334,14 +334,14 @@ asm_nand_init: movec %d0, %ACR2 movec %d0, %ACR3 -#ifdef CONFIG_SYS_CS0_BASE +#ifdef CFG_SYS_CS0_BASE /* Must disable global address */ move.l #0xFC008000, %a1 - move.l #(CONFIG_SYS_CS0_BASE), (%a1) + move.l #(CFG_SYS_CS0_BASE), (%a1) move.l #0xFC008008, %a1 - move.l #(CONFIG_SYS_CS0_CTRL), (%a1) + move.l #(CFG_SYS_CS0_CTRL), (%a1) move.l #0xFC008004, %a1 - move.l #(CONFIG_SYS_CS0_MASK), (%a1) + move.l #(CFG_SYS_CS0_MASK), (%a1) #endif /* NAND port configuration */ @@ -442,10 +442,10 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* initialize general use internal ram */ @@ -456,7 +456,7 @@ _start: move.l %d0, (%a2) /* invalidate and disable cache */ - move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 + move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0 movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -464,7 +464,7 @@ _start: movec %d0, %ACR2 movec %d0, %ACR3 #else - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 #endif @@ -472,7 +472,7 @@ _start: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index ceb462f438f..c05356fc930 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -135,28 +135,28 @@ #endif /* CONFIG_CF_V4 */ -#ifndef CONFIG_SYS_CACHE_ICACR -#define CONFIG_SYS_CACHE_ICACR 0 +#ifndef CFG_SYS_CACHE_ICACR +#define CFG_SYS_CACHE_ICACR 0 #endif -#ifndef CONFIG_SYS_CACHE_DCACR -#ifdef CONFIG_SYS_CACHE_ICACR -#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR +#ifndef CFG_SYS_CACHE_DCACR +#ifdef CFG_SYS_CACHE_ICACR +#define CFG_SYS_CACHE_DCACR CFG_SYS_CACHE_ICACR #else -#define CONFIG_SYS_CACHE_DCACR 0 +#define CFG_SYS_CACHE_DCACR 0 #endif #endif -#ifndef CONFIG_SYS_CACHE_ACR0 -#define CONFIG_SYS_CACHE_ACR0 0 +#ifndef CFG_SYS_CACHE_ACR0 +#define CFG_SYS_CACHE_ACR0 0 #endif -#ifndef CONFIG_SYS_CACHE_ACR1 -#define CONFIG_SYS_CACHE_ACR1 0 +#ifndef CFG_SYS_CACHE_ACR1 +#define CFG_SYS_CACHE_ACR1 0 #endif -#ifndef CONFIG_SYS_CACHE_ACR2 -#define CONFIG_SYS_CACHE_ACR2 0 +#ifndef CFG_SYS_CACHE_ACR2 +#define CFG_SYS_CACHE_ACR2 0 #endif #ifndef CONFIG_SYS_CACHE_ACR3 diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 672aa0bb14e..dab8b26a703 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -14,7 +14,7 @@ #include #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -37,7 +37,7 @@ #include #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -59,7 +59,7 @@ #include #include -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -82,7 +82,7 @@ #include #include -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -105,7 +105,7 @@ #include #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -128,7 +128,7 @@ #include #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -152,7 +152,7 @@ #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (192) @@ -175,7 +175,7 @@ #include #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (128) @@ -198,7 +198,7 @@ #include #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ - (CONFIG_SYS_UART_PORT * 0x40)) + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -223,7 +223,7 @@ #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -246,7 +246,7 @@ #include #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -271,12 +271,12 @@ #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#if (CONFIG_SYS_UART_PORT < 4) +#if (CFG_SYS_UART_PORT < 4) #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ - (CONFIG_SYS_UART_PORT * 0x4000)) + (CFG_SYS_UART_PORT * 0x4000)) #else #define CONFIG_SYS_UART_BASE (MMAP_UART4 + \ - ((CONFIG_SYS_UART_PORT - 4) * 0x4000)) + ((CFG_SYS_UART_PORT - 4) * 0x4000)) #endif #define MMAP_DSPI MMAP_DSPI0 @@ -320,7 +320,7 @@ #define FEC1_TX_INIT 31 #endif -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100)) #ifdef CONFIG_SLTTMR #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) @@ -339,7 +339,7 @@ #ifdef CONFIG_PCI #define CFG_SYS_PCI_BAR0 (0x40000000) #define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE) -#define CFG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) +#define CFG_SYS_PCI_TBATR0 (CFG_SYS_MBAR) #define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE) #endif #endif /* CONFIG_M547x */ diff --git a/arch/m68k/include/asm/immap_520x.h b/arch/m68k/include/asm/immap_520x.h index bb1237453ff..7c7443b9688 100644 --- a/arch/m68k/include/asm/immap_520x.h +++ b/arch/m68k/include/asm/immap_520x.h @@ -9,32 +9,32 @@ #ifndef __IMMAP_520X__ #define __IMMAP_520X__ -#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000) -#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000) -#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x0005C000) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) -#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00088000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x0008C000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00090000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000A8000) +#define MMAP_SCM1 (CFG_SYS_MBAR + 0x00000000) +#define MMAP_XBS (CFG_SYS_MBAR + 0x00004000) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00008000) +#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00030000) +#define MMAP_SCM2 (CFG_SYS_MBAR + 0x00040000) +#define MMAP_EDMA (CFG_SYS_MBAR + 0x00044000) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00048000) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00054000) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00058000) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x0005C000) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00060000) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00064000) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00068000) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00070000) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00074000) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00078000) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x0007C000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00080000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00084000) +#define MMAP_EPORT0 (CFG_SYS_MBAR + 0x00088000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x0008C000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00090000) +#define MMAP_RCM (CFG_SYS_MBAR + 0x000A0000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x000A0004) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000A8000) #include #include diff --git a/arch/m68k/include/asm/immap_5235.h b/arch/m68k/include/asm/immap_5235.h index 27d905ef941..a1825c2a944 100644 --- a/arch/m68k/include/asm/immap_5235.h +++ b/arch/m68k/include/asm/immap_5235.h @@ -9,42 +9,42 @@ #ifndef __IMMAP_5235__ #define __IMMAP_5235__ -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN1 (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_ETPU (CFG_SYS_MBAR + 0x001D0000) +#define MMAP_CAN2 (CFG_SYS_MBAR + 0x001F0000) #include #include diff --git a/arch/m68k/include/asm/immap_5249.h b/arch/m68k/include/asm/immap_5249.h index b599ca6e81c..aa4c3ef42fa 100644 --- a/arch/m68k/include/asm/immap_5249.h +++ b/arch/m68k/include/asm/immap_5249.h @@ -8,13 +8,13 @@ #ifndef __IMMAP_5249__ #define __IMMAP_5249__ -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000400) #include #include diff --git a/arch/m68k/include/asm/immap_5253.h b/arch/m68k/include/asm/immap_5253.h index 883782aa97c..1ab7243dfd8 100644 --- a/arch/m68k/include/asm/immap_5253.h +++ b/arch/m68k/include/asm/immap_5253.h @@ -9,20 +9,20 @@ #ifndef __IMMAP_5253__ #define __IMMAP_5253__ -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_I2C0 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_I2C0 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000400) +#define MMAP_CAN0 (CFG_SYS_MBAR + 0x00010000) +#define MMAP_CAN1 (CFG_SYS_MBAR + 0x00011000) -#define MMAP_PAR (CONFIG_SYS_MBAR2 + 0x0000019C) -#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440) -#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00) +#define MMAP_PAR (CFG_SYS_MBAR2 + 0x0000019C) +#define MMAP_I2C1 (CFG_SYS_MBAR2 + 0x00000440) +#define MMAP_UART2 (CFG_SYS_MBAR2 + 0x00000C00) #include #include diff --git a/arch/m68k/include/asm/immap_5271.h b/arch/m68k/include/asm/immap_5271.h index 27d78613993..a5bf18c4b84 100644 --- a/arch/m68k/include/asm/immap_5271.h +++ b/arch/m68k/include/asm/immap_5271.h @@ -9,42 +9,42 @@ #ifndef __IMMAP_5271__ #define __IMMAP_5271__ -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN1 (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_ETPU (CFG_SYS_MBAR + 0x001D0000) +#define MMAP_CAN2 (CFG_SYS_MBAR + 0x001F0000) #include #include diff --git a/arch/m68k/include/asm/immap_5272.h b/arch/m68k/include/asm/immap_5272.h index cd7b67256cf..c5c3cc75125 100644 --- a/arch/m68k/include/asm/immap_5272.h +++ b/arch/m68k/include/asm/immap_5272.h @@ -8,24 +8,24 @@ #ifndef __IMMAP_5272__ #define __IMMAP_5272__ -#define MMAP_CFG (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000020) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x000000A0) -#define MMAP_PWM (CONFIG_SYS_MBAR + 0x000000C0) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x000000E0) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_TMR0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_TMR1 (CONFIG_SYS_MBAR + 0x00000220) -#define MMAP_TMR2 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_TMR3 (CONFIG_SYS_MBAR + 0x00000260) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_PLIC (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00000840) -#define MMAP_USB (CONFIG_SYS_MBAR + 0x00001000) +#define MMAP_CFG (CFG_SYS_MBAR + 0x00000000) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000020) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000040) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00000080) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x000000A0) +#define MMAP_PWM (CFG_SYS_MBAR + 0x000000C0) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x000000E0) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000180) +#define MMAP_TMR0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_TMR1 (CFG_SYS_MBAR + 0x00000220) +#define MMAP_TMR2 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_TMR3 (CFG_SYS_MBAR + 0x00000260) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00000280) +#define MMAP_PLIC (CFG_SYS_MBAR + 0x00000300) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00000840) +#define MMAP_USB (CFG_SYS_MBAR + 0x00001000) #include diff --git a/arch/m68k/include/asm/immap_5275.h b/arch/m68k/include/asm/immap_5275.h index 8b1a08b4f24..9b8d71d30d4 100644 --- a/arch/m68k/include/asm/immap_5275.h +++ b/arch/m68k/include/asm/immap_5275.h @@ -10,44 +10,44 @@ #ifndef __IMMAP_5275__ #define __IMMAP_5275__ -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FEC0FIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00001800) -#define MMAP_FEC1FIFO (CONFIG_SYS_MBAR + 0x00001C00) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110004) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FEC0FIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_FEC1 (CFG_SYS_MBAR + 0x00001800) +#define MMAP_FEC1FIFO (CFG_SYS_MBAR + 0x00001C00) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_RCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110004) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_USB (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_PWM0 (CFG_SYS_MBAR + 0x001D0000) #include #include diff --git a/arch/m68k/include/asm/immap_5282.h b/arch/m68k/include/asm/immap_5282.h index d7c68f5749a..f810a4dd5cb 100644 --- a/arch/m68k/include/asm/immap_5282.h +++ b/arch/m68k/include/asm/immap_5282.h @@ -8,42 +8,42 @@ #ifndef __IMMAP_5282__ #define __IMMAP_5282__ -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAMC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_QADC (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_GPTMRA (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_GPTMRB (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_CFMC (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CFMMEM (CONFIG_SYS_MBAR + 0x04000000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAMC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_QADC (CFG_SYS_MBAR + 0x00190000) +#define MMAP_GPTMRA (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_GPTMRB (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_CFMC (CFG_SYS_MBAR + 0x001D0000) +#define MMAP_CFMMEM (CFG_SYS_MBAR + 0x04000000) #include #include diff --git a/arch/m68k/include/asm/immap_5301x.h b/arch/m68k/include/asm/immap_5301x.h index 29e60863bfd..e1f7858b100 100644 --- a/arch/m68k/include/asm/immap_5301x.h +++ b/arch/m68k/include/asm/immap_5301x.h @@ -9,46 +9,46 @@ #ifndef __IMMAP_5301X__ #define __IMMAP_5301X__ -#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_MPU (CONFIG_SYS_MBAR + 0x00014000) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000) -#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00034000) -#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000) -#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) -#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00088000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x0008C000) -#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00090000) -#define MMAP_EPORT1 (CONFIG_SYS_MBAR + 0x00094000) -#define MMAP_VOICOD (CONFIG_SYS_MBAR + 0x0009C000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) -#define MMAP_RTC (CONFIG_SYS_MBAR + 0x000A8000) -#define MMAP_SIM (CONFIG_SYS_MBAR + 0x000AC000) -#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B0000) -#define MMAP_USBH (CONFIG_SYS_MBAR + 0x000B4000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000) -#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x000C4000) -#define MMAP_IIM (CONFIG_SYS_MBAR + 0x000C8000) -#define MMAP_ESDHC (CONFIG_SYS_MBAR + 0x000CC000) +#define MMAP_SCM1 (CFG_SYS_MBAR + 0x00000000) +#define MMAP_XBS (CFG_SYS_MBAR + 0x00004000) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00008000) +#define MMAP_MPU (CFG_SYS_MBAR + 0x00014000) +#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00030000) +#define MMAP_FEC1 (CFG_SYS_MBAR + 0x00034000) +#define MMAP_SCM2 (CFG_SYS_MBAR + 0x00040000) +#define MMAP_EDMA (CFG_SYS_MBAR + 0x00044000) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00048000) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x0004C000) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00054000) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00058000) +#define MMAP_DSPI (CFG_SYS_MBAR + 0x0005C000) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00060000) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00064000) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00068000) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00070000) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00074000) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00078000) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x0007C000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00080000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00084000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00088000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x0008C000) +#define MMAP_EPORT0 (CFG_SYS_MBAR + 0x00090000) +#define MMAP_EPORT1 (CFG_SYS_MBAR + 0x00094000) +#define MMAP_VOICOD (CFG_SYS_MBAR + 0x0009C000) +#define MMAP_RCM (CFG_SYS_MBAR + 0x000A0000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x000A0004) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000) +#define MMAP_RTC (CFG_SYS_MBAR + 0x000A8000) +#define MMAP_SIM (CFG_SYS_MBAR + 0x000AC000) +#define MMAP_USBOTG (CFG_SYS_MBAR + 0x000B0000) +#define MMAP_USBH (CFG_SYS_MBAR + 0x000B4000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000B8000) +#define MMAP_SSI (CFG_SYS_MBAR + 0x000BC000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x000C0000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x000C4000) +#define MMAP_IIM (CFG_SYS_MBAR + 0x000C8000) +#define MMAP_ESDHC (CFG_SYS_MBAR + 0x000CC000) #include #include diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h index 930e0899e8c..d6442d95b4b 100644 --- a/arch/m68k/include/asm/immap_5307.h +++ b/arch/m68k/include/asm/immap_5307.h @@ -7,15 +7,15 @@ #ifndef __IMMAP_5307__ #define __IMMAP_5307__ -#define MMAP_SIM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DRAMC (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000244) +#define MMAP_SIM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_CSM (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DRAMC (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00000244) typedef struct sim { u8 rsr; diff --git a/arch/m68k/include/asm/m5249.h b/arch/m68k/include/asm/m5249.h index 9303629e4b2..afafb4e547d 100644 --- a/arch/m68k/include/asm/m5249.h +++ b/arch/m68k/include/asm/m5249.h @@ -14,14 +14,14 @@ /* * useful definitions for reading/writing MBAR offset memory */ -#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y -#define mbar2_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) -#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y -#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR2 + x)) = y -#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR2 + x)) = y +#define mbar_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y +#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x)) +#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x)) = y +#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR2 + x)) = y +#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR2 + x)) = y /* * Size of internal RAM diff --git a/arch/m68k/include/asm/m5271.h b/arch/m68k/include/asm/m5271.h index 7ebeddbb683..e63b42c00de 100644 --- a/arch/m68k/include/asm/m5271.h +++ b/arch/m68k/include/asm/m5271.h @@ -11,12 +11,12 @@ #ifndef _MCF5271_H_ #define _MCF5271_H_ -#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) -#define mbar_readShort(x) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) -#define mbar_readByte(x) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y +#define mbar_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) +#define mbar_readShort(x) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) +#define mbar_readByte(x) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y #define MCF_FMPLL_SYNCR 0x120000 #define MCF_FMPLL_SYNSR 0x120004 diff --git a/arch/m68k/include/asm/m5282.h b/arch/m68k/include/asm/m5282.h index 0c91cf491e2..180f20386fc 100644 --- a/arch/m68k/include/asm/m5282.h +++ b/arch/m68k/include/asm/m5282.h @@ -108,112 +108,112 @@ /* General Purpose I/O Module GPIO */ -#define MCFGPIO_PORTA (*(vu_char *) (CONFIG_SYS_MBAR+0x100000)) -#define MCFGPIO_PORTB (*(vu_char *) (CONFIG_SYS_MBAR+0x100001)) -#define MCFGPIO_PORTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100002)) -#define MCFGPIO_PORTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100003)) -#define MCFGPIO_PORTE (*(vu_char *) (CONFIG_SYS_MBAR+0x100004)) -#define MCFGPIO_PORTF (*(vu_char *) (CONFIG_SYS_MBAR+0x100005)) -#define MCFGPIO_PORTG (*(vu_char *) (CONFIG_SYS_MBAR+0x100006)) -#define MCFGPIO_PORTH (*(vu_char *) (CONFIG_SYS_MBAR+0x100007)) -#define MCFGPIO_PORTJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100008)) -#define MCFGPIO_PORTDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100009)) -#define MCFGPIO_PORTEH (*(vu_char *) (CONFIG_SYS_MBAR+0x10000A)) -#define MCFGPIO_PORTEL (*(vu_char *) (CONFIG_SYS_MBAR+0x10000B)) -#define MCFGPIO_PORTAS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000C)) -#define MCFGPIO_PORTQS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000D)) -#define MCFGPIO_PORTSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10000E)) -#define MCFGPIO_PORTTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10000F)) -#define MCFGPIO_PORTTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100010)) -#define MCFGPIO_PORTUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100011)) - -#define MCFGPIO_DDRA (*(vu_char *) (CONFIG_SYS_MBAR+0x100014)) -#define MCFGPIO_DDRB (*(vu_char *) (CONFIG_SYS_MBAR+0x100015)) -#define MCFGPIO_DDRC (*(vu_char *) (CONFIG_SYS_MBAR+0x100016)) -#define MCFGPIO_DDRD (*(vu_char *) (CONFIG_SYS_MBAR+0x100017)) -#define MCFGPIO_DDRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100018)) -#define MCFGPIO_DDRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100019)) -#define MCFGPIO_DDRG (*(vu_char *) (CONFIG_SYS_MBAR+0x10001A)) -#define MCFGPIO_DDRH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001B)) -#define MCFGPIO_DDRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x10001C)) -#define MCFGPIO_DDRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x10001D)) -#define MCFGPIO_DDREH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001E)) -#define MCFGPIO_DDREL (*(vu_char *) (CONFIG_SYS_MBAR+0x10001F)) -#define MCFGPIO_DDRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100020)) -#define MCFGPIO_DDRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100021)) -#define MCFGPIO_DDRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100022)) -#define MCFGPIO_DDRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100023)) -#define MCFGPIO_DDRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100024)) -#define MCFGPIO_DDRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100025)) - -#define MCFGPIO_PORTAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) -#define MCFGPIO_PORTBP (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) -#define MCFGPIO_PORTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) -#define MCFGPIO_PORTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) -#define MCFGPIO_PORTEP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) -#define MCFGPIO_PORTFP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) -#define MCFGPIO_PORTGP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) -#define MCFGPIO_PORTHP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) -#define MCFGPIO_PORTJP (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) -#define MCFGPIO_PORTDDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) -#define MCFGPIO_PORTEHP (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) -#define MCFGPIO_PORTELP (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) -#define MCFGPIO_PORTASP (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) -#define MCFGPIO_PORTQSP (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) -#define MCFGPIO_PORTSDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) -#define MCFGPIO_PORTTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) -#define MCFGPIO_PORTTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) -#define MCFGPIO_PORTUAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) - -#define MCFGPIO_SETA (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) -#define MCFGPIO_SETB (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) -#define MCFGPIO_SETC (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) -#define MCFGPIO_SETD (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) -#define MCFGPIO_SETE (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) -#define MCFGPIO_SETF (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) -#define MCFGPIO_SETG (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) -#define MCFGPIO_SETH (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) -#define MCFGPIO_SETJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) -#define MCFGPIO_SETDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) -#define MCFGPIO_SETEH (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) -#define MCFGPIO_SETEL (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) -#define MCFGPIO_SETAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) -#define MCFGPIO_SETQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) -#define MCFGPIO_SETSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) -#define MCFGPIO_SETTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) -#define MCFGPIO_SETTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) -#define MCFGPIO_SETUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) - -#define MCFGPIO_CLRA (*(vu_char *) (CONFIG_SYS_MBAR+0x10003C)) -#define MCFGPIO_CLRB (*(vu_char *) (CONFIG_SYS_MBAR+0x10003D)) -#define MCFGPIO_CLRC (*(vu_char *) (CONFIG_SYS_MBAR+0x10003E)) -#define MCFGPIO_CLRD (*(vu_char *) (CONFIG_SYS_MBAR+0x10003F)) -#define MCFGPIO_CLRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100040)) -#define MCFGPIO_CLRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100041)) -#define MCFGPIO_CLRG (*(vu_char *) (CONFIG_SYS_MBAR+0x100042)) -#define MCFGPIO_CLRH (*(vu_char *) (CONFIG_SYS_MBAR+0x100043)) -#define MCFGPIO_CLRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100044)) -#define MCFGPIO_CLRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100045)) -#define MCFGPIO_CLREH (*(vu_char *) (CONFIG_SYS_MBAR+0x100046)) -#define MCFGPIO_CLREL (*(vu_char *) (CONFIG_SYS_MBAR+0x100047)) -#define MCFGPIO_CLRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100048)) -#define MCFGPIO_CLRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100049)) -#define MCFGPIO_CLRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004A)) -#define MCFGPIO_CLRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10004B)) -#define MCFGPIO_CLRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004C)) -#define MCFGPIO_CLRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x10004D)) - -#define MCFGPIO_PBCDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100050)) -#define MCFGPIO_PFPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100051)) -#define MCFGPIO_PEPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100052)) -#define MCFGPIO_PJPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100054)) -#define MCFGPIO_PSDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100055)) -#define MCFGPIO_PASPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100056)) -#define MCFGPIO_PEHLPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100058)) -#define MCFGPIO_PQSPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100059)) -#define MCFGPIO_PTCPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005A)) -#define MCFGPIO_PTDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005B)) -#define MCFGPIO_PUAPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005C)) +#define MCFGPIO_PORTA (*(vu_char *) (CFG_SYS_MBAR+0x100000)) +#define MCFGPIO_PORTB (*(vu_char *) (CFG_SYS_MBAR+0x100001)) +#define MCFGPIO_PORTC (*(vu_char *) (CFG_SYS_MBAR+0x100002)) +#define MCFGPIO_PORTD (*(vu_char *) (CFG_SYS_MBAR+0x100003)) +#define MCFGPIO_PORTE (*(vu_char *) (CFG_SYS_MBAR+0x100004)) +#define MCFGPIO_PORTF (*(vu_char *) (CFG_SYS_MBAR+0x100005)) +#define MCFGPIO_PORTG (*(vu_char *) (CFG_SYS_MBAR+0x100006)) +#define MCFGPIO_PORTH (*(vu_char *) (CFG_SYS_MBAR+0x100007)) +#define MCFGPIO_PORTJ (*(vu_char *) (CFG_SYS_MBAR+0x100008)) +#define MCFGPIO_PORTDD (*(vu_char *) (CFG_SYS_MBAR+0x100009)) +#define MCFGPIO_PORTEH (*(vu_char *) (CFG_SYS_MBAR+0x10000A)) +#define MCFGPIO_PORTEL (*(vu_char *) (CFG_SYS_MBAR+0x10000B)) +#define MCFGPIO_PORTAS (*(vu_char *) (CFG_SYS_MBAR+0x10000C)) +#define MCFGPIO_PORTQS (*(vu_char *) (CFG_SYS_MBAR+0x10000D)) +#define MCFGPIO_PORTSD (*(vu_char *) (CFG_SYS_MBAR+0x10000E)) +#define MCFGPIO_PORTTC (*(vu_char *) (CFG_SYS_MBAR+0x10000F)) +#define MCFGPIO_PORTTD (*(vu_char *) (CFG_SYS_MBAR+0x100010)) +#define MCFGPIO_PORTUA (*(vu_char *) (CFG_SYS_MBAR+0x100011)) + +#define MCFGPIO_DDRA (*(vu_char *) (CFG_SYS_MBAR+0x100014)) +#define MCFGPIO_DDRB (*(vu_char *) (CFG_SYS_MBAR+0x100015)) +#define MCFGPIO_DDRC (*(vu_char *) (CFG_SYS_MBAR+0x100016)) +#define MCFGPIO_DDRD (*(vu_char *) (CFG_SYS_MBAR+0x100017)) +#define MCFGPIO_DDRE (*(vu_char *) (CFG_SYS_MBAR+0x100018)) +#define MCFGPIO_DDRF (*(vu_char *) (CFG_SYS_MBAR+0x100019)) +#define MCFGPIO_DDRG (*(vu_char *) (CFG_SYS_MBAR+0x10001A)) +#define MCFGPIO_DDRH (*(vu_char *) (CFG_SYS_MBAR+0x10001B)) +#define MCFGPIO_DDRJ (*(vu_char *) (CFG_SYS_MBAR+0x10001C)) +#define MCFGPIO_DDRDD (*(vu_char *) (CFG_SYS_MBAR+0x10001D)) +#define MCFGPIO_DDREH (*(vu_char *) (CFG_SYS_MBAR+0x10001E)) +#define MCFGPIO_DDREL (*(vu_char *) (CFG_SYS_MBAR+0x10001F)) +#define MCFGPIO_DDRAS (*(vu_char *) (CFG_SYS_MBAR+0x100020)) +#define MCFGPIO_DDRQS (*(vu_char *) (CFG_SYS_MBAR+0x100021)) +#define MCFGPIO_DDRSD (*(vu_char *) (CFG_SYS_MBAR+0x100022)) +#define MCFGPIO_DDRTC (*(vu_char *) (CFG_SYS_MBAR+0x100023)) +#define MCFGPIO_DDRTD (*(vu_char *) (CFG_SYS_MBAR+0x100024)) +#define MCFGPIO_DDRUA (*(vu_char *) (CFG_SYS_MBAR+0x100025)) + +#define MCFGPIO_PORTAP (*(vu_char *) (CFG_SYS_MBAR+0x100028)) +#define MCFGPIO_PORTBP (*(vu_char *) (CFG_SYS_MBAR+0x100029)) +#define MCFGPIO_PORTCP (*(vu_char *) (CFG_SYS_MBAR+0x10002A)) +#define MCFGPIO_PORTDP (*(vu_char *) (CFG_SYS_MBAR+0x10002B)) +#define MCFGPIO_PORTEP (*(vu_char *) (CFG_SYS_MBAR+0x10002C)) +#define MCFGPIO_PORTFP (*(vu_char *) (CFG_SYS_MBAR+0x10002D)) +#define MCFGPIO_PORTGP (*(vu_char *) (CFG_SYS_MBAR+0x10002E)) +#define MCFGPIO_PORTHP (*(vu_char *) (CFG_SYS_MBAR+0x10002F)) +#define MCFGPIO_PORTJP (*(vu_char *) (CFG_SYS_MBAR+0x100030)) +#define MCFGPIO_PORTDDP (*(vu_char *) (CFG_SYS_MBAR+0x100031)) +#define MCFGPIO_PORTEHP (*(vu_char *) (CFG_SYS_MBAR+0x100032)) +#define MCFGPIO_PORTELP (*(vu_char *) (CFG_SYS_MBAR+0x100033)) +#define MCFGPIO_PORTASP (*(vu_char *) (CFG_SYS_MBAR+0x100034)) +#define MCFGPIO_PORTQSP (*(vu_char *) (CFG_SYS_MBAR+0x100035)) +#define MCFGPIO_PORTSDP (*(vu_char *) (CFG_SYS_MBAR+0x100036)) +#define MCFGPIO_PORTTCP (*(vu_char *) (CFG_SYS_MBAR+0x100037)) +#define MCFGPIO_PORTTDP (*(vu_char *) (CFG_SYS_MBAR+0x100038)) +#define MCFGPIO_PORTUAP (*(vu_char *) (CFG_SYS_MBAR+0x100039)) + +#define MCFGPIO_SETA (*(vu_char *) (CFG_SYS_MBAR+0x100028)) +#define MCFGPIO_SETB (*(vu_char *) (CFG_SYS_MBAR+0x100029)) +#define MCFGPIO_SETC (*(vu_char *) (CFG_SYS_MBAR+0x10002A)) +#define MCFGPIO_SETD (*(vu_char *) (CFG_SYS_MBAR+0x10002B)) +#define MCFGPIO_SETE (*(vu_char *) (CFG_SYS_MBAR+0x10002C)) +#define MCFGPIO_SETF (*(vu_char *) (CFG_SYS_MBAR+0x10002D)) +#define MCFGPIO_SETG (*(vu_char *) (CFG_SYS_MBAR+0x10002E)) +#define MCFGPIO_SETH (*(vu_char *) (CFG_SYS_MBAR+0x10002F)) +#define MCFGPIO_SETJ (*(vu_char *) (CFG_SYS_MBAR+0x100030)) +#define MCFGPIO_SETDD (*(vu_char *) (CFG_SYS_MBAR+0x100031)) +#define MCFGPIO_SETEH (*(vu_char *) (CFG_SYS_MBAR+0x100032)) +#define MCFGPIO_SETEL (*(vu_char *) (CFG_SYS_MBAR+0x100033)) +#define MCFGPIO_SETAS (*(vu_char *) (CFG_SYS_MBAR+0x100034)) +#define MCFGPIO_SETQS (*(vu_char *) (CFG_SYS_MBAR+0x100035)) +#define MCFGPIO_SETSD (*(vu_char *) (CFG_SYS_MBAR+0x100036)) +#define MCFGPIO_SETTC (*(vu_char *) (CFG_SYS_MBAR+0x100037)) +#define MCFGPIO_SETTD (*(vu_char *) (CFG_SYS_MBAR+0x100038)) +#define MCFGPIO_SETUA (*(vu_char *) (CFG_SYS_MBAR+0x100039)) + +#define MCFGPIO_CLRA (*(vu_char *) (CFG_SYS_MBAR+0x10003C)) +#define MCFGPIO_CLRB (*(vu_char *) (CFG_SYS_MBAR+0x10003D)) +#define MCFGPIO_CLRC (*(vu_char *) (CFG_SYS_MBAR+0x10003E)) +#define MCFGPIO_CLRD (*(vu_char *) (CFG_SYS_MBAR+0x10003F)) +#define MCFGPIO_CLRE (*(vu_char *) (CFG_SYS_MBAR+0x100040)) +#define MCFGPIO_CLRF (*(vu_char *) (CFG_SYS_MBAR+0x100041)) +#define MCFGPIO_CLRG (*(vu_char *) (CFG_SYS_MBAR+0x100042)) +#define MCFGPIO_CLRH (*(vu_char *) (CFG_SYS_MBAR+0x100043)) +#define MCFGPIO_CLRJ (*(vu_char *) (CFG_SYS_MBAR+0x100044)) +#define MCFGPIO_CLRDD (*(vu_char *) (CFG_SYS_MBAR+0x100045)) +#define MCFGPIO_CLREH (*(vu_char *) (CFG_SYS_MBAR+0x100046)) +#define MCFGPIO_CLREL (*(vu_char *) (CFG_SYS_MBAR+0x100047)) +#define MCFGPIO_CLRAS (*(vu_char *) (CFG_SYS_MBAR+0x100048)) +#define MCFGPIO_CLRQS (*(vu_char *) (CFG_SYS_MBAR+0x100049)) +#define MCFGPIO_CLRSD (*(vu_char *) (CFG_SYS_MBAR+0x10004A)) +#define MCFGPIO_CLRTC (*(vu_char *) (CFG_SYS_MBAR+0x10004B)) +#define MCFGPIO_CLRTD (*(vu_char *) (CFG_SYS_MBAR+0x10004C)) +#define MCFGPIO_CLRUA (*(vu_char *) (CFG_SYS_MBAR+0x10004D)) + +#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_SYS_MBAR+0x100050)) +#define MCFGPIO_PFPAR (*(vu_char *) (CFG_SYS_MBAR+0x100051)) +#define MCFGPIO_PEPAR (*(vu_short *)(CFG_SYS_MBAR+0x100052)) +#define MCFGPIO_PJPAR (*(vu_char *) (CFG_SYS_MBAR+0x100054)) +#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_SYS_MBAR+0x100055)) +#define MCFGPIO_PASPAR (*(vu_short *)(CFG_SYS_MBAR+0x100056)) +#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_SYS_MBAR+0x100058)) +#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_SYS_MBAR+0x100059)) +#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005A)) +#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005B)) +#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005C)) /* Bit level definitions and macros */ #define MCFGPIO_PORT7 (0x80) @@ -310,25 +310,25 @@ /* System Conrol Module SCM */ -#define MCFSCM_RAMBAR (*(vu_long *) (CONFIG_SYS_MBAR+0x00000008)) -#define MCFSCM_CRSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000010)) -#define MCFSCM_CWCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000011)) -#define MCFSCM_LPICR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000012)) -#define MCFSCM_CWSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000013)) - -#define MCFSCM_MPARK (*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C)) -#define MCFSCM_MPR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000020)) -#define MCFSCM_PACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000024)) -#define MCFSCM_PACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000025)) -#define MCFSCM_PACR2 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000026)) -#define MCFSCM_PACR3 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000027)) -#define MCFSCM_PACR4 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000028)) -#define MCFSCM_PACR5 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A)) -#define MCFSCM_PACR6 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B)) -#define MCFSCM_PACR7 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C)) -#define MCFSCM_PACR8 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E)) -#define MCFSCM_GPACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000030)) -#define MCFSCM_GPACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000031)) +#define MCFSCM_RAMBAR (*(vu_long *) (CFG_SYS_MBAR+0x00000008)) +#define MCFSCM_CRSR (*(vu_char *) (CFG_SYS_MBAR+0x00000010)) +#define MCFSCM_CWCR (*(vu_char *) (CFG_SYS_MBAR+0x00000011)) +#define MCFSCM_LPICR (*(vu_char *) (CFG_SYS_MBAR+0x00000012)) +#define MCFSCM_CWSR (*(vu_char *) (CFG_SYS_MBAR+0x00000013)) + +#define MCFSCM_MPARK (*(vu_long *) (CFG_SYS_MBAR+0x0000001C)) +#define MCFSCM_MPR (*(vu_char *) (CFG_SYS_MBAR+0x00000020)) +#define MCFSCM_PACR0 (*(vu_char *) (CFG_SYS_MBAR+0x00000024)) +#define MCFSCM_PACR1 (*(vu_char *) (CFG_SYS_MBAR+0x00000025)) +#define MCFSCM_PACR2 (*(vu_char *) (CFG_SYS_MBAR+0x00000026)) +#define MCFSCM_PACR3 (*(vu_char *) (CFG_SYS_MBAR+0x00000027)) +#define MCFSCM_PACR4 (*(vu_char *) (CFG_SYS_MBAR+0x00000028)) +#define MCFSCM_PACR5 (*(vu_char *) (CFG_SYS_MBAR+0x0000002A)) +#define MCFSCM_PACR6 (*(vu_char *) (CFG_SYS_MBAR+0x0000002B)) +#define MCFSCM_PACR7 (*(vu_char *) (CFG_SYS_MBAR+0x0000002C)) +#define MCFSCM_PACR8 (*(vu_char *) (CFG_SYS_MBAR+0x0000002E)) +#define MCFSCM_GPACR0 (*(vu_char *) (CFG_SYS_MBAR+0x00000030)) +#define MCFSCM_GPACR1 (*(vu_char *) (CFG_SYS_MBAR+0x00000031)) #define MCFSCM_CRSR_EXT (0x80) #define MCFSCM_CRSR_CWDR (0x20) @@ -337,8 +337,8 @@ /* Reset Controller Module RCM */ -#define MCFRESET_RCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110000)) -#define MCFRESET_RSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110001)) +#define MCFRESET_RCR (*(vu_char *) (CFG_SYS_MBAR+0x00110000)) +#define MCFRESET_RSR (*(vu_char *) (CFG_SYS_MBAR+0x00110001)) #define MCFRESET_RCR_SOFTRST (0x80) #define MCFRESET_RCR_FRCRSTOUT (0x40) @@ -360,9 +360,9 @@ /* Chip Configuration Module CCM */ -#define MCFCCM_CCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00110004)) -#define MCFCCM_RCON (*(vu_short *)(CONFIG_SYS_MBAR+0x00110008)) -#define MCFCCM_CIR (*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A)) +#define MCFCCM_CCR (*(vu_short *)(CFG_SYS_MBAR+0x00110004)) +#define MCFCCM_RCON (*(vu_short *)(CFG_SYS_MBAR+0x00110008)) +#define MCFCCM_CIR (*(vu_short *)(CFG_SYS_MBAR+0x0011000A)) /* Bit level definitions and macros */ #define MCFCCM_CCR_LOAD (0x8000) @@ -377,18 +377,18 @@ /* Clock Module */ -#define MCFCLOCK_SYNCR (*(vu_short *)(CONFIG_SYS_MBAR+0x120000)) -#define MCFCLOCK_SYNSR (*(vu_char *) (CONFIG_SYS_MBAR+0x120002)) +#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_SYS_MBAR+0x120000)) +#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_SYS_MBAR+0x120002)) #define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) #define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) #define MCFCLOCK_SYNSR_LOCK 0x08 -#define MCFSDRAMC_DCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00000040)) -#define MCFSDRAMC_DACR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000048)) -#define MCFSDRAMC_DMR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c)) -#define MCFSDRAMC_DACR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000050)) -#define MCFSDRAMC_DMR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000054)) +#define MCFSDRAMC_DCR (*(vu_short *)(CFG_SYS_MBAR+0x00000040)) +#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_SYS_MBAR+0x00000048)) +#define MCFSDRAMC_DMR0 (*(vu_long *) (CFG_SYS_MBAR+0x0000004c)) +#define MCFSDRAMC_DACR1 (*(vu_long *) (CFG_SYS_MBAR+0x00000050)) +#define MCFSDRAMC_DMR1 (*(vu_long *) (CFG_SYS_MBAR+0x00000054)) #define MCFSDRAMC_DCR_NAM (0x2000) #define MCFSDRAMC_DCR_COC (0x1000) @@ -418,60 +418,60 @@ #define MCFSDRAMC_DMR_UD (0x00000002) #define MCFSDRAMC_DMR_V (0x00000001) -#define MCFWTM_WCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140000)) -#define MCFWTM_WMR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140002)) -#define MCFWTM_WCNTR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140004)) -#define MCFWTM_WSR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140006)) +#define MCFWTM_WCR (*(vu_short *)(CFG_SYS_MBAR+0x00140000)) +#define MCFWTM_WMR (*(vu_short *)(CFG_SYS_MBAR+0x00140002)) +#define MCFWTM_WCNTR (*(vu_short *)(CFG_SYS_MBAR+0x00140004)) +#define MCFWTM_WSR (*(vu_short *)(CFG_SYS_MBAR+0x00140006)) /********************************************************************* * General Purpose Timer (GPT) Module *********************************************************************/ -#define MCFGPTA_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000)) -#define MCFGPTA_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001)) -#define MCFGPTA_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002)) -#define MCFGPTA_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003)) -#define MCFGPTA_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004)) -#define MCFGPTA_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006)) -#define MCFGPTA_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008)) -#define MCFGPTA_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009)) -#define MCFGPTA_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B)) -#define MCFGPTA_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C)) -#define MCFGPTA_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D)) -#define MCFGPTA_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E)) -#define MCFGPTA_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F)) -#define MCFGPTA_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010)) -#define MCFGPTA_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012)) -#define MCFGPTA_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014)) -#define MCFGPTA_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016)) -#define MCFGPTA_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018)) -#define MCFGPTA_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019)) -#define MCFGPTA_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A)) -#define MCFGPTA_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D)) -#define MCFGPTA_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E)) - -#define MCFGPTB_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000)) -#define MCFGPTB_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001)) -#define MCFGPTB_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002)) -#define MCFGPTB_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003)) -#define MCFGPTB_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004)) -#define MCFGPTB_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006)) -#define MCFGPTB_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008)) -#define MCFGPTB_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009)) -#define MCFGPTB_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B)) -#define MCFGPTB_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C)) -#define MCFGPTB_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D)) -#define MCFGPTB_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E)) -#define MCFGPTB_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F)) -#define MCFGPTB_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010)) -#define MCFGPTB_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012)) -#define MCFGPTB_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014)) -#define MCFGPTB_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016)) -#define MCFGPTB_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018)) -#define MCFGPTB_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019)) -#define MCFGPTB_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A)) -#define MCFGPTB_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D)) -#define MCFGPTB_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E)) +#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_SYS_MBAR+0x1A0000)) +#define MCFGPTA_GPTCFORC (*(vu_char *)(CFG_SYS_MBAR+0x1A0001)) +#define MCFGPTA_GPTOC3M (*(vu_char *)(CFG_SYS_MBAR+0x1A0002)) +#define MCFGPTA_GPTOC3D (*(vu_char *)(CFG_SYS_MBAR+0x1A0003)) +#define MCFGPTA_GPTCNT (*(vu_short *)(CFG_SYS_MBAR+0x1A0004)) +#define MCFGPTA_GPTSCR1 (*(vu_char *)(CFG_SYS_MBAR+0x1A0006)) +#define MCFGPTA_GPTTOV (*(vu_char *)(CFG_SYS_MBAR+0x1A0008)) +#define MCFGPTA_GPTCTL1 (*(vu_char *)(CFG_SYS_MBAR+0x1A0009)) +#define MCFGPTA_GPTCTL2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000B)) +#define MCFGPTA_GPTIE (*(vu_char *)(CFG_SYS_MBAR+0x1A000C)) +#define MCFGPTA_GPTSCR2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000D)) +#define MCFGPTA_GPTFLG1 (*(vu_char *)(CFG_SYS_MBAR+0x1A000E)) +#define MCFGPTA_GPTFLG2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000F)) +#define MCFGPTA_GPTC0 (*(vu_short *)(CFG_SYS_MBAR+0x1A0010)) +#define MCFGPTA_GPTC1 (*(vu_short *)(CFG_SYS_MBAR+0x1A0012)) +#define MCFGPTA_GPTC2 (*(vu_short *)(CFG_SYS_MBAR+0x1A0014)) +#define MCFGPTA_GPTC3 (*(vu_short *)(CFG_SYS_MBAR+0x1A0016)) +#define MCFGPTA_GPTPACTL (*(vu_char *)(CFG_SYS_MBAR+0x1A0018)) +#define MCFGPTA_GPTPAFLG (*(vu_char *)(CFG_SYS_MBAR+0x1A0019)) +#define MCFGPTA_GPTPACNT (*(vu_short *)(CFG_SYS_MBAR+0x1A001A)) +#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_SYS_MBAR+0x1A001D)) +#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_SYS_MBAR+0x1A001E)) + +#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_SYS_MBAR+0x1B0000)) +#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_SYS_MBAR+0x1B0001)) +#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_SYS_MBAR+0x1B0002)) +#define MCFGPTB_GPTOC3D (*(vu_char *)(CFG_SYS_MBAR+0x1B0003)) +#define MCFGPTB_GPTCNT (*(vu_short *)(CFG_SYS_MBAR+0x1B0004)) +#define MCFGPTB_GPTSCR1 (*(vu_char *)(CFG_SYS_MBAR+0x1B0006)) +#define MCFGPTB_GPTTOV (*(vu_char *)(CFG_SYS_MBAR+0x1B0008)) +#define MCFGPTB_GPTCTL1 (*(vu_char *)(CFG_SYS_MBAR+0x1B0009)) +#define MCFGPTB_GPTCTL2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000B)) +#define MCFGPTB_GPTIE (*(vu_char *)(CFG_SYS_MBAR+0x1B000C)) +#define MCFGPTB_GPTSCR2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000D)) +#define MCFGPTB_GPTFLG1 (*(vu_char *)(CFG_SYS_MBAR+0x1B000E)) +#define MCFGPTB_GPTFLG2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000F)) +#define MCFGPTB_GPTC0 (*(vu_short *)(CFG_SYS_MBAR+0x1B0010)) +#define MCFGPTB_GPTC1 (*(vu_short *)(CFG_SYS_MBAR+0x1B0012)) +#define MCFGPTB_GPTC2 (*(vu_short *)(CFG_SYS_MBAR+0x1B0014)) +#define MCFGPTB_GPTC3 (*(vu_short *)(CFG_SYS_MBAR+0x1B0016)) +#define MCFGPTB_GPTPACTL (*(vu_char *)(CFG_SYS_MBAR+0x1B0018)) +#define MCFGPTB_GPTPAFLG (*(vu_char *)(CFG_SYS_MBAR+0x1B0019)) +#define MCFGPTB_GPTPACNT (*(vu_short *)(CFG_SYS_MBAR+0x1B001A)) +#define MCFGPTB_GPTPORT (*(vu_char *)(CFG_SYS_MBAR+0x1B001D)) +#define MCFGPTB_GPTDDR (*(vu_char *)(CFG_SYS_MBAR+0x1B001E)) /* Bit level definitions and macros */ #define MCFGPT_GPTIOS_IOS3 (0x08) @@ -556,7 +556,7 @@ /* Coldfire Flash Module CFM */ -#define MCFCFM_MCR (*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000)) +#define MCFCFM_MCR (*(vu_short *)(CFG_SYS_MBAR+0x1D0000)) #define MCFCFM_MCR_LOCK (0x0400) #define MCFCFM_MCR_PVIE (0x0200) #define MCFCFM_MCR_AEIE (0x0100) @@ -564,23 +564,23 @@ #define MCFCFM_MCR_CCIE (0x0040) #define MCFCFM_MCR_KEYACC (0x0020) -#define MCFCFM_CLKD (*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002)) +#define MCFCFM_CLKD (*(vu_char *)(CFG_SYS_MBAR+0x1D0002)) -#define MCFCFM_SEC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008)) +#define MCFCFM_SEC (*(vu_long*) (CFG_SYS_MBAR+0x1D0008)) #define MCFCFM_SEC_KEYEN (0x80000000) #define MCFCFM_SEC_SECSTAT (0x40000000) -#define MCFCFM_PROT (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010)) -#define MCFCFM_SACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014)) -#define MCFCFM_DACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018)) -#define MCFCFM_USTAT (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020)) +#define MCFCFM_PROT (*(vu_long*) (CFG_SYS_MBAR+0x1D0010)) +#define MCFCFM_SACC (*(vu_long*) (CFG_SYS_MBAR+0x1D0014)) +#define MCFCFM_DACC (*(vu_long*) (CFG_SYS_MBAR+0x1D0018)) +#define MCFCFM_USTAT (*(vu_char*) (CFG_SYS_MBAR+0x1D0020)) #define MCFCFM_USTAT_CBEIF 0x80 #define MCFCFM_USTAT_CCIF 0x40 #define MCFCFM_USTAT_PVIOL 0x20 #define MCFCFM_USTAT_ACCERR 0x10 #define MCFCFM_USTAT_BLANK 0x04 -#define MCFCFM_CMD (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024)) +#define MCFCFM_CMD (*(vu_char*) (CFG_SYS_MBAR+0x1D0024)) #define MCFCFM_CMD_ERSVER 0x05 #define MCFCFM_CMD_PGERSVER 0x06 #define MCFCFM_CMD_PGM 0x20 diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c index 7eca6725a65..0b4629f1c8a 100644 --- a/arch/m68k/lib/bdinfo.c +++ b/arch/m68k/lib/bdinfo.c @@ -16,7 +16,7 @@ int arch_setup_bdinfo(void) { struct bd_info *bd = gd->bd; - bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ + bd->bi_mbar_base = CFG_SYS_MBAR; /* base of internal registers */ bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ @@ -38,7 +38,7 @@ void arch_print_bdinfo(void) struct bd_info *bd = gd->bd; bdinfo_print_mhz("busfreq", bd->bi_busfreq); -#if defined(CONFIG_SYS_MBAR) +#if defined(CFG_SYS_MBAR) bdinfo_print_num_l("mbar", bd->bi_mbar_base); #endif bdinfo_print_mhz("cpufreq", bd->bi_intfreq); diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c index aa2b93e0e0f..4ddda69f5a3 100644 --- a/arch/m68k/lib/cache.c +++ b/arch/m68k/lib/cache.c @@ -34,18 +34,18 @@ void icache_enable(void) *cf_icache_status = 1; #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) - __asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2)); + __asm__ __volatile__("movec %0, %%acr2"::"r"(CFG_SYS_CACHE_ACR2)); __asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3)); #if defined(CONFIG_CF_V4E) __asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6)); __asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7)); #endif #else - __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0)); - __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1)); + __asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1)); #endif - __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR)); + __asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_ICACR)); } void icache_disable(void) @@ -72,9 +72,9 @@ void icache_invalid(void) { u32 temp; - temp = CONFIG_SYS_ICACHE_INV; + temp = CFG_SYS_ICACHE_INV; if (*cf_icache_status) - temp |= CONFIG_SYS_CACHE_ICACR; + temp |= CFG_SYS_CACHE_ICACR; __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); } @@ -89,15 +89,15 @@ void dcache_enable(void) *cf_dcache_status = 1; #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) - __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0)); - __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1)); + __asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1)); #if defined(CONFIG_CF_V4E) __asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4)); __asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5)); #endif #endif - __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR)); + __asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_DCACR)); } void dcache_disable(void) @@ -124,11 +124,11 @@ void dcache_invalid(void) #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) u32 temp; - temp = CONFIG_SYS_DCACHE_INV; + temp = CFG_SYS_DCACHE_INV; if (*cf_dcache_status) - temp |= CONFIG_SYS_CACHE_DCACR; + temp |= CFG_SYS_CACHE_DCACR; if (*cf_icache_status) - temp |= CONFIG_SYS_CACHE_ICACR; + temp |= CFG_SYS_CACHE_ICACR; __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); #endif diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S index 6b9f253952a..7063f32610b 100644 --- a/arch/mips/mach-mtmips/mt7621/spl/start.S +++ b/arch/mips/mach-mtmips/mt7621/spl/start.S @@ -19,7 +19,7 @@ #ifndef CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_SP_OFFSET) + CFG_SYS_INIT_SP_OFFSET) #endif #define SP_ADDR_TEMP 0xbe10dff0 diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 33835eeec2a..63c2729411c 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -77,10 +77,10 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ SCCR_TSECCM | #endif -#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ +#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ SCCR_TSEC1CM | #endif -#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ +#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ SCCR_TSEC2CM | #endif #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ @@ -92,10 +92,10 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ SCCR_USBMPHCM | #endif -#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ +#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */ SCCR_USBDRCM | #endif -#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ +#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */ SCCR_SATACM | #endif 0; @@ -115,11 +115,11 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ - (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | +#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ + (CFG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ - (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | +#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ + (CFG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | #endif #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | @@ -130,11 +130,11 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ - (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | +#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */ + (CFG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ - (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | +#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */ + (CFG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | #endif 0; @@ -175,26 +175,26 @@ void cpu_init_f (volatile immap_t * im) setbits_be32(&im->sysconf.spcr, SPCR_TBEN); /* System General Purpose Register */ -#ifdef CONFIG_SYS_SICRH +#ifdef CFG_SYS_SICRH #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ - __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, + __raw_writel((im->sysconf.sicrh & 0x0000000C) | CFG_SYS_SICRH, &im->sysconf.sicrh); #else - __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh); + __raw_writel(CFG_SYS_SICRH, &im->sysconf.sicrh); #endif #endif -#ifdef CONFIG_SYS_SICRL - __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl); +#ifdef CFG_SYS_SICRL + __raw_writel(CFG_SYS_SICRL, &im->sysconf.sicrl); #endif -#ifdef CONFIG_SYS_GPR1 - __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1); +#ifdef CFG_SYS_GPR1 + __raw_writel(CFG_SYS_GPR1, &im->sysconf.gpr1); #endif -#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */ - __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr); +#ifdef CFG_SYS_DDRCDR /* DDR control driver register */ + __raw_writel(CFG_SYS_DDRCDR, &im->sysconf.ddrcdr); #endif -#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */ - __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir); +#ifdef CFG_SYS_OBIR /* Output buffer impedance register */ + __raw_writel(CFG_SYS_OBIR, &im->sysconf.obir); #endif #if !defined(CONFIG_PINCTRL) diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 6d1c6b055c6..4f982b8303a 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -59,9 +59,9 @@ void board_add_ram_info(int use_default) printf(", %s MHz)", strmhz(buf, gd->mem_clk)); -#if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE) +#if defined(CONFIG_SYS_LB_SDRAM) && defined(CFG_SYS_LBC_SDRAM_SIZE) puts("\nSDRAM: "); - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)"); + print_size (CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)"); #endif } @@ -204,12 +204,12 @@ long int spd_sdram() return 0; } -#ifdef CONFIG_SYS_DDRCDR_VALUE +#ifdef CFG_SYS_DDRCDR_VALUE /* * Adjust DDR II IO voltage biasing. It just makes it work. */ if(spd.mem_type == SPD_MEMTYPE_DDR2) { - immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; + immap->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE; } udelay(50000); #endif @@ -693,7 +693,7 @@ long int spd_sdram() ddr->sdram_mode = (0 | (1 << (16 + 10)) /* DQS Differential disable */ -#ifdef CONFIG_SYS_DDR_MODE_WEAK +#ifdef CFG_SYS_DDR_MODE_WEAK | (1 << (16 + 1)) /* weak driver (~60%) */ #endif | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ @@ -767,8 +767,8 @@ long int spd_sdram() debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2); } -#ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; +#ifdef CFG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ + ddr->sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL; #endif debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 8fcf20854ed..7cc0383afbf 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -54,12 +54,12 @@ void cpu_init_f (volatile immap_t * im) im->sysconf.spcr |= SPCR_TBEN; /* DDR control driver register */ -#ifdef CONFIG_SYS_DDRCDR - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; +#ifdef CFG_SYS_DDRCDR + im->sysconf.ddrcdr = CFG_SYS_DDRCDR; #endif /* Output buffer impedance register */ -#ifdef CONFIG_SYS_OBIR - im->sysconf.obir = CONFIG_SYS_OBIR; +#ifdef CFG_SYS_OBIR + im->sysconf.obir = CFG_SYS_OBIR; #endif /* diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 8a351b927c0..52326f0ec15 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -246,7 +246,7 @@ in_flash: #if CONFIG_VAL(SYS_MALLOC_F_LEN) -#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE #error "SYS_MALLOC_F_LEN too large to fit into initial RAM." #endif @@ -486,7 +486,7 @@ init_e300_core: /* time t 10 */ #if defined(CONFIG_WATCHDOG) /* Initialise the Watchdog values and reset it (if req) */ /*------------------------------------------------------*/ - lis r4, CONFIG_SYS_WATCHDOG_VALUE + lis r4, CFG_SYS_WATCHDOG_VALUE ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) stw r4, SWCRR(r3) @@ -1048,10 +1048,10 @@ trap_init: lock_ram_in_cache: /* Allocate Initial RAM in data cache. */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 + lis r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l + li r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \ + (CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r4 1: dcbz r0, r3 @@ -1070,10 +1070,10 @@ lock_ram_in_cache: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 + lis r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l + li r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \ + (CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r4 1: icbi r0, r3 dcbi r0, r3 @@ -1122,14 +1122,14 @@ map_flash_by_law1: * LBIU Local Access Widow 0 will not cover this memory space. So, we * need another window to map in it. */ - lis r4, (CONFIG_SYS_FLASH_BASE)@h - ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l - stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ + lis r4, (CFG_SYS_FLASH_BASE)@h + ori r4, r4, (CFG_SYS_FLASH_BASE)@l + stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_SYS_FLASH_BASE */ - /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ + /* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR1 */ lis r4, (0x80000012)@h ori r4, r4, (0x80000012)@l - li r5, CONFIG_SYS_FLASH_SIZE + li r5, CFG_SYS_FLASH_SIZE 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ addi r4, r4, 1 bne 1b @@ -1150,24 +1150,24 @@ remap_flash_by_law0: lwz r4, BR0(r3) li r5, 0x7FFF and r4, r4, r5 - lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h - ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l + lis r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@h + ori r5, r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@l or r5, r5, r4 - stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ + stw r5, BR0(r3) /* r5 <= (CFG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ lwz r4, OR0(r3) - lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) + lis r5, ~((CFG_SYS_FLASH_SIZE << 4) - 1) or r4, r4, r5 stw r4, OR0(r3) - lis r4, (CONFIG_SYS_FLASH_BASE)@h - ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l - stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ + lis r4, (CFG_SYS_FLASH_BASE)@h + ori r4, r4, (CFG_SYS_FLASH_BASE)@l + stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_SYS_FLASH_BASE */ - /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ + /* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR0 */ lis r4, (0x80000012)@h ori r4, r4, (0x80000012)@l - li r5, CONFIG_SYS_FLASH_SIZE + li r5, CFG_SYS_FLASH_SIZE 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ addi r4, r4, 1 bne 1b diff --git a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h index f8c2f104c1b..b2f98074fc0 100644 --- a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h +++ b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h @@ -1,7 +1,7 @@ #ifdef CONFIG_ARCH_MPC8308 -#ifndef CONFIG_SYS_SICRL -#define CONFIG_SYS_SICRL (\ +#ifndef CFG_SYS_SICRL +#define CFG_SYS_SICRL (\ CONFIG_SICRL_SPI |\ CONFIG_SICRL_UART |\ CONFIG_SICRL_IRQ |\ @@ -10,8 +10,8 @@ ) #endif -#ifndef CONFIG_SYS_SICRH -#define CONFIG_SYS_SICRH (\ +#ifndef CFG_SYS_SICRH +#define CFG_SYS_SICRH (\ CONFIG_SICRH_ESDHC_A |\ CONFIG_SICRH_ESDHC_B |\ CONFIG_SICRH_ESDHC_C |\ diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 3dccc0e1068..013a171ed87 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index ed890114ec4..c7d473d4a1b 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -23,7 +23,7 @@ */ static void check_erratum_a4849(uint32_t svr) { - void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000; + void __iomem *dcsr = (void *)CFG_SYS_DCSRBAR + 0xb0000; unsigned int i; #if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041) @@ -120,7 +120,7 @@ static void check_erratum_a4580(uint32_t svr) */ static void check_erratum_a007212(void) { - u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); + u32 __iomem *plldgdcr = (void *)(CFG_SYS_DCSRBAR + 0x21c20); if (in_be32(plldgdcr) & 0x1fe) { /* check if PLL ratio is set by workaround */ diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 6acd31d2847..74ad7483dc1 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -417,7 +417,7 @@ void print_reginfo(void) /* Common ddr init for non-corenet fsl 85xx platforms */ #ifndef CONFIG_FSL_CORENET #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \ - !defined(CONFIG_SYS_INIT_L2_ADDR) + !defined(CFG_SYS_INIT_L2_ADDR) int dram_init(void) { #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \ @@ -486,7 +486,7 @@ int dram_init(void) #endif /* CONFIG_SYS_RAMBOOT */ #endif -#if CONFIG_POST & CONFIG_SYS_POST_MEMORY +#if CONFIG_POST & CFG_SYS_POST_MEMORY /* Board-specific functions defined in each board's ddr.c */ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, @@ -591,7 +591,7 @@ static void dump_spd_ddr_reg(void) /* invalid the TLBs for DDR and setup new ones to cover p_addr */ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) { - u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + u32 vstart = CFG_SYS_DDR_SDRAM_BASE; unsigned long epn; u32 tsize, valid, ptr; int ddr_esel; @@ -624,8 +624,8 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); #if !defined(CONFIG_PHYS_64BIT) || \ - !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ - (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) test_cap = p_size; #else test_cap = gd->ram_size; @@ -635,7 +635,7 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); if (reset_tlb(p_addr, p_size, phys_offset) == -1) return -1; - *vstart = CONFIG_SYS_DDR_SDRAM_BASE; + *vstart = CFG_SYS_DDR_SDRAM_BASE; *size = (u32) p_size; printf("Testing 0x%08llx - 0x%08llx\n", (u64)(*vstart) + (*phys_offset), @@ -651,13 +651,13 @@ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); - *vstart = CONFIG_SYS_DDR_SDRAM_BASE; + *vstart = CFG_SYS_DDR_SDRAM_BASE; *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ *phys_offset = 0; #if !defined(CONFIG_PHYS_64BIT) || \ - !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ - (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { puts("Cannot test more than "); print_size(CONFIG_MAX_MEM_MAPPED, diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2c320b202ea..f07e8ab388e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -165,7 +165,7 @@ void disable_cpc_sram(void) for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { /* find and disable LAW of SRAM */ - struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); + struct law_entry law = find_law(CFG_SYS_INIT_L3_ADDR); if (law.index == -1) { printf("\nFatal error happened\n"); @@ -315,15 +315,15 @@ void fsl_erratum_a007212_workaround(void) { ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 ddr_pll_ratio; - u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); - u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); - u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); + u32 __iomem *plldgdcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c20); + u32 __iomem *plldadcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c28); + u32 __iomem *dpdovrcr4 = (void *)(CFG_SYS_DCSRBAR + 0x21e80); #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) - u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); - u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); + u32 __iomem *plldgdcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c40); + u32 __iomem *plldadcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c48); #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) - u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); - u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); + u32 __iomem *plldgdcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c60); + u32 __iomem *plldadcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c68); #endif #endif /* @@ -378,7 +378,7 @@ void fsl_erratum_a007212_workaround(void) ulong cpu_init_f(void) { extern void m8560_cpm_reset (void); -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) @@ -403,7 +403,7 @@ ulong cpu_init_f(void) #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) /* Disable the LAW created for NOR flash by the PBI commands */ - law = find_law(CONFIG_SYS_PBI_FLASH_BASE); + law = find_law(CFG_SYS_PBI_FLASH_BASE); if (law.index != -1) disable_law(law.index); @@ -430,7 +430,7 @@ ulong cpu_init_f(void) /* Invalidate the CPC before DDR gets enabled */ invalidate_cpc(); - #ifdef CONFIG_SYS_DCSRBAR_PHYS + #ifdef CFG_SYS_DCSRBAR_PHYS /* set DCSRCR so that DCSR space is 1G */ setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); in_be32(&gur->dcsrcr); @@ -533,7 +533,7 @@ int l2cache_init(void) asm("msync;isync"); cache_ctl = l2cache->l2ctl; -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L2_ADDR) if (cache_ctl & MPC85xx_L2CTL_L2E) { /* Clear L2 SRAM memory-mapped base address */ out_be32(&l2cache->l2srbar0, 0x0); @@ -590,15 +590,15 @@ int l2cache_init(void) if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { puts("already enabled"); -#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) +#if defined(CFG_SYS_INIT_L2_ADDR) && defined(CFG_SYS_FLASH_BASE) u32 l2srbar = l2cache->l2srbar0; if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE - && l2srbar >= CONFIG_SYS_FLASH_BASE) { - l2srbar = CONFIG_SYS_INIT_L2_ADDR; + && l2srbar >= CFG_SYS_FLASH_BASE) { + l2srbar = CFG_SYS_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; - printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); + printf(", moving to 0x%08x", CFG_SYS_INIT_L2_ADDR); } -#endif /* CONFIG_SYS_INIT_L2_ADDR */ +#endif /* CFG_SYS_INIT_L2_ADDR */ puts("\n"); } else { asm("msync;isync"); @@ -625,9 +625,9 @@ int l2cache_init(void) #endif /* enable the cache */ - mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); + mtspr(SPRN_L2CSR0, CFG_SYS_INIT_L2CSR0); - if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { + if (CFG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) ; print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); @@ -656,7 +656,7 @@ skip_l2: int cpu_init_r(void) { __maybe_unused u32 svr = get_svr(); -#ifdef CONFIG_SYS_LBC_LCRR +#ifdef CFG_SYS_LBC_LCRR fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; #endif #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) @@ -763,13 +763,13 @@ int cpu_init_r(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 if (IS_SVR_REV(svr, 1, 0)) { int i; - __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; + __be32 *p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb004c; for (i = 0; i < 12; i++) { p += i + (i > 5 ? 11 : 0); out_be32(p, 0x2); } - p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; + p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb0108; out_be32(p, 0x34); } #endif @@ -799,18 +799,18 @@ int cpu_init_r(void) { if (SVR_MAJ(svr) < 3) { void *p; - p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; + p = (void *)CFG_SYS_DCSRBAR + 0x20520; setbits_be32(p, 1 << (31 - 14)); } } #endif -#ifdef CONFIG_SYS_LBC_LCRR +#ifdef CFG_SYS_LBC_LCRR /* * Modify the CLKDIV field of LCRR register to improve the writing * speed for NOR flash. */ - clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); + clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CFG_SYS_LBC_LCRR); __raw_readl(&lbc->lcrr); isync(); #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 @@ -850,7 +850,7 @@ int cpu_init_r(void) */ if (IS_SVR_REV(get_svr(), 1, 0)) { struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) - (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); + (CFG_SYS_DCSRBAR + CFG_SYS_DCSR_DCFG_OFFSET); setbits_be32(&dcfg->ecccr1, (DCSR_DCFG_ECC_DISABLE_USB1 | DCSR_DCFG_ECC_DISABLE_USB2)); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 18bfa2aed14..a67f37e3af9 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -17,15 +17,15 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_A003399_NOR_WORKAROUND void setup_ifc(void) { - struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc_regs = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; u32 _mas0, _mas1, _mas2, _mas3, _mas7; - phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS; + phys_addr_t flash_phys = CFG_SYS_FLASH_BASE_PHYS; /* * Adjust the TLB we were running out of to match the phys addr of the * chip select we are adjusting and will return to. */ - flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024; + flash_phys += (~CFG_SYS_AMASK0) + 1 - 4*1024*1024; _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15); _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT | @@ -52,7 +52,7 @@ void setup_ifc(void) * * TLB entry is created for IVPR + IVOR15 to map on valid OP code address * bacause flash's physical address is going to change as - * CONFIG_SYS_FLASH_BASE_PHYS. + * CFG_SYS_FLASH_BASE_PHYS. */ _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB); @@ -72,9 +72,9 @@ void setup_ifc(void) #endif /* Change flash's physical address */ - ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); - ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0); - ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0); + ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CFG_SYS_CSPR0); + ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CFG_SYS_CSOR0); + ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CFG_SYS_AMASK0); return; } @@ -101,7 +101,7 @@ void cpu_init_early_f(void *fdt) #ifdef CONFIG_ARCH_QEMU_E500 /* - * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, + * CFG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, * so we need to populate it before it accesses it. */ gd->fdt_blob = fdt; @@ -109,9 +109,9 @@ void cpu_init_early_f(void *fdt) mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); - mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); + mas2 = FSL_BOOKE_MAS2(CFG_SYS_CCSRBAR, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CFG_SYS_CCSRBAR_PHYS); write_tlb(mas0, mas1, mas2, mas3, mas7); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 32348b4e147..a7e1df104d7 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -144,14 +144,14 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #ifdef CONFIG_DEEP_SLEEP #ifdef CONFIG_SPL_MMC_BOOT - off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START, - CONFIG_SYS_MMC_U_BOOT_SIZE); + off = fdt_add_mem_rsv(blob, CFG_SYS_MMC_U_BOOT_START, + CFG_SYS_MMC_U_BOOT_SIZE); if (off < 0) printf("Failed to reserve memory for SD deep sleep: %s\n", fdt_strerror(off)); #elif defined(CONFIG_SPL_SPI_BOOT) - off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START, - CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE); + off = fdt_add_mem_rsv(blob, CFG_SYS_SPI_FLASH_U_BOOT_START, + CFG_SYS_SPI_FLASH_U_BOOT_SIZE); if (off < 0) printf("Failed to reserve memory for SPI deep sleep: %s\n", fdt_strerror(off)); @@ -448,7 +448,7 @@ void fdt_add_enet_stashing(void *fdt) static void ft_fixup_clks(void *blob, const char *compat, u32 offset, unsigned long freq) { - phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; + phys_addr_t phys = offset + CFG_SYS_CCSRBAR_PHYS; int off = fdt_node_offset_by_compat_reg(blob, compat, phys); if (off >= 0) { @@ -679,17 +679,17 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) ft_fixup_dpaa_clks(blob); -#if defined(CONFIG_SYS_BMAN_MEM_PHYS) +#if defined(CFG_SYS_BMAN_MEM_PHYS) fdt_portal(blob, "fsl,bman-portal", "bman-portals", - (u64)CONFIG_SYS_BMAN_MEM_PHYS, - CONFIG_SYS_BMAN_MEM_SIZE); + (u64)CFG_SYS_BMAN_MEM_PHYS, + CFG_SYS_BMAN_MEM_SIZE); fdt_fixup_bportals(blob); #endif -#if defined(CONFIG_SYS_QMAN_MEM_PHYS) +#if defined(CFG_SYS_QMAN_MEM_PHYS) fdt_portal(blob, "fsl,qman-portal", "qman-portals", - (u64)CONFIG_SYS_QMAN_MEM_PHYS, - CONFIG_SYS_QMAN_MEM_SIZE); + (u64)CFG_SYS_QMAN_MEM_PHYS, + CFG_SYS_QMAN_MEM_SIZE); fdt_fixup_qportals(blob); #endif @@ -737,7 +737,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) * beginning of CCSR. */ #define CCSR_VIRT_TO_PHYS(x) \ - (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) + (CFG_SYS_CCSRBAR_PHYS + ((x) - CFG_SYS_CCSRBAR)) static void msg(const char *name, uint64_t uaddr, uint64_t daddr) { @@ -783,8 +783,8 @@ int ft_verify_fdt(void *fdt) return 0; } - if (addr != CONFIG_SYS_CCSRBAR_PHYS) { - msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr); + if (addr != CFG_SYS_CCSRBAR_PHYS) { + msg("CCSR", CFG_SYS_CCSRBAR_PHYS, addr); /* No point in checking anything else */ return 0; } @@ -818,12 +818,12 @@ int ft_verify_fdt(void *fdt) * the 'reg' property to be wrong, so check it here. For now, we * only check for "fsl,elbc" nodes. */ -#ifdef CONFIG_SYS_LBC_ADDR +#ifdef CFG_SYS_LBC_ADDR off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc"); if (off > 0) { const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL); if (reg) { - uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR); + uint64_t uaddr = CCSR_VIRT_TO_PHYS(CFG_SYS_LBC_ADDR); addr = fdt_translate_address(fdt, off, reg); if (uaddr != addr) { diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 3a6ce32f7e6..9b6577e547e 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -203,7 +203,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 struct ccsr_sfp_regs __iomem *sfp_regs = - (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR); + (struct ccsr_sfp_regs __iomem *)(CFG_SYS_SFP_ADDR); u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1; u32 bc_status, fc_status, dc_status, pll_sr2; serdes_corenet_t __iomem *srds_regs = (void *)sd_addr; diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 437ecde6155..7c2de02c4c5 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -264,9 +264,9 @@ void serdes_reset_rx(enum srds_prtcl device) } #endif -#ifndef CONFIG_SYS_DCSRBAR_PHYS -#define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ -#define CONFIG_SYS_DCSRBAR 0x80000000 +#ifndef CFG_SYS_DCSRBAR_PHYS +#define CFG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ +#define CFG_SYS_DCSRBAR 0x80000000 #define __DCSR_NOT_DEFINED_BY_CONFIG #endif @@ -315,16 +315,16 @@ static void enable_bank(ccsr_gur_t *gur, int bank) */ { #ifdef __DCSR_NOT_DEFINED_BY_CONFIG - struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS); + struct law_entry law = find_law(CFG_SYS_DCSRBAR_PHYS); int law_index; if (law.index == -1) - law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS, + law_index = set_next_law(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_DCSR); else - set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, + set_law(law.index, CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_DCSR); #endif - u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114; + u32 *p = (void *)CFG_SYS_DCSRBAR + 0x20114; out_be32(p, rcw5); #ifdef __DCSR_NOT_DEFINED_BY_CONFIG if (law.index == -1) diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 2b790868e12..540a6e6e191 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 2, 1, 0), SET_QP_INFO(3, 4, 2, 1), diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 7db05d9672b..8f645258a5f 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 2, 1, 0), SET_QP_INFO(3, 4, 2, 1), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index ba54b0310a7..db411162022 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO( 1, 2, 1, 0), SET_QP_INFO( 3, 4, 2, 1), diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index 6f11c81aba5..bd05eae2551 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 2, 1, 0), SET_QP_INFO(3, 4, 2, 1), diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index d37e1ccf1e7..391751ce1e7 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -276,8 +276,8 @@ __secondary_start_page: mtspr SPRN_L2CSR1,r3 #endif - lis r3,CONFIG_SYS_INIT_L2CSR0@h - ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l + lis r3,CFG_SYS_INIT_L2CSR0@h + ori r3,r3,CFG_SYS_INIT_L2CSR0@l mtspr SPRN_L2CSR0,r3 isync 2: diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index e2bdc2f9f11..a6e352ceabb 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -218,22 +218,22 @@ void get_sys_info(sys_info_t *sys_info) #ifndef CONFIG_PME_PLAT_CLK_DIV switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { case 1: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK]; break; case 2: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 2; break; case 3: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 3; break; case 4: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 4; break; case 6: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 2; break; case 7: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 3; break; default: printf("Error: Unknown PME clock select!\n"); @@ -243,7 +243,7 @@ void get_sys_info(sys_info_t *sys_info) } #else - sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; + sys_info->freq_pme = sys_info->freq_systembus / CFG_SYS_PME_CLK; #endif #endif @@ -380,25 +380,25 @@ void get_sys_info(sys_info_t *sys_info) #ifndef CONFIG_FM_PLAT_CLK_DIV switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { case 1: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK]; break; case 2: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 2; break; case 3: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 3; break; case 4: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 4; break; case 5: sys_info->freq_fman[0] = sys_info->freq_systembus; break; case 6: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 2; break; case 7: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 3; break; default: printf("Error: Unknown FMan1 clock select!\n"); @@ -407,31 +407,31 @@ void get_sys_info(sys_info_t *sys_info) break; } #if (CFG_SYS_NUM_FMAN) == 2 -#ifdef CONFIG_SYS_FM2_CLK +#ifdef CFG_SYS_FM2_CLK #define FM2_CLK_SEL 0x00000038 #define FM2_CLK_SHIFT 3 rcw_tmp = in_be32(&gur->rcwsr[15]); switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { case 1: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1]; break; case 2: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 2; break; case 3: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 3; break; case 4: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 4; break; case 5: sys_info->freq_fman[1] = sys_info->freq_systembus; break; case 6: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 2; break; case 7: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 3; break; default: printf("Error: Unknown FMan2 clock select!\n"); @@ -442,7 +442,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #endif /* CFG_SYS_NUM_FMAN == 2 */ #else - sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; + sys_info->freq_fman[0] = sys_info->freq_systembus / CFG_SYS_FM1_CLK; #endif #endif diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index 47df3c2ce19..ce2b9c21667 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -14,10 +14,10 @@ DECLARE_GLOBAL_DATA_PTR; ulong cpu_init_f(void) { -#ifdef CONFIG_SYS_INIT_L2_ADDR +#ifdef CFG_SYS_INIT_L2_ADDR ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; - out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); + out_be32(&l2cache->l2srbar0, CFG_SYS_INIT_L2_ADDR); /* set MBECCDIS=1, SBECCDIS=1 */ out_be32(&l2cache->l2errdis, diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 53417569743..562b6993b9d 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -128,7 +128,7 @@ bootsect: .Lconf_pair_start: .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */ - .long CONFIG_SYS_INIT_L2_ADDR + .long CFG_SYS_INIT_L2_ADDR .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */ .long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC @@ -428,12 +428,12 @@ l2_disabled: mtspr SPRN_BUCSR,r0 #endif -#if defined(CONFIG_SYS_INIT_DBCR) +#if defined(CFG_SYS_INIT_DBCR) lis r1,0xffff ori r1,r1,0xffff mtspr DBSR,r1 /* Clear all status bits */ - lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ - ori r0,r0,CONFIG_SYS_INIT_DBCR@l + lis r0,CFG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ + ori r0,r0,CFG_SYS_INIT_DBCR@l mtspr DBCR0,r0 #endif @@ -573,34 +573,34 @@ nexti: mflr r1 /* R1 = our PC */ * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for * long-term TLBs, so we use TLB0 here. */ -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS) -#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) -#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." +#if !defined(CFG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CFG_SYS_CCSRBAR_PHYS_LOW) +#error "CFG_SYS_CCSRBAR_PHYS_HIGH and CFG_SYS_CCSRBAR_PHYS_LOW) must be defined." #endif create_ccsr_new_tlb: /* * Create a TLB for the new location of CCSR. Register R8 is reserved - * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). + * for the virtual address of this TLB (CFG_SYS_CCSRBAR). */ - lis r8, CONFIG_SYS_CCSRBAR@h - ori r8, r8, CONFIG_SYS_CCSRBAR@l - lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h - ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l + lis r8, CFG_SYS_CCSRBAR@h + ori r8, r8, CFG_SYS_CCSRBAR@l + lis r9, (CFG_SYS_CCSRBAR + 0x1000)@h + ori r9, r9, (CFG_SYS_CCSRBAR + 0x1000)@l create_tlb0_entry 0, \ 0, BOOKE_PAGESZ_4K, \ - CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ - CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ - CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 + CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ + CFG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ + CFG_SYS_CCSRBAR_PHYS_HIGH, r3 /* * Create a TLB for the current location of CCSR. Register R9 is reserved - * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). + * for the virtual address of this TLB (CFG_SYS_CCSRBAR + 0x1000). */ create_ccsr_old_tlb: create_tlb0_entry 1, \ 0, BOOKE_PAGESZ_4K, \ - CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ + CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \ 0, r3 /* The default CCSR address is always a 32-bit number */ @@ -634,7 +634,7 @@ infinite_debug_loop: #ifdef CONFIG_FSL_CORENET -#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) +#define CCSR_LAWBARH0 (CFG_SYS_CCSRBAR + 0x1000) #define LAW_SIZE_4K 0xb #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) #define CCSRAR_C 0x80000000 /* Commit */ @@ -644,10 +644,10 @@ create_temp_law: * On CoreNet systems, we create the temporary LAW using a special LAW * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. */ - lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h - ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l - lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h - ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l + lis r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h + ori r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l + lis r1, CFG_SYS_CCSRBAR_PHYS_LOW@h + ori r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l lis r2, CCSRBAR_LAWAR@h ori r2, r2, CCSRBAR_LAWAR@l @@ -683,10 +683,10 @@ read_old_ccsrbar: * instruction. */ write_new_ccsrbar: - lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h - ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l - lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h - ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l + lis r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h + ori r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l + lis r1, CFG_SYS_CCSRBAR_PHYS_LOW@h + ori r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l lis r2, CCSRAR_C@h ori r2, r2, CCSRAR_C@l @@ -723,9 +723,9 @@ write_new_ccsrbar: lwz r0, 0(r9) isync -/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ -#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ - (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) +/* CFG_SYS_CCSRBAR_PHYS right shifted by 12 */ +#define CCSRBAR_PHYS_RS12 ((CFG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ + (CFG_SYS_CCSRBAR_PHYS_LOW >> 12)) /* Write the new value to CCSRBAR. */ lis r0, CCSRBAR_PHYS_RS12@h @@ -752,10 +752,10 @@ write_new_ccsrbar: /* Delete the temporary TLBs */ delete_temp_tlbs: - delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3 - delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3 + delete_tlb0_entry 0, CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3 + delete_tlb0_entry 1, CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3 -#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ +#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS) */ #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) create_ccsr_l2_tlb: @@ -765,14 +765,14 @@ create_ccsr_l2_tlb: */ create_tlb0_entry 0, \ 0, BOOKE_PAGESZ_4K, \ - CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ - CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ - CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 + CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ + CFG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ + CFG_SYS_CCSRBAR_PHYS_HIGH, r3 enable_l2_cluster_l2: /* enable L2 cache */ - lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h - ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l + lis r3, (CFG_SYS_CCSRBAR + 0xC20000)@h + ori r3, r3, (CFG_SYS_CCSRBAR + 0xC20000)@l li r4, 33 /* stash id */ stw r4, 4(r3) lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h @@ -813,7 +813,7 @@ enable_l2_cluster_l2: beq 1b delete_ccsr_l2_tlb: - delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 + delete_tlb0_entry 0, CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 #endif /* @@ -863,7 +863,7 @@ delete_ccsr_l2_tlb: andi. r1,r3,L1CSR0_DCE@l beq 2b #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 -#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) +#define DCSR_LAWBARH0 (CFG_SYS_CCSRBAR + 0x1000) #define LAW_SIZE_1M 0x13 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M) @@ -884,13 +884,13 @@ delete_ccsr_l2_tlb: rlwimi r0, r8, 16, MAS0_ESEL_MSK lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l - lis r7, CONFIG_SYS_CCSRBAR@h - ori r7, r7, CONFIG_SYS_CCSRBAR@l + lis r7, CFG_SYS_CCSRBAR@h + ori r7, r7, CFG_SYS_CCSRBAR@l ori r2, r7, MAS2_I|MAS2_G - lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h - ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l - lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h - ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + lis r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h + ori r3, r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l + lis r4, CFG_SYS_CCSRBAR_PHYS_HIGH@h + ori r4, r4, CFG_SYS_CCSRBAR_PHYS_HIGH@l mtspr MAS0, r0 mtspr MAS1, r1 mtspr MAS2, r2 @@ -1132,7 +1132,7 @@ create_init_ram_area: create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \ - CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 /* @@ -1148,7 +1148,7 @@ create_init_ram_area: create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \ - CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 #else @@ -1164,19 +1164,19 @@ create_init_ram_area: #endif /* create a temp mapping in AS=1 to the stack */ -#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ - defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) +#if defined(CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ + defined(CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH) create_tlb1_entry 14, \ 1, BOOKE_PAGESZ_16K, \ - CONFIG_SYS_INIT_RAM_ADDR, 0, \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6 + CFG_SYS_INIT_RAM_ADDR, 0, \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6 #else create_tlb1_entry 14, \ 1, BOOKE_PAGESZ_16K, \ - CONFIG_SYS_INIT_RAM_ADDR, 0, \ - CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_INIT_RAM_ADDR, 0, \ + CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 #endif @@ -1194,8 +1194,8 @@ switch_as: /* Allocate Initial RAM in data cache. */ - lis r3,CONFIG_SYS_INIT_RAM_ADDR@h - ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + lis r3,CFG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CFG_SYS_INIT_RAM_ADDR@l mfspr r2, L1CFG0 andi. r2, r2, 0x1ff /* cache size * 1024 / (2 * L1 line size) */ @@ -1230,11 +1230,11 @@ switch_as: .globl _start_cont _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ - lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h - ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ + lis r3,(CFG_SYS_INIT_RAM_ADDR)@h + ori r3,r3,((CFG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ #if CONFIG_VAL(SYS_MALLOC_F_LEN) -#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE #error "SYS_MALLOC_F_LEN too large to fit into initial RAM." #endif @@ -1243,8 +1243,8 @@ _start_cont: #endif /* End of RAM */ - lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h - ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l + lis r4,(CFG_SYS_INIT_RAM_ADDR)@h + ori r4,r4,(CFG_SYS_INIT_RAM_SIZE)@l li r0,0 @@ -1826,8 +1826,8 @@ trap_init: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h - ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l + lis r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h + ori r3,r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l mfspr r4,L1CFG0 andi. r4,r4,0x1ff slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) @@ -1844,8 +1844,8 @@ unlock_ram_in_cache: sync /* Invalidate the TLB entries for the cache */ - lis r3,CONFIG_SYS_INIT_RAM_ADDR@h - ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + lis r3,CFG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CFG_SYS_INIT_RAM_ADDR@l tlbivax 0,r3 addi r3,r3,0x1000 tlbivax 0,r3 diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c index d2744bb9f82..bab076b2b18 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index 99b52bacdad..59f4f9c6692 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c index 17521dc3a4a..390bb115375 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 8fe4e96a114..37ea7788ccf 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 81e60722f9f..5d21bef5878 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -302,7 +302,7 @@ uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { - unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; + unsigned int ram_tlb_address = (unsigned int)CFG_SYS_DDR_SDRAM_BASE; u64 memsize = (u64)memsize_in_meg << 20; u64 size; @@ -324,13 +324,13 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { return - setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); + setup_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg); } /* Invalidate the DDR TLBs for the requested size */ void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { - u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + u32 vstart = CFG_SYS_DDR_SDRAM_BASE; unsigned long epn; u32 tsize, valid, ptr; phys_addr_t rpn = 0; @@ -351,7 +351,7 @@ void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) void clear_ddr_tlbs(unsigned int memsize_in_meg) { - clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); + clear_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg); } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index f28826c5d1a..d918b4395bf 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -64,7 +64,7 @@ SECTIONS _end = .; #if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) -#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS) +#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS) mmc_u_boot_offs = .; #endif #endif @@ -101,7 +101,7 @@ SECTIONS .resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : { KEEP(*(.resetvec)) } = 0xffff -#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS) +#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS) mmc_u_boot_offs = .; #endif #endif diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index 0ebb7b33a8b..1f1107e61d5 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -141,8 +141,8 @@ in_flash: mtspr DER, r2 /* set up the stack on top of internal DPRAM */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l + lis r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@h + ori r3, r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@l stw r0, -4(r3) stw r0, -8(r3) addi r1, r3, -8 diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 1101b9138f1..1c051d18980 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -230,7 +230,7 @@ static int pamu_config_spaace(uint32_t liodn, int pamu_init(void) { - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; struct ccsr_pamu *regs; u32 i = 0; u64 ppaact_phys, ppaact_lim, ppaact_size; @@ -292,7 +292,7 @@ int pamu_init(void) void pamu_enable(void) { u32 i = 0; - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; for (i = 0; i < CONFIG_NUM_PAMU; i++) { setbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE); @@ -304,7 +304,7 @@ void pamu_enable(void) void pamu_reset(void) { u32 i = 0; - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; struct ccsr_pamu *regs; for (i = 0; i < CONFIG_NUM_PAMU; i++) { @@ -328,7 +328,7 @@ void pamu_reset(void) void pamu_disable(void) { u32 i = 0; - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; for (i = 0; i < CONFIG_NUM_PAMU; i++) { diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index 71496ab294d..caad6670cc9 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -21,17 +21,17 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; i++; -#ifdef CONFIG_SYS_FLASH_BASE_PHYS +#ifdef CFG_SYS_FLASH_BASE_PHYS tbl->start_addr[i] = - (uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS); + (uint64_t)virt_to_phys((void *)CFG_SYS_FLASH_BASE_PHYS); tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */ tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; i++; #endif -#if (defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_INIT_L3_VADDR)) +#if (defined(CONFIG_SPL_BUILD) && (CFG_SYS_INIT_L3_VADDR)) tbl->start_addr[i] = - (uint64_t)virt_to_phys((void *)CONFIG_SYS_INIT_L3_VADDR); + (uint64_t)virt_to_phys((void *)CFG_SYS_INIT_L3_VADDR); tbl->size[i] = 256 * 1024; /* 256K CPC flash */ tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 2edf0d6f83c..d9e5a7d6217 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -43,9 +43,9 @@ #elif defined(CONFIG_ARCH_P1023) #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 2 -#define CONFIG_SYS_QMAN_NUM_PORTALS 3 -#define CONFIG_SYS_BMAN_NUM_PORTALS 3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 +#define CFG_SYS_QMAN_NUM_PORTALS 3 +#define CFG_SYS_BMAN_NUM_PORTALS 3 +#define CFG_SYS_FM_MURAM_SIZE 0x10000 /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) @@ -68,7 +68,7 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 5 #define CFG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -78,7 +78,7 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 5 #define CFG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -90,7 +90,7 @@ #define CFG_SYS_NUM_FM2_DTSEC 4 #define CFG_SYS_NUM_FM1_10GEC 1 #define CFG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -103,7 +103,7 @@ #define CFG_SYS_NUM_FM1_10GEC 1 #define CFG_SYS_NUM_FM2_DTSEC 5 #define CFG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_BSC9131) @@ -134,11 +134,11 @@ #define CFG_SYS_FSL_SRDS_3 #define CFG_SYS_FSL_SRDS_4 #define CFG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_PME_CLK 0 +#define CFG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM1_CLK 3 -#define CONFIG_SYS_FM2_CLK 3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM1_CLK 3 +#define CFG_SYS_FM2_CLK 3 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -147,9 +147,9 @@ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 #define CFG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_FM1_CLK 0 +#define CFG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #ifdef CONFIG_ARCH_B4860 #define CONFIG_MAX_DSP_CPUS 12 @@ -173,11 +173,11 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_PME_PLAT_CLK_DIV 2 -#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_FM_PLAT_CLK_DIV 1 -#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV -#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CFG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV +#define CFG_SYS_FM_MURAM_SIZE 0x30000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -191,9 +191,9 @@ #define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM1_CLK 0 +#define CFG_SYS_FM1_CLK 0 #define CONFIG_QBMAN_CLK_DIV 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CFG_SYS_FM_MURAM_SIZE 0x30000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -212,10 +212,10 @@ #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #endif #define CONFIG_PME_PLAT_CLK_DIV 1 -#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV -#define CONFIG_SYS_FM1_CLK 0 +#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CFG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 5038cb9f590..a03f091c305 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -469,7 +469,7 @@ extern void print_lbc_regs(void); extern void init_early_memctl_regs(void); extern void upmconfig(uint upm, uint *table, uint size); -#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR) +#define LBC_BASE_ADDR ((fsl_lbc_t *)CFG_SYS_LBC_ADDR) #define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr)) #define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr)) #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br)) diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index de85bcfdcf9..0af3d8902ac 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -18,15 +18,15 @@ struct srio_liodn_id_table { #define SET_SRIO_LIODN_1(port, idA) \ { .id = { idA }, .num_ids = 1, .portid = port, \ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ } #define SET_SRIO_LIODN_2(port, idA, idB) \ { .id = { idA, idB }, .num_ids = 2, .portid = port, \ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ } #define SET_SRIO_LIODN_BASE(port, id_a) \ @@ -70,22 +70,22 @@ extern void fdt_fixup_liodn(void *blob); { .compat[0] = name1, \ .compat[1] = name2, \ .id = { idA }, .num_ids = 1, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ { .compat = name, \ .id = { idA }, .num_ids = 1, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ { .compat = name, \ .id = { idA, idB }, .num_ids = 2, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_GUTS_LIODN(compat, liodn, name, compatoff) \ diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 3e707600f28..e8b26802062 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -9,11 +9,11 @@ #ifdef CONFIG_NXP_ESBC #if defined(CONFIG_FSL_CORENET) -#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 +#define CFG_SYS_PBI_FLASH_BASE 0xc0000000 #else -#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 +#define CFG_SYS_PBI_FLASH_BASE 0xce000000 #endif -#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 +#define CFG_SYS_PBI_FLASH_WINDOW 0xcff80000 #if defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ @@ -21,18 +21,18 @@ defined(CONFIG_TARGET_T1042D4RDB) || \ defined(CONFIG_TARGET_T1042RDB_PI) || \ defined(CONFIG_ARCH_T1024) -#undef CONFIG_SYS_INIT_L3_ADDR -#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#undef CFG_SYS_INIT_L3_ADDR +#define CFG_SYS_INIT_L3_ADDR 0xbff00000 #endif #if defined(CONFIG_RAMBOOT_PBL) -#undef CONFIG_SYS_INIT_L3_ADDR -#ifdef CONFIG_SYS_INIT_L3_VADDR -#define CONFIG_SYS_INIT_L3_ADDR \ - (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ +#undef CFG_SYS_INIT_L3_ADDR +#ifdef CFG_SYS_INIT_L3_VADDR +#define CFG_SYS_INIT_L3_ADDR \ + (CFG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ 0xbff00000 #else -#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#define CFG_SYS_INIT_L3_ADDR 0xbff00000 #endif #endif diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 8e182026708..19774f3053b 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -871,11 +871,11 @@ struct ccsr_gpio { #define CFG_SYS_MPC83xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET) -#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) +#define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_MDIO1_OFFSET 0x24000 +#define CFG_SYS_TSEC1_OFFSET 0x24000 +#define CFG_SYS_MDIO1_OFFSET 0x24000 -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #endif /* __IMMAP_83xx__ */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 9ae698743ee..283fdf3b458 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2445,10 +2445,10 @@ struct ccsr_pman { #ifdef CONFIG_SYS_FSL_SFP_VER_3_0 /* In SFPv3, OSPR register is now at offset 0x200. * * So directly mapping sfp register map to this address */ -#define CONFIG_SYS_OSPR_OFFSET 0x200 -#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET) +#define CFG_SYS_OSPR_OFFSET 0x200 +#define CFG_SYS_SFP_OFFSET (0xE8000 + CFG_SYS_OSPR_OFFSET) #else -#define CONFIG_SYS_SFP_OFFSET 0xE8000 +#define CFG_SYS_SFP_OFFSET 0xE8000 #endif #define CFG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 #define CFG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 @@ -2489,7 +2489,7 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CFG_SYS_FSL_SEC_OFFSET 0x300000 #define CFG_SYS_FSL_JR0_OFFSET 0x301000 -#define CONFIG_SYS_SEC_MON_OFFSET 0x314000 +#define CFG_SYS_SEC_MON_OFFSET 0x314000 #define CFG_SYS_FSL_CORENET_PME_OFFSET 0x316000 #define CFG_SYS_FSL_QMAN_OFFSET 0x318000 #define CFG_SYS_FSL_BMAN_OFFSET 0x31a000 @@ -2542,13 +2542,13 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000 #define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100 #ifdef CONFIG_TSECV2 -#define CONFIG_SYS_TSEC1_OFFSET 0xB0000 +#define CFG_SYS_TSEC1_OFFSET 0xB0000 #elif defined(CONFIG_TSECV2_1) -#define CONFIG_SYS_TSEC1_OFFSET 0x10000 +#define CFG_SYS_TSEC1_OFFSET 0x10000 #else -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CFG_SYS_TSEC1_OFFSET 0x24000 #endif -#define CONFIG_SYS_MDIO1_OFFSET 0x24000 +#define CFG_SYS_MDIO1_OFFSET 0x24000 #define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #if defined(CONFIG_ARCH_C29X) #define CFG_SYS_FSL_SEC_OFFSET 0x80000 @@ -2559,8 +2559,8 @@ struct ccsr_pman { #endif #define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 -#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000 -#define CONFIG_SYS_SFP_OFFSET 0xE7000 +#define CFG_SYS_SEC_MON_OFFSET 0xE6000 +#define CFG_SYS_SFP_OFFSET 0xE7000 #define CFG_SYS_FSL_QMAN_OFFSET 0x88000 #define CFG_SYS_FSL_BMAN_OFFSET 0x8a000 #define CFG_SYS_FSL_FM1_OFFSET 0x100000 @@ -2574,9 +2574,9 @@ struct ccsr_pman { #define CFG_SYS_FSL_SRIO_OFFSET 0xC0000 #define CFG_SYS_FSL_CPC_ADDR \ - (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET) + (CFG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET) #define CFG_SYS_FSL_SCFG_ADDR \ - (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET) + (CFG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET) #define CFG_SYS_FSL_QMAN_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET) #define CFG_SYS_FSL_BMAN_ADDR \ @@ -2603,9 +2603,9 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET) #define CFG_SYS_FSL_DDR3_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET) -#define CONFIG_SYS_LBC_ADDR \ +#define CFG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET) -#define CONFIG_SYS_IFC_ADDR \ +#define CFG_SYS_IFC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET) #define CFG_SYS_MPC85xx_ESPI_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET) @@ -2659,7 +2659,7 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET) #define CFG_SYS_FSL_SRIO_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET) -#define CONFIG_SYS_PAMU_ADDR \ +#define CFG_SYS_PAMU_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET) #define CFG_SYS_PCIE1_ADDR \ @@ -2667,14 +2667,14 @@ struct ccsr_pman { #define CFG_SYS_PCIE2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET) -#define CONFIG_SYS_SFP_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET) +#define CFG_SYS_SFP_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_SFP_OFFSET) -#define CONFIG_SYS_SEC_MON_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET) +#define CFG_SYS_SEC_MON_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_SEC_MON_OFFSET) -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 struct ccsr_cluster_l2 { @@ -2735,7 +2735,7 @@ struct ccsr_cluster_l2 { (CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET) #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ -#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000 +#define CFG_SYS_DCSR_DCFG_OFFSET 0X20000 struct dcsr_dcfg_regs { u8 res_0[0x520]; u32 ecccr1; diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c index d4a6057527c..b638ea7be61 100644 --- a/arch/powerpc/lib/spl.c +++ b/arch/powerpc/lib/spl.c @@ -23,7 +23,7 @@ void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) image_entry_arg_t image_entry = (image_entry_arg_t)spl_image->entry_point; - image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, + image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CFG_SYS_BOOTMAPSZ, 0, 0); } #endif /* CONFIG_SPL_OS_BOOT */ diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h index 99d8797a549..03c196fec3b 100644 --- a/arch/sh/include/asm/config.h +++ b/arch/sh/include/asm/config.h @@ -9,7 +9,7 @@ #include /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4) +#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ +#define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 4) #endif diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c index c11101b44ec..1eb97ac5bb1 100644 --- a/arch/x86/lib/physmem.c +++ b/arch/x86/lib/physmem.c @@ -144,7 +144,7 @@ static void x86_phys_memset_page(phys_addr_t map_addr, uintptr_t offset, int c, /* Make sure the window is below U-Boot. */ assert(window + LARGE_PAGE_SIZE < - gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_STACK_SIZE); + gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CFG_SYS_STACK_SIZE); /* Map the page into the window and then memset the appropriate part. */ x86_phys_map_page(window, map_addr, 1); memset((void *)(window + offset), c, size); diff --git a/arch/xtensa/include/asm/addrspace.h b/arch/xtensa/include/asm/addrspace.h index 3b27f9308a0..920b5fd26b2 100644 --- a/arch/xtensa/include/asm/addrspace.h +++ b/arch/xtensa/include/asm/addrspace.h @@ -22,8 +22,8 @@ * The actual location of memory and IO is the board property. */ -#define IOADDR(x) (CONFIG_SYS_IO_BASE + (x)) -#define MEMADDR(x) (CONFIG_SYS_MEMORY_BASE + (x)) +#define IOADDR(x) (CFG_SYS_IO_BASE + (x)) +#define MEMADDR(x) (CFG_SYS_MEMORY_BASE + (x)) #define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \ XCHAL_VECBASE_RESET_PADDR) diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c index f9a37e7215c..ea49c7a99c0 100644 --- a/board/BuS/eb_cpu5282/eb_cpu5282.c +++ b/board/BuS/eb_cpu5282/eb_cpu5282.c @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR; int checkboard (void) { puts("Board: EB+CPU5282 (BuS Elektronik GmbH & Co. KG)\n"); -#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) puts(" Boot from Internal FLASH\n"); #endif return 0; @@ -38,7 +38,7 @@ int dram_init(void) size = 0; MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 | - MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4); + MCFSDRAMC_DCR_RC((15 * CFG_SYS_CLK / 1000000) >> 4); asm (" nop"); #ifdef CFG_SYS_SDRAM_BASE0 MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE0)| @@ -94,7 +94,7 @@ int dram_init(void) return 0; } -#if defined(CONFIG_SYS_DRAM_TEST) +#if defined(CFG_SYS_DRAM_TEST) int testdram(void) { uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 695d6f6ed47..91709134000 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -88,7 +88,7 @@ int board_init(void) #if defined(CONFIG_MISC_INIT_R) -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR) +#if defined(CONFIG_CMD_I2C) && defined(CFG_SYS_I2C_G762_ADDR) /* * Start I2C fan (GMT G762 controller) */ @@ -100,11 +100,11 @@ static void init_fan(void) /* Enable open-loop and PWM modes */ data = 0x20; - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR, + if (i2c_write(CFG_SYS_I2C_G762_ADDR, G762_REG_FAN_CMD1, 1, &data, 1) != 0) goto err; data = 0; - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR, + if (i2c_write(CFG_SYS_I2C_G762_ADDR, G762_REG_SET_CNT, 1, &data, 1) != 0) goto err; /* @@ -124,18 +124,18 @@ static void init_fan(void) * Start fan at low speed (2800 RPM): */ data = 0x08; - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR, + if (i2c_write(CFG_SYS_I2C_G762_ADDR, G762_REG_SET_OUT, 1, &data, 1) != 0) goto err; return; err: printf("Error: failed to start I2C fan @%02x\n", - CONFIG_SYS_I2C_G762_ADDR); + CFG_SYS_I2C_G762_ADDR); } #else static void init_fan(void) {} -#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */ +#endif /* CONFIG_CMD_I2C && CFG_SYS_I2C_G762_ADDR */ #if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO) /* diff --git a/board/Synology/common/legacy.c b/board/Synology/common/legacy.c index 06f964f53a3..a0bace7b46c 100644 --- a/board/Synology/common/legacy.c +++ b/board/Synology/common/legacy.c @@ -56,8 +56,8 @@ void setup_board_tags(struct tag **in_params) t = (struct tag_mv_uboot *)¶ms->u; t->uboot_version = VER_NUM | syno_board_id(); - t->tclk = CONFIG_SYS_TCLK; - t->sysclk = CONFIG_SYS_TCLK * 2; + t->tclk = CFG_SYS_TCLK; + t->sysclk = CFG_SYS_TCLK * 2; t->isusbhost = usb_port_modes(); for (i = 0; i < ETHADDR_MAX; i++) { diff --git a/board/armltd/integrator/timer.c b/board/armltd/integrator/timer.c index d220b877d66..9db5135a8ff 100644 --- a/board/armltd/integrator/timer.c +++ b/board/armltd/integrator/timer.c @@ -41,10 +41,10 @@ static unsigned long long div_clock = DIV_CLOCK_INIT; static unsigned long long div_timer = 1; /* Divisor to convert timer reading * change to U-Boot ticks */ -/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */ +/* CONFIG_SYS_HZ = CFG_SYS_HZ_CLOCK/(div_clock * div_timer) */ static ulong timestamp; /* U-Boot ticks since startup */ -#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) +#define READ_TIMER (*(volatile ulong *)(CFG_SYS_TIMERBASE+4)) /* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec * - unless otherwise stated @@ -55,7 +55,7 @@ static ulong timestamp; /* U-Boot ticks since startup */ int timer_init (void) { /* Load timer with initial value */ - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL; #ifdef CONFIG_ARCH_CINTEGRATOR /* Set timer to be * enabled 1 @@ -66,7 +66,7 @@ int timer_init (void) * 32 bit 1 * wrapping 0 */ - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = 0x000000C2; #else /* Set timer to be * enabled 1 @@ -75,7 +75,7 @@ int timer_init (void) * divider 256 10 * XX 00 */ - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = 0x00000088; #endif /* init the timestamp */ @@ -85,7 +85,7 @@ int timer_init (void) /* start "advancing" time stamp from 0 */ timestamp = 0L; - div_timer = CONFIG_SYS_HZ_CLOCK; + div_timer = CFG_SYS_HZ_CLOCK; do_div(div_timer, CONFIG_SYS_HZ); do_div(div_timer, div_clock); @@ -156,7 +156,7 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - unsigned long long tmp = CONFIG_SYS_HZ_CLOCK; + unsigned long long tmp = CFG_SYS_HZ_CLOCK; do_div(tmp, div_clock); diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index af326dc6f45..4ca544f1017 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -108,7 +108,7 @@ unsigned long __section(".data") prior_stage_fdt_address[2]; #define JUNO_FLASH_SEC_SIZE (256 * 1024) static phys_addr_t find_dtb_in_nor_flash(const char *partname) { - phys_addr_t sector = CONFIG_SYS_FLASH_BASE; + phys_addr_t sector = CFG_SYS_FLASH_BASE; int i; for (i = 0; @@ -140,7 +140,7 @@ static phys_addr_t find_dtb_in_nor_flash(const char *partname) imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg; reg = readl(imginfo + 0x54); - return CONFIG_SYS_FLASH_BASE + + return CFG_SYS_FLASH_BASE + reg * JUNO_FLASH_SEC_SIZE; } } diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c index ade7f9d120a..f38f5564a06 100644 --- a/board/cadence/xtfpga/xtfpga.c +++ b/board/cadence/xtfpga/xtfpga.c @@ -58,8 +58,8 @@ unsigned long get_board_sys_clk(void) * else non-zero (hang). */ -#ifdef CONFIG_SYS_FPGAREG_FREQ - return (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ); +#ifdef CFG_SYS_FPGAREG_FREQ + return (*(volatile unsigned long *)CFG_SYS_FPGAREG_FREQ); #else /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */ return 50000000; @@ -90,7 +90,7 @@ int misc_init_r(void) if (s == 0) { unsigned int x; char s[] = __stringify(CONFIG_ETHBASE); - x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW) + x = (*(volatile u32 *)CFG_SYS_FPGAREG_DIPSW) & FPGAREG_MAC_MASK; sprintf(&s[15], "%02x", x); env_set("ethaddr", s); @@ -106,9 +106,9 @@ U_BOOT_DRVINFO(sysreset) = { static struct ethoc_eth_pdata ethoc_pdata = { .eth_pdata = { - .iobase = CONFIG_SYS_ETHOC_BASE, + .iobase = CFG_SYS_ETHOC_BASE, }, - .packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR, + .packet_base = CFG_SYS_ETHOC_BUFFER_ADDR, }; U_BOOT_DRVINFO(ethoc) = { diff --git a/board/cavium/thunderx/atf.c b/board/cavium/thunderx/atf.c index 1a039c53c14..37340fe9700 100644 --- a/board/cavium/thunderx/atf.c +++ b/board/cavium/thunderx/atf.c @@ -187,7 +187,7 @@ static void atf_print_part_table(void) int ret; char *ptype; - struct storage_partition *part = (void *)CONFIG_SYS_LOWMEM_BASE; + struct storage_partition *part = (void *)CFG_SYS_LOWMEM_BASE; pcount = atf_get_pcount(); diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index a8f8c785584..ab20825ed36 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -20,7 +20,7 @@ #include static const struct pl01x_serial_plat serial0 = { - .base = CONFIG_SYS_SERIAL0, + .base = CFG_SYS_SERIAL0, .type = TYPE_PL011, .clock = 0, .skip_init = true, @@ -32,7 +32,7 @@ U_BOOT_DRVINFO(thunderx_serial0) = { }; static const struct pl01x_serial_plat serial1 = { - .base = CONFIG_SYS_SERIAL1, + .base = CFG_SYS_SERIAL1, .type = TYPE_PL011, .clock = 0, .skip_init = true, diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c index 5d15ed4e691..8416af163ad 100644 --- a/board/cobra5272/flash.c +++ b/board/cobra5272/flash.c @@ -12,7 +12,7 @@ #include #include -#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE +#define PHYS_FLASH_1 CFG_SYS_FLASH_BASE #define FLASH_BANK_SIZE 0x200000 flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; @@ -102,8 +102,8 @@ unsigned long flash_init(void) } flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]); + CFG_SYS_FLASH_BASE, + CFG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]); return size; } @@ -117,8 +117,8 @@ unsigned long flash_init(void) #define CMD_PROGRAM 0x00A0 #define CMD_UNLOCK_BYPASS 0x0020 -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1))) +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_SYS_FLASH_BASE + (0x00000555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_SYS_FLASH_BASE + (0x000002AA<<1))) #define BIT_ERASE_DONE 0x0080 #define BIT_RDY_MASK 0x0080 diff --git a/board/cortina/presidio-asic/lowlevel_init.S b/board/cortina/presidio-asic/lowlevel_init.S index cbf8134346d..8d8842ebedf 100644 --- a/board/cortina/presidio-asic/lowlevel_init.S +++ b/board/cortina/presidio-asic/lowlevel_init.S @@ -27,7 +27,7 @@ skip_smp_setup: #if defined(CONFIG_SOC_CA8277B) /* Enable CPU Timer */ - ldr x0, =CONFIG_SYS_TIMER_BASE + ldr x0, =CFG_SYS_TIMER_BASE mov x1, #1 str w1, [x0] #endif diff --git a/board/cortina/presidio-asic/presidio.c b/board/cortina/presidio-asic/presidio.c index f344622b024..aae0a5dac06 100644 --- a/board/cortina/presidio-asic/presidio.c +++ b/board/cortina/presidio-asic/presidio.c @@ -84,7 +84,7 @@ int board_init(void) unsigned int reg_data, jtag_id; /* Enable timer */ - writel(1, CONFIG_SYS_TIMER_BASE); + writel(1, CFG_SYS_TIMER_BASE); /* Enable snoop in CCI400 slave port#4 */ writel(3, 0xF5595000); diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 2436aab71cc..e3a0f266a4c 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -371,20 +371,20 @@ int rmii_hw_init(void) /* Set polarity to non-inverted */ buf[0] = 0x0; buf[1] = 0x0; - ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); + ret = i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); if (ret) { printf("\nExpander @ 0x%02x write FAILED!!!\n", - CONFIG_SYS_I2C_EXPANDER_ADDR); + CFG_SYS_I2C_EXPANDER_ADDR); return ret; } /* Configure P07-P05 as outputs */ buf[0] = 0x1f; buf[1] = 0xff; - ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); + ret = i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); if (ret) { printf("\nExpander @ 0x%02x write FAILED!!!\n", - CONFIG_SYS_I2C_EXPANDER_ADDR); + CFG_SYS_I2C_EXPANDER_ADDR); } /* For Ethernet RMII selection @@ -392,16 +392,16 @@ int rmii_hw_init(void) * P06(SelB)=1 * P05(SelC)=1 */ - if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { + if (i2c_read(CFG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { printf("\nExpander @ 0x%02x read FAILED!!!\n", - CONFIG_SYS_I2C_EXPANDER_ADDR); + CFG_SYS_I2C_EXPANDER_ADDR); } buf[0] &= 0x1f; buf[0] |= (0 << 7) | (1 << 6) | (1 << 5); - if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { + if (i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { printf("\nExpander @ 0x%02x write FAILED!!!\n", - CONFIG_SYS_I2C_EXPANDER_ADDR); + CFG_SYS_I2C_EXPANDER_ADDR); } /* Set the output as high */ diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index 913c2ea1664..ceb0d2cf0aa 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -193,6 +193,6 @@ int board_mmc_init(struct bd_info *bd) int board_mmc_getcd(struct mmc *mmc) { - return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN); + return !at91_get_pio_value(CFG_SYS_MMC_CD_PIN); } #endif diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index a4254250bbf..a39bcb4fa0c 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -41,7 +41,7 @@ static void *get_fdt_virt(void) if (gd->flags & GD_FLG_RELOC) return (void *)gd->fdt_blob; else - return (void *)CONFIG_SYS_TMPVIRT; + return (void *)CFG_SYS_TMPVIRT; } static uint64_t get_fdt_phys(void) @@ -163,7 +163,7 @@ int misc_init_r(void) * U-Boot is relocated to RAM already, let's delete the temporary FDT * virtual-physical mapping that was used in the pre-relocation phase. */ - disable_tlb(find_tlb_idx((void *)CONFIG_SYS_TMPVIRT, 1)); + disable_tlb(find_tlb_idx((void *)CFG_SYS_TMPVIRT, 1)); /* * Detect the presence of the platform bus node, and @@ -248,7 +248,7 @@ void init_tlbs(void) init_used_tlb_cams(); /* Create a dynamic AS=0 CCSRBAR mapping */ - assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + assert(!tlb_map_range(CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, 1024 * 1024, TLB_MAP_IO)); /* Create a RAM map that spans all accessible RAM */ diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 2304e9e8ec3..21f4ba98b53 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -240,7 +240,7 @@ int misc_init_r(void) if (str && (strcmp(str, "4") == 0)) { writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) | AT91SAM9_PMC_MDIV_4, &pmc->mckr); - at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); serial_setbrg(); /* Notify the user that the clock is not default */ printf("Setting master clock to %s MHz\n", diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index d31ad026568..9ca350ed468 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -43,7 +43,7 @@ int fsl_check_boot_mode_secure(void) { uint32_t val; - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR); val = sfp_in32(&sfp_regs->ospr) & ITS_MASK; diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 3424d49208f..285ed9afcc9 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -85,7 +85,7 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); - u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE); + u32 csf_flash_offset = csf_hdr_addr & ~(CFG_SYS_PBI_FLASH_BASE); u32 flash_addr, addr; int found = 0; int i = 0; @@ -160,7 +160,7 @@ static int get_ie_info_addr(uintptr_t *ie_addr) */ #if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) sg_tbl = (struct fsl_secboot_sg_table *) - (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + + (((u32)hdr->psgtable & ~(CFG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr + @@ -170,7 +170,7 @@ static int get_ie_info_addr(uintptr_t *ie_addr) /* IE Key Table is the first entry in the SG Table */ #if defined(CONFIG_MPC85xx) *ie_addr = (uintptr_t)((sg_tbl->src_addr & - ~(CONFIG_SYS_PBI_FLASH_BASE)) + + ~(CFG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else *ie_addr = (uintptr_t)sg_tbl->src_addr; @@ -203,7 +203,7 @@ static u32 check_srk(struct fsl_secboot_img_priv *img) /* This function returns ospr's key_revoc values.*/ static u32 get_key_revoc(void) { - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >> OSPR_KEY_REVOC_SHIFT; } @@ -342,7 +342,7 @@ static inline u32 get_key_len(struct fsl_secboot_img_priv *img) */ static void fsl_secboot_header_verification_failure(void) { - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); /* 29th bit of OSPR is ITS */ u32 its = sfp_in32(&sfp_regs->ospr) >> 2; @@ -367,7 +367,7 @@ static void fsl_secboot_header_verification_failure(void) */ static void fsl_secboot_image_verification_failure(void) { - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT; @@ -871,7 +871,7 @@ static int secboot_init(struct fsl_secboot_img_priv **img_ptr) int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, uintptr_t *img_addr_ptr) { - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); ulong hash[SHA256_BYTES/sizeof(ulong)]; char hash_str[NUM_HEX_CHARS + 1]; struct fsl_secboot_img_priv *img; diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 8951fae32d3..1a1e9343d23 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -11,12 +11,12 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), #endif #ifdef PIXIS_BASE_PHYS SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), @@ -24,9 +24,9 @@ struct law_entry law_table[] = { #ifdef CPLD_BASE_PHYS SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 7302b760662..1a2d9cbfc0c 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -11,20 +11,20 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), #ifdef CPLD_BASE @@ -41,25 +41,25 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) #if !defined(CONFIG_NXP_ESBC) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #else /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot - * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR, + * the physical address of the SRAM is at CFG_SYS_INIT_L3_ADDR, * and virtual address is CONFIG_SYS_MONITOR_BASE */ SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000, - CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, + CFG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #endif @@ -80,13 +80,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -112,26 +112,26 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 6, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x00100000, + CFG_SYS_BMAN_MEM_PHYS + 0x00100000, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_1M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SW|MAS3_SR, 0, 0, 11, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x00100000, + CFG_SYS_QMAN_MEM_PHYS + 0x00100000, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_1M, 1), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_4M, 1), #endif diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 2bb838cea6c..da2c1de078b 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -29,15 +29,15 @@ #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #endif -#ifdef CONFIG_SYS_I2C_FPGA_ADDR +#ifdef CFG_SYS_I2C_FPGA_ADDR u8 qixis_read_i2c(unsigned int reg) { #if !CONFIG_IS_ENABLED(DM_I2C) - return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg); + return i2c_reg_read(CFG_SYS_I2C_FPGA_ADDR, reg); #else struct udevice *dev; - if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev)) + if (i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev)) return 0xff; return dm_i2c_reg_read(dev, reg); @@ -48,11 +48,11 @@ void qixis_write_i2c(unsigned int reg, u8 value) { u8 val = value; #if !CONFIG_IS_ENABLED(DM_I2C) - i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val); + i2c_reg_write(CFG_SYS_I2C_FPGA_ADDR, reg, val); #else struct udevice *dev; - if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev)) + if (!i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev)) dm_i2c_reg_write(dev, reg, val); #endif diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index af76327e4d2..784046ac4e0 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -100,12 +100,12 @@ u16 qixis_read_minor(void); char *qixis_read_time(char *result); char *qixis_read_tag(char *buf); const char *byte_to_binary_mask(u8 val, u8 mask, char *buf); -#ifdef CONFIG_SYS_I2C_FPGA_ADDR +#ifdef CFG_SYS_I2C_FPGA_ADDR u8 qixis_read_i2c(unsigned int reg); void qixis_write_i2c(unsigned int reg, u8 value); #endif -#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR) +#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CFG_SYS_I2C_FPGA_ADDR) #define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg)) #define QIXIS_WRITE(reg, value) \ qixis_write_i2c(offsetof(struct qixis, reg), value) @@ -114,7 +114,7 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) #endif -#ifdef CONFIG_SYS_I2C_FPGA_ADDR +#ifdef CFG_SYS_I2C_FPGA_ADDR #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg)) #define QIXIS_WRITE_I2C(reg, value) \ qixis_write_i2c(offsetof(struct qixis, reg), value) diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index f17a6c186d3..194b5d27295 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -117,7 +117,7 @@ int misc_init_r(void) struct udevice *dev; int ret; - ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR, + ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_FPGA_ADDR, 1, &dev); if (ret) { printf("%s: Cannot find udev for a bus %d\n", __func__, @@ -128,7 +128,7 @@ int misc_init_r(void) #else i2c_set_bus_num(bus_num); - i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); + i2c_write(CFG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); #endif return 0; diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d0674d014ac..d5cb7312095 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -196,7 +196,7 @@ void board_init_f(ulong dummy) porsr1 = in_be32(&gur->porsr1); pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | DCFG_CCSR_PORSR1_RCW_SRC_I2C); - out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), + out_be32((unsigned int *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), pinctl); #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 8b74d458237..4f5834347db 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -98,7 +98,7 @@ struct cpld_data { #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) static void cpld_show(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n", in_8(&cpld_data->cpld_ver) & VERSION_MASK, @@ -248,7 +248,7 @@ int board_eth_init(struct bd_info *bis) static void convert_serdes_mux(int type, int need_reset) { char current_serdes; - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); current_serdes = cpld_data->serdes_mux; @@ -322,7 +322,7 @@ int config_serdes_mux(void) #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) int config_board_mux(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); int conflict_flag; conflict_flag = 0; @@ -610,7 +610,7 @@ u16 flash_read16(void *addr) && !defined(CONFIG_SPL_BUILD) static void convert_flash_bank(char bank) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); printf("Now switch to boot from flash bank %d.\n", bank); cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK; @@ -644,7 +644,7 @@ U_BOOT_CMD( static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); if (argc > 2) return CMD_RET_USAGE; @@ -671,7 +671,7 @@ U_BOOT_CMD( static void print_serdes_mux(void) { char current_serdes; - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); current_serdes = cpld_data->serdes_mux; diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 5fe40c4bdb2..841d8b59bb4 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -57,8 +57,8 @@ enum { struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nor0", - CONFIG_SYS_NOR0_CSPR, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -71,8 +71,8 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor1", - CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -97,15 +97,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, - CONFIG_SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, { - CONFIG_SYS_FPGA_FTIM0, - CONFIG_SYS_FPGA_FTIM1, - CONFIG_SYS_FPGA_FTIM2, - CONFIG_SYS_FPGA_FTIM3 + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 }, } }; @@ -126,8 +126,8 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor0", - CONFIG_SYS_NOR0_CSPR, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -139,8 +139,8 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor1", - CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -152,15 +152,15 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, - CONFIG_SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, { - CONFIG_SYS_FPGA_FTIM0, - CONFIG_SYS_FPGA_FTIM1, - CONFIG_SYS_FPGA_FTIM2, - CONFIG_SYS_FPGA_FTIM3 + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 }, } }; diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 232035638b3..9db3aa58605 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -12,14 +12,14 @@ u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; return in_8(p + reg); } void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; out_8(p + reg, value); } diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index a8a7263a653..741a4d64ea9 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -60,15 +60,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "cpld", - CONFIG_SYS_CPLD_CSPR, - CONFIG_SYS_CPLD_CSPR_EXT, - CONFIG_SYS_CPLD_AMASK, - CONFIG_SYS_CPLD_CSOR, + CFG_SYS_CPLD_CSPR, + CFG_SYS_CPLD_CSPR_EXT, + CFG_SYS_CPLD_AMASK, + CFG_SYS_CPLD_CSOR, { - CONFIG_SYS_CPLD_FTIM0, - CONFIG_SYS_CPLD_FTIM1, - CONFIG_SYS_CPLD_FTIM2, - CONFIG_SYS_CPLD_FTIM3 + CFG_SYS_CPLD_FTIM0, + CFG_SYS_CPLD_FTIM1, + CFG_SYS_CPLD_FTIM2, + CFG_SYS_CPLD_FTIM3 }, } }; @@ -102,15 +102,15 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "cpld", - CONFIG_SYS_CPLD_CSPR, - CONFIG_SYS_CPLD_CSPR_EXT, - CONFIG_SYS_CPLD_AMASK, - CONFIG_SYS_CPLD_CSOR, + CFG_SYS_CPLD_CSPR, + CFG_SYS_CPLD_CSPR_EXT, + CFG_SYS_CPLD_AMASK, + CFG_SYS_CPLD_CSOR, { - CONFIG_SYS_CPLD_FTIM0, - CONFIG_SYS_CPLD_FTIM1, - CONFIG_SYS_CPLD_FTIM2, - CONFIG_SYS_CPLD_FTIM3 + CFG_SYS_CPLD_FTIM0, + CFG_SYS_CPLD_FTIM1, + CFG_SYS_CPLD_FTIM2, + CFG_SYS_CPLD_FTIM3 }, } }; diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 97d71dbf2ad..3d0881643cd 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR; struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nor0", - CONFIG_SYS_NOR0_CSPR, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -55,8 +55,8 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor1", - CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -81,15 +81,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, - CONFIG_SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, { - CONFIG_SYS_FPGA_FTIM0, - CONFIG_SYS_FPGA_FTIM1, - CONFIG_SYS_FPGA_FTIM2, - CONFIG_SYS_FPGA_FTIM3 + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 }, } }; @@ -110,8 +110,8 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor0", - CONFIG_SYS_NOR0_CSPR, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -123,8 +123,8 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor1", - CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -136,15 +136,15 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, - CONFIG_SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, { - CONFIG_SYS_FPGA_FTIM0, - CONFIG_SYS_FPGA_FTIM1, - CONFIG_SYS_FPGA_FTIM2, - CONFIG_SYS_FPGA_FTIM3 + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 }, } }; diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c index 548601a5ae1..ee19d4ff8aa 100644 --- a/board/freescale/ls1046ardb/cpld.c +++ b/board/freescale/ls1046ardb/cpld.c @@ -12,14 +12,14 @@ u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; return in_8(p + reg); } void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; out_8(p + reg, value); } diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index ff3abc83022..0d3f22ce2bb 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR; struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nor0", - CONFIG_SYS_NOR0_CSPR_EARLY, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR_EARLY, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -52,13 +52,13 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { CFG_SYS_NOR_FTIM3 }, 0, - CONFIG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR, 0, }, { "nor1", - CONFIG_SYS_NOR1_CSPR_EARLY, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR1_CSPR_EARLY, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK_EARLY, CFG_SYS_NOR_CSOR, { @@ -68,7 +68,7 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { CFG_SYS_NOR_FTIM3 }, 0, - CONFIG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR, CFG_SYS_NOR_AMASK, }, { @@ -86,10 +86,10 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSOR, { SYS_FPGA_CS_FTIM0, SYS_FPGA_CS_FTIM1, @@ -121,10 +121,10 @@ struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSOR, { SYS_FPGA_CS_FTIM0, SYS_FPGA_CS_FTIM1, @@ -746,12 +746,12 @@ int set_serdes_volt(int svdd) /* Read the BRDCFG54 via CLPD */ #if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR, + ret = i2c_read(CFG_SYS_I2C_FPGA_ADDR, QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); #else struct udevice *dev; - ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev); + ret = i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev); if (!ret) ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET, (void *)&brdcfg4, 1); @@ -766,7 +766,7 @@ int set_serdes_volt(int svdd) /* Write to the BRDCFG4 */ #if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, + ret = i2c_write(CFG_SYS_I2C_FPGA_ADDR, QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); #else ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET, diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README index 971633c9c8b..a4cb1a6cac4 100644 --- a/board/freescale/ls2080aqds/README +++ b/board/freescale/ls2080aqds/README @@ -118,10 +118,10 @@ Kernel.itb 0x01000000 0x08000 Environment Variables --------------------- - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined - the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. + the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. - mcmemsize: MC DRAM block size. If this variable is not defined - the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. + the value CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) ------------------------------------------------------------------- diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 5df85722d1d..91db618227d 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -217,7 +217,7 @@ int board_init(void) #ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT #if CONFIG_IS_ENABLED(DM_I2C) - rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR); + rtc_enable_32khz_output(0, CFG_SYS_I2C_RTC_ADDR); #else rtc_enable_32khz_output(); #endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 437675517eb..cf5b1ee46e0 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -57,9 +57,9 @@ DECLARE_GLOBAL_DATA_PTR; static struct pl01x_serial_plat serial0 = { #if CONFIG_CONS_INDEX == 0 - .base = CONFIG_SYS_SERIAL0, + .base = CFG_SYS_SERIAL0, #elif CONFIG_CONS_INDEX == 1 - .base = CONFIG_SYS_SERIAL1, + .base = CFG_SYS_SERIAL1, #else #error "Unsupported console index value." #endif @@ -72,7 +72,7 @@ U_BOOT_DRVINFO(nxp_serial0) = { }; static struct pl01x_serial_plat serial1 = { - .base = CONFIG_SYS_SERIAL1, + .base = CFG_SYS_SERIAL1, .type = TYPE_PL011, }; diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c index efff0551409..d67db24d588 100644 --- a/board/freescale/m5249evb/m5249evb.c +++ b/board/freescale/m5249evb/m5249evb.c @@ -26,7 +26,7 @@ int checkboard (void) { /* * Set LED on */ - val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED; + val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_SYS_GPIO1_LED; mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ return 0; @@ -42,13 +42,13 @@ int dram_init(void) * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 */ -#ifdef CONFIG_SYS_FAST_CLK +#ifdef CFG_SYS_FAST_CLK /* * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 */ mbar_writeShort(MCFSIM_DCR, 0x8239); -#elif CONFIG_SYS_PLL_BYPASS +#elif CFG_SYS_PLL_BYPASS /* * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c index bff1ac5fb11..fbd48354160 100644 --- a/board/freescale/m5253demo/flash.c +++ b/board/freescale/m5253demo/flash.c @@ -42,7 +42,7 @@ ulong flash_init(void) ulong size = 0; ulong fbase = 0; - fbase = (ulong) CONFIG_SYS_FLASH_BASE; + fbase = (ulong) CFG_SYS_FLASH_BASE; flash_get_size((FPWV *) fbase, &flash_info[0]); flash_get_offsets((ulong) fbase, &flash_info[0]); fbase += flash_info[0].size; @@ -64,9 +64,9 @@ int flash_get_offsets(ulong base, flash_info_t * info) info->start[0] = base; info->protect[0] = 0; - for (i = 1; i < CONFIG_SYS_SST_SECT; i++) { + for (i = 1; i < CFG_SYS_SST_SECT; i++) { info->start[i] = info->start[i - 1] - + CONFIG_SYS_SST_SECTSZ; + + CFG_SYS_SST_SECTSZ; info->protect[i] = 0; } } @@ -162,8 +162,8 @@ ulong flash_get_size(FPWV * addr, flash_info_t * info) info->sector_count = 0; info->size = 0; - info->sector_count = CONFIG_SYS_SST_SECT; - info->size = CONFIG_SYS_SST_SECT * CONFIG_SYS_SST_SECTSZ; + info->sector_count = CFG_SYS_SST_SECT; + info->size = CFG_SYS_SST_SECT * CFG_SYS_SST_SECTSZ; /* reset ID mode */ *addr = (FPWV) 0x00F000F0; @@ -222,7 +222,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) start = get_timer(0); - if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) { + if ((s_last - s_first) == (CFG_SYS_SST_SECT - 1)) { if (prot == 0) { addr = (FPWV *) info->start[0]; @@ -259,7 +259,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) enable_interrupts(); return 0; - } else if (prot == CONFIG_SYS_SST_SECT) { + } else if (prot == CFG_SYS_SST_SECT) { return 1; } } @@ -282,7 +282,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) flag = disable_interrupts(); - base = (FPWV *) (CONFIG_SYS_FLASH_BASE); /* First sector */ + base = (FPWV *) (CFG_SYS_FLASH_BASE); /* First sector */ base[FLASH_CYCLE1] = 0x00AA; /* unlock */ base[FLASH_CYCLE2] = 0x0055; /* unlock */ @@ -411,7 +411,7 @@ int write_word(flash_info_t * info, FPWV * dest, u16 data) return (2); } - base = (FPWV *) (CONFIG_SYS_FLASH_BASE); + base = (FPWV *) (CFG_SYS_FLASH_BASE); /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 179a2a242a8..c1cff52fb3d 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -36,7 +36,7 @@ int dram_init(void) if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { u32 RC, temp; - RC = (CONFIG_SYS_CLK / 1000000) >> 1; + RC = (CFG_SYS_CLK / 1000000) >> 1; RC = (RC * 15) >> 4; /* Initialize DRAM Control Register: DCR */ @@ -113,7 +113,7 @@ void ide_set_reset(int idereset) mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); #define CALC_TIMING(t) (t + period - 1) / period - period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ + period = 1000000000 / (CFG_SYS_CLK / 2); /* period in ns */ /*ata->ton = CALC_TIMING (180); */ out_8(&ata->t1, CALC_TIMING(piotms[2][0])); diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README index 0de36a7f747..34f05f3fdc7 100644 --- a/board/freescale/m53017evb/README +++ b/board/freescale/m53017evb/README @@ -68,7 +68,7 @@ CONFIG_M53015 -- define for MCF53015 CPUs CONFIG_M53017EVB -- define for M53017EVB board CONFIG_MCFUART -- define to use common CF Uart driver -CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CFG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 CONFIG_BAUDRATE -- define UART baudrate CONFIG_MCFRTC -- define to use common CF RTC driver @@ -96,11 +96,11 @@ CONFIG_SYS_I2C_SLAVE -- define for I2C slave address CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset CONFIG_SYS_IMMR -- define for MBAR offset -CONFIG_SYS_MBAR -- define MBAR offset +CFG_SYS_MBAR -- define MBAR offset CONFIG_MONITOR_IS_IN_RAM -- Not support -CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM +CFG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index a10c365ec37..d921eef8b67 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -23,7 +23,7 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { struct nand_chip *this = mtd_to_nand(mtdinfo); - volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; + volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR; if (ctrl & NAND_CTRL_CHANGE) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README index bfbcd5dc81d..7240648796b 100644 --- a/board/freescale/m5373evb/README +++ b/board/freescale/m5373evb/README @@ -67,7 +67,7 @@ CONFIG_M5373 -- define for all Freescale MCF5373 CPUs CONFIG_M5373EVB -- define for M5373EVB board CONFIG_MCFUART -- define to use common CF Uart driver -CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CFG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 CONFIG_BAUDRATE -- define UART baudrate CONFIG_MCFRTC -- define to use common CF RTC driver @@ -95,11 +95,11 @@ CONFIG_SYS_I2C_SLAVE -- define for I2C slave address CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset CONFIG_SYS_IMMR -- define for MBAR offset -CONFIG_SYS_MBAR -- define MBAR offset +CFG_SYS_MBAR -- define MBAR offset CONFIG_MONITOR_IS_IN_RAM -- Not support -CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM +CFG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c index fdf3e0ac1b1..6d825a66e33 100644 --- a/board/freescale/m5373evb/nand.c +++ b/board/freescale/m5373evb/nand.c @@ -23,7 +23,7 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { struct nand_chip *this = mtd_to_nand(mtdinfo); - volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; + volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR; if (ctrl & NAND_CTRL_CHANGE) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 85d43cccd1a..4a145540265 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_SYS_DRAM_TEST) +#if defined(CFG_SYS_DRAM_TEST) int testdram(void) { @@ -103,25 +103,25 @@ int fixed_sdram(void) im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; + im->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE; udelay(50000); - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; + im->ddr.sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL; udelay(1000); - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.csbnds[0].csbnds = CFG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_SYS_DDR_CS0_CONFIG; udelay(1000); - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CFG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CFG_SYS_DDR_INTERVAL; sync(); udelay(1000); diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index d1943889915..7b6ef5b11c9 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -12,7 +12,7 @@ struct law_entry law_table[] = { /* LBC window - maps 256M */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index e4c951feb5a..73e024eaa01 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -103,11 +103,11 @@ void lbc_sdram_init(void) uint idx; volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; + uint *sdram_addr = (uint *)CFG_SYS_LBC_SDRAM_BASE; uint lsdmr_common; puts("LBC SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, + print_size(CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* @@ -115,17 +115,17 @@ void lbc_sdram_init(void) */ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; + lbc->lbcr = CFG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; + lbc->lsrt = CFG_SYS_LBC_LSRT; + lbc->mrtpr = CFG_SYS_LBC_MRTPR; asm("msync"); /* * MPC8548 uses "new" 15-16 style addressing. */ - lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; + lsdmr_common = CFG_SYS_LBC_LSDMR_COMMON; lsdmr_common |= LSDMR_BSMA1516; /* diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index 9c8e9486008..994a32dd92a 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -11,16 +11,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -29,7 +29,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 0: * FLASH(cover boot page) 16M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1), @@ -37,7 +37,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 1: * CCSRBAR 1M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), @@ -45,8 +45,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 2: * LBC SDRAM 64M Cacheable, non-guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, - CONFIG_SYS_LBC_SDRAM_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_LBC_SDRAM_BASE, + CFG_SYS_LBC_SDRAM_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 2, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 4f27d3e8ecc..d447ad840ad 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -42,7 +42,7 @@ u32 get_board_rev(void) int rev = readl(&fuse->gp[6]); - if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) + if (!i2c_probe(CFG_SYS_DIALOG_PMIC_I2C_ADDR)) rev = 0; return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; @@ -81,7 +81,7 @@ static int power_init(void) int ret; struct pmic *p; - if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { + if (!i2c_probe(CFG_SYS_DIALOG_PMIC_I2C_ADDR)) { ret = pmic_dialog_init(I2C_PMIC); if (ret) return ret; diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c index 2dcee79b3ae..13fc2fa2e38 100644 --- a/board/freescale/p1010rdb/law.c +++ b/board/freescale/p1010rdb/law.c @@ -8,8 +8,8 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), }; diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index ab3b2e3e69b..0f014823c93 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -83,7 +83,7 @@ struct cpld_data { int board_early_init_f(void) { ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; /* Clock configuration to access CPLD using IFC(GPCM) */ setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); /* @@ -97,7 +97,7 @@ int board_early_init_f(void) int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* @@ -118,12 +118,12 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_16M, 1); set_tlb(1, flashbase + 0x1000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, + CFG_SYS_FLASH_BASE_PHYS + 0x1000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel+1, BOOKE_PAGESZ_16M, 1); return 0; @@ -138,7 +138,7 @@ int config_board_mux(int ctrl_type) struct udevice *dev; int ret; #if defined(CONFIG_TARGET_P1010RDB_PA) - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR1, 1, &dev); @@ -254,7 +254,7 @@ int config_board_mux(int ctrl_type) #endif #else #if defined(CONFIG_TARGET_P1010RDB_PA) - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); switch (ctrl_type) { case MUX_TYPE_IFC: @@ -404,7 +404,7 @@ int i2c_pca9557_read(int type) int checkboard(void) { struct cpu_type *cpu; - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); u8 val; cpu = gd->arch.cpu; diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index 9bf948cb5c9..e450f626e0a 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -29,7 +29,7 @@ void board_init_f(ulong bootflag) { u32 plat_ratio; ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; console_init_f(); diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 5e1fa70bca5..265cde81a3c 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -8,19 +8,19 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CFG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CFG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CFG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -36,17 +36,17 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), #ifndef CONFIG_SPL_BUILD - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE + 0x1000000, + CFG_SYS_FLASH_BASE_PHYS + 0x1000000, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 3, BOOKE_PAGESZ_16M, 1), @@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G - Board CPLD */ - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), @@ -73,14 +73,14 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_1M, 1), #if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), #endif -#ifdef CONFIG_SYS_INIT_L2_ADDR +#ifdef CFG_SYS_INIT_L2_ADDR /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1) #endif diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index f896fd7ccce..5f16779abaa 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -201,7 +201,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, } #endif /* CONFIG_SYS_DDR_RAW_TIMING */ -#ifdef CONFIG_SYS_DDR_CS0_BNDS +#ifdef CFG_SYS_DDR_CS0_BNDS /* Fixed sdram init -- doesn't use serial presence detect. */ phys_size_t fixed_sdram(void) { @@ -209,35 +209,35 @@ phys_size_t fixed_sdram(void) char buf[32]; size_t ddr_size; fsl_ddr_cfg_regs_t ddr_cfg_regs = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[0].bnds = CFG_SYS_DDR_CS0_BNDS, + .cs[0].config = CFG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CFG_SYS_DDR_CS0_CONFIG_2, #if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, + .cs[1].bnds = CFG_SYS_DDR_CS1_BNDS, + .cs[1].config = CFG_SYS_DDR_CS1_CONFIG, + .cs[1].config_2 = CFG_SYS_DDR_CS1_CONFIG_2, #endif - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, + .timing_cfg_3 = CFG_SYS_DDR_TIMING_3, + .timing_cfg_0 = CFG_SYS_DDR_TIMING_0, + .timing_cfg_1 = CFG_SYS_DDR_TIMING_1, + .timing_cfg_2 = CFG_SYS_DDR_TIMING_2, + .ddr_sdram_cfg = CFG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CFG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CFG_SYS_DDR_MODE_1, + .ddr_sdram_mode_2 = CFG_SYS_DDR_MODE_2, + .ddr_sdram_md_cntl = CFG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CFG_SYS_DDR_INTERVAL, .ddr_data_init = 0xdeadbeef, /* Poison value */ - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 + .ddr_sdram_clk_cntl = CFG_SYS_DDR_CLK_CTRL, + .ddr_init_addr = CFG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CFG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CFG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CFG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CFG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CFG_SYS_DDR_WRLVL_CONTROL, + .ddr_sr_cntr = CFG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CFG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CFG_SYS_DDR_RCW_2 }; get_sys_info(&sysinfo); @@ -248,7 +248,7 @@ phys_size_t fixed_sdram(void) fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + if (set_ddr_laws(CFG_SYS_DDR_SDRAM_BASE, ddr_size, LAW_TRGT_IF_DDR_1) < 0) { printf("ERROR setting Local Access Windows for DDR\n"); return 0; diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 8f3f4840e60..6085984eab4 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -8,11 +8,11 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #ifdef CONFIG_VSC7385_ENET - SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), #endif diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 2999c85d0ae..ab797244297 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -90,20 +90,20 @@ void board_reset_prepare(void) * This ensures that external watchdog does not trigger * another reset or possible infinite reset loop. */ - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); in_8(&cpld_data->wd_cfg); /* Read back to sync write */ } void board_reset_last(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); out_8(&cpld_data->system_rst, 1); } void board_cpld_init(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg); out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); @@ -226,7 +226,7 @@ int board_early_init_f(void) int checkboard(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u8 in, out, invert, io_config, val; int bus_num = CONFIG_SYS_SPD_BUS_NUM; @@ -246,7 +246,7 @@ int checkboard(void) struct udevice *dev; int ret; - ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR, + ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_PCA9557_ADDR, 1, &dev); if (ret) { printf("%s: Cannot find udev for a bus %d\n", __func__, @@ -264,10 +264,10 @@ int checkboard(void) #else /* Non DM I2C support - will be removed */ i2c_set_bus_num(bus_num); - if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || - i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || - i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 || - i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) { + if (i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || + i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || + i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 || + i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) { printf("Error reading i2c boot information!\n"); return 0; /* Don't want to hang() on this error */ } @@ -319,7 +319,7 @@ int checkboard(void) int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); #ifdef CONFIG_VSC7385_ENET unsigned int vscfw_addr; @@ -344,7 +344,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */ 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 4cc5e01f578..94773969e9d 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -8,20 +8,20 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -32,14 +32,14 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), #ifndef CONFIG_SPL_BUILD /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_64M, 1), @@ -57,13 +57,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_VSC7385_ENET /* *I*G - VSC7385 Switch */ - SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_VSC7385_BASE, CFG_SYS_VSC7385_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif #endif /* not SPL */ - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), @@ -76,27 +76,27 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR) /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), #if defined(CONFIG_TARGET_P1020RDB_PD) /* **M** - 2G DDR on P1020MBG, map the second 1G */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + CFG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 9, BOOKE_PAGESZ_1G, 1), #endif #endif /* RAMBOOT/SPL */ -#ifdef CONFIG_SYS_INIT_L2_ADDR +#ifdef CFG_SYS_INIT_L2_ADDR /* ***G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1), #if CONFIG_SYS_L2_SIZE >= (256 << 10) - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR + 0x40000, + CFG_SYS_INIT_L2_ADDR_PHYS + 0x40000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 12, BOOKE_PAGESZ_256K, 1) #endif diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 23ec32b7f97..3e12c816abc 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -35,10 +35,10 @@ static u8 lane_to_slot[] = { }; static int riser_phy_addr[] = { - CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, }; /* @@ -101,12 +101,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, slot = lane_to_slot[lane]; if (slot) { sprintf(phy, "phy_sgmii_%x", - CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + (port - FM1_DTSEC1)); fdt_set_phy_handle(fdt, compat, addr, phy); } else { sprintf(phy, "phy_sgmii_%x", - CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + CFG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1)); fdt_set_phy_handle(fdt, compat, addr, phy); } @@ -158,9 +158,9 @@ int board_eth_init(struct bd_info *bis) * is RGMII, we'll also override its PHY address later. We assume that * DTSEC4 and DTSEC5 are used for RGMII. */ - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR); for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; @@ -180,8 +180,8 @@ int board_eth_init(struct bd_info *bis) case PHY_INTERFACE_MODE_RGMII_ID: /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ fm_info_set_phy_address(i, i == FM1_DTSEC5 ? - CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : - CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + CFG_SYS_FM1_DTSEC5_PHY_ADDR : + CFG_SYS_FM1_DTSEC4_PHY_ADDR); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", @@ -198,7 +198,7 @@ int board_eth_init(struct bd_info *bis) slot = lane_to_slot[lane]; if (slot) fm_info_set_phy_address(FM1_10GEC1, - CONFIG_SYS_FM1_10GEC1_PHY_ADDR); + CFG_SYS_FM1_10GEC1_PHY_ADDR); } fm_info_set_mdio(FM1_10GEC1, diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 1b1263091e5..575259b19c0 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -119,7 +119,7 @@ void board_config_lanes_mux(void) int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* @@ -140,7 +140,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c index 47c3b1627e3..17a6226cafc 100644 --- a/board/freescale/t102xrdb/cpld.c +++ b/board/freescale/t102xrdb/cpld.c @@ -14,14 +14,14 @@ u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; return in_8(p + reg); } void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; out_8(p + reg, value); } diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index 818c20cf1b5..1b417398992 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -222,7 +222,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, #if defined(CONFIG_DEEP_SLEEP) void board_mem_sleep_setup(void) { - void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; + void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE; /* does not provide HW signals for power management */ clrbits_8(cpld_base + 0x17, 0x40); diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c index 850ece0110e..d636bef325f 100644 --- a/board/freescale/t102xrdb/law.c +++ b/board/freescale/t102xrdb/law.c @@ -9,19 +9,19 @@ struct law_entry law_table[] = { #ifdef CONFIG_MTD_NOR_FLASH - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif -#ifdef CONFIG_SYS_CPLD_BASE_PHYS - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index f777f5a2fe7..baa59615b3e 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -130,8 +130,8 @@ int board_early_init_f(void) int board_early_init_r(void) { -#ifdef CONFIG_SYS_FLASH_BASE - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; +#ifdef CFG_SYS_FLASH_BASE + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited @@ -150,7 +150,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c index 74744c8ab0a..2519a9e4dbe 100644 --- a/board/freescale/t102xrdb/tlb.c +++ b/board/freescale/t102xrdb/tlb.c @@ -8,31 +8,31 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the * SRAM is at 0xfffc0000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), #else @@ -42,13 +42,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -64,27 +64,27 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 4, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), #endif #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_4M, 1), #endif @@ -93,18 +93,18 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), #endif -#ifdef CONFIG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1), #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 12, BOOKE_PAGESZ_1G, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + CFG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 13, BOOKE_PAGESZ_1G, 1) #endif diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c index ac34095f3b6..9ac57bbd830 100644 --- a/board/freescale/t104xrdb/cpld.c +++ b/board/freescale/t104xrdb/cpld.c @@ -7,7 +7,7 @@ * * The following macros need to be defined: * - * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map + * CFG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map */ #include @@ -18,14 +18,14 @@ u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; return in_8(p + reg); } void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; out_8(p + reg, value); } diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index 539a36d2a9b..02ddb661415 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -115,7 +115,7 @@ found: #if defined(CONFIG_DEEP_SLEEP) void board_mem_sleep_setup(void) { - void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; + void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE; /* does not provide HW signals for power management */ clrbits_8(cpld_base + 0x17, 0x40); diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 5ce24b40964..fe51d68c7bb 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -49,7 +49,7 @@ int board_eth_init(struct bd_info *bis) * DTSEC3 */ fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_SGMII1_PHY_ADDR); + CFG_SYS_SGMII1_PHY_ADDR); break; #endif #ifdef CONFIG_TARGET_T1042RDB @@ -59,7 +59,7 @@ int board_eth_init(struct bd_info *bis) fm_info_set_phy_address(i, 0); /* T1042RDB only supports SGMII on DTSEC3 */ fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_SGMII1_PHY_ADDR); + CFG_SYS_SGMII1_PHY_ADDR); break; #endif #ifdef CONFIG_TARGET_T1042D4RDB @@ -68,11 +68,11 @@ int board_eth_init(struct bd_info *bis) * & DTSEC3 */ if (FM1_DTSEC1 == i) - phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR; + phy_addr = CFG_SYS_SGMII1_PHY_ADDR; if (FM1_DTSEC2 == i) - phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR; + phy_addr = CFG_SYS_SGMII2_PHY_ADDR; if (FM1_DTSEC3 == i) - phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR; + phy_addr = CFG_SYS_SGMII3_PHY_ADDR; fm_info_set_phy_address(i, phy_addr); break; #endif @@ -81,9 +81,9 @@ int board_eth_init(struct bd_info *bis) case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_ID: if (FM1_DTSEC4 == i) - phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; + phy_addr = CFG_SYS_RGMII1_PHY_ADDR; if (FM1_DTSEC5 == i) - phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; + phy_addr = CFG_SYS_RGMII2_PHY_ADDR; fm_info_set_phy_address(i, phy_addr); break; case PHY_INTERFACE_MODE_QSGMII: @@ -112,7 +112,7 @@ int board_eth_init(struct bd_info *bis) if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) { for (i = 0; i < 4; i++) { bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i; + phy_addr = CFG_SYS_FM1_QSGMII11_PHY_ADDR + i; phy_int = PHY_INTERFACE_MODE_QSGMII; vsc9953_port_info_set_mdio(i, bus); @@ -124,7 +124,7 @@ int board_eth_init(struct bd_info *bis) if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) { for (i = 4; i < 8; i++) { bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4; + phy_addr = CFG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4; phy_int = PHY_INTERFACE_MODE_QSGMII; vsc9953_port_info_set_mdio(i, bus); diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c index 2f00d801069..a0d6eb5b270 100644 --- a/board/freescale/t104xrdb/law.c +++ b/board/freescale/t104xrdb/law.c @@ -9,19 +9,19 @@ struct law_entry law_table[] = { #ifdef CONFIG_MTD_NOR_FLASH - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif -#ifdef CONFIG_SYS_CPLD_BASE_PHYS - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index 66a142b3ad0..dd8283f3c60 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -46,7 +46,7 @@ void board_init_f(ulong bootflag) porsr1 = in_be32(&gur->porsr1); pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); - out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), + out_be32((unsigned int *)(CFG_SYS_DCSRBAR + 0x20000), pinctl); } #endif diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 7d3fd291a01..45ebdd30004 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -62,8 +62,8 @@ int board_early_init_f(void) int board_early_init_r(void) { -#ifdef CONFIG_SYS_FLASH_BASE - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; +#ifdef CFG_SYS_FLASH_BASE + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* @@ -84,7 +84,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 905e4771c91..10be580b813 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -8,32 +8,32 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) && \ !defined(CONFIG_NXP_ESBC) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the * SRAM is at 0xfffc0000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), @@ -44,8 +44,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * and virtual address is 0xfffc0000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR, - CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_VADDR, + CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), #else @@ -55,13 +55,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -77,27 +77,27 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 4, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), #endif #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_4M, 1), #endif @@ -111,18 +111,18 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), #endif -#ifdef CONFIG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1), #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 12, BOOKE_PAGESZ_1G, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + CFG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 13, BOOKE_PAGESZ_1G, 1) #endif diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c index f97467e8445..3cdd4937684 100644 --- a/board/freescale/t208xqds/law.c +++ b/board/freescale/t208xqds/law.c @@ -11,19 +11,19 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif #ifdef QIXIS_BASE_PHYS SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 82710cf897b..8be55e52e5f 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -282,7 +282,7 @@ static void esdhc_adapter_card_ident(void) int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* @@ -303,7 +303,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index f2448e86c0d..3d220afc16e 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -11,31 +11,31 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) @@ -54,13 +54,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -92,27 +92,27 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif @@ -143,7 +143,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 19, BOOKE_PAGESZ_2G, 1) #endif diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c index b9ba62adffc..933fa0decc3 100644 --- a/board/freescale/t208xrdb/cpld.c +++ b/board/freescale/t208xrdb/cpld.c @@ -11,14 +11,14 @@ u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; return in_8(p + reg); } void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; out_8(p + reg, value); } diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c index 3ff4c773d59..53a13694506 100644 --- a/board/freescale/t208xrdb/law.c +++ b/board/freescale/t208xrdb/law.c @@ -11,19 +11,19 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif -#ifdef CONFIG_SYS_CPLD_BASE_PHYS - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 1c8017b593a..04cb313e8c4 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -77,7 +77,7 @@ int checkboard(void) int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -96,7 +96,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index 45c27c08120..688a208c621 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -11,31 +11,31 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) @@ -54,13 +54,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -92,27 +92,27 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif @@ -126,8 +126,8 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif -#ifdef CONFIG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 17, BOOKE_PAGESZ_4K, 1), #endif @@ -142,7 +142,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 19, BOOKE_PAGESZ_2G, 1) #endif diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c index d484509bc20..8b1012086ec 100644 --- a/board/freescale/t4rdb/cpld.c +++ b/board/freescale/t4rdb/cpld.c @@ -9,7 +9,7 @@ * * The following macros need to be defined: * - * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the + * CFG_SYS_CPLD_BASE - The virtual address of the base of the * CPLD register map * */ @@ -22,14 +22,14 @@ u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; return in_8(p + reg); } void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; out_8(p + reg, value); } diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c index 438589604f1..43eeb884e2f 100644 --- a/board/freescale/t4rdb/law.c +++ b/board/freescale/t4rdb/law.c @@ -8,19 +8,19 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif -#ifdef CONFIG_SYS_CPLD_BASE_PHYS - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index 20ce7523e57..0bd0ba93962 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -54,7 +54,7 @@ int checkboard(void) int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* @@ -75,7 +75,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index c57af3046f9..f5af893c2d9 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -8,29 +8,29 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) /* * *I*G - L3SRAM. When L3 is used as 512K SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_512K, 1), #else @@ -40,13 +40,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -73,28 +73,28 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 6, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif @@ -108,13 +108,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif -#ifdef CONFIG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 17, BOOKE_PAGESZ_4K, 1), #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 18, BOOKE_PAGESZ_2G, 1) #endif diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 4889a6a4f3b..4fac146353d 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -40,26 +40,26 @@ static long fixed_sdram(void) out_be32(&im->sysconf.ddrlaw[0].bar, CFG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); - out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); + out_be32(&im->sysconf.ddrcdr, CFG_SYS_DDRCDR_VALUE); out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); - out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); + out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG); /* Currently we use only one CS, so disable the other bank. */ out_be32(&im->ddr.cs_config[1], 0); - out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); - out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_SDRAM_CLK_CNTL); + out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); - out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); - out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); - out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); - out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); + out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); - out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL); sync(); /* enable DDR controller */ diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 6c5e6fbbcb0..f1599306e61 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -82,7 +82,7 @@ int onenand_board_init(struct mtd_info *mtd) { if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) { struct onenand_chip *this = mtd->priv; - this->base = (void *)CONFIG_SYS_ONENAND_BASE; + this->base = (void *)CFG_SYS_ONENAND_BASE; return 0; } return 1; diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c index 5401bddf06a..b433f69675a 100644 --- a/board/keymile/common/qrio.c +++ b/board/keymile/common/qrio.c @@ -20,7 +20,7 @@ void show_qrio(void) { - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; u16 id_rev = in_be16(qrio_base + ID_REV_OFF); printf("QRIO: id = %u, revision = %u\n", @@ -33,7 +33,7 @@ bool qrio_get_selftest_pin(void) { u8 slftest; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; slftest = in_8(qrio_base + SLFTEST_OFF); @@ -46,7 +46,7 @@ bool qrio_get_pgy_pres_pin(void) { u8 pgy_pres; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; pgy_pres = in_8(qrio_base + BPRTH_OFF); @@ -57,7 +57,7 @@ int qrio_get_gpio(u8 port_off, u8 gpio_nr) { u32 gprt; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; gprt = in_be32(qrio_base + port_off + GPRT_OFF); @@ -68,7 +68,7 @@ void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value) { u32 gprt, mask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; mask = 1U << gpio_nr; @@ -85,7 +85,7 @@ void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value) { u32 direct, mask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; mask = 1U << gpio_nr; @@ -100,7 +100,7 @@ void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr) { u32 direct, mask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; mask = 1U << gpio_nr; @@ -113,7 +113,7 @@ void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val) { u32 direct, mask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; mask = 1U << gpio_nr; @@ -133,7 +133,7 @@ void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val) void qrio_wdmask(u8 bit, bool wden) { u16 wdmask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; wdmask = in_be16(qrio_base + WDMASK_OFF); @@ -150,7 +150,7 @@ void qrio_wdmask(u8 bit, bool wden) void qrio_prst(u8 bit, bool en, bool wden) { u16 prst; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; qrio_wdmask(bit, wden); @@ -170,7 +170,7 @@ void qrio_prstcfg(u8 bit, u8 mode) { unsigned long prstcfg; u8 i; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; prstcfg = in_be32(qrio_base + PRSTCFG_OFF); @@ -191,7 +191,7 @@ void qrio_prstcfg(u8 bit, u8 mode) void qrio_set_leds(void) { u8 ctrlh; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; /* set UNIT LED to RED and BOOT LED to ON */ ctrlh = in_8(qrio_base + CTRLH_OFF); @@ -205,7 +205,7 @@ void qrio_set_leds(void) void qrio_enable_app_buffer(void) { u8 ctrll; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; /* enable application buffer */ ctrll = in_8(qrio_base + CTRLL_OFF); @@ -219,7 +219,7 @@ void qrio_enable_app_buffer(void) void qrio_cpuwd_flag(bool flag) { u8 reason1; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; reason1 = in_8(qrio_base + REASON1_OFF); if (flag) @@ -246,7 +246,7 @@ void qrio_cpuwd_flag(bool flag) bool qrio_reason_unitrst(void) { u16 reason; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; reason = in_be16(qrio_base + REASON1_OFF); @@ -258,7 +258,7 @@ bool qrio_reason_unitrst(void) void qrio_uprstreq(u8 mode) { u32 rstcfg; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; rstcfg = in_8(qrio_base + RSTCFG_OFF); @@ -277,7 +277,7 @@ void qrio_uprstreq(u8 mode) ulong early_bootcount_load(void) { - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; u16 id_rev = in_be16(qrio_base + ID_REV_OFF); u8 id = (id_rev >> 8) & 0xff; u8 rev = id_rev & 0xff; @@ -295,7 +295,7 @@ ulong early_bootcount_load(void) void early_bootcount_store(ulong ebootcount) { - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; u16 id_rev = in_be16(qrio_base + ID_REV_OFF); u8 id = (id_rev >> 8) & 0xff; u8 rev = id_rev & 0xff; diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index ddd8f7a13e1..88afc76bbbf 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -40,7 +40,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; static int piggy_present(void) { struct km_bec_fpga __iomem *base = - (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE; + (struct km_bec_fpga __iomem *)CFG_SYS_KMBEC_FPGA_BASE; return in_8(&base->bprth) & PIGGY_PRESENT; } @@ -53,7 +53,7 @@ int ethernet_present(void) int board_early_init_r(void) { struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; + (struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE; #if defined(CONFIG_ARCH_MPC8360) unsigned short svid; @@ -126,18 +126,18 @@ static int fixed_sdram(void) u32 ddr_size_log2; out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); - out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f); - out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); - out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); - out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); - out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); - out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); - out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); + out_be32(&im->ddr.csbnds[0].csbnds, (CFG_SYS_DDR_CS0_BNDS) | 0x7f); + out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG); + out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); + out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); + out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL); + out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL); udelay(200); setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); @@ -215,7 +215,7 @@ int post_hotkeys_pressed(void) { int testpin = 0; struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; + (struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE; int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG); testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0; debug("post_hotkeys_pressed: %d\n", !testpin); diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c index 6a1711092b6..9f68c215f38 100644 --- a/board/keymile/kmcent2/kmcent2.c +++ b/board/keymile/kmcent2/kmcent2.c @@ -44,7 +44,7 @@ int checkboard(void) int board_early_init_f(void) { - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); bool cpuwd_flag = false; @@ -141,7 +141,7 @@ int board_early_init_r(void) { int ret = 0; - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* @@ -162,7 +162,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); diff --git a/board/keymile/kmcent2/law.c b/board/keymile/kmcent2/law.c index b04a8e20dce..ec3bb8fe806 100644 --- a/board/keymile/kmcent2/law.c +++ b/board/keymile/kmcent2/law.c @@ -10,12 +10,12 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC), /* other application LAW are not used in u-boot */ }; diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c index 0f6dc6063ab..41b24e39433 100644 --- a/board/keymile/kmcent2/tlb.c +++ b/board/keymile/kmcent2/tlb.c @@ -11,20 +11,20 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -35,13 +35,13 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX | MAS3_SR, MAS2_W | MAS2_G, 0, 2, BOOKE_PAGESZ_128M, 1), @@ -56,22 +56,22 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 4, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 9, BOOKE_PAGESZ_4M, 1), @@ -80,11 +80,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), /* QRIO */ - SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_QRIO_BASE, CFG_SYS_QRIO_BASE_PHYS, MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 11, BOOKE_PAGESZ_64K, 1), /* MRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS, MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 12, BOOKE_PAGESZ_128M, 1), /* BFTIC */ @@ -96,7 +96,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * in cpu_init_f, so do not use them here!!. */ /* PAXE */ - SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS, MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 16, BOOKE_PAGESZ_128M, 1) }; diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 1a7fa3fc1e4..e005ece469b 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -52,7 +52,7 @@ int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; /* Disable unused MCK1 */ setbits_be32(&gur->ddrclkdr, 2); diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index fa95886fa3b..238b9637bad 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -232,7 +232,7 @@ int board_init(void) gpmc_init(); #if defined(CONFIG_CMD_ONENAND) enable_gpmc_cs_config(gpmc_regs_onenandrx51, &gpmc_cfg->cs[0], - CONFIG_SYS_ONENAND_BASE, GPMC_SIZE_256M); + CFG_SYS_ONENAND_BASE, GPMC_SIZE_256M); #endif /* Enable the clks & power */ per_clocks_enable(); diff --git a/board/samsung/goni/onenand.c b/board/samsung/goni/onenand.c index 9f21795437a..c67c107b16c 100644 --- a/board/samsung/goni/onenand.c +++ b/board/samsung/goni/onenand.c @@ -14,7 +14,7 @@ int onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; - this->base = (void *)CONFIG_SYS_ONENAND_BASE; + this->base = (void *)CFG_SYS_ONENAND_BASE; this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; this->chip_probe = s5pc110_chip_probe; diff --git a/board/samsung/universal_c210/onenand.c b/board/samsung/universal_c210/onenand.c index 37e911c430a..265a2cde4b4 100644 --- a/board/samsung/universal_c210/onenand.c +++ b/board/samsung/universal_c210/onenand.c @@ -13,7 +13,7 @@ int onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; - this->base = (void *)CONFIG_SYS_ONENAND_BASE; + this->base = (void *)CFG_SYS_ONENAND_BASE; this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; this->chip_probe = s5pc210_chip_probe; diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index 3d0f7341a37..15044c7d0ed 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -246,7 +246,7 @@ void mem_init(void) setting.cr = SDRAM_BASE_CONF; setting.mdr = AT91_SDRAMC_MD_SDRAM; - setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; + setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000; /* * I write here directly in this register, because this diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 1eee972d49e..ad44a7c0d28 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -168,7 +168,7 @@ void sdramc_configure(unsigned int mask) at91_sdram_hw_init(); setting.cr = SDRAM_BASE_CONF | mask; setting.mdr = AT91_SDRAMC_MD_SDRAM; - setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; + setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000; writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC | AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL, diff --git a/board/socrates/law.c b/board/socrates/law.c index 840941b63e5..e4427ecff1b 100644 --- a/board/socrates/law.c +++ b/board/socrates/law.c @@ -30,12 +30,12 @@ */ struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), -#if defined(CONFIG_SYS_FPGA_BASE) - SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#if defined(CFG_SYS_FPGA_BASE) + SET_LAW(CFG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif - SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index ad49999dc28..61402a554b7 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -34,20 +34,20 @@ phys_size_t fixed_sdram(void) ddr->cs0_config = 0; ddr->sdram_cfg = 0; - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2; - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL; + ddr->cs0_bnds = CFG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CFG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_0 = CFG_SYS_DDR_TIMING_0; + ddr->timing_cfg_1 = CFG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CFG_SYS_DDR_MODE; + ddr->sdram_interval = CFG_SYS_DDR_INTERVAL; + ddr->sdram_cfg_2 = CFG_SYS_DDR_CONFIG_2; + ddr->sdram_clk_cntl = CFG_SYS_DDR_CLK_CONTROL; asm ("sync;isync;msync"); udelay(1000); - ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG; + ddr->sdram_cfg = CFG_SYS_DDR_CONFIG; asm ("sync; isync; msync"); udelay(1000); @@ -62,7 +62,7 @@ phys_size_t fixed_sdram(void) } #endif -#if defined(CONFIG_SYS_DRAM_TEST) +#if defined(CFG_SYS_DRAM_TEST) int testdram(void) { uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index eaba87542e7..9c4dd186fca 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -83,7 +83,7 @@ int misc_init_r (void) /* * Check if boot FLASH isn't max size */ - if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { + if (gd->bd->bi_flashsize < (0 - CFG_SYS_FLASH0)) { set_lbc_or(0, gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); set_lbc_br(0, gd->bd->bi_flashstart | @@ -98,7 +98,7 @@ int misc_init_r (void) /* * Check if only one FLASH bank is available */ - if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { + if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CFG_SYS_FLASH0)) { set_lbc_or(1, 0); set_lbc_br(1, 0); @@ -143,7 +143,7 @@ void local_bus_init (void) sys_info_t sysinfo; uint clkdiv; uint lbc_mhz; - uint lcrr = CONFIG_SYS_LBC_LCRR; + uint lcrr = CFG_SYS_LBC_LCRR; get_sys_info (&sysinfo); clkdiv = lbc->lcrr & LCRR_CLKDIV; @@ -204,8 +204,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* Fixup FPGA mapping */ val[i++] = 3; /* chip select number */ val[i++] = 0; /* always 0 */ - val[i++] = CONFIG_SYS_FPGA_BASE; - val[i++] = CONFIG_SYS_FPGA_SIZE; + val[i++] = CFG_SYS_FPGA_BASE; + val[i++] = CFG_SYS_FPGA_SIZE; rc = fdt_find_and_setprop(blob, "/localbus", "ranges", val, i * sizeof(u32), 1); diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index 1ab403d145e..631f6c34075 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -14,16 +14,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -33,7 +33,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xfc000000 64M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_64M, 1), @@ -53,12 +53,12 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), -#if defined(CONFIG_SYS_FPGA_BASE) +#if defined(CFG_SYS_FPGA_BASE) /* * TLB 4: 1M Non-cacheable, guarded * 0xc0000000 1M FPGA and NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE, + SET_TLB_ENTRY(1, CFG_SYS_FPGA_BASE, CFG_SYS_FPGA_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_1M, 1), #endif @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * (0xcbfc0000 256K LIME GDC MMIO) * MMIO is relocatable and could be at 0xcbfc0000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE, + SET_TLB_ENTRY(1, CFG_SYS_LIME_BASE, CFG_SYS_LIME_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), @@ -79,7 +79,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), @@ -91,11 +91,11 @@ struct fsl_e_tlb_entry tlb_table[] = { * Make sure the TLB count at the top of this table is correct. * Likely it needs to be increased by two for these entries. */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x10000000, CFG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), #endif diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c index 5426fc4ffd8..429f886771b 100644 --- a/board/sysam/amcore/amcore.c +++ b/board/sysam/amcore/amcore.c @@ -77,7 +77,7 @@ int dram_init(void) * DCR * set proper RC as per specification */ - RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1; + RC = (CFG_SYS_CPU_CLK / 1000000) >> 1; RC = (RC * 15) >> 4; /* 0x8000 is the faster option */ diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 34818736a4f..1683f780a33 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -121,7 +121,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* adjust memory start address for LPAE */ if (lpae) { start[0] -= CFG_SYS_SDRAM_BASE; - start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; + start[0] += CFG_SYS_LPAE_SDRAM_BASE; } if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { @@ -175,11 +175,11 @@ void ft_board_setup_ex(void *blob, struct bd_info *bd) if (prop1 && prop2) { initrd_start = __be64_to_cpu(*prop1); initrd_start -= CFG_SYS_SDRAM_BASE; - initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_start += CFG_SYS_LPAE_SDRAM_BASE; initrd_start = __cpu_to_be64(initrd_start); initrd_end = __be64_to_cpu(*prop2); initrd_end -= CFG_SYS_SDRAM_BASE; - initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_end += CFG_SYS_LPAE_SDRAM_BASE; initrd_end = __cpu_to_be64(initrd_end); err = fdt_delprop(blob, nodeoffset, @@ -223,7 +223,7 @@ void ft_board_setup_ex(void *blob, struct bd_info *bd) if (size) { *reserve_start -= CFG_SYS_SDRAM_BASE; *reserve_start += - CONFIG_SYS_LPAE_SDRAM_BASE; + CFG_SYS_LPAE_SDRAM_BASE; *reserve_start = __cpu_to_be64(*reserve_start); } else { diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index 929668ebaa8..09cbd6bf719 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -146,7 +146,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM; gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ - tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init); + tca642x_set_inital_state(CFG_SYS_I2C_TCA642X_ADDR, tca642x_init); return 0; } diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c index 9d921032eaf..bc7e5c5764f 100644 --- a/board/xes/common/fsl_8xxx_misc.c +++ b/board/xes/common/fsl_8xxx_misc.c @@ -13,7 +13,7 @@ */ int board_flash_wp_on(void) { - if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + if (pca953x_get_val(CFG_SYS_I2C_PCA953X_ADDR0) & CONFIG_SYS_PCA953X_NVM_WP) return 1; @@ -30,7 +30,7 @@ uint get_board_derivative(void) #if defined(CONFIG_MPC85xx) volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; #elif defined(CONFIG_MPC86xx) - volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR; + volatile immap_t *immap = (immap_t *)CFG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; #endif diff --git a/boot/Kconfig b/boot/Kconfig index 4a001bcee85..668270cc660 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -654,7 +654,7 @@ config SYS_MONITOR_BASE default TEXT_BASE help The physical start address of boot monitor code (which is the same as - CONFIG_TEXT_BASE when linking) and the same as CONFIG_SYS_FLASH_BASE + CONFIG_TEXT_BASE when linking) and the same as CFG_SYS_FLASH_BASE when booting from flash. config SPL_SYS_MONITOR_BASE diff --git a/boot/image-board.c b/boot/image-board.c index 8813be544be..0fd63291d3f 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -161,8 +161,8 @@ phys_size_t env_get_bootm_mapsize(void) return tmp; } -#if defined(CONFIG_SYS_BOOTMAPSZ) - return CONFIG_SYS_BOOTMAPSZ; +#if defined(CFG_SYS_BOOTMAPSZ) + return CFG_SYS_BOOTMAPSZ; #else return env_get_bootm_size(); #endif diff --git a/cmd/date.c b/cmd/date.c index 0e2dfbc4fc2..58505e6e1d3 100644 --- a/cmd/date.c +++ b/cmd/date.c @@ -51,10 +51,10 @@ static int do_date(struct cmd_tbl *cmdtp, int flag, int argc, } #elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY) old_bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM); + i2c_set_bus_num(CFG_SYS_RTC_BUS_NUM); #else old_bus = I2C_GET_BUS(); - I2C_SET_BUS(CONFIG_SYS_RTC_BUS_NUM); + I2C_SET_BUS(CFG_SYS_RTC_BUS_NUM); #endif switch (argc) { diff --git a/cmd/i2c.c b/cmd/i2c.c index 7b84378f7cd..da8b4c25555 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -97,19 +97,19 @@ static uint i2c_mm_last_alen; * When multiple buses are present, the list is an array of bus-address * pairs. The following macros take care of this */ -#if defined(CONFIG_SYS_I2C_NOPROBES) +#if defined(CFG_SYS_I2C_NOPROBES) #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) static struct { uchar bus; uchar addr; -} i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; +} i2c_no_probes[] = CFG_SYS_I2C_NOPROBES; #define GET_BUS_NUM i2c_get_bus_num() #define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b)) #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a)) #define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr #else /* single bus */ -static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; +static uchar i2c_no_probes[] = CFG_SYS_I2C_NOPROBES; #define GET_BUS_NUM 0 #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */ #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a)) @@ -912,7 +912,7 @@ static int do_i2c_probe(struct cmd_tbl *cmdtp, int flag, int argc, int j; int addr = -1; int found = 0; -#if defined(CONFIG_SYS_I2C_NOPROBES) +#if defined(CFG_SYS_I2C_NOPROBES) int k, skip; unsigned int bus = GET_BUS_NUM; #endif /* NOPROBES */ @@ -932,7 +932,7 @@ static int do_i2c_probe(struct cmd_tbl *cmdtp, int flag, int argc, if ((0 <= addr) && (j != addr)) continue; -#if defined(CONFIG_SYS_I2C_NOPROBES) +#if defined(CFG_SYS_I2C_NOPROBES) skip = 0; for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) { if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) { @@ -955,7 +955,7 @@ static int do_i2c_probe(struct cmd_tbl *cmdtp, int flag, int argc, } putc ('\n'); -#if defined(CONFIG_SYS_I2C_NOPROBES) +#if defined(CFG_SYS_I2C_NOPROBES) puts ("Excluded chip addresses:"); for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) { if (COMPARE_BUS(bus,k)) @@ -1702,7 +1702,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, #ifndef CONFIG_SYS_I2C_DIRECT_BUS int j; - for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) { + for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) { if (i2c_bus[i].next_hop[j].chip == 0) break; printf("->%s@0x%2x:%d", @@ -1737,7 +1737,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name); #ifndef CONFIG_SYS_I2C_DIRECT_BUS int j; - for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) { + for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) { if (i2c_bus[i].next_hop[j].chip == 0) break; printf("->%s@0x%2x:%d", diff --git a/common/board_f.c b/common/board_f.c index aab1130763e..e027248db56 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -900,9 +900,9 @@ static const init_fnc_t init_sequence_f[] = { post_init_f, #endif INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_SYS_DRAM_TEST) +#if defined(CFG_SYS_DRAM_TEST) testdram, -#endif /* CONFIG_SYS_DRAM_TEST */ +#endif /* CFG_SYS_DRAM_TEST */ INIT_FUNC_WATCHDOG_RESET #ifdef CONFIG_POST diff --git a/common/board_r.c b/common/board_r.c index f7fb7df54a0..347bb7f7c02 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -346,7 +346,7 @@ static int initr_flash(void) * NOTE: Maybe we should add some schedule()? XXX */ if (env_get_yesno("flashchecksum") == 1) { - const uchar *flash_base = (const uchar *)CONFIG_SYS_FLASH_BASE; + const uchar *flash_base = (const uchar *)CFG_SYS_FLASH_BASE; printf(" CRC: %08X", crc32(0, flash_base, @@ -356,8 +356,8 @@ static int initr_flash(void) putc('\n'); /* update start of FLASH memory */ -#ifdef CONFIG_SYS_FLASH_BASE - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; +#ifdef CFG_SYS_FLASH_BASE + bd->bi_flashstart = CFG_SYS_FLASH_BASE; #endif /* size of FLASH memory (final value) */ bd->bi_flashsize = flash_size; @@ -370,7 +370,7 @@ static int initr_flash(void) #if defined(CONFIG_OXC) || defined(CONFIG_RMU) /* flash mapped at end of memory map */ bd->bi_flashoffset = CONFIG_TEXT_BASE + flash_size; -#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE +#elif CONFIG_SYS_MONITOR_BASE == CFG_SYS_FLASH_BASE bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */ #endif return 0; diff --git a/common/spl/Kconfig.nxp b/common/spl/Kconfig.nxp index 8da85539afd..fc696cf0cee 100644 --- a/common/spl/Kconfig.nxp +++ b/common/spl/Kconfig.nxp @@ -26,7 +26,7 @@ config SPL_SYS_CCSR_DO_NOT_RELOCATE bool "Ensures that CCSR is not relocated" depends on PPC help - If this is defined, then CONFIG_SYS_CCSRBAR_PHYS will be forced to a + If this is defined, then CFG_SYS_CCSRBAR_PHYS will be forced to a value that ensures that CCSR is not relocated. config TPL_SYS_CCSR_DO_NOT_RELOCATE @@ -59,7 +59,7 @@ config SPL_RELOC_TEXT_BASE config SPL_RELOC_STACK hex "Address of the start of the stack SPL will use after relocation." help - If unspecified, this is equal to CONFIG_SYS_SPL_MALLOC_START. Starting + If unspecified, this is equal to CFG_SYS_SPL_MALLOC_START. Starting address of the malloc pool used in SPL. When this option is set the full malloc is used in SPL and it is set up by spl_init() and before that, the simple malloc() can be used if CONFIG_SYS_MALLOC_F is defined. diff --git a/common/spl/spl.c b/common/spl/spl.c index 22d2a0621e1..1d2e8fda728 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -43,8 +43,8 @@ DECLARE_GLOBAL_DATA_PTR; DECLARE_BINMAN_MAGIC_SYM; -#ifndef CONFIG_SYS_UBOOT_START -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#ifndef CFG_SYS_UBOOT_START +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE #endif u32 *boot_params_ptr = NULL; @@ -250,7 +250,7 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image) spl_image->entry_point = u_boot_pos; spl_image->load_addr = u_boot_pos; } else { - spl_image->entry_point = CONFIG_SYS_UBOOT_START; + spl_image->entry_point = CFG_SYS_UBOOT_START; spl_image->load_addr = CONFIG_TEXT_BASE; } spl_image->os = IH_OS_U_BOOT; diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index c1ed31e367c..08da7fed88e 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -828,7 +828,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, } /* - * If a platform does not provide CONFIG_SYS_UBOOT_START, U-Boot's + * If a platform does not provide CFG_SYS_UBOOT_START, U-Boot's * Makefile will set it to 0 and it will end up as the entry point * here. What it actually means is: use the load address. */ diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index eaa95fb9b59..1ef5e412624 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -20,7 +20,7 @@ static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector, unsigned long __weak spl_nor_get_uboot_base(void) { - return CONFIG_SYS_UBOOT_BASE; + return CFG_SYS_UBOOT_BASE; } static int spl_nor_load_image(struct spl_image_info *spl_image, diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index da6742416ed..2aff025f76e 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -31,7 +31,7 @@ static int spi_load_image_os(struct spl_image_info *spl_image, int err; /* Read for a header, parse or error out. */ - spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, sizeof(*header), + spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS, sizeof(*header), (void *)header); if (image_get_magic(header) != IH_MAGIC) @@ -41,12 +41,12 @@ static int spi_load_image_os(struct spl_image_info *spl_image, if (err) return err; - spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, + spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS, spl_image->size, (void *)spl_image->load_addr); /* Read device tree. */ - spi_flash_read(flash, CONFIG_SYS_SPI_ARGS_OFFS, - CONFIG_SYS_SPI_ARGS_SIZE, + spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS, + CFG_SYS_SPI_ARGS_SIZE, (void *)CONFIG_SYS_SPL_ARGS_ADDR); return 0; diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c index fb804f02089..bcac25cd021 100644 --- a/common/spl/spl_ubi.c +++ b/common/spl/spl_ubi.c @@ -31,7 +31,7 @@ int spl_ubi_load_image(struct spl_image_info *spl_image, #ifdef CONFIG_SPL_ONENAND_SUPPORT case BOOT_DEVICE_ONENAND: info.read = onenand_spl_read_block; - info.peb_size = CONFIG_SYS_ONENAND_BLOCK_SIZE; + info.peb_size = CFG_SYS_ONENAND_BLOCK_SIZE; break; #endif default: diff --git a/common/spl/spl_xip.c b/common/spl/spl_xip.c index 1258d85e63d..77c23ba0597 100644 --- a/common/spl/spl_xip.c +++ b/common/spl/spl_xip.c @@ -25,6 +25,6 @@ static int spl_xip(struct spl_image_info *spl_image, } #endif return(spl_parse_image_header(spl_image, bootdev, - (const struct legacy_img_hdr *)CONFIG_SYS_UBOOT_BASE)); + (const struct legacy_img_hdr *)CFG_SYS_UBOOT_BASE)); } SPL_LOAD_IMAGE_METHOD("XIP", 0, BOOT_DEVICE_XIP, spl_xip); diff --git a/doc/README.atmel_mci b/doc/README.atmel_mci index 00e64ba0c7d..0b6d2c53db7 100644 --- a/doc/README.atmel_mci +++ b/doc/README.atmel_mci @@ -60,7 +60,7 @@ int board_mmc_init(struct bd_info *bd) /* this is a weak define that we are overriding */ int board_mmc_getcd(struct mmc *mmc) { - return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN); + return !at91_get_gpio_value(CFG_SYS_MMC_CD_PIN); } #endif @@ -70,5 +70,5 @@ and the board definition files needs: /* SD/MMC card */ #define CONFIG_GENERIC_ATMEL_MCI 1 #define CONFIG_ATMEL_MCI_PORTB 1 /* Atmel XE-EK uses port B */ -#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC9 +#define CFG_SYS_MMC_CD_PIN AT91_PIN_PC9 #define CONFIG_CMD_MMC 1 diff --git a/doc/README.cfi b/doc/README.cfi index ad52850818f..38185747028 100644 --- a/doc/README.cfi +++ b/doc/README.cfi @@ -35,12 +35,12 @@ In addition, the t3corp board defines the routine thusly: void flash_cmd_reset(flash_info_t *info) { /* - * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and + * FLASH at address CFG_SYS_FLASH_BASE is a Spansion chip and * needs the Spansion type reset commands. The other flash chip * is located behind a FPGA (Xilinx DS617) and needs the Intel type * reset command. */ - if (info->start[0] == CONFIG_SYS_FLASH_BASE) + if (info->start[0] == CFG_SYS_FLASH_BASE) flash_write_cmd(info, 0, 0, AMD_CMD_RESET); else flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); diff --git a/doc/README.davinci b/doc/README.davinci index 607531af2a8..326efa0a2d6 100644 --- a/doc/README.davinci +++ b/doc/README.davinci @@ -75,7 +75,7 @@ http://www.ti.com/tool/TMDXLCDK138 Davinci special defines ======================= -CONFIG_SYS_DV_NOR_BOOT_CFG: AM18xx based boards, booting in NOR Boot mode +CFG_SYS_DV_NOR_BOOT_CFG: AM18xx based boards, booting in NOR Boot mode need a "NOR Boot Configuration Word" stored in the NOR Flash. This define adds this. More Info about this, see: diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci index 82fea6201d6..767614cbc6d 100644 --- a/doc/README.generic_usb_ohci +++ b/doc/README.generic_usb_ohci @@ -11,7 +11,7 @@ Configuration options CONFIG_USB_OHCI_NEW: enable the new OHCI driver - CONFIG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI + CFG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI registers CONFIG_SYS_USB_OHCI_SLOT_NAME: slot name diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx index 3c6ebbdb0e6..bafffe6dc51 100644 --- a/doc/README.mpc85xx +++ b/doc/README.mpc85xx @@ -59,13 +59,13 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 3) TLB entry for the stack during AS1 Location : Lable "create_init_ram_area" TLB Entry : 14 - EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR Properties : 16K, AS1, IPROT 4) TLB entry for CCSRBAR during AS1 execution Location : cpu_init_early_f TLB Entry : 13 - EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR Properties : 1M, AS1, I, G 5) Invalidate unproctected TLB Entries @@ -84,7 +84,7 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 8) Update Flash's TLB entry Location : Board_init_r TLB entry : Search from TLB entries - EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS Properties : Board specific size, AS0, I, G, IPROT @@ -94,7 +94,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot Location : Label "_start" TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB #if defined(CONFIG_NXP_ESBC) - EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW Properties : 1M, AS1, I, G, IPROT #else EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 @@ -105,7 +105,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot Location : Label "create_init_ram_area" TLB Entry : 15 #if defined(CONFIG_NXP_ESBC) - EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW Properties : 1M, AS1, I, G, IPROT #else EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 @@ -115,13 +115,13 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 3) TLB entry for the stack during AS1 Location : Lable "create_init_ram_area" TLB Entry : 14 - EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR Properties : 16K, AS1, IPROT 4) TLB entry for CCSRBAR during AS1 execution Location : cpu_init_early_f TLB Entry : 13 - EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR Properties : 1M, AS1, I, G 5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399 @@ -162,5 +162,5 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 12) Update Flash's TLB entry Location : Board_init_r TLB entry : Search from TLB entries - EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS Properties : Board specific size, AS0, I, G, IPROT diff --git a/doc/README.nand b/doc/README.nand index a3c3ab4b950..37657512533 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -134,7 +134,7 @@ Configuration Options: chip.IO_ADDR_R = ...; chip.IO_ADDR_W = ...; - if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL)) + if (nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL)) error out /* diff --git a/doc/README.serial_multi b/doc/README.serial_multi index c9049fd01d6..0446fe95937 100644 --- a/doc/README.serial_multi +++ b/doc/README.serial_multi @@ -35,7 +35,7 @@ just after switching the console: setenv sout serial_scc; setenv baudrate 38400 After that press 'enter' at the SCC console. Note that baudrates <38400 -are not allowed on LWMON with watchdog enabled (see CONFIG_SYS_BAUDRATE_TABLE in +are not allowed on LWMON with watchdog enabled (see CFG_SYS_BAUDRATE_TABLE in include/configs/lwmon.h). diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst index 584503eb12e..770327fea21 100644 --- a/doc/arch/m68k.rst +++ b/doc/arch/m68k.rst @@ -112,16 +112,16 @@ CONFIG_M5272: Other options, generally set inside include/configs/.h, they may apply to one or more cpu for the ColdFire family: -CONFIG_SYS_MBAR: +CFG_SYS_MBAR: defines the base address of the MCF5272 configuration registers -CONFIG_SYS_SCR: +CFG_SYS_SCR: defines the contents of the System Configuration Register -CONFIG_SYS_SPR: +CFG_SYS_SPR: defines the contents of the System Protection Register -CONFIG_SYS_MFD: +CFG_SYS_MFD: defines the PLL Multiplication Factor Divider (see table 9-4 of MCF user manual) -CONFIG_SYS_RFD: +CFG_SYS_RFD: defines the PLL Reduce Frequency Devider (see table 9-4 of MCF user manual) CONFIG_SYS_CSx_BASE: @@ -136,9 +136,9 @@ CONFIG_SYS_CSx_RO: if set to 0 chip select x is read/write else chip select is read only CONFIG_SYS_CSx_WS: defines the number of wait states of chip select x -CONFIG_SYS_CACHE_ICACR: +CFG_SYS_CACHE_ICACR: cache-related registers config -CONFIG_SYS_CACHE_DCACR: +CFG_SYS_CACHE_DCACR: cache-related registers config CONFIG_SYS_CACHE_ACRX: cache-related registers config @@ -162,7 +162,7 @@ CFG_SYS_SDRAM_EMOD: these options are used. CONFIG_MCFUART: defines enabling of ColdFire UART driver -CONFIG_SYS_UART_PORT: +CFG_SYS_UART_PORT: defines the UART port to be used (only a single UART can be actually enabled) -CONFIG_SYS_SBFHDR_SIZE: +CFG_SYS_SBFHDR_SIZE: size of the prepended SBF header, if any diff --git a/doc/develop/driver-model/migration.rst b/doc/develop/driver-model/migration.rst index 43665de64f5..fe1ae210def 100644 --- a/doc/develop/driver-model/migration.rst +++ b/doc/develop/driver-model/migration.rst @@ -99,7 +99,7 @@ The I2C subsystem has supported the driver model since early 2015. Maintainers should submit patches switching over to using CONFIG_DM_I2C and other base driver model options in time for inclusion in the 2021.10 release. -CONFIG_SYS_TIMER_RATE and CONFIG_SYS_TIMER_COUNTER +CFG_SYS_TIMER_RATE and CFG_SYS_TIMER_COUNTER -------------------------------------------------- Deadline: 2023.01 diff --git a/doc/device-tree-bindings/video/exynos-dp.txt b/doc/device-tree-bindings/video/exynos-dp.txt index 464a85302ec..273d8fc7968 100644 --- a/doc/device-tree-bindings/video/exynos-dp.txt +++ b/doc/device-tree-bindings/video/exynos-dp.txt @@ -30,9 +30,9 @@ Optional properties: 8(WHITE_GRAY_BALCKBAR_64),9(MOBILE_WHITEBAR_32), 10(MOBILE_WHITEBAR_64) samsung,h-sync-polarity: Horizontal Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,v-sync-polarity: Vertical Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,interlaced: Progressive if 0, else Interlaced samsung,color-space: input video data format COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2 diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt index b022f6163f1..bff0cecfcfb 100644 --- a/doc/device-tree-bindings/video/exynos-fb.txt +++ b/doc/device-tree-bindings/video/exynos-fb.txt @@ -23,15 +23,15 @@ Board(panel specific): samsung,vl-height: Height of display area in mm samsung,vl-clkp: Clock polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-oep: Output Enable polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-hsp: Horizontal Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-vsp: Vertical Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-dp: Data polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-cmd-allow-len: Wait end of frame samsung,winid: Window number on which data is to be displayed diff --git a/doc/imx/common/imx5.txt b/doc/imx/common/imx5.txt index ea0e144cedc..6c8c2e594fb 100644 --- a/doc/imx/common/imx5.txt +++ b/doc/imx/common/imx5.txt @@ -16,7 +16,7 @@ i.MX5x SoCs. of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. -1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. +1.2 CFG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. This option should be enabled for boards having a SYS_ON_OFF_CTL signal connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the reference designs. diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index 15897f63dd9..83f210d2d05 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -162,7 +162,7 @@ bootm_low for use by the bootm command. See also "bootm_size" environment variable. Address defined by "bootm_low" is also the base of the initial memory mapping for the Linux - kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and + kernel -- see the description of CFG_SYS_BOOTMAPSZ and bootm_mapsize. bootm_mapsize @@ -170,7 +170,7 @@ bootm_mapsize This variable is given as a hexadecimal number and it defines the size of the memory region starting at base address bootm_low that is accessible by the Linux kernel - during early boot. If unset, CONFIG_SYS_BOOTMAPSZ is used + during early boot. If unset, CFG_SYS_BOOTMAPSZ is used as the default value if it is defined, and bootm_size is used otherwise. @@ -228,7 +228,7 @@ initrd_high is usually what you want since it allows for maximum initrd size. If for some reason you want to make sure that the initrd image is loaded below the - CONFIG_SYS_BOOTMAPSZ limit, you can set this environment + CFG_SYS_BOOTMAPSZ limit, you can set this environment variable to a value of "no" or "off" or "0". Alternatively, you can set it to a maximum upper address to use (U-Boot will still check that it diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 8d6424c9da1..570252d186a 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -83,7 +83,7 @@ config BOOTCOUNT_I2C bool "Boot counter on I2C device" help Enable support for the bootcounter on an i2c (like RTC) device. - CONFIG_SYS_I2C_RTC_ADDR = i2c chip address + CFG_SYS_I2C_RTC_ADDR = i2c chip address CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for the bootcounter. diff --git a/drivers/bootcount/bootcount_i2c.c b/drivers/bootcount/bootcount_i2c.c index 496741d63f7..b3ac67ea35d 100644 --- a/drivers/bootcount/bootcount_i2c.c +++ b/drivers/bootcount/bootcount_i2c.c @@ -17,7 +17,7 @@ void bootcount_store(ulong a) buf[0] = BC_MAGIC; buf[1] = (a & 0xff); - ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, + ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, CONFIG_BOOTCOUNT_ALEN, buf, 2); if (ret != 0) puts("Error writing bootcount\n"); @@ -28,7 +28,7 @@ ulong bootcount_load(void) unsigned char buf[3]; int ret; - ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, + ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, CONFIG_BOOTCOUNT_ALEN, buf, 2); if (ret != 0) { puts("Error loading bootcount\n"); diff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c index b2bfb529cc8..2fdc2fbd554 100644 --- a/drivers/clk/at91/compat.c +++ b/drivers/clk/at91/compat.c @@ -150,7 +150,7 @@ static int at91_slow_clk_enable(struct clk *clk) static ulong at91_slow_clk_get_rate(struct clk *clk) { - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; } static struct clk_ops at91_slow_clk_ops = { diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index b79e99b63de..8fde77c23ee 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -14,7 +14,7 @@ config SPL_DM help Enable driver model in SPL. You will need to provide a suitable malloc() implementation. If you are not using the - full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, + full malloc() enabled by CFG_SYS_SPL_MALLOC_START, consider using CONFIG_SPL_SYS_MALLOC_SIMPLE. In that case you must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size. In most cases driver model will only allocate a few uclasses @@ -27,7 +27,7 @@ config TPL_DM help Enable driver model in TPL. You will need to provide a suitable malloc() implementation. If you are not using the - full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, + full malloc() enabled by CFG_SYS_SPL_MALLOC_START, consider using CONFIG_TPL_SYS_MALLOC_SIMPLE. In that case you must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size. In most cases driver model will only allocate a few uclasses @@ -42,7 +42,7 @@ config VPL_DM help Enable driver model in VPL. You will need to provide a suitable malloc() implementation. If you are not using the - full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, + full malloc() enabled by CFG_SYS_SPL_MALLOC_START, consider using CONFIG_SPL_SYS_MALLOC_SIMPLE. config DM_WARN diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 4975dbb821e..cd332718b64 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -22,7 +22,7 @@ /* * CFG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view - * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for + * of DDR controllers. It is the same as CFG_SYS_DDR_SDRAM_BASE for * all Power SoCs. But it could be different for ARM SoCs. For example, * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of * 0x00_8000_0000 ~ 0x00_ffff_ffff @@ -32,7 +32,7 @@ #ifdef CONFIG_MPC83xx #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE #else -#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_DDR_SDRAM_BASE #endif #endif diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index a1ff47035be..ca49ee40a71 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -24,8 +24,8 @@ #define CONFIG_FPGA_DELAY() #endif -#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ #endif static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize); @@ -138,7 +138,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) ts = get_timer (0); /* get current time */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for STATUS to go high.\n"); (*fn->abort) (cookie); return FPGA_FAIL; diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index f264ff8c0ec..3eed461e1e5 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -22,8 +22,8 @@ #define CONFIG_FPGA_DELAY() #endif -#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */ #endif static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize); @@ -130,7 +130,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) ts = get_timer(0); /* get current time */ do { CONFIG_FPGA_DELAY(); - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts("** Timeout waiting for STATUS to go high.\n"); (*fn->abort) (cookie); diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index f72dfdec94e..57a4532f736 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -21,8 +21,8 @@ #define CONFIG_FPGA_DELAY() #endif -#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); @@ -149,7 +149,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) /* Now wait for INIT and BUSY to go high */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ return FPGA_FAIL; @@ -182,7 +182,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) CONFIG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for BUSY to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ return FPGA_FAIL; @@ -214,7 +214,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) CONFIG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ ret_val = FPGA_FAIL; @@ -333,7 +333,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) ts = get_timer (0); /* get current time */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to start.\n"); return FPGA_FAIL; } @@ -347,7 +347,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) /* Now wait for INIT to go high */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); return FPGA_FAIL; } @@ -404,7 +404,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) putc ('*'); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); ret_val = FPGA_FAIL; break; diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index b7a063a95fc..fdec89bb815 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -26,8 +26,8 @@ #define CONFIG_FPGA_DELAY() #endif -#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); @@ -154,7 +154,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) /* Now wait for INIT and BUSY to go high */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ return FPGA_FAIL; @@ -187,7 +187,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) CONFIG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for BUSY to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ return FPGA_FAIL; @@ -221,7 +221,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) CONFIG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ ret_val = FPGA_FAIL; @@ -340,7 +340,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) ts = get_timer (0); /* get current time */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to start.\n"); if (*fn->abort) (*fn->abort) (cookie); @@ -356,7 +356,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) /* Now wait for INIT to go high */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); if (*fn->abort) (*fn->abort) (cookie); @@ -423,7 +423,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) putc ('*'); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); ret_val = FPGA_FAIL; break; diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 0d536f0d044..8871deaea6f 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -49,8 +49,8 @@ * which yields 11.44 mS. So let's make it bigger in order to handle * an XC2V1000, if anyone can ever get ahold of one. */ -#ifndef CONFIG_SYS_FPGA_WAIT_INIT -#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */ +#ifndef CFG_SYS_FPGA_WAIT_INIT +#define CFG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */ #endif /* @@ -58,15 +58,15 @@ * This is normally not necessary since for most reasonable configuration * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary. */ -#ifndef CONFIG_SYS_FPGA_WAIT_BUSY -#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/ +#ifndef CFG_SYS_FPGA_WAIT_BUSY +#define CFG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/ #endif /* Default timeout for waiting for FPGA to enter operational mode after * configuration data has been written. */ -#ifndef CONFIG_SYS_FPGA_WAIT_CONFIG -#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */ +#ifndef CFG_SYS_FPGA_WAIT_CONFIG +#define CFG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */ #endif static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); @@ -190,9 +190,9 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) udelay(10); ts = get_timer(0); do { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) { printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n", - __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT); + __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT); (*fn->abort)(cookie); return FPGA_FAIL; } @@ -209,9 +209,9 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) ts = get_timer(0); do { CONFIG_FPGA_DELAY(); - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) { printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n", - __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT); + __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT); (*fn->abort)(cookie); return FPGA_FAIL; } @@ -260,9 +260,9 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, break; } - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_CONFIG) { printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n", - __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG); + __func__, __LINE__, CFG_SYS_FPGA_WAIT_CONFIG); (*fn->abort)(cookie); ret_val = FPGA_FAIL; break; @@ -350,10 +350,10 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) #ifdef CONFIG_SYS_FPGA_CHECK_BUSY ts = get_timer(0); while ((*fn->busy)(cookie)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_BUSY) { printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n", __func__, __LINE__, - CONFIG_SYS_FPGA_WAIT_BUSY); + CFG_SYS_FPGA_WAIT_BUSY); (*fn->abort)(cookie); return FPGA_FAIL; } diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 0c83df46da4..53dd780a6ca 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -36,8 +36,8 @@ #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001 -#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif #ifndef CONFIG_SYS_FPGA_PROG_TIME @@ -232,7 +232,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype) /* Polling the PCAP_INIT status for Reset */ ts = get_timer(0); while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for INIT to clear\n", __func__); return FPGA_FAIL; @@ -246,7 +246,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype) ts = get_timer(0); while (!(readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for INIT to set\n", __func__); return FPGA_FAIL; @@ -400,7 +400,7 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, /* Check FPGA configuration completion */ ts = get_timer(0); while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for FPGA to config\n", __func__); return FPGA_FAIL; @@ -484,7 +484,7 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, /* Check FPGA configuration completion */ ts = get_timer(0); while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for FPGA to config\n", __func__); return FPGA_FAIL; @@ -561,7 +561,7 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, /* Check FPGA configuration completion */ ts = get_timer(0); while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for FPGA to config\n", __func__); return FPGA_FAIL; diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index 2fd2996798c..b5ed35256ee 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -14,8 +14,8 @@ #include /* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CONFIG_SYS_I2C_PCA953X_ADDR -#define CONFIG_SYS_I2C_PCA953X_ADDR (~0) +#ifndef CFG_SYS_I2C_PCA953X_ADDR +#define CFG_SYS_I2C_PCA953X_ADDR (~0) #endif enum { @@ -26,14 +26,14 @@ enum { PCA953X_CMD_INVERT, }; -#ifdef CONFIG_SYS_I2C_PCA953X_WIDTH +#ifdef CFG_SYS_I2C_PCA953X_WIDTH struct pca953x_chip_ngpio { uint8_t chip; uint8_t ngpio; }; static struct pca953x_chip_ngpio pca953x_chip_ngpios[] = - CONFIG_SYS_I2C_PCA953X_WIDTH; + CFG_SYS_I2C_PCA953X_WIDTH; /* * Determine the number of GPIO pins supported. If we don't know we assume @@ -204,7 +204,7 @@ static struct cmd_tbl cmd_pca953x[] = { static int do_pca953x(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR; + static uint8_t chip = CFG_SYS_I2C_PCA953X_ADDR; int ret = CMD_RET_USAGE, val; ulong ul_arg2 = 0; ulong ul_arg3 = 0; diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c index 7f67f96b0ec..b07496e6e49 100644 --- a/drivers/gpio/tca642x.c +++ b/drivers/gpio/tca642x.c @@ -52,7 +52,7 @@ static int tca642x_reg_write(uchar chip, uint8_t addr, int ret; org_bus_num = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM); + i2c_set_bus_num(CFG_SYS_I2C_TCA642X_BUS_NUM); if (i2c_read(chip, addr, 1, (uint8_t *)&valw, 1)) { printf("Could not read before writing\n"); @@ -76,7 +76,7 @@ static int tca642x_reg_read(uchar chip, uint8_t addr, uint8_t *data) int ret = 0; org_bus_num = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM); + i2c_set_bus_num(CFG_SYS_I2C_TCA642X_BUS_NUM); if (i2c_read(chip, addr, 1, (u8 *)&valw, 1)) { ret = -1; goto error; @@ -242,7 +242,7 @@ static struct cmd_tbl cmd_tca642x[] = { static int do_tca642x(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - static uchar chip = CONFIG_SYS_I2C_TCA642X_ADDR; + static uchar chip = CFG_SYS_I2C_TCA642X_ADDR; int ret = CMD_RET_USAGE, val; int gpio_bank = 0; uint8_t bank_shift; diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c index ae177227dea..25ef937dc0b 100644 --- a/drivers/i2c/davinci_i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -91,7 +91,7 @@ static uint _davinci_i2c_setspeed(struct i2c_regs *i2c_base, psc = 2; /* SCLL + SCLH */ - div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; + div = (CFG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */ REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */ REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll)); diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index edbcd83b646..187db92b75f 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_M68K -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR +#define CONFIG_SYS_IMMR CFG_SYS_MBAR #endif #if !CONFIG_IS_ENABLED(DM_I2C) diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index c3f6a1251f1..7f65db23205 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -35,7 +35,7 @@ struct i2c_adapter *i2c_get_adapter(int index) #if !defined(CONFIG_SYS_I2C_DIRECT_BUS) struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] = - CONFIG_SYS_I2C_BUSES; + CFG_SYS_I2C_BUSES; #endif DECLARE_GLOBAL_DATA_PTR; @@ -114,7 +114,7 @@ static int i2c_mux_set_all(void) /* Connect requested bus if behind muxes */ if (i2c_bus_tmp->next_hop[0].chip != 0) { /* Set all muxes along the path to that bus */ - for (i = 0; i < CONFIG_SYS_I2C_MAX_HOPS; i++) { + for (i = 0; i < CFG_SYS_I2C_MAX_HOPS; i++) { int ret; if (i2c_bus_tmp->next_hop[i].chip == 0) @@ -143,7 +143,7 @@ static int i2c_mux_disconnect_all(void) /* Disconnect current bus (turn off muxes if any) */ if ((i2c_bus_tmp->next_hop[0].chip != 0) && (I2C_ADAP->init_done != 0)) { - i = CONFIG_SYS_I2C_MAX_HOPS; + i = CFG_SYS_I2C_MAX_HOPS; do { uint8_t chip; int ret; diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c index 4edcba29110..b9b0ff1c39e 100644 --- a/drivers/i2c/kona_i2c.c +++ b/drivers/i2c/kona_i2c.c @@ -129,7 +129,7 @@ struct bcm_kona_i2c_dev { #define DEF_DEVICE(num) \ {(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]} -static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = { +static struct bcm_kona_i2c_dev g_i2c_devs[CFG_SYS_MAX_I2C_BUS] = { #ifdef CONFIG_SYS_I2C_BASE0 DEF_DEVICE(0), #endif diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index f48a4f25aae..a9c7d6e1bc2 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif /* CONFIG_DM_I2C */ /* - * On SUNXI, we get CONFIG_SYS_TCLK from this include, so we want to + * On SUNXI, we get CFG_SYS_TCLK from this include, so we want to * always have it. */ #if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_ARCH_SUNXI) @@ -427,9 +427,9 @@ static int twsi_stop(struct mvtwsi_registers *twsi, uint tick) static uint twsi_calc_freq(const int n, const int m) { #ifdef CONFIG_ARCH_SUNXI - return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)); + return CFG_SYS_TCLK / (10 * (m + 1) * (1 << n)); #else - return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n)); + return CFG_SYS_TCLK / (10 * (m + 1) * (2 << n)); #endif } diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index f80ff5383bc..9a1599dcd91 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -39,8 +39,8 @@ DECLARE_GLOBAL_DATA_PTR; #define VF610_I2C_REGSHIFT 0 #define I2C_EARLY_INIT_INDEX 0 -#ifdef CONFIG_SYS_I2C_IFDR_DIV -#define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV +#ifdef CFG_SYS_I2C_IFDR_DIV +#define I2C_IFDR_DIV_CONSERVATIVE CFG_SYS_I2C_IFDR_DIV #else #define I2C_IFDR_DIV_CONSERVATIVE 0x7e #endif diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c index 8fdaacd5e04..58b00587363 100644 --- a/drivers/misc/fsl_ifc.c +++ b/drivers/misc/fsl_ifc.c @@ -12,37 +12,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "cs0", -#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - CONFIG_SYS_CSPR0, -#ifdef CONFIG_SYS_CSPR0_EXT - CONFIG_SYS_CSPR0_EXT, +#if defined(CFG_SYS_CSPR0) && defined(CFG_SYS_CSOR0) + CFG_SYS_CSPR0, +#ifdef CFG_SYS_CSPR0_EXT + CFG_SYS_CSPR0_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK0 - CONFIG_SYS_AMASK0, +#ifdef CFG_SYS_AMASK0 + CFG_SYS_AMASK0, #else 0, #endif - CONFIG_SYS_CSOR0, + CFG_SYS_CSOR0, { - CONFIG_SYS_CS0_FTIM0, - CONFIG_SYS_CS0_FTIM1, - CONFIG_SYS_CS0_FTIM2, - CONFIG_SYS_CS0_FTIM3, + CFG_SYS_CS0_FTIM0, + CFG_SYS_CS0_FTIM1, + CFG_SYS_CS0_FTIM2, + CFG_SYS_CS0_FTIM3, }, -#ifdef CONFIG_SYS_CSOR0_EXT - CONFIG_SYS_CSOR0_EXT, +#ifdef CFG_SYS_CSOR0_EXT + CFG_SYS_CSOR0_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR0_FINAL - CONFIG_SYS_CSPR0_FINAL, +#ifdef CFG_SYS_CSPR0_FINAL + CFG_SYS_CSPR0_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK0_FINAL - CONFIG_SYS_AMASK0_FINAL, +#ifdef CFG_SYS_AMASK0_FINAL + CFG_SYS_AMASK0_FINAL, #else 0, #endif @@ -52,37 +52,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 2 { "cs1", -#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) - CONFIG_SYS_CSPR1, -#ifdef CONFIG_SYS_CSPR1_EXT - CONFIG_SYS_CSPR1_EXT, +#if defined(CFG_SYS_CSPR1) && defined(CFG_SYS_CSOR1) + CFG_SYS_CSPR1, +#ifdef CFG_SYS_CSPR1_EXT + CFG_SYS_CSPR1_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK1 - CONFIG_SYS_AMASK1, +#ifdef CFG_SYS_AMASK1 + CFG_SYS_AMASK1, #else 0, #endif - CONFIG_SYS_CSOR1, + CFG_SYS_CSOR1, { - CONFIG_SYS_CS1_FTIM0, - CONFIG_SYS_CS1_FTIM1, - CONFIG_SYS_CS1_FTIM2, - CONFIG_SYS_CS1_FTIM3, + CFG_SYS_CS1_FTIM0, + CFG_SYS_CS1_FTIM1, + CFG_SYS_CS1_FTIM2, + CFG_SYS_CS1_FTIM3, }, -#ifdef CONFIG_SYS_CSOR1_EXT - CONFIG_SYS_CSOR1_EXT, +#ifdef CFG_SYS_CSOR1_EXT + CFG_SYS_CSOR1_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR1_FINAL - CONFIG_SYS_CSPR1_FINAL, +#ifdef CFG_SYS_CSPR1_FINAL + CFG_SYS_CSPR1_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK1_FINAL - CONFIG_SYS_AMASK1_FINAL, +#ifdef CFG_SYS_AMASK1_FINAL + CFG_SYS_AMASK1_FINAL, #else 0, #endif @@ -93,37 +93,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 3 { "cs2", -#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) - CONFIG_SYS_CSPR2, -#ifdef CONFIG_SYS_CSPR2_EXT - CONFIG_SYS_CSPR2_EXT, +#if defined(CFG_SYS_CSPR2) && defined(CFG_SYS_CSOR2) + CFG_SYS_CSPR2, +#ifdef CFG_SYS_CSPR2_EXT + CFG_SYS_CSPR2_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK2 - CONFIG_SYS_AMASK2, +#ifdef CFG_SYS_AMASK2 + CFG_SYS_AMASK2, #else 0, #endif - CONFIG_SYS_CSOR2, + CFG_SYS_CSOR2, { - CONFIG_SYS_CS2_FTIM0, - CONFIG_SYS_CS2_FTIM1, - CONFIG_SYS_CS2_FTIM2, - CONFIG_SYS_CS2_FTIM3, + CFG_SYS_CS2_FTIM0, + CFG_SYS_CS2_FTIM1, + CFG_SYS_CS2_FTIM2, + CFG_SYS_CS2_FTIM3, }, -#ifdef CONFIG_SYS_CSOR2_EXT - CONFIG_SYS_CSOR2_EXT, +#ifdef CFG_SYS_CSOR2_EXT + CFG_SYS_CSOR2_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR2_FINAL - CONFIG_SYS_CSPR2_FINAL, +#ifdef CFG_SYS_CSPR2_FINAL + CFG_SYS_CSPR2_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK2_FINAL - CONFIG_SYS_AMASK2_FINAL, +#ifdef CFG_SYS_AMASK2_FINAL + CFG_SYS_AMASK2_FINAL, #else 0, #endif @@ -134,37 +134,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 4 { "cs3", -#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) - CONFIG_SYS_CSPR3, -#ifdef CONFIG_SYS_CSPR3_EXT - CONFIG_SYS_CSPR3_EXT, +#if defined(CFG_SYS_CSPR3) && defined(CFG_SYS_CSOR3) + CFG_SYS_CSPR3, +#ifdef CFG_SYS_CSPR3_EXT + CFG_SYS_CSPR3_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK3 - CONFIG_SYS_AMASK3, +#ifdef CFG_SYS_AMASK3 + CFG_SYS_AMASK3, #else 0, #endif - CONFIG_SYS_CSOR3, + CFG_SYS_CSOR3, { - CONFIG_SYS_CS3_FTIM0, - CONFIG_SYS_CS3_FTIM1, - CONFIG_SYS_CS3_FTIM2, - CONFIG_SYS_CS3_FTIM3, + CFG_SYS_CS3_FTIM0, + CFG_SYS_CS3_FTIM1, + CFG_SYS_CS3_FTIM2, + CFG_SYS_CS3_FTIM3, }, -#ifdef CONFIG_SYS_CSOR3_EXT - CONFIG_SYS_CSOR3_EXT, +#ifdef CFG_SYS_CSOR3_EXT + CFG_SYS_CSOR3_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR3_FINAL - CONFIG_SYS_CSPR3_FINAL, +#ifdef CFG_SYS_CSPR3_FINAL + CFG_SYS_CSPR3_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK3_FINAL - CONFIG_SYS_AMASK3_FINAL, +#ifdef CFG_SYS_AMASK3_FINAL + CFG_SYS_AMASK3_FINAL, #else 0, #endif @@ -175,37 +175,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 5 { "cs4", -#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) - CONFIG_SYS_CSPR4, -#ifdef CONFIG_SYS_CSPR4_EXT - CONFIG_SYS_CSPR4_EXT, +#if defined(CFG_SYS_CSPR4) && defined(CFG_SYS_CSOR4) + CFG_SYS_CSPR4, +#ifdef CFG_SYS_CSPR4_EXT + CFG_SYS_CSPR4_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK4 - CONFIG_SYS_AMASK4, +#ifdef CFG_SYS_AMASK4 + CFG_SYS_AMASK4, #else 0, #endif - CONFIG_SYS_CSOR4, + CFG_SYS_CSOR4, { - CONFIG_SYS_CS4_FTIM0, - CONFIG_SYS_CS4_FTIM1, - CONFIG_SYS_CS4_FTIM2, - CONFIG_SYS_CS4_FTIM3, + CFG_SYS_CS4_FTIM0, + CFG_SYS_CS4_FTIM1, + CFG_SYS_CS4_FTIM2, + CFG_SYS_CS4_FTIM3, }, -#ifdef CONFIG_SYS_CSOR4_EXT - CONFIG_SYS_CSOR4_EXT, +#ifdef CFG_SYS_CSOR4_EXT + CFG_SYS_CSOR4_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR4_FINAL - CONFIG_SYS_CSPR4_FINAL, +#ifdef CFG_SYS_CSPR4_FINAL + CFG_SYS_CSPR4_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK4_FINAL - CONFIG_SYS_AMASK4_FINAL, +#ifdef CFG_SYS_AMASK4_FINAL + CFG_SYS_AMASK4_FINAL, #else 0, #endif @@ -257,37 +257,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 7 { "cs6", -#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) - CONFIG_SYS_CSPR6, -#ifdef CONFIG_SYS_CSPR6_EXT - CONFIG_SYS_CSPR6_EXT, +#if defined(CFG_SYS_CSPR6) && defined(CFG_SYS_CSOR6) + CFG_SYS_CSPR6, +#ifdef CFG_SYS_CSPR6_EXT + CFG_SYS_CSPR6_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK6 - CONFIG_SYS_AMASK6, +#ifdef CFG_SYS_AMASK6 + CFG_SYS_AMASK6, #else 0, #endif - CONFIG_SYS_CSOR6, + CFG_SYS_CSOR6, { - CONFIG_SYS_CS6_FTIM0, - CONFIG_SYS_CS6_FTIM1, - CONFIG_SYS_CS6_FTIM2, - CONFIG_SYS_CS6_FTIM3, + CFG_SYS_CS6_FTIM0, + CFG_SYS_CS6_FTIM1, + CFG_SYS_CS6_FTIM2, + CFG_SYS_CS6_FTIM3, }, -#ifdef CONFIG_SYS_CSOR6_EXT - CONFIG_SYS_CSOR6_EXT, +#ifdef CFG_SYS_CSOR6_EXT + CFG_SYS_CSOR6_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR6_FINAL - CONFIG_SYS_CSPR6_FINAL, +#ifdef CFG_SYS_CSPR6_FINAL + CFG_SYS_CSPR6_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK6_FINAL - CONFIG_SYS_AMASK6_FINAL, +#ifdef CFG_SYS_AMASK6_FINAL + CFG_SYS_AMASK6_FINAL, #else 0, #endif @@ -298,37 +298,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 8 { "cs7", -#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) - CONFIG_SYS_CSPR7, -#ifdef CONFIG_SYS_CSPR7_EXT - CONFIG_SYS_CSPR7_EXT, +#if defined(CFG_SYS_CSPR7) && defined(CFG_SYS_CSOR7) + CFG_SYS_CSPR7, +#ifdef CFG_SYS_CSPR7_EXT + CFG_SYS_CSPR7_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK7 - CONFIG_SYS_AMASK7, +#ifdef CFG_SYS_AMASK7 + CFG_SYS_AMASK7, #else 0, #endif - CONFIG_SYS_CSOR7, -#ifdef CONFIG_SYS_CSOR7_EXT - CONFIG_SYS_CSOR7_EXT, + CFG_SYS_CSOR7, +#ifdef CFG_SYS_CSOR7_EXT + CFG_SYS_CSOR7_EXT, #else 0, #endif { - CONFIG_SYS_CS7_FTIM0, - CONFIG_SYS_CS7_FTIM1, - CONFIG_SYS_CS7_FTIM2, - CONFIG_SYS_CS7_FTIM3, + CFG_SYS_CS7_FTIM0, + CFG_SYS_CS7_FTIM1, + CFG_SYS_CS7_FTIM2, + CFG_SYS_CS7_FTIM3, }, -#ifdef CONFIG_SYS_CSPR7_FINAL - CONFIG_SYS_CSPR7_FINAL, +#ifdef CFG_SYS_CSPR7_FINAL + CFG_SYS_CSPR7_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK7_FINAL - CONFIG_SYS_AMASK7_FINAL, +#ifdef CFG_SYS_AMASK7_FINAL + CFG_SYS_AMASK7_FINAL, #else 0, #endif @@ -412,91 +412,91 @@ void init_final_memctl_regs(void) #else void init_early_memctl_regs(void) { -#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); - set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); - set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); - set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); +#if defined(CFG_SYS_CSPR0) && defined(CFG_SYS_CSOR0) + set_ifc_ftim(IFC_CS0, IFC_FTIM0, CFG_SYS_CS0_FTIM0); + set_ifc_ftim(IFC_CS0, IFC_FTIM1, CFG_SYS_CS0_FTIM1); + set_ifc_ftim(IFC_CS0, IFC_FTIM2, CFG_SYS_CS0_FTIM2); + set_ifc_ftim(IFC_CS0, IFC_FTIM3, CFG_SYS_CS0_FTIM3); #ifndef CONFIG_A003399_NOR_WORKAROUND -#ifdef CONFIG_SYS_CSPR0_EXT - set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); +#ifdef CFG_SYS_CSPR0_EXT + set_ifc_cspr_ext(IFC_CS0, CFG_SYS_CSPR0_EXT); #endif -#ifdef CONFIG_SYS_CSOR0_EXT - set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT); +#ifdef CFG_SYS_CSOR0_EXT + set_ifc_csor_ext(IFC_CS0, CFG_SYS_CSOR0_EXT); #endif - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); - set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); + set_ifc_cspr(IFC_CS0, CFG_SYS_CSPR0); + set_ifc_amask(IFC_CS0, CFG_SYS_AMASK0); + set_ifc_csor(IFC_CS0, CFG_SYS_CSOR0); #endif #endif -#ifdef CONFIG_SYS_CSPR1_EXT - set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); +#ifdef CFG_SYS_CSPR1_EXT + set_ifc_cspr_ext(IFC_CS1, CFG_SYS_CSPR1_EXT); #endif -#ifdef CONFIG_SYS_CSOR1_EXT - set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT); +#ifdef CFG_SYS_CSOR1_EXT + set_ifc_csor_ext(IFC_CS1, CFG_SYS_CSOR1_EXT); #endif -#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) - set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); - set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); - set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); - set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); +#if defined(CFG_SYS_CSPR1) && defined(CFG_SYS_CSOR1) + set_ifc_ftim(IFC_CS1, IFC_FTIM0, CFG_SYS_CS1_FTIM0); + set_ifc_ftim(IFC_CS1, IFC_FTIM1, CFG_SYS_CS1_FTIM1); + set_ifc_ftim(IFC_CS1, IFC_FTIM2, CFG_SYS_CS1_FTIM2); + set_ifc_ftim(IFC_CS1, IFC_FTIM3, CFG_SYS_CS1_FTIM3); - set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); + set_ifc_csor(IFC_CS1, CFG_SYS_CSOR1); + set_ifc_amask(IFC_CS1, CFG_SYS_AMASK1); + set_ifc_cspr(IFC_CS1, CFG_SYS_CSPR1); #endif -#ifdef CONFIG_SYS_CSPR2_EXT - set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); +#ifdef CFG_SYS_CSPR2_EXT + set_ifc_cspr_ext(IFC_CS2, CFG_SYS_CSPR2_EXT); #endif -#ifdef CONFIG_SYS_CSOR2_EXT - set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT); +#ifdef CFG_SYS_CSOR2_EXT + set_ifc_csor_ext(IFC_CS2, CFG_SYS_CSOR2_EXT); #endif -#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) - set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); - set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); - set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); - set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); +#if defined(CFG_SYS_CSPR2) && defined(CFG_SYS_CSOR2) + set_ifc_ftim(IFC_CS2, IFC_FTIM0, CFG_SYS_CS2_FTIM0); + set_ifc_ftim(IFC_CS2, IFC_FTIM1, CFG_SYS_CS2_FTIM1); + set_ifc_ftim(IFC_CS2, IFC_FTIM2, CFG_SYS_CS2_FTIM2); + set_ifc_ftim(IFC_CS2, IFC_FTIM3, CFG_SYS_CS2_FTIM3); - set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); + set_ifc_csor(IFC_CS2, CFG_SYS_CSOR2); + set_ifc_amask(IFC_CS2, CFG_SYS_AMASK2); + set_ifc_cspr(IFC_CS2, CFG_SYS_CSPR2); #endif -#ifdef CONFIG_SYS_CSPR3_EXT - set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); +#ifdef CFG_SYS_CSPR3_EXT + set_ifc_cspr_ext(IFC_CS3, CFG_SYS_CSPR3_EXT); #endif -#ifdef CONFIG_SYS_CSOR3_EXT - set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT); +#ifdef CFG_SYS_CSOR3_EXT + set_ifc_csor_ext(IFC_CS3, CFG_SYS_CSOR3_EXT); #endif -#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) - set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); - set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); - set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); - set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); +#if defined(CFG_SYS_CSPR3) && defined(CFG_SYS_CSOR3) + set_ifc_ftim(IFC_CS3, IFC_FTIM0, CFG_SYS_CS3_FTIM0); + set_ifc_ftim(IFC_CS3, IFC_FTIM1, CFG_SYS_CS3_FTIM1); + set_ifc_ftim(IFC_CS3, IFC_FTIM2, CFG_SYS_CS3_FTIM2); + set_ifc_ftim(IFC_CS3, IFC_FTIM3, CFG_SYS_CS3_FTIM3); - set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); - set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); + set_ifc_cspr(IFC_CS3, CFG_SYS_CSPR3); + set_ifc_amask(IFC_CS3, CFG_SYS_AMASK3); + set_ifc_csor(IFC_CS3, CFG_SYS_CSOR3); #endif -#ifdef CONFIG_SYS_CSPR4_EXT - set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); +#ifdef CFG_SYS_CSPR4_EXT + set_ifc_cspr_ext(IFC_CS4, CFG_SYS_CSPR4_EXT); #endif -#ifdef CONFIG_SYS_CSOR4_EXT - set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT); +#ifdef CFG_SYS_CSOR4_EXT + set_ifc_csor_ext(IFC_CS4, CFG_SYS_CSOR4_EXT); #endif -#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) - set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); - set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); - set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2); - set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3); +#if defined(CFG_SYS_CSPR4) && defined(CFG_SYS_CSOR4) + set_ifc_ftim(IFC_CS4, IFC_FTIM0, CFG_SYS_CS4_FTIM0); + set_ifc_ftim(IFC_CS4, IFC_FTIM1, CFG_SYS_CS4_FTIM1); + set_ifc_ftim(IFC_CS4, IFC_FTIM2, CFG_SYS_CS4_FTIM2); + set_ifc_ftim(IFC_CS4, IFC_FTIM3, CFG_SYS_CS4_FTIM3); - set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4); - set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4); - set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4); + set_ifc_cspr(IFC_CS4, CFG_SYS_CSPR4); + set_ifc_amask(IFC_CS4, CFG_SYS_AMASK4); + set_ifc_csor(IFC_CS4, CFG_SYS_CSOR4); #endif #ifdef CONFIG_SYS_CSPR5_EXT @@ -516,66 +516,66 @@ void init_early_memctl_regs(void) set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5); #endif -#ifdef CONFIG_SYS_CSPR6_EXT - set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); +#ifdef CFG_SYS_CSPR6_EXT + set_ifc_cspr_ext(IFC_CS6, CFG_SYS_CSPR6_EXT); #endif -#ifdef CONFIG_SYS_CSOR6_EXT - set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT); +#ifdef CFG_SYS_CSOR6_EXT + set_ifc_csor_ext(IFC_CS6, CFG_SYS_CSOR6_EXT); #endif -#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) - set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); - set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); - set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2); - set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3); +#if defined(CFG_SYS_CSPR6) && defined(CFG_SYS_CSOR6) + set_ifc_ftim(IFC_CS6, IFC_FTIM0, CFG_SYS_CS6_FTIM0); + set_ifc_ftim(IFC_CS6, IFC_FTIM1, CFG_SYS_CS6_FTIM1); + set_ifc_ftim(IFC_CS6, IFC_FTIM2, CFG_SYS_CS6_FTIM2); + set_ifc_ftim(IFC_CS6, IFC_FTIM3, CFG_SYS_CS6_FTIM3); - set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6); - set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6); - set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6); + set_ifc_cspr(IFC_CS6, CFG_SYS_CSPR6); + set_ifc_amask(IFC_CS6, CFG_SYS_AMASK6); + set_ifc_csor(IFC_CS6, CFG_SYS_CSOR6); #endif -#ifdef CONFIG_SYS_CSPR7_EXT - set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); +#ifdef CFG_SYS_CSPR7_EXT + set_ifc_cspr_ext(IFC_CS7, CFG_SYS_CSPR7_EXT); #endif -#ifdef CONFIG_SYS_CSOR7_EXT - set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT); +#ifdef CFG_SYS_CSOR7_EXT + set_ifc_csor_ext(IFC_CS7, CFG_SYS_CSOR7_EXT); #endif -#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) - set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); - set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); - set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2); - set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3); +#if defined(CFG_SYS_CSPR7) && defined(CFG_SYS_CSOR7) + set_ifc_ftim(IFC_CS7, IFC_FTIM0, CFG_SYS_CS7_FTIM0); + set_ifc_ftim(IFC_CS7, IFC_FTIM1, CFG_SYS_CS7_FTIM1); + set_ifc_ftim(IFC_CS7, IFC_FTIM2, CFG_SYS_CS7_FTIM2); + set_ifc_ftim(IFC_CS7, IFC_FTIM3, CFG_SYS_CS7_FTIM3); - set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7); - set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7); - set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7); + set_ifc_cspr(IFC_CS7, CFG_SYS_CSPR7); + set_ifc_amask(IFC_CS7, CFG_SYS_AMASK7); + set_ifc_csor(IFC_CS7, CFG_SYS_CSOR7); #endif } void init_final_memctl_regs(void) { -#ifdef CONFIG_SYS_CSPR0_FINAL - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL); +#ifdef CFG_SYS_CSPR0_FINAL + set_ifc_cspr(IFC_CS0, CFG_SYS_CSPR0_FINAL); #endif -#ifdef CONFIG_SYS_AMASK0_FINAL - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); +#ifdef CFG_SYS_AMASK0_FINAL + set_ifc_amask(IFC_CS0, CFG_SYS_AMASK0); #endif -#ifdef CONFIG_SYS_CSPR1_FINAL - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL); +#ifdef CFG_SYS_CSPR1_FINAL + set_ifc_cspr(IFC_CS1, CFG_SYS_CSPR1_FINAL); #endif -#ifdef CONFIG_SYS_AMASK1_FINAL - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL); +#ifdef CFG_SYS_AMASK1_FINAL + set_ifc_amask(IFC_CS1, CFG_SYS_AMASK1_FINAL); #endif -#ifdef CONFIG_SYS_CSPR2_FINAL - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL); +#ifdef CFG_SYS_CSPR2_FINAL + set_ifc_cspr(IFC_CS2, CFG_SYS_CSPR2_FINAL); #endif -#ifdef CONFIG_SYS_AMASK2_FINAL - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); +#ifdef CFG_SYS_AMASK2_FINAL + set_ifc_amask(IFC_CS2, CFG_SYS_AMASK2); #endif -#ifdef CONFIG_SYS_CSPR3_FINAL - set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL); +#ifdef CFG_SYS_CSPR3_FINAL + set_ifc_cspr(IFC_CS3, CFG_SYS_CSPR3_FINAL); #endif -#ifdef CONFIG_SYS_AMASK3_FINAL - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); +#ifdef CFG_SYS_AMASK3_FINAL + set_ifc_amask(IFC_CS3, CFG_SYS_AMASK3); #endif } #endif diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c index 9c4b4d7e46d..6b831281e96 100644 --- a/drivers/misc/fsl_portals.c +++ b/drivers/misc/fsl_portals.c @@ -20,25 +20,25 @@ #endif #include -#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE) -#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE) +#define MAX_BPORTALS (CFG_SYS_BMAN_CINH_SIZE / CFG_SYS_BMAN_SP_CINH_SIZE) +#define MAX_QPORTALS (CFG_SYS_QMAN_CINH_SIZE / CFG_SYS_QMAN_SP_CINH_SIZE) void setup_qbman_portals(void) { - void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE + - CONFIG_SYS_BMAN_SWP_ISDR_REG; - void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE + - CONFIG_SYS_QMAN_SWP_ISDR_REG; + void __iomem *bpaddr = (void *)CFG_SYS_BMAN_CINH_BASE + + CFG_SYS_BMAN_SWP_ISDR_REG; + void __iomem *qpaddr = (void *)CFG_SYS_QMAN_CINH_BASE + + CFG_SYS_QMAN_SWP_ISDR_REG; struct ccsr_qman *qman = (void *)CFG_SYS_FSL_QMAN_ADDR; /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ #ifdef CONFIG_PHYS_64BIT - out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); + out_be32(&qman->qcsp_bare, (u32)(CFG_SYS_QMAN_MEM_PHYS >> 32)); #endif - out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); + out_be32(&qman->qcsp_bar, (u32)CFG_SYS_QMAN_MEM_PHYS); #ifdef CONFIG_FSL_CORENET int i; - for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { + for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) { u8 sdest = qp_info[i].sdest; u16 fliodn = qp_info[i].fliodn; u16 dliodn = qp_info[i].dliodn; @@ -53,7 +53,7 @@ void setup_qbman_portals(void) #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) int i; - for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { + for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) { u8 sdest = qp_info[i].sdest; u16 ficid = qp_info[i].ficid; u16 dicid = qp_info[i].dicid; @@ -68,10 +68,10 @@ void setup_qbman_portals(void) #endif /* Change default state of BMan ISDR portals to all 1s */ - inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS, - CONFIG_SYS_BMAN_SP_CINH_SIZE); - inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS, - CONFIG_SYS_QMAN_SP_CINH_SIZE); + inhibit_portals(bpaddr, CFG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS, + CFG_SYS_BMAN_SP_CINH_SIZE); + inhibit_portals(qpaddr, CFG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS, + CFG_SYS_QMAN_SP_CINH_SIZE); } void inhibit_portals(void __iomem *addr, int max_portals, diff --git a/drivers/misc/fsl_sec_mon.c b/drivers/misc/fsl_sec_mon.c index 321bd27fd32..3597ee22242 100644 --- a/drivers/misc/fsl_sec_mon.c +++ b/drivers/misc/fsl_sec_mon.c @@ -10,7 +10,7 @@ static u32 get_sec_mon_state(void) { struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); + (CFG_SYS_SEC_MON_ADDR); return sec_mon_in32(&sec_mon_regs->hp_stat) & HPSR_SSM_ST_MASK; } @@ -19,7 +19,7 @@ static int set_sec_mon_state_non_sec(void) u32 sts; int timeout = 10; struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); + (CFG_SYS_SEC_MON_ADDR); sts = get_sec_mon_state(); @@ -120,7 +120,7 @@ static int set_sec_mon_state_soft_fail(void) u32 sts; int timeout = 10; struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); + (CFG_SYS_SEC_MON_ADDR); printf("SEC_MON state transitioning to Soft Fail.\n"); sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV); diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index aa00d7e2014..6d7c0cff22a 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -9,7 +9,7 @@ #include #include -#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS +#ifndef CFG_SYS_MMC_U_BOOT_OFFS extern uchar mmc_u_boot_offs[]; #endif @@ -97,7 +97,7 @@ void __noreturn mmc_boot(void) } #ifdef CONFIG_FSL_CORENET - offset = CONFIG_SYS_MMC_U_BOOT_OFFS; + offset = CFG_SYS_MMC_U_BOOT_OFFS; #else sector = 0; again: @@ -153,16 +153,16 @@ again: val = *(tmp_buf + blk_off + ESDHC_BOOT_IMAGE_ADDR + i); offset = (offset << 8) + val; } -#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS +#ifndef CFG_SYS_MMC_U_BOOT_OFFS offset += (ulong)&mmc_u_boot_offs - CONFIG_SPL_TEXT_BASE; #else - offset += CONFIG_SYS_MMC_U_BOOT_OFFS; + offset += CFG_SYS_MMC_U_BOOT_OFFS; #endif #endif /* * Load U-Boot image from mmc into RAM */ - code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; + code_len = CFG_SYS_MMC_U_BOOT_SIZE; blk_start = offset / mmc->read_bl_len; blk_off = offset % mmc->read_bl_len; blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len + 1; @@ -176,7 +176,7 @@ again: blk_start++; } err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, - (uchar *)CONFIG_SYS_MMC_U_BOOT_DST + + (uchar *)CFG_SYS_MMC_U_BOOT_DST + (blk_off ? (mmc->read_bl_len - blk_off) : 0)); if (err != blk_cnt) { puts("spl: mmc read failed!!\n"); @@ -189,18 +189,18 @@ again: * after SDHC DMA transfer. */ if (blk_off) - memcpy((uchar *)CONFIG_SYS_MMC_U_BOOT_DST, + memcpy((uchar *)CFG_SYS_MMC_U_BOOT_DST, tmp_buf + blk_off, mmc->read_bl_len - blk_off); /* * Clean d-cache and invalidate i-cache, to * make sure that no stale data is executed. */ - flush_cache(CONFIG_SYS_MMC_U_BOOT_DST, CONFIG_SYS_MMC_U_BOOT_SIZE); + flush_cache(CFG_SYS_MMC_U_BOOT_DST, CFG_SYS_MMC_U_BOOT_SIZE); /* * Jump to U-Boot image */ - uboot = (void *)CONFIG_SYS_MMC_U_BOOT_START; + uboot = (void *)CFG_SYS_MMC_U_BOOT_START; (*uboot)(); } diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 607a22368cb..d91819acfd7 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -24,8 +24,8 @@ #include #include "atmel_mci.h" -#ifndef CONFIG_SYS_MMC_CLK_OD -# define CONFIG_SYS_MMC_CLK_OD 150000 +#ifndef CFG_SYS_MMC_CLK_OD +# define CFG_SYS_MMC_CLK_OD 150000 #endif #define MMC_DEFAULT_BLKLEN 512 @@ -448,9 +448,9 @@ static int mci_init(struct mmc *mmc) /* Set default clocks and blocklen */ #ifdef CONFIG_DM_MMC - mci_set_mode(dev, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + mci_set_mode(dev, CFG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); #else - mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + mci_set_mode(mmc, CFG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); #endif return 0; diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c index b2d0fac9636..3ce7cbf71f8 100644 --- a/drivers/mmc/sh_sdhi.c +++ b/drivers/mmc/sh_sdhi.c @@ -761,7 +761,7 @@ int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks) struct mmc *mmc; struct sh_sdhi_host *host = NULL; - if (ch >= CONFIG_SYS_SH_SDHI_NR_CHANNEL) + if (ch >= CFG_SYS_SH_SDHI_NR_CHANNEL) return -ENODEV; host = malloc(sizeof(struct sh_sdhi_host)); diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index d34d8ee9767..c1cdd2cbc3e 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -53,7 +53,7 @@ * AMD/Spansion Application Note: Migration from Single-byte to Three-byte * Device IDs, Publication Number 25538 Revision A, November 8, 2001 * - * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between + * Define CFG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between * reading and writing ... (yes there is such a Hardware). */ @@ -119,14 +119,14 @@ phys_addr_t cfi_flash_bank_addr(int i) #else __weak phys_addr_t cfi_flash_bank_addr(int i) { - return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; + return ((phys_addr_t [])CFG_SYS_FLASH_BANKS_LIST)[i]; } #endif __weak unsigned long cfi_flash_bank_size(int i) { -#ifdef CONFIG_SYS_FLASH_BANKS_SIZES - return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i]; +#ifdef CFG_SYS_FLASH_BANKS_SIZES + return ((unsigned long [])CFG_SYS_FLASH_BANKS_SIZES)[i]; #else return 0; #endif @@ -178,7 +178,7 @@ __maybe_weak u64 flash_read64(void *addr) */ #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || \ (defined(CONFIG_SYS_MONITOR_BASE) && \ - (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)) + (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE)) static flash_info_t *flash_get_info(ulong base) { int i; @@ -227,7 +227,7 @@ static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) int i; int cword_offset; int cp_offset; -#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA) u32 cmd_le = cpu_to_le32(cmd); #endif uchar val; @@ -235,7 +235,7 @@ static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) for (i = info->portwidth; i > 0; i--) { cword_offset = (info->portwidth - i) % info->chipwidth; -#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA) cp_offset = info->portwidth - i; val = *((uchar *)&cmd_le + cword_offset); #else @@ -292,7 +292,7 @@ static inline uchar flash_read_uchar(flash_info_t *info, uint offset) uchar retval; cp = flash_map(info, 0, offset); -#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA) retval = flash_read8(cp); #else retval = flash_read8(cp + info->portwidth - 1); @@ -335,7 +335,7 @@ static ulong flash_read_long (flash_info_t *info, flash_sect_t sect, for (x = 0; x < 4 * info->portwidth; x++) debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); #endif -#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA) retval = ((flash_read8(addr) << 16) | (flash_read8(addr + info->portwidth) << 24) | (flash_read8(addr + 2 * info->portwidth)) | @@ -580,7 +580,7 @@ static int flash_status_check(flash_info_t *info, flash_sect_t sector, #endif /* Wait for command completion */ -#ifdef CONFIG_SYS_LOW_RES_TIMER +#ifdef CFG_SYS_LOW_RES_TIMER reset_timer(); #endif start = get_timer(0); @@ -673,7 +673,7 @@ static int flash_status_poll(flash_info_t *info, void *src, void *dst, #endif /* Wait for command completion */ -#ifdef CONFIG_SYS_LOW_RES_TIMER +#ifdef CFG_SYS_LOW_RES_TIMER reset_timer(); #endif start = get_timer(0); @@ -713,7 +713,7 @@ static int flash_status_poll(flash_info_t *info, void *src, void *dst, */ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) { -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA) unsigned short w; unsigned int l; unsigned long long ll; @@ -724,7 +724,7 @@ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) cword->w8 = c; break; case FLASH_CFI_16BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA) w = c; w <<= 8; cword->w16 = (cword->w16 >> 8) | w; @@ -733,7 +733,7 @@ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) #endif break; case FLASH_CFI_32BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA) l = c; l <<= 24; cword->w32 = (cword->w32 >> 8) | l; @@ -742,7 +742,7 @@ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) #endif break; case FLASH_CFI_64BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA) ll = c; ll <<= 56; cword->w64 = (cword->w64 >> 8) | ll; @@ -2359,7 +2359,7 @@ static void flash_protect_default(void) /* Monitor protection ON by default */ #if defined(CONFIG_SYS_MONITOR_BASE) && \ - (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ + (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE) && \ (!defined(CONFIG_MONITOR_IS_IN_RAM)) flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c index 59de3256405..18abd754418 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_nand.c +++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c @@ -780,10 +780,10 @@ static void fsl_ifc_ctrl_init(void) ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev); if (ver >= FSL_IFC_V2_0_0) ifc_ctrl->regs.rregs = - (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET; + (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET; else ifc_ctrl->regs.rregs = - (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET; + (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET; /* clear event registers */ ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U); diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index 7d4b77dd11d..3b464ce10ce 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -54,14 +54,14 @@ static inline int check_read_ecc(uchar *buf, u32 *eccstat, static inline struct fsl_ifc_runtime *runtime_regs_address(void) { - struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL}; + struct fsl_ifc regs = {(void *)CFG_SYS_IFC_ADDR, NULL}; int ver = 0; ver = ifc_in32(®s.gregs->ifc_rev); if (ver >= FSL_IFC_V2_0_0) - regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET; + regs.rregs = (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET; else - regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET; + regs.rregs = (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET; return regs.rregs; } @@ -108,7 +108,7 @@ static inline int bad_block(uchar *marker, int port_size) int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) { - struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR; + struct fsl_ifc_fcm *gregs = (void *)CFG_SYS_IFC_ADDR; struct fsl_ifc_runtime *ifc = NULL; uchar *buf = (uchar *)CFG_SYS_NAND_BASE; int page_size; diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index 5bc5301d634..a884c65d18b 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -84,8 +84,8 @@ struct lpc32xx_nand_mlc_registers { static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers = (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE; -#if !defined(CONFIG_SYS_MAX_NAND_CHIPS) -#define CONFIG_SYS_MAX_NAND_CHIPS 1 +#if !defined(CFG_SYS_MAX_NAND_CHIPS) +#define CFG_SYS_MAX_NAND_CHIPS 1 #endif #define clkdiv(v, w, o) (((1+(clk/v)) & w) << o) @@ -586,7 +586,7 @@ void board_nand_init(void) lpc32xx_nand_init(); /* identify chip */ - ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL); + ret = nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL); if (ret) { pr_err("nand_scan_ident returned %i", ret); return; diff --git a/drivers/mtd/onenand/onenand_spl.c b/drivers/mtd/onenand/onenand_spl.c index ab6f1a8be3e..2699958a5de 100644 --- a/drivers/mtd/onenand/onenand_spl.c +++ b/drivers/mtd/onenand/onenand_spl.c @@ -49,12 +49,12 @@ static inline int onenand_bufferram_address(int block) static inline uint16_t onenand_readw(uint32_t addr) { - return readw(CONFIG_SYS_ONENAND_BASE + addr); + return readw(CFG_SYS_ONENAND_BASE + addr); } static inline void onenand_writew(uint16_t value, uint32_t addr) { - writew(value, CONFIG_SYS_ONENAND_BASE + addr); + writew(value, CFG_SYS_ONENAND_BASE + addr); } static enum onenand_spl_pagesize onenand_spl_get_geometry(void) @@ -82,7 +82,7 @@ static enum onenand_spl_pagesize onenand_spl_get_geometry(void) static int onenand_spl_read_page(uint32_t block, uint32_t page, uint32_t *buf, enum onenand_spl_pagesize pagesize) { - const uint32_t addr = CONFIG_SYS_ONENAND_BASE + ONENAND_DATARAM; + const uint32_t addr = CFG_SYS_ONENAND_BASE + ONENAND_DATARAM; uint32_t offset; onenand_writew(onenand_block_address(block), diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c index 3a8c7b867eb..04791df69bb 100644 --- a/drivers/mtd/onenand/onenand_uboot.c +++ b/drivers/mtd/onenand/onenand_uboot.c @@ -35,7 +35,7 @@ void onenand_init(void) /* It's used for some board init required */ err = onenand_board_init(&onenand_mtd); #else - onenand_chip.base = (void *) CONFIG_SYS_ONENAND_BASE; + onenand_chip.base = (void *) CFG_SYS_ONENAND_BASE; #endif if (!err && !(onenand_scan(&onenand_mtd, 1))) { diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c index 5c41d7558c2..dfc35d6eabf 100644 --- a/drivers/mtd/spi/fsl_espi_spl.c +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -49,8 +49,8 @@ void fsl_spi_boot(void) } #ifdef CONFIG_FSL_CORENET - offset = CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS; - code_len = CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE; + offset = CFG_SYS_SPI_FLASH_U_BOOT_OFFS; + code_len = CFG_SYS_SPI_FLASH_U_BOOT_SIZE; #else /* * Load U-Boot image from SPI flash into RAM @@ -66,7 +66,7 @@ void fsl_spi_boot(void) flash->page_size, (void *)buf); offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR); /* Skip spl code */ - offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS; + offset += CFG_SYS_SPI_FLASH_U_BOOT_OFFS; /* Get the code size from offset 0x48 */ code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE); /* Skip spl code */ @@ -76,7 +76,7 @@ void fsl_spi_boot(void) printf("Loading second stage boot loader "); while (copy_len <= code_len) { spi_flash_read(flash, offset + copy_len, 0x2000, - (void *)(CONFIG_SYS_SPI_FLASH_U_BOOT_DST + (void *)(CFG_SYS_SPI_FLASH_U_BOOT_DST + copy_len)); copy_len = copy_len + 0x2000; putc('.'); @@ -85,7 +85,7 @@ void fsl_spi_boot(void) /* * Jump to U-Boot image */ - flush_cache(CONFIG_SYS_SPI_FLASH_U_BOOT_DST, code_len); - uboot = (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_START; + flush_cache(CFG_SYS_SPI_FLASH_U_BOOT_DST, code_len); + uboot = (void *)CFG_SYS_SPI_FLASH_U_BOOT_START; (*uboot)(); } diff --git a/drivers/mtd/stm32_flash.c b/drivers/mtd/stm32_flash.c index 95afa2d6bc7..4523344ba6b 100644 --- a/drivers/mtd/stm32_flash.c +++ b/drivers/mtd/stm32_flash.c @@ -39,7 +39,7 @@ unsigned long flash_init(void) for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { flash_info[i].flash_id = FLASH_STM32; flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20); + flash_info[i].start[0] = CFG_SYS_FLASH_BASE + (i << 20); flash_info[i].size = sect_sz_kb[0]; for (j = 1; j < CONFIG_SYS_MAX_FLASH_SECT; j++) { flash_info[i].start[j] = flash_info[i].start[j - 1] diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index c23e0c07702..c8381cc7133 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -128,7 +128,7 @@ static void dtsec_init_phy(struct fm_eth *fm_eth) struct dtsec *regs = (struct dtsec *)CFG_SYS_FSL_FM1_DTSEC1_ADDR; /* Assign a Physical address to the TBI */ - out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); + out_be32(®s->tbipa, CFG_SYS_TBIPA_VALUE); #endif if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII || diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 1d3b7aa0583..c476cb31200 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -67,9 +67,9 @@ static void fm_init_muram(int fm_idx, void *reg) void *base = reg; muram[fm_idx].base = base; - muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE; + muram[fm_idx].size = CFG_SYS_FM_MURAM_SIZE; muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE; - muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE; + muram[fm_idx].top = base + CFG_SYS_FM_MURAM_SIZE; } /* diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 8443cbb6b65..618c1bccbe3 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -244,9 +244,9 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) { int off; uint32_t ph; - phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset; + phys_addr_t paddr = CFG_SYS_CCSRBAR_PHYS + info->compat_offset; #ifndef CONFIG_SYS_FMAN_V3 - u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS + + u64 dtsec1_addr = (u64)CFG_SYS_CCSRBAR_PHYS + CFG_SYS_FSL_FM1_DTSEC1_OFFSET; #endif diff --git a/drivers/net/fsl-mc/dpio/qbman_sys.h b/drivers/net/fsl-mc/dpio/qbman_sys.h index 8be38e11a84..ff998d49dc4 100644 --- a/drivers/net/fsl-mc/dpio/qbman_sys.h +++ b/drivers/net/fsl-mc/dpio/qbman_sys.h @@ -256,12 +256,12 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, s->addr_cena = d->cena_bar; s->addr_cinh = d->cinh_bar; - s->cena = (void *)valloc(CONFIG_SYS_PAGE_SIZE); + s->cena = (void *)valloc(CFG_SYS_PAGE_SIZE); if (!s->cena) { printf("Could not allocate page for cena shadow\n"); return -1; } - memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE); + memset((void *)s->cena, 0x00, CFG_SYS_PAGE_SIZE); #ifdef QBMAN_CHECKING /* We should never be asked to initialise for a portal that isn't in diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 68833f9ddd9..69da465eaab 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -54,7 +54,7 @@ static int mc_memset_resv_ram; static struct mc_version mc_ver_info; static int mc_boot_status = -1; static int mc_dpl_applied = -1; -#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET static int mc_aiop_applied = -1; #endif struct fsl_mc_io *root_mc_io = NULL; @@ -500,13 +500,13 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr) int dpc_size; #endif -#ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET - BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 || - CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff); +#ifdef CFG_SYS_LS_MC_DRAM_DPC_OFFSET + BUILD_BUG_ON((CFG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 || + CFG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff); - mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET; + mc_dpc_offset = CFG_SYS_LS_MC_DRAM_DPC_OFFSET; #else -#error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined" +#error "CFG_SYS_LS_MC_DRAM_DPC_OFFSET not defined" #endif /* @@ -531,7 +531,7 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr) } dpc_size = fdt_totalsize(dpc_fdt_hdr); - if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) { + if (dpc_size > CFG_SYS_LS_MC_DPC_MAX_LENGTH) { printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n", dpc_size); return -EINVAL; @@ -576,13 +576,13 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) int dpl_size; #endif -#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET - BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || - CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff); +#ifdef CFG_SYS_LS_MC_DRAM_DPL_OFFSET + BUILD_BUG_ON((CFG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || + CFG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff); - mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET; + mc_dpl_offset = CFG_SYS_LS_MC_DRAM_DPL_OFFSET; #else -#error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined" +#error "CFG_SYS_LS_MC_DRAM_DPL_OFFSET not defined" #endif /* @@ -603,7 +603,7 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) } dpl_size = fdt_totalsize(dpl_fdt_hdr); - if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) { + if (dpl_size > CFG_SYS_LS_MC_DPL_MAX_LENGTH) { printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n", dpl_size); return -EINVAL; @@ -624,7 +624,7 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) */ static unsigned long get_mc_boot_timeout_ms(void) { - unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS; + unsigned long timeout_ms = CFG_SYS_LS_MC_BOOT_TIMEOUT_MS; char *timeout_ms_env_var = env_get(MC_BOOT_TIMEOUT_ENV_VAR); @@ -636,14 +636,14 @@ static unsigned long get_mc_boot_timeout_ms(void) "\' environment variable: %lu\n", timeout_ms); - timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS; + timeout_ms = CFG_SYS_LS_MC_BOOT_TIMEOUT_MS; } } return timeout_ms; } -#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET __weak bool soc_has_aiop(void) { @@ -666,12 +666,12 @@ static int load_mc_aiop_img(u64 aiop_fw_addr) #ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr + - CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); + CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); #else aiop_img = (void *)aiop_fw_addr; mc_copy_image("MC AIOP image", - (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH, - mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); + (u64)aiop_img, CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH, + mc_ram_addr + CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); #endif mc_aiop_applied = 0; @@ -896,7 +896,7 @@ int get_mc_boot_status(void) return mc_boot_status; } -#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET int get_aiop_apply_status(void) { return mc_aiop_applied; @@ -938,14 +938,14 @@ u64 mc_get_dram_addr(void) */ unsigned long mc_get_dram_block_size(void) { - unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; + unsigned long dram_block_size = CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; char *dram_block_size_env_var = env_get(MC_MEM_SIZE_ENV_VAR); if (dram_block_size_env_var) { dram_block_size = hextoul(dram_block_size_env_var, NULL); - if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) { + if (dram_block_size < CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) { printf("fsl-mc: WARNING: Invalid value for \'" MC_MEM_SIZE_ENV_VAR "\' environment variable: %lu\n", @@ -1838,7 +1838,7 @@ static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc, case 's': { char sub_cmd; u64 mc_fw_addr, mc_dpc_addr; -#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET u64 aiop_fw_addr; #endif if (argc < 3) @@ -1864,7 +1864,7 @@ static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc, err = mc_init_object(); break; -#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET case 'a': if (argc < 4) goto usage; diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index 6825f9e27c0..cc61a107403 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -43,11 +43,11 @@ DECLARE_GLOBAL_DATA_PTR; static void init_eth_info(struct fec_info_dma *info) { /* setup Receive and Transmit buffer descriptor */ -#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM +#ifdef CFG_SYS_FEC_BUF_USE_SRAM static u32 tmp; if (info->index == 0) - tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; + tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000; else info->rxbd = (cbd_t *)DBUF_LENGTH; @@ -59,7 +59,7 @@ static void init_eth_info(struct fec_info_dma *info) tmp = (u32)info->txbd; info->txbuf = (char *)((u32)info->txbuf + tmp + - (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); tmp = (u32)info->txbuf; #else info->rxbd = @@ -67,7 +67,7 @@ static void init_eth_info(struct fec_info_dma *info) (PKTBUFSRX * sizeof(cbd_t))); info->txbd = (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE, - (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); info->txbuf = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); #endif @@ -283,15 +283,15 @@ static int fec_init(struct udevice *dev) /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) * Settings: Last, Tx CRC */ - for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) { + for (i = 0; i < CFG_SYS_TX_ETH_BUFFER; i++) { info->txbd[i].cbd_sc = 0; info->txbd[i].cbd_datlen = 0; info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); } - info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; + info->txbd[CFG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; info->used_tbd_idx = 0; - info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER; + info->clean_tbd_num = CFG_SYS_TX_ETH_BUFFER; /* Set Rx FIFO alarm and granularity value */ fecp->rfcr = 0x0c000000; @@ -352,7 +352,7 @@ static int mcdmafec_send(struct udevice *dev, void *packet, int length) miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status); /* process all the consumed TBDs */ - while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) { + while (info->clean_tbd_num < CFG_SYS_TX_ETH_BUFFER) { p_used_tbd = &info->txbd[info->used_tbd_idx]; if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) { #ifdef ET_DEBUG @@ -363,7 +363,7 @@ static int mcdmafec_send(struct udevice *dev, void *packet, int length) } /* clean this buffer descriptor */ - if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1)) + if (info->used_tbd_idx == (CFG_SYS_TX_ETH_BUFFER - 1)) p_used_tbd->cbd_sc = BD_ENET_TX_WRAP; else p_used_tbd->cbd_sc = 0; @@ -371,7 +371,7 @@ static int mcdmafec_send(struct udevice *dev, void *packet, int length) /* update some indeces for a correct handling of TBD ring */ info->clean_tbd_num++; info->used_tbd_idx = (info->used_tbd_idx + 1) - % CONFIG_SYS_TX_ETH_BUFFER; + % CFG_SYS_TX_ETH_BUFFER; } /* Check for valid length of data. */ @@ -389,7 +389,7 @@ static int mcdmafec_send(struct udevice *dev, void *packet, int length) p_tbd->cbd_datlen = length; p_tbd->cbd_bufaddr = (u32)packet; p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; - info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER; + info->tx_idx = (info->tx_idx + 1) % CFG_SYS_TX_ETH_BUFFER; /* Enable DMA transmit task */ MCD_continDma(info->tx_task); @@ -524,8 +524,8 @@ static int mcdmafec_probe(struct udevice *dev) if (val) info->tx_init = fdt32_to_cpu(*val); -#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM - u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; +#ifdef CFG_SYS_FEC_BUF_USE_SRAM + u32 tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000; #endif init_eth_info(info); diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 4dd848932b9..ec1fae9688b 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -39,11 +39,11 @@ DECLARE_GLOBAL_DATA_PTR; static void init_eth_info(struct fec_info_s *info) { -#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM +#ifdef CFG_SYS_FEC_BUF_USE_SRAM static u32 tmp; if (info->index == 0) - tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; + tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000; else info->rxbd = (cbd_t *)DBUF_LENGTH; @@ -56,7 +56,7 @@ static void init_eth_info(struct fec_info_s *info) tmp = (u32)info->txbd; info->txbuf = (char *)((u32)info->txbuf + tmp + - (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); tmp = (u32)info->txbuf; #else info->rxbd = @@ -387,7 +387,7 @@ static int mcffec_send(struct udevice *dev, void *packet, int length) /* Activate transmit Buffer Descriptor polling */ fecp->tdar = 0x01000000; /* Descriptor polling active */ -#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM +#ifndef CFG_SYS_FEC_BUF_USE_SRAM /* * FEC unable to initial transmit data packet. * A nop will ensure the descriptor polling active completed. diff --git a/drivers/net/qe/uec.h b/drivers/net/qe/uec.h index 32b7d3e5613..551d7061ccc 100644 --- a/drivers/net/qe/uec.h +++ b/drivers/net/qe/uec.h @@ -605,10 +605,10 @@ enum uec_num_of_threads { #define STD_UEC_INFO(num) \ { \ .uf_info = { \ - .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\ - .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \ - .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \ - .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\ + .ucc_num = CFG_SYS_UEC##num##_UCC_NUM,\ + .rx_clock = CFG_SYS_UEC##num##_RX_CLK, \ + .tx_clock = CFG_SYS_UEC##num##_TX_CLK, \ + .eth_type = CFG_SYS_UEC##num##_ETH_TYPE,\ }, \ .num_threads_tx = UEC_NUM_OF_THREADS_1, \ .num_threads_rx = UEC_NUM_OF_THREADS_1, \ @@ -616,9 +616,9 @@ enum uec_num_of_threads { .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ .tx_bd_ring_len = 16, \ .rx_bd_ring_len = 16, \ - .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \ - .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \ - .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \ + .phy_address = CFG_SYS_UEC##num##_PHY_ADDR, \ + .enet_interface_type = CFG_SYS_UEC##num##_INTERFACE_TYPE, \ + .speed = CFG_SYS_UEC##num##_INTERFACE_SPEED, \ } struct uec_inf { diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index d69a9ff4773..8b6f034ea16 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -764,7 +764,7 @@ static int tsec_initialize(struct bd_info *bis, priv->phyregs_sgmii = tsec_info->miiregs_sgmii; priv->phyaddr = tsec_info->phyaddr; - priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE; + priv->tbiaddr = CFG_SYS_TBIPA_VALUE; priv->flags = tsec_info->flags; strcpy(dev->name, tsec_info->devname); @@ -832,7 +832,7 @@ int tsec_probe(struct udevice *dev) struct eth_pdata *pdata = dev_get_plat(dev); struct tsec_private *priv = dev_get_priv(dev); struct ofnode_phandle_args phandle_args; - u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE; + u32 tbiaddr = CFG_SYS_TBIPA_VALUE; struct tsec_data *data; ofnode parent, child; fdt_addr_t reg; diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c index af8d99cefbe..09883f06be2 100644 --- a/drivers/net/vsc7385.c +++ b/drivers/net/vsc7385.c @@ -39,13 +39,13 @@ int vsc7385_upload_firmware(void *firmware, unsigned int size) u8 *fw = firmware; unsigned int i; - u32 *gloreset = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c050); - u32 *icpu_ctrl = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c040); - u32 *icpu_addr = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c044); - u32 *icpu_data = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c048); - u32 *icpu_rom_map = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c070); + u32 *gloreset = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c050); + u32 *icpu_ctrl = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c040); + u32 *icpu_addr = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c044); + u32 *icpu_data = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c048); + u32 *icpu_rom_map = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c070); #ifdef DEBUG - u32 *chipid = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c060); + u32 *chipid = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c060); #endif out_be32(gloreset, 3); diff --git a/drivers/power/power_dialog.c b/drivers/power/power_dialog.c index e286dd108f3..ad7aaf35a9a 100644 --- a/drivers/power/power_dialog.c +++ b/drivers/power/power_dialog.c @@ -24,7 +24,7 @@ int pmic_dialog_init(unsigned char bus) p->number_of_regs = DIALOG_NUM_OF_REGS; p->interface = PMIC_I2C; - p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR; + p->hw.i2c.addr = CFG_SYS_DIALOG_PMIC_I2C_ADDR; p->hw.i2c.tx_num = 1; p->bus = bus; diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 83461c024c7..63371e71bf7 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -605,10 +605,10 @@ enum uec_num_of_threads { #define STD_UEC_INFO(num) \ { \ .uf_info = { \ - .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\ - .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \ - .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \ - .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\ + .ucc_num = CFG_SYS_UEC##num##_UCC_NUM,\ + .rx_clock = CFG_SYS_UEC##num##_RX_CLK, \ + .tx_clock = CFG_SYS_UEC##num##_TX_CLK, \ + .eth_type = CFG_SYS_UEC##num##_ETH_TYPE,\ }, \ .num_threads_tx = UEC_NUM_OF_THREADS_1, \ .num_threads_rx = UEC_NUM_OF_THREADS_1, \ @@ -616,9 +616,9 @@ enum uec_num_of_threads { .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ .tx_bd_ring_len = 16, \ .rx_bd_ring_len = 16, \ - .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \ - .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \ - .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \ + .phy_address = CFG_SYS_UEC##num##_PHY_ADDR, \ + .enet_interface_type = CFG_SYS_UEC##num##_INTERFACE_TYPE, \ + .speed = CFG_SYS_UEC##num##_INTERFACE_SPEED, \ } struct uec_inf { diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 9d429c832f4..fcf06d10328 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -52,7 +52,7 @@ * * Some boards do not have a PHY for each ethernet port. These ports are known * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate - * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address) + * CFG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address) * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network * speed and duplex should be for the port. @@ -61,10 +61,10 @@ * #define CONFIG_FIXED_PHY 0xFFFFFFFF * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address) * - * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR - * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02 - * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR - * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04 + * #define CFG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR + * #define CFG_SYS_UEC2_PHY_ADDR 0x02 + * #define CFG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR + * #define CFG_SYS_UEC4_PHY_ADDR 0x04 * * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \ * {name, speed, duplex}, diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 40ca66bdcee..0e9d3d24dd8 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -80,8 +80,8 @@ enum ds_type { #endif /*---------------------------------------------------------------------*/ -#ifndef CONFIG_SYS_I2C_RTC_ADDR -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#ifndef CFG_SYS_I2C_RTC_ADDR +# define CFG_SYS_I2C_RTC_ADDR 0x68 #endif #if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000) @@ -212,13 +212,13 @@ void rtc_reset (void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } #endif /* !CONFIG_DM_RTC */ diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index 486c01f9ba2..2c780ab8edf 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -184,13 +184,13 @@ void rtc_reset (void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } #else static uchar rtc_read(struct udevice *dev, uchar reg) diff --git a/drivers/rtc/ds1374.c b/drivers/rtc/ds1374.c index 9f2647d707e..89442f9386b 100644 --- a/drivers/rtc/ds1374.c +++ b/drivers/rtc/ds1374.c @@ -29,8 +29,8 @@ #endif /*---------------------------------------------------------------------*/ -#ifndef CONFIG_SYS_I2C_RTC_ADDR -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#ifndef CFG_SYS_I2C_RTC_ADDR +# define CFG_SYS_I2C_RTC_ADDR 0x68 #endif #if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000) @@ -194,21 +194,21 @@ void rtc_reset (void){ */ static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write(uchar reg, uchar val, bool set) { if (set == true) { - val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg); - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + val |= i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } else { - val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val; - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + val = i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg) & ~val; + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } } static void rtc_write_raw (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c index 5b72e86768a..bd32ed2dbf9 100644 --- a/drivers/rtc/ds3231.c +++ b/drivers/rtc/ds3231.c @@ -164,13 +164,13 @@ void rtc_enable_32khz_output(void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } #else static int ds3231_rtc_get(struct udevice *dev, struct rtc_time *tmp) diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 8be532c3e31..66a0faa0ecf 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -319,7 +319,7 @@ int rtc_get(struct rtc_time *tm) { u8 buf[M41T62_DATETIME_REG_SIZE]; - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); m41t62_update_rtc_time(tm, buf); return 0; @@ -329,10 +329,10 @@ int rtc_set(struct rtc_time *tm) { u8 buf[M41T62_DATETIME_REG_SIZE]; - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); m41t62_set_rtc_buf(tm, buf); - if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, + if (i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) { printf("I2C write failed in %s()\n", __func__); return -1; @@ -349,8 +349,8 @@ void rtc_reset(void) * M41T82: Make sure HT (Halt Update) bit is cleared. * This bit is 0 in M41T62 so its save to clear it always. */ - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); + i2c_read(CFG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); val &= ~M41T80_ALHOUR_HT; - i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); + i2c_write(CFG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); } #endif /* CONFIG_DM_RTC */ diff --git a/drivers/rtc/max6900.c b/drivers/rtc/max6900.c index 11928839dcf..e03a87f94da 100644 --- a/drivers/rtc/max6900.c +++ b/drivers/rtc/max6900.c @@ -16,20 +16,20 @@ #include #include -#ifndef CONFIG_SYS_I2C_RTC_ADDR -#define CONFIG_SYS_I2C_RTC_ADDR 0x50 +#ifndef CFG_SYS_I2C_RTC_ADDR +#define CFG_SYS_I2C_RTC_ADDR 0x50 #endif /* ------------------------------------------------------------------------- */ static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); udelay(2500); } diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c index 19faefba7c8..91a412440b8 100644 --- a/drivers/rtc/pcf8563.c +++ b/drivers/rtc/pcf8563.c @@ -111,12 +111,12 @@ void rtc_reset (void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } #else static int pcf8563_rtc_get(struct udevice *dev, struct rtc_time *tmp) diff --git a/drivers/rtc/pt7c4338.c b/drivers/rtc/pt7c4338.c index c987494b669..e0a7bd3662f 100644 --- a/drivers/rtc/pt7c4338.c +++ b/drivers/rtc/pt7c4338.c @@ -53,12 +53,12 @@ /****** Helper functions ****************************************/ static u8 rtc_read(u8 reg) { - return i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, reg); + return i2c_reg_read(CFG_SYS_I2C_RTC_ADDR, reg); } static void rtc_write(u8 reg, u8 val) { - i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write(CFG_SYS_I2C_RTC_ADDR, reg, val); } /****************************************************************/ diff --git a/drivers/rtc/rs5c372.c b/drivers/rtc/rs5c372.c index 97ec001aef5..6b1c23ca5db 100644 --- a/drivers/rtc/rs5c372.c +++ b/drivers/rtc/rs5c372.c @@ -39,8 +39,8 @@ static unsigned int rtc_debug = DEBUG; #define rtc_debug 0 /* gcc will remove all the debug code for us */ #endif -#ifndef CONFIG_SYS_I2C_RTC_ADDR -#define CONFIG_SYS_I2C_RTC_ADDR 0x32 +#ifndef CFG_SYS_I2C_RTC_ADDR +#define CFG_SYS_I2C_RTC_ADDR 0x32 #endif #define RS5C372_RAM_SIZE 0x10 @@ -63,7 +63,7 @@ rs5c372_readram(unsigned char *buf, int len) { int ret; - ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, len); + ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, len); if (ret != 0) { printf("%s: failed to read\n", __FUNCTION__); return ret; @@ -103,7 +103,7 @@ rs5c372_enable(void) buf[14] = 0; /* reg. 13 */ buf[15] = 0; /* reg. 14 */ buf[16] = USE_24HOUR_MODE; /* reg. 15 */ - ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1); + ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1); if (ret != 0) { printf("%s: failed\n", __FUNCTION__); return; @@ -204,7 +204,7 @@ int rtc_set (struct rtc_time *tmp) memset(buf, 0, sizeof(buf)); /* only read register 15 */ - ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1); + ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1); if (ret == 0) { /* need to save register 15 */ @@ -233,7 +233,7 @@ int rtc_set (struct rtc_time *tmp) printf("WARNING: year should be between 1970 and 2069!\n"); buf[7] = bin2bcd(tmp->tm_year % 100); - ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8); + ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8); if (ret != 0) { printf("rs5c372_set_datetime(), i2c_master_send() returned %d\n",ret); return -1; diff --git a/drivers/rtc/rx8010sj.c b/drivers/rtc/rx8010sj.c index d513561b820..bf93b557748 100644 --- a/drivers/rtc/rx8010sj.c +++ b/drivers/rtc/rx8010sj.c @@ -33,8 +33,8 @@ #endif /*---------------------------------------------------------------------*/ -#ifndef CONFIG_SYS_I2C_RTC_ADDR -# define CONFIG_SYS_I2C_RTC_ADDR 0x32 +#ifndef CFG_SYS_I2C_RTC_ADDR +# define CFG_SYS_I2C_RTC_ADDR 0x32 #endif /* @@ -313,7 +313,7 @@ static int rx8010sj_rtc_reset(DEV_TYPE *dev) int rtc_get(struct rtc_time *tm) { struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, + .chip = CFG_SYS_I2C_RTC_ADDR, }; return rx8010sj_rtc_get(&dev, tm); @@ -322,7 +322,7 @@ int rtc_get(struct rtc_time *tm) int rtc_set(struct rtc_time *tm) { struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, + .chip = CFG_SYS_I2C_RTC_ADDR, }; return rx8010sj_rtc_set(&dev, tm); @@ -331,7 +331,7 @@ int rtc_set(struct rtc_time *tm) void rtc_reset(void) { struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, + .chip = CFG_SYS_I2C_RTC_ADDR, }; rx8010sj_rtc_reset(&dev); @@ -340,7 +340,7 @@ void rtc_reset(void) void rtc_init(void) { struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, + .chip = CFG_SYS_I2C_RTC_ADDR, }; rx8010sj_rtc_init(&dev); diff --git a/drivers/rtc/x1205.c b/drivers/rtc/x1205.c index ce23427b174..4a8d1c5903f 100644 --- a/drivers/rtc/x1205.c +++ b/drivers/rtc/x1205.c @@ -77,7 +77,7 @@ static void rtc_write(int reg, u8 val) { - i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1); + i2c_write(CFG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1); } /* @@ -89,7 +89,7 @@ int rtc_get(struct rtc_time *tm) { u8 buf[8]; - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); + i2c_read(CFG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 83cda1f2040..8a489a2e3f9 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; /* * Table with supported baudrates (defined in config_xyz.h) */ -static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; +static const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE; #if CONFIG_IS_ENABLED(SERIAL_PRESENT) static int serial_check_stdout(const void *blob, struct udevice **devp) diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 6cdbb89841c..4d549650948 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -22,7 +22,7 @@ static struct serial_device *serial_current; /* * Table with supported baudrates (defined in config_xyz.h) */ -static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; +static const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE; /** * serial_null() - Void registration routine of a serial driver @@ -459,7 +459,7 @@ void default_serial_puts(const char *s) } #if CONFIG_POST & CONFIG_SYS_POST_UART -static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE; +static const int bauds[] = CFG_SYS_BAUDRATE_TABLE; /** * uart_post_test() - Test the currently selected serial port using POST diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 0ee6171108a..9ebc4ed48f0 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -225,7 +225,7 @@ static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs) SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); /* setup format */ - scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; + scalar = ((CFG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; /* * Use following format: @@ -314,7 +314,7 @@ static int davinci_spi_set_speed(struct udevice *bus, uint max_hz) struct davinci_spi_slave *ds = dev_get_priv(bus); debug("%s speed %u\n", __func__, max_hz); - if (max_hz > CONFIG_SYS_SPI_CLK / 2) + if (max_hz > CFG_SYS_SPI_CLK / 2) return -EINVAL; ds->freq = max_hz; diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index bc5da0a1e6e..2bb7390bbfb 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -131,7 +131,7 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint hz) * follows: * SPI actual frequency = core_clk / (SPR * (2 ^ SPPR)) */ - divider = DIV_ROUND_UP(CONFIG_SYS_TCLK, hz); + divider = DIV_ROUND_UP(CFG_SYS_TCLK, hz); if (divider < 16) { /* This is the easy case, divider is less than 16 */ spr = divider; @@ -205,7 +205,7 @@ static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode) data = readl(®->timing1); data &= ~KW_SPI_TMISO_SAMPLE_MASK; - if (CONFIG_SYS_TCLK == 250000000 && + if (CFG_SYS_TCLK == 250000000 && mode & SPI_CPOL && mode & SPI_CPHA) data |= KW_SPI_TMISO_SAMPLE_2; diff --git a/drivers/sysreset/sysreset_xtfpga.c b/drivers/sysreset/sysreset_xtfpga.c index ad1781e6c0f..84fbc79016a 100644 --- a/drivers/sysreset/sysreset_xtfpga.c +++ b/drivers/sysreset/sysreset_xtfpga.c @@ -15,8 +15,8 @@ static int xtfpga_reset_request(struct udevice *dev, enum sysreset_t type) { switch (type) { case SYSRESET_COLD: - writel(CONFIG_SYS_FPGAREG_RESET_CODE, - CONFIG_SYS_FPGAREG_RESET); + writel(CFG_SYS_FPGAREG_RESET_CODE, + CFG_SYS_FPGAREG_RESET); break; default: return -EPROTONOSUPPORT; diff --git a/drivers/timer/arm_global_timer.c b/drivers/timer/arm_global_timer.c index 065f10bb742..2e50d9fbc58 100644 --- a/drivers/timer/arm_global_timer.c +++ b/drivers/timer/arm_global_timer.c @@ -59,7 +59,7 @@ static int arm_global_timer_probe(struct udevice *dev) return ret; uc_priv->clock_rate = ret; } else { - uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; + uc_priv->clock_rate = CFG_SYS_HZ_CLOCK; } /* init timer */ diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c index 72be2977547..9c3b64ae5b1 100644 --- a/drivers/timer/imx-gpt-timer.c +++ b/drivers/timer/imx-gpt-timer.c @@ -28,9 +28,9 @@ #define GPT_CLKSRC_IPG_CLK (1 << 6) #define GPT_CLKSRC_IPG_CLK_24M (5 << 6) -/* If CONFIG_SYS_HZ_CLOCK not specified et's default to 3Mhz */ -#ifndef CONFIG_SYS_HZ_CLOCK -#define CONFIG_SYS_HZ_CLOCK 3000000 +/* If CFG_SYS_HZ_CLOCK not specified et's default to 3Mhz */ +#ifndef CFG_SYS_HZ_CLOCK +#define CFG_SYS_HZ_CLOCK 3000000 #endif struct imx_gpt_timer_regs { @@ -60,7 +60,7 @@ static u64 imx_gpt_timer_get_count(struct udevice *dev) static int imx_gpt_setup(struct imx_gpt_timer_regs *regs, u32 rate) { - u32 prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1; + u32 prescaler = (rate / CFG_SYS_HZ_CLOCK) - 1; /* Reset the timer */ setbits_le32(®s->cr, GPT_CR_SWR); @@ -138,7 +138,7 @@ static int imx_gpt_timer_probe(struct udevice *dev) return ret; } - uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; + uc_priv->clock_rate = CFG_SYS_HZ_CLOCK; return 0; } diff --git a/drivers/timer/orion-timer.c b/drivers/timer/orion-timer.c index d0eab3ce781..d588f0cbcd1 100644 --- a/drivers/timer/orion-timer.c +++ b/drivers/timer/orion-timer.c @@ -72,7 +72,7 @@ unsigned long notrace timer_early_get_rate(void) if (IS_ENABLED(CONFIG_ARCH_MVEBU)) return MVEBU_TIMER_FIXED_RATE_25MHZ; else - return CONFIG_SYS_TCLK; + return CFG_SYS_TCLK; } /** @@ -117,7 +117,7 @@ static int orion_timer_probe(struct udevice *dev) if (type == INPUT_CLOCK_25MHZ) uc_priv->clock_rate = MVEBU_TIMER_FIXED_RATE_25MHZ; else - uc_priv->clock_rate = CONFIG_SYS_TCLK; + uc_priv->clock_rate = CFG_SYS_TCLK; orion_timer_init(priv->base, type); return 0; diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c index f07251e54c0..1213a14ef19 100644 --- a/drivers/timer/stm32_timer.c +++ b/drivers/timer/stm32_timer.c @@ -97,11 +97,11 @@ static int stm32_timer_probe(struct udevice *dev) rate = clk_get_rate(&clk); /* we set timer prescaler to obtain a 1MHz timer counter frequency */ - psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1; + psc = (rate / CFG_SYS_HZ_CLOCK) - 1; writel(psc, ®s->psc); /* Set timer frequency to 1MHz */ - uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; + uc_priv->clock_rate = CFG_SYS_HZ_CLOCK; /* Configure timer for auto-reload */ setbits_le32(®s->cr1, CR1_ARPE); diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 9acef5ee4f8..3f4418198cc 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1993,7 +1993,7 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) gohci.disabled = 1; gohci.sleeping = 0; gohci.irq = -1; - gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; + gohci.regs = (struct ohci_regs *)CFG_SYS_USB_OHCI_REGS_BASE; gohci.flags = 0; gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c index 54d1efc8f5f..b0a99c9cd5d 100644 --- a/drivers/video/imx/ipu_common.c +++ b/drivers/video/imx/ipu_common.c @@ -221,13 +221,13 @@ static struct clk ipu_clk = { .usecount = 0, }; -#if !defined CONFIG_SYS_LDB_CLOCK -#define CONFIG_SYS_LDB_CLOCK 65000000 +#if !defined CFG_SYS_LDB_CLOCK +#define CFG_SYS_LDB_CLOCK 65000000 #endif static struct clk ldb_clk = { .name = "ldb_clk", - .rate = CONFIG_SYS_LDB_CLOCK, + .rate = CFG_SYS_LDB_CLOCK, .usecount = 0, }; diff --git a/env/Kconfig b/env/Kconfig index 24111dfaf47..4e506ae262b 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -140,7 +140,7 @@ config ENV_IS_IN_FLASH type flash chips the second sector can be used: the offset for this sector is given here. - CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE. + CONFIG_ENV_OFFSET is used relative to CFG_SYS_FLASH_BASE. CONFIG_ENV_ADDR: diff --git a/env/embedded.c b/env/embedded.c index 9f26e6cad9c..27fb45bf8c3 100644 --- a/env/embedded.c +++ b/env/embedded.c @@ -92,6 +92,6 @@ unsigned long env_size __UBOOT_ENV_SECTION__(env_size) = sizeof(env_t); /* * Add in absolutes. */ -GEN_ABS(env_offset, (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)); +GEN_ABS(env_offset, (CONFIG_ENV_ADDR - CFG_SYS_FLASH_BASE)); #endif /* ENV_IS_EMBEDDED */ diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index 17c76bcf3db..d60f494b58b 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -17,8 +17,8 @@ #endif #endif -#ifndef CONFIG_SYS_BAUDRATE_TABLE -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#ifndef CFG_SYS_BAUDRATE_TABLE +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #endif #endif /* __CONFIG_FALLBACKS_H */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 6dfa3dd0f02..246437a51e2 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -13,7 +13,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #define CONFIG_WATCHDOG_TIMEOUT 5000 @@ -41,11 +41,11 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ -#define CONFIG_SYS_PLL_ODR 0x36 -#define CONFIG_SYS_PLL_FDR 0x7D +#define CFG_SYS_CLK 166666666 /* CPU Core Clock */ +#define CFG_SYS_PLL_ODR 0x36 +#define CFG_SYS_PLL_FDR 0x7D -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 /* * Low Level Configuration Settings @@ -53,9 +53,9 @@ * You should know what you are doing if you make changes here. */ /* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221 /* * Start addresses for the final memory configuration @@ -75,14 +75,14 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* * Configuration for environment @@ -95,15 +95,15 @@ /* Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -117,8 +117,8 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007F0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x007F0001 +#define CFG_SYS_CS0_CTRL 0x00001FA0 #endif /* _M5208EVBE_H */ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index e28662c6e59..128ef50b476 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -18,14 +18,14 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ /* I2C */ -#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) -#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) -#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) +#define CFG_SYS_I2C_PINMUX_REG (gpio->par_qspi) +#define CFG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) +#define CFG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */ #ifdef CONFIG_MCFFEC @@ -50,10 +50,10 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 75000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 +#define CFG_SYS_CLK 75000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 2 -#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000 /* * Low Level Configuration Settings @@ -63,9 +63,9 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x21 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -81,16 +81,16 @@ * the maximum mapped by the Linux kernel during initialization ?? */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -104,15 +104,15 @@ * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -130,13 +130,13 @@ * CS7 - Available */ #ifdef CONFIG_NORFLASH_PS32BIT -# define CONFIG_SYS_CS0_BASE 0xFFC00000 -# define CONFIG_SYS_CS0_MASK 0x003f0001 -# define CONFIG_SYS_CS0_CTRL 0x00001D00 +# define CFG_SYS_CS0_BASE 0xFFC00000 +# define CFG_SYS_CS0_MASK 0x003f0001 +# define CFG_SYS_CS0_CTRL 0x00001D00 #else -# define CONFIG_SYS_CS0_BASE 0xFFE00000 -# define CONFIG_SYS_CS0_MASK 0x001f0001 -# define CONFIG_SYS_CS0_CTRL 0x00001D80 +# define CFG_SYS_CS0_BASE 0xFFE00000 +# define CFG_SYS_CS0_MASK 0x001f0001 +# define CFG_SYS_CS0_CTRL 0x00001D80 #endif #endif /* _M5329EVB_H */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index f1da278d515..0e38eeb4a36 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -18,7 +18,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ @@ -26,9 +26,9 @@ * Clock configuration: enable only one of the following options */ -#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ -#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ -#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ +#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ +#define CFG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ /* * Low Level Configuration Settings @@ -36,14 +36,14 @@ * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_MBAR2 0x80000000 +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR2 0x80000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ #define LDS_BOARD_TEXT \ . = DEFINED(env_offset) ? env_offset : .; \ @@ -56,7 +56,7 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) #if 0 /* test-only */ #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ @@ -67,33 +67,33 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \ CF_ADDRMASK(2) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ +#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ CF_CACR_DBWE) /*----------------------------------------------------------------------- @@ -101,25 +101,25 @@ */ /* CS0 - AMD Flash, address 0xffc00000 */ -#define CONFIG_SYS_CS0_BASE 0xffe00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ +#define CFG_SYS_CS0_BASE 0xffe00000 +#define CFG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ -#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ +#define CFG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ /* CS1 - FPGA, address 0xe0000000 */ -#define CONFIG_SYS_CS1_BASE 0xe0000000 -#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ -#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ +#define CFG_SYS_CS1_BASE 0xe0000000 +#define CFG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ +#define CFG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ -#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ -#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ +#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ +#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */ #endif /* M5249 */ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index bd3c57d1438..7e37c6d1199 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -8,7 +8,7 @@ #include -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) /* Configuration for environment @@ -20,7 +20,7 @@ env/embedded.o(.text*); #ifdef CONFIG_DRIVER_DM9000 -# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) +# define CONFIG_DM9000_BASE (CFG_SYS_CS1_BASE | 0x300) # define DM9000_IO CONFIG_DM9000_BASE # define DM9000_DATA (CONFIG_DM9000_BASE + 4) # undef CONFIG_DM9000_DEBUG @@ -45,18 +45,18 @@ #define CONFIG_HOSTNAME "M5253DEMO" /* I2C */ -#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) -#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) -#define CONFIG_SYS_I2C_PINMUX_SET (0) - -#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ -#define CONFIG_SYS_FAST_CLK -#ifdef CONFIG_SYS_FAST_CLK -# define CONFIG_SYS_PLLCR 0x1243E054 -# define CONFIG_SYS_CLK 140000000 +#define CFG_SYS_I2C_PINMUX_REG (*(u32 *) (CFG_SYS_MBAR+0x19C)) +#define CFG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) +#define CFG_SYS_I2C_PINMUX_SET (0) + +#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_SYS_FAST_CLK +#ifdef CFG_SYS_FAST_CLK +# define CFG_SYS_PLLCR 0x1243E054 +# define CFG_SYS_CLK 140000000 #else -# define CONFIG_SYS_PLLCR 0x135a4140 -# define CONFIG_SYS_CLK 70000000 +# define CFG_SYS_PLLCR 0x135a4140 +# define CFG_SYS_CLK 70000000 #endif /* @@ -65,14 +65,14 @@ * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ /* * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ /* * Start addresses for the final memory configuration @@ -87,10 +87,10 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) #define FLASH_SST6401B 0x200 #define SST_ID_xF6401B 0x236D236D @@ -101,45 +101,45 @@ * Amd/Atmel use 0x30 for sector erase, SST use 0x50. * 0x30 is block erase in SST */ -# define CONFIG_SYS_FLASH_SIZE 0x800000 +# define CFG_SYS_FLASH_SIZE 0x800000 #else -# define CONFIG_SYS_SST_SECT 2048 -# define CONFIG_SYS_SST_SECTSZ 0x1000 +# define CFG_SYS_SST_SECT 2048 +# define CFG_SYS_SST_SECTSZ 0x1000 #endif /* Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \ CF_ADDRMASK(8) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ +#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ CF_CACR_DBWE) -#define CONFIG_SYS_CS0_BASE 0xFF800000 -#define CONFIG_SYS_CS0_MASK 0x007F0021 -#define CONFIG_SYS_CS0_CTRL 0x00001D80 +#define CFG_SYS_CS0_BASE 0xFF800000 +#define CFG_SYS_CS0_MASK 0x007F0021 +#define CFG_SYS_CS0_CTRL 0x00001D80 -#define CONFIG_SYS_CS1_BASE 0xE0000000 -#define CONFIG_SYS_CS1_MASK 0x00000001 -#define CONFIG_SYS_CS1_CTRL 0x00003DD8 +#define CFG_SYS_CS1_BASE 0xE0000000 +#define CFG_SYS_CS1_MASK 0x00000001 +#define CFG_SYS_CS1_CTRL 0x00003DD8 /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ -#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ -#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ +#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ +#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */ #endif /* _M5253DEMO_H */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 7c3bc032bfe..847b4c2593d 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -17,7 +17,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ @@ -51,22 +51,22 @@ "save\0" \ "" -#define CONFIG_SYS_CLK 66000000 +#define CFG_SYS_CLK 66000000 /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_SCR 0x0003 -#define CONFIG_SYS_SPR 0xffff +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_SCR 0x0003 +#define CFG_SYS_SPR 0xffff /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -75,35 +75,35 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 +#define CFG_SYS_FLASH_BASE 0xffe00000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -111,11 +111,11 @@ /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_PACNT 0x00000000 -#define CONFIG_SYS_PADDR 0x0000 -#define CONFIG_SYS_PADAT 0x0000 -#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ -#define CONFIG_SYS_PBDDR 0x0000 -#define CONFIG_SYS_PBDAT 0x0000 -#define CONFIG_SYS_PDCNT 0x00000000 +#define CFG_SYS_PACNT 0x00000000 +#define CFG_SYS_PADDR 0x0000 +#define CFG_SYS_PADAT 0x0000 +#define CFG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ +#define CFG_SYS_PBDDR 0x0000 +#define CFG_SYS_PBDAT 0x0000 +#define CFG_SYS_PDCNT 0x00000000 #endif /* _M5272C3_H */ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 4eb4abea725..ff9f8535896 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -21,7 +21,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -34,9 +34,9 @@ /* Available command configuration */ /* I2C */ -#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) -#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) -#define CONFIG_SYS_I2C_PINMUX_SET (0x000F) +#define CFG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) +#define CFG_SYS_I2C_PINMUX_CLR (0xFFF0) +#define CFG_SYS_I2C_PINMUX_SET (0x000F) #ifdef CONFIG_MCFFEC # define CONFIG_OVERWRITE_ETHADDR_ONCE @@ -54,7 +54,7 @@ "save\0" \ "" -#define CONFIG_SYS_CLK 150000000 +#define CFG_SYS_CLK 150000000 /* * Low Level Configuration Settings @@ -62,13 +62,13 @@ * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -77,34 +77,34 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ -#define CONFIG_SYS_FLASH_SIZE 0x200000 +#define CFG_SYS_FLASH_SIZE 0x200000 /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -112,12 +112,12 @@ /*----------------------------------------------------------------------- * Memory bank definitions */ -#define CONFIG_SYS_CS0_BASE 0xffe00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x001F0001 +#define CFG_SYS_CS0_BASE 0xffe00000 +#define CFG_SYS_CS0_CTRL 0x00001980 +#define CFG_SYS_CS0_MASK 0x001F0001 -#define CONFIG_SYS_CS1_BASE 0x30000000 -#define CONFIG_SYS_CS1_CTRL 0x00001900 -#define CONFIG_SYS_CS1_MASK 0x00070001 +#define CFG_SYS_CS1_BASE 0x30000000 +#define CFG_SYS_CS1_CTRL 0x00001900 +#define CFG_SYS_CS1_MASK 0x00070001 #endif /* _M5275EVB_H */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index eda394467e9..bde9e770e52 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -17,7 +17,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ @@ -49,25 +49,25 @@ "save\0" \ "" -#define CONFIG_SYS_CLK 64000000 +#define CFG_SYS_CLK 64000000 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ -#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ -#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ +#define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ +#define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -76,65 +76,65 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 -#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE +#define CFG_SYS_INT_FLASH_BASE 0xf0000000 +#define CFG_SYS_INT_FLASH_ENABLE 0x21 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DBWE | \ CF_CACR_EUSP) /*----------------------------------------------------------------------- * Memory bank definitions */ -#define CONFIG_SYS_CS0_BASE 0xFFE00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x001F0001 +#define CFG_SYS_CS0_BASE 0xFFE00000 +#define CFG_SYS_CS0_CTRL 0x00001980 +#define CFG_SYS_CS0_MASK 0x001F0001 /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ -#define CONFIG_SYS_PADDR 0x0000000 -#define CONFIG_SYS_PADAT 0x0000000 +#define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ +#define CFG_SYS_PADDR 0x0000000 +#define CFG_SYS_PADAT 0x0000000 -#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ -#define CONFIG_SYS_PBDDR 0x0000000 -#define CONFIG_SYS_PBDAT 0x0000000 +#define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CFG_SYS_PBDDR 0x0000000 +#define CFG_SYS_PBDAT 0x0000000 -#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ +#define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PEHLPAR 0xC0 -#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ -#define CONFIG_SYS_DDRUA 0x05 -#define CONFIG_SYS_PJPAR 0xFF +#define CFG_SYS_PEHLPAR 0xC0 +#define CFG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ +#define CFG_SYS_DDRUA 0x05 +#define CFG_SYS_PJPAR 0xFF #endif /* _CONFIG_M5282EVB_H */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 159993a46bc..0e9ba4c3ada 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -18,17 +18,17 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #define CONFIG_WATCHDOG_TIMEOUT 5000 #ifdef CONFIG_MCFFEC -# define CONFIG_SYS_TX_ETH_BUFFER 8 -# define CONFIG_SYS_FEC_BUF_USE_SRAM +# define CFG_SYS_TX_ETH_BUFFER 8 +# define CFG_SYS_FEC_BUF_USE_SRAM #endif -#define CONFIG_SYS_RTC_CNT (0x8000) -#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) +#define CFG_SYS_RTC_CNT (0x8000) +#define CFG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) /* I2C */ @@ -54,10 +54,10 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 /* * Low Level Configuration Settings @@ -67,9 +67,9 @@ /* * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221 /* * Start addresses for the final memory configuration @@ -89,17 +89,17 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_FLASH_SPANSION_S29WS_N 1 -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ #endif -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -113,15 +113,15 @@ * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) /*----------------------------------------------------------------------- @@ -135,12 +135,12 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x00FF0001 +#define CFG_SYS_CS0_CTRL 0x00001FA0 -#define CONFIG_SYS_CS1_BASE 0xC0000000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x00001FA0 +#define CFG_SYS_CS1_BASE 0xC0000000 +#define CFG_SYS_CS1_MASK 0x00070001 +#define CFG_SYS_CS1_CTRL 0x00001FA0 #endif /* _M53017EVB_H */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index d7ece639349..8f83810f165 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -18,7 +18,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ @@ -46,12 +46,12 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 -#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) +#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000) /* * Low Level Configuration Settings @@ -61,9 +61,9 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -83,22 +83,22 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif #ifdef CONFIG_CMD_NAND -# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE +# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE # define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 #endif -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -112,15 +112,15 @@ * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) /*----------------------------------------------------------------------- @@ -134,18 +134,18 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007f0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fa0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x007f0001 +#define CFG_SYS_CS0_CTRL 0x00001fa0 -#define CONFIG_SYS_CS1_BASE 0x10000000 -#define CONFIG_SYS_CS1_MASK 0x001f0001 -#define CONFIG_SYS_CS1_CTRL 0x002A3780 +#define CFG_SYS_CS1_BASE 0x10000000 +#define CFG_SYS_CS1_MASK 0x001f0001 +#define CFG_SYS_CS1_CTRL 0x002A3780 #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK (16 << 20) -#define CONFIG_SYS_CS2_CTRL 0x00001f60 +#define CFG_SYS_CS2_BASE 0x20000000 +#define CFG_SYS_CS2_MASK (16 << 20) +#define CFG_SYS_CS2_CTRL 0x00001f60 #endif #endif /* _M5329EVB_H */ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index b2fc6923e0d..43c642edeb1 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -20,7 +20,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ @@ -48,12 +48,12 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 -#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) +#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000) /* * Low Level Configuration Settings @@ -63,9 +63,9 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -85,20 +85,20 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif -# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE +# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE # define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -112,15 +112,15 @@ * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) /*----------------------------------------------------------------------- @@ -134,16 +134,16 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007f0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fa0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x007f0001 +#define CFG_SYS_CS0_CTRL 0x00001fa0 -#define CONFIG_SYS_CS1_BASE 0x10000000 -#define CONFIG_SYS_CS1_MASK 0x001f0001 -#define CONFIG_SYS_CS1_CTRL 0x002A3780 +#define CFG_SYS_CS1_BASE 0x10000000 +#define CFG_SYS_CS1_MASK 0x001f0001 +#define CFG_SYS_CS1_CTRL 0x002A3780 -#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK (16 << 20) -#define CONFIG_SYS_CS2_CTRL 0x00001f60 +#define CFG_SYS_CS2_BASE 0x20000000 +#define CFG_SYS_CS2_MASK (16 << 20) +#define CFG_SYS_CS2_CTRL 0x00001f60 #endif /* _M5373EVB_H */ diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index 2e7140cd86a..232cf9e9984 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -59,21 +59,21 @@ /* Miscellaneous configurable options */ /* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) -#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800) +#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) +#define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800) /* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE CONFIG_TEXT_BASE +#define CFG_SYS_FLASH_BASE CONFIG_TEXT_BASE /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Environment Configuration */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index d9627e393d9..85c080cf27a 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -25,20 +25,20 @@ */ /* System Clock Configuration Register */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ +#define CFG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ +#define CFG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ +#define CFG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ /* * System IO Config */ -#define CONFIG_SYS_SICRH 0x08200000 -#define CONFIG_SYS_SICRL 0x00000000 +#define CFG_SYS_SICRH 0x08200000 +#define CFG_SYS_SICRL 0x00000000 /* * Output Buffer Impedance */ -#define CONFIG_SYS_OBIR 0x30100000 +#define CFG_SYS_OBIR 0x30100000 /* * Device configurations @@ -60,9 +60,9 @@ * DDR Setup */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 +#define CFG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) +#define CFG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ @@ -70,14 +70,14 @@ * Manually set up DDR parameters */ #define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ +#define CFG_SYS_DDR_CS0_BNDS 0x0000000f +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | CSCONFIG_ODT_WR_ONLY_CURRENT \ | CSCONFIG_ROW_BIT_13 \ | CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ +#define CFG_SYS_DDR_TIMING_3 0x00000000 +#define CFG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | (0 << TIMING_CFG0_WRT_SHIFT) \ | (0 << TIMING_CFG0_RRT_SHIFT) \ | (0 << TIMING_CFG0_WWT_SHIFT) \ @@ -86,7 +86,7 @@ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) /* 0x00260802 */ /* DDR400 */ -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ +#define CFG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | (7 << TIMING_CFG1_CASLAT_SHIFT) \ @@ -95,7 +95,7 @@ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | (2 << TIMING_CFG1_WRTORD_SHIFT)) /* 0x3937d322 */ -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ +#define CFG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ | (5 << TIMING_CFG2_CPO_SHIFT) \ | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ @@ -104,23 +104,23 @@ | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) /* 0x02984cc8 */ -#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ +#define CFG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) /* 0x06090100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ +#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2) /* 0x43000000 */ -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ +#define CFG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ +#define CFG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ | (0x0442 << SDRAM_MODE_SD_SHIFT)) /* 0x04400442 */ /* DDR400 */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 +#define CFG_SYS_DDR_MODE2 0x00000000 /* * Memory test */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#undef CFG_SYS_DRAM_TEST /* memory test, takes time */ /* * The reserved memory @@ -129,14 +129,14 @@ /* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ /* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ +#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ /* * NAND Flash on the Local Bus @@ -146,14 +146,14 @@ /* Vitesse 7385 */ -#define CONFIG_SYS_VSC7385_BASE 0xF0000000 +#define CFG_SYS_VSC7385_BASE 0xF0000000 /* * Serial Port */ #define CFG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} #define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) @@ -165,13 +165,13 @@ #define CONFIG_FSL_SERDES2 0xe3100 /* I2C */ -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } +#define CFG_SYS_I2C_NOPROBES { {0, 0x51} } /* * Config on-board RTC */ #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ /* * General PCI @@ -198,7 +198,7 @@ #ifdef CONFIG_TSEC1 #define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CFG_SYS_TSEC1_OFFSET 0x24000 #define TSEC1_PHY_ADDR 2 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #define TSEC1_PHYIDX 0 @@ -226,7 +226,7 @@ * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Environment Configuration diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 25b4fe0c7d4..ff02c2cd847 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -28,16 +28,16 @@ * Only possible on E500 Version 2 or newer cores. */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xe0000000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ @@ -112,32 +112,32 @@ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx */ -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#define CFG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull +#define CFG_SYS_FLASH_BASE_PHYS 0xfff000000ull #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_FLASH_BANKS_LIST \ - {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST \ + {CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS} #define CONFIG_HWCONFIG /* enable hwconfig */ /* * SDRAM on the Local Bus */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull +#define CFG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull #else -#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE +#define CFG_SYS_LBC_SDRAM_BASE_PHYS CFG_SYS_LBC_SDRAM_BASE #endif -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +#define CFG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ /* * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. + * The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000. * * For BR2, need: * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 @@ -149,12 +149,12 @@ * 0 4 8 12 16 20 24 28 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into * FIXME: the top 17 bits of BR2. */ /* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64. * * For OR2, need: * 64MB mask for AM, OR2[0:7] = 1111 1100 @@ -167,10 +167,10 @@ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 */ -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ +#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ /* * Common settings for all Local Bus SDRAM commands. @@ -178,7 +178,7 @@ * or BSMA1617 (for CPU 1.0) (old) * is OR'ed in too. */ -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ +#define CFG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ | LSDMR_PRETOACT7 \ | LSDMR_ACTTORW7 \ | LSDMR_BL8 \ @@ -226,25 +226,25 @@ #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR #endif -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port */ #define CFG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600) /* * I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +#define CFG_SYS_I2C_NOPROBES { {0, 0x69} } #endif /* @@ -326,7 +326,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ /* * Environment Configuration diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 21491b9f97c..a8af0a101c8 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -16,10 +16,10 @@ #include #ifdef CONFIG_SDCARD -#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (512 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x11000000) +#define CFG_SYS_MMC_U_BOOT_START (0x11000000) +#define CFG_SYS_MMC_U_BOOT_OFFS (96 << 10) #endif #ifdef CONFIG_SPIFLASH @@ -27,10 +27,10 @@ #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #else -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) #endif #endif @@ -111,11 +111,11 @@ extern unsigned long get_sdram_size(void); #endif #define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xffe00000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* * Memory map @@ -136,15 +136,15 @@ extern unsigned long get_sdram_size(void); */ /* NOR Flash on IFC */ -#define CONFIG_SYS_FLASH_BASE 0xee000000 +#define CFG_SYS_FLASH_BASE 0xee000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -161,7 +161,7 @@ extern unsigned long get_sdram_size(void); FTIM2_NOR_TWP(0x1c) #define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ /* CFI for NOR Flash */ @@ -237,85 +237,85 @@ extern unsigned long get_sdram_size(void); /* Set up IFC registers for boot location NOR/NAND */ #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif /* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffb00000 +#define CFG_SYS_CPLD_BASE 0xffb00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull +#define CFG_SYS_CPLD_BASE_PHYS 0xfffb00000ull #else -#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE #endif -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 0x0 +#define CFG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR3 0x0 /* CPLD Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Config the L2 Cache as L2 SRAM */ #if defined(CONFIG_SPL_BUILD) #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xD0000000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xD0000000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #else -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xD0000000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #endif #endif #endif @@ -324,11 +324,11 @@ extern unsigned long get_sdram_size(void); #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600) /* I2C */ #define I2C_PCA9557_ADDR1 0x18 @@ -343,7 +343,7 @@ extern unsigned long get_sdram_size(void); /* RTC */ #define CONFIG_RTC_PT7C4338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* * SPI interface will not be available in case of NAND boot SPI CS0 will be @@ -393,7 +393,7 @@ extern unsigned long get_sdram_size(void); */ #if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10)) #endif #endif @@ -410,7 +410,7 @@ extern unsigned long get_sdram_size(void); * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ /* * Environment Configuration diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index c3ef2163335..1e02855fefd 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -39,32 +39,32 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ +#define CONFIG_POST CFG_SYS_POST_MEMORY /* test POST memory test */ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CFG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ +#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ CONFIG_RAMBOOT_TEXT_BASE) #else -#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR #endif #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull #endif /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x52 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -74,18 +74,18 @@ */ /* Set the local bus clock 1/8 of platform clock */ -#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 +#define CFG_SYS_LBC_LCRR LCRR_CLKDIV_8 /* * This board doesn't have a promjet connector. * However, it uses commone corenet board LAW and TLB. * It is necessary to use the same start address with proper offset. */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CFG_SYS_FLASH_BASE 0xe0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#define CFG_SYS_FLASH_BASE_PHYS 0xfe0000000ull #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif #define CONFIG_FSL_CPLD @@ -130,28 +130,28 @@ | OR_FCM_EHTR) #endif /* CONFIG_NAND_FSL_ELBC */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000} #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS #endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -159,13 +159,13 @@ */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* I2C */ @@ -244,52 +244,52 @@ #define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull /* Qman/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull #else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE #endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 +#define CFG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf4200000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull +#define CFG_SYS_QMAN_MEM_PHYS 0xff4200000ull #else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE #endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 -#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 -#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 -#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 +#define CFG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 +#define CFG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 +#define CFG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 +#define CFG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 +#define CFG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 -#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f +#define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c +#define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d +#define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e +#define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 +#define CFG_SYS_FM1_10GEC1_PHY_ADDR 0 -#define CONFIG_SYS_TBIPA_VALUE 8 +#define CFG_SYS_TBIPA_VALUE 8 #endif #ifdef CONFIG_MMC @@ -305,7 +305,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ /* * Environment Configuration diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 417b9ae7b24..bad34d9771e 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -12,7 +12,7 @@ /* * NS16550 Configuration */ -#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK #define CFG_SYS_NS16550_COM1 KW_UART0_BASE /* @@ -32,7 +32,7 @@ * U-Boot bootcode configuration */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ /* size in bytes reserved for initial data */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 87b68227a0d..9a9663b34ba 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -12,7 +12,7 @@ /* * NS16550 Configuration */ -#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK #define CFG_SYS_NS16550_COM1 KW_UART0_BASE /* @@ -37,7 +37,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ /* size in bytes reserved for initial data */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index b567b63980e..b5fb0a9b529 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -29,18 +29,18 @@ #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CFG_SYS_MMC_U_BOOT_START (0x30000000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -93,7 +93,7 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -101,20 +101,20 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull #endif /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #if defined(CONFIG_TARGET_T1024RDB) #define SPD_EEPROM_ADDRESS 0x51 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -125,15 +125,15 @@ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE 0xe8000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -160,30 +160,30 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} #ifdef CONFIG_TARGET_T1024RDB /* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR2_EXT (0xf) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 +#define CFG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR2 0x0 /* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 +#define CFG_SYS_CS2_FTIM3 0x0 #endif /* NAND Flash on IFC */ @@ -235,72 +235,72 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#define CFG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS #endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* I2C */ @@ -315,7 +315,7 @@ */ #define RTC #define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* * eSPI - Enhanced SPI @@ -363,36 +363,37 @@ /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull #else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE #endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull #else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE #endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 + #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN @@ -421,7 +422,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 37dfe32e21b..bee4b704a24 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -36,18 +36,18 @@ #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CFG_SYS_MMC_U_BOOT_START (0x30000000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif @@ -63,7 +63,7 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -71,24 +71,24 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 /* - * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence - * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address - * (CONFIG_SYS_INIT_L3_VADDR) will be different. + * For Secure Boot CFG_SYS_INIT_L3_ADDR will be redefined and hence + * Physical address (CFG_SYS_INIT_L3_ADDR) and virtual address + * (CFG_SYS_INIT_L3_VADDR) will be different. */ -#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_VADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x51 @@ -97,11 +97,11 @@ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #define CFG_SYS_NOR_CSPR_EXT (0xf) -#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -128,7 +128,7 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} /* CPLD on IFC */ #define CPLD_LBMAP_MASK 0x3F @@ -157,25 +157,25 @@ #define CPLD_INT_MASK_TDMR2 0x01 #endif -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR2_EXT (0xf) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 +#define CFG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR2 0x0 /* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 +#define CFG_SYS_CS2_FTIM3 0x0 /* NAND Flash on IFC */ #define CFG_SYS_NAND_BASE 0xff800000 @@ -213,55 +213,55 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -269,13 +269,13 @@ */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 @@ -289,7 +289,7 @@ */ #define RTC #define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /*DVI encoder*/ #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 @@ -344,58 +344,58 @@ /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_FMAN_ENET #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#define CFG_SYS_SGMII1_PHY_ADDR 0x03 #elif defined(CONFIG_TARGET_T1040D4RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 +#define CFG_SYS_SGMII1_PHY_ADDR 0x01 #elif defined(CONFIG_TARGET_T1042D4RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 -#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 -#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 +#define CFG_SYS_SGMII1_PHY_ADDR 0x02 +#define CFG_SYS_SGMII2_PHY_ADDR 0x03 +#define CFG_SYS_SGMII3_PHY_ADDR 0x01 #endif #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 +#define CFG_SYS_RGMII1_PHY_ADDR 0x04 +#define CFG_SYS_RGMII2_PHY_ADDR 0x05 #else -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 +#define CFG_SYS_RGMII1_PHY_ADDR 0x01 +#define CFG_SYS_RGMII2_PHY_ADDR 0x02 #endif /* Enable VSC9953 L2 Switch driver on T1040 SoC */ #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) #define CONFIG_VSC9953 #ifdef CONFIG_TARGET_T1040RDB -#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 -#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 +#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 +#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 #else -#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 -#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c +#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 +#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c #endif #endif #endif @@ -409,7 +409,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Dynamic MTD Partition support with mtdparts diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 798822e5031..be8c30db26a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -31,18 +31,18 @@ #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CFG_SYS_MMC_U_BOOT_START (0x00200000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -69,18 +69,18 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -90,16 +90,16 @@ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_FLASH_BASE 0xe0000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR_EXT (0xf) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -121,8 +121,8 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CFG_SYS_FLASH_BASE_PHYS} #define QIXIS_BASE 0xffdf0000 #define QIXIS_LBMAP_SWITCH 6 @@ -141,23 +141,23 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ +#define CFG_SYS_CSPR3_EXT (0xf) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 /* NAND Flash on IFC */ #define CFG_SYS_NAND_BASE 0xff800000 @@ -195,81 +195,81 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Serial Port */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* * I2C @@ -360,28 +360,28 @@ /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 18 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 18 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 18 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 18 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN @@ -418,7 +418,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index ea366b671c0..795873f4233 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -31,18 +31,18 @@ #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CFG_SYS_MMC_U_BOOT_START (0x00200000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -69,18 +69,18 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -90,10 +90,10 @@ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -116,29 +116,29 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS } /* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR2_EXT (0xf) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 +#define CFG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR2 0x0 /* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 +#define CFG_SYS_CS2_FTIM3 0x0 /* NAND Flash on IFC */ #define CFG_SYS_NAND_BASE 0xff800000 @@ -176,65 +176,65 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Serial Port */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* * I2C @@ -319,28 +319,28 @@ /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 18 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 18 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 18 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 18 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN @@ -384,7 +384,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index cc86c9d4a51..ffd56454939 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -24,10 +24,10 @@ #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST 0x00200000 +#define CFG_SYS_MMC_U_BOOT_START 0x00200000 +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif @@ -51,39 +51,39 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE 0xe0000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -91,13 +91,13 @@ */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* I2C */ @@ -135,7 +135,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration @@ -159,14 +159,14 @@ /* * IFC Definitions */ -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR_EXT (0xf) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -188,8 +188,8 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CFG_SYS_FLASH_BASE_PHYS} /* NAND Flash on IFC */ #define CFG_SYS_NAND_BASE 0xff800000 @@ -227,71 +227,71 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 /* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR3_EXT (0xf) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 0x0 /* CPLD Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 /* I2C */ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ @@ -318,28 +318,28 @@ /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 50 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 50 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 50 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 50 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 25d9c96e164..69b8b048ce3 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -205,8 +205,8 @@ * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB) */ #if defined(CONFIG_NOR) -#define CONFIG_SYS_FLASH_BASE (0x08000000) -#define CONFIG_SYS_FLASH_SIZE 0x01000000 +#define CFG_SYS_FLASH_BASE (0x08000000) +#define CFG_SYS_FLASH_SIZE 0x01000000 #endif /* NOR support */ #endif /* ! __CONFIG_AM335X_EVM_H */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index a9a4c8d17fc..c57a0ddc21d 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -89,7 +89,7 @@ /* on one chip */ #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CFG_SYS_FLASH_BASE NAND_BASE #endif #endif /* __CONFIG_H */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 4ff8528cf8a..bcdff2e98ac 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -9,7 +9,7 @@ #define __CONFIG_AM43XX_EVM_H #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include @@ -25,7 +25,7 @@ /* SPL defines. */ /* Enabling L2 Cache */ -#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CFG_SYS_PL310_BASE 0x48242000 /* * When building U-Boot such that there is no previous loader diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 84555f3b13d..340a8ce6dc8 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -53,9 +53,9 @@ * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) * 0x9E0000 - 0x2000000 : USERLAND */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 +#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000 +#define CFG_SYS_SPI_ARGS_OFFS 0x140000 +#define CFG_SYS_SPI_ARGS_SIZE 0x80000 /* SPI SPL */ diff --git a/include/configs/amcore.h b/include/configs/amcore.h index eba78d3894c..ee0be972d24 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -10,7 +10,7 @@ #define CONFIG_HOSTNAME "AMCORE" -#define CONFIG_SYS_UART_PORT 0 +#define CFG_SYS_UART_PORT 0 #define CONFIG_EXTRA_ENV_SETTINGS \ "upgrade_uboot=loady; " \ @@ -24,21 +24,21 @@ "erase 0xfff00000 0xffffffff; " \ "cp.b 0x20000 0xfff00000 ${filesize}\0" -#define CONFIG_SYS_CLK 45000000 -#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) +#define CFG_SYS_CLK 45000000 +#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 2) /* Register Base Addrs */ -#define CONFIG_SYS_MBAR 0x10000000 +#define CFG_SYS_MBAR 0x10000000 /* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 /* size of internal SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 0x1000000 -#define CONFIG_SYS_FLASH_BASE 0xffc00000 +#define CFG_SYS_FLASH_BASE 0xffc00000 /* amcore design has flash data bytes wired swapped */ -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA /* reserve 128-4KB */ #define LDS_BOARD_TEXT \ @@ -46,7 +46,7 @@ env/embedded.o(.text*); /* memory map space for linux boot data */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* * Cache Configuration @@ -56,25 +56,25 @@ * sdram - single region - no masks */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ CF_ACR_EN) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ CF_CACR_EC) /* CS0 - AMD Flash, address 0xffc00000 */ -#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) +#define CFG_SYS_CS0_BASE (CFG_SYS_FLASH_BASE>>16) /* 4MB, AA=0,V=1 C/I BIT for errata */ -#define CONFIG_SYS_CS0_MASK 0x003f0001 +#define CFG_SYS_CS0_MASK 0x003f0001 /* WS=10, AA=1, PS=16bit (10) */ -#define CONFIG_SYS_CS0_CTRL 0x1980 +#define CFG_SYS_CS0_CTRL 0x1980 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ -#define CONFIG_SYS_CS1_BASE 0x3000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x0100 +#define CFG_SYS_CS1_BASE 0x3000 +#define CFG_SYS_CS1_MASK 0x00070001 +#define CFG_SYS_CS1_CTRL 0x0100 #endif /* __AMCORE_CONFIG_H */ diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 63c7dfc1feb..9c6f76383de 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -8,8 +8,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Miscellaneous configurable options */ diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 865aad2a3f9..034cd7a7cdf 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -8,8 +8,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x2000 /* * Serial Port diff --git a/include/configs/ap152.h b/include/configs/ap152.h index 0464a69e823..c56b35150a5 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -8,8 +8,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x2000 /* * Serial Port diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 356d4c35ee2..c9375b4d162 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -107,7 +107,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __CONFIG_H */ diff --git a/include/configs/arbel.h b/include/configs/arbel.h index ed32e772f8e..60758b0ca02 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -7,9 +7,9 @@ #define __CONFIG_ARBEL_H #define CFG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_BOOTMAPSZ (20 << 20) -#define CONFIG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_BOOTMAPSZ (20 << 20) +#define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Default environemnt variables */ #define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 90cf4705f4f..c1eec5d06cc 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -20,7 +20,7 @@ #endif /* Framebuffer */ -#define CONFIG_SYS_LDB_CLOCK 28341000 +#define CFG_SYS_LDB_CLOCK 28341000 #include "mx6_common.h" @@ -407,8 +407,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h index cbd0d6cea01..bb1bd50838a 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h @@ -17,11 +17,11 @@ #define CFG_SYS_SDRAM_BASE ASPEED_DRAM_BASE #ifdef CONFIG_PRE_CON_BUF_SZ -#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ) -#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ) +#define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ) +#define CFG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ) #else -#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE) -#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE) +#define CFG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE) #endif /* diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index b142ea3c335..f5922fc416e 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -55,19 +55,19 @@ * interface etc. */ -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 3) #define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ /* * Define baudrate for UART1 (console output, tftp, ...) * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud - * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected + * CFG_SYS_BAUDRATE_TABLE defines values that can be selected * in u-boot command interface */ -#define CONFIG_SYS_UART_PORT (2) -#define CONFIG_SYS_UART2_ALT3_GPIO +#define CFG_SYS_UART_PORT (2) +#define CFG_SYS_UART2_ALT3_GPIO /* * Watchdog configuration; Watchdog is disabled for running from RAM @@ -125,7 +125,7 @@ * it needs non-blocking CFI routines. */ -#define CONFIG_SYS_FPGA_WAIT 1000 +#define CFG_SYS_FPGA_WAIT 1000 /* End of user parameters to be customized */ @@ -139,19 +139,19 @@ /* Base register address */ -#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ /* System Conf. Reg. & System Protection Reg. */ -#define CONFIG_SYS_SCR 0x0003; -#define CONFIG_SYS_SPR 0xffff; +#define CFG_SYS_SCR 0x0003; +#define CFG_SYS_SPR 0xffff; /* * Definitions for initial stack pointer and data area (in internal SRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_CTRL 0x221 /* * Start addresses for the final memory configuration @@ -170,23 +170,23 @@ * CS4 - unused * CS5 - unused */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x00ff0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fc0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x00ff0001 +#define CFG_SYS_CS0_CTRL 0x00001fc0 -#define CONFIG_SYS_CS1_BASE 0x01000000 -#define CONFIG_SYS_CS1_MASK 0x00ff0001 -#define CONFIG_SYS_CS1_CTRL 0x00001fc0 +#define CFG_SYS_CS1_BASE 0x01000000 +#define CFG_SYS_CS1_MASK 0x00ff0001 +#define CFG_SYS_CS1_CTRL 0x00001fc0 -#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK 0x00ff0001 -#define CONFIG_SYS_CS2_CTRL 0x0000fec0 +#define CFG_SYS_CS2_BASE 0x20000000 +#define CFG_SYS_CS2_MASK 0x00ff0001 +#define CFG_SYS_CS2_CTRL 0x0000fec0 -#define CONFIG_SYS_CS3_BASE 0x21000000 -#define CONFIG_SYS_CS3_MASK 0x00ff0001 -#define CONFIG_SYS_CS3_CTRL 0x0000fec0 +#define CFG_SYS_CS3_BASE 0x21000000 +#define CFG_SYS_CS3_MASK 0x00ff0001 +#define CFG_SYS_CS3_CTRL 0x0000fec0 -#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CFG_SYS_FLASH_BASE 0x00000000 /* Reserve 256 kB for Monitor */ @@ -195,12 +195,12 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ -#define CONFIG_SYS_FLASH_SIZE 0x2000000 +#define CFG_SYS_FLASH_SIZE 0x2000000 #define LDS_BOARD_TEXT \ . = DEFINED(env_offset) ? env_offset : .; \ @@ -208,15 +208,15 @@ /* Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) #endif /* _CONFIG_ASTRO_MCF5373L_H */ diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 4631acfd664..4aa876a9f79 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -12,7 +12,7 @@ #include /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ #endif diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 0d76f419db5..b9cc7ba974d 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -24,8 +24,8 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ /* * SDRAM: 1 bank, min 32, max 128 MB @@ -34,11 +34,11 @@ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) #ifdef CONFIG_AT91SAM9XE -# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM #else -# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 #endif /* NAND flash */ @@ -51,6 +51,6 @@ #endif /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ #endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index dcc1cca4791..56247e390bf 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -11,16 +11,16 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #include /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 #define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -42,6 +42,6 @@ #define CONFIG_DM9000_NO_SROM /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ #endif diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index aefa9fc60c4..afdb74785f8 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -19,20 +19,20 @@ #include /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* SDRAM */ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NOR flash, if populated */ #ifdef CONFIG_SYS_USE_NORFLASH #define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 /* Address and size of Primary Environment Sector */ @@ -50,9 +50,9 @@ #define MASTER_PLL_OUT 3 /* clocks */ -#define CONFIG_SYS_MOR_VAL \ +#define CFG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) -#define CONFIG_SYS_PLLAR_VAL \ +#define CFG_SYS_PLLAR_VAL \ (AT91_PMC_PLLAR_29 | \ AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ AT91_PMC_PLLXR_PLLCOUNT(63) | \ @@ -60,31 +60,31 @@ AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +#define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +#define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBICSA_VAL \ +#define CFG_SYS_MATRIX_EBICSA_VAL \ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 0 +#define CFG_SYS_SDRC_MR_VAL1 0 /* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +#define CFG_SYS_SDRC_TR_VAL1 0x13C /* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ +#define CFG_SYS_SDRC_CR_VAL \ (AT91_SDRAMC_NC_9 | \ AT91_SDRAMC_NR_13 | \ AT91_SDRAMC_NB_4 | \ @@ -98,10 +98,10 @@ (1 << 28)) /* Exit Self Refresh to Active Delay */ /* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE #define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH #define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ @@ -110,35 +110,35 @@ #define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR #define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL #define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ #define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ +#define CFG_SYS_SMC0_SETUP0_VAL \ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ +#define CFG_SYS_SMC0_PULSE0_VAL \ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ +#define CFG_SYS_SMC0_CYCLE0_VAL \ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ +#define CFG_SYS_SMC0_MODE0_VAL \ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ AT91_SMC_MODE_DBW_16 | \ AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ +#define CFG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ AT91_RSTC_MR_URSTEN | \ AT91_RSTC_MR_ERSTL(15)) /* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ +#define CFG_SYS_WDTC_WDMR_VAL \ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ AT91_WDT_MR_WDV(0xfff) | \ AT91_WDT_MR_WDDIS | \ @@ -160,6 +160,6 @@ #endif /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ #endif diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 08cfee1a4e1..2ceb8067d58 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -11,8 +11,8 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x70000000 @@ -41,9 +41,9 @@ 56, 57, 58, 59, 60, 61, 62, 63, } #endif -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 76f87c16192..0f9e2cfb582 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -10,8 +10,8 @@ #define __AT91SAM9N12_CONFIG_H_ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ /* Misc CPU related */ #define CFG_SYS_SDRAM_BASE 0x20000000 @@ -35,9 +35,9 @@ /* SPL */ -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20953f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20953f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index e1111b6dd38..cad00f647b6 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -13,15 +13,15 @@ #include /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index eb1d1ad60d1..509c458e5fa 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -9,8 +9,8 @@ #define __CONFIG_H__ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ /* general purpose I/O */ @@ -38,9 +38,9 @@ /* SPL */ -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index 83ac87b10a5..03e04e6e680 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -39,15 +39,15 @@ /* support JEDEC */ #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } /* max number of memory banks */ /* * There are 4 banks supported for this Controller, * but we have only 1 bank connected to flash on board */ -#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} +#define CFG_SYS_FLASH_BANKS_SIZES {0x4000000} /* max number of sectors on one chip */ #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) @@ -63,7 +63,7 @@ */ /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Increase max gunzip size */ /* Support autoboot from RAM (kernel image is loaded via debug port) */ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 6d82712186d..04dc50b1cb2 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -19,8 +19,8 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_512M /* diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h index cba109b74a9..43edc91b101 100644 --- a/include/configs/bcm7260.h +++ b/include/configs/bcm7260.h @@ -12,7 +12,7 @@ #define CFG_SYS_NS16550_COM1 0xf040c000 -#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000 +#define CFG_SYS_INIT_RAM_ADDR 0x10200000 #include "bcmstb.h" diff --git a/include/configs/bcm7445.h b/include/configs/bcm7445.h index a07f1b7ad0f..114337294e0 100644 --- a/include/configs/bcm7445.h +++ b/include/configs/bcm7445.h @@ -12,7 +12,7 @@ #define CFG_SYS_NS16550_COM1 0xf040ab00 -#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000 +#define CFG_SYS_INIT_RAM_ADDR 0x80200000 #include "bcmstb.h" diff --git a/include/configs/bcm963138.h b/include/configs/bcm963138.h index f1b68ba6733..c61acf6b86b 100644 --- a/include/configs/bcm963138.h +++ b/include/configs/bcm963138.h @@ -7,6 +7,6 @@ #define __BCM963138_H #define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_HZ_CLOCK 500000000 +#define CFG_SYS_HZ_CLOCK 500000000 #endif diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 9769a714092..57360b60ca9 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -82,7 +82,7 @@ extern phys_addr_t prior_stage_fdt_address; * initramfs images, in which case this limitation is eliminated. */ #define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 +#define CFG_SYS_INIT_RAM_SIZE 0x100000 /* * CONFIG_SYS_LOAD_ADDR - 1 MiB. @@ -102,7 +102,7 @@ extern phys_addr_t prior_stage_fdt_address; /* * Serial console configuration. */ -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} /* diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index a075a5b2f32..0842a4a8f54 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -200,7 +200,7 @@ #define PHYS_SDRAM_SIZE (SZ_512M) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __CONFIG_H */ diff --git a/include/configs/blanche.h b/include/configs/blanche.h index 0b1fc91d9e1..cb28ae28dd3 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -26,10 +26,10 @@ #define CONFIG_SH_QSPI_BASE 0xE6B10000 #else #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } -#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) } +#define CFG_SYS_FLASH_BASE 0x00000000 +#define CFG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ +#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) } +#define CFG_SYS_FLASH_BANKS_SIZES { (CFG_SYS_FLASH_SIZE) } #endif /* Board Clock */ diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h index e40f110cac6..0d254cd7f9c 100644 --- a/include/configs/bmips_bcm3380.h +++ b/include/configs/bmips_bcm3380.h @@ -14,7 +14,7 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM3380_H */ diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index 508317f231e..7865b9c17e5 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -14,7 +14,7 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6318_H */ diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index c5bda16d2bc..93426d2661d 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -14,7 +14,7 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM63268_H */ diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index 32397c26e8a..e992fe6a560 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -14,7 +14,7 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6328_H */ diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h index 18c99727a04..224b6977747 100644 --- a/include/configs/bmips_bcm6338.h +++ b/include/configs/bmips_bcm6338.h @@ -14,9 +14,9 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif -#define CONFIG_SYS_FLASH_BASE 0xbfc00000 +#define CFG_SYS_FLASH_BASE 0xbfc00000 #endif /* __CONFIG_BMIPS_BCM6338_H */ diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index f8d7148d497..3211d23049e 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -14,9 +14,9 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif -#define CONFIG_SYS_FLASH_BASE 0xbfc00000 +#define CFG_SYS_FLASH_BASE 0xbfc00000 #endif /* __CONFIG_BMIPS_BCM6348_H */ diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index d564a32ee52..7e2449ca24f 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -14,9 +14,9 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif -#define CONFIG_SYS_FLASH_BASE 0xbe000000 +#define CFG_SYS_FLASH_BASE 0xbe000000 #endif /* __CONFIG_BMIPS_BCM6358_H */ diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index f982a4363db..443ee470107 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -14,7 +14,7 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6362_H */ diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index 11d623c28b2..c550f97b935 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -14,9 +14,9 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif -#define CONFIG_SYS_FLASH_BASE 0xb8000000 +#define CFG_SYS_FLASH_BASE 0xb8000000 #endif /* __CONFIG_BMIPS_BCM6368_H */ diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h index 30965c85bfa..f2129140725 100644 --- a/include/configs/bmips_bcm6838.h +++ b/include/configs/bmips_bcm6838.h @@ -14,7 +14,7 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6838_H */ diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index 7e358a6314b..3cdd0e47eae 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -9,7 +9,7 @@ #include /* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } #endif /* __CONFIG_BMIPS_COMMON_H */ diff --git a/include/configs/boston.h b/include/configs/boston.h index 0033a7fb022..14ce8a4c0f3 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -27,7 +27,7 @@ # define CFG_SYS_SDRAM_BASE 0x80000000 #endif -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* * Console diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 78b2000aa2e..d35c7c4a591 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -13,7 +13,7 @@ /* -- i.mx6 specifica -- */ #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#define CFG_SYS_PL310_BASE L2_PL310_BASE #endif /* !CONFIG_SYS_L2CACHE_OFF */ #define CONFIG_MXC_GPT_HCLK @@ -77,8 +77,8 @@ BUR_COMMON_ENV \ /* RAM */ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Ethernet */ #define CONFIG_FEC_FIXED_SPEED _1000BASET diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index f1734aaca7f..3e0b4250788 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -22,7 +22,7 @@ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Timer information */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 6f2b8245b98..6f3396bad4c 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -19,7 +19,7 @@ /* Flat Device Tree Definitions */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CFG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 diff --git a/include/configs/ci20.h b/include/configs/ci20.h index f268dfd0943..3329c24fa68 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -12,7 +12,7 @@ /* Memory configuration */ #define CFG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* NS16550-ish UARTs */ #define CFG_SYS_NS16550_CLK 48000000 diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index eb899c45578..b1f9470d9ca 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -23,8 +23,8 @@ #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 #define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } +#define CFG_SYS_I2C_PCA953X_ADDR 0x20 +#define CFG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } #undef CONFIG_EXTRA_ENV_SETTINGS @@ -83,8 +83,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* SPI Flash support */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 47c4aacc436..d5c03957975 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -22,8 +22,8 @@ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Serial console */ #define CONFIG_MXC_UART_BASE UART4_BASE @@ -139,7 +139,7 @@ #define CONFIG_MXC_USB_FLAGS 0 /* Boot */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* misc */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 8f058213e9e..8ad1cfb5ded 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -9,7 +9,7 @@ #define __CONFIG_CM_T43_H #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include @@ -32,7 +32,7 @@ #define CONFIG_POWER_TPS65218 /* Enabling L2 Cache */ -#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CFG_SYS_PL310_BASE 0x48242000 /* * Since SPL did pll and ddr initialization for us, diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 65b9074cd9c..01828ea2011 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -29,18 +29,18 @@ * --- */ -#define CONFIG_SYS_CLK 66000000 +#define CFG_SYS_CLK 66000000 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ /* --- * Define baudrate for UART1 (console output, tftp, ...) * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud - * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command + * CFG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command * interface * --- */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) /* --- * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change @@ -133,21 +133,21 @@ enter a valid image address in flash */ * --- */ -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ /* --- * System Conf. Reg. & System Protection Reg. * --- */ -#define CONFIG_SYS_SCR 0x0003 -#define CONFIG_SYS_SPR 0xffff +#define CFG_SYS_SCR 0x0003 +#define CFG_SYS_SPR 0xffff /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in internal SRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -168,28 +168,28 @@ enter a valid image address in flash */ *----------------------------------------------------------------------- */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 +#define CFG_SYS_FLASH_BASE 0xffe00000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -209,15 +209,15 @@ enter a valid image address in flash */ /*----------------------------------------------------------------------- * Port configuration (GPIO) */ -#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external +#define CFG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external GPIO*/ -#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs +#define CFG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs (1^=output, 0^=input) */ -#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ -#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART +#define CFG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ +#define CFG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART configuration */ -#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ -#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */ -#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */ +#define CFG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ +#define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */ +#define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */ #endif /* _CONFIG_COBRA5272_H */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index ca8445a3d05..12dc946fc78 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -117,8 +117,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND /* NAND stuff */ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 14278e9ca4f..c6a79debd6b 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -101,7 +101,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index c08095561d8..32a79b02554 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -161,8 +161,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND /* NAND stuff */ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 11283071397..fa778ec9e2b 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -86,8 +86,8 @@ #define PHYS_SDRAM_SIZE (256 * SZ_1M) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* USB Host Support */ diff --git a/include/configs/corvus.h b/include/configs/corvus.h index c7a3e47437b..8a61086ecc1 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -24,8 +24,8 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* serial console */ #define CONFIG_USART_BASE ATMEL_BASE_DBGU @@ -63,10 +63,10 @@ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } -#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_MASTER_CLOCK 132096000 #define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index e2e1cfedbde..578277fc75c 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -17,13 +17,13 @@ /* * SoC Configuration */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CFG_SYS_EXCEPTION_VECTORS_HIGH +#define CFG_SYS_OSCIN_FREQ 24000000 +#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) +#define CFG_SYS_DV_NOR_BOOT_CFG (0x11) #endif /* @@ -36,7 +36,7 @@ /* memtest will be run on 16MB */ -#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ +#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \ DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ DAVINCI_SYSCFG_SUSPSRC_UART2 | \ @@ -47,17 +47,17 @@ * PLL configuration */ -#define CONFIG_SYS_DA850_PLL0_PLLM 24 -#define CONFIG_SYS_DA850_PLL1_PLLM 21 +#define CFG_SYS_DA850_PLL0_PLLM 24 +#define CFG_SYS_DA850_PLL1_PLLM 21 /* * DDR2 memory configuration */ -#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ +#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ DV_DDR_PHY_EXT_STRBEN | \ (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ +#define CFG_SYS_DA850_DDR2_SDBCR ( \ (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ @@ -67,9 +67,9 @@ (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ -#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 +#define CFG_SYS_DA850_DDR2_SDBCR2 0 -#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR ( \ (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ @@ -79,7 +79,7 @@ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ (0 << DV_DDR_SDTMR1_WTR_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ @@ -88,20 +88,20 @@ (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ (0 << DV_DDR_SDTMR2_CKE_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 -#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 +#define CFG_SYS_DA850_DDR2_SDRCR 0x00000494 +#define CFG_SYS_DA850_DDR2_PBBPR 0x30 /* * Serial Driver info */ #define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) +#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) /* * I2C Configuration */ -#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 +#define CFG_SYS_I2C_EXPANDER_ADDR 0x20 /* * Flash & Environment @@ -125,7 +125,7 @@ #endif #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE +#define CFG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ #endif diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index b16f3d48e38..4b31bbf4e11 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -43,8 +43,8 @@ #define PHYS_SDRAM_SIZE SZ_512M #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index c473f3d86eb..66aa6d5c3c4 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -29,8 +29,8 @@ /* * NOR Flash */ -#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE -#define CONFIG_SYS_FLASH_SIZE SZ_4M +#define CFG_SYS_FLASH_BASE EMC_CS0_BASE +#define CFG_SYS_FLASH_SIZE SZ_4M /* * NAND controller diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index ddc436d5019..f9b3d19480e 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -73,8 +73,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment */ diff --git a/include/configs/display5.h b/include/configs/display5.h index 0a7428b02ca..7636d2869a9 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -30,9 +30,9 @@ */ /* Below values are "dummy" - only to avoid build break */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x150000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x10000 +#define CFG_SYS_SPI_KERNEL_OFFS 0x150000 +#define CFG_SYS_SPI_ARGS_OFFS 0x140000 +#define CFG_SYS_SPI_ARGS_SIZE 0x10000 #define CONFIG_MXC_UART_BASE UART5_BASE @@ -285,8 +285,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* ENV config */ #ifdef CONFIG_ENV_IS_IN_SPI_FLASH diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index bb335a0a473..8217712e390 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -63,9 +63,9 @@ * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) * 0x9E0000 - 0x2000000 : USERLAND */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 +#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000 +#define CFG_SYS_SPI_ARGS_OFFS 0x140000 +#define CFG_SYS_SPI_ARGS_SIZE 0x80000 /* SPI SPL */ @@ -87,8 +87,8 @@ /* Parallel NOR Support */ #if defined(CONFIG_NOR) /* NOR: device related configs */ -#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ -#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CFG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ +#define CFG_SYS_FLASH_BASE (0x08000000) /* Reduce SPL size by removing unlikey targets */ #endif /* NOR support */ diff --git a/include/configs/draak.h b/include/configs/draak.h index 8bfba78dc8e..8140bc469c5 100644 --- a/include/configs/draak.h +++ b/include/configs/draak.h @@ -14,7 +14,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* __DRAAK_H */ diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h index 677a4856230..bd88c42a3ba 100644 --- a/include/configs/dragonboard845c.h +++ b/include/configs/dragonboard845c.h @@ -11,7 +11,7 @@ #include #include -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x5000000\0" \ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 80de73d15d5..426155dbdbf 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -12,7 +12,7 @@ * High Level Configuration Options (easy to change) * *----------------------------------------------------------------------*/ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ @@ -27,18 +27,18 @@ * Environment is in the second sector of the first 256k of flash * *----------------------------------------------------------------------*/ -/*#define CONFIG_SYS_DRAM_TEST 1 */ -#undef CONFIG_SYS_DRAM_TEST +/*#define CFG_SYS_DRAM_TEST 1 */ +#undef CFG_SYS_DRAM_TEST /*----------------------------------------------------------------------* * Clock and PLL Configuration * *----------------------------------------------------------------------*/ -#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ +#define CFG_SYS_CLK 80000000 /* 8MHz * 8 */ /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */ -#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ -#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ +#define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ +#define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ /*----------------------------------------------------------------------* * Network * @@ -54,14 +54,14 @@ * You should know what you are doing if you make changes here. *-----------------------------------------------------------------------*/ -#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) *-----------------------------------------------------------------------*/ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -79,34 +79,34 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 -#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE +#define CFG_SYS_INT_FLASH_BASE 0xF0000000 +#define CFG_SYS_INT_FLASH_ENABLE 0x21 -#define CONFIG_SYS_FLASH_SIZE 16*1024*1024 +#define CFG_SYS_FLASH_SIZE 16*1024*1024 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DBWE | \ CF_CACR_EUSP) @@ -114,36 +114,36 @@ * Memory bank definitions */ -#define CONFIG_SYS_CS0_BASE 0xFF000000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 +#define CFG_SYS_CS0_BASE 0xFF000000 +#define CFG_SYS_CS0_CTRL 0x00001980 +#define CFG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS2_BASE 0xE0000000 -#define CONFIG_SYS_CS2_CTRL 0x00001980 -#define CONFIG_SYS_CS2_MASK 0x000F0001 +#define CFG_SYS_CS2_BASE 0xE0000000 +#define CFG_SYS_CS2_CTRL 0x00001980 +#define CFG_SYS_CS2_MASK 0x000F0001 -#define CONFIG_SYS_CS3_BASE 0xE0100000 -#define CONFIG_SYS_CS3_CTRL 0x00001980 -#define CONFIG_SYS_CS3_MASK 0x000F0001 +#define CFG_SYS_CS3_BASE 0xE0100000 +#define CFG_SYS_CS3_CTRL 0x00001980 +#define CFG_SYS_CS3_MASK 0x000F0001 /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ -#define CONFIG_SYS_PADDR 0x0000000 -#define CONFIG_SYS_PADAT 0x0000000 +#define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ +#define CFG_SYS_PADDR 0x0000000 +#define CFG_SYS_PADAT 0x0000000 -#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ -#define CONFIG_SYS_PBDDR 0x0000000 -#define CONFIG_SYS_PBDAT 0x0000000 +#define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CFG_SYS_PBDDR 0x0000000 +#define CFG_SYS_PBDAT 0x0000000 -#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ +#define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PASPAR 0x0F0F -#define CONFIG_SYS_PEHLPAR 0xC0 -#define CONFIG_SYS_PUAPAR 0x0F -#define CONFIG_SYS_DDRUA 0x05 -#define CONFIG_SYS_PJPAR 0xFF +#define CFG_SYS_PASPAR 0x0F0F +#define CFG_SYS_PEHLPAR 0xC0 +#define CFG_SYS_PUAPAR 0x0F +#define CFG_SYS_DDRUA 0x05 +#define CFG_SYS_PJPAR 0xFF /*----------------------------------------------------------------------- * I2C diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index 597efd6745c..d1882a9646b 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -16,7 +16,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* __EBISU_H */ diff --git a/include/configs/edison.h b/include/configs/edison.h index b05141ad645..455a889b64c 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -10,6 +10,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_STACK_SIZE (32 * 1024) +#define CFG_SYS_STACK_SIZE (32 * 1024) #endif diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index d24bc56f34a..141f9913e63 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -51,8 +51,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index e39bb94314f..29b7748e786 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -28,8 +28,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 6cae663cb8a..6647148c96f 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -16,7 +16,7 @@ /* NAND specific changes for etamin due to different page size */ #undef CFG_SYS_NAND_ECCPOS -#define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */ +#define CFG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */ #define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 97a8ffb4f61..52eb0be6761 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -18,19 +18,19 @@ /* CPU information */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ /* 32kB internal SRAM */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */ -#define CONFIG_SYS_INIT_RAM_SIZE (32 << 10) +#define CFG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */ +#define CFG_SYS_INIT_RAM_SIZE (32 << 10) /* 128MB SDRAM in 1 bank */ #define CFG_SYS_SDRAM_BASE 0x20000000 #define CFG_SYS_SDRAM_SIZE (128 << 20) /* 512kB on-chip NOR flash */ -# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ +# define CFG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ /* bootstrap + u-boot + env + linux in dataflash on CS0 */ @@ -53,16 +53,16 @@ /* MMC */ #ifdef CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 +#define CFG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 #endif /* RTC */ #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#define CFG_SYS_I2C_RTC_ADDR 0x51 #endif /* I2C */ -#define CONFIG_SYS_MAX_I2C_BUS 1 +#define CFG_SYS_MAX_I2C_BUS 1 #define I2C_SOFT_DECLARATIONS diff --git a/include/configs/evb_ast2500.h b/include/configs/evb_ast2500.h index cd6cb062eca..bec1660cf48 100644 --- a/include/configs/evb_ast2500.h +++ b/include/configs/evb_ast2500.h @@ -11,7 +11,7 @@ #include -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* Misc */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h index ecd05fe15ce..c9c988b9374 100644 --- a/include/configs/evb_ast2600.h +++ b/include/configs/evb_ast2600.h @@ -8,7 +8,7 @@ #include -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* Misc */ #define STR_HELPER(s) #s diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index a94f5a15f0d..c9e0c13172c 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -15,7 +15,7 @@ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" -#define CONFIG_SYS_SPI_BASE 0x12D30000 +#define CFG_SYS_SPI_BASE 0x12D30000 #define FLASH_SIZE (4 << 20) #define CONFIG_SPI_BOOTING diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h index 68c36dc2fd9..8672b9e9527 100644 --- a/include/configs/exynos78x0-common.h +++ b/include/configs/exynos78x0-common.h @@ -18,7 +18,7 @@ #define CPU_RELEASE_ADDR secondary_boot_addr -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600} #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index f5353ec79a1..89e531649a6 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -14,8 +14,8 @@ #endif /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 @@ -32,10 +32,10 @@ /* SPL */ -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #define CFG_SYS_NAND_U_BOOT_SIZE 0xa0000 #define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index a7557144402..0ba4efe67ac 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -9,14 +9,14 @@ /* RAM */ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) @@ -25,7 +25,7 @@ #endif /* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 } /* RAM */ diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 6cdfe8c4c3c..36dcee87c5f 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -14,7 +14,7 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ /* TODO: Check: Can this be unified with CFG_SYS_SDRAM_BASE? */ -#define CONFIG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE /* * Memory test @@ -28,16 +28,16 @@ /* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ /* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ +#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} /* @@ -49,7 +49,7 @@ * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Environment Configuration diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 85ceaf8ccb1..97fe76cfa8e 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -38,8 +38,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Command definition */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 1dba2e92fb9..cbaf03c2a22 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -92,11 +92,11 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index fe00272a1bd..b855bbc25fb 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -54,8 +54,8 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* * MTD Command for mtdparts diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 0d281a3379a..4aef0b4abd1 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) +#define CFG_SYS_BOOTMAPSZ (16 << 20) #define CONFIG_PL011_CLOCK 150000000 diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 775f166f1d3..c5ef2f99b0f 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -26,7 +26,7 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0xf6801000 diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index 914c3ad9ef0..fad1f980481 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -18,7 +18,7 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0xe82b1000 diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index fcb2dec54ec..59ea8960071 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -21,8 +21,8 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_1G /* diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 0ae935208ca..fbfcded4712 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -20,8 +20,8 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_1G /* diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 594aa4f75e7..b0abd548826 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -80,7 +80,7 @@ /* CS2 Base address */ #define PHYS_FLASH_1 0xc0000000 /* Flash Base for U-Boot */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 /* Address and size of Redundant Environment Sector */ /* diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index d4e2583ee8a..1f30798550c 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -110,8 +110,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* UART */ #ifdef CONFIG_MXC_UART diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 1b08c5e9a7e..4e23f1a2dc5 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -106,8 +106,8 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index a074df5829b..402f83c18ea 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -56,7 +56,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __IMX6DL_MAMOJ_CONFIG_H */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 855af29ec96..99da081cdae 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -86,8 +86,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* SPL */ #ifdef CONFIG_SPL diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index 0a688afe6cd..2d9d3c34b0d 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -64,8 +64,8 @@ #define PHYS_SDRAM_SIZE SZ_128M #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index e5118f11580..76771fd66ce 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -70,8 +70,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* MMC Config*/ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index e62f9c5462b..c228cf7f37b 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -11,7 +11,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -123,8 +123,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 143da001104..03325e6c3a7 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -71,8 +71,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index c7669305f59..80321cf2d8d 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -18,8 +18,8 @@ #endif /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 9937071874f..8a694c88a53 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -15,10 +15,10 @@ #define UBOOT_ITB_OFFSET_FSPI \ (UBOOT_ITB_OFFSET + FSPI_CONF_BLOCK_SIZE) #ifdef CONFIG_FSPI_CONF_HEADER -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + UBOOT_ITB_OFFSET_FSPI) #else -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #endif @@ -53,8 +53,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index cd47d842ffc..41ab9307793 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -38,8 +38,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 58e165c35a7..28ce834769c 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -29,8 +29,8 @@ "splblk=0x42\0" \ BOOTENV -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index f532c1052f5..85fd5e2371f 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) /* Initial environment variables */ @@ -75,8 +75,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index 415248eadfc..204fc4b3164 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #define MEM_LAYOUT_ENV_SETTINGS \ @@ -23,8 +23,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 8857bc7c598..024b86c7f1d 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #define BOOT_TARGET_DEVICES(func) \ @@ -45,8 +45,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index 628bb5813ff..4633843d1bb 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #define BOOT_TARGET_DEVICES(func) \ @@ -43,8 +43,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index a169be35a49..a585cbf87e4 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) /* Enable Distro Boot */ @@ -23,8 +23,8 @@ "splblk=0x40\0" \ BOOTENV -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index 62bcef5eecd..5443022b04c 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -11,8 +11,8 @@ #include /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index d394762e3bb..738677ff37c 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ @@ -50,8 +50,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 /* Totally 2GB DDR */ diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index 3e995c97217..d67bad8971d 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -11,7 +11,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ @@ -52,8 +52,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 /* Totally 2GB DDR */ #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 1943a24b79d..58f7dc6518c 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -12,7 +12,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) /* GUIDs for capsule updatable firmware images */ #define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \ @@ -131,8 +131,8 @@ "fi;\0" /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 /* Totally 6GB or 4G DDR */ diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index 7d360583c41..e79aa570753 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) /* Enable Distro Boot */ @@ -23,8 +23,8 @@ "splblk=0x40\0" \ BOOTENV -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 271376cb9fc..4df98e3f373 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -46,8 +46,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 672a9fa7a34..aa29e7884f9 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -52,8 +52,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index dd354b0265d..3b4cd656223 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -84,8 +84,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index fe27ac36a3b..2e2e5ed43cd 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CFG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 592df2795b1..d313bdc2a44 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD #define CONFIG_MALLOC_F_ADDR 0x22040000 @@ -50,8 +50,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x80000000 diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 077a4d843dc..895c50f6025 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -124,8 +124,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 #define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h index a2c004880a7..e180387c687 100644 --- a/include/configs/imxrt1020-evk.h +++ b/include/configs/imxrt1020-evk.h @@ -22,6 +22,6 @@ * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_UBOOT_START 0x800023FD +#define CFG_SYS_UBOOT_START 0x800023FD #endif /* __IMXRT1020_EVK_H */ diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index d1a7dab37c5..84228676c7f 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -29,6 +29,6 @@ * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_UBOOT_START 0x800023FD +#define CFG_SYS_UBOOT_START 0x800023FD #endif /* __IMXRT1050_EVK_H */ diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h index 2459fe24e24..f83429082ac 100644 --- a/include/configs/imxrt1170-evk.h +++ b/include/configs/imxrt1170-evk.h @@ -23,7 +23,7 @@ #define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \ DMAMEM_SZ_ALL) /* For SPL */ -#define CONFIG_SYS_UBOOT_START 0x202403FD +#define CFG_SYS_UBOOT_START 0x202403FD /* For SPL ends */ #endif /* __IMXRT1170_EVK_H */ diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 8d0458d1d63..7a55c6aeefc 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -6,7 +6,7 @@ * Common ARM Integrator configuration settings */ -#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ +#define CFG_SYS_TIMERBASE 0x13000100 /* Timer1 */ /* * The ARM boot monitor initializes the board. @@ -41,6 +41,6 @@ * - SIB block * - U-Boot environment */ -#define CONFIG_SYS_FLASH_BASE 0x24000000 +#define CFG_SYS_FLASH_BASE 0x24000000 /* Timeout values in ticks */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index c8457d97161..6bee098d6a8 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -17,10 +17,10 @@ #include "integrator-common.h" /* Integrator/AP-specific configuration */ -#define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ +#define CFG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ /* Flash settings */ -#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ +#define CFG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ /*----------------------------------------------------------------------- * PCI definitions diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index bf09510d02f..25bb41ebc46 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -17,7 +17,7 @@ #include "integrator-common.h" /* Integrator CP-specific configuration */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ #define CONFIG_SERVERIP 192.168.1.100 #define CONFIG_IPADDR 192.168.1.104 diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index 2a0b0c7163a..e66f994a375 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -18,14 +18,14 @@ /* DDR Configuration */ #define CFG_SYS_SDRAM_BASE1 0x880000000 /* FLASH Configuration */ -#define CONFIG_SYS_FLASH_BASE 0x000000000 +#define CFG_SYS_FLASH_BASE 0x000000000 /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_UBOOT_BASE 0x50280000 +#define CFG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else -#define CONFIG_SYS_UBOOT_BASE 0x50080000 +#define CFG_SYS_UBOOT_BASE 0x50080000 #endif /* HyperFlash related configuration */ diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index e690ef95906..ab204c62b7d 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -21,10 +21,10 @@ /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_UBOOT_BASE 0x50280000 +#define CFG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else -#define CONFIG_SYS_UBOOT_BASE 0x50080000 +#define CFG_SYS_UBOOT_BASE 0x50080000 #endif /* U-Boot general configuration */ diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 35cf27a2eb9..cc5ec219b8d 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -13,7 +13,7 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS #define CONFIG_KM_DEF_ENV_BOOTPARAMS \ diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h index 888bb2981f7..f64c0eee1bb 100644 --- a/include/configs/km/km-mpc832x.h +++ b/include/configs/km/km-mpc832x.h @@ -1,34 +1,34 @@ /* * System IO Config */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS +#define CFG_SYS_SICRL SICRL_IRQ_CKS -#define CONFIG_SYS_DDRCDR (\ +#define CFG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ DDRCDR_NZ_MAXZ | \ DDRCDR_M_ODR) -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ +#define CFG_SYS_DDR_CS0_BNDS 0x0000007f +#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_32_BE | \ SDRAM_CFG_SREN | \ SDRAM_CFG_HSE) -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ +#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CFG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CFG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ CSCONFIG_ODT_WR_CFG | \ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 +#define CFG_SYS_DDR_MODE 0x47860242 +#define CFG_SYS_DDR_MODE2 0x8080c000 -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ +#define CFG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ @@ -37,7 +37,7 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ +#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ (2 << TIMING_CFG1_WRTORD_SHIFT) | \ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ (3 << TIMING_CFG1_WRREC_SHIFT) | \ @@ -46,7 +46,7 @@ (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ (3 << TIMING_CFG1_PRETOACT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ +#define CFG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ @@ -54,7 +54,7 @@ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ (5 << TIMING_CFG2_CPO_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CFG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 +#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CFG_SYS_KMBEC_FPGA_SIZE 128 diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h index fb43fb81bc0..5c9f912383d 100644 --- a/include/configs/km/km-mpc8360.h +++ b/include/configs/km/km-mpc8360.h @@ -1,6 +1,6 @@ /* KMBEC FPGA (PRIO) */ -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 64 +#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CFG_SYS_KMBEC_FPGA_SIZE 64 /* * High Level Configuration Options @@ -9,34 +9,34 @@ /* * System IO Setup */ -#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) +#define CFG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) /** * DDR RAM settings */ -#define CONFIG_SYS_DDR_SDRAM_CFG (\ +#define CFG_SYS_DDR_SDRAM_CFG (\ SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_SREN | \ SDRAM_CFG_HSE) -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (\ +#define CFG_SYS_DDR_CLK_CNTL (\ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL (\ +#define CFG_SYS_DDR_INTERVAL (\ (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CFG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDRCDR (\ +#define CFG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_Q_DRN) -#define CONFIG_SYS_DDR_MODE 0x47860452 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 +#define CFG_SYS_DDR_MODE 0x47860452 +#define CFG_SYS_DDR_MODE2 0x8080c000 -#define CONFIG_SYS_DDR_TIMING_0 (\ +#define CFG_SYS_DDR_TIMING_0 (\ (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ @@ -46,7 +46,7 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ +#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ (2 << TIMING_CFG1_WRTORD_SHIFT) | \ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ (3 << TIMING_CFG1_WRREC_SHIFT) | \ @@ -55,7 +55,7 @@ (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ (3 << TIMING_CFG1_PRETOACT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_2 (\ +#define CFG_SYS_DDR_TIMING_2 (\ (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ @@ -64,11 +64,11 @@ (5 << TIMING_CFG2_CPO_SHIFT) | \ (0 << TIMING_CFG2_ADD_LAT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CFG_SYS_DDR_TIMING_3 0x00000000 /* EEprom support */ /* * PAXE on the local bus CS3 */ -#define CONFIG_SYS_PAXE_BASE 0xA0000000 +#define CFG_SYS_PAXE_BASE 0xA0000000 diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index db1daee1363..e6a3613b7a2 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -9,7 +9,7 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ +#define CFG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #define CFG_83XX_DDR_USES_CS0 @@ -22,15 +22,15 @@ /* * The reserved memory */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 +#define CFG_SYS_FLASH_BASE 0xF0000000 /* Reserve 768 kB for Mon */ /* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ /* * Init Local Bus Memory Controller: * @@ -44,21 +44,21 @@ /* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ +#define CFG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } /* I2C */ #define CFG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ +#define CFG_SYS_I2C_MAX_HOPS 1 +#define CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ {1, {I2C_NULL_HOP} } } #if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_KMETER1 -#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE #endif /* @@ -66,7 +66,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* * Environment diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index b5913ed7000..7307c495c38 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -9,8 +9,8 @@ /* include common defines/options for all Keymile boards */ #include "keymile-common.h" -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \ CONFIG_KM_PHRAM + \ @@ -19,24 +19,24 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x54 /* POST memory regions test */ -#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS) +#define CONFIG_POST (CFG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* * IFC Definitions */ /* NOR Flash Definitions */ -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_TE | \ CSPR_MSEL_NOR | \ @@ -63,18 +63,18 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 /* NAND Flash Definitions */ #define CFG_SYS_NAND_BASE 0x68000000 @@ -110,40 +110,40 @@ FTIM2_NAND_TWHRE(0x3c)) #define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } /* QRIO FPGA Definitions */ -#define CONFIG_SYS_QRIO_BASE 0x70000000 -#define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE +#define CFG_SYS_QRIO_BASE 0x70000000 +#define CFG_SYS_QRIO_BASE_PHYS CFG_SYS_QRIO_BASE -#define CONFIG_SYS_CSPR2_EXT (0x00) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ +#define CFG_SYS_CSPR2_EXT (0x00) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_TE | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \ +#define CFG_SYS_AMASK2 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \ CSOR_GPCM_TRHZ_20 | \ CSOR_GPCM_BCTLD) -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ FTIM0_GPCM_TEADC(0x8) | \ FTIM0_GPCM_TEAHC(0x2)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ FTIM1_GPCM_TRAD(0x6)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x7)) -#define CONFIG_SYS_CS2_FTIM3 0x04000000 +#define CFG_SYS_CS2_FTIM3 0x04000000 /* * Serial Port @@ -155,11 +155,11 @@ */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CFG_SYS_I2C_MAX_HOPS 1 #define CFG_SYS_NUM_I2C_BUSES 3 #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x0 -#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ +#define CFG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ {1, {I2C_NULL_HOP} }, \ } @@ -205,12 +205,12 @@ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +${filesize}\0" \ - "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ - "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ + "erase " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ "cp.b ${load_addr_r} " \ - __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ + __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \ "set_fdthigh=true\0" \ @@ -238,6 +238,6 @@ "ethrotate=no\0" \ "" -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ #endif diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index dbf038cefa0..e152714b116 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -25,10 +25,10 @@ #define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE) /* Application IFC CS4 MRAM */ -#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE +#define CFG_SYS_MRAM_BASE SYS_LAWAPP_BASE #define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS #define SYS_MRAM_CSPR_EXT (0x0f) -#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \ +#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CFG_SYS_MRAM_BASE) | \ CSPR_PORT_SIZE_8 | /* 8 bit */ \ CSPR_MSEL_GPCM | /* msel = gpcm */ \ CSPR_V /* bank is valid */) @@ -44,14 +44,14 @@ FTIM2_GPCM_TCH(0x2) | \ FTIM2_GPCM_TWP(0x8)) #define SYS_MRAM_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT -#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR -#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK -#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR -#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0 -#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1 -#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2 -#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3 +#define CFG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT +#define CFG_SYS_CSPR4 SYS_MRAM_CSPR +#define CFG_SYS_AMASK4 SYS_MRAM_AMASK +#define CFG_SYS_CSOR4 SYS_MRAM_CSOR +#define CFG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0 +#define CFG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1 +#define CFG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2 +#define CFG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3 /* Application IFC CS6: BFTIC */ #define SYS_BFTIC_BASE 0xd0000000 @@ -73,20 +73,20 @@ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) #define SYS_BFTIC_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT -#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR -#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK -#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR -#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0 -#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1 -#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2 -#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3 +#define CFG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT +#define CFG_SYS_CSPR6 SYS_BFTIC_CSPR +#define CFG_SYS_AMASK6 SYS_BFTIC_AMASK +#define CFG_SYS_CSOR6 SYS_BFTIC_CSOR +#define CFG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0 +#define CFG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1 +#define CFG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2 +#define CFG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3 /* Application IFC CS7 PAXE */ -#define CONFIG_SYS_PAXE_BASE 0xd8000000 -#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE) +#define CFG_SYS_PAXE_BASE 0xd8000000 +#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CFG_SYS_PAXE_BASE) #define SYS_PAXE_CSPR_EXT (0x0f) -#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \ +#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CFG_SYS_PAXE_BASE) | \ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ CSPR_MSEL_GPCM | /* MSEL = GPCM */\ CSPR_V) /* valid */ @@ -102,14 +102,14 @@ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) #define SYS_PAXE_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT -#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR -#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK -#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR -#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0 -#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1 -#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2 -#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3 +#define CFG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT +#define CFG_SYS_CSPR7 SYS_PAXE_CSPR +#define CFG_SYS_AMASK7 SYS_PAXE_AMASK +#define CFG_SYS_CSOR7 SYS_PAXE_CSOR +#define CFG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0 +#define CFG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1 +#define CFG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2 +#define CFG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3 /* PRST */ #define KM_BFTIC4_RST 0 @@ -145,25 +145,25 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E /* POST memory regions test */ -#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS +#define CONFIG_POST CFG_SYS_POST_MEM_REGIONS /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x54 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -189,12 +189,12 @@ * IFC Definitions */ /* NOR flash on IFC CS0 */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \ - CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \ + CFG_SYS_FLASH_BASE) #define CFG_SYS_NOR_CSPR_EXT (0x0f) -#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \ CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\ 0x00000010 | /* drive TE high */\ CSPR_MSEL_NOR | /* MSEL = NOR */\ @@ -217,18 +217,18 @@ FTIM2_NOR_TWPH(0x6)) #define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 /* More NOR Flash params */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} /* NAND Flash on IFC CS1*/ #define CFG_SYS_NAND_BASE 0xfa000000 @@ -266,23 +266,23 @@ FTIM2_NAND_TWHRE(0x3c)) #define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 /* More NAND Flash Params */ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } /* QRIO on IFC CS2 */ -#define CONFIG_SYS_QRIO_BASE 0xfb000000 -#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE) +#define CFG_SYS_QRIO_BASE 0xfb000000 +#define CFG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CFG_SYS_QRIO_BASE) #define SYS_QRIO_CSPR_EXT (0x0f) -#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ +#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ 0x00000010 | /* drive TE high */\ CSPR_MSEL_GPCM | /* MSEL = GPCM */\ @@ -300,28 +300,28 @@ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x7)) #define SYS_QRIO_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT -#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR -#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK -#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR -#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3 +#define CFG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT +#define CFG_SYS_CSPR2 SYS_QRIO_CSPR +#define CFG_SYS_AMASK2 SYS_QRIO_AMASK +#define CFG_SYS_CSOR2 SYS_QRIO_CSOR +#define CFG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0 +#define CFG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1 +#define CFG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2 +#define CFG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3 #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Serial Port - controlled on board with jumper J8 @@ -331,7 +331,7 @@ */ #if !defined(CONFIG_DM_SERIAL) #define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR + 0x11C500) #endif #ifndef __ASSEMBLY__ @@ -351,30 +351,30 @@ int get_scl(void); #define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 /* Qman / Bman */ /* RGMII (FM1@DTESC5) is local managemant interface */ -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11 +#define CFG_SYS_RGMII2_PHY_ADDR 0x11 /* * Hardware Watchdog @@ -387,7 +387,7 @@ int get_scl(void); * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration @@ -412,12 +412,12 @@ int get_scl(void); __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +${filesize}\0" \ - "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ - "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ + "erase " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ "cp.b ${load_addr_r} " \ - __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ + __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \ "set_fdthigh=true\0" \ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index b9540298747..2be996aaaf0 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -12,7 +12,7 @@ #define CONFIG_NAND_ECC_BCH #define CONFIG_NAND_KMETER1 #define NAND_MAX_CHIPS 1 -#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ +#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" @@ -26,7 +26,7 @@ /** * KMCOGE5NE has 512 MB RAM */ -#define CONFIG_SYS_DDR_CS0_CONFIG (\ +#define CFG_SYS_DDR_CS0_CONFIG (\ CSCONFIG_EN | \ CSCONFIG_AP | \ CSCONFIG_ODT_WR_ONLY_CURRENT | \ @@ -35,7 +35,7 @@ CSCONFIG_COL_BIT_10) /* enable POST tests */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) +#define CONFIG_POST (CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 4245875e39e..910fc1b2cb2 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -16,7 +16,7 @@ #include "km/km-mpc83xx.h" #include "km/km-mpc8360.h" -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10 | \ CSCONFIG_ODT_WR_ONLY_CURRENT) diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index e2808ec02dc..6fcacdb0c66 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -16,10 +16,10 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* Board and environment settings */ #define CONFIG_MXC_UART_BASE UART4_BASE diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 73b59517621..80a32304606 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -19,8 +19,8 @@ #define PHYS_SDRAM_SIZE (SZ_4G) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 /* Board and environment settings */ #define CONFIG_HOSTNAME "kontron-mx8mm" diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 9b452818c1e..2abcb849a28 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -61,8 +61,8 @@ BOOTENV -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index bbf0761814b..9c3174d0e02 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -12,17 +12,17 @@ /* we don't have secure memory unless we have a BL31 */ #ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT -#undef CONFIG_SYS_MEM_RESERVE_SECURE +#undef CFG_SYS_MEM_RESERVE_SECURE #endif /* DDR */ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL /* early stack pointer */ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index 967de66f3c9..c551585a206 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -68,8 +68,8 @@ #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* environment organization */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index de1fc0bfa4c..136e228682a 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -87,8 +87,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment */ diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 9b70eed46f7..828f9109634 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -31,7 +31,7 @@ #ifdef CONFIG_CMD_I2C /* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ #if defined(CONFIG_NET2BIG_V2) -#define CONFIG_SYS_I2C_G762_ADDR 0x3e +#define CFG_SYS_I2C_G762_ADDR 0x3e #endif #endif /* CONFIG_CMD_I2C */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index bee064c6f38..2664982715f 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -17,10 +17,10 @@ /* * SoC Configuration */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CFG_SYS_EXCEPTION_VECTORS_HIGH +#define CFG_SYS_OSCIN_FREQ 24000000 +#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) /* * Memory Info @@ -38,7 +38,7 @@ */ #define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) +#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) /* * U-Boot general configuration diff --git a/include/configs/librem5.h b/include/configs/librem5.h index 3a2c508ffac..11b3fa6c857 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -79,8 +79,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index b9134508853..f16c7e91221 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -9,14 +9,14 @@ /* RAM */ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) @@ -26,7 +26,7 @@ #endif /* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 } /* RAM */ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index d1ebd99ae14..721da818633 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -88,8 +88,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* FLASH and environment organization */ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 07124370775..7598e54ed2b 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -10,10 +10,10 @@ #include #include -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL /*SPI device */ #define CFG_SYS_FSL_QSPI_BASE 0x40000000 diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 54555b34dd4..e772c019077 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -17,7 +17,7 @@ */ #ifdef CONFIG_FSL_QIXIS -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_BRDCFG_REG 0x04 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x08 @@ -47,7 +47,7 @@ * RTC configuration */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* Voltage monitor on channel 2*/ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 49a77fd6b6b..b058308ecdb 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -7,8 +7,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* * DDR: 800 MHz ( 1600 MT/s data rate ) @@ -41,8 +41,8 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001 -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* * Serial Port @@ -104,7 +104,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_LS102XA_STREAM_ID diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 1f5a80ff085..5494b71e2b2 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -7,8 +7,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE #ifdef CONFIG_NAND_BOOT #define CFG_SYS_NAND_U_BOOT_SIZE (400 << 10) @@ -19,8 +19,8 @@ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -30,16 +30,16 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR1_CSPR_EXT (0x0) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ @@ -61,10 +61,10 @@ #define CFG_SYS_NOR_FTIM3 0 #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ + CFG_SYS_FLASH_BASE_PHYS + 0x8000000} /* * NAND Flash Definitions @@ -111,7 +111,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 0 @@ -131,96 +131,96 @@ #define QIXIS_PWR_CTL2 0x21 #define QIXIS_PWR_CTL2_PCTL 0x2 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* * QIXIS Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ FTIM0_GPCM_TEADC(0xe) | \ FTIM0_GPCM_TEAHC(0xe)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ FTIM2_GPCM_TCH(0xe) | \ FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_FPGA_FTIM3 0x0 #endif #if defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #endif /* @@ -296,7 +296,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_LS102XA_STREAM_ID diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 49546066115..bc9eac700e9 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -6,8 +6,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* XHCI Support - enabled by default */ @@ -56,8 +56,8 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* Serial Port */ #define CFG_SYS_NS16550_CLK get_serial_clock() @@ -141,7 +141,7 @@ "bootm $load_addr#$board\0" /* Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_LS102XA_STREAM_ID diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index d77224934c0..f1ccb5fc084 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -7,8 +7,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE #define DDR_SDRAM_CFG 0x470c0008 #define DDR_CS0_BNDS 0x008000bf @@ -59,18 +59,18 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -94,52 +94,52 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* CPLD */ -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ FTIM0_GPCM_TEADC(0xf) | \ FTIM0_GPCM_TEAHC(0xf)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0xff)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_FPGA_FTIM3 /* * Serial Port @@ -298,7 +298,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_LS102XA_STREAM_ID diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 064c4f069cb..bdd3951e85f 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -13,10 +13,10 @@ /* Link Definitions */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL /* * SMP Definitinos diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 25391151866..228fb122f5f 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -17,7 +17,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 1 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 5 @@ -35,19 +35,19 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) #endif /* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 1 +#define CFG_SYS_RTC_BUS_NUM 1 #define I2C_MUX_CH_RTC 0xB /* Store environment at top of flash */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index e7b2543b730..5c134612576 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -10,7 +10,7 @@ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_RTC_BUS_NUM 0 /* Store environment at top of flash */ @@ -21,7 +21,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 2 #define QIXIS_LBMAP_MASK 0xe0 #define QIXIS_LBMAP_SHIFT 0x5 @@ -39,12 +39,12 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) #endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e940dff9988..b4048744b1e 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -32,10 +32,10 @@ /* Link Definitions */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CPU_RELEASE_ADDR secondary_boot_addr @@ -82,14 +82,14 @@ #if defined(CONFIG_TFABOOT) || \ (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)) /* - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x60000000 for booting */ -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -104,7 +104,7 @@ /* FMan ucode */ #ifndef SPL_NO_FMAN #ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #endif #endif diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 87751f786c8..dab57382edd 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -39,13 +39,13 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR1_CSPR_EXT (0x0) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ @@ -66,10 +66,10 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ + CFG_SYS_FLASH_BASE_PHYS + 0x8000000} -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA /* * NAND Flash Definitions @@ -125,7 +125,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 0 @@ -143,130 +143,130 @@ #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* * QIXIS Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ FTIM0_GPCM_TEADC(0x20) | \ FTIM0_GPCM_TEAHC(0x10)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_FPGA_FTIM3 0x0 #endif #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #endif #endif diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 76251fde57c..12c4853ea96 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -21,7 +21,7 @@ #define CFG_SYS_NOR_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) #define CFG_SYS_NOR_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -41,11 +41,11 @@ FTIM2_NOR_TWPH(0x8) | \ FTIM2_NOR_TWP(0x10)) #define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA /* * NAND Flash Definitions @@ -91,97 +91,97 @@ /* * CPLD */ -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE -#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) -#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ +#define CFG_SYS_CPLD_CSPR_EXT (0x0) +#define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ +#define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ FTIM0_GPCM_TEADC(0xf) | \ FTIM0_GPCM_TEAHC(0xf)) -#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0xff)) -#define CONFIG_SYS_CPLD_FTIM3 0x0 +#define CFG_SYS_CPLD_FTIM3 0x0 /* IFC Timing Params */ #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 - -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 + +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 + +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 - -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 + +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif #endif -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3 /* * Environment diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index ce254d8b3f1..cac30e4679e 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -32,10 +32,10 @@ /* Link Definitions */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CPU_RELEASE_ADDR secondary_boot_addr @@ -68,7 +68,7 @@ /* FMan ucode */ #ifndef SPL_NO_FMAN #ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #endif #endif diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 8402eac4184..58ae0fb0a6c 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -8,7 +8,7 @@ #include "ls1046a_common.h" -#define CONFIG_SYS_UBOOT_BASE 0x40100000 +#define CFG_SYS_UBOOT_BASE 0x40100000 /* * NAND Flash Definitions @@ -48,14 +48,14 @@ #define CONFIG_MTD_NAND_VERIFY_WRITE /* IFC Timing Params */ -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 /* EEPROM */ #define I2C_RETIMER_ADDR 0x18 @@ -67,8 +67,8 @@ /* RTC */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ +#define CFG_SYS_RTC_BUS_NUM 0 /* * Environment diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index d565492f1d1..553ae841cab 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -33,14 +33,14 @@ /* IFC */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) /* - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x60000000 for booting */ -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -58,13 +58,13 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR1_CSPR_EXT (0x0) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ @@ -86,10 +86,10 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ + CFG_SYS_FLASH_BASE_PHYS + 0x8000000} -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA /* * NAND Flash Definitions @@ -145,7 +145,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 0 @@ -163,130 +163,130 @@ #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* * QIXIS Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ FTIM0_GPCM_TEADC(0x20) | \ FTIM0_GPCM_TEAHC(0x10)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_FPGA_FTIM3 0x0 #endif #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #endif #endif diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 0df68915989..f3904e7b3f7 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -16,7 +16,7 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #if defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_UBOOT_BASE 0x40100000 +#define CFG_SYS_UBOOT_BASE 0x40100000 #endif #define CFG_SYS_NAND_BASE 0x7e800000 @@ -55,46 +55,46 @@ /* * CPLD */ -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE -#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) -#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ +#define CFG_SYS_CPLD_CSPR_EXT (0x0) +#define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) +#define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) /* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CPLD_FTIM3 0x0 +#define CFG_SYS_CPLD_FTIM3 0x0 /* IFC Timing Params */ -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 + +#define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3 /* EEPROM */ #define I2C_RETIMER_ADDR 0x18 diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index f8eaee881d0..bacc84f629a 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -30,10 +30,10 @@ #define CFG_SYS_FSL_QSPI_BASE 0x20000000 #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL /* * SMP Definitinos */ @@ -64,18 +64,18 @@ * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) * * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x30000000 for booting */ -#define CONFIG_SYS_FLASH_BASE 0x580000000ULL -#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x580000000ULL +#define CFG_SYS_FLASH_BASE_PHYS 0x80000000 +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 +#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000 +#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 #ifndef __ASSEMBLY__ unsigned long long get_qixis_addr(void); @@ -92,12 +92,12 @@ unsigned long long get_qixis_addr(void); /* MC firmware */ /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 -#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 +#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 +#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 /* * Carve out a DDR region which will not be used by u-boot/Linux @@ -107,7 +107,7 @@ unsigned long long get_qixis_addr(void); */ #if defined(CONFIG_FSL_MC_ENET) -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) +#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) #endif /* Miscellaneous configurable options */ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index b75d4ccf5cf..d84622f3225 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -22,27 +22,27 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR1_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -59,13 +59,13 @@ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000 #ifndef SYS_NO_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ + CFG_SYS_FLASH_BASE + 0x40000000} #endif #endif @@ -101,7 +101,7 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_QMAP_MASK 0xe0 #define QIXIS_QMAP_SHIFT 5 @@ -127,8 +127,8 @@ #define QIXIS_SDID_MASK 0x07 #define QIXIS_ESDHC_NO_ADAPTER 0x7 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) @@ -139,9 +139,9 @@ #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) +#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) #else -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) +#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) #endif /* QIXIS Timing parameters*/ #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ @@ -155,102 +155,102 @@ #define SYS_FPGA_CS_FTIM3 0x0 #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK3 SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 #else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK2 SYS_FPGA_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK3 SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 #endif #endif -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 /* * I2C bus multiplexer @@ -281,7 +281,7 @@ * RTC configuration */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #ifdef CONFIG_FSL_DSPI #if !defined(CONFIG_TFABOOT) && \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 27510adae67..187b3072f02 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -20,17 +20,17 @@ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -44,12 +44,12 @@ FTIM2_NOR_TCH(0x0) | \ FTIM2_NOR_TWP(0x1)) #define CFG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000 #ifndef SYS_NO_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif #endif @@ -85,7 +85,7 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_BRDCFG4_OFFSET 0x54 #define QIXIS_LBMAP_SWITCH 2 #define QIXIS_QMAP_MASK 0xe0 @@ -107,8 +107,8 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) @@ -117,8 +117,8 @@ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) /* QIXIS Timing parameters*/ #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ @@ -132,36 +132,36 @@ #if defined(CONFIG_TFABOOT) || \ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK2 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #endif -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 #define I2C_MUX_CH_VOL_MONITOR 0xA /* Voltage monitor on channel 2*/ @@ -191,7 +191,7 @@ * RTC configuration */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #endif #ifndef SPL_NO_ENV diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 21c097ecbbd..18defd5e5a6 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -17,10 +17,10 @@ /* Link Definitions */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL /* * SMP Definitinos @@ -56,18 +56,18 @@ * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) * * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x30000000 for booting */ -#define CONFIG_SYS_FLASH_BASE 0x580000000ULL -#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x580000000ULL +#define CFG_SYS_FLASH_BASE_PHYS 0x80000000 +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 +#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000 +#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 #ifndef __ASSEMBLY__ unsigned long long get_qixis_addr(void); @@ -84,13 +84,13 @@ unsigned long long get_qixis_addr(void); /* MC firmware */ /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 /* For LS2085A */ -#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 -#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 +#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 +#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 /* * Carve out a DDR region which will not be used by u-boot/Linux @@ -99,7 +99,7 @@ unsigned long long get_qixis_addr(void); * 512MB aligned, so the min size to hide is 512MB. */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) +#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) #endif /* Miscellaneous configurable options */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 7315790f1fe..067587b53c5 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -10,10 +10,10 @@ #include "ls2080a_common.h" #ifdef CONFIG_FSL_QSPI -#define CONFIG_SYS_I2C_IFDR_DIV 0x7e +#define CFG_SYS_I2C_IFDR_DIV 0x7e #endif -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4) #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -25,27 +25,27 @@ #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR1_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -61,13 +61,13 @@ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000 #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ + CFG_SYS_FLASH_BASE + 0x40000000} #endif #define CFG_SYS_NAND_CSPR_EXT (0x0) @@ -119,92 +119,92 @@ #define QIXIS_RCW_SRC_QSPI 0x62 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_CSPR3_EXT (0x0) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_CSPR3_EXT (0x0) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ +#define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) +#define CFG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) /* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 #if defined(CONFIG_SPL) #if defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CFG_SYS_NAND_U_BOOT_SIZE (640 * 1024) #endif #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 /* * I2C @@ -229,7 +229,7 @@ */ #define RTC #define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index daca3be16c5..32a11948723 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -32,17 +32,17 @@ #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -58,13 +58,13 @@ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000 #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ + CFG_SYS_FLASH_BASE + 0x40000000} #endif #define CFG_SYS_NAND_CSPR_EXT (0x0) @@ -113,70 +113,70 @@ #define QIXIS_RCW_SRC_NAND 0x119 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_CSPR3_EXT (0x0) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_CSPR3_EXT (0x0) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ +#define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) +#define CFG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) /* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CFG_SYS_NAND_U_BOOT_SIZE (512 * 1024) #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif #endif -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 #ifdef CONFIG_TARGET_LS2081ARDB #define QIXIS_QMAP_MASK 0x07 @@ -197,7 +197,7 @@ * I2C */ #ifdef CONFIG_TARGET_LS2081ARDB -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #endif #define I2C_MUX_PCA_ADDR 0x75 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ @@ -212,10 +212,10 @@ */ #define RTC #ifdef CONFIG_TARGET_LS2081ARDB -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#define CFG_SYS_I2C_RTC_ADDR 0x51 #else #define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 #endif #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index ad85e2de6ed..bbee9df404a 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -10,15 +10,15 @@ #include #include -#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CFG_SYS_FLASH_BASE 0x20000000 /* DDR */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL #define CFG_SYS_SDRAM_SIZE 0x200000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -42,22 +42,22 @@ /* Serial Port */ #define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) -#define CONFIG_SYS_SERIAL0 0x21c0000 -#define CONFIG_SYS_SERIAL1 0x21d0000 -#define CONFIG_SYS_SERIAL2 0x21e0000 -#define CONFIG_SYS_SERIAL3 0x21f0000 +#define CFG_SYS_SERIAL0 0x21c0000 +#define CFG_SYS_SERIAL1 0x21d0000 +#define CFG_SYS_SERIAL2 0x21e0000 +#define CFG_SYS_SERIAL3 0x21f0000 /*below might needs to be removed*/ -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1, \ - (void *)CONFIG_SYS_SERIAL2, \ - (void *)CONFIG_SYS_SERIAL3 } +#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ + (void *)CFG_SYS_SERIAL1, \ + (void *)CFG_SYS_SERIAL2, \ + (void *)CFG_SYS_SERIAL3 } /* MC firmware */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 /* * Carve out a DDR region which will not be used by u-boot/Linux @@ -66,7 +66,7 @@ * 512MB aligned, so the min size to hide is 512MB. */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) +#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) #endif /* I2C bus multiplexer */ @@ -75,10 +75,10 @@ /* RTC */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* Qixis */ -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 /* USB */ diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 4e8a9048596..9f891064bd5 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -9,7 +9,7 @@ #include "lx2160a_common.h" /* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_RTC_BUS_NUM 0 /* MAC/PHY configuration */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index bb9239cc599..58c0ff36571 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -9,7 +9,7 @@ #include "lx2160a_common.h" /* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 4 +#define CFG_SYS_RTC_BUS_NUM 4 /* EMC2305 */ #define I2C_MUX_CH_EMC2305 0x09 diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index b70abb013f4..157688ef7d7 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -11,7 +11,7 @@ /* USB */ /* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_RTC_BUS_NUM 0 /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index cbdb2fa1357..f87bbf7ccf3 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -21,8 +21,8 @@ #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* * U-Boot general configurations @@ -58,13 +58,13 @@ #define CONFIG_FEC_MXC_PHYADDR 0x0 #endif -#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ +#define CFG_SYS_RTC_BUS_NUM 1 /* I2C2 */ /* * RTC */ #ifdef CONFIG_CMD_DATE -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 #endif /* @@ -77,7 +77,7 @@ #endif /* LVDS display */ -#define CONFIG_SYS_LDB_CLOCK 33260000 +#define CFG_SYS_LDB_CLOCK 33260000 #define CONFIG_IMX_VIDEO_SKIP /* IIM Fuses */ diff --git a/include/configs/malta.h b/include/configs/malta.h index c9aee00cd35..65f4b05649b 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -28,7 +28,7 @@ #endif #define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* * Serial driver @@ -38,9 +38,9 @@ * Flash configuration */ #ifdef CONFIG_64BIT -# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000 +# define CFG_SYS_FLASH_BASE 0xffffffffbe000000 #else -# define CONFIG_SYS_FLASH_BASE 0xbe000000 +# define CFG_SYS_FLASH_BASE 0xbe000000 #endif /* diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 8aa3b0cd808..7c401a2cfd6 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -9,7 +9,7 @@ #include "mx6_common.h" -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) +#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + 0x80000) /* * Below defines are set but NOT really used since we by @@ -24,12 +24,12 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* NOR 16-bit mode */ -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR #define CONFIG_FLASH_VERIFY /* NOR Flash MTD */ -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } -#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } +#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) } +#define CFG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } /* Ethernet Configuration */ #define CONFIG_FEC_MXC_PHYADDR 1 @@ -116,7 +116,7 @@ "nor_img_addr=0x11000000\0" \ "nor_img_file=core-image-lwn-mccmon6.nor\0" \ "emmc_img_file=core-image-lwn-mccmon6.ext4\0" \ - "nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ + "nor_bank_start=" __stringify(CFG_SYS_FLASH_BASE) "\0" \ "nor_img_size=0x02000000\0" \ "factory_script_file=factory.scr\0" \ "factory_load_script=" \ @@ -215,8 +215,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index 2422cbf9f0b..9e480fe0558 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -18,8 +18,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment configs */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 2e07886c194..d190e4b5039 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -28,8 +28,8 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ +#define CFG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ /* Misc CPU related */ @@ -47,8 +47,8 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 139b5bca108..edd2466caa9 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -13,7 +13,7 @@ /* uart */ /* The following table includes the supported baudrates */ -# define CONFIG_SYS_BAUDRATE_TABLE \ +# define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} #define CONFIG_HOSTNAME "microblaze-generic" @@ -95,6 +95,6 @@ /* SPL part */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE #endif /* __CONFIG_H */ diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index ac5ff9289a5..cfe926c0a14 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -14,7 +14,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #if defined(CONFIG_CMD_NET) #define CONFIG_FEC_MXC_PHYADDR 1 @@ -46,8 +46,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h index 65cd6f5bc4c..d5bd4926348 100644 --- a/include/configs/mt7620.h +++ b/include/configs/mt7620.h @@ -10,13 +10,13 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 #endif /* __CONFIG_MT7620_H */ diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 1211bb47488..7c8c67f4469 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -13,7 +13,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED 0x1c000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x800000 +#define CFG_SYS_INIT_SP_OFFSET 0x800000 /* MMC */ #define MMC_SUPPORTS_TUNING @@ -27,10 +27,10 @@ #endif /* Serial common */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 } /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 #endif /* __CONFIG_MT7621_H */ diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index e5d60e1cd2b..8c297266d8b 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -10,10 +10,10 @@ #define __MT7622_H /* Uboot definition */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* SPL -> Uboot */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index 9c5034f5f08..9df2715fc7d 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -10,7 +10,7 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x80000 +#define CFG_SYS_INIT_SP_OFFSET 0x80000 /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) @@ -19,14 +19,14 @@ #endif /* Serial common */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 } /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 #endif /* __CONFIG_MT7628_H */ diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index d330adbc01b..bfa44aacc72 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -18,7 +18,7 @@ /* Defines for SPL */ #define CONFIG_SPI_ADDR 0x30000000 -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) +#define CFG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) /* SPL -> Uboot */ diff --git a/include/configs/mt7981.h b/include/configs/mt7981.h index 249f0b9662d..14c885ec55c 100644 --- a/include/configs/mt7981.h +++ b/include/configs/mt7981.h @@ -10,10 +10,10 @@ #define __MT7981_H /* Uboot definition */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* SPL -> Uboot */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt7986.h b/include/configs/mt7986.h index 990e411a640..0c41af1fc32 100644 --- a/include/configs/mt7986.h +++ b/include/configs/mt7986.h @@ -10,10 +10,10 @@ #define __MT7986_H /* Uboot definition */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* SPL -> Uboot */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h index d15941660ab..3a35527da10 100644 --- a/include/configs/mt8512.h +++ b/include/configs/mt8512.h @@ -10,7 +10,7 @@ #define __MT8512_H /* Uboot definition */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE #define ENV_BOOT_READ_IMAGE \ "boot_rd_img=mmc dev 0" \ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index e45bfd76b6e..fa275d61d18 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -32,13 +32,13 @@ /* * NS16550 Configuration */ -#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) #define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif -#if defined(CONFIG_ARMADA_38X) && !defined(CONFIG_SYS_BAUDRATE_TABLE) -#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ +#if defined(CONFIG_ARMADA_38X) && !defined(CFG_SYS_BAUDRATE_TABLE) +#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ 921600, 1000000, 1152000, 1500000, \ diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h index 9c4038be8b0..5c9620371e3 100644 --- a/include/configs/mvebu_alleycat-5.h +++ b/include/configs/mvebu_alleycat-5.h @@ -11,7 +11,7 @@ /* additions for new ARM relocation support */ #define CFG_SYS_SDRAM_BASE 0x200000000 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } /* Default Env vars */ @@ -37,6 +37,6 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_SYS_TCLK 325000000 +#define CFG_SYS_TCLK 325000000 #endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */ diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 7641b562219..9bfc48c52d9 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -15,7 +15,7 @@ /* additions for new ARM relocation support */ #define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ +#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ 921600, 1000000, 1152000, 1500000, \ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index 358e06fd207..beac3ae6496 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -9,14 +9,14 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ +#define CFG_SYS_TCLK 250000000 /* 250MHz */ /* additions for new ARM relocation support */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* auto boot */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } /* diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 2229980db37..3c99b70a2bb 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -113,12 +113,12 @@ #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_DDR_CLKSEL 0 -#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 -#define CONFIG_SYS_MAIN_PWR_ON +#define CFG_SYS_DDR_CLKSEL 0 +#define CFG_SYS_CLKTL_CBCDR 0x59E35100 +#define CFG_SYS_MAIN_PWR_ON /*----------------------------------------------------------------------- * environment organization diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index e84bac67ef7..2bc462cc37e 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -61,8 +61,8 @@ #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* environment organization */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 9e837a38833..b52e70c95a0 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -24,7 +24,7 @@ /* PMIC Controller */ #define CONFIG_POWER_FSL #define CONFIG_POWER_FSL_MC13892 -#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 +#define CFG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 #define CFG_SYS_FSL_PMIC_I2C_ADDR 0x8 /* Command definition */ @@ -96,8 +96,8 @@ #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* Framebuffer and LCD */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 52ff7b00b43..7160654eb30 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -87,7 +87,7 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR @@ -97,8 +97,8 @@ #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* FLASH and environment organization */ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 43145567544..245530aa640 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -12,7 +12,7 @@ #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ #else #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#define CFG_SYS_PL310_BASE L2_PL310_BASE #endif #endif diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 3c4ba095e4e..12741c08de5 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -86,8 +86,8 @@ /* Physical Memory Map */ #define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index 9c160c41ece..f6d3b2eeb9c 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -28,8 +28,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #define CONFIG_MXC_USB_PORTSC PORT_PTS_UTMI diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 711b5a334aa..5e95e430c49 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -140,8 +140,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 3fdf829e968..1a2160cce59 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -16,7 +16,7 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } +#define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } #include "mx6sabre_common.h" @@ -26,7 +26,7 @@ #endif #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR #endif #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 3c2621d8c91..358d9f47c0f 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -83,8 +83,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index a3a12aeb390..6632e4ea29c 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -83,8 +83,8 @@ #define PHYS_SDRAM_SIZE SZ_2G #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index f0e239fdb6e..0dd40563c29 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -79,8 +79,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index a0f9c537e5d..6f5dffe4fbb 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -107,8 +107,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 8199b4b8319..cb1019bd56a 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -109,8 +109,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 827385c65e2..4154d328ded 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -103,8 +103,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index c39b3572b84..6c165521f7a 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -82,8 +82,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index 362de482f57..85922fa436c 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -18,7 +18,7 @@ /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */ /* UART */ #define LPUART_BASE LPUART4_RBASE @@ -48,8 +48,8 @@ "bootz ${loadaddr} - ${fdt_addr}; " \ "fi;\0" \ -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE SZ_256K #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 9ef1eea5e61..99e01896c71 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -15,7 +15,7 @@ /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ /* UART */ #define LPUART_BASE LPUART4_RBASE @@ -92,7 +92,7 @@ "bootz; " \ "fi;\0" \ -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE SZ_256K #endif /* __CONFIG_H */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 9d6b3d40484..5df080ade4a 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -46,11 +46,11 @@ /* Memory sizes */ /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 +#define CFG_SYS_INIT_RAM_ADDR 0x00000000 #if defined(CONFIG_MX23) -#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024) +#define CFG_SYS_INIT_RAM_SIZE (32 * 1024) #elif defined(CONFIG_MX28) -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) +#define CFG_SYS_INIT_RAM_SIZE (128 * 1024) #endif /* Point initial SP in SRAM so SPL can use it too. */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index cdd12866ac0..a32fcd57f8f 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -23,8 +23,8 @@ #define PHYS_SDRAM_SIZE SZ_256M #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 9d098113164..dd7f9513199 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -91,8 +91,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 9ad4f590697..9c364adc636 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -47,7 +47,7 @@ */ #define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } +#define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } /* USB device configuration */ #define CONFIG_USB_DEVICE @@ -64,7 +64,7 @@ * Board ONENAND Info. */ -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#define CFG_SYS_ONENAND_BASE ONENAND_MAP /* Environment information */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -150,7 +150,7 @@ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). * This rate is divided by a local divisor. */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CFG_SYS_TIMERBASE (OMAP34XX_GPT2) /* * Physical Memory Map @@ -162,8 +162,8 @@ */ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CFG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CFG_SYS_INIT_RAM_SIZE 0x800 /* * Attached kernel image diff --git a/include/configs/novena.h b/include/configs/novena.h index 8d39d75a42b..6f588f99c34 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -31,8 +31,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* I2C */ #define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 080c659b6ec..09c4ddb6646 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -24,8 +24,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/nsim.h b/include/configs/nsim.h index b930a538640..013a3491a39 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -12,8 +12,8 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_256M /* diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index 5ac951a370a..ea1edab9fc1 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -8,8 +8,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #if IS_ENABLED(CONFIG_CMD_USB) # define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h index b475354bbc6..c0ea9e852dc 100644 --- a/include/configs/octeon_common.h +++ b/include/configs/octeon_common.h @@ -8,10 +8,10 @@ #define __OCTEON_COMMON_H__ #if defined(CONFIG_RAM_OCTEON) -#define CONFIG_SYS_INIT_SP_OFFSET 0x20180000 +#define CFG_SYS_INIT_SP_OFFSET 0x20180000 #else /* No DDR init -> run in L2 cache with limited resources */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x00180000 +#define CFG_SYS_INIT_SP_OFFSET 0x00180000 #endif #define CFG_SYS_SDRAM_BASE 0xffffffff80000000 diff --git a/include/configs/odroid.h b/include/configs/odroid.h index ce8ea583fa1..8b00a279215 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -14,7 +14,7 @@ #include #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x10502000 +#define CFG_SYS_PL310_BASE 0x10502000 #endif #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 0890f51eff2..f4e23bbb0f3 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -20,7 +20,7 @@ /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CFG_SYS_FLASH_BASE NAND_BASE #define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} #define CFG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 6eec955e88f..8bb8521f1c1 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -25,7 +25,7 @@ /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CFG_SYS_FLASH_BASE NAND_BASE #define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} #define CFG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 10f6ba63601..a6b5e55b541 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -66,8 +66,8 @@ BOOTENV /* OneNAND config */ -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) +#define CFG_SYS_ONENAND_BASE ONENAND_MAP +#define CFG_SYS_ONENAND_BLOCK_SIZE (128*1024) /* NAND config */ #define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 6001037ae88..38955377510 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -144,9 +144,9 @@ /* **** PISMO SUPPORT *** */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CFG_SYS_FLASH_BASE 0x10000000 #endif -#define CONFIG_SYS_FLASH_SIZE 0x4000000 +#define CFG_SYS_FLASH_SIZE 0x4000000 #endif /* __CONFIG_H */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 883cc0b99c9..1634db86064 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -37,8 +37,8 @@ /* Required support for the TCA642X GPIO we have on the uEVM */ #define CONFIG_TCA642X -#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 -#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 +#define CFG_SYS_I2C_TCA642X_BUS_NUM 4 +#define CFG_SYS_I2C_TCA642X_ADDR 0x22 /* Enabled commands */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 5b0d87a3367..788a1113868 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -17,9 +17,9 @@ /* * SoC Configuration */ -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CFG_SYS_OSCIN_FREQ 24000000 +#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) /* * Memory Info @@ -32,7 +32,7 @@ /* memtest will be run on 16MB */ -#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ +#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \ DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ DAVINCI_SYSCFG_SUSPSRC_UART2 | \ @@ -44,17 +44,17 @@ */ /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */ -#define CONFIG_SYS_DA850_PLL0_PLLM 18 -#define CONFIG_SYS_DA850_PLL1_PLLM 21 +#define CFG_SYS_DA850_PLL0_PLLM 18 +#define CFG_SYS_DA850_PLL1_PLLM 21 /* * DDR2 memory configuration */ -#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ +#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ DV_DDR_PHY_EXT_STRBEN | \ (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ +#define CFG_SYS_DA850_DDR2_SDBCR ( \ (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ @@ -64,9 +64,9 @@ (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ -#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 +#define CFG_SYS_DA850_DDR2_SDBCR2 0 -#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR ( \ (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ @@ -76,7 +76,7 @@ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ (1 << DV_DDR_SDTMR1_WTR_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ @@ -85,21 +85,21 @@ (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ (2 << DV_DDR_SDTMR2_CKE_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 -#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 +#define CFG_SYS_DA850_DDR2_SDRCR 0x00000492 +#define CFG_SYS_DA850_DDR2_PBBPR 0x30 /* * Serial Driver info */ #define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) +#define CFG_SYS_SPI_BASE DAVINCI_SPI1_BASE +#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) /* * I2C Configuration */ -#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 +#define CFG_SYS_I2C_EXPANDER_ADDR 0x20 /* * Flash & Environment diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 53889d699b2..e42a736136b 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -15,8 +15,8 @@ /* Physical Memory Map */ #define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* USB */ #ifdef CONFIG_USB_EHCI_MX6 diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h index d155e553e20..c96deda61d7 100644 --- a/include/configs/p1_p2_bootsrc.h +++ b/include/configs/p1_p2_bootsrc.h @@ -7,11 +7,11 @@ #include -#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR) -#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required" +#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CFG_SYS_I2C_PCA9557_ADDR) +#error "CONFIG_SYS_SPD_BUS_NUM and CFG_SYS_I2C_PCA9557_ADDR are required" #endif -#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1 +#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CFG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CFG_SYS_I2C_PCA9557_ADDR 3 msk 1 #define __VAR_CMD(var, cmd) __stringify(var=cmd\0) #define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 14d702e1efe..e8b752785b4 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -83,19 +83,19 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE #ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR -#define CONFIG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512) +#define CFG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512) #else -#define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CFG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO #endif #elif defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define CFG_SYS_NAND_U_BOOT_SIZE (832 << 10) @@ -118,8 +118,8 @@ */ #define CONFIG_L2_CACHE -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xffe00000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ #define SPD_EEPROM_ADDRESS 0x52 @@ -130,40 +130,40 @@ #define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G #endif #define CFG_SYS_SDRAM_SIZE (1u << (CFG_SYS_SDRAM_SIZE_LAW - 19)) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* Default settings for DDR3 */ #ifndef CONFIG_TARGET_P2020RDB -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 - -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 - -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 -#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_MODE_1 0x40461520 -#define CONFIG_SYS_DDR_MODE_2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x0C300000 +#define CFG_SYS_DDR_CS0_BNDS 0x0000003f +#define CFG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CFG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CFG_SYS_DDR_CS1_BNDS 0x0040007f +#define CFG_SYS_DDR_CS1_CONFIG 0x80014302 +#define CFG_SYS_DDR_CS1_CONFIG_2 0x00000000 + +#define CFG_SYS_DDR_INIT_ADDR 0x00000000 +#define CFG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CFG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CFG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CFG_SYS_DDR_WRLVL_CONTROL 0x8655A608 +#define CFG_SYS_DDR_SR_CNTR 0x00000000 +#define CFG_SYS_DDR_RCW_1 0x00000000 +#define CFG_SYS_DDR_RCW_2 0x00000000 +#define CFG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ +#define CFG_SYS_DDR_CONTROL_2 0x04401050 +#define CFG_SYS_DDR_TIMING_4 0x00220001 +#define CFG_SYS_DDR_TIMING_5 0x03402400 + +#define CFG_SYS_DDR_TIMING_3 0x00020000 +#define CFG_SYS_DDR_TIMING_0 0x00330004 +#define CFG_SYS_DDR_TIMING_1 0x6f6B4846 +#define CFG_SYS_DDR_TIMING_2 0x0FA8C8CF +#define CFG_SYS_DDR_CLK_CTRL 0x03000000 +#define CFG_SYS_DDR_MODE_1 0x40461520 +#define CFG_SYS_DDR_MODE_2 0x8000c000 +#define CFG_SYS_DDR_INTERVAL 0x0C300000 #endif /* @@ -186,23 +186,23 @@ * Local Bus Definitions */ #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_SYS_FLASH_BASE 0xec000000 +#define CFG_SYS_FLASH_BASE 0xec000000 #else -#define CONFIG_SYS_FLASH_BASE 0xef000000 +#define CFG_SYS_FLASH_BASE 0xef000000 #endif #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \ | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ /* Nand Flash */ @@ -241,42 +241,42 @@ #endif #endif /* CONFIG_NAND_FSL_ELBC */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS #endif /* Size of used area in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_CPLD_BASE 0xffa00000 +#define CFG_SYS_CPLD_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull +#define CFG_SYS_CPLD_BASE_PHYS 0xfffa00000ull #else -#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE #endif /* CPLD config size: 1Mb */ /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET #define __VSCFW_ADDR "vscfw_addr=ef000000\0" -#define CONFIG_SYS_VSC7385_BASE 0xffb00000 +#define CFG_SYS_VSC7385_BASE 0xffb00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull +#define CFG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull #else -#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE +#define CFG_SYS_VSC7385_BASE_PHYS CFG_SYS_VSC7385_BASE #endif /* The size of the VSC7385 firmware image */ @@ -292,18 +292,18 @@ */ #if defined(CONFIG_SPL_BUILD) #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #else -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #endif /* CONFIG_TPL_BUILD */ #endif #endif @@ -315,15 +315,15 @@ #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600) /* I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } +#define CFG_SYS_I2C_NOPROBES { {0, 0x29} } #endif /* @@ -331,8 +331,8 @@ */ #define CONFIG_RTC_PT7C4338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 +#define CFG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_PCA9557_ADDR 0x18 /* enable read and write access to EEPROM */ @@ -397,7 +397,7 @@ */ #if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10)) #endif #endif @@ -418,7 +418,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ /* * Environment Configuration diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 85cedde0988..2a1660bf188 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -35,8 +35,8 @@ #define PHYS_SDRAM_SIZE SZ_256M #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index f7e36f22ce8..4421e740d9e 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -37,8 +37,8 @@ #define PHYS_SDRAM_SIZE SZ_256M #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 586cddf4184..5c2ff5d02ee 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -119,8 +119,8 @@ #define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index cf705dcb197..3674e4cddae 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -16,8 +16,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ #define ENV_MMC \ diff --git a/include/configs/pg-wcom-expu1.h b/include/configs/pg-wcom-expu1.h index e08d9414129..1b72739d143 100644 --- a/include/configs/pg-wcom-expu1.h +++ b/include/configs/pg-wcom-expu1.h @@ -13,23 +13,23 @@ #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" /* CLIPS FPGA Definitions */ -#define CONFIG_SYS_CSPR3_EXT (0x00) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \ +#define CFG_SYS_CSPR3_EXT (0x00) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ CSOR_GPCM_TRHZ_40) -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ FTIM0_GPCM_TEADC(0x7) | \ FTIM0_GPCM_TEAHC(0x2)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ FTIM1_GPCM_TRAD(0x12)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) -#define CONFIG_SYS_CS3_FTIM3 0x04000000 +#define CFG_SYS_CS3_FTIM3 0x04000000 /* PRST */ #define WCOM_CLIPS_RST 0 diff --git a/include/configs/pg-wcom-seli8.h b/include/configs/pg-wcom-seli8.h index 9a7669c940b..e4bcae5bb5e 100644 --- a/include/configs/pg-wcom-seli8.h +++ b/include/configs/pg-wcom-seli8.h @@ -12,23 +12,23 @@ #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" /* PAXK FPGA Definitions */ -#define CONFIG_SYS_CSPR3_EXT (0x00) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \ +#define CFG_SYS_CSPR3_EXT (0x00) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ CSOR_GPCM_TRHZ_40) -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ FTIM0_GPCM_TEADC(0x7) | \ FTIM0_GPCM_TEAHC(0x2)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ FTIM1_GPCM_TRAD(0x12)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) -#define CONFIG_SYS_CS3_FTIM3 0x04000000 +#define CFG_SYS_CS3_FTIM3 0x04000000 /* PRST */ #define KM_LIU_RST 0 diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index ac68c933a06..7f73117ac1c 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -11,7 +11,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -60,8 +60,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index aedaf806e5e..11a833bb127 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -59,8 +59,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index d9abbbc28b3..3cc2a693cee 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -18,9 +18,9 @@ * Memory Layout */ /* Initial RAM for temporary stack, global data */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_INIT_RAM_ADDR \ - (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE) +#define CFG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_INIT_RAM_ADDR \ + (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE) /* SDRAM Configuration (for final code, data, stack, heap) */ #define CFG_SYS_SDRAM_BASE 0x88000000 diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index fc2cab960c6..9e6c210c40b 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -92,8 +92,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 22b4976d722..8af8883fad6 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -92,8 +92,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #ifdef CONFIG_VIDEO #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index f5b9eed2bcd..7028264d722 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -94,8 +94,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* PMIC */ #define CONFIG_POWER_PFUZE3000 diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 91baff96386..f9301a5524b 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -63,8 +63,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 3fbddd903a3..a233fb8ed74 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -22,47 +22,47 @@ #define MASTER_PLL_DIV 15 #define MASTER_PLL_MUL 162 #define MAIN_PLL_DIV 2 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* clocks */ /* CKGR_MOR - enable main osc. */ -#define CONFIG_SYS_MOR_VAL \ +#define CFG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | \ (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ +#define CFG_SYS_PLLAR_VAL \ (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ AT91_PMC_PLLXR_OUT(3) | \ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 +#define CFG_SYS_PIOC_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 +#define CFG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ -#define CONFIG_SYS_MATRIX_EBICSA_VAL \ +#define CFG_SYS_MATRIX_EBICSA_VAL \ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL /* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +#define CFG_SYS_SDRC_TR_VAL1 0x13C /* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ +#define CFG_SYS_SDRC_CR_VAL \ (AT91_SDRAMC_NC_9 | \ AT91_SDRAMC_NR_13 | \ AT91_SDRAMC_NB_4 | \ @@ -76,10 +76,10 @@ (1 << 28)) /* Exit Self Refresh to Active Delay */ /* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE #define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH #define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ @@ -88,37 +88,37 @@ #define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR #define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL #define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ #define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ +#define CFG_SYS_SMC0_SETUP0_VAL \ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ +#define CFG_SYS_SMC0_PULSE0_VAL \ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ +#define CFG_SYS_SMC0_CYCLE0_VAL \ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ +#define CFG_SYS_SMC0_MODE0_VAL \ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ AT91_SMC_MODE_DBW_16 | \ AT91_SMC_MODE_TDF | \ AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ +#define CFG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ AT91_RSTC_CR_PROCRST | \ AT91_RSTC_MR_ERSTL(1) | \ AT91_RSTC_MR_ERSTL(2)) /* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ +#define CFG_SYS_WDTC_WDMR_VAL \ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ AT91_WDT_MR_WDV(0xfff) | \ AT91_WDT_MR_WDDIS | \ @@ -139,10 +139,10 @@ /* NOR flash */ #define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 #define CONFIG_EXTRA_ENV_SETTINGS \ "partition=nand0,0\0" \ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index c1f6334d6a1..9fd897958a4 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -22,14 +22,14 @@ #define MASTER_PLL_DIV 6 #define MASTER_PLL_MUL 65 #define MAIN_PLL_DIV 2 /* 2 or 4 */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ /* clocks */ -#define CONFIG_SYS_MOR_VAL \ +#define CFG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | \ (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ +#define CFG_SYS_PLLAR_VAL \ (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ AT91_PMC_PLLXR_OUT(3) | \ AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ @@ -38,43 +38,43 @@ #if (MAIN_PLL_DIV == 2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) #else /* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_4) /* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_4) #endif /* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +#define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +#define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ +#define CFG_SYS_MATRIX_EBI0CSA_VAL \ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 0 +#define CFG_SYS_SDRC_MR_VAL1 0 /* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA +#define CFG_SYS_SDRC_TR_VAL1 0x3AA /* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ +#define CFG_SYS_SDRC_CR_VAL \ (AT91_SDRAMC_NC_9 | \ AT91_SDRAMC_NR_13 | \ AT91_SDRAMC_NB_4 | \ @@ -88,10 +88,10 @@ (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ /* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE #define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH #define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ @@ -100,37 +100,37 @@ #define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR #define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL #define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ #define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ +#define CFG_SYS_SMC0_SETUP0_VAL \ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ +#define CFG_SYS_SMC0_PULSE0_VAL \ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ +#define CFG_SYS_SMC0_CYCLE0_VAL \ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ +#define CFG_SYS_SMC0_MODE0_VAL \ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ AT91_SMC_MODE_DBW_16 | \ AT91_SMC_MODE_TDF | \ AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ +#define CFG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ AT91_RSTC_CR_PROCRST | \ AT91_RSTC_MR_ERSTL(1) | \ AT91_RSTC_MR_ERSTL(2)) /* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ +#define CFG_SYS_WDTC_WDMR_VAL \ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ AT91_WDT_MR_WDV(0xfff) | \ AT91_WDT_MR_WDDIS | \ @@ -142,7 +142,7 @@ /* NOR flash, if populated */ #define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -166,7 +166,7 @@ AT91_MATRIX_SCFG_SLOT_CYCLE(255)) /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ #define CONFIG_EXTRA_ENV_SETTINGS \ "partition=nand0,0\0" \ diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index 4a0a16818ed..686411eee2e 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -16,8 +16,8 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x70000000 @@ -53,9 +53,9 @@ 56, 57, 58, 59, 60, 61, 62, 63, } #endif -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/poleg.h b/include/configs/poleg.h index 365fdd30c08..518d7a3639c 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -7,10 +7,10 @@ #define __CONFIG_POLEG_H #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ +#define CFG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ #endif -#define CONFIG_SYS_BOOTMAPSZ (0x30 << 20) +#define CFG_SYS_BOOTMAPSZ (0x30 << 20) #define CFG_SYS_SDRAM_BASE 0x0 /* Default environemnt variables */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index bee1ef64948..2b25c31b1d8 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -9,8 +9,8 @@ #define __PRESIDIO_ASIC_H /* Generic Timer Definitions */ -#define CONFIG_SYS_TIMER_RATE 25000000 -#define CONFIG_SYS_TIMER_COUNTER 0xf4321008 +#define CFG_SYS_TIMER_RATE 25000000 +#define CFG_SYS_TIMER_COUNTER 0xf4321008 /* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE * does not yet support DT. Thus define it here. @@ -18,7 +18,7 @@ #define GICD_BASE 0xf7011000 #define GICC_BASE 0xf7012000 -#define CONFIG_SYS_TIMER_BASE 0xf4321000 +#define CFG_SYS_TIMER_BASE 0xf4321000 /* Use external clock source */ #define PRESIDIO_APB_CLK 125000000 @@ -26,11 +26,11 @@ /* Cortina Serial Configuration */ #define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK) -#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1} +#define CORTINA_SERIAL_PORTS {(void *)CFG_SYS_SERIAL0, \ + (void *)CFG_SYS_SERIAL1} -#define CONFIG_SYS_SERIAL0 PER_UART0_CFG -#define CONFIG_SYS_SERIAL1 PER_UART1_CFG +#define CFG_SYS_SERIAL0 PER_UART0_CFG +#define CFG_SYS_SERIAL1 PER_UART1_CFG /* SDRAM Bank #1 */ #define DDR_BASE 0x00000000 @@ -58,7 +58,7 @@ /* nand driver parameters */ #ifdef CONFIG_TARGET_PRESIDIO_ASIC - #define CFG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE + #define CFG_SYS_NAND_BASE CFG_SYS_FLASH_BASE #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h index 58020ae95b1..c41bb341d82 100644 --- a/include/configs/qcs404-evb.h +++ b/include/configs/qcs404-evb.h @@ -11,7 +11,7 @@ #include #include -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x5000000\0" \ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index e7c810957d6..aa9cae017d9 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -12,39 +12,39 @@ /* Needed to fill the ccsrbar pointer */ /* Virtual address to CCSRBAR */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CFG_SYS_CCSRBAR 0xe0000000 /* Physical address should be a function call */ #ifndef __ASSEMBLY__ extern unsigned long long get_phys_ccsrbar_addr_early(void); -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32) -#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early() +#define CFG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32) +#define CFG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early() #else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR #endif /* Virtual address to a temporary map if we need it (max 128MB) */ -#define CONFIG_SYS_TMPVIRT 0xe8000000 +#define CFG_SYS_TMPVIRT 0xe8000000 /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CONFIG_HWCONFIG -#define CONFIG_SYS_INIT_RAM_ADDR 0x00100000 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 +#define CFG_SYS_INIT_RAM_ADDR 0x00100000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* RTC */ #define CONFIG_RTC_PT7C4338 @@ -58,7 +58,7 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index f6ee7201eba..bad74cc620d 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -10,12 +10,12 @@ #define CFG_SYS_SDRAM_SIZE 0x04000000 /* Address of u-boot image in Flash */ -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) +#define CFG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* * NOR Flash ( Spantion S29GL256P ) */ -#define CONFIG_SYS_FLASH_BASE (0xA0000000) -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BASE (0xA0000000) +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif /* __CONFIG_H */ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 606a0a7ecde..a86180ead57 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -15,14 +15,14 @@ #endif /* console */ -#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } +#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 } #define CFG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) #define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) /* Timer */ #define CONFIG_TMU_TIMER -#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 8) +#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ +#define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 8) #endif /* __RCAR_GEN2_COMMON_H */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 58530725978..e9cbd253824 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -18,7 +18,7 @@ #define GICC_BASE 0xF1020000 /* console */ -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 } /* PHY needs a longer autoneg timeout */ #define PHY_ANEG_TIMEOUT 20000 diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index b4c19727478..a4cae697181 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -8,7 +8,7 @@ #include #include "rockchip-common.h" -#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000 #define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index fac27a7d27c..302546630ac 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -8,7 +8,7 @@ #include "rockchip-common.h" -#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000 #define CONFIG_IRAM_BASE 0x10080000 diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 6889ba591b3..58ad62afe16 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -8,7 +8,7 @@ #include #include "rockchip-common.h" -#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000 #define CONFIG_IRAM_BASE 0x10080000 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 4aa7e0449db..6b55c57dd77 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -9,7 +9,7 @@ #include #include "rockchip-common.h" -#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000 #define CONFIG_IRAM_BASE 0xff700000 diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 2c24944d9c3..e3549275138 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -17,14 +17,14 @@ /* Use SoC timer for AArch32, but architected timer for AArch64 */ #ifndef CONFIG_ARM64 -#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER \ +#define CFG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_COUNTER \ (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo) #endif /* Memory layout */ #define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* * The board really has 256M. However, the VC (VideoCore co-processor) shares * the RAM, and uses a configurable portion at the top. We tell U-Boot that a diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 76836add302..84a5ae6965d 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -10,10 +10,10 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CFG_SYS_TIMER_RATE (24 * 1000 * 1000) /* TIMER1,initialized by ddr initialize code */ -#define CONFIG_SYS_TIMER_BASE 0x10350020 -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) +#define CFG_SYS_TIMER_BASE 0x10350020 +#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMER_BASE + 8) #define CFG_SYS_SDRAM_BASE 0x60000000 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index ed891ab22a9..3d49d52b381 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -124,6 +124,6 @@ /* FLASH and environment organization */ #define CONFIG_MMC_DEFAULT_DEV 0 -#define CONFIG_SYS_ONENAND_BASE 0xB0000000 +#define CFG_SYS_ONENAND_BASE 0xB0000000 #endif /* __CONFIG_H */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 614d04fda07..06be9c0f652 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -87,7 +87,7 @@ "mmcrootpart=3\0" \ "opts=always_resume=1" -#define CONFIG_SYS_ONENAND_BASE 0x0C000000 +#define CFG_SYS_ONENAND_BASE 0x0C000000 #ifndef __ASSEMBLY__ void universal_spi_scl(int bit); diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 41e52546ed3..2e422cd241e 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -14,7 +14,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* __SALVATOR_X_H */ diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h index 75302bf5c05..f44ce909b91 100644 --- a/include/configs/sam9x60_curiosity.h +++ b/include/configs/sam9x60_curiosity.h @@ -10,8 +10,8 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0 /* ignored in arm */ diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 22813d4c544..27b39ebf417 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -11,8 +11,8 @@ #define __CONFIG_H__ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0 /* ignored in arm */ diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index 79f354d2e6c..d62146e7797 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -11,8 +11,8 @@ #include "at91-sama5_common.h" -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SPL */ diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index f826eab9ff2..1979cb366e5 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -12,8 +12,8 @@ #include "at91-sama5_common.h" -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h index 01ed1a3c8e7..a072b21dfb8 100644 --- a/include/configs/sama5d2_icp.h +++ b/include/configs/sama5d2_icp.h @@ -11,8 +11,8 @@ #include "at91-sama5_common.h" -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h index 2e3c1ea4006..bf3c92bdf39 100644 --- a/include/configs/sama5d2_ptc_ek.h +++ b/include/configs/sama5d2_ptc_ek.h @@ -12,8 +12,8 @@ #include "at91-sama5_common.h" -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 3f58928565f..4f579ad9c56 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -27,7 +27,7 @@ /* NOR flash */ #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CFG_SYS_FLASH_BASE 0x10000000 #endif /* SDRAM */ diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index 68fa31fe76f..59f13edbc85 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -9,8 +9,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x60000000 #define CFG_SYS_SDRAM_SIZE 0x20000000 diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 5a7f5e135b5..1081e0bbc49 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -17,7 +17,7 @@ #define CFG_SYS_SDRAM_SIZE \ (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20) -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} #ifndef SANDBOX_NO_SDL diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h index af5fe27e68b..f7cdd5a1956 100644 --- a/include/configs/sdm845.h +++ b/include/configs/sdm845.h @@ -11,7 +11,7 @@ #include #include -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x4000000\0" \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 31552f4619d..5a001716fb0 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -35,7 +35,7 @@ #define CFG_SYS_SDRAM_BASE PHYS_DRAM_1 /* Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ /* NS16550 Configuration */ #define CFG_SYS_NS16550_CLK (48000000) diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index d2bc73a400e..794475942a2 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -36,8 +36,8 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ /* misc settings */ @@ -87,8 +87,8 @@ * leaving the correct space for initial global data structure above that * address while providing maximum stack area below. */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* Defines for SPL */ @@ -102,11 +102,11 @@ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } -#define CONFIG_SYS_MASTER_CLOCK (198656000/2) +#define CFG_SYS_MASTER_CLOCK (198656000/2) #define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x2060bf09 -#define CONFIG_SYS_MCKR 0x100 -#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) -#define CONFIG_SYS_AT91_PLLB 0x10483f0e +#define CFG_SYS_AT91_PLLA 0x2060bf09 +#define CFG_SYS_MCKR 0x100 +#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR) +#define CFG_SYS_AT91_PLLB 0x10483f0e #endif /* __CONFIG_H */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 64963eebe5c..ffa1a1fcb0e 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -88,7 +88,7 @@ * Boot configuration */ -#define CONFIG_SYS_ONENAND_BASE 0xE7100000 +#define CFG_SYS_ONENAND_BASE 0xE7100000 /* * Ethernet Contoller driver diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index 44b9109d442..14f9cf56028 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -39,7 +39,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 9b1cb372ece..b7aa49ce435 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -15,16 +15,16 @@ #include /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* CPU */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 #define CFG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +#define CFG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* Mem test settings */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 95516800793..afca7e18e9b 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -15,7 +15,7 @@ * Clocks */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CFG_SYS_TIMERBASE OMAP34XX_GPT2 #define V_NS16550_CLK 48000000 #define V_OSCK 26000000 @@ -55,7 +55,7 @@ #define CFG_SYS_NS16550_CLK V_NS16550_CLK #define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ 115200 } /* diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 49883ea7a3c..35c777b774e 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -18,7 +18,7 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} /* * L4 OSC1 Timer 0 diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h index 261ae56c1dc..29b4b22b398 100644 --- a/include/configs/socfpga_arria5_secu1.h +++ b/include/configs/socfpga_arria5_secu1.h @@ -10,7 +10,7 @@ #include /* Eternal oscillator */ -#define CONFIG_SYS_TIMER_RATE 40000000 +#define CFG_SYS_TIMER_RATE 40000000 /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512MiB on SECU1 */ @@ -21,7 +21,7 @@ * the last two bytes of the 128 bytes large NVRAM in the * RTC which begin at address 0x20 */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* Environment settings */ diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h index 7012097276c..aa13878177e 100644 --- a/include/configs/socfpga_chameleonv3.h +++ b/include/configs/socfpga_chameleonv3.h @@ -17,7 +17,7 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} #define CONFIG_EXTRA_ENV_SETTINGS \ "autoload=no\0" \ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 7ef7c5da828..bbbdea6664c 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -12,12 +12,12 @@ */ #define PHYS_SDRAM_1 0x0 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CFG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 /* SPL memory allocation configuration, this is for FAT implementation */ -#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ +#define CFG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ CONFIG_SYS_SPL_MALLOC_SIZE) #endif @@ -27,9 +27,9 @@ * at this address to not overwrite the bootcounter by checking, if the * bootcounter address is located in the internal SRAM. */ -#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ - (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE))) +#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CFG_SYS_INIT_RAM_ADDR) && \ + (CONFIG_SYS_BOOTCOUNT_ADDR < (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE))) #endif /* @@ -48,16 +48,16 @@ /* * Cache */ -#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS +#define CFG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* * L4 OSC1 Timer 0 */ #ifndef CONFIG_TIMER -#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) -#ifndef CONFIG_SYS_TIMER_RATE -#define CONFIG_SYS_TIMER_RATE 25000000 +#define CFG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS +#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMERBASE + 0x4) +#ifndef CFG_SYS_TIMER_RATE +#define CFG_SYS_TIMER_RATE 25000000 #endif #endif diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 9403e2f4306..47089f312d2 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -26,8 +26,8 @@ /* * U-Boot run time memory configurations */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 +#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CFG_SYS_INIT_RAM_SIZE 0x40000 /* * U-Boot environment configurations diff --git a/include/configs/socrates.h b/include/configs/socrates.h index c628860eac7..0a2d5815170 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -42,20 +42,20 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ +#define CFG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#undef CFG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_CCSRBAR 0xE0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xE0000000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CONFIG_VERY_BIG_RAM /* I2C addresses of SPD EEPROMs */ @@ -63,46 +63,46 @@ /* Hardcoded values, to use instead of SPD */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935D322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 -#define CONFIG_SYS_DDR_MODE 0x00480432 -#define CONFIG_SYS_DDR_INTERVAL 0x030C0100 -#define CONFIG_SYS_DDR_CONFIG_2 0x04400000 -#define CONFIG_SYS_DDR_CONFIG 0xC3008000 -#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 +#define CFG_SYS_DDR_CS0_BNDS 0x0000000f +#define CFG_SYS_DDR_CS0_CONFIG 0x80010102 +#define CFG_SYS_DDR_TIMING_0 0x00260802 +#define CFG_SYS_DDR_TIMING_1 0x3935D322 +#define CFG_SYS_DDR_TIMING_2 0x14904CC8 +#define CFG_SYS_DDR_MODE 0x00480432 +#define CFG_SYS_DDR_INTERVAL 0x030C0100 +#define CFG_SYS_DDR_CONFIG_2 0x04400000 +#define CFG_SYS_DDR_CONFIG 0xC3008000 +#define CFG_SYS_DDR_CLK_CONTROL 0x03800000 #define CFG_SYS_SDRAM_SIZE 256 /* in Megs */ /* * Flash on the LocalBus */ -#define CONFIG_SYS_FLASH0 0xFE000000 -#define CONFIG_SYS_FLASH1 0xFC000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } +#define CFG_SYS_FLASH0 0xFE000000 +#define CFG_SYS_FLASH1 0xFC000000 +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH1, CFG_SYS_FLASH0 } -#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ +#define CFG_SYS_LBC_FLASH_BASE CFG_SYS_FLASH1 /* Localbus flash start */ +#define CFG_SYS_FLASH_BASE CFG_SYS_LBC_FLASH_BASE /* start of FLASH */ -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ +#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ +#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* FPGA and NAND */ -#define CONFIG_SYS_FPGA_BASE 0xc0000000 -#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ +#define CFG_SYS_FPGA_BASE 0xc0000000 +#define CFG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ -#define CFG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) +#define CFG_SYS_NAND_BASE (CFG_SYS_FPGA_BASE + 0x70) /* LIME GDC */ -#define CONFIG_SYS_LIME_BASE 0xc8000000 +#define CFG_SYS_LIME_BASE 0xc8000000 /* * General PCI @@ -137,7 +137,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 008aa500107..de0f48b79a1 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -54,8 +54,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h index 3c70856fc70..a5987c5e17a 100644 --- a/include/configs/stemmy.h +++ b/include/configs/stemmy.h @@ -15,7 +15,7 @@ */ /* FIXME: This should be loaded from device tree... */ -#define CONFIG_SYS_PL310_BASE 0xa0412000 +#define CFG_SYS_PL310_BASE 0xa0412000 /* Linux does not boot if FDT / initrd is loaded to end of RAM */ #define BOOT_ENV \ diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 806323e375d..9294d57ca84 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -14,7 +14,7 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x3E000000 -#define CONFIG_SYS_HZ_CLOCK 750000000 /* 750 MHz */ +#define CFG_SYS_HZ_CLOCK 750000000 /* 750 MHz */ /* Environment */ @@ -22,7 +22,7 @@ * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ SZ_256M +#define CFG_SYS_BOOTMAPSZ SZ_256M #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 51f69010b17..afd7d50428b 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -7,13 +7,13 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index 221b7abe1ad..c8aad47966f 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -10,15 +10,15 @@ #include /* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_16M +#define CFG_SYS_BOOTMAPSZ SZ_16M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index 55e70ce9250..573a6b17956 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -10,15 +10,15 @@ #include /* For booting Linux, use the first 12MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_8M + SZ_4M +#define CFG_SYS_BOOTMAPSZ SZ_8M + SZ_4M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index c7d6d9368a2..14e883a3589 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -10,15 +10,15 @@ #include /* For booting Linux, use the first 6MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_4M + SZ_2M +#define CFG_SYS_BOOTMAPSZ SZ_4M + SZ_2M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) @@ -33,7 +33,7 @@ "ramdisk_addr_r=0xC0438000\0" \ BOOTENV -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ +#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + \ CONFIG_SPL_PAD_TO) /* For splashcreen */ diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index f959fcf26f3..67e6a3a19d2 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -11,11 +11,11 @@ #include /* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_16M +#define CFG_SYS_BOOTMAPSZ SZ_16M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_HZ_CLOCK 1000000 +#define CFG_SYS_HZ_CLOCK 1000000 #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index c8688e9ca7b..4786eb001bc 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -11,11 +11,11 @@ #include /* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_16M +#define CFG_SYS_BOOTMAPSZ SZ_16M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_HZ_CLOCK 1000000 +#define CFG_SYS_HZ_CLOCK 1000000 #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h index f7fa8c51d8e..e667fe6f6ac 100644 --- a/include/configs/stm32h750-art-pi.h +++ b/include/configs/stm32h750-art-pi.h @@ -11,11 +11,11 @@ #include /* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M) +#define CFG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M) -#define CONFIG_SYS_FLASH_BASE 0x90000000 +#define CFG_SYS_FLASH_BASE 0x90000000 -#define CONFIG_SYS_HZ_CLOCK 1000000 +#define CFG_SYS_HZ_CLOCK 1000000 #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index d7111493142..c259a616133 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -19,7 +19,7 @@ * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ SZ_256M +#define CFG_SYS_BOOTMAPSZ SZ_256M /* NAND support */ diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h index c51022b40d2..ad8126f6103 100644 --- a/include/configs/stm32mp13_st_common.h +++ b/include/configs/stm32mp13_st_common.h @@ -15,7 +15,7 @@ #include /* uart with on-board st-link */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600, \ 1000000, 2000000, 4000000} diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index f78ce41ed85..c9cfadd9ce0 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -19,7 +19,7 @@ * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ SZ_256M +#define CFG_SYS_BOOTMAPSZ SZ_256M /* NAND support */ diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 6bdc286cfca..38b5aa7319c 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -14,7 +14,7 @@ #include /* uart with on-board st-link */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600, \ 1000000, 2000000 } diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index 234327e017b..faff8d6ed6d 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -10,7 +10,7 @@ #define CONFIG_HOSTNAME "stmark2" -#define CONFIG_SYS_UART_PORT 0 +#define CFG_SYS_UART_PORT 0 #define LDS_BOARD_TEXT \ board/sysam/stmark2/sbf_dram_init.o (.text*) @@ -34,24 +34,24 @@ "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ "" -#define CONFIG_SYS_SBFHDR_SIZE 0x7 +#define CFG_SYS_SBFHDR_SIZE 0x7 /* Input, PCI, Flexbus, and VCO */ #define CONFIG_PRAM 2048 /* 2048 KB */ -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 /* * Definitions for initial stack pointer and data area (in internal SRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 /* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_INIT_SP_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ +#define CFG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_SP_OFFSET ((CFG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) +#define CFG_SYS_SBFHDR_DATA_OFFSET (CFG_SYS_INIT_RAM_SIZE - 32) /* * Start addresses for the final memory configuration @@ -61,7 +61,7 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 #define CFG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ -#define CONFIG_SYS_DRAM_TEST +#define CFG_SYS_DRAM_TEST #if defined(CONFIG_CF_SBF) #define CONFIG_SERIAL_BOOT @@ -75,7 +75,7 @@ * the maximum mapped by the Linux kernel during initialization ?? */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ (CFG_SYS_SDRAM_SIZE << 20)) /* Configuration for environment @@ -83,22 +83,22 @@ */ /* Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) -#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CFG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CFG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ CF_CACR_ICINVA | CF_CACR_EUSP) -#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ +#define CFG_SYS_CACHE_DCACR ((CFG_SYS_CACHE_ICACR | \ CF_CACR_DEC | CF_CACR_DDCM_P | \ CF_CACR_DCINVA) & ~CF_CACR_ICINVA) -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 12) +#define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 12) #endif /* __STMARK2_CONFIG_H */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index b2dcb6058b1..7eadb6d421e 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_STV0991_H #define __CONFIG_STV0991_H -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#define CFG_SYS_EXCEPTION_VECTORS_HIGH /* ram memory-related information */ #define PHYS_SDRAM_1 0x00000000 @@ -16,8 +16,8 @@ /* user interface */ /* MISC */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_ADDR 0x00190000 /* U-Boot Load Address */ /* Misc configuration */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index e1a66f53ff5..1677aafad03 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -62,9 +62,9 @@ * is known yet. * H6 has SRAM A1 at 0x00020000. */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS +#define CFG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS /* FIXME: this may be larger on some SoCs */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ #define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index daa9bbec88a..69926890010 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -6,7 +6,7 @@ #define __CONFIG_H /* Timers for fasp(TIMCLK) */ -#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */ +#define CFG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */ /* * SDRAM (for initialize) @@ -28,7 +28,7 @@ */ /* RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Serial (pl011) */ #define UART_CLK (62500000) @@ -36,8 +36,8 @@ #define CONFIG_PL01x_PORTS {(void *)(0x2a400000)} /* Support MTD */ -#define CONFIG_SYS_FLASH_BASE (0x08000000) -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CFG_SYS_FLASH_BASE (0x08000000) +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE} /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 1aba986e1e6..baaf94e2dd5 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -29,8 +29,8 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ /* Misc CPU related */ @@ -49,8 +49,8 @@ * leaving the correct space for initial global data structure above * that address while providing maximum stack area below. */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -136,11 +136,11 @@ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } -#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_MASTER_CLOCK 132096000 #define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x202A3F01 -#define CONFIG_SYS_MCKR 0x1300 -#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) -#define CONFIG_SYS_AT91_PLLB 0x10193F05 +#define CFG_SYS_AT91_PLLA 0x202A3F01 +#define CFG_SYS_MCKR 0x1300 +#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR) +#define CFG_SYS_AT91_PLLB 0x10193F05 #endif diff --git a/include/configs/tb100.h b/include/configs/tb100.h index cd1309b3b88..1318f5e5ee4 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -12,8 +12,8 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_128M /* diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 2d8bde1cee8..f6544f6226c 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -15,10 +15,10 @@ /* Physical Memory Map */ #define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_BOOTMAPSZ 0x10000000 +#define CFG_SYS_BOOTMAPSZ 0x10000000 /* Framebuffer */ #define CONFIG_IMX_HDMI diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 7e764b0000b..66cf7ae5847 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -17,8 +17,8 @@ /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ #ifndef CONFIG_ARM64 -#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE +#define CFG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE #endif /* Environment */ @@ -42,11 +42,11 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ #ifndef CONFIG_ARM64 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CFG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE +#define CFG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN /* Defines for SPL */ #endif diff --git a/include/configs/ten64.h b/include/configs/ten64.h index 04772c9e4ef..57724719a9d 100644 --- a/include/configs/ten64.h +++ b/include/configs/ten64.h @@ -10,7 +10,7 @@ #include "ls1088a_common.h" -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd" #define SD_BOOTCOMMAND "run distro_bootcmd" diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 1f60b9b4979..7becf1eb7cb 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -8,7 +8,7 @@ #define MEM_BASE 0x00500000 -#define CONFIG_SYS_LOWMEM_BASE MEM_BASE +#define CFG_SYS_LOWMEM_BASE MEM_BASE /* Link Definitions */ @@ -22,8 +22,8 @@ /* Generic Interrupt Controller Definitions */ #define GICD_BASE (0x801000000000) #define GICR_BASE (0x801000002000) -#define CONFIG_SYS_SERIAL0 0x87e024000000 -#define CONFIG_SYS_SERIAL1 0x87e025000000 +#define CFG_SYS_SERIAL0 0x87e024000000 +#define CFG_SYS_SERIAL1 0x87e025000000 /* Miscellaneous configurable options */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index e5b23d2a54c..03849adb5ab 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -74,7 +74,7 @@ /** * Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CFG_SYS_TIMERBASE 0x4802E000 /* NS16550 Configuration */ #define CFG_SYS_NS16550_CLK (48000000) diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 4a7c3d5b449..7b04292d218 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -25,7 +25,7 @@ /** * Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CFG_SYS_TIMERBASE 0x4802E000 /* * NS16550 Configuration diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 00eb329faa8..ed17b429209 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -12,7 +12,7 @@ #define __CONFIG_TI_AM335X_COMMON_H__ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 65abb187d96..ea45bba409c 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -14,7 +14,7 @@ /* SoC Configuration */ /* Memory Configuration */ -#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 +#define CFG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ #ifdef CONFIG_SYS_MALLOC_F_LEN @@ -44,7 +44,7 @@ #endif /* SPI Configuration */ -#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) +#define CFG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) /* Keystone net */ #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR @@ -176,9 +176,9 @@ #include #include #ifndef CONFIG_SOC_K2G -#define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) +#define CFG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) #else -#define CONFIG_SYS_HZ_CLOCK get_external_clk(sys_clk) +#define CFG_SYS_HZ_CLOCK get_external_clk(sys_clk) #endif #endif /* __CONFIG_KS2_EVM_H */ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index d282c3956e0..36a05b6896e 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -27,7 +27,7 @@ /* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CFG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} /* Select serial console configuration */ @@ -46,7 +46,7 @@ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). * This rate is divided by a local divisor. */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CFG_SYS_TIMERBASE (OMAP34XX_GPT2) /* SPL */ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index ce50e35d8d4..9a068e26140 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -12,7 +12,7 @@ #define __CONFIG_TI_OMAP4_COMMON_H #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CFG_SYS_PL310_BASE 0x48242000 #endif /* Get CPU defs */ @@ -20,7 +20,7 @@ #include /* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE +#define CFG_SYS_TIMERBASE GPT2_BASE #include diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index c49c177390b..37ab2e44672 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -17,7 +17,7 @@ #define __CONFIG_TI_OMAP5_COMMON_H /* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE +#define CFG_SYS_TIMERBASE GPT2_BASE #include diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index a609aa3a2aa..0f28690612a 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -41,6 +41,6 @@ * Else boot FIT image. */ -#define CONFIG_SYS_FLASH_BASE 0x0C000000 +#define CFG_SYS_FLASH_BASE 0x0C000000 #endif /* __TOTAL_COMPUTE_H */ diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 13789819917..24943c8dcfb 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -8,8 +8,8 @@ #define CFG_SYS_SDRAM_BASE 0xa0000000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* * Serial Port diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index f8e3a2d017a..9c3454add46 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -269,8 +269,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* * All the defines above are for the TQMa6 SoM diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 999130600cc..ce897fcd932 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -17,8 +17,8 @@ /* Config on-board RTC */ #define CONFIG_RTC_DS1337 -#define CONFIG_SYS_RTC_BUS_NUM 2 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_RTC_BUS_NUM 2 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* Turn off RTC square-wave output to save battery */ #define CONFIG_RTC_DS1337_NOOSC diff --git a/include/configs/trats.h b/include/configs/trats.h index 23dcf20c1f4..5bd0ca2a964 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -12,7 +12,7 @@ #include #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x10502000 +#define CFG_SYS_PL310_BASE 0x10502000 #endif /* TRATS has 4 banks of DRAM */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 9c6433ccfd8..cef563696bd 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -13,7 +13,7 @@ #include #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x10502000 +#define CFG_SYS_PL310_BASE 0x10502000 #endif /* TRATS2 has 4 banks of DRAM */ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index 4ca8eafc914..fdb420ed874 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -9,7 +9,7 @@ #define _CONFIG_TURRIS_MOX_H #define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ +#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ 921600, 1000000, 1152000, 1500000, \ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index c1e80b44c85..fac8c1eeb4e 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -50,8 +50,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index f73092661a1..0e0d5b5b3e4 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -58,8 +58,8 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* PMIC */ #define CONFIG_POWER_PFUZE3000 diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index a977271c1e6..ab199bc726a 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -14,7 +14,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* __ULCB_H */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index a57ecffd596..8cd81f1cddd 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -37,7 +37,7 @@ #if !defined(CONFIG_ARM64) /* Time clock 1MHz */ -#define CONFIG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_RATE 1000000 #endif #define CFG_SYS_NAND_REGS_BASE 0x68100000 @@ -162,11 +162,11 @@ LINUXBOOT_ENV_SETTINGS \ BOOTENV -#define CONFIG_SYS_BOOTMAPSZ 0x20000000 +#define CFG_SYS_BOOTMAPSZ 0x20000000 /* only for SPL */ /* subtract sizeof(struct legacy_img_hdr) */ -#define CONFIG_SYS_UBOOT_BASE (0x130000 - 0x40) +#define CFG_SYS_UBOOT_BASE (0x130000 - 0x40) #endif /* __CONFIG_UNIPHIER_H__ */ diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index d2fd23e1d91..657dbadd339 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -17,8 +17,8 @@ #include /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* * Hardware drivers @@ -28,8 +28,8 @@ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index e944e78603e..da68d7a0da9 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -61,7 +61,7 @@ #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __CONFIG_H */ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index d9e5dfaceaf..b03159805c1 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -10,7 +10,7 @@ /* Onboard devices */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 #define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index b209d97e5ec..18ac6b2b089 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -53,8 +53,8 @@ "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x2 " \ "${blkcnt}; fi\0" -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M #if defined(CONFIG_ENV_IS_IN_MMC) /* Environment in eMMC, before config block at the end of 1st "boot sector" */ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 1b9f2ca26f6..88839a6e561 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -65,8 +65,8 @@ "${blkcnt} / 0x200; mmc dev 2 1; mmc write ${loadaddr} 0x0 " \ "${blkcnt}; fi\0" -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K /* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */ #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 9a46d50c6f3..30c1f5025b0 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -254,9 +254,9 @@ BOOTENV #ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 #else -#define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000) +#define CFG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000) #endif #endif /* __VEXPRESS_AEMV8_H */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index de571f63ee1..e8b6acf8b8f 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -112,16 +112,16 @@ #define SCTL_BASE V2M_SYSCTL #define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) -#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) +#define CFG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) /* PL011 Serial Configuration */ #define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1} +#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ + (void *)CFG_SYS_SERIAL1} -#define CONFIG_SYS_SERIAL0 V2M_UART0 -#define CONFIG_SYS_SERIAL1 V2M_UART1 +#define CFG_SYS_SERIAL0 V2M_UART0 +#define CFG_SYS_SERIAL1 V2M_UART1 /* Miscellaneous configurable options */ #define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) @@ -135,7 +135,7 @@ /* additions for new relocation code */ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Basic environment settings */ #define BOOT_TARGET_DEVICES(func) \ @@ -164,7 +164,7 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" /* FLASH and environment organization */ -#define CONFIG_SYS_FLASH_SIZE 0x04000000 +#define CFG_SYS_FLASH_SIZE 0x04000000 /* Timeout values in ticks */ @@ -177,6 +177,6 @@ */ /* Store environment at top of flash */ -#define CONFIG_SYS_FLASH_BANKS_LIST { V2M_NOR0, V2M_NOR1 } +#define CFG_SYS_FLASH_BANKS_LIST { V2M_NOR0, V2M_NOR1 } #endif /* VEXPRESS_COMMON_H */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 7b526f725af..14e6b2bac91 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -124,7 +124,7 @@ #define PHYS_SDRAM_SIZE (128 * 1024 * 1024) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif diff --git a/include/configs/vinco.h b/include/configs/vinco.h index df0e269b5d2..9f72bdde816 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -21,7 +21,7 @@ #define CONFIG_USART_ID 30 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c +#define CFG_SYS_TIMER_COUNTER 0xfc06863c /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 @@ -31,7 +31,7 @@ #ifdef CONFIG_CMD_MMC #define ATMEL_BASE_MMCI 0xfc000000 -#define CONFIG_SYS_MMC_CLK_OD 500000 +#define CFG_SYS_MMC_CLK_OD 500000 /* For generating MMC partitions */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 7555d97c814..ab5cd5cf636 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -24,8 +24,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 38b940d35ea..43050d61c37 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -9,14 +9,14 @@ /* RAM */ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 /* Serial SPL */ #define CFG_SYS_NS16550_CLK 40000000 diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 3acef221327..23027b1d3d9 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -90,8 +90,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index cba215c379f..56c90aa1032 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -85,8 +85,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 32555c9b6af..065006f912c 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -42,7 +42,7 @@ */ /* driver configuration */ -#define CONFIG_SYS_MAX_NAND_CHIPS 1 +#define CFG_SYS_MAX_NAND_CHIPS 1 #define CFG_SYS_NAND_BASE MLC_NAND_BASE /* diff --git a/include/configs/x530.h b/include/configs/x530.h index a0162cab219..dee87cb7732 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -13,7 +13,7 @@ /* * NS16550 Configuration */ -#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) #define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index f76c1f8be0f..3e17b53dde2 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -30,7 +30,7 @@ * CPU Features */ -#define CONFIG_SYS_STACK_SIZE (32 * 1024) +#define CFG_SYS_STACK_SIZE (32 * 1024) /*----------------------------------------------------------------------- * Environment configuration diff --git a/include/configs/xea.h b/include/configs/xea.h index 87f628d4ab8..b432ab2dc8e 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -16,9 +16,9 @@ /* SPL */ -#define CONFIG_SYS_SPI_KERNEL_OFFS SZ_1M -#define CONFIG_SYS_SPI_ARGS_OFFS SZ_512K -#define CONFIG_SYS_SPI_ARGS_SIZE SZ_32K +#define CFG_SYS_SPI_KERNEL_OFFS SZ_1M +#define CFG_SYS_SPI_ARGS_OFFS SZ_512K +#define CFG_SYS_SPI_ARGS_SIZE SZ_32K /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 8caf5394ed4..ee3130ed327 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -15,7 +15,7 @@ #define GICR_BASE 0xF9080000 /* Serial setup */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } /* GUID for capsule updatable firmware image */ diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h index 0ccd38b7e69..7d77189693e 100644 --- a/include/configs/xilinx_versal_net.h +++ b/include/configs/xilinx_versal_net.h @@ -20,7 +20,7 @@ #define GICR_BASE 0xF9060000 /* Serial setup */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } #if defined(CONFIG_CMD_DFU) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 60f007a10fc..efe241df97e 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -15,7 +15,7 @@ #define GICC_BASE 0xF9020000 /* Serial setup */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } /* GUIDs for capsule updatable firmware images */ @@ -192,9 +192,9 @@ #endif #if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) -# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000 -# define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000 -# define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000 +# define CFG_SYS_SPI_KERNEL_OFFS 0x80000 +# define CFG_SYS_SPI_ARGS_OFFS 0xa0000 +# define CFG_SYS_SPI_ARGS_SIZE 0xa0000 #endif /* u-boot is like dtb */ diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h index b6bc402a7e9..3a7b7e03d6a 100644 --- a/include/configs/xilinx_zynqmp_r5.h +++ b/include/configs/xilinx_zynqmp_r5.h @@ -10,13 +10,13 @@ /* Serial drivers */ /* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} /* Boot configuration */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Extend size of kernel image for uncompression */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 613ed959553..3e604894ad4 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -22,8 +22,8 @@ #define PHYS_SDRAM_SIZE (128 << 20) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment is in stored in the eMMC boot partition */ diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 8739bb24841..9201dac7abc 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -21,12 +21,12 @@ /*===================*/ #if XCHAL_HAVE_PTP_MMU -#define CONFIG_SYS_MEMORY_BASE \ +#define CFG_SYS_MEMORY_BASE \ (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) -#define CONFIG_SYS_IO_BASE 0xf0000000 +#define CFG_SYS_IO_BASE 0xf0000000 #else -#define CONFIG_SYS_MEMORY_BASE 0x60000000 -#define CONFIG_SYS_IO_BASE 0x90000000 +#define CFG_SYS_MEMORY_BASE 0x60000000 +#define CFG_SYS_IO_BASE 0x90000000 #define CONFIG_MAX_MEM_MAPPED 0x10000000 #endif @@ -100,16 +100,16 @@ */ /* FPGA core clock frequency in Hz (also input to UART) */ -#define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ +#define CFG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ /* * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): * Bits 0..5 set the lower 6 bits of the default ethernet MAC. * Bit 6 is reserved for future use by Tensilica. - * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to + * Bit 7 maps the first 128KB of ROM address space at CFG_SYS_ROM_BASE to * the base of flash * (when on/1) or to the base of RAM (when off/0). */ -#define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) +#define CFG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ #define FPGAREG_MAC_WIDTH 6 #define FPGAREG_MAC_MASK 0x3f @@ -120,8 +120,8 @@ #define FPGAREG_BOOT_FLASH (1<cspr_cs[i].cspr_ext)) diff --git a/include/i2c.h b/include/i2c.h index c07e60b04bd..51390f8fd84 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -633,10 +633,10 @@ void i2c_early_init_f(void); */ #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ -#if !defined(CONFIG_SYS_I2C_MAX_HOPS) +#if !defined(CFG_SYS_I2C_MAX_HOPS) /* no muxes used bus = i2c adapters */ #define CONFIG_SYS_I2C_DIRECT_BUS 1 -#define CONFIG_SYS_I2C_MAX_HOPS 0 +#define CFG_SYS_I2C_MAX_HOPS 0 #define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) #else /* we use i2c muxes */ @@ -644,8 +644,8 @@ void i2c_early_init_f(void); #endif /* define the I2C bus number for RTC and DTT if not already done */ -#if !defined(CONFIG_SYS_RTC_BUS_NUM) -#define CONFIG_SYS_RTC_BUS_NUM 0 +#if !defined(CFG_SYS_RTC_BUS_NUM) +#define CFG_SYS_RTC_BUS_NUM 0 #endif struct i2c_adapter { @@ -705,7 +705,7 @@ struct i2c_next_hop { struct i2c_bus_hose { int adapter; - struct i2c_next_hop next_hop[CONFIG_SYS_I2C_MAX_HOPS]; + struct i2c_next_hop next_hop[CFG_SYS_I2C_MAX_HOPS]; }; #define I2C_NULL_HOP {{-1, ""}, 0, 0} extern struct i2c_bus_hose i2c_bus[]; @@ -931,12 +931,12 @@ unsigned int i2c_get_bus_speed(void); * completely to new multibus support. */ #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) -# if !defined(CONFIG_SYS_MAX_I2C_BUS) -# define CONFIG_SYS_MAX_I2C_BUS 2 +# if !defined(CFG_SYS_MAX_I2C_BUS) +# define CFG_SYS_MAX_I2C_BUS 2 # endif # define I2C_MULTI_BUS 1 #else -# define CONFIG_SYS_MAX_I2C_BUS 1 +# define CFG_SYS_MAX_I2C_BUS 1 # define I2C_MULTI_BUS 0 #endif diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 053b68a10a4..636734dd3c6 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -26,38 +26,38 @@ * Define default values for some CCSR macros to make header files cleaner* * * To completely disable CCSR relocation in a board header file, define - * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS - * to a value that is the same as CONFIG_SYS_CCSRBAR. + * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CFG_SYS_CCSRBAR_PHYS + * to a value that is the same as CFG_SYS_CCSRBAR. */ -#ifdef CONFIG_SYS_CCSRBAR_PHYS -#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ -CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." +#ifdef CFG_SYS_CCSRBAR_PHYS +#error "Do not define CFG_SYS_CCSRBAR_PHYS directly. Use \ +CFG_SYS_CCSRBAR_PHYS_LOW and/or CFG_SYS_CCSRBAR_PHYS_HIGH instead." #endif #if CONFIG_IS_ENABLED(SYS_CCSR_DO_NOT_RELOCATE) -#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH -#undef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#undef CFG_SYS_CCSRBAR_PHYS_HIGH +#undef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif -#ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#ifndef CFG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf #else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT +#ifndef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT #endif -#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ - CONFIG_SYS_CCSRBAR_PHYS_LOW) +#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CFG_SYS_CCSRBAR_PHYS_LOW) #endif /* __MPC85xx_H__ */ diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 9fe47480325..ea8d17d557e 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -16,9 +16,9 @@ * platform register addresses */ -#define GUTS_SVR (CONFIG_SYS_CCSRBAR + 0xE00A4) -#define MCM_ABCR (CONFIG_SYS_CCSRBAR + 0x01000) -#define MCM_DBCR (CONFIG_SYS_CCSRBAR + 0x01008) +#define GUTS_SVR (CFG_SYS_CCSRBAR + 0xE00A4) +#define MCM_ABCR (CFG_SYS_CCSRBAR + 0x01000) +#define MCM_DBCR (CFG_SYS_CCSRBAR + 0x01008) /* * l2cr values. Look in config_.h for the actual setup diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h index 1321da19102..52cd1c4dbc4 100644 --- a/include/mtd/cfi_flash.h +++ b/include/mtd/cfi_flash.h @@ -147,8 +147,8 @@ struct cfi_pri_hdr { u8 minor_version; } __attribute__((packed)); -#ifndef CONFIG_SYS_FLASH_BANKS_LIST -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#ifndef CFG_SYS_FLASH_BANKS_LIST +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif /* diff --git a/include/mvebu_mmc.h b/include/mvebu_mmc.h index e75c3fa3289..0f6f5c23dee 100644 --- a/include/mvebu_mmc.h +++ b/include/mvebu_mmc.h @@ -21,7 +21,7 @@ #define MVEBU_MMC_CLOCKRATE_MAX 50000000 #define MVEBU_MMC_BASE_DIV_MAX 0x7ff -#define MVEBU_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK +#define MVEBU_MMC_BASE_FAST_CLOCK CFG_SYS_TCLK #define MVEBU_MMC_BASE_FAST_CLK_100 100000000 #define MVEBU_MMC_BASE_FAST_CLK_200 200000000 diff --git a/include/post.h b/include/post.h index ec03556e917..867a66f3007 100644 --- a/include/post.h +++ b/include/post.h @@ -142,7 +142,7 @@ extern int memory_post_test(int flags); #define CONFIG_SYS_POST_RTC 0x00000001 #define CONFIG_SYS_POST_WATCHDOG 0x00000002 -#define CONFIG_SYS_POST_MEMORY 0x00000004 +#define CFG_SYS_POST_MEMORY 0x00000004 #define CONFIG_SYS_POST_CPU 0x00000008 #define CONFIG_SYS_POST_I2C 0x00000010 #define CONFIG_SYS_POST_CACHE 0x00000020 @@ -163,7 +163,7 @@ extern int memory_post_test(int flags); #define CONFIG_SYS_POST_CODEC 0x00200000 #define CONFIG_SYS_POST_COPROC 0x00400000 #define CONFIG_SYS_POST_FLASH 0x00800000 -#define CONFIG_SYS_POST_MEM_REGIONS 0x01000000 +#define CFG_SYS_POST_MEM_REGIONS 0x01000000 #endif /* CONFIG_POST */ diff --git a/include/spl.h b/include/spl.h index 3eb27de6166..fb8c279d726 100644 --- a/include/spl.h +++ b/include/spl.h @@ -470,7 +470,7 @@ void spl_set_bd(void); * spl_set_header_raw_uboot() - Set up a standard SPL image structure * * This sets up the given spl_image which the standard values obtained from - * config options: CONFIG_SYS_MONITOR_LEN, CONFIG_SYS_UBOOT_START, + * config options: CONFIG_SYS_MONITOR_LEN, CFG_SYS_UBOOT_START, * CONFIG_TEXT_BASE. * * @spl_image: Image description to set up diff --git a/include/system-constants.h b/include/system-constants.h index 07c3505e8f5..0d6b71b35a0 100644 --- a/include/system-constants.h +++ b/include/system-constants.h @@ -12,10 +12,10 @@ #define SYS_INIT_SP_ADDR CONFIG_CUSTOM_SYS_INIT_SP_ADDR #else #ifdef CONFIG_MIPS -#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET) +#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CFG_SYS_INIT_SP_OFFSET) #else #define SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #endif #endif diff --git a/include/tca642x.h b/include/tca642x.h index bda86c1ed88..c0a3cef5bd5 100644 --- a/include/tca642x.h +++ b/include/tca642x.h @@ -41,13 +41,13 @@ enum { #define TCA642X_DIR_IN 1 /* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CONFIG_SYS_I2C_TCA642X_ADDR -#define CONFIG_SYS_I2C_TCA642X_ADDR (~0) +#ifndef CFG_SYS_I2C_TCA642X_ADDR +#define CFG_SYS_I2C_TCA642X_ADDR (~0) #endif /* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CONFIG_SYS_I2C_TCA642X_BUS_NUM -#define CONFIG_SYS_I2C_TCA642X_BUS_NUM (0) +#ifndef CFG_SYS_I2C_TCA642X_BUS_NUM +#define CFG_SYS_I2C_TCA642X_BUS_NUM (0) #endif struct tca642x_bank_info { diff --git a/include/tsec.h b/include/tsec.h index 72f34851ad1..de279b21171 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -124,8 +124,8 @@ #define RCTRL_PROM 0x00000008 -#ifndef CONFIG_SYS_TBIPA_VALUE -# define CONFIG_SYS_TBIPA_VALUE 0x1f +#ifndef CFG_SYS_TBIPA_VALUE +# define CFG_SYS_TBIPA_VALUE 0x1f #endif #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN diff --git a/lib/time.c b/lib/time.c index f3aaf472d10..82350260eac 100644 --- a/lib/time.c +++ b/lib/time.c @@ -25,21 +25,21 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SYS_TIMER_RATE +#ifdef CFG_SYS_TIMER_RATE /* Returns tick rate in ticks per second */ ulong notrace get_tbclk(void) { - return CONFIG_SYS_TIMER_RATE; + return CFG_SYS_TIMER_RATE; } #endif -#ifdef CONFIG_SYS_TIMER_COUNTER +#ifdef CFG_SYS_TIMER_COUNTER unsigned long notrace timer_read_counter(void) { #ifdef CONFIG_SYS_TIMER_COUNTS_DOWN - return ~readl(CONFIG_SYS_TIMER_COUNTER); + return ~readl(CFG_SYS_TIMER_COUNTER); #else - return readl(CONFIG_SYS_TIMER_COUNTER); + return readl(CFG_SYS_TIMER_COUNTER); #endif } @@ -47,8 +47,8 @@ ulong timer_get_boot_us(void) { ulong count = timer_read_counter(); -#ifdef CONFIG_SYS_TIMER_RATE - const ulong timer_rate = CONFIG_SYS_TIMER_RATE; +#ifdef CFG_SYS_TIMER_RATE + const ulong timer_rate = CFG_SYS_TIMER_RATE; if (timer_rate == 1000000) return count; diff --git a/post/drivers/memory.c b/post/drivers/memory.c index 8deac75ebb0..71dad7b8c02 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -138,7 +138,7 @@ #include #include -#if CONFIG_POST & (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_MEM_REGIONS) +#if CONFIG_POST & (CFG_SYS_POST_MEMORY | CFG_SYS_POST_MEM_REGIONS) DECLARE_GLOBAL_DATA_PTR; @@ -535,4 +535,4 @@ int memory_post_test(int flags) return ret; } -#endif /* CONFIG_POST&(CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) */ +#endif /* CONFIG_POST&(CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) */ diff --git a/post/tests.c b/post/tests.c index 5c019b643df..fc36e738f73 100644 --- a/post/tests.c +++ b/post/tests.c @@ -109,7 +109,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_RTC }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_MEMORY +#if CONFIG_POST & CFG_SYS_POST_MEMORY { "Memory test", "memory", @@ -118,7 +118,7 @@ struct post_test post_list[] = &memory_post_test, NULL, NULL, - CONFIG_SYS_POST_MEMORY + CFG_SYS_POST_MEMORY }, #endif #if CONFIG_POST & CONFIG_SYS_POST_CPU @@ -286,7 +286,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_FLASH }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_MEM_REGIONS +#if CONFIG_POST & CFG_SYS_POST_MEM_REGIONS { "Memory regions test", "mem_regions", @@ -295,7 +295,7 @@ struct post_test post_list[] = &memory_regions_post_test, NULL, NULL, - CONFIG_SYS_POST_MEM_REGIONS + CFG_SYS_POST_MEM_REGIONS }, #endif }; diff --git a/tools/envcrc.c b/tools/envcrc.c index bce77902476..a021c785aee 100644 --- a/tools/envcrc.c +++ b/tools/envcrc.c @@ -23,13 +23,13 @@ #if defined(CONFIG_ENV_IS_IN_FLASH) # ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +# define CONFIG_ENV_ADDR (CFG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif # ifndef CONFIG_ENV_OFFSET -# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) +# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CFG_SYS_FLASH_BASE) # endif # if !defined(CONFIG_ENV_ADDR_REDUND) && defined(CONFIG_ENV_OFFSET_REDUND) -# define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND) +# define CONFIG_ENV_ADDR_REDUND (CFG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND) # endif # ifndef CONFIG_ENV_SIZE # define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -- cgit v1.3.1 From 2a776c79dbfadeac094cd420d2d7b22937aac0c9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:09 -0500 Subject: Convert CONFIG_FSL_CADMUS to Kconfig This converts the following to Kconfig: CONFIG_FSL_CADMUS Signed-off-by: Tom Rini --- board/freescale/mpc8548cds/Kconfig | 3 +++ include/configs/MPC8548CDS.h | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/freescale/mpc8548cds/Kconfig b/board/freescale/mpc8548cds/Kconfig index bd9153bc0d7..723ead51e5c 100644 --- a/board/freescale/mpc8548cds/Kconfig +++ b/board/freescale/mpc8548cds/Kconfig @@ -3,6 +3,9 @@ if TARGET_MPC8548CDS config PCI1 def_bool y +config FSL_CADMUS + def_bool y + config SYS_BOARD default "mpc8548cds" diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index ff02c2cd847..e41b8e0843a 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -217,8 +217,6 @@ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 */ -#define CONFIG_FSL_CADMUS - #define CADMUS_BASE_ADDR 0xf8000000 #ifdef CONFIG_PHYS_64BIT #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull -- cgit v1.3.1 From 345c09de5e7ca2c015faaf58c1e6c6b15883a63b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:10 -0500 Subject: Convert CONFIG_FSL_DEVICE_DISABLE to Kconfig This converts the following to Kconfig: CONFIG_FSL_DEVICE_DISABLE Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ++++ include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/ls1021aiot.h | 2 -- include/configs/ls1021aqds.h | 2 -- include/configs/ls1021atsn.h | 2 -- include/configs/ls1021atwr.h | 2 -- 6 files changed, 4 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index e75a895e008..369e68b8193 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -1,5 +1,6 @@ config ARCH_LS1021A bool + select FSL_DEVICE_DISABLE select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI select SYS_FSL_DDR_BE if SYS_FSL_DDR select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR @@ -30,6 +31,9 @@ config ARCH_LS1021A menu "LS102xA architecture" depends on ARCH_LS1021A +config FSL_DEVICE_DISABLE + bool + config LS1_DEEP_SLEEP bool "Deep sleep" diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 7307c495c38..6ccb4f07e3b 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -168,7 +168,6 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE /* * Miscellaneous configurable options diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index b058308ecdb..3063635592e 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -95,8 +95,6 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE - #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5494b71e2b2..137d459c291 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -279,8 +279,6 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE - #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index bc9eac700e9..052a15658d7 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -70,8 +70,6 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index f1ccb5fc084..f39c7c08844 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -160,8 +160,6 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ -- cgit v1.3.1 From 060613f119837fafc7c90a5dcc1aa1bf81ff319b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:11 -0500 Subject: Convert CONFIG_FSL_IIM to Kconfig This converts the following to Kconfig: CONFIG_FSL_IIM Signed-off-by: Tom Rini --- configs/m53menlo_defconfig | 1 + configs/mx51evk_defconfig | 1 + configs/mx53ppd_defconfig | 1 + configs/usbarmory_defconfig | 1 + doc/README.fsl_iim | 2 +- drivers/misc/Kconfig | 4 ++++ include/configs/m53menlo.h | 3 --- include/configs/mx51evk.h | 1 - include/configs/mx53ppd.h | 2 -- include/configs/usbarmory.h | 3 --- 10 files changed, 9 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index b4ada56a36b..a5760242be5 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -80,6 +80,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y +CONFIG_FSL_IIM=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index 89597c05748..d76ebe8fd22 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -40,6 +40,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC0" CONFIG_ARP_TIMEOUT=200 +CONFIG_FSL_IIM=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_PHYLIB=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 328f546c5b3..ed4ebbbe3c2 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -52,6 +52,7 @@ CONFIG_SYS_I2C_MXC=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y +CONFIG_FSL_IIM=y CONFIG_I2C_EEPROM=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index 510e215bff3..ed2bcc69fc5 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -29,6 +29,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y +CONFIG_FSL_IIM=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_PINCTRL=y diff --git a/doc/README.fsl_iim b/doc/README.fsl_iim index e087f5e0e4f..78d3cb8b3ef 100644 --- a/doc/README.fsl_iim +++ b/doc/README.fsl_iim @@ -45,4 +45,4 @@ Fuse operations: Configuration: CONFIG_FSL_IIM - Define this to enable the fsl_iim driver. + Enable this to enable the fsl_iim driver. diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index a6da6e215de..fb3bbb3b919 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -267,6 +267,10 @@ config DS4510 and a configurable timer for the supervisor function. The device is connected over I2C. +config FSL_IIM + bool "Enable FSL IC Identification Module (IIM) driver" + depends on ARCH_MX31 || ARCH_MX5 + config FSL_SEC_MON bool "Enable FSL SEC_MON Driver" help diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index f87bbf7ccf3..eca86a94519 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -80,9 +80,6 @@ #define CFG_SYS_LDB_CLOCK 33260000 #define CONFIG_IMX_VIDEO_SKIP -/* IIM Fuses */ -#define CONFIG_FSL_IIM - /* Watchdog */ /* diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 3c99b70a2bb..6d9b954587e 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -17,7 +17,6 @@ /* * Hardware drivers */ -#define CONFIG_FSL_IIM #define CONFIG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 7160654eb30..913bc1996d4 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -102,8 +102,6 @@ /* FLASH and environment organization */ -#define CONFIG_FSL_IIM - /* Backlight Control */ #define CONFIG_IMX6_PWM_PER_CLK 66666000 diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index da68d7a0da9..a2bc3cd23a5 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -27,9 +27,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Fuse */ -#define CONFIG_FSL_IIM - /* Linux boot */ #define CONFIG_HOSTNAME "usbarmory" -- cgit v1.3.1 From 5cafaedeac41c966b8f554182944d9dc0b531190 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:13 -0500 Subject: Convert CONFIG_FSL_SERDES to Kconfig This converts the following to Kconfig: CONFIG_FSL_SERDES Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc83xx/Kconfig | 4 ++++ arch/powerpc/cpu/mpc83xx/serdes.c | 4 ---- configs/MPC837XERDB_defconfig | 1 + include/configs/MPC837XERDB.h | 1 - 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index ec3405e9678..563f52c5fdb 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -196,6 +196,10 @@ config 83XX_PCICLK config FSL_ELBC bool +config FSL_SERDES + bool "SerDes initialization" + depends on !MPC83XX_SERDES + source "board/freescale/mpc837xerdb/Kconfig" source "board/gdsys/mpc8308/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c index bb963ee5e2f..d4848b2ec4d 100644 --- a/arch/powerpc/cpu/mpc83xx/serdes.c +++ b/arch/powerpc/cpu/mpc83xx/serdes.c @@ -8,8 +8,6 @@ * Author: Li Yang */ -#ifndef CONFIG_MPC83XX_SERDES - #include #include #include @@ -151,5 +149,3 @@ void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) tmp |= FSL_SRDSRSTCTL_RST; out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); } - -#endif /* !CONFIG_MPC83XX_SERDES */ diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 7054333d737..e6289fe104d 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -147,6 +147,7 @@ CONFIG_ACR_RPTCNT_4=y CONFIG_SPCR_TSECEP_3=y CONFIG_LCRR_DBYP_PLL_BYPASSED=y CONFIG_LCRR_CLKDIV_8=y +CONFIG_FSL_SERDES=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 85c080cf27a..717320c34ae 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -160,7 +160,6 @@ #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) /* SERDES */ -#define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000 #define CONFIG_FSL_SERDES2 0xe3100 -- cgit v1.3.1 From 022dc9e505ea70ea5e5c81f78a629a6016d4fd9d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:14 -0500 Subject: Convert CONFIG_HIKEY_GPIO et al to Kconfig This converts the following to Kconfig: CONFIG_HIKEY_GPIO CONFIG_TCA642X Signed-off-by: Tom Rini --- configs/hikey_defconfig | 1 + configs/omap5_uevm_defconfig | 2 +- drivers/gpio/Kconfig | 9 +++++++++ include/configs/hikey.h | 2 -- include/configs/omap5_uevm.h | 1 - 5 files changed, 11 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index 9eec9281849..d023653815c 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -30,6 +30,7 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_HIKEY_GPIO=y CONFIG_MMC_DW=y CONFIG_MMC_DW_K3=y CONFIG_POWER_LEGACY=y diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index d12199766ad..91878c11ed4 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -47,7 +47,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SCSI_AHCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y -CONFIG_CMD_TCA642X=y +CONFIG_TCA642X=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index ff87fbfb397..e007b38fac7 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -169,6 +169,10 @@ config FXL6408_GPIO This driver supports the Fairchild FXL6408 device. FXL6408 is a fully configurable 8-bit I2C-controlled GPIO expander. +config HIKEY_GPIO + bool "HI6220 GPIO driver" + depends on DM_GPIO + config INTEL_BROADWELL_GPIO bool "Intel Broadwell GPIO driver" depends on DM @@ -374,8 +378,13 @@ config XILINX_GPIO help This config enable the Xilinx GPIO driver for Microblaze. +config TCA642X + bool "TCA642x legacy GPIO driver" + config CMD_TCA642X bool "tca642x - Command to access tca642x state" + depends on TCA642X + default y help DEPRECATED - This needs conversion to driver model diff --git a/include/configs/hikey.h b/include/configs/hikey.h index c5ef2f99b0f..eefdbd6ed11 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -32,8 +32,6 @@ #define GICD_BASE 0xf6801000 #define GICC_BASE 0xf6802000 -#define CONFIG_HIKEY_GPIO - /* Initial environment variables */ /* diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 1634db86064..d7fa2d43914 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -36,7 +36,6 @@ #define CONFIG_HSMMC2_8BIT /* Required support for the TCA642X GPIO we have on the uEVM */ -#define CONFIG_TCA642X #define CFG_SYS_I2C_TCA642X_BUS_NUM 4 #define CFG_SYS_I2C_TCA642X_ADDR 0x22 -- cgit v1.3.1 From d9feb83505b3a7c06487a1748db4f20ad189e33a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:15 -0500 Subject: Convert CONFIG_POWER_LTC3676 et al to Kconfig This converts the following to Kconfig: CONFIG_POWER_FSL CONFIG_POWER_FSL_MC13892 CONFIG_POWER_HI6553 CONFIG_POWER_LTC3676 CONFIG_POWER_PFUZE100 CONFIG_POWER_PFUZE3000 CONFIG_POWER_SPI CONFIG_POWER_TPS65090_EC CONFIG_POWER_TPS65218 CONFIG_POWER_TPS65910 Signed-off-by: Tom Rini --- board/freescale/common/Makefile | 2 ++ configs/am335x_baltos_defconfig | 1 + configs/am335x_boneblack_vboot_defconfig | 1 + configs/am335x_evm_defconfig | 1 + configs/am335x_evm_spiboot_defconfig | 1 + configs/am335x_hs_evm_defconfig | 1 + configs/am335x_hs_evm_uart_defconfig | 1 + configs/am335x_sl50_defconfig | 1 + configs/am43xx_evm_defconfig | 2 ++ configs/am43xx_evm_qspiboot_defconfig | 2 ++ configs/am43xx_evm_rtconly_defconfig | 2 ++ configs/am43xx_evm_usbhost_boot_defconfig | 2 ++ configs/am43xx_hs_evm_defconfig | 2 ++ configs/am43xx_hs_evm_qspi_defconfig | 2 ++ configs/cl-som-imx7_defconfig | 1 + configs/cm_t43_defconfig | 1 + configs/gwventana_emmc_defconfig | 2 ++ configs/gwventana_gw5904_defconfig | 2 ++ configs/gwventana_nand_defconfig | 2 ++ configs/hikey_defconfig | 1 + configs/imx8mq_evk_defconfig | 1 + configs/kontron_pitx_imx8m_defconfig | 1 + configs/mx51evk_defconfig | 2 ++ configs/mx53loco_defconfig | 1 + configs/mx6sabreauto_defconfig | 1 + configs/mx6sabresd_defconfig | 1 + configs/novena_defconfig | 1 + configs/pcm051_rev3_defconfig | 1 + configs/phycore-am335x-r2-regor_defconfig | 1 + configs/phycore-am335x-r2-wega_defconfig | 1 + configs/pico-dwarf-imx7d_defconfig | 1 + configs/pico-hobbit-imx7d_defconfig | 1 + configs/pico-imx7d_bl33_defconfig | 1 + configs/pico-imx7d_defconfig | 1 + configs/pico-nymph-imx7d_defconfig | 1 + configs/pico-pi-imx7d_defconfig | 1 + configs/udoo_neo_defconfig | 1 + configs/vining_2000_defconfig | 1 + drivers/power/Kconfig | 21 +++++++++++++++++++++ drivers/power/pmic/Kconfig | 27 +++++++++++++++++++++++++++ drivers/power/pmic/Makefile | 7 ++++--- drivers/power/power_fsl.c | 2 -- include/configs/am335x_evm.h | 3 --- include/configs/am335x_sl50.h | 7 ------- include/configs/am43xx_evm.h | 8 -------- include/configs/baltos.h | 3 --- include/configs/cl-som-imx7.h | 1 - include/configs/cm_t43.h | 3 --- include/configs/el6x_common.h | 1 - include/configs/gw_ventana.h | 2 -- include/configs/hikey.h | 2 -- include/configs/imx8mq_evk.h | 1 - include/configs/kontron_pitx_imx8m.h | 1 - include/configs/mx51evk.h | 2 -- include/configs/mx53loco.h | 2 -- include/configs/mx6sabreauto.h | 1 - include/configs/mx6sabresd.h | 1 - include/configs/novena.h | 1 - include/configs/peach-pi.h | 2 -- include/configs/phycore_am335x_r2.h | 2 -- include/configs/pico-imx7d.h | 1 - include/configs/tqma6.h | 1 - include/configs/udoo_neo.h | 1 - include/configs/vining_2000.h | 1 - 64 files changed, 101 insertions(+), 52 deletions(-) (limited to 'include') diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 377c6aa077d..cc1371867d8 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -61,7 +61,9 @@ obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o obj-$(CONFIG_ZM7300) += zm7300.o +ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y) obj-$(CONFIG_POWER_PFUZE100) += pfuze.o +endif obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o ifneq (,$(filter $(SOC), imx8ulp imx9)) diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index bd23b71b096..9976cee81fc 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -79,6 +79,7 @@ CONFIG_PHY_SMSC=y CONFIG_DM_MDIO=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index 66b7fb6e06d..442783a9d02 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -76,6 +76,7 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_PMIC=y # CONFIG_SPL_DM_PMIC is not set CONFIG_PMIC_TPS65217=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index f73123e0b71..78e63c91750 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -102,6 +102,7 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_PMIC=y # CONFIG_SPL_DM_PMIC is not set CONFIG_PMIC_TPS65217=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index 7f422010c1c..335a43d87b4 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -93,6 +93,7 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_PMIC=y # CONFIG_SPL_DM_PMIC is not set CONFIG_PMIC_TPS65217=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index 8d3a4548d9a..5dc9ba98fde 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -80,6 +80,7 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_PMIC=y # CONFIG_SPL_DM_PMIC is not set CONFIG_PMIC_TPS65217=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig index 7080b14c467..68513c1b6a9 100644 --- a/configs/am335x_hs_evm_uart_defconfig +++ b/configs/am335x_hs_evm_uart_defconfig @@ -81,6 +81,7 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_PMIC=y # CONFIG_SPL_DM_PMIC is not set CONFIG_PMIC_TPS65217=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 65b20550c0c..673824cfecf 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -75,6 +75,7 @@ CONFIG_PHY_SMSC=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y CONFIG_PMIC_TPS65217=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 2dfd936057f..2faf1322f9e 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -88,6 +88,8 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY=y CONFIG_SPL_PHY=y CONFIG_OMAP_USB2_PHY=y +CONFIG_POWER_TPS65218=y +CONFIG_POWER_TPS62362=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index fc6cad59cf4..9c90924020f 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -53,6 +53,8 @@ CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_POWER_TPS65218=y +CONFIG_POWER_TPS62362=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig index 357da192b83..4241070930f 100644 --- a/configs/am43xx_evm_rtconly_defconfig +++ b/configs/am43xx_evm_rtconly_defconfig @@ -72,6 +72,8 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_POWER_TPS65218=y +CONFIG_POWER_TPS62362=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 0e58221c820..91270d032bf 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -91,6 +91,8 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY=y CONFIG_SPL_PHY=y CONFIG_OMAP_USB2_PHY=y +CONFIG_POWER_TPS65218=y +CONFIG_POWER_TPS62362=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 2b5a7fb2599..b6b74af735e 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -86,6 +86,8 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY=y CONFIG_SPL_PHY=y CONFIG_OMAP_USB2_PHY=y +CONFIG_POWER_TPS65218=y +CONFIG_POWER_TPS62362=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig index 08cac404c6e..03e46dde0f2 100644 --- a/configs/am43xx_hs_evm_qspi_defconfig +++ b/configs/am43xx_hs_evm_qspi_defconfig @@ -55,6 +55,8 @@ CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_POWER_TPS65218=y +CONFIG_POWER_TPS62362=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index f3ee559d21f..3571dba6d2a 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -95,6 +95,7 @@ CONFIG_PHY_ATHEROS=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_DM_REGULATOR=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 0a5ce2046f1..867ca303205 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -95,6 +95,7 @@ CONFIG_PHY_ATHEROS=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_TPS65218=y CONFIG_POWER_I2C=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index cabe09e6d38..ce81b558ee2 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -119,6 +119,8 @@ CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_LTC3676=y +CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_POWER_I2C=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index f58abd9c5e5..3ef909a1ce3 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -123,6 +123,8 @@ CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_LTC3676=y +CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_POWER_I2C=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index a41b3c4c97e..d3d4876658a 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -129,6 +129,8 @@ CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_LTC3676=y +CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_POWER_I2C=y diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index d023653815c..152459ece8d 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -34,6 +34,7 @@ CONFIG_HIKEY_GPIO=y CONFIG_MMC_DW=y CONFIG_MMC_DW_K3=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_HI6553=y CONFIG_CONS_INDEX=4 CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 274cdb948d7..79a27dedb37 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -88,6 +88,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig index d2726b1c200..898a0b45e85 100644 --- a/configs/kontron_pitx_imx8m_defconfig +++ b/configs/kontron_pitx_imx8m_defconfig @@ -95,6 +95,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index d76ebe8fd22..774523bc84b 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -54,6 +54,8 @@ CONFIG_POWER_LEGACY=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_POWER_FSL=y +CONFIG_POWER_SPI=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index 193120f71a4..08bcd35f073 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -58,6 +58,7 @@ CONFIG_POWER_LEGACY=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_POWER_FSL=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_USB=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 2aa15ce8c65..634473f3074 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -95,6 +95,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 766ce0edc45..4f7d3704203 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -102,6 +102,7 @@ CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_POWER_I2C=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index f6690b4ac85..5f761799a21 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -79,6 +79,7 @@ CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE100=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index 373c609d214..3ed55916d23 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -56,6 +56,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_SMSC=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig index b6b5274f03e..1b316765685 100644 --- a/configs/phycore-am335x-r2-regor_defconfig +++ b/configs/phycore-am335x-r2-regor_defconfig @@ -83,6 +83,7 @@ CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 CONFIG_DM_SPI_FLASH=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig index 5012049fed9..c5ffb412747 100644 --- a/configs/phycore-am335x-r2-wega_defconfig +++ b/configs/phycore-am335x-r2-wega_defconfig @@ -84,6 +84,7 @@ CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000 CONFIG_DM_SPI_FLASH=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 821357827a7..46777e04fdb 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -81,6 +81,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 759866ce119..fb354d1cdee 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -81,6 +81,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 8631f81f333..35e6f1d5493 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -77,6 +77,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_CONS_INDEX=4 CONFIG_MXC_UART=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index a84954d22fd..13cc97bb73c 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -81,6 +81,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 821357827a7..46777e04fdb 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -81,6 +81,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index dec42809747..6e92366beff 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -81,6 +81,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 95428e19935..f62a585b1c3 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -57,6 +57,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_ANATOP=y diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 3b5658ddc89..7f84209b655 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -89,6 +89,7 @@ CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE100=y CONFIG_POWER_I2C=y CONFIG_PWM_IMX=y CONFIG_DM_SERIAL=y diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index bc47cf144dd..5dbcde333ba 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -430,6 +430,10 @@ config PALMAS_POWER bool "Palmas power support" depends on OMAP54XX +config POWER_FSL + bool "Power control (legacy) for Freescale / NXP platforms" + depends on POWER_LEGACY + config POWER_I2C bool "I2C-based power control for legacy power" depends on POWER_LEGACY @@ -440,6 +444,10 @@ config POWER_I2C Not to be used for new designs and existing ones should be moved to the new PMIC interface based on driver model. +config POWER_SPI + bool "SPI-based power control for legacy power_fsl driver" + depends on POWER_FSL && !POWER_I2C + config SPL_POWER_I2C bool "I2C-based power control for legacy power" depends on SPL_POWER_LEGACY @@ -451,4 +459,17 @@ config SPL_POWER_I2C Not to be used for new designs and existing ones should be moved to the new PMIC interface based on driver model. +choice + prompt "PMIC chip" + default POWER_FSL_MC13892 + depends on POWER_FSL && POWER_I2C + +config POWER_FSL_MC13892 + bool "MC13892" + +config POWER_FSL_MC34704 + bool "MC34704" + +endchoice + endif diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index d30bb4d4e9c..d94048db5f7 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -393,8 +393,35 @@ config PMIC_TPS65217 only, and you can enable the regulator/charger drivers separately if required. +config POWER_TPS65218 + bool "Enable legacy driver for TPS65218 PMIC" + +config POWER_TPS62362 + bool "Enable legacy driver for TPS62362 PMIC" + +config SPL_POWER_TPS62362 + bool "Enable legacy driver for TPS62362 PMIC in SPL" + default y if POWER_TPS62362 + depends on SPL + +config SPL_POWER_TPS65910 + bool "Enable legacy driver for TPS65910 PMIC in SPL" + depends on SPL + if POWER_LEGACY || SPL_POWER_LEGACY +config POWER_HI6553 + bool "Enable legacy driver for HI6553 PMIC" + +config POWER_LTC3676 + bool "Enable legacy driver for LTC3676 PMIC" + +config POWER_PFUZE100 + bool "Enable legacy driver for PFUZE100 PMIC" + +config POWER_PFUZE3000 + bool "Enable legacy driver for PFUZE3000 PMIC" + config POWER_MC34VR500 bool "Enable driver for Freescale MC34VR500 PMIC" ---help--- diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index e78dc1e2053..c3180c58208 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o obj-$(CONFIG_PMIC_TPS65219) += tps65219.o obj-$(CONFIG_PMIC_TPS65941) += tps65941.o +obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y) obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o @@ -40,9 +41,9 @@ obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o -obj-$(CONFIG_POWER_TPS62362) += pmic_tps62362.o -obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o -obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o obj-$(CONFIG_POWER_HI6553) += pmic_hi6553.o obj-$(CONFIG_POWER_MC34VR500) += pmic_mc34vr500.o endif + +obj-$(CONFIG_$(SPL_)POWER_TPS62362) += pmic_tps62362.o +obj-$(CONFIG_SPL_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index 7180b5127a5..9bb7e39f2cc 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -49,8 +49,6 @@ int pmic_init(unsigned char bus) p->interface = PMIC_I2C; p->hw.i2c.addr = CFG_SYS_FSL_PMIC_I2C_ADDR; p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH; -#else -#error "You must select CONFIG_POWER_SPI or CONFIG_POWER_I2C" #endif return 0; diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 69b8b048ce3..755f7fae3e4 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -165,9 +165,6 @@ #define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -/* PMIC support */ -#define CONFIG_POWER_TPS65910 - #ifdef CONFIG_MTD_RAW_NAND /* NAND: device related configs */ /* NAND: driver related configs */ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index 4af9edafca8..342a068c855 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -43,11 +43,4 @@ #define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -/* PMIC support */ -#define CONFIG_POWER_TPS65910 - -/* SPL */ - -/* Network. */ - #endif /* ! __CONFIG_AM335X_SL50_H */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index bcdff2e98ac..7659c1cc061 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -16,14 +16,6 @@ /* NS16550 Configuration */ #define CFG_SYS_NS16550_CLK 48000000 -/* I2C Configuration */ - -/* Power */ -#define CONFIG_POWER_TPS65218 -#define CONFIG_POWER_TPS62362 - -/* SPL defines. */ - /* Enabling L2 Cache */ #define CFG_SYS_PL310_BASE 0x48242000 diff --git a/include/configs/baltos.h b/include/configs/baltos.h index f29729d09ba..6f6552e6dc3 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -188,9 +188,6 @@ #define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -/* PMIC support */ -#define CONFIG_POWER_TPS65910 - /* SPL */ #ifndef CONFIG_NOR_BOOT diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index b1f9470d9ca..4aaa52f2698 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -19,7 +19,6 @@ #define IMX_FEC_BASE ENET_IPS_BASE_ADDR /* PMIC */ -#define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 #define CONFIG_PCA953X diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 8ad1cfb5ded..fcc17fc6b7c 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -28,9 +28,6 @@ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -/* Power */ -#define CONFIG_POWER_TPS65218 - /* Enabling L2 Cache */ #define CFG_SYS_PL310_BASE 0x48242000 diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index 141f9913e63..89e071c0df6 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -17,7 +17,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* Commands */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index b855bbc25fb..65283afd2a0 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -30,9 +30,7 @@ /* * PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 -#define CONFIG_POWER_LTC3676 #define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c /* Various command support */ diff --git a/include/configs/hikey.h b/include/configs/hikey.h index eefdbd6ed11..d4280decc9f 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -13,8 +13,6 @@ #include -#define CONFIG_POWER_HI6553 - /* Physical Memory Map */ /* CONFIG_TEXT_BASE needs to align with where ATF loads bl33.bin */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index aa29e7884f9..688c0bf7008 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -18,7 +18,6 @@ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 2abcb849a28..17c63d83410 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -20,7 +20,6 @@ /* For RAW image gives a error info not panic */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 6d9b954587e..d9d76d7c08d 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -21,8 +21,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* PMIC Controller */ -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL #define CONFIG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 2500000 diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index b52e70c95a0..d0107fcc8cb 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -22,8 +22,6 @@ #define CONFIG_MXC_USB_FLAGS 0 /* PMIC Controller */ -#define CONFIG_POWER_FSL -#define CONFIG_POWER_FSL_MC13892 #define CFG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 #define CFG_SYS_FSL_PMIC_I2C_ADDR 0x8 diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 1a2160cce59..f5f95a1bd1c 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -37,7 +37,6 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif /* __MX6SABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 0d06b6dc467..78a554d0ccb 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -25,7 +25,6 @@ #endif /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* USB Configs */ diff --git a/include/configs/novena.h b/include/configs/novena.h index 6f588f99c34..16a89b97b06 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -50,7 +50,6 @@ #endif /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* UART */ diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index bfc0011fbf9..fb6eb572cfa 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -22,8 +22,6 @@ #define CFG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_POWER_TPS65090_EC - /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index 43a60825b57..f922491637d 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -79,8 +79,6 @@ #define V_OSCK 25000000 /* Clock output from T2 */ #define V_SCLK V_OSCK -#define CONFIG_POWER_TPS65910 - #ifdef CONFIG_MTD_RAW_NAND /* NAND: device related configs */ /* NAND: driver related configs */ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 7028264d722..83907b06ebb 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -98,7 +98,6 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* PMIC */ -#define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 /* FLASH and environment organization */ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 9c3454add46..7a1ad9544a3 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -31,7 +31,6 @@ #define CONFIG_I2C_MULTI_BUS #if !defined(CONFIG_DM_PMIC) -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #define TQMA6_PFUZE100_I2C_BUS 2 #endif diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 0e0d5b5b3e4..d4c92233aca 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -62,7 +62,6 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* PMIC */ -#define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 #define PFUZE3000_I2C_BUS 0 diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index ab5cd5cf636..1a71b300fc5 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -31,7 +31,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* Network */ -- cgit v1.3.1 From 19b4040df03813ffeb3af77d4f44b1b08013bf77 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:16 -0500 Subject: Convert CONFIG_HWCONFIG to Kconfig This converts the following to Kconfig: CONFIG_HWCONFIG Signed-off-by: Tom Rini --- common/Kconfig | 4 ++++ configs/MCR3000_defconfig | 1 + configs/da850evm_defconfig | 1 + configs/da850evm_direct_nor_defconfig | 1 + configs/da850evm_nand_defconfig | 1 + configs/gazerbeam_defconfig | 1 + configs/gwventana_emmc_defconfig | 1 + configs/gwventana_gw5904_defconfig | 1 + configs/gwventana_nand_defconfig | 1 + configs/kmcoge5ne_defconfig | 1 + configs/kmeter1_defconfig | 1 + configs/kmopti2_defconfig | 1 + configs/kmsupx5_defconfig | 1 + configs/kmtepr2_defconfig | 1 + configs/kontron_sl28_defconfig | 1 + configs/legoev3_defconfig | 1 + configs/socrates_defconfig | 1 + configs/tuge1_defconfig | 1 + configs/tuxx1_defconfig | 1 + doc/README.hwconfig | 3 --- include/configs/MPC837XERDB.h | 2 -- include/configs/MPC8548CDS.h | 2 -- include/configs/P1010RDB.h | 1 - include/configs/P2041RDB.h | 2 -- include/configs/T102xRDB.h | 2 -- include/configs/T104xRDB.h | 2 -- include/configs/T208xQDS.h | 2 -- include/configs/T208xRDB.h | 2 -- include/configs/T4240RDB.h | 2 -- include/configs/da850evm.h | 1 - include/configs/gw_ventana.h | 1 - include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/kmcent2.h | 2 -- include/configs/legoev3.h | 1 - include/configs/ls1012a_common.h | 1 - include/configs/ls1021aiot.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atsn.h | 1 - include/configs/ls1021atwr.h | 1 - include/configs/ls1028a_common.h | 1 - include/configs/ls1043a_common.h | 1 - include/configs/ls1046a_common.h | 1 - include/configs/ls1088a_common.h | 1 - include/configs/ls2080a_common.h | 1 - include/configs/lx2160a_common.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/qemu-ppce500.h | 2 -- 47 files changed, 22 insertions(+), 40 deletions(-) (limited to 'include') diff --git a/common/Kconfig b/common/Kconfig index 21434c5cf16..053e93eb1ab 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -676,6 +676,10 @@ config CLOCKS bool "Call set_cpu_clk_info" depends on ARM +config HWCONFIG + bool "hwconfig infrastructure" + default y if PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 + config SYS_FSL_CLK bool depends on ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 || \ diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index 6c41d7c88d1..d8d6417d21e 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -29,6 +29,7 @@ CONFIG_AUTOBOOT_DELAY_STR="root" CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run flashboot" CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index ec80edf293a..9b1b6198178 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -35,6 +35,7 @@ CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y +CONFIG_HWCONFIG=y CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 01cdc4f7843..9332c8cb3ff 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -29,6 +29,7 @@ CONFIG_BOOTCOMMAND="run envboot; run mmcboot; " # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y +CONFIG_HWCONFIG=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=1050 diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index a7aaf46ea51..f979c45a3be 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -33,6 +33,7 @@ CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y +CONFIG_HWCONFIG=y CONFIG_SPL_PAD_TO=0x8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0xc0000000 diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index 3974e3d2bd3..d2946971b48 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -131,6 +131,7 @@ CONFIG_DISPLAY_CPUINFO=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=1024 diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index ce81b558ee2..b275247d25d 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -39,6 +39,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HWCONFIG=y CONFIG_MISC_INIT_R=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 3ef909a1ce3..6169042c7e6 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -39,6 +39,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HWCONFIG=y CONFIG_MISC_INIT_R=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index d3d4876658a..6d57ad49a13 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -39,6 +39,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HWCONFIG=y CONFIG_MISC_INIT_R=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 298ff16b7eb..71d196533f7 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -167,6 +167,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 9386f2c5121..66ec936cce4 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -137,6 +137,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 173306668fb..3ba334c2401 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -150,6 +150,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index c281611dd4c..4a02e5e88fc 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -130,6 +130,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index e099f74de1c..55158864ea3 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -150,6 +150,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index f044334e80e..9b90ed478cc 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -39,6 +39,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOARD_LATE_INIT=y +# CONFIG_HWCONFIG is not set CONFIG_PCI_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig index 98e37f18b4f..90c1b94b021 100644 --- a/configs/legoev3_defconfig +++ b/configs/legoev3_defconfig @@ -23,6 +23,7 @@ CONFIG_BOOTCOMMAND="if mmc rescan; then if run loadbootscr; then run bootscript; CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_CLOCKS=y +CONFIG_HWCONFIG=y CONFIG_HUSH_PARSER=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index b89c348e5a5..ab52ea26a08 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -23,6 +23,7 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="echo;echo Welcome on the ABB Socrates Board;echo" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=276 CONFIG_CMD_REGINFO=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 3b8560f3e06..894a79df59e 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -130,6 +130,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 04ce0b3afec..6e66e6ce305 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -152,6 +152,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/doc/README.hwconfig b/doc/README.hwconfig index b6ddb438cfa..5408a22bb6a 100644 --- a/doc/README.hwconfig +++ b/doc/README.hwconfig @@ -1,6 +1,3 @@ -To enable this feature just define CONFIG_HWCONFIG in your board -config file. - This implements a simple hwconfig infrastructure: an interface for software knobs to control hardware. diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 717320c34ae..2796adbdcd8 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -14,8 +14,6 @@ * High Level Configuration Options */ -#define CONFIG_HWCONFIG - /* * On-board devices */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index e41b8e0843a..75ac2695707 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -122,8 +122,6 @@ #define CFG_SYS_FLASH_BANKS_LIST \ {CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS} -#define CONFIG_HWCONFIG /* enable hwconfig */ - /* * SDRAM on the Local Bus */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index a8af0a101c8..0a1b932e94e 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -96,7 +96,6 @@ #endif #endif -#define CONFIG_HWCONFIG /* * These can be toggled for performance analysis, otherwise use default. */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 1e02855fefd..acbd43419f2 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -132,8 +132,6 @@ #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000} -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index b5fb0a9b529..e394237daf0 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -270,8 +270,6 @@ #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index bee4b704a24..f681a218229 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -248,8 +248,6 @@ #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index be8c30db26a..a93e05dd4d2 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -246,8 +246,6 @@ #define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 795873f4233..cf65a0da188 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -211,8 +211,6 @@ #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index ffd56454939..b51762264ad 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -70,8 +70,6 @@ #define CFG_SYS_FLASH_BASE 0xe0000000 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 578277fc75c..a818a4b39f8 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -137,7 +137,6 @@ * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_HWCONFIG /* enable hwconfig */ #define DEFAULT_LINUX_BOOT_ENV \ "loadaddr=0xc0700000\0" \ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 65283afd2a0..6c5ca0a5205 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -45,7 +45,6 @@ #define CONFIG_IMX_VIDEO_SKIP /* Miscellaneous configurable options */ -#define CONFIG_HWCONFIG /* Memory configuration */ diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 6ccb4f07e3b..bbd2b36c45a 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -166,7 +166,6 @@ #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 /* diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index e152714b116..89c5a24ee90 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -309,8 +309,6 @@ #define CFG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2 #define CFG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3 -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 2664982715f..abe470fe890 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -48,7 +48,6 @@ * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_HWCONFIG /* enable hwconfig */ #define CONFIG_SETUP_INITRD_TAG #define CONFIG_EXTRA_ENV_SETTINGS \ "bootenvfile=uEnv.txt\0" \ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 7598e54ed2b..9e4f949016e 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -24,7 +24,6 @@ #define CFG_SYS_NS16550_CLK (get_serial_clock()) -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 3063635592e..a9680149807 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -92,7 +92,6 @@ #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 137d459c291..34d4c2fdecc 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -276,7 +276,6 @@ #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 #ifdef CONFIG_LPUART diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 052a15658d7..a5b7364435d 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -67,7 +67,6 @@ /* PCIe */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index f39c7c08844..059941e713a 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -157,7 +157,6 @@ #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index bdd3951e85f..b190bfe9c8e 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -34,7 +34,6 @@ /* Physical Memory Map */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index b4048744b1e..a3fa92d1ff4 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -110,7 +110,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #ifndef SPL_NO_MISC diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index cac30e4679e..4ed5481c3e7 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -74,7 +74,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index bacc84f629a..57429d4bbe3 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -114,7 +114,6 @@ unsigned long long get_qixis_addr(void); /* Physical Memory Map */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #ifndef SPL_NO_ENV diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 18defd5e5a6..e82456fd814 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -107,7 +107,6 @@ unsigned long long get_qixis_addr(void); /* Physical Memory Map */ /* fixme: these need to be checked against the board */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 /* Initial environment variables */ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index bbee9df404a..ff85d966e66 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -84,7 +84,6 @@ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 /* Initial environment variables */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index e8b752785b4..eda2d43d0c1 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -112,7 +112,6 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_HWCONFIG /* * These can be toggled for performance analysis, otherwise use default. */ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index aa9cae017d9..d1b20da24a8 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -33,8 +33,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE -#define CONFIG_HWCONFIG - #define CFG_SYS_INIT_RAM_ADDR 0x00100000 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 -- cgit v1.3.1 From 4eea76574062e9079b6a267229962d6ec0be910a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:18 -0500 Subject: pwm: imx: Remove unused references to CONFIG_IMX6_PWM_PER_CLK On platforms that use DM_PWM, we do not need to define this value anymore, so remove it from config files. Signed-off-by: Tom Rini --- include/configs/aristainetos2.h | 2 -- include/configs/ge_b1x5v2.h | 3 --- include/configs/ge_bx50v3.h | 2 -- include/configs/mx53ppd.h | 3 --- 4 files changed, 10 deletions(-) (limited to 'include') diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index c1eec5d06cc..b1ec8ef269c 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -424,8 +424,6 @@ /* check this console not needed, after test remove it */ #define CONFIG_IMX_VIDEO_SKIP -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ "sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 97fe76cfa8e..a8a6229f526 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -12,9 +12,6 @@ #include "mx6_common.h" -/* PWM */ -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - /* UART */ #define CONFIG_MXC_UART_BASE UART3_BASE diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index cbaf03c2a22..705cb763a66 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -106,6 +106,4 @@ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - #endif /* __GE_BX50V3_CONFIG_H */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 913bc1996d4..963dd92dd70 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -102,9 +102,6 @@ /* FLASH and environment organization */ -/* Backlight Control */ -#define CONFIG_IMX6_PWM_PER_CLK 66666000 - #define CONFIG_IMX_VIDEO_SKIP #endif /* __CONFIG_H */ -- cgit v1.3.1 From 0ea156ba00f34b3b9c8735d25c8ec7b8dffffb45 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:19 -0500 Subject: Convert CONFIG_IMX_VIDEO_SKIP et al to Kconfig This converts the following to Kconfig: CONFIG_IMX_VIDEO_SKIP CONFIG_IMX_HDMI Signed-off-by: Tom Rini --- configs/aristainetos2c_defconfig | 1 + configs/aristainetos2ccslb_defconfig | 1 + configs/cm_fx6_defconfig | 1 + configs/ge_b1x5v2_defconfig | 1 + configs/ge_bx50v3_defconfig | 2 ++ configs/gwventana_emmc_defconfig | 2 ++ configs/gwventana_gw5904_defconfig | 2 ++ configs/gwventana_nand_defconfig | 2 ++ configs/imx6dl_icore_nand_defconfig | 1 + configs/imx6q_icore_nand_defconfig | 1 + configs/imx6qdl_icore_mmc_defconfig | 1 + configs/imx6qdl_icore_nand_defconfig | 1 + configs/m53menlo_defconfig | 1 + configs/marsboard_defconfig | 2 ++ configs/mx53cx9020_defconfig | 1 + configs/mx53ppd_defconfig | 1 + configs/mx6cuboxi_defconfig | 2 ++ configs/mx6qsabrelite_defconfig | 2 ++ configs/mx6sabreauto_defconfig | 2 ++ configs/mx6sabresd_defconfig | 2 ++ configs/nitrogen6dl2g_defconfig | 2 ++ configs/nitrogen6dl_defconfig | 2 ++ configs/nitrogen6q2g_defconfig | 2 ++ configs/nitrogen6q_defconfig | 2 ++ configs/nitrogen6s1g_defconfig | 2 ++ configs/nitrogen6s_defconfig | 2 ++ configs/novena_defconfig | 2 ++ configs/pico-imx6_defconfig | 2 ++ configs/riotboard_defconfig | 2 ++ configs/tbs2910_defconfig | 2 ++ configs/wandboard_defconfig | 2 ++ drivers/video/imx/Kconfig | 7 +++++++ include/configs/apalis_imx6.h | 2 -- include/configs/aristainetos2.h | 4 ---- include/configs/cm_fx6.h | 3 --- include/configs/colibri_imx6.h | 4 ---- include/configs/embestmx6boards.h | 4 ---- include/configs/ge_b1x5v2.h | 3 --- include/configs/ge_bx50v3.h | 4 ---- include/configs/gw_ventana.h | 4 ---- include/configs/imx6-engicam.h | 10 ---------- include/configs/m53menlo.h | 1 - include/configs/mx53cx9020.h | 3 --- include/configs/mx53ppd.h | 2 -- include/configs/mx6cuboxi.h | 4 ---- include/configs/mx6sabre_common.h | 4 ---- include/configs/nitrogen6x.h | 4 ---- include/configs/novena.h | 4 ---- include/configs/pico-imx6.h | 4 ---- include/configs/tbs2910.h | 4 ---- include/configs/wandboard.h | 4 ---- 51 files changed, 58 insertions(+), 72 deletions(-) (limited to 'include') diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 5ff29548b0d..4c7ded9d22f 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -118,6 +118,7 @@ CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_DISPLAY=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index 0a208543dfe..a23c77af897 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -118,6 +118,7 @@ CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_DISPLAY=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index ea7596611c5..217752cbd4d 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -116,6 +116,7 @@ CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SOURCE=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig index 180a6a8568e..353942dd787 100644 --- a/configs/ge_b1x5v2_defconfig +++ b/configs/ge_b1x5v2_defconfig @@ -133,6 +133,7 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_VIDEO=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_WATCHDOG_TIMEOUT_MSECS=30000 CONFIG_IMX_WATCHDOG=y CONFIG_BCH=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index d9fbdbd6401..e35788fd850 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -98,6 +98,8 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_WATCHDOG_TIMEOUT_MSECS=8000 CONFIG_IMX_WATCHDOG=y CONFIG_BCH=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index b275247d25d..f999b447755 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -163,6 +163,8 @@ CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_HIDE_LOGO_VERSION=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 6169042c7e6..4c6291f0c51 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -167,6 +167,8 @@ CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_HIDE_LOGO_VERSION=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 6d57ad49a13..4e062e477e8 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -173,6 +173,8 @@ CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_HIDE_LOGO_VERSION=y diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index fe4866e2f51..759bbf9b34e 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -74,6 +74,7 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index 2cb995e7ae1..c7d31d502ba 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -75,6 +75,7 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 9f6d29a268b..f5a7e969786 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -98,6 +98,7 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index 2cb995e7ae1..c7d31d502ba 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -75,6 +75,7 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index a5760242be5..e332de2aa9e 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -122,6 +122,7 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_SPLASH_SOURCE=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index a6cffa2db65..27c5ebe000f 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -67,6 +67,8 @@ CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig index b34f2e7e6b4..c20c6a40a1d 100644 --- a/configs/mx53cx9020_defconfig +++ b/configs/mx53cx9020_defconfig @@ -40,3 +40,4 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index ed4ebbbe3c2..d8cb654a59f 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -81,6 +81,7 @@ CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_WATCHDOG_TIMEOUT_MSECS=8000 CONFIG_IMX_WATCHDOG=y CONFIG_BCH=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 0904bd11013..a9957aba7c2 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -84,6 +84,8 @@ CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index becf36e01c6..6869b903b7f 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -89,6 +89,8 @@ CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 634473f3074..8e94a84409d 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -120,6 +120,8 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 4f7d3704203..9472e032c81 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -125,6 +125,8 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index 3ec4df14a86..87ca8487fbd 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -94,6 +94,8 @@ CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 6a6510e12e2..1bdd2f02e9d 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -94,6 +94,8 @@ CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index e2acce8757e..dc010b02a91 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -97,6 +97,8 @@ CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index ceb843f15e0..fe3291d22b7 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -97,6 +97,8 @@ CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index bb0d6f5439f..b31652495f2 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -94,6 +94,8 @@ CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index 0232d0c9d76..eb11959e4ae 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -94,6 +94,8 @@ CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 5f761799a21..3999ae1c829 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -99,5 +99,7 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_BMP_16BPP=y diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig index 9b3f76d8e5d..a6ed013f8b6 100644 --- a/configs/pico-imx6_defconfig +++ b/configs/pico-imx6_defconfig @@ -99,6 +99,8 @@ CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 1bf40270e83..9f8fbc85c8a 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -84,6 +84,8 @@ CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 4c5b98bc656..0df8a689002 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -114,6 +114,8 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_VIDEO_BMP_RLE8=y # CONFIG_GZIP is not set CONFIG_OF_LIBFDT_ASSUME_MASK=0xff diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 525f55ee00c..a6baff1e24c 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -83,6 +83,8 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig index afe950b6df7..34e8b640595 100644 --- a/drivers/video/imx/Kconfig +++ b/drivers/video/imx/Kconfig @@ -6,3 +6,10 @@ config VIDEO_IPUV3 This enables framebuffer driver for i.MX processors working on the IPUv3(Image Processing Unit) internal graphic processor. +config IMX_VIDEO_SKIP + bool "Enable calling board_video_skip function" + depends on VIDEO_IPUV3 + +config IMX_HDMI + bool "Enable HDMI support in IPUv3" + depends on VIDEO_IPUV3 diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index c9375b4d162..a3c86545f07 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -32,8 +32,6 @@ #define CONFIG_USBD_HS /* Framebuffer and LCD */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP /* Command definition */ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index b1ec8ef269c..6faf544d21b 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -420,10 +420,6 @@ /* UBI support */ -/* Framebuffer */ -/* check this console not needed, after test remove it */ -#define CONFIG_IMX_VIDEO_SKIP - #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ "sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index d5c03957975..9df8baa8a96 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -143,9 +143,6 @@ /* misc */ -/* Display */ -#define CONFIG_IMX_HDMI - /* EEPROM */ #endif /* __CONFIG_CM_FX6_H */ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index c6a79debd6b..60a3862a4d1 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -28,10 +28,6 @@ /* Client */ #define CONFIG_USBD_HS -/* Framebuffer and LCD */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - /* Command definition */ #undef CONFIG_IPADDR diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 29b7748e786..22e0fa5aabf 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -43,10 +43,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #include "mx6_common.h" /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index a8a6229f526..1458b187de2 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -28,9 +28,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USBD_HS -/* Video */ -#define CONFIG_IMX_VIDEO_SKIP - /* Memory */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 705cb763a66..f62b8f175e1 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -102,8 +102,4 @@ #define CFG_SYS_FSL_USDHC_NUM 3 -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #endif /* __GE_BX50V3_CONFIG_H */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 6c5ca0a5205..4d0a78c6269 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -40,10 +40,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USBD_HS -/* Framebuffer and LCD */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - /* Miscellaneous configurable options */ /* Memory configuration */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index 1f30798550c..36b6b95b84d 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -132,14 +132,4 @@ /* MTD device */ #endif -/* Falcon Mode */ -#ifdef CONFIG_SPL_OS_BOOT -/* MMC support: args@1MB kernel@2MB */ -#endif - -/* Framebuffer */ -#ifdef CONFIG_VIDEO_IPUV3 -# define CONFIG_IMX_VIDEO_SKIP -#endif - #endif /* __IMX6_ENGICAM_CONFIG_H */ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index eca86a94519..66591390d90 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -78,7 +78,6 @@ /* LVDS display */ #define CFG_SYS_LDB_CLOCK 33260000 -#define CONFIG_IMX_VIDEO_SKIP /* Watchdog */ diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 2bc462cc37e..cd806cb698e 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -66,7 +66,4 @@ /* environment organization */ -/* Framebuffer and LCD */ -#define CONFIG_IMX_VIDEO_SKIP - #endif /* __CONFIG_H */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 963dd92dd70..9464d6e44ae 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -102,6 +102,4 @@ /* FLASH and environment organization */ -#define CONFIG_IMX_VIDEO_SKIP - #endif /* __CONFIG_H */ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 12741c08de5..f7f209c20b5 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -14,10 +14,6 @@ /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - /* USB */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 5e95e430c49..6294fd1e2c4 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -145,10 +145,6 @@ /* Environment organization */ -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #define CONFIG_USBD_HS #endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index dd7f9513199..5020b3bb71d 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -26,10 +26,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Framebuffer and LCD */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #ifdef CONFIG_CMD_MMC #define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) #else diff --git a/include/configs/novena.h b/include/configs/novena.h index 16a89b97b06..4e46dfc526c 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -63,10 +63,6 @@ #define CONFIG_USBD_HS #endif -/* Video output */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - /* Extra U-Boot environment. */ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 9e6c210c40b..6d7873daa0a 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -100,8 +100,4 @@ /* Ethernet Configuration */ #define CONFIG_FEC_MXC_PHYADDR 1 -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #endif /* __CONFIG_H * */ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index f6544f6226c..fcc96749422 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -20,10 +20,6 @@ #define CFG_SYS_BOOTMAPSZ 0x10000000 -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - /* PCI */ #ifdef CONFIG_CMD_PCI #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 23027b1d3d9..6923009d459 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -20,10 +20,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ "splashpos=m,m\0" \ -- cgit v1.3.1 From 500dfebf22cbf0adbef02b80c75a93892ee861ec Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:20 -0500 Subject: mpc8548cds: Migrate CONFIG_INTERRUPTS to Kconfig Only this platform sets this option, define it in the board Kconfig file. Signed-off-by: Tom Rini --- board/freescale/mpc8548cds/Kconfig | 3 +++ include/configs/MPC8548CDS.h | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/freescale/mpc8548cds/Kconfig b/board/freescale/mpc8548cds/Kconfig index 723ead51e5c..bb0a0758964 100644 --- a/board/freescale/mpc8548cds/Kconfig +++ b/board/freescale/mpc8548cds/Kconfig @@ -6,6 +6,9 @@ config PCI1 config FSL_CADMUS def_bool y +config INTERRUPTS + def_bool y + config SYS_BOARD default "mpc8548cds" diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 75ac2695707..83eb18c3b7a 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ - #ifndef __ASSEMBLY__ #include #endif -- cgit v1.3.1 From d5c77533b422eabc469e9f55d14afc3ac9ac49f6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:21 -0500 Subject: Convert CONFIG_IODELAY_RECALIBRATION to Kconfig This converts the following to Kconfig: CONFIG_IODELAY_RECALIBRATION Signed-off-by: Tom Rini --- arch/arm/mach-omap2/omap5/Kconfig | 4 ++++ include/configs/am57xx_evm.h | 2 -- include/configs/dra7xx_evm.h | 2 -- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 18a66764224..0787d192b69 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -1,7 +1,11 @@ if OMAP54XX +config IODELAY_RECALIBRATION + bool + config DRA7XX bool + select IODELAY_RECALIBRATION select SYS_OMAP_ABE_SYSCK help DRA7xx is an OMAP based SOC with Dual Core A-15s. diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 340a8ce6dc8..dacfd41cced 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -14,8 +14,6 @@ #include #include -#define CONFIG_IODELAY_RECALIBRATION - #define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ #define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 8217712e390..ac3fcacc68e 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -13,8 +13,6 @@ #include -#define CONFIG_IODELAY_RECALIBRATION - #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED 0x80000000 -- cgit v1.3.1 From c136a861054e698dec86f5f7b2a326ad38cd197f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:22 -0500 Subject: Convert CONFIG_IOMUX_SHARE_CONF_REG et al to Kconfig This converts the following to Kconfig: CONFIG_IOMUX_LPSR CONFIG_IOMUX_SHARE_CONF_REG Signed-off-by: Tom Rini --- arch/arm/Kconfig | 1 + arch/arm/include/asm/arch-vf610/imx-regs.h | 3 --- arch/arm/mach-imx/Kconfig | 6 ++++++ arch/arm/mach-imx/mx6/Kconfig | 3 +++ arch/arm/mach-imx/mx7/Kconfig | 1 + include/configs/colibri-imx6ull.h | 1 - include/configs/mx6sllevk.h | 2 -- include/configs/mx6ullevk.h | 2 -- include/configs/mx7_common.h | 3 --- 9 files changed, 11 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3f68d0988b7..eb5e3b69d84 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1245,6 +1245,7 @@ config ARCH_VF610 bool "Freescale Vybrid" select CPU_V7A select GPIO_EXTRA_HEADER + select IOMUX_SHARE_CONF_REG select MACH_IMX select SYS_FSL_ERRATUM_ESDHC111 imply CMD_MTDPARTS diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 97211f4b12a..fa3a97824fa 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -103,9 +103,6 @@ #define QSPI0_AMBA_BASE 0x20000000 -/* MUX mode and PAD ctrl are in one register */ -#define CONFIG_IOMUX_SHARE_CONF_REG - #define FEC_QUIRK_ENET_MAC #define I2C_QUIRK_REG diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index b72b6af4340..ee5f1996a83 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -195,3 +195,9 @@ config IMX_CONTAINER_CFG help This is to specific the cfg file for generating container image which will be loaded by SPL. + +config IOMUX_LPSR + bool + +config IOMUX_SHARE_CONF_REG + bool diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 752c57f52db..e6b0ee75793 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -168,6 +168,7 @@ config TARGET_COLIBRI_IMX6ULL select BOARD_LATE_INIT select DM select DM_THERMAL + select IOMUX_LPSR config TARGET_DART_6UL bool "Variscite imx6ULL dart(DART-SOM-6ULL)" @@ -396,6 +397,7 @@ config TARGET_MX6SLLEVK select BOARD_LATE_INIT select DM select DM_THERMAL + select IOMUX_LPSR imply CMD_DM config TARGET_MX6SXSABRESD @@ -464,6 +466,7 @@ config TARGET_MX6ULL_14X14_EVK select BOARD_LATE_INIT select DM select DM_THERMAL + select IOMUX_LPSR imply CMD_DM config TARGET_MX6ULZ_SMM_M2 diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 3c388183bc2..0bb18f65200 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -6,6 +6,7 @@ config MX7 select ARCH_SUPPORT_PSCI select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select IOMUX_LPSR select ROM_UNIFIED_SECTIONS select SYSCOUNTER_TIMER imply CMD_FUSE diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 12dc946fc78..c0c3b4e0359 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -11,7 +11,6 @@ #define __COLIBRI_IMX6ULL_CONFIG_H #include "mx6_common.h" -#define CONFIG_IOMUX_LPSR #define PHYS_SDRAM_SIZE SZ_1G diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 6632e4ea29c..8731f6a3e4a 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -92,8 +92,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CFG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_IOMUX_LPSR - /* USB Configs */ #ifdef CONFIG_CMD_USB #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 4154d328ded..0e986093f35 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -108,8 +108,6 @@ /* environment organization */ -#define CONFIG_IOMUX_LPSR - #ifdef CONFIG_CMD_NET #define CONFIG_FEC_ENET_DEV 1 #endif diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 4704276a74d..d5af6990107 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -17,9 +17,6 @@ #define CONFIG_MXC_GPT_HCLK #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ -/* Enable iomux-lpsr support */ -#define CONFIG_IOMUX_LPSR - /* Miscellaneous configurable options */ /* UART */ -- cgit v1.3.1 From 68e54040ccc3c5432be720e0cc6da3489eaceef6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:23 -0500 Subject: sandbox: Move CONFIG_IO_TRACE to Kconfig This is only used on sandbox, so select it there. Cc: Simon Glass Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/Kconfig | 1 + common/Kconfig | 3 +++ include/configs/sandbox.h | 2 -- 3 files changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/Kconfig b/arch/Kconfig index ae397166979..51d46a45fef 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -146,6 +146,7 @@ config SANDBOX select DM_SPI select DM_SPI_FLASH select GZIP_COMPRESSED + select IO_TRACE select LZO select OF_BOARD_SETUP select PCI_ENDPOINT diff --git a/common/Kconfig b/common/Kconfig index 053e93eb1ab..8c71d3c972b 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1086,3 +1086,6 @@ config FDT_SIMPLEFB These functions can be used by board to indicate to the OS the presence of the simple frame buffer with associated reserved memory + +config IO_TRACE + bool diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 1081e0bbc49..1779f1894e7 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -6,8 +6,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_IO_TRACE - #define CONFIG_MALLOC_F_ADDR 0x0010000 /* Size of our emulated memory */ -- cgit v1.3.1 From d5596cbc6e4d189e006f0422b162cd12e07c5b97 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:24 -0500 Subject: arm: lpc32xx: Remove unused hsuart driver This driver is not enabled in any config currently, remove it. Cc: Trevor Woerner Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-lpc32xx/config.h | 8 --- arch/arm/mach-lpc32xx/devices.c | 16 ----- drivers/serial/Makefile | 1 - drivers/serial/lpc32xx_hsuart.c | 112 ----------------------------- include/dm/platform_data/lpc32xx_hsuart.h | 18 ----- 5 files changed, 155 deletions(-) delete mode 100644 drivers/serial/lpc32xx_hsuart.c delete mode 100644 include/dm/platform_data/lpc32xx_hsuart.h (limited to 'include') diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 3ad78cb1e64..41160384a4d 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -11,14 +11,6 @@ /* Basic CPU architecture */ -/* UART configuration */ -#if (CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \ - (CONFIG_CONS_INDEX == 7) -#if !defined(CONFIG_LPC32XX_HSUART) -#define CONFIG_LPC32XX_HSUART -#endif -#endif - #if !defined(CFG_SYS_NS16550_CLK) #define CFG_SYS_NS16550_CLK 13000000 #endif diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c index 3fcf8facb41..6a67a3591aa 100644 --- a/arch/arm/mach-lpc32xx/devices.c +++ b/arch/arm/mach-lpc32xx/devices.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include @@ -53,26 +52,11 @@ static const struct ns16550_plat lpc32xx_uart[] = { .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, }; -#if defined(CONFIG_LPC32XX_HSUART) -static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = { - { HS_UART1_BASE, }, - { HS_UART2_BASE, }, - { HS_UART7_BASE, }, -}; -#endif - U_BOOT_DRVINFOS(lpc32xx_uarts) = { -#if defined(CONFIG_LPC32XX_HSUART) - { "lpc32xx_hsuart", &lpc32xx_hsuart[0], }, - { "lpc32xx_hsuart", &lpc32xx_hsuart[1], }, -#endif { "ns16550_serial", &lpc32xx_uart[0], }, { "ns16550_serial", &lpc32xx_uart[1], }, { "ns16550_serial", &lpc32xx_uart[2], }, { "ns16550_serial", &lpc32xx_uart[3], }, -#if defined(CONFIG_LPC32XX_HSUART) - { "lpc32xx_hsuart", &lpc32xx_hsuart[2], }, -#endif }; #endif diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 45cf94c74c6..33fa5682211 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -38,7 +38,6 @@ obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o obj-$(CONFIG_CORTINA_UART) += serial_cortina.o obj-$(CONFIG_DEBUG_SBI_CONSOLE) += serial_sbi.o obj-$(CONFIG_EFI_APP) += serial_efi.o -obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += serial_mcf.o obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P_SERIAL) += serial_s5p.o diff --git a/drivers/serial/lpc32xx_hsuart.c b/drivers/serial/lpc32xx_hsuart.c deleted file mode 100644 index d39a3c0494e..00000000000 --- a/drivers/serial/lpc32xx_hsuart.c +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011-2015 Vladimir Zapolskiy - */ - -#include -#include -#include -#include -#include - -#include -#include - -struct lpc32xx_hsuart_priv { - struct hsuart_regs *hsuart; -}; - -static int lpc32xx_serial_setbrg(struct udevice *dev, int baudrate) -{ - struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); - struct hsuart_regs *hsuart = priv->hsuart; - u32 div; - - /* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */ - div = (get_serial_clock() / 14 + baudrate / 2) / baudrate - 1; - if (div > 255) - div = 255; - - writel(div, &hsuart->rate); - - return 0; -} - -static int lpc32xx_serial_getc(struct udevice *dev) -{ - struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); - struct hsuart_regs *hsuart = priv->hsuart; - - if (!(readl(&hsuart->level) & HSUART_LEVEL_RX)) - return -EAGAIN; - - return readl(&hsuart->rx) & HSUART_RX_DATA; -} - -static int lpc32xx_serial_putc(struct udevice *dev, const char c) -{ - struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); - struct hsuart_regs *hsuart = priv->hsuart; - - /* Wait for empty FIFO */ - if (readl(&hsuart->level) & HSUART_LEVEL_TX) - return -EAGAIN; - - writel(c, &hsuart->tx); - - return 0; -} - -static int lpc32xx_serial_pending(struct udevice *dev, bool input) -{ - struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); - struct hsuart_regs *hsuart = priv->hsuart; - - if (input) { - if (readl(&hsuart->level) & HSUART_LEVEL_RX) - return 1; - } else { - if (readl(&hsuart->level) & HSUART_LEVEL_TX) - return 1; - } - - return 0; -} - -static int lpc32xx_serial_init(struct hsuart_regs *hsuart) -{ - /* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */ - writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) | - HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0, - &hsuart->ctrl); - - return 0; -} - -static int lpc32xx_hsuart_probe(struct udevice *dev) -{ - struct lpc32xx_hsuart_plat *plat = dev_get_plat(dev); - struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); - - priv->hsuart = (struct hsuart_regs *)plat->base; - - lpc32xx_serial_init(priv->hsuart); - - return 0; -} - -static const struct dm_serial_ops lpc32xx_hsuart_ops = { - .setbrg = lpc32xx_serial_setbrg, - .getc = lpc32xx_serial_getc, - .putc = lpc32xx_serial_putc, - .pending = lpc32xx_serial_pending, -}; - -U_BOOT_DRIVER(lpc32xx_hsuart) = { - .name = "lpc32xx_hsuart", - .id = UCLASS_SERIAL, - .probe = lpc32xx_hsuart_probe, - .ops = &lpc32xx_hsuart_ops, - .priv_auto = sizeof(struct lpc32xx_hsuart_priv), - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/include/dm/platform_data/lpc32xx_hsuart.h b/include/dm/platform_data/lpc32xx_hsuart.h deleted file mode 100644 index 6f41e0e734a..00000000000 --- a/include/dm/platform_data/lpc32xx_hsuart.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015 Vladimir Zapolskiy - */ - -#ifndef _LPC32XX_HSUART_PLAT_H -#define _LPC32XX_HSUART_PLAT_H - -/** - * struct lpc32xx_hsuart_plat - NXP LPC32xx HSUART platform data - * - * @base: Base register address - */ -struct lpc32xx_hsuart_plat { - unsigned long base; -}; - -#endif -- cgit v1.3.1 From 00faea644a0afb8eccb332af446c4ca9d0abe095 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:25 -0500 Subject: arm: ls102xa: Migrate LS102XA_STREAM_ID This symbol appears to be globally used in the architecture, select it. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ++++ include/configs/km/pg-wcom-ls102xa.h | 6 ------ include/configs/ls1021aiot.h | 2 -- include/configs/ls1021aqds.h | 2 -- include/configs/ls1021atsn.h | 2 -- include/configs/ls1021atwr.h | 2 -- 6 files changed, 4 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 369e68b8193..7e138e0cc5b 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -2,6 +2,7 @@ config ARCH_LS1021A bool select FSL_DEVICE_DISABLE select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI + select LS102XA_STREAM_ID select SYS_FSL_DDR_BE if SYS_FSL_DDR select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR select SYS_FSL_IFC_BE @@ -37,6 +38,9 @@ config FSL_DEVICE_DISABLE config LS1_DEEP_SLEEP bool "Deep sleep" +config LS102XA_STREAM_ID + bool + config MAX_CPUS int "Maximum number of CPUs permitted for LS102xA" default 2 diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index bbd2b36c45a..c1174b87ab7 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -168,12 +168,6 @@ #define HWCONFIG_BUFFER_SIZE 256 -/* - * Miscellaneous configurable options - */ - -#define CONFIG_LS102XA_STREAM_ID - /* * Environment */ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index a9680149807..024a7185275 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -103,8 +103,6 @@ */ #define CFG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_LS102XA_STREAM_ID - #include #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 34d4c2fdecc..5a91cc3efec 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -295,8 +295,6 @@ */ #define CFG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_LS102XA_STREAM_ID - /* * Environment */ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index a5b7364435d..5612c60ae90 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -140,8 +140,6 @@ /* Miscellaneous configurable options */ #define CFG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_LS102XA_STREAM_ID - /* Environment */ #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 059941e713a..3c4c207edd0 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -297,8 +297,6 @@ */ #define CFG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_LS102XA_STREAM_ID - /* * Environment */ -- cgit v1.3.1 From 4982e123b293b1fd44164b6760ee3647720d72ba Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:26 -0500 Subject: arm: samsung: Move CONFIG_MISC_COMMON to Kconfig This option controls using board/samsung/common/misc.c, so add a Kconfig file there as well and select it from the boards which use this functionality. Signed-off-by: Tom Rini Reviewed-by: Simon Glass Reviewed-by: Minkyu Kang --- arch/arm/Kconfig | 1 + arch/arm/mach-exynos/Kconfig | 5 +++++ arch/arm/mach-s5pc1xx/Kconfig | 1 + board/samsung/common/Kconfig | 2 ++ include/configs/odroid.h | 6 ------ include/configs/odroid_xu3.h | 1 - include/configs/s5p_goni.h | 2 -- include/configs/s5pc210_universal.h | 3 --- include/configs/trats.h | 3 --- include/configs/trats2.h | 3 --- 10 files changed, 9 insertions(+), 18 deletions(-) create mode 100644 board/samsung/common/Kconfig (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index eb5e3b69d84..fb696abac80 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2342,6 +2342,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/samsung/common/Kconfig" source "board/siemens/common/Kconfig" source "board/seeed/npi_imx6ull/Kconfig" source "board/socionext/developerbox/Kconfig" diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 84102908561..29e35e443c6 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -67,10 +67,12 @@ config TARGET_SMDKV310 select SUPPORT_SPL config TARGET_TRATS + select MISC_COMMON bool "Exynos4210 Trats board" config TARGET_S5PC210_UNIVERSAL bool "EXYNOS4210 Universal C210 board" + select MISC_COMMON config TARGET_ORIGEN bool "Exynos4412 Origen board" @@ -79,9 +81,11 @@ config TARGET_ORIGEN config TARGET_TRATS2 bool "Exynos4412 Trat2 board" + select MISC_COMMON config TARGET_ODROID bool "Exynos4412 Odroid board" + select MISC_COMMON endchoice endif @@ -113,6 +117,7 @@ config TARGET_ODROID_XU3 bool "Exynos5422 Odroid board" select EXYNOS5_DT select EXYNOS5420 + select MISC_COMMON select OF_CONTROL config TARGET_ARNDALE diff --git a/arch/arm/mach-s5pc1xx/Kconfig b/arch/arm/mach-s5pc1xx/Kconfig index 8cffced5512..b6a4b0b653f 100644 --- a/arch/arm/mach-s5pc1xx/Kconfig +++ b/arch/arm/mach-s5pc1xx/Kconfig @@ -9,6 +9,7 @@ config TARGET_S5P_GONI select OF_CONTROL select BLK select DM_MMC + select MISC_COMMON config TARGET_SMDKC100 bool "Support smdkc100 board" diff --git a/board/samsung/common/Kconfig b/board/samsung/common/Kconfig new file mode 100644 index 00000000000..849aeff6134 --- /dev/null +++ b/board/samsung/common/Kconfig @@ -0,0 +1,2 @@ +config MISC_COMMON + bool diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 8b00a279215..f252b349437 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -143,10 +143,4 @@ "kernel_addr_r=0x41000000\0" \ BOOTENV -/* - * Supported Odroid boards: X3, U3 - * TODO: Add Odroid X support - */ -#define CONFIG_MISC_COMMON - #endif /* __CONFIG_H */ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index d2d7fca5445..5bbe7aadcb2 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -57,7 +57,6 @@ "params.bin raw 0x1880 0x20\0" /* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */ -#define CONFIG_MISC_COMMON #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) /* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 3d49d52b381..fdade1ee66f 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -61,8 +61,6 @@ #define COMMON_BOOT "${console} ${meminfo} ${mtdparts}" -#define CONFIG_MISC_COMMON - #define CONFIG_EXTRA_ENV_SETTINGS \ "updateb=" \ "onenand erase 0x0 0x100000;" \ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 06be9c0f652..80d3fc9258c 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -95,9 +95,6 @@ void universal_spi_sda(int bit); int universal_spi_read(void); #endif -/* Common misc for Samsung */ -#define CONFIG_MISC_COMMON - /* Download menu - definitions for check keys */ #ifndef __ASSEMBLY__ diff --git a/include/configs/trats.h b/include/configs/trats.h index 5bd0ca2a964..ec18842bbe8 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -125,9 +125,6 @@ /* GPT */ -/* Common misc for Samsung */ -#define CONFIG_MISC_COMMON - /* Download menu - definitions for check keys */ #ifndef __ASSEMBLY__ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index cef563696bd..0aa331e3935 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -115,9 +115,6 @@ /* GPT */ -/* Common misc for Samsung */ -#define CONFIG_MISC_COMMON - /* Download menu - definitions for check keys */ #ifndef __ASSEMBLY__ -- cgit v1.3.1 From 2568bd6db760b384f7c17f5afdfc1cb63b17ed53 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:27 -0500 Subject: arm: Remove unused mx27 code We no longer have any i.MX27 platforms, remove the remaining support code. Signed-off-by: Tom Rini --- arch/arm/cpu/arm926ejs/Makefile | 1 - arch/arm/cpu/arm926ejs/mx27/Makefile | 7 - arch/arm/cpu/arm926ejs/mx27/generic.c | 378 --------------------------------- arch/arm/cpu/arm926ejs/mx27/relocate.S | 50 ----- arch/arm/cpu/arm926ejs/mx27/reset.c | 41 ---- arch/arm/cpu/arm926ejs/mx27/timer.c | 166 --------------- arch/arm/lib/asm-offsets.c | 29 +-- drivers/gpio/mxc_gpio.c | 12 +- drivers/mtd/nand/raw/mxc_nand.c | 3 +- drivers/mtd/nand/raw/mxc_nand.h | 2 +- drivers/net/fec_mxc.c | 3 - drivers/spi/mxc_spi.c | 8 - include/configs/imx27lite-common.h | 134 ------------ 13 files changed, 9 insertions(+), 825 deletions(-) delete mode 100644 arch/arm/cpu/arm926ejs/mx27/Makefile delete mode 100644 arch/arm/cpu/arm926ejs/mx27/generic.c delete mode 100644 arch/arm/cpu/arm926ejs/mx27/relocate.S delete mode 100644 arch/arm/cpu/arm926ejs/mx27/reset.c delete mode 100644 arch/arm/cpu/arm926ejs/mx27/timer.c delete mode 100644 include/configs/imx27lite-common.h (limited to 'include') diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 7f1436d76e1..7e7ad4f35d7 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -12,7 +12,6 @@ extra-y := endif endif -obj-$(CONFIG_MX27) += mx27/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/ obj-$(if $(filter spear,$(SOC)),y) += spear/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile deleted file mode 100644 index ac5ebaf5ef8..00000000000 --- a/arch/arm/cpu/arm926ejs/mx27/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# - -obj-y += generic.o timer.o reset.o relocate.o diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c deleted file mode 100644 index 8b9d3a272af..00000000000 --- a/arch/arm/cpu/arm926ejs/mx27/generic.c +++ /dev/null @@ -1,378 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2008 Eric Jarrige - * Copyright (c) 2009 Ilya Yanok - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_MMC_MXC -#include -#endif - -/* - * get the system pll clock in Hz - * - * mfi + mfn / (mfd +1) - * f = 2 * f_ref * -------------------- - * pd + 1 - */ -static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) -{ - unsigned int mfi = (pll >> 10) & 0xf; - unsigned int mfn = pll & 0x3ff; - unsigned int mfd = (pll >> 16) & 0x3ff; - unsigned int pd = (pll >> 26) & 0xf; - - mfi = mfi <= 5 ? 5 : mfi; - - return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn), - (mfd + 1) * (pd + 1)); -} - -static ulong clk_in_32k(void) -{ - return 1024 * CONFIG_MX27_CLK32; -} - -static ulong clk_in_26m(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { - /* divide by 1.5 */ - return 26000000 * 2 / 3; - } else { - return 26000000; - } -} - -static ulong imx_get_mpllclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref; - - if (cscr & CSCR_MCU_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - return imx_decode_pll(readl(&pll->mpctl0), fref); -} - -static ulong imx_get_armclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref = imx_get_mpllclk(); - ulong div; - - if (!(cscr & CSCR_ARM_SRC_MPLL)) - fref = lldiv((fref * 2), 3); - - div = ((cscr >> 12) & 0x3) + 1; - - return lldiv(fref, div); -} - -static ulong imx_get_ahbclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref = imx_get_mpllclk(); - ulong div; - - div = ((cscr >> 8) & 0x3) + 1; - - return lldiv(fref * 2, 3 * div); -} - -static __attribute__((unused)) ulong imx_get_spllclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref; - - if (cscr & CSCR_SP_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - return imx_decode_pll(readl(&pll->spctl0), fref); -} - -static ulong imx_decode_perclk(ulong div) -{ - return lldiv((imx_get_mpllclk() * 2), (div * 3)); -} - -static ulong imx_get_perclk1(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1); -} - -static ulong imx_get_perclk2(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1); -} - -static __attribute__((unused)) ulong imx_get_perclk3(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1); -} - -static __attribute__((unused)) ulong imx_get_perclk4(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1); -} - -unsigned int mxc_get_clock(enum mxc_clock clk) -{ - switch (clk) { - case MXC_ARM_CLK: - return imx_get_armclk(); - case MXC_I2C_CLK: - return imx_get_ahbclk()/2; - case MXC_UART_CLK: - return imx_get_perclk1(); - case MXC_FEC_CLK: - return imx_get_ahbclk(); - case MXC_ESDHC_CLK: - return imx_get_perclk2(); - } - return -1; -} - - -u32 get_cpu_rev(void) -{ - return MXC_CPU_MX27 << 12; -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo (void) -{ - char buf[32]; - - printf("CPU: Freescale i.MX27 at %s MHz\n\n", - strmhz(buf, imx_get_mpllclk())); - return 0; -} -#endif - -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FEC_MXC) - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - /* enable FEC clock */ - writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1); - writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0); - return fecmxc_initialize(bis); -#else - return 0; -#endif -} - -/* - * Initializes on-chip MMC controllers. - * to override, implement board_mmc_init() - */ -int cpu_mmc_init(struct bd_info *bis) -{ -#ifdef CONFIG_MMC_MXC - return mxc_mmc_init(bis); -#else - return 0; -#endif -} - -void imx_gpio_mode(int gpio_mode) -{ - struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE; - unsigned int pin = gpio_mode & GPIO_PIN_MASK; - unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; - unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT; - unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT; - unsigned int tmp; - - /* Pullup enable */ - if (gpio_mode & GPIO_PUEN) { - writel(readl(®s->port[port].puen) | (1 << pin), - ®s->port[port].puen); - } else { - writel(readl(®s->port[port].puen) & ~(1 << pin), - ®s->port[port].puen); - } - - /* Data direction */ - if (gpio_mode & GPIO_OUT) { - writel(readl(®s->port[port].gpio_dir) | 1 << pin, - ®s->port[port].gpio_dir); - } else { - writel(readl(®s->port[port].gpio_dir) & ~(1 << pin), - ®s->port[port].gpio_dir); - } - - /* Primary / alternate function */ - if (gpio_mode & GPIO_AF) { - writel(readl(®s->port[port].gpr) | (1 << pin), - ®s->port[port].gpr); - } else { - writel(readl(®s->port[port].gpr) & ~(1 << pin), - ®s->port[port].gpr); - } - - /* use as gpio? */ - if (!(gpio_mode & (GPIO_PF | GPIO_AF))) { - writel(readl(®s->port[port].gius) | (1 << pin), - ®s->port[port].gius); - } else { - writel(readl(®s->port[port].gius) & ~(1 << pin), - ®s->port[port].gius); - } - - /* Output / input configuration */ - if (pin < 16) { - tmp = readl(®s->port[port].ocr1); - tmp &= ~(3 << (pin * 2)); - tmp |= (ocr << (pin * 2)); - writel(tmp, ®s->port[port].ocr1); - - writel(readl(®s->port[port].iconfa1) & ~(3 << (pin * 2)), - ®s->port[port].iconfa1); - writel(readl(®s->port[port].iconfa1) | aout << (pin * 2), - ®s->port[port].iconfa1); - writel(readl(®s->port[port].iconfb1) & ~(3 << (pin * 2)), - ®s->port[port].iconfb1); - writel(readl(®s->port[port].iconfb1) | bout << (pin * 2), - ®s->port[port].iconfb1); - } else { - pin -= 16; - - tmp = readl(®s->port[port].ocr2); - tmp &= ~(3 << (pin * 2)); - tmp |= (ocr << (pin * 2)); - writel(tmp, ®s->port[port].ocr2); - - writel(readl(®s->port[port].iconfa2) & ~(3 << (pin * 2)), - ®s->port[port].iconfa2); - writel(readl(®s->port[port].iconfa2) | aout << (pin * 2), - ®s->port[port].iconfa2); - writel(readl(®s->port[port].iconfb2) & ~(3 << (pin * 2)), - ®s->port[port].iconfb2); - writel(readl(®s->port[port].iconfb2) | bout << (pin * 2), - ®s->port[port].iconfb2); - } -} - -#ifdef CONFIG_MXC_UART -void mx27_uart1_init_pins(void) -{ - int i; - unsigned int mode[] = { - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - -} -#endif /* CONFIG_MXC_UART */ - -#ifdef CONFIG_FEC_MXC -void mx27_fec_init_pins(void) -{ - int i; - unsigned int mode[] = { - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC | GPIO_PUEN, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_CLR, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); -} - -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) -{ - int i; - struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; - struct fuse_bank *bank = &iim->bank[0]; - struct fuse_bank0_regs *fuse = - (struct fuse_bank0_regs *)bank->fuse_regs; - - for (i = 0; i < 6; i++) - mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff; -} -#endif /* CONFIG_FEC_MXC */ - -#ifdef CONFIG_MMC_MXC -void mx27_sd1_init_pins(void) -{ - int i; - unsigned int mode[] = { - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - -} - -void mx27_sd2_init_pins(void) -{ - int i; - unsigned int mode[] = { - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - -} -#endif /* CONFIG_MMC_MXC */ diff --git a/arch/arm/cpu/arm926ejs/mx27/relocate.S b/arch/arm/cpu/arm926ejs/mx27/relocate.S deleted file mode 100644 index 5dfa272be24..00000000000 --- a/arch/arm/cpu/arm926ejs/mx27/relocate.S +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * relocate - i.MX27-specific vector relocation - * - * Copyright (c) 2013 Albert ARIBAUD - */ - -#include -#include -#include - -/* - * The i.MX27 SoC is very specific with respect to exceptions: it - * does not provide RAM at the high vectors address (0xFFFF0000), - * thus only the low address (0x00000000) is useable; but that is - * in ROM. Therefore, vectors cannot be changed at all. - * - * However, these ROM-based vectors actually just perform indirect - * calls through pointers located in RAM at SoC-specific addresses, - * as follows: - * - * Offset Exception Use by ROM code - * 0x00000000 reset indirect branch to [0x00000014] - * 0x00000004 undefined instruction indirect branch to [0xfffffef0] - * 0x00000008 software interrupt indirect branch to [0xfffffef4] - * 0x0000000c prefetch abort indirect branch to [0xfffffef8] - * 0x00000010 data abort indirect branch to [0xfffffefc] - * 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000 - * 0x00000018 IRQ indirect branch to [0xffffff00] - * 0x0000001c FIQ indirect branch to [0xffffff04] - * - * In order to initialize exceptions on i.MX27, we must copy U-Boot's - * indirect (not exception!) vector table into 0xfffffef0..0xffffff04 - * taking care not to copy vectors number 5 (reserved exception). - */ - - .section .text.relocate_vectors,"ax",%progbits - -ENTRY(relocate_vectors) - - ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ - ldr r1, =32 /* size of vector table */ - add r0, r0, r1 /* skip to indirect table */ - ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */ - ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */ - stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */ - - bx lr - -ENDPROC(relocate_vectors) diff --git a/arch/arm/cpu/arm926ejs/mx27/reset.c b/arch/arm/cpu/arm926ejs/mx27/reset.c deleted file mode 100644 index 496fb30817d..00000000000 --- a/arch/arm/cpu/arm926ejs/mx27/reset.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2009 - * Ilya Yanok, Emcraft Systems Ltd, - */ - -#include -#include -#include -#include - -/* - * Reset the cpu by setting up the watchdog timer and let it time out - */ -void reset_cpu(void) -{ - struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; - /* Disable watchdog and set Time-Out field to 0 */ - writew(0x0000, ®s->wcr); - - /* Write Service Sequence */ - writew(0x5555, ®s->wsr); - writew(0xAAAA, ®s->wsr); - - /* Enable watchdog */ - writew(WCR_WDE, ®s->wcr); - - while (1); - /*NOTREACHED*/ -} diff --git a/arch/arm/cpu/arm926ejs/mx27/timer.c b/arch/arm/cpu/arm926ejs/mx27/timer.c deleted file mode 100644 index 4fd6a805968..00000000000 --- a/arch/arm/cpu/arm926ejs/mx27/timer.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2009 - * Ilya Yanok, Emcraft Systems Ltd, - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* General purpose timers bitfields */ -#define GPTCR_SWR (1 << 15) /* Software reset */ -#define GPTCR_FRR (1 << 8) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */ -#define GPTCR_TEN 1 /* Timer enable */ - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp (gd->arch.tbl) -#define lastinc (gd->arch.lastinc) - -/* - * "time" is measured in 1 / CONFIG_SYS_HZ seconds, - * "tick" is internal timer period - */ -#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION -/* ~0.4% error - measured with stop-watch on 100s boot-delay */ -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_MX27_CLK32); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - time *= CONFIG_MX27_CLK32; - do_div(time, CONFIG_SYS_HZ); - return time; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us = us * CONFIG_MX27_CLK32 + 999999; - do_div(us, 1000000); - return us; -} -#else -/* ~2% error */ -#define TICK_PER_TIME ((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \ - CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / CONFIG_MX27_CLK32) - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - do_div(tick, TICK_PER_TIME); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - return time * TICK_PER_TIME; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us += US_PER_TICK - 1; - do_div(us, US_PER_TICK); - return us; -} -#endif - -/* nothing really to do with interrupts, just starts up a counter. */ -/* The 32768Hz 32-bit timer overruns in 131072 seconds */ -int timer_init(void) -{ - int i; - struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE; - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - /* setup GP Timer 1 */ - writel(GPTCR_SWR, ®s->gpt_tctl); - - writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0); - writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1); - - for (i = 0; i < 100; i++) - writel(0, ®s->gpt_tctl); /* We have no udelay by now */ - writel(0, ®s->gpt_tprer); /* 32Khz */ - /* Freerun Mode, PERCLK1 input */ - writel(readl(®s->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, - ®s->gpt_tctl); - writel(readl(®s->gpt_tctl) | GPTCR_TEN, ®s->gpt_tctl); - - return 0; -} - -unsigned long long get_ticks(void) -{ - struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE; - ulong now = readl(®s->gpt_tcn); /* current tick value */ - - if (now >= lastinc) { - /* - * normal mode (non roll) - * move stamp forward with absolut diff ticks - */ - timestamp += (now - lastinc); - } else { - /* we have rollover of incrementer */ - timestamp += (0xFFFFFFFF - lastinc) + now; - } - lastinc = now; - return timestamp; -} - -static ulong get_timer_masked(void) -{ - /* - * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ - * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in - * 5 * 10^6 days - long enough. - */ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds AND preserve advance timstamp value */ -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = us_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - /*NOP*/; -} - -ulong get_tbclk(void) -{ - return CONFIG_MX27_CLK32; -} diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c index 22fd541f9a2..6de0ce91524 100644 --- a/arch/arm/lib/asm-offsets.c +++ b/arch/arm/lib/asm-offsets.c @@ -15,8 +15,7 @@ #include #include -#if defined(CONFIG_MX27) \ - || defined(CONFIG_MX51) || defined(CONFIG_MX53) +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) #include #endif @@ -35,32 +34,6 @@ int main(void) * code. Is it better to define the macros directly in headers? */ -#if defined(CONFIG_MX27) - DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); - DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); - DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); - DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); - - DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); - DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); - DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); - DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); - DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); - DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); - DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); - - DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); - DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); - DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); - DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); - DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); - - DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + - offsetof(struct system_control_regs, gpcr)); - DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + - offsetof(struct system_control_regs, fmcr)); -#endif - #if defined(CONFIG_MX51) || defined(CONFIG_MX53) /* Round up to make sure size gives nice stack alignment */ DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 03471db9e80..1dec4e35e0a 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -44,13 +44,13 @@ static unsigned long gpio_ports[] = { [0] = GPIO1_BASE_ADDR, [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, -#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ +#if defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050) [3] = GPIO4_BASE_ADDR, #endif -#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050) [4] = GPIO5_BASE_ADDR, @@ -352,12 +352,12 @@ static const struct mxc_gpio_plat mxc_plat[] = { { 0, (struct gpio_regs *)GPIO1_BASE_ADDR }, { 1, (struct gpio_regs *)GPIO2_BASE_ADDR }, { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, -#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ +#if defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, #endif -#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { 4, (struct gpio_regs *)GPIO5_BASE_ADDR }, #ifndef CONFIG_IMX8M @@ -376,12 +376,12 @@ U_BOOT_DRVINFOS(mxc_gpios) = { { "gpio_mxc", &mxc_plat[0] }, { "gpio_mxc", &mxc_plat[1] }, { "gpio_mxc", &mxc_plat[2] }, -#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ +#if defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[3] }, #endif -#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[4] }, #ifndef CONFIG_IMX8M diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index fa903e324c5..8aa5f734213 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -12,8 +12,7 @@ #include #include #include -#if defined(CONFIG_MX27) || \ - defined(CONFIG_MX51) || defined(CONFIG_MX53) +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) #include #endif #include "mxc_nand.h" diff --git a/drivers/mtd/nand/raw/mxc_nand.h b/drivers/mtd/nand/raw/mxc_nand.h index 771f61e2491..084fac705a1 100644 --- a/drivers/mtd/nand/raw/mxc_nand.h +++ b/drivers/mtd/nand/raw/mxc_nand.h @@ -24,7 +24,7 @@ * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. * Also some of registers are moved and/or changed meaning as seen below. */ -#if defined(CONFIG_MX27) || defined(CONFIG_MX31) +#if defined(CONFIG_MX31) #define MXC_NFC_V1 #define is_mxc_nfc_1() 1 #define is_mxc_nfc_21() 0 diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index bbc4434ddb9..a61a1fc7573 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -251,9 +251,6 @@ static int miiphy_restart_aneg(struct eth_device *dev) * Wake up from sleep if necessary * Reset PHY, then delay 300ns */ -#ifdef CONFIG_MX27 - fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); -#endif fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); udelay(1000); diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 5adfdf8b5fc..ea9cc3d1f98 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -91,14 +91,6 @@ struct cspi_regs { #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ #endif -#ifdef CONFIG_MX27 -/* i.MX27 has a completely wrong register layout and register definitions in the - * datasheet, the correct one is in the Freescale's Linux driver */ - -#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ -"See linux mxc_spi driver from Freescale for details." -#endif - __weak int board_spi_cs_gpio(unsigned bus, unsigned cs) { return -1; diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h deleted file mode 100644 index b0abd548826..00000000000 --- a/include/configs/imx27lite-common.h +++ /dev/null @@ -1,134 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Heiko Schocher - * - * based on: - * Copyright (C) 2009 Ilya Yanok - */ - -#ifndef __IMX27LITE_COMMON_CONFIG_H -#define __IMX27LITE_COMMON_CONFIG_H - -/* - * SoC Configuration - */ -#define CONFIG_MX27 -#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ - -/* - * Lowlevel configuration - */ -#define SDRAM_ESDCFG_REGISTER_VAL(cas) \ - (ESDCFG_TRC(10) | \ - ESDCFG_TRCD(3) | \ - ESDCFG_TCAS(cas) | \ - ESDCFG_TRRD(1) | \ - ESDCFG_TRAS(5) | \ - ESDCFG_TWR | \ - ESDCFG_TMRD(2) | \ - ESDCFG_TRP(2) | \ - ESDCFG_TXP(3)) - -#define SDRAM_ESDCTL_REGISTER_VAL \ - (ESDCTL_PRCT(0) | \ - ESDCTL_BL | \ - ESDCTL_PWDT(0) | \ - ESDCTL_SREFR(3) | \ - ESDCTL_DSIZ_32 | \ - ESDCTL_COL10 | \ - ESDCTL_ROW13 | \ - ESDCTL_SDE) - -#define SDRAM_ALL_VAL 0xf00 - -#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ -#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 - -#define MPCTL0_VAL 0x1ef15d5 - -#define SPCTL0_VAL 0x043a1c09 - -#define CSCR_VAL 0x33f08107 - -#define PCDR0_VAL 0x120470c3 -#define PCDR1_VAL 0x03030303 -#define PCCR0_VAL 0xffffffff -#define PCCR1_VAL 0xfffffffc - -#define AIPI1_PSR0_VAL 0x20040304 -#define AIPI1_PSR1_VAL 0xdffbfcfb -#define AIPI2_PSR0_VAL 0x07ffc200 -#define AIPI2_PSR1_VAL 0xffffffff - -/* - * Memory Info - */ -/* memtest start address */ -#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ - -/* - * Serial Driver info - */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) - -/* - * Flash & Environment - */ -/* Use buffered writes (~10x faster) */ -/* Use hardware sector protection */ -/* CS2 Base address */ -#define PHYS_FLASH_1 0xc0000000 -/* Flash Base for U-Boot */ -#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 -/* Address and size of Redundant Environment Sector */ - -/* - * Ethernet - */ -#define CONFIG_FEC_MXC_PHYADDR 0x1f - -/* - * MTD - */ - -/* - * NAND - */ -#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 -#define CFG_SYS_NAND_BASE 0xd8000000 -#define CONFIG_MXC_NAND_HWECC - -/* - * U-Boot general configuration - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "kernel_addr_r=a0800000\0" \ - "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ - "rootpath=/opt/eldk-4.2-arm/arm\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm\0" \ - "bootcmd=run net_nfs\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - -/* additions for new relocation code, must be added to all boards */ -#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#endif /* __IMX27LITE_COMMON_CONFIG_H */ -- cgit v1.3.1 From 6c03a652755ca415e3a1fa92525b5a8c230c9289 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:28 -0500 Subject: Convert CONFIG_MXS_OCOTP to Kconfig This converts the following to Kconfig: CONFIG_MXS_OCOTP Signed-off-by: Tom Rini --- drivers/misc/Kconfig | 8 ++++++++ include/configs/mxs.h | 5 ----- 2 files changed, 8 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index fb3bbb3b919..122d605a537 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -330,6 +330,14 @@ config MXC_OCOTP Programmable memory pages that are stored on the some Freescale i.MX processors. +config MXS_OCOTP + bool "Enable MXS OCOTP Driver" + depends on ARCH_MX23 || ARCH_MX28 + help + If you say Y here, you will get support for the One Time + Programmable memory pages that are stored on the + Freescale i.MXS family of processors. + config NPCM_HOST bool "Enable support espi or LPC for Host" depends on REGMAP && SYSCON diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 5df080ade4a..30f27e7f0c1 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -86,11 +86,6 @@ #define CFG_SYS_NAND_BASE 0x60000000 #endif -/* OCOTP */ -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXS_OCOTP -#endif - /* SPI */ #ifdef CONFIG_CMD_SPI #define CONFIG_SPI_HALF_DUPLEX -- cgit v1.3.1 From 9200011e9563c2deb71eae3c6769a92ea4e6c733 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:29 -0500 Subject: Convert CONFIG_NAND_KMETER1 et al to Kconfig This converts the following to Kconfig: CONFIG_NAND_ECC_BCH CONFIG_NAND_KIRKWOOD CONFIG_NAND_KMETER1 Signed-off-by: Tom Rini --- arch/arm/mach-kirkwood/include/mach/config.h | 1 - configs/kmcoge5ne_defconfig | 1 + drivers/mtd/nand/raw/Kconfig | 13 +++++++++++++ include/configs/km/km-mpc83xx.h | 1 - include/configs/kmcoge5ne.h | 2 -- 5 files changed, 14 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index a2781e25a23..a6de7676294 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -34,7 +34,6 @@ * NAND configuration */ #ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_KIRKWOOD #define CFG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ #define NAND_ALLOW_ERASE_ALL 1 #endif diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 71d196533f7..c2a17c6212f 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -235,6 +235,7 @@ CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_KMETER1=y CONFIG_DM_ETH_PHY=y CONFIG_QE_UEC=y # CONFIG_PCI is not set diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index eb37b627599..338a3562a4a 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -225,6 +225,19 @@ config NAND_FSL_IFC help Enable the Freescale Integrated Flash Controller NAND driver. +config NAND_KIRKWOOD + bool "Support for Kirkwood NAND controller" + depends on ARCH_KIRKWOOD + default y + +config NAND_ECC_BCH + bool + +config NAND_KMETER1 + bool "Support KMETER1 NAND controller" + depends on VENDOR_KM + select NAND_ECC_BCH + config NAND_LPC32XX_MLC bool "Support LPC32XX_MLC controller" select SYS_NAND_SELF_INIT diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index e6a3613b7a2..840a4d5401f 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -57,7 +57,6 @@ {1, {I2C_NULL_HOP} } } #if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 #define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE #endif diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 2be996aaaf0..c24d6ad8bc2 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -9,8 +9,6 @@ #define __CONFIG_H #define CONFIG_HOSTNAME "kmcoge5ne" -#define CONFIG_NAND_ECC_BCH -#define CONFIG_NAND_KMETER1 #define NAND_MAX_CHIPS 1 #define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ -- cgit v1.3.1 From c3187fb1448baf142d43fcc3d6f0e88e082050b9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:30 -0500 Subject: Convert CONFIG_PCA953X to Kconfig This converts the following to Kconfig: CONFIG_PCA953X Cc: Uri Mashiach Signed-off-by: Tom Rini --- README | 2 -- configs/cl-som-imx7_defconfig | 1 + drivers/gpio/Kconfig | 4 ++++ include/configs/cl-som-imx7.h | 1 - include/configs/imx8qxp_mek.h | 4 ---- include/configs/mx6sabreauto.h | 1 - 6 files changed, 5 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/README b/README index 0a7635d1a24..eb76c73ac3d 100644 --- a/README +++ b/README @@ -483,8 +483,6 @@ The following options need to be configured: must also be configured. See I2C Support, below. - GPIO Support: - CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO - The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of chip-ngpio pairs that tell the PCA953X driver the number of pins supported by a particular chip. diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index 3571dba6d2a..d1a044e3f7b 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -74,6 +74,7 @@ CONFIG_ETHPRIME="FEC" CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_CMD_PCA953X=y +CONFIG_PCA953X=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e007b38fac7..1e4b50ef72b 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -520,6 +520,10 @@ config SPL_DM_PCA953X Now, max 24 bits chips and PCA953X compatible chips are supported +config PCA953X + bool "NXP's PCA953X series I2C GPIO (legacy driver)" + depends on !DM_PCA953X + config MPC8XXX_GPIO bool "Freescale MPC8XXX GPIO driver" depends on DM_GPIO diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 4aaa52f2698..5c9004cbd93 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -21,7 +21,6 @@ /* PMIC */ #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 -#define CONFIG_PCA953X #define CFG_SYS_I2C_PCA953X_ADDR 0x20 #define CFG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 19f1dba0470..d75b8bf0c18 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -110,10 +110,6 @@ /* LPDDR4 board total DDR is 3GB */ #define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ -#ifndef CONFIG_DM_PCA953X -#define CONFIG_PCA953X -#endif - /* Misc configuration */ #endif /* __IMX8QXP_MEK_H */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index f5f95a1bd1c..888da7ce365 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -15,7 +15,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_PCA953X #define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } #include "mx6sabre_common.h" -- cgit v1.3.1 From ea467ea1cda0c9f6b85be34b5e1bbb6f905fa814 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:31 -0500 Subject: Convert CONFIG_RTC_DS1337 et al to Kconfig This converts the following to Kconfig: CONFIG_RTC_DS1337 CONFIG_RTC_DS1337_NOOSC CONFIG_RTC_DS1338 CONFIG_RTC_DS1374 CONFIG_RTC_DS3231 CONFIG_RTC_MC13XXX CONFIG_RTC_MXS CONFIG_RTC_PT7C4338 Signed-off-by: Tom Rini --- README | 22 -------------- configs/MPC837XERDB_defconfig | 1 + configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PA_NAND_defconfig | 1 + configs/P1010RDB-PA_NOR_defconfig | 1 + configs/P1010RDB-PA_SDCARD_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_NAND_defconfig | 1 + configs/P1010RDB-PB_NOR_defconfig | 1 + configs/P1010RDB-PB_SDCARD_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 1 + configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 1 + configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig | 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 1 + configs/P2020RDB-PC_SDCARD_defconfig | 1 + configs/P2020RDB-PC_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_defconfig | 1 + configs/T1024RDB_NAND_defconfig | 1 + configs/T1024RDB_SDCARD_defconfig | 1 + configs/T1024RDB_SPIFLASH_defconfig | 1 + configs/T1024RDB_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 1 + configs/T1042D4RDB_SDCARD_defconfig | 1 + configs/T1042D4RDB_SPIFLASH_defconfig | 1 + configs/T1042D4RDB_defconfig | 1 + configs/eb_cpu5282_defconfig | 1 + configs/eb_cpu5282_internal_defconfig | 1 + configs/ls2080aqds_SECURE_BOOT_defconfig | 1 + configs/ls2080aqds_defconfig | 1 + configs/ls2080aqds_nand_defconfig | 1 + configs/ls2080aqds_qspi_defconfig | 1 + configs/ls2080aqds_sdcard_defconfig | 1 + configs/ls2080ardb_SECURE_BOOT_defconfig | 1 + configs/ls2080ardb_defconfig | 1 + configs/ls2080ardb_nand_defconfig | 1 + configs/ls2088aqds_tfa_defconfig | 1 + configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_qspi_defconfig | 1 + configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_tfa_defconfig | 1 + configs/mx28evk_defconfig | 1 + configs/mx51evk_defconfig | 1 + configs/qemu-ppce500_defconfig | 1 + configs/work_92105_defconfig | 1 + drivers/rtc/Kconfig | 42 ++++++++++++++++++++++++++- include/configs/MPC837XERDB.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/T102xRDB.h | 2 -- include/configs/T104xRDB.h | 2 -- include/configs/eb_cpu5282.h | 1 - include/configs/ls1012aqds.h | 1 - include/configs/ls1046afrwy.h | 1 - include/configs/ls1088aqds.h | 1 - include/configs/ls1088ardb.h | 3 -- include/configs/ls2080aqds.h | 2 -- include/configs/ls2080ardb.h | 2 -- include/configs/lx2160a_common.h | 1 - include/configs/mx28evk.h | 5 ---- include/configs/mx51evk.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/qemu-ppce500.h | 3 -- include/configs/tqma6_wru4.h | 2 -- include/configs/work_92105.h | 2 -- 84 files changed, 105 insertions(+), 55 deletions(-) (limited to 'include') diff --git a/README b/README index eb76c73ac3d..dd43a0c08d4 100644 --- a/README +++ b/README @@ -460,28 +460,6 @@ The following options need to be configured: to 0 disables calling WATCHDOG_RESET() from the timer interrupt. -- Real-Time Clock: - - When CONFIG_CMD_DATE is selected, the type of the RTC - has to be selected, too. Define exactly one of the - following options: - - CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC - CONFIG_RTC_MC13XXX - use MC13783 or MC13892 RTC - CONFIG_RTC_MC146818 - use MC146818 RTC - CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC - CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC - CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC - CONFIG_RTC_DS1339 - use Maxim, Inc. DS1339 RTC - CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC - CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC - CONFIG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337 - CONFIG_SYS_RV3029_TCR - enable trickle charger on - RV3029 RTC. - - Note that if the RTC uses I2C, then the I2C interface - must also be configured. See I2C Support, below. - - GPIO Support: The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of chip-ngpio pairs that tell the PCA953X driver the number of diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index e6289fe104d..b00655824e2 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -207,6 +207,7 @@ CONFIG_DM_ETH_PHY=y CONFIG_RGMII=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_RTC_DS1374=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index a3d9a8b4b76..b32837c778c 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -129,6 +129,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 2ca02503993..575d5bffcb2 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -93,6 +93,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 5d57aa3ba4b..21c752d9747 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -114,6 +114,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index a13b48c20ec..a514d4ba36d 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -116,6 +116,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index a9c7652fab0..db71e9bce4e 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -128,6 +128,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index a0277d0aa61..291c4a40380 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -92,6 +92,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index f43a5a0c542..8237da39c27 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -113,6 +113,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index ef52f948827..9cb53d64e23 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -115,6 +115,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 2b2744dd74e..95746971087 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -132,6 +132,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 29b7d848095..7b3919dc162 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -95,6 +95,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 98164d2bade..3ad137dbd56 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -116,6 +116,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index d74fbecfaa1..cde657ce007 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -118,6 +118,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index efd0a7eb896..1faeab2c3b3 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -131,6 +131,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 44e98b9520f..190d02fa504 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -94,6 +94,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 9c650437660..5e32768c28d 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -115,6 +115,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 4b967352f4d..bce763c73bf 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -117,6 +117,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index b65e6518787..79df4a8f011 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -142,6 +142,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 034a971bc8b..d70db00236e 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -124,6 +124,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 9476c28e98b..b885a2a5f33 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -126,6 +126,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index ecd5e978c8b..710a41915c2 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -104,6 +104,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 80f4d22518c..f40e001b51a 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -141,6 +141,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 50fc0c124e8..e320ea9b428 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -123,6 +123,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index dafb430e4c0..d6a188c27e9 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -125,6 +125,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 411b4f05a44..b369b2fad3c 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -103,6 +103,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 8b0b6e4e680..7e31f130be1 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -144,6 +144,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 6a17f085a7f..f671d0b1d5a 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -126,6 +126,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 2738b208f16..109f03b3b8f 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -128,6 +128,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index fdd7703f72c..7f8cba1483b 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -106,6 +106,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 5904aa54b29..228c5f9e89a 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -147,6 +147,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 938148df93a..ca2b37fcb2f 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -129,6 +129,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index c4a41c4c0eb..f83360a87ae 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -131,6 +131,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index a4ed8fb39cd..524101022d5 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -109,6 +109,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 9b4ca39d34f..4f22e240b20 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -146,6 +146,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index a6d98b42ce1..84e0b4e1a1a 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -128,6 +128,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index b3e4a1f0d0e..a0ce9a9533f 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -130,6 +130,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index f1a9c058caa..e15c487c427 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -108,6 +108,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index f21c53d59f1..e51db832637 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -129,6 +129,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x200000 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 6f9f5a2603a..5472cccff8f 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -123,6 +123,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 76a59604f2f..0dd725128c5 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -126,6 +126,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index a4825909e7a..8a2096c56d9 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -98,6 +98,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0xEFE00000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 1aa0e9eec17..cc6a80447c0 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -129,6 +129,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x380000 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index ba1820e93a2..cb270adc37f 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -123,6 +123,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 98cd9b71e03..79530eac8fd 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -126,6 +126,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index f6301a57cfd..a671ae3d879 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -98,6 +98,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0xEFF10000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index f904bb313bb..a831c1c5d2a 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -52,4 +52,5 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 CONFIG_MCFFEC=y CONFIG_MII=y +CONFIG_RTC_DS1338=y CONFIG_MCFUART=y diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index 2ce6ff91403..6a673c91811 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -50,4 +50,5 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 CONFIG_MCFFEC=y CONFIG_MII=y +CONFIG_RTC_DS1338=y CONFIG_MCFUART=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index f66f5298366..d449b42aa3b 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -95,6 +95,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index d601c083e28..973537aaebe 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -98,6 +98,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index e2b6044d1fa..4fc44194931 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -111,6 +111,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 8abd58d53eb..4cd1c85852f 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -91,6 +91,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index 389b32b2d6d..52566582ca3 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -105,6 +105,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index e4d15dda14d..15bc69ec47d 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -92,6 +92,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index 4030fd4693b..88b5d239266 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -95,6 +95,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index b6e154b78b5..8339cf7232d 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -114,6 +114,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 09df15154e7..a9faa1525ac 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -111,6 +111,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 8cdfe5cc0bd..d3a113332de 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -80,6 +80,7 @@ CONFIG_MII=y CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 84c9f152665..f94142d0731 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -87,6 +87,7 @@ CONFIG_MII=y CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 3ac03305c7a..1dd7c1dd808 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -98,6 +98,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 41891d83ace..246ab403754 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -106,6 +106,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index 996dd5c9707..dad8839a6c1 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -61,6 +61,7 @@ CONFIG_PINCTRL_MXS=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RTC_MXS=y CONFIG_CONS_INDEX=0 CONFIG_SPI=y CONFIG_USB=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index 774523bc84b..b173648c8eb 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -56,6 +56,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_POWER_FSL=y CONFIG_POWER_SPI=y +CONFIG_RTC_MC13XXX=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index d6ff4ac2c29..cdad1b09950 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -52,6 +52,7 @@ CONFIG_E1000=y CONFIG_TSEC_ENET=y CONFIG_PCI_MPC85XX=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 127bbf715fc..167a07860fd 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -72,6 +72,7 @@ CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y +CONFIG_RTC_DS1374=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_CONS_INDEX=5 CONFIG_SYS_NS16550=y diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 23963271928..b6987225698 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -68,9 +68,38 @@ config RTC_DS1307 bool "Enable DS1307 driver" depends on DM_RTC help - Support for Dallas Semiconductor (now Maxim) DS1307 and DS1338/9 and + Support for Dallas Semiconductor (now Maxim) DS1307 and DS1339 and compatible Real Time Clock devices. +config RTC_DS1337 + bool "Enable DS1337 driver" + help + Support for Dallas Semiconductor (now Maxim) DS1337/8/9 compatible + Real Time Clock devices. + +config RTC_DS1337_NOOSC + bool "Enable support for no oscillator output in DS1337 driver" + depends on RTC_DS1337 + +config RTC_DS1338 + bool "Enable DS1338 driver" + help + Support for Dallas Semiconductor (now Maxim) DS1338 and compatible + Real Time Clock devices. + +config RTC_DS1374 + bool "Enable DS1374 driver" + depends on !DM_RTC + help + Support for Dallas Semiconductor (now Maxim) DS1374 and compatible + Real Time Clock devices. + +config RTC_DS3231 + bool "Enable DS3231 driver" + help + Support for Dallas Semiconductor (now Maxim) DS3231 compatible + Real Time Clock devices. + config RTC_DS3232 bool "Enable DS3232 driver" depends on DM_RTC @@ -111,6 +140,9 @@ config RTC_PCF8563 If you say yes here you get support for the Philips PCF8563 RTC and compatible chips. +config RTC_PT7C4338 + bool "Enable Pericom Technology PT7C4338 RTC driver" + config RTC_RV3028 bool "Enable RV3028 driver" depends on DM_RTC @@ -169,6 +201,10 @@ config RTC_S35392A help Enable s35392a driver which provides rtc get and set function. +config RTC_MC13XXX + bool "Enable MC13XXX RTC driver" + depends on !DM_RTC + config RTC_MC146818 bool "Enable MC146818 driver" help @@ -185,6 +221,10 @@ config SYS_MCFRTC_BASE hex "Base address for RTC in immap.h" depends on MCFRTC +config RTC_MXS + bool "Enable i.MXS RTC driver" + depends on ARCH_MX23 || ARCH_MX28 + config RTC_M41T62 bool "Enable M41T62 driver" help diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 2796adbdcd8..de63a0f1993 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -167,7 +167,6 @@ /* * Config on-board RTC */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ #define CFG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ /* diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 0a1b932e94e..c0805f979be 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -341,7 +341,6 @@ extern unsigned long get_sdram_size(void); /* enable read and write access to EEPROM */ /* RTC */ -#define CONFIG_RTC_PT7C4338 #define CFG_SYS_I2C_RTC_ADDR 0x68 /* diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e394237daf0..623d4cf5562 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -311,8 +311,6 @@ /* * RTC configuration */ -#define RTC -#define CONFIG_RTC_DS1337 1 #define CFG_SYS_I2C_RTC_ADDR 0x68 /* diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index f681a218229..d3fd10526bd 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -285,8 +285,6 @@ /* * RTC configuration */ -#define RTC -#define CONFIG_RTC_DS1337 1 #define CFG_SYS_I2C_RTC_ADDR 0x68 /*DVI encoder*/ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 426155dbdbf..21eab9b3a47 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -150,7 +150,6 @@ */ #ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1338 #define CONFIG_I2C_RTC_ADDR 0x68 #endif diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index e772c019077..495bb3911b3 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -46,7 +46,6 @@ /* * RTC configuration */ -#define RTC #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 58ae0fb0a6c..1759d25f3a3 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -66,7 +66,6 @@ #define I2C_MUX_CH_RTC 0x1 /* Channel 0*/ /* RTC */ -#define RTC #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ #define CFG_SYS_RTC_BUS_NUM 0 diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index d84622f3225..a35045d640f 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -280,7 +280,6 @@ /* * RTC configuration */ -#define RTC #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #ifdef CONFIG_FSL_DSPI diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 187b3072f02..7bc4fc6a665 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -186,13 +186,10 @@ #define I2C_MUX_CH_DEFAULT 0x8 #define I2C_MUX_CH5 0xD -#ifndef SPL_NO_RTC /* * RTC configuration */ -#define RTC #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ -#endif #ifndef SPL_NO_ENV /* Initial environment variables */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 067587b53c5..924d4057d93 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -227,8 +227,6 @@ /* * RTC configuration */ -#define RTC -#define CONFIG_RTC_DS3231 1 #define CFG_SYS_I2C_RTC_ADDR 0x68 /* Initial environment variables */ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 32a11948723..c50b6030680 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -210,11 +210,9 @@ /* * RTC configuration */ -#define RTC #ifdef CONFIG_TARGET_LS2081ARDB #define CFG_SYS_I2C_RTC_ADDR 0x51 #else -#define CONFIG_RTC_DS3231 1 #define CFG_SYS_I2C_RTC_ADDR 0x68 #endif diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index ff85d966e66..a469c83fa4e 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -74,7 +74,6 @@ #define I2C_MUX_CH_DEFAULT 0x8 /* RTC */ -#define RTC #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* Qixis */ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index bc8c8933704..c740d853327 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -17,11 +17,6 @@ /* UBI and NAND partitioning */ -/* RTC */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_MXS -#endif - /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ "ubifs_file=filesystem.ubifs\0" \ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index d9d76d7c08d..ddd37b3936f 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -26,7 +26,6 @@ #define CONFIG_FSL_PMIC_CLK 2500000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX /* * MMC Configs diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index eda2d43d0c1..c8acce8b06b 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -329,7 +329,6 @@ * I2C2 EEPROM */ -#define CONFIG_RTC_PT7C4338 #define CFG_SYS_I2C_RTC_ADDR 0x68 #define CFG_SYS_I2C_PCA9557_ADDR 0x18 diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index d1b20da24a8..30a9eae8523 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -44,9 +44,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* RTC */ -#define CONFIG_RTC_PT7C4338 - /* * Miscellaneous configurable options */ diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index ce897fcd932..4d8839b6e60 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -16,11 +16,9 @@ /* Watchdog */ /* Config on-board RTC */ -#define CONFIG_RTC_DS1337 #define CFG_SYS_RTC_BUS_NUM 2 #define CFG_SYS_I2C_RTC_ADDR 0x68 /* Turn off RTC square-wave output to save battery */ -#define CONFIG_RTC_DS1337_NOOSC /* LED */ diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 065006f912c..010da1531ff 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -19,8 +19,6 @@ #define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CFG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_RTC_DS1374 - /* * U-Boot General Configurations */ -- cgit v1.3.1 From 1c34f7885d7dc109b3ffa6e2c071bf777ed917e8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:32 -0500 Subject: Convert CONFIG_SH_GPIO_PFC et al to Kconfig This converts the following to Kconfig: CONFIG_SH_GPIO_PFC CONFIG_TMU_TIMER Signed-off-by: Tom Rini --- arch/arm/mach-rmobile/Kconfig.32 | 4 ++++ drivers/gpio/Kconfig | 5 +++++ include/configs/rcar-gen2-common.h | 5 ----- 3 files changed, 9 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32 index a07eff71dfe..31badc5a47d 100644 --- a/arch/arm/mach-rmobile/Kconfig.32 +++ b/arch/arm/mach-rmobile/Kconfig.32 @@ -8,6 +8,7 @@ config RCAR_GEN2 bool "Renesas RCar Gen2" select PHY select PHY_RCAR_GEN2 + select TMU_TIMER config R8A7740 bool "Renesas SoC R8A7740" @@ -121,6 +122,9 @@ config TARGET_STOUT endchoice +config TMU_TIMER + bool + config SYS_SOC default "rmobile" diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 1e4b50ef72b..365615a53f7 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -596,6 +596,11 @@ config ZYNQMP_GPIO_MODEPIN are accessed using xilinx firmware. In modepin register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits set/clear IO. +config SH_GPIO_PFC + bool "Pinmuxed GPIO support for SuperH" + depends on RCAR_GEN2 && !PINCTRL_PFC + default y + config SL28CPLD_GPIO bool "Kontron sl28cpld GPIO driver" depends on DM_GPIO && SL28CPLD diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index a86180ead57..291c2a43d4d 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -10,10 +10,6 @@ #include -#ifndef CONFIG_PINCTRL_PFC -#define CONFIG_SH_GPIO_PFC -#endif - /* console */ #define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 } @@ -21,7 +17,6 @@ #define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) /* Timer */ -#define CONFIG_TMU_TIMER #define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 8) -- cgit v1.3.1 From d91365203c06e0fbfa329e707196e9aa51241e4c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:33 -0500 Subject: Convert CONFIG_SMSC_LPC47M et al to Kconfig This converts the following to Kconfig: CONFIG_SMSC_LPC47M CONFIG_SMSC_SIO1007 Signed-off-by: Tom Rini --- configs/cougarcanyon2_defconfig | 1 + configs/crownbay_defconfig | 1 + drivers/misc/Kconfig | 6 ++++++ include/configs/cougarcanyon2.h | 2 -- include/configs/crownbay.h | 2 -- 5 files changed, 8 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 203eff8e165..8b47f2d89f8 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -52,6 +52,7 @@ CONFIG_SYSCON=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y +CONFIG_SMSC_SIO1007=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index cb0f0d7c8d0..038cbbe5b99 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -56,6 +56,7 @@ CONFIG_SYSCON=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y +CONFIG_SMSC_LPC47M=y CONFIG_E1000=y CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 122d605a537..b07261d3db5 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -112,6 +112,12 @@ config SIFIVE_OTP Enable support for reading and writing the eMemory OTP on the SiFive SoCs. +config SMSC_LPC47M + bool "LPC47M SMSC driver" + +config SMSC_SIO1007 + bool "SIO1007 SMSC driver" + config VEXPRESS_CONFIG bool "Enable support for Arm Versatile Express config bus" depends on MISC diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h index efd0b778435..b64c7df1b25 100644 --- a/include/configs/cougarcanyon2.h +++ b/include/configs/cougarcanyon2.h @@ -8,8 +8,6 @@ #include -#define CONFIG_SMSC_SIO1007 - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vga\0" \ "stderr=serial,vga\0" diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index e8a8af7e649..ff74deb3d40 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -12,8 +12,6 @@ #include -#define CONFIG_SMSC_LPC47M - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" -- cgit v1.3.1 From 8ce59b5932946b10d5abdd4b06577e7413bbec13 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:34 -0500 Subject: Convert CONFIG_SPD_EEPROM to Kconfig This converts the following to Kconfig: CONFIG_SPD_EEPROM Cc: Stefan Roese Signed-off-by: Tom Rini --- README | 7 ------- configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/socrates_defconfig | 1 + drivers/ddr/Kconfig | 8 ++++++++ include/configs/MPC8548CDS.h | 1 - include/configs/db-mv784mp-gp.h | 3 --- include/configs/socrates.h | 1 - 9 files changed, 12 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/README b/README index dd43a0c08d4..0acc0b41091 100644 --- a/README +++ b/README @@ -1683,13 +1683,6 @@ Low Level (hardware related) configuration options: Sets the EBC0_CFG register for the NDFC. If not defined a default value will be used. -- CONFIG_SPD_EEPROM - Get DDR timing information from an I2C EEPROM. Common - with pluggable memory modules such as SODIMMs - - SPD_EEPROM_ADDRESS - I2C address of the SPD EEPROM - - CONFIG_SYS_SPD_BUS_NUM If SPD EEPROM is on an I2C bus other than the first one, specify here. Note that the value must resolve diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 86a67d7b21f..517fd785dd3 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -45,6 +45,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC0" +CONFIG_SPD_EEPROM=y CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 2ac4f266850..5c83e808d57 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -44,6 +44,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC0" +CONFIG_SPD_EEPROM=y CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index faabd7bc045..b354237db3e 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -44,6 +44,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC0" +CONFIG_SPD_EEPROM=y CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index ab52ea26a08..f45f570764c 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -57,6 +57,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xFFF20000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="TSEC0" +CONFIG_SPD_EEPROM=y CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFE001001 diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig index 738b7884012..fa873cc4875 100644 --- a/drivers/ddr/Kconfig +++ b/drivers/ddr/Kconfig @@ -37,3 +37,11 @@ config SYS_SPD_BUS_NUM source "drivers/ddr/altera/Kconfig" source "drivers/ddr/imx/Kconfig" + +config SPD_EEPROM + bool "DDR controller makes use of an SPD EEPROM for JEDEC information" + depends on SYS_FSL_DDR || SYS_FSL_MMDC || CONFIG_ARMADA_XP + help + Get DDR timing information from an I2C EEPROM. Common with pluggable + memory modules such as SODIMMs. You must define SPD_EEPROM_ADDRESS + to the I2C address of the SPD EEPROM. diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 83eb18c3b7a..780ee5ae865 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -30,7 +30,6 @@ #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 7b305955c96..bf8b35102ad 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -45,7 +45,4 @@ /* SPL */ /* Defines for SPL */ -/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SPD_EEPROM 0x4e - #endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 0a2d5815170..95393d3ab25 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -50,7 +50,6 @@ #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -- cgit v1.3.1 From fcd7ba655e24c736c7f3a1d12fb98f1c9c2705b6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:35 -0500 Subject: Convert CONFIG_TPS6586X_POWER et al to Kconfig This converts the following to Kconfig: CONFIG_TPS6586X_POWER CONFIG_TWL6030_POWER Signed-off-by: Tom Rini --- configs/omap4_panda_defconfig | 1 + configs/omap4_sdp4430_defconfig | 1 + configs/seaboard_defconfig | 1 + drivers/power/Kconfig | 7 +++++++ include/configs/seaboard.h | 1 - include/configs/ti_omap4_common.h | 3 --- 6 files changed, 10 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig index 0cae1c61508..79807f104f5 100644 --- a/configs/omap4_panda_defconfig +++ b/configs/omap4_panda_defconfig @@ -45,6 +45,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y +CONFIG_TWL6030_POWER=y CONFIG_CONS_INDEX=3 CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig index e15c6d5cb13..e2f1bc67df5 100644 --- a/configs/omap4_sdp4430_defconfig +++ b/configs/omap4_sdp4430_defconfig @@ -42,6 +42,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y +CONFIG_TWL6030_POWER=y CONFIG_CONS_INDEX=3 CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index 686a3c062b1..2375040a9ec 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_TPS6586X_POWER=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 5dbcde333ba..7f3b990d231 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -411,6 +411,9 @@ config SY8106A_VOUT1_VOLT is typically used to power the VDD-CPU and should be 1200mV. Values can range from 680mV till 1950mV. +config TPS6586X_POWER + bool "Enable legacy driver for TI TPS6586x power management chip" + config TWL4030_POWER depends on OMAP34XX bool "Enable driver for TI TWL4030 power management chip" @@ -419,6 +422,10 @@ config TWL4030_POWER The TWL4030 in a combination audio CODEC/power management with GPIO and it is commonly used with the OMAP3 family of processors +config TWL6030_POWER + depends on OMAP44XX + bool "Enable driver for TI TWL6030 power management chip" + config POWER_MT6323 bool "Poweroff driver for mediatek mt6323" select CMD_POWEROFF diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 4887747968f..73b738bd099 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -12,7 +12,6 @@ /* LP0 suspend / resume */ #define CONFIG_TEGRA_LP0 #define CONFIG_TEGRA_PMU -#define CONFIG_TPS6586X_POWER #define CONFIG_TEGRA_CLOCK_SCALING #include "tegra20-common.h" diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 9a068e26140..64ec59d78eb 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -32,9 +32,6 @@ #define CFG_SYS_NS16550_COM3 UART3_BASE #endif -/* TWL6030 */ -#define CONFIG_TWL6030_POWER 1 - /* * Environment setup */ -- cgit v1.3.1 From b43295a27712c136afc68b0cf272e0356474642c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:36 -0500 Subject: Convert CONFIG_TEGRA_CLOCK_SCALING et al to Kconfig This converts the following to Kconfig: CONFIG_TEGRA_CLOCK_SCALING CONFIG_TEGRA_LP0 CONFIG_TEGRA_PMU Signed-off-by: Tom Rini --- arch/arm/mach-tegra/tegra20/Kconfig | 12 ++++++++++++ arch/arm/mach-tegra/tegra20/warmboot.c | 4 ---- include/configs/seaboard.h | 5 ----- 3 files changed, 12 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index 5c4d35b5673..345563fc789 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -1,5 +1,15 @@ if TEGRA20 +config TEGRA_LP0 + bool + select TEGRA_CLOCK_SCALING + +config TEGRA_PMU + bool + +config TEGRA_CLOCK_SCALING + bool + choice prompt "Tegra20 board select" optional @@ -23,6 +33,8 @@ config TARGET_PLUTUX config TARGET_SEABOARD bool "NVIDIA Seaboard" select BOARD_LATE_INIT + select TEGRA_LP0 + select TEGRA_PMU config TARGET_TEC bool "Avionic Design Tamonten Evaluation Carrier" diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 3d3758f6e6f..5e3a9ebaceb 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -23,10 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_TEGRA_CLOCK_SCALING -#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0" -#endif - /* * This is the place in SRAM where the SDRAM parameters are stored. There * are 4 blocks, one for each RAM code diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 73b738bd099..f272fe9bf8f 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -9,11 +9,6 @@ #include -/* LP0 suspend / resume */ -#define CONFIG_TEGRA_LP0 -#define CONFIG_TEGRA_PMU -#define CONFIG_TEGRA_CLOCK_SCALING - #include "tegra20-common.h" /* High-level configuration options */ -- cgit v1.3.1 From 08d01cda45d60af377e94fca05445d2fac232b8d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:37 -0500 Subject: Nokia RX-51: Migrate legacy USB device options to Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move a number of legacy USB UDC options to Kconfig, over from the config header. Cc: Pali Rohár Signed-off-by: Tom Rini --- README | 7 ------- board/nokia/rx51/Kconfig | 30 ++++++++++++++++++++++++++++++ include/configs/nokia_rx51.h | 9 --------- 3 files changed, 30 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/README b/README index 0acc0b41091..103562bbbe8 100644 --- a/README +++ b/README @@ -629,13 +629,6 @@ The following options need to be configured: variable usbtty to be cdc_acm should suffice. The following might be defined in YourBoardName.h - CONFIG_USB_DEVICE - Define this to build a UDC device - - CONFIG_USB_TTY - Define this to have a tty type of device available to - talk to the UDC device - CONFIG_USBD_HS Define this to enable the high speed support for usb device and usbtty. If this feature is enabled, a routine diff --git a/board/nokia/rx51/Kconfig b/board/nokia/rx51/Kconfig index 7cf05077dad..c884543a3d8 100644 --- a/board/nokia/rx51/Kconfig +++ b/board/nokia/rx51/Kconfig @@ -1,5 +1,35 @@ if TARGET_NOKIA_RX51 +config USB_DEVICE + def_bool y + help + Legacy UDC device support + +config USB_TTY + def_bool y + help + Legacy tty type of device available to talk to the UDC device + +config USBD_VENDORID + hex + default 0x0421 + +config USBD_PRODUCTID_CDCACM + hex + default 0x01c8 + +config USBD_PRODUCTID_GSERIAL + hex + default 0x01c8 + +config USBD_MANUFACTURER + string + default "Nokia" + +config USBD_PRODUCT_NAME + string + default "N900 (U-Boot)" + config NR_DRAM_BANKS default 2 diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 9c364adc636..caaa9ed86b3 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -49,15 +49,6 @@ #define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } -/* USB device configuration */ -#define CONFIG_USB_DEVICE -#define CONFIG_USB_TTY -#define CONFIG_USBD_VENDORID 0x0421 -#define CONFIG_USBD_PRODUCTID_CDCACM 0x01c8 -#define CONFIG_USBD_PRODUCTID_GSERIAL 0x01c8 -#define CONFIG_USBD_MANUFACTURER "Nokia" -#define CONFIG_USBD_PRODUCT_NAME "N900 (U-Boot)" - #define GPIO_SLIDE 71 /* -- cgit v1.3.1 From a9c3bce3626686efc9528c048e9296bb734d988c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:38 -0500 Subject: Convert CONFIG_USB_GADGET_AT91 to Kconfig This converts the following to Kconfig: CONFIG_USB_GADGET_AT91 Signed-off-by: Tom Rini --- configs/smartweb_defconfig | 1 + configs/taurus_defconfig | 1 + drivers/usb/gadget/Kconfig | 4 ++++ include/configs/smartweb.h | 4 ---- include/configs/taurus.h | 4 ---- 5 files changed, 6 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 601353c67a6..ed0ed2c7bb1 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -97,6 +97,7 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Siemens AG" CONFIG_USB_GADGET_VENDOR_NUM=0x0908 CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2 +CONFIG_USB_GADGET_AT91=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_WDT=y CONFIG_WDT_AT91=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index ef9e444a670..9a1dac78f12 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -115,6 +115,7 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Siemens AG" CONFIG_USB_GADGET_VENDOR_NUM=0x0908 CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2 +CONFIG_USB_GADGET_AT91=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_WDT=y CONFIG_WDT_AT91=y diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index e8da73c7886..e120efeb007 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -82,6 +82,10 @@ config USB_GADGET_BCM_UDC_OTG_PHY help Enable the Broadcom UDC OTG physical device interface. +config USB_GADGET_AT91 + bool "Atmel AT91 USB Gadget Controller" + depends on ARCH_AT91 + config USB_GADGET_DWC2_OTG bool "DesignWare USB2.0 HS OTG controller (gadget mode)" select USB_GADGET_DUALSPEED diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 794475942a2..b988b96e58d 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -64,10 +64,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -/* USB DFU support */ - -#define CONFIG_USB_GADGET_AT91 - /* DFU class support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 diff --git a/include/configs/taurus.h b/include/configs/taurus.h index baaf94e2dd5..30f84255820 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -62,10 +62,6 @@ #endif #if defined(CONFIG_BOARD_TAURUS) -/* USB DFU support */ - -#define CONFIG_USB_GADGET_AT91 - /* DFU class support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 #endif -- cgit v1.3.1 From be3bea2ba33bc731dbca72576f8b30c587c2e3b3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:39 -0500 Subject: Convert CONFIG_VSC7385_ENET et al to Kconfig This converts the following to Kconfig: CONFIG_VSC7385_ENET CONFIG_VSC9953 Signed-off-by: Tom Rini --- configs/MPC837XERDB_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 1 + configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 1 + configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig | 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 1 + configs/P2020RDB-PC_SDCARD_defconfig | 1 + configs/P2020RDB-PC_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_defconfig | 1 + drivers/net/Kconfig | 6 ++++++ include/configs/MPC837XERDB.h | 5 ----- include/configs/T104xRDB.h | 1 - include/configs/p1_p2_rdb_pc.h | 3 --- 25 files changed, 27 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index b00655824e2..1a571cf6bce 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -206,6 +206,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_ETH_PHY=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_RTC_DS1374=y CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 79df4a8f011..b9d52a755da 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -139,6 +139,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index d70db00236e..f86bc553da4 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -121,6 +121,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index b885a2a5f33..0b9e108ba58 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -123,6 +123,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 710a41915c2..9f68ede4bef 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -101,6 +101,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index f40e001b51a..3dd2475643d 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -138,6 +138,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index e320ea9b428..bd64dcc9ef4 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -120,6 +120,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index d6a188c27e9..140d271a197 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -122,6 +122,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index b369b2fad3c..3f653895abf 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -100,6 +100,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 7e31f130be1..abe064c04e9 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -141,6 +141,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index f671d0b1d5a..78a54dd461d 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -123,6 +123,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 109f03b3b8f..a8bdb5a2209 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -125,6 +125,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 7f8cba1483b..7a533ed41d7 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -103,6 +103,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 228c5f9e89a..3abb9d7f75b 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -144,6 +144,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index ca2b37fcb2f..551b5fca8e0 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -126,6 +126,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index f83360a87ae..493e2c94c14 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -128,6 +128,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 524101022d5..fc82fa8ab98 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -106,6 +106,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 4f22e240b20..b6ae81dd425 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -143,6 +143,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 84e0b4e1a1a..cfbb3c274ee 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -125,6 +125,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index a0ce9a9533f..36c6c7e26e6 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -127,6 +127,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index e15c487c427..691df7cc21b 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -105,6 +105,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 029bf3872aa..13e434e5913 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -676,6 +676,12 @@ config XILINX_AXIMRMAC rates from 10GE to 100GE. This could be present in some of the Xilinx Versal designs. +config VSC7385_ENET + bool "Vitesse 7385 Switch Firmware Upload driver" + +config VSC9953 + bool "Vitesse VSC9953 L2 Switch driver" + config XILINX_EMACLITE select PHYLIB select MII diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index de63a0f1993..95a90199a42 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -14,11 +14,6 @@ * High Level Configuration Options */ -/* - * On-board devices - */ -#define CONFIG_VSC7385_ENET - /* System performance - define the value i.e. CONFIG_SYS_XXX */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index d3fd10526bd..b6938056bbe 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -385,7 +385,6 @@ /* Enable VSC9953 L2 Switch driver on T1040 SoC */ #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) -#define CONFIG_VSC9953 #ifdef CONFIG_TARGET_T1040RDB #define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 #define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index c8acce8b06b..9738e9fa9cb 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -13,7 +13,6 @@ #include #if defined(CONFIG_TARGET_P1020RDB_PC) -#define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0x5c @@ -43,7 +42,6 @@ * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off */ #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0x64 @@ -63,7 +61,6 @@ #endif #if defined(CONFIG_TARGET_P2020RDB) -#define CONFIG_VSC7385_ENET #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xc8 #define __SW_BOOT_SPI 0x28 -- cgit v1.3.1 From 17f13e7119cc628bc26edf12252794770247df63 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:42 -0500 Subject: scripts/config_whitelist.txt: Remove more referenced symbols Perform some deeper investigation on the remaining symbols listed in this file and remove more. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- include/configs/P1010RDB.h | 2 -- scripts/config_whitelist.txt | 21 --------------------- 2 files changed, 23 deletions(-) (limited to 'include') diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index c0805f979be..b1d6b15811d 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -173,8 +173,6 @@ extern unsigned long get_sdram_size(void); #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE #endif -#define CONFIG_MTD_PARTITION - #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ccc3a731974..12c23a5dfdf 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1,5 +1,4 @@ CONFIG_ARM_GIC_BASE_ADDRESS -CONFIG_AUTO_ZRELADDR CONFIG_BOARDDIR CONFIG_DFU_ALT CONFIG_DFU_ALT_BOOT_EMMC @@ -8,7 +7,6 @@ CONFIG_DFU_ALT_SYSTEM CONFIG_DFU_ENV_SETTINGS CONFIG_DM9000_BASE CONFIG_DM9000_BYTE_SWAPPED -CONFIG_DM9000_DEBUG CONFIG_DM9000_NO_SROM CONFIG_DM9000_USE_16BIT CONFIG_DW_WDT_CLOCK_KHZ @@ -49,8 +47,6 @@ CONFIG_FSL_PMIC_MODE CONFIG_FSL_SDHC_V2_3 CONFIG_FSL_SERDES1 CONFIG_FSL_SERDES2 -CONFIG_FTRTC010_EXTCLK -CONFIG_FTRTC010_PCLK CONFIG_GATEWAYIP CONFIG_GMII CONFIG_G_DNL_THOR_PRODUCT_NUM @@ -64,7 +60,6 @@ CONFIG_HW_ENV_SETTINGS CONFIG_I2C_ENV_EEPROM_BUS CONFIG_I2C_MULTI_BUS CONFIG_I2C_MVTWSI -CONFIG_I2C_MVTWSI_BASE CONFIG_I2C_MVTWSI_BASE0 CONFIG_I2C_MVTWSI_BASE1 CONFIG_I2C_RTC_ADDR @@ -136,12 +131,8 @@ CONFIG_MIU_2BIT_INTERLEAVED CONFIG_MMC_DEFAULT_DEV CONFIG_MMC_SUNXI_SLOT CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC85XX_FEC -CONFIG_MPC85XX_FEC_NAME CONFIG_MTD_NAND_VERIFY_WRITE -CONFIG_MTD_PARTITION CONFIG_MVGBE_PORTS -CONFIG_MVS CONFIG_MXC_GPT_HCLK CONFIG_MXC_NAND_HWECC CONFIG_MXC_NAND_IP_REGS_BASE @@ -150,15 +141,10 @@ CONFIG_MXC_UART_BASE CONFIG_MXC_USB_FLAGS CONFIG_MXC_USB_PORT CONFIG_MXC_USB_PORTSC -CONFIG_MXS CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC CONFIG_NAND_CS_INIT -CONFIG_NAND_OMAP_GPMC_WSCFG -CONFIG_NAND_SECBOOT -CONFIG_NAND_SPL CONFIG_NETDEV CONFIG_NETMASK -CONFIG_NEVER_ASSERT_ODT_TO_CPU CONFIG_NORBOOT CONFIG_NUM_DSP_CPUS CONFIG_ODROID_REV_AIN @@ -174,12 +160,10 @@ CONFIG_PHY_INTERFACE_MODE CONFIG_PHY_IRAM_BASE CONFIG_PL011_CLOCK CONFIG_PL01x_PORTS -CONFIG_PM CONFIG_PME_PLAT_CLK_DIV CONFIG_POST CONFIG_POSTBOOTMENU CONFIG_POST_EXTERNAL_WORD_FUNCS -CONFIG_POST_SKIP_ENV_FLAGS CONFIG_POWER_LTC3676_I2C_ADDR CONFIG_POWER_PFUZE100_I2C_ADDR CONFIG_POWER_PFUZE3000_I2C_ADDR @@ -204,7 +188,6 @@ CONFIG_SCIF_A CONFIG_SCSI_DEV_LIST CONFIG_SC_TIMER_CLK CONFIG_SERIAL_BOOT -CONFIG_SERIAL_SOFTWARE_FIFO CONFIG_SERVERIP CONFIG_SETUP_INITRD_TAG CONFIG_SET_DFU_ALT_BUF_LEN @@ -213,14 +196,12 @@ CONFIG_SH_ETHER_CACHE_INVALIDATE CONFIG_SH_ETHER_CACHE_WRITEBACK CONFIG_SH_ETHER_PHY_ADDR CONFIG_SH_ETHER_PHY_MODE -CONFIG_SH_ETHER_SH7734_MII CONFIG_SH_ETHER_USE_PORT CONFIG_SH_QSPI_BASE CONFIG_SLIC CONFIG_SMDK5420 CONFIG_SMP_PEN_ADDR CONFIG_SOCRATES -CONFIG_SOFT_I2C_READ_REPEATED_START CONFIG_SPI_ADDR CONFIG_SPI_BOOTING CONFIG_SPI_FLASH_QUAD @@ -244,7 +225,6 @@ CONFIG_TESTPIN_MASK CONFIG_TESTPIN_REG CONFIG_THOR_RESET_OFF CONFIG_TPM_TIS_BASE_ADDRESS -CONFIG_TSEC CONFIG_TSEC1 CONFIG_TSEC1_NAME CONFIG_TSEC2 @@ -262,7 +242,6 @@ CONFIG_UBOOTPATH CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_UEC_ETH -CONFIG_UEC_ETH2 CONFIG_USART_BASE CONFIG_USART_ID CONFIG_USBD_HS -- cgit v1.3.1 From d948c8988c212bc8fe94db556b7ef265d2e96452 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:43 -0500 Subject: sandbox: Rework how SDL is enabled / disabled Given that we can use Kconfig logic directly to see if we have a program available on the host or not, change from passing NO_SDL to instead controlling CONFIG_SANDBOX_SDL in Kconfig directly. Introduce CONFIG_HOST_HAS_SDL as the way to test for sdl2-config and default CONFIG_SANDBOX_SDL on if we have that, or not. Cc: Simon Glass Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- .azure-pipelines.yml | 4 ++-- arch/sandbox/Kconfig | 7 +++++++ arch/sandbox/config.mk | 4 +--- doc/arch/sandbox/sandbox.rst | 9 +++------ doc/build/tools.rst | 2 +- drivers/video/Kconfig | 2 +- include/configs/sandbox.h | 4 ---- 7 files changed, 15 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index d02c6636ffa..add8847225f 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -30,7 +30,7 @@ stages: %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel" displayName: 'Install Toolchain' - script: | - echo make tools-only_defconfig tools-only NO_SDL=1 > build-tools.sh + echo make tools-only_defconfig tools-only > build-tools.sh %CD:~0,2%\msys64\usr\bin\bash -lc "bash build-tools.sh" displayName: 'Build Host Tools' env: @@ -47,7 +47,7 @@ stages: - script: brew install make ossp-uuid displayName: Brew install dependencies - script: | - gmake tools-only_config tools-only NO_SDL=1 \ + gmake tools-only_config tools-only \ HOSTCFLAGS="-I/usr/local/opt/openssl@1.1/include" \ HOSTLDFLAGS="-L/usr/local/opt/openssl@1.1/lib" \ -j$(sysctl -n hw.logicalcpu) diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 96b3402b47c..0ce77de2fcb 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -47,6 +47,13 @@ config HOST_32BIT config HOST_64BIT def_bool $(cc-define,_LP64) +config HOST_HAS_SDL + def_bool $(success,sdl2-config --version) + +config SANDBOX_SDL + bool "Enable SDL2 support in sandbox" + default HOST_HAS_SDL + config SANDBOX_CRASH_RESET bool "Reset on crash" help diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 3e2c7f9ebe5..1284ef390b5 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -8,9 +8,7 @@ SDL_CONFIG ?= sdl2-config # Define this to avoid linking with SDL, which requires SDL libraries # This can solve 'sdl-config: Command not found' errors -ifneq ($(NO_SDL),) -PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL -else +ifeq ($(CONFIG_SANDBOX_SDL),y) PLATFORM_LIBS += $(shell $(SDL_CONFIG) --libs) PLATFORM_CPPFLAGS += $(shell $(SDL_CONFIG) --cflags) endif diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst index 34c4e06d9b8..e6d84036516 100644 --- a/doc/arch/sandbox/sandbox.rst +++ b/doc/arch/sandbox/sandbox.rst @@ -56,11 +56,8 @@ To run sandbox U-Boot use something like:: Note: If you get errors about 'sdl-config: Command not found' you may need to install libsdl2.0-dev or similar to get SDL support. Alternatively you can -build sandbox without SDL (i.e. no display/keyboard support) by removing -the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using:: - - make sandbox_defconfig all NO_SDL=1 - ./u-boot +build sandbox without SDL (i.e. no display/keyboard support) by disabling +CONFIG_SANDBOX_SDL in the .config file. U-Boot will start on your computer, showing a sandbox emulation of the serial console:: @@ -84,7 +81,7 @@ To exit, type 'poweroff' or press Ctrl-C. Console / LCD support --------------------- -Assuming that CONFIG_SANDBOX_SDL is defined when building, you can run the +Assuming that CONFIG_SANDBOX_SDL is enabled when building, you can run the sandbox with LCD and keyboard emulation, using something like:: ./u-boot -d u-boot.dtb -l diff --git a/doc/build/tools.rst b/doc/build/tools.rst index c06f9152741..ec017229258 100644 --- a/doc/build/tools.rst +++ b/doc/build/tools.rst @@ -44,4 +44,4 @@ applications using a linux toolchain (gcc, bash, etc), targeting respectively Launch the MSYS2 shell of the MSYS2 environment, and do the following:: $ make tools-only_defconfig - $ make tools-only NO_SDL=1 + $ make tools-only diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index c841b99bb30..f539977d9b7 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -622,7 +622,7 @@ config VIDEO_ARM_MALIDP config VIDEO_SANDBOX_SDL bool "Enable sandbox video console using SDL" - depends on SANDBOX + depends on SANDBOX_SDL help When using sandbox you can enable an emulated LCD display which appears as an SDL (Simple DirectMedia Layer) window. This is a diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 1779f1894e7..8d9af7f088d 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -18,8 +18,4 @@ #define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} -#ifndef SANDBOX_NO_SDL -#define CONFIG_SANDBOX_SDL -#endif - #endif -- cgit v1.3.1 From 9cebc4ad8ebe6832c6d0eca786a85533a3b54ce4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:44 -0500 Subject: post: Migrate to Kconfig We move the existing CONFIG_POST_* functionality over to CFG_POST and then introduce CONFIG_POST to Kconfig. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- configs/P2041RDB_NAND_defconfig | 1 + configs/P2041RDB_SDCARD_defconfig | 1 + configs/P2041RDB_SPIFLASH_defconfig | 1 + configs/P2041RDB_defconfig | 1 + configs/kmcent2_defconfig | 1 + configs/kmcoge5ne_defconfig | 1 + configs/pg_wcom_expu1_defconfig | 1 + configs/pg_wcom_expu1_update_defconfig | 1 + configs/pg_wcom_seli8_defconfig | 1 + configs/pg_wcom_seli8_update_defconfig | 1 + doc/README.POST | 6 +-- doc/README.fsl-ddr | 2 +- drivers/serial/serial-uclass.c | 2 +- drivers/serial/serial.c | 2 +- include/configs/P2041RDB.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 4 +- include/configs/kmcent2.h | 2 +- include/configs/kmcoge5ne.h | 4 +- include/post.h | 4 +- include/serial.h | 4 +- post/cpu/mpc83xx/ecc.c | 2 +- post/drivers/flash.c | 2 +- post/drivers/i2c.c | 4 +- post/drivers/memory.c | 4 +- post/drivers/rtc.c | 4 +- post/lib_powerpc/andi.c | 2 +- post/lib_powerpc/asm.S | 2 +- post/lib_powerpc/b.c | 2 +- post/lib_powerpc/cmp.c | 2 +- post/lib_powerpc/cmpi.c | 2 +- post/lib_powerpc/complex.c | 2 +- post/lib_powerpc/cpu.c | 4 +- post/lib_powerpc/cr.c | 2 +- post/lib_powerpc/fpu/20001122-1.c | 4 +- post/lib_powerpc/fpu/20010114-2.c | 4 +- post/lib_powerpc/fpu/20010226-1.c | 4 +- post/lib_powerpc/fpu/980619-1.c | 4 +- post/lib_powerpc/fpu/acc1.c | 4 +- post/lib_powerpc/fpu/compare-fp-1.c | 4 +- post/lib_powerpc/fpu/fpu.c | 4 +- post/lib_powerpc/fpu/mul-subnormal-single-1.c | 4 +- post/lib_powerpc/load.c | 2 +- post/lib_powerpc/multi.c | 2 +- post/lib_powerpc/rlwimi.c | 2 +- post/lib_powerpc/rlwinm.c | 2 +- post/lib_powerpc/rlwnm.c | 2 +- post/lib_powerpc/srawi.c | 2 +- post/lib_powerpc/store.c | 2 +- post/lib_powerpc/string.c | 2 +- post/lib_powerpc/three.c | 2 +- post/lib_powerpc/threei.c | 2 +- post/lib_powerpc/threex.c | 2 +- post/lib_powerpc/two.c | 2 +- post/lib_powerpc/twox.c | 2 +- post/post.c | 4 +- post/tests.c | 68 +++++++++++++-------------- test/Kconfig | 5 ++ 58 files changed, 114 insertions(+), 99 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 74ad7483dc1..be85c54e480 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -486,7 +486,7 @@ int dram_init(void) #endif /* CONFIG_SYS_RAMBOOT */ #endif -#if CONFIG_POST & CFG_SYS_POST_MEMORY +#if CFG_POST & CFG_SYS_POST_MEMORY /* Board-specific functions defined in each board's ddr.c */ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 3d24b1a78c1..f495205f5bd 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -112,3 +112,4 @@ CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 +CONFIG_POST=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index cec55a1412b..23a7b66fbcb 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -107,3 +107,4 @@ CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 +CONFIG_POST=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 5fcf1546423..7dfbde04693 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -109,3 +109,4 @@ CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 +CONFIG_POST=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index ce198e28cb8..aea0b89f97d 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -104,3 +104,4 @@ CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 +CONFIG_POST=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index 48ac85b699b..41b26287d56 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -110,3 +110,4 @@ CONFIG_FS_CRAMFS=y CONFIG_BCH=y CONFIG_PANIC_HANG=y CONFIG_LZO=y +CONFIG_POST=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index c2a17c6212f..013277c9bf1 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -243,3 +243,4 @@ CONFIG_QE_UEC=y CONFIG_QE=y CONFIG_SYS_NS16550=y CONFIG_BCH=y +CONFIG_POST=y diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index ed55f7bfd0a..d21e180d1fc 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -100,3 +100,4 @@ CONFIG_SCSI_AHCI_PLAT=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_POST=y diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index 64ddaf8aa61..54773b06339 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -98,3 +98,4 @@ CONFIG_SCSI_AHCI_PLAT=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_POST=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index ad08e3582e3..8311b3a3a00 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -100,3 +100,4 @@ CONFIG_SCSI_AHCI_PLAT=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_POST=y diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index 01a6198d727..d6f4a054790 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -98,3 +98,4 @@ CONFIG_SCSI_AHCI_PLAT=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_POST=y diff --git a/doc/README.POST b/doc/README.POST index 1d1c25bdf9e..5d92f3fe6e9 100644 --- a/doc/README.POST +++ b/doc/README.POST @@ -242,11 +242,11 @@ storage server and etc. All POST-related code will be #ifdef'ed with the CONFIG_POST macro. This macro will be defined in the config_.h file for those -boards that need POST. The CONFIG_POST macro will contain the list of +boards that need POST. The CFG_POST macro will contain the list of POST tests for the board. The macro will have the format of array composed of post_test structures: -#define CONFIG_POST \ +#define CFG_POST \ { "On-board peripherals test", "board", \ " This test performs full check-up of the " \ @@ -257,7 +257,7 @@ composed of post_test structures: A new file, post.h, will be created in the include/ directory. This file will contain common POST declarations and will define a set of -macros that will be reused for defining CONFIG_POST. As an example, +macros that will be reused for defining CFG_POST. As an example, the following macro may be defined: #define POST_CACHE \ diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index cec5d94df4a..10e63f3be1d 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -137,7 +137,7 @@ Memory testing options for mpc85xx 2. Memory test can be done with Power-On-Self-Test function, activated at compile time. - In order to enable the POST memory test, CONFIG_POST needs to be + In order to enable the POST memory test, CFG_POST needs to be defined in board configuraiton header file. By default, POST memory test performs a fast test. A slow test can be enabled by changing the flag at compiling time. To test memory bigger than 2GB, 36BIT support is needed. diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 8a489a2e3f9..c02106747a0 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -526,7 +526,7 @@ static int serial_post_probe(struct udevice *dev) ops->getconfig += gd->reloc_off; if (ops->setconfig) ops->setconfig += gd->reloc_off; -#if CONFIG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CONFIG_SYS_POST_UART if (ops->loop) ops->loop += gd->reloc_off; #endif diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 4d549650948..369a8e38e3e 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -458,7 +458,7 @@ void default_serial_puts(const char *s) dev->putc(*s++); } -#if CONFIG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CONFIG_SYS_POST_UART static const int bauds[] = CFG_SYS_BAUDRATE_TABLE; /** diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index acbd43419f2..8b901ca47a0 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -41,7 +41,7 @@ */ #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_POST CFG_SYS_POST_MEMORY /* test POST memory test */ +#define CFG_POST CFG_SYS_POST_MEMORY /* test POST memory test */ /* * Config the L3 Cache as L3 SRAM diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index c1174b87ab7..dfa81c037f4 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -25,8 +25,8 @@ #define SPD_EEPROM_ADDRESS 0x54 /* POST memory regions test */ -#define CONFIG_POST (CFG_SYS_POST_MEM_REGIONS) -#define CONFIG_POST_EXTERNAL_WORD_FUNCS +#define CFG_POST (CFG_SYS_POST_MEM_REGIONS) +#define CFG_POST_EXTERNAL_WORD_FUNCS /* * IFC Definitions diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 89c5a24ee90..527f0383bc6 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -148,7 +148,7 @@ #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E /* POST memory regions test */ -#define CONFIG_POST CFG_SYS_POST_MEM_REGIONS +#define CFG_POST CFG_SYS_POST_MEM_REGIONS /* * Config the L3 Cache as L3 SRAM diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index c24d6ad8bc2..6b30fb4b617 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -33,8 +33,8 @@ CSCONFIG_COL_BIT_10) /* enable POST tests */ -#define CONFIG_POST (CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) -#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ +#define CFG_POST (CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) +#define CFG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ diff --git a/include/post.h b/include/post.h index 867a66f3007..e68d5c89020 100644 --- a/include/post.h +++ b/include/post.h @@ -16,7 +16,7 @@ #if defined(CONFIG_POST) -#ifndef CONFIG_POST_EXTERNAL_WORD_FUNCS +#ifndef CFG_POST_EXTERNAL_WORD_FUNCS #ifdef CONFIG_SYS_POST_WORD_ADDR #define _POST_WORD_ADDR CONFIG_SYS_POST_WORD_ADDR #else @@ -51,7 +51,7 @@ static inline void post_word_store (ulong value) extern ulong post_word_load(void); extern void post_word_store(ulong value); -#endif /* CONFIG_POST_EXTERNAL_WORD_FUNCS */ +#endif /* CFG_POST_EXTERNAL_WORD_FUNCS */ #endif /* defined (CONFIG_POST) */ #endif /* __ASSEMBLY__ */ diff --git a/include/serial.h b/include/serial.h index fe01bcfadb9..f4d7dc58a9e 100644 --- a/include/serial.h +++ b/include/serial.h @@ -14,7 +14,7 @@ struct serial_device { int (*tstc)(void); void (*putc)(const char c); void (*puts)(const char *s); -#if CONFIG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CONFIG_SYS_POST_UART void (*loop)(int); #endif struct serial_device *next; @@ -242,7 +242,7 @@ struct dm_serial_ops { * @return 0 if OK, -ve on error */ int (*clear)(struct udevice *dev); -#if CONFIG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CONFIG_SYS_POST_UART /** * loop() - Control serial device loopback mode * diff --git a/post/cpu/mpc83xx/ecc.c b/post/cpu/mpc83xx/ecc.c index edd74115672..45263e6b44c 100644 --- a/post/cpu/mpc83xx/ecc.c +++ b/post/cpu/mpc83xx/ecc.c @@ -17,7 +17,7 @@ #include #include -#if CONFIG_POST & CONFIG_SYS_POST_ECC +#if CFG_POST & CONFIG_SYS_POST_ECC /* * We use the RAW I/O accessors where possible in order to * achieve performance goal, since the test's execution time diff --git a/post/drivers/flash.c b/post/drivers/flash.c index 7d65f46d9fe..e157d369110 100644 --- a/post/drivers/flash.c +++ b/post/drivers/flash.c @@ -6,7 +6,7 @@ * Licensed under the GPL-2 or later. */ -#if CONFIG_POST & CONFIG_SYS_POST_FLASH +#if CFG_POST & CONFIG_SYS_POST_FLASH #include #include #include diff --git a/post/drivers/i2c.c b/post/drivers/i2c.c index 3b378921faf..057454ffd8f 100644 --- a/post/drivers/i2c.c +++ b/post/drivers/i2c.c @@ -26,7 +26,7 @@ #include #include -#if CONFIG_POST & CONFIG_SYS_POST_I2C +#if CFG_POST & CONFIG_SYS_POST_I2C static int i2c_ignore_device(unsigned int chip) { @@ -94,4 +94,4 @@ int i2c_post_test (int flags) #endif } -#endif /* CONFIG_POST & CONFIG_SYS_POST_I2C */ +#endif /* CFG_POST & CONFIG_SYS_POST_I2C */ diff --git a/post/drivers/memory.c b/post/drivers/memory.c index 71dad7b8c02..1be2b41df45 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -138,7 +138,7 @@ #include #include -#if CONFIG_POST & (CFG_SYS_POST_MEMORY | CFG_SYS_POST_MEM_REGIONS) +#if CFG_POST & (CFG_SYS_POST_MEMORY | CFG_SYS_POST_MEM_REGIONS) DECLARE_GLOBAL_DATA_PTR; @@ -535,4 +535,4 @@ int memory_post_test(int flags) return ret; } -#endif /* CONFIG_POST&(CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) */ +#endif /* CFG_POST&(CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) */ diff --git a/post/drivers/rtc.c b/post/drivers/rtc.c index c603f0e6728..cfed56b680c 100644 --- a/post/drivers/rtc.c +++ b/post/drivers/rtc.c @@ -26,7 +26,7 @@ #include #include -#if CONFIG_POST & CONFIG_SYS_POST_RTC +#if CFG_POST & CONFIG_SYS_POST_RTC static int rtc_post_skip (ulong * diff) { @@ -189,4 +189,4 @@ int rtc_post_test (int flags) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_RTC */ +#endif /* CFG_POST & CONFIG_SYS_POST_RTC */ diff --git a/post/lib_powerpc/andi.c b/post/lib_powerpc/andi.c index d4f60aa7388..d69d61396bc 100644 --- a/post/lib_powerpc/andi.c +++ b/post/lib_powerpc/andi.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/asm.S b/post/lib_powerpc/asm.S index 91b599932ff..13302d79689 100644 --- a/post/lib_powerpc/asm.S +++ b/post/lib_powerpc/asm.S @@ -10,7 +10,7 @@ #include #include -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU /* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */ .global cpu_post_exec_02 diff --git a/post/lib_powerpc/b.c b/post/lib_powerpc/b.c index 0b02e9169e2..eb9371fa6b2 100644 --- a/post/lib_powerpc/b.c +++ b/post/lib_powerpc/b.c @@ -24,7 +24,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, diff --git a/post/lib_powerpc/cmp.c b/post/lib_powerpc/cmp.c index e70869774ce..e4d0931fc9a 100644 --- a/post/lib_powerpc/cmp.c +++ b/post/lib_powerpc/cmp.c @@ -23,7 +23,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/cmpi.c b/post/lib_powerpc/cmpi.c index 85a9b0ad36b..983892d0063 100644 --- a/post/lib_powerpc/cmpi.c +++ b/post/lib_powerpc/cmpi.c @@ -23,7 +23,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); diff --git a/post/lib_powerpc/complex.c b/post/lib_powerpc/complex.c index bb29e917012..d2ec21b0cbe 100644 --- a/post/lib_powerpc/complex.c +++ b/post/lib_powerpc/complex.c @@ -18,7 +18,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); extern int cpu_post_complex_2_asm (int x, int n); diff --git a/post/lib_powerpc/cpu.c b/post/lib_powerpc/cpu.c index 1d471073429..77c25381729 100644 --- a/post/lib_powerpc/cpu.c +++ b/post/lib_powerpc/cpu.c @@ -20,7 +20,7 @@ #include #include -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern int cpu_post_test_cmp (void); extern int cpu_post_test_cmpi (void); @@ -118,4 +118,4 @@ int cpu_post_test (int flags) return ret; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_CPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_CPU */ diff --git a/post/lib_powerpc/cr.c b/post/lib_powerpc/cr.c index 56ed355dde7..077fb0f2da3 100644 --- a/post/lib_powerpc/cr.c +++ b/post/lib_powerpc/cr.c @@ -33,7 +33,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); extern void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); diff --git a/post/lib_powerpc/fpu/20001122-1.c b/post/lib_powerpc/fpu/20001122-1.c index 4b452dc083d..eddd3f915ee 100644 --- a/post/lib_powerpc/fpu/20001122-1.c +++ b/post/lib_powerpc/fpu/20001122-1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU int fpu_post_test_math1 (void) { @@ -40,4 +40,4 @@ int fpu_post_test_math1 (void) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/20010114-2.c b/post/lib_powerpc/fpu/20010114-2.c index 4aadd1e0482..9e3e54661f9 100644 --- a/post/lib_powerpc/fpu/20010114-2.c +++ b/post/lib_powerpc/fpu/20010114-2.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU static float rintf (float x) { @@ -45,4 +45,4 @@ int fpu_post_test_math2 (void) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/20010226-1.c b/post/lib_powerpc/fpu/20010226-1.c index b09a25c2118..5bb38609003 100644 --- a/post/lib_powerpc/fpu/20010226-1.c +++ b/post/lib_powerpc/fpu/20010226-1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU int fpu_post_test_math3 (void) { @@ -33,4 +33,4 @@ int fpu_post_test_math3 (void) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/980619-1.c b/post/lib_powerpc/fpu/980619-1.c index 2fea708306c..415cd50c85d 100644 --- a/post/lib_powerpc/fpu/980619-1.c +++ b/post/lib_powerpc/fpu/980619-1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU int fpu_post_test_math4 (void) { @@ -39,4 +39,4 @@ int fpu_post_test_math4 (void) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/acc1.c b/post/lib_powerpc/fpu/acc1.c index 9e5783b2579..4cf3b7cef75 100644 --- a/post/lib_powerpc/fpu/acc1.c +++ b/post/lib_powerpc/fpu/acc1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU static double func (const double *array) { @@ -36,4 +36,4 @@ int fpu_post_test_math5 (void) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/compare-fp-1.c b/post/lib_powerpc/fpu/compare-fp-1.c index d46a13adcdf..029600fd2b7 100644 --- a/post/lib_powerpc/fpu/compare-fp-1.c +++ b/post/lib_powerpc/fpu/compare-fp-1.c @@ -15,7 +15,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU static int failed; @@ -204,4 +204,4 @@ int fpu_post_test_math6 (void) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/fpu.c b/post/lib_powerpc/fpu/fpu.c index bd65f623d50..8993b36e801 100644 --- a/post/lib_powerpc/fpu/fpu.c +++ b/post/lib_powerpc/fpu/fpu.c @@ -21,7 +21,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU #include @@ -71,4 +71,4 @@ int fpu_post_test (int flags) return ret; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/mul-subnormal-single-1.c b/post/lib_powerpc/fpu/mul-subnormal-single-1.c index cb61c9114d7..87b882c6b22 100644 --- a/post/lib_powerpc/fpu/mul-subnormal-single-1.c +++ b/post/lib_powerpc/fpu/mul-subnormal-single-1.c @@ -15,7 +15,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU union uf { @@ -82,4 +82,4 @@ int fpu_post_test_math7 (void) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/load.c b/post/lib_powerpc/load.c index 5269563b1e1..ece0b2756e0 100644 --- a/post/lib_powerpc/load.c +++ b/post/lib_powerpc/load.c @@ -28,7 +28,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); extern void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); diff --git a/post/lib_powerpc/multi.c b/post/lib_powerpc/multi.c index f082e4c546c..0e9ee88eb5d 100644 --- a/post/lib_powerpc/multi.c +++ b/post/lib_powerpc/multi.c @@ -21,7 +21,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_02(ulong *code, ulong op1, ulong op2); diff --git a/post/lib_powerpc/rlwimi.c b/post/lib_powerpc/rlwimi.c index 7b4dc79fb17..d24a3f665c7 100644 --- a/post/lib_powerpc/rlwimi.c +++ b/post/lib_powerpc/rlwimi.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/rlwinm.c b/post/lib_powerpc/rlwinm.c index 8a03e9b9bcb..9f4a3edb3ea 100644 --- a/post/lib_powerpc/rlwinm.c +++ b/post/lib_powerpc/rlwinm.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/rlwnm.c b/post/lib_powerpc/rlwnm.c index e2beb4e4171..224e6bdd45e 100644 --- a/post/lib_powerpc/rlwnm.c +++ b/post/lib_powerpc/rlwnm.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/srawi.c b/post/lib_powerpc/srawi.c index d4a8fabc425..713d4f2276b 100644 --- a/post/lib_powerpc/srawi.c +++ b/post/lib_powerpc/srawi.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/store.c b/post/lib_powerpc/store.c index 8e278fee885..2dbcccf098a 100644 --- a/post/lib_powerpc/store.c +++ b/post/lib_powerpc/store.c @@ -28,7 +28,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); extern void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); diff --git a/post/lib_powerpc/string.c b/post/lib_powerpc/string.c index 0d8d280b271..9b54847632a 100644 --- a/post/lib_powerpc/string.c +++ b/post/lib_powerpc/string.c @@ -20,7 +20,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); extern void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, diff --git a/post/lib_powerpc/three.c b/post/lib_powerpc/three.c index fc6f1f5674a..55f0ff8a882 100644 --- a/post/lib_powerpc/three.c +++ b/post/lib_powerpc/three.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/threei.c b/post/lib_powerpc/threei.c index f49c85e6b9d..ec52d238e69 100644 --- a/post/lib_powerpc/threei.c +++ b/post/lib_powerpc/threei.c @@ -21,7 +21,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/threex.c b/post/lib_powerpc/threex.c index 6bc5a54706b..6f5f0b8eb76 100644 --- a/post/lib_powerpc/threex.c +++ b/post/lib_powerpc/threex.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/two.c b/post/lib_powerpc/two.c index fa376c76b1b..b44dd4e2084 100644 --- a/post/lib_powerpc/two.c +++ b/post/lib_powerpc/two.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/twox.c b/post/lib_powerpc/twox.c index 5c36012a9b7..320cc0a64e7 100644 --- a/post/lib_powerpc/twox.c +++ b/post/lib_powerpc/twox.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); extern ulong cpu_post_makecr (long v); diff --git a/post/post.c b/post/post.c index b81425d8cf8..9964b410804 100644 --- a/post/post.c +++ b/post/post.c @@ -168,7 +168,7 @@ static void post_bootmode_test_off(void) post_word_store(word); } -#ifndef CONFIG_POST_SKIP_ENV_FLAGS +#ifndef CFG_POST_SKIP_ENV_FLAGS static void post_get_env_flags(int *test_flags) { int flag[] = { POST_POWERON, POST_NORMAL, POST_SLOWTEST, @@ -227,7 +227,7 @@ static void post_get_flags(int *test_flags) for (j = 0; j < post_list_size; j++) test_flags[j] = post_list[j].flags; -#ifndef CONFIG_POST_SKIP_ENV_FLAGS +#ifndef CFG_POST_SKIP_ENV_FLAGS post_get_env_flags(test_flags); #endif diff --git a/post/tests.c b/post/tests.c index fc36e738f73..d61ea74d512 100644 --- a/post/tests.c +++ b/post/tests.c @@ -45,7 +45,7 @@ extern void sysmon_reloc (void); struct post_test post_list[] = { -#if CONFIG_POST & CONFIG_SYS_POST_OCM +#if CFG_POST & CONFIG_SYS_POST_OCM { "OCM test", "ocm", @@ -57,7 +57,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_OCM }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_CACHE +#if CFG_POST & CONFIG_SYS_POST_CACHE { "Cache test", "cache", @@ -69,9 +69,9 @@ struct post_test post_list[] = CONFIG_SYS_POST_CACHE }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG -#if defined(CONFIG_POST_WATCHDOG) - CONFIG_POST_WATCHDOG, +#if CFG_POST & CONFIG_SYS_POST_WATCHDOG +#if defined(CFG_POST_WATCHDOG) + CFG_POST_WATCHDOG, #else { "Watchdog timer test", @@ -85,7 +85,7 @@ struct post_test post_list[] = }, #endif #endif -#if CONFIG_POST & CONFIG_SYS_POST_I2C +#if CFG_POST & CONFIG_SYS_POST_I2C { "I2C test", "i2c", @@ -97,7 +97,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_I2C }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_RTC +#if CFG_POST & CONFIG_SYS_POST_RTC { "RTC test", "rtc", @@ -109,7 +109,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_RTC }, #endif -#if CONFIG_POST & CFG_SYS_POST_MEMORY +#if CFG_POST & CFG_SYS_POST_MEMORY { "Memory test", "memory", @@ -121,7 +121,7 @@ struct post_test post_list[] = CFG_SYS_POST_MEMORY }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU { "CPU test", "cpu", @@ -134,7 +134,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_CPU }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU { "FPU test", "fpu", @@ -147,9 +147,9 @@ struct post_test post_list[] = CONFIG_SYS_POST_FPU }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_UART -#if defined(CONFIG_POST_UART) - CONFIG_POST_UART, +#if CFG_POST & CONFIG_SYS_POST_UART +#if defined(CFG_POST_UART) + CFG_POST_UART, #else { "UART test", @@ -161,9 +161,9 @@ struct post_test post_list[] = NULL, CONFIG_SYS_POST_UART }, -#endif /* CONFIG_POST_UART */ +#endif /* CFG_POST_UART */ #endif -#if CONFIG_POST & CONFIG_SYS_POST_ETHER +#if CFG_POST & CONFIG_SYS_POST_ETHER { "ETHERNET test", "ethernet", @@ -175,7 +175,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_ETHER }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_USB +#if CFG_POST & CONFIG_SYS_POST_USB { "USB test", "usb", @@ -187,7 +187,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_USB }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_SPR +#if CFG_POST & CONFIG_SYS_POST_SPR { "SPR test", "spr", @@ -199,7 +199,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_SPR }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_SYSMON +#if CFG_POST & CONFIG_SYS_POST_SYSMON { "SYSMON test", "sysmon", @@ -211,7 +211,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_SYSMON }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_DSP +#if CFG_POST & CONFIG_SYS_POST_DSP { "DSP test", "dsp", @@ -223,7 +223,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_DSP }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_CODEC +#if CFG_POST & CONFIG_SYS_POST_CODEC { "CODEC test", "codec", @@ -235,7 +235,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_CODEC }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_ECC +#if CFG_POST & CONFIG_SYS_POST_ECC { "ECC test", "ecc", @@ -247,22 +247,22 @@ struct post_test post_list[] = CONFIG_SYS_POST_ECC }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 - CONFIG_POST_BSPEC1, +#if CFG_POST & CONFIG_SYS_POST_BSPEC1 + CFG_POST_BSPEC1, #endif -#if CONFIG_POST & CONFIG_SYS_POST_BSPEC2 - CONFIG_POST_BSPEC2, +#if CFG_POST & CONFIG_SYS_POST_BSPEC2 + CFG_POST_BSPEC2, #endif -#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3 - CONFIG_POST_BSPEC3, +#if CFG_POST & CONFIG_SYS_POST_BSPEC3 + CFG_POST_BSPEC3, #endif -#if CONFIG_POST & CONFIG_SYS_POST_BSPEC4 - CONFIG_POST_BSPEC4, +#if CFG_POST & CONFIG_SYS_POST_BSPEC4 + CFG_POST_BSPEC4, #endif -#if CONFIG_POST & CONFIG_SYS_POST_BSPEC5 - CONFIG_POST_BSPEC5, +#if CFG_POST & CONFIG_SYS_POST_BSPEC5 + CFG_POST_BSPEC5, #endif -#if CONFIG_POST & CONFIG_SYS_POST_COPROC +#if CFG_POST & CONFIG_SYS_POST_COPROC { "Coprocessors communication test", "coproc_com", @@ -274,7 +274,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_COPROC }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_FLASH +#if CFG_POST & CONFIG_SYS_POST_FLASH { "Parallel NOR flash test", "flash", @@ -286,7 +286,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_FLASH }, #endif -#if CONFIG_POST & CFG_SYS_POST_MEM_REGIONS +#if CFG_POST & CFG_SYS_POST_MEM_REGIONS { "Memory regions test", "mem_regions", diff --git a/test/Kconfig b/test/Kconfig index a6b463e4d06..9f4641ae6bc 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -1,3 +1,8 @@ +config POST + bool "Power On Self Test support" + help + See doc/README.POST for more details + menuconfig UNIT_TEST bool "Unit tests" help -- cgit v1.3.1 From 7102d324f6b41741ee74587d43d77b302b1bbd96 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:45 -0500 Subject: m68k: Rename CONFIG_WATCHDOG_TIMEOUT to CONFIG_WATCHDOG_TIMEOUT_MSECS In practice, it is clear that the usage in m68k of CONFIG_WATCHDOG_TIMEOUT is setting a value in milliseconds. Rename this to the existing symbol and move to Kconfig. Signed-off-by: Tom Rini --- arch/m68k/cpu/mcf523x/cpu.c | 2 +- arch/m68k/cpu/mcf52x2/cpu.c | 6 +++--- arch/m68k/cpu/mcf532x/cpu.c | 2 +- configs/M5208EVBE_defconfig | 1 + configs/M5235EVB_Flash32_defconfig | 1 + configs/M5235EVB_defconfig | 1 + configs/M5272C3_defconfig | 1 + configs/M53017EVB_defconfig | 1 + configs/M5329AFEE_defconfig | 1 + configs/M5329BFEE_defconfig | 1 + configs/M5373EVB_defconfig | 1 + configs/astro_mcf5373l_defconfig | 1 + include/configs/M5208EVBE.h | 2 -- include/configs/M5235EVB.h | 2 -- include/configs/M5272C3.h | 2 -- include/configs/M53017EVB.h | 2 -- include/configs/M5329EVB.h | 2 -- include/configs/M5373EVB.h | 2 -- include/configs/astro_mcf5373l.h | 10 ---------- include/configs/cobra5272.h | 12 ------------ 20 files changed, 14 insertions(+), 39 deletions(-) (limited to 'include') diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c index 6d87908965d..ba2c2289119 100644 --- a/arch/m68k/cpu/mcf523x/cpu.c +++ b/arch/m68k/cpu/mcf523x/cpu.c @@ -92,7 +92,7 @@ int watchdog_init(void) u32 wdog_module = 0; /* set timeout and enable watchdog */ - wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT_MSECS); wdog_module |= (wdog_module / 8192); out_be16(&wdp->mr, wdog_module); diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c index d21d82fef75..d7cbf11e255 100644 --- a/arch/m68k/cpu/mcf52x2/cpu.c +++ b/arch/m68k/cpu/mcf52x2/cpu.c @@ -87,7 +87,7 @@ int watchdog_init(void) /* set timeout and enable watchdog */ out_be16(&wdt->mr, - (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1); /* reset watchdog counter */ out_be16(&wdt->sr, 0x5555); @@ -253,7 +253,7 @@ int watchdog_init(void) /* set timeout and enable watchdog */ out_be16(&wdt->wdog_wrrr, - (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1); /* reset watchdog counter */ out_be16(&wdt->wdog_wcr, 0); @@ -323,7 +323,7 @@ int watchdog_init(void) /* set timeout and enable watchdog */ out_be16(&wdt->wmr, - (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1); /* reset watchdog counter */ out_be16(&wdt->wsr, 0x5555); diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c index 8a48d73475c..548cbca36aa 100644 --- a/arch/m68k/cpu/mcf532x/cpu.c +++ b/arch/m68k/cpu/mcf532x/cpu.c @@ -131,7 +131,7 @@ int watchdog_init(void) u32 wdog_module = 0; /* set timeout and enable watchdog */ - wdog_module = ((CFG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module = ((CFG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT_MSECS); #ifdef CONFIG_M5329 out_be16(&wdp->mr, wdog_module / 8192); #else diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index fd219cbaebc..680c2d43671 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -43,3 +43,4 @@ CONFIG_SYS_MAX_FLASH_SECT=254 CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=5000 diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index 1b7b1568003..c0087aa67f9 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -50,3 +50,4 @@ CONFIG_SYS_MAX_FLASH_SECT=137 CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=5000 diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index fffcdddd491..b099e986067 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -50,3 +50,4 @@ CONFIG_SYS_MAX_FLASH_SECT=137 CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=5000 diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index 5e7d40144f9..a321b1c5c24 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -62,3 +62,4 @@ CONFIG_SYS_MAX_FLASH_SECT=137 CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=10000 diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index 6586f0468b2..32d19580880 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -49,3 +49,4 @@ CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=5000 diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index bf1d70f832c..9f0b4196392 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -48,3 +48,4 @@ CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=5000 diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index b83b542f8f8..05388796fb1 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -50,3 +50,4 @@ CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=5000 diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index 181f79b1e90..90d83216489 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -50,3 +50,4 @@ CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=3360 diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index afbcb86c034..9e5665a12b8 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -50,3 +50,4 @@ CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=3355 diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 246437a51e2..b360238b332 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -15,8 +15,6 @@ */ #define CFG_SYS_UART_PORT (0) -#define CONFIG_WATCHDOG_TIMEOUT 5000 - /* I2C */ #ifdef CONFIG_MCFFEC diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 128ef50b476..ed45eccb62c 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -20,8 +20,6 @@ #define CFG_SYS_UART_PORT (0) -#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ - /* I2C */ #define CFG_SYS_I2C_PINMUX_REG (gpio->par_qspi) #define CFG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 847b4c2593d..a9339e50525 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -19,8 +19,6 @@ #define CFG_SYS_UART_PORT (0) -#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ - #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ /* Configuration for environment diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 0e9ba4c3ada..42b74aeb9b5 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -20,8 +20,6 @@ #define CFG_SYS_UART_PORT (0) -#define CONFIG_WATCHDOG_TIMEOUT 5000 - #ifdef CONFIG_MCFFEC # define CFG_SYS_TX_ETH_BUFFER 8 # define CFG_SYS_FEC_BUF_USE_SRAM diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 8f83810f165..72f0c63a1e2 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -20,8 +20,6 @@ #define CFG_SYS_UART_PORT (0) -#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ - /* I2C */ #ifdef CONFIG_MCFFEC diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 43c642edeb1..4e8b54e01f4 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -22,8 +22,6 @@ #define CFG_SYS_UART_PORT (0) -#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ - /* I2C */ #ifdef CONFIG_MCFFEC diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index f5922fc416e..62aa99342a0 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -69,16 +69,6 @@ #define CFG_SYS_UART_PORT (2) #define CFG_SYS_UART2_ALT3_GPIO -/* - * Watchdog configuration; Watchdog is disabled for running from RAM - * and set to highest possible value else. Beware there is no check - * in the watchdog code to validate the timeout value set here! - */ - -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ -#endif - /* * Configuration for environment * Environment is located in the last sector of the flash diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 01828ea2011..6d6e2fc6962 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -42,18 +42,6 @@ #define CFG_SYS_UART_PORT (0) -/* --- - * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change - * timeout acc. to your needs - * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000 - * for 10 sec - * --- - */ - -#if 0 -#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ -#endif - /* --- * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different * bootloader residing in flash ('chainloading'); if you want to use -- cgit v1.3.1 From 2f420f135ffdc7d30834d640efb504261426afa3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:04 -0500 Subject: net: tsec: Remove non-DM_ETH support code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Doing this removes some board support code which was also unused. Finally, this removes some CONFIG symbols that otherwise needed to be migrated to Kconfig, but were unused in code now. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-ls102xa/config.h | 5 - arch/powerpc/include/asm/config_mpc85xx.h | 17 --- arch/powerpc/include/asm/immap_83xx.h | 5 - arch/powerpc/include/asm/immap_85xx.h | 8 -- board/freescale/common/pixis.c | 73 ---------- board/freescale/mpc8548cds/mpc8548cds.c | 82 ------------ board/freescale/p1010rdb/p1010rdb.c | 43 ------ board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 50 ------- drivers/net/tsec.c | 199 +--------------------------- include/configs/MPC837XERDB.h | 27 ---- include/configs/MPC8548CDS.h | 27 ---- include/configs/P1010RDB.h | 31 ----- include/configs/ls1021aiot.h | 21 --- include/configs/ls1021aqds.h | 26 ---- include/configs/p1_p2_rdb_pc.h | 21 --- include/configs/socrates.h | 16 --- include/tsec.h | 60 --------- 17 files changed, 1 insertion(+), 710 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 6413a307d27..14f86df5ed5 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -36,11 +36,6 @@ #define CFG_SYS_FSL_SEC_OFFSET 0x00700000 #define CFG_SYS_FSL_JR0_OFFSET 0x00710000 -#define CFG_SYS_TSEC1_OFFSET 0x01d10000 -#define CFG_SYS_MDIO1_OFFSET 0x01d24000 - -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d9e5a7d6217..1b5b4947f1a 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -24,18 +24,9 @@ #elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_TSECV2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -/* P1011 is single core version of P1020 */ -#elif defined(CONFIG_ARCH_P1011) -#define CONFIG_TSECV2 - -#elif defined(CONFIG_ARCH_P1020) -#define CONFIG_TSECV2 - #elif defined(CONFIG_ARCH_P1021) -#define CONFIG_TSECV2 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 @@ -47,13 +38,8 @@ #define CFG_SYS_BMAN_NUM_PORTALS 3 #define CFG_SYS_FM_MURAM_SIZE 0x10000 -/* P1024 is lower end variant of P1020 */ -#elif defined(CONFIG_ARCH_P1024) -#define CONFIG_TSECV2 - /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_ARCH_P1025) -#define CONFIG_TSECV2 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 @@ -108,12 +94,10 @@ #elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_TSECV2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_TSECV2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #elif defined(CONFIG_ARCH_T4240) @@ -221,7 +205,6 @@ #elif defined(CONFIG_ARCH_C29X) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_TSECV2_1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000 diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 19774f3053b..24bd438c143 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -873,9 +873,4 @@ struct ccsr_gpio { #define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) -#define CFG_SYS_TSEC1_OFFSET 0x24000 -#define CFG_SYS_MDIO1_OFFSET 0x24000 - -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #endif /* __IMMAP_83xx__ */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 283fdf3b458..7293720fb3c 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2541,13 +2541,6 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_USB2_OFFSET 0x23000 #define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000 #define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100 -#ifdef CONFIG_TSECV2 -#define CFG_SYS_TSEC1_OFFSET 0xB0000 -#elif defined(CONFIG_TSECV2_1) -#define CFG_SYS_TSEC1_OFFSET 0x10000 -#else -#define CFG_SYS_TSEC1_OFFSET 0x24000 -#endif #define CFG_SYS_MDIO1_OFFSET 0x24000 #define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #if defined(CONFIG_ARCH_C29X) @@ -2673,7 +2666,6 @@ struct ccsr_pman { #define CFG_SYS_SEC_MON_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_SEC_MON_OFFSET) -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index 6fdb11039e5..cb9f4549725 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -281,79 +281,6 @@ U_BOOT_CMD( "" ); -#ifdef CONFIG_PIXIS_SGMII_CMD - -/* Enable or disable SGMII mode for a TSEC - */ -static int pixis_set_sgmii(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - int which_tsec = -1; - unsigned char mask; - unsigned char switch_mask; - - if ((argc > 2) && (strcmp(argv[1], "all") != 0)) - which_tsec = simple_strtoul(argv[1], NULL, 0); - - switch (which_tsec) { -#ifdef CONFIG_TSEC1 - case 1: - mask = PIXIS_VSPEED2_TSEC1SER; - switch_mask = PIXIS_VCFGEN1_TSEC1SER; - break; -#endif -#ifdef CONFIG_TSEC2 - case 2: - mask = PIXIS_VSPEED2_TSEC2SER; - switch_mask = PIXIS_VCFGEN1_TSEC2SER; - break; -#endif -#ifdef CONFIG_TSEC3 - case 3: - mask = PIXIS_VSPEED2_TSEC3SER; - switch_mask = PIXIS_VCFGEN1_TSEC3SER; - break; -#endif -#ifdef CONFIG_TSEC4 - case 4: - mask = PIXIS_VSPEED2_TSEC4SER; - switch_mask = PIXIS_VCFGEN1_TSEC4SER; - break; -#endif - default: - mask = PIXIS_VSPEED2_MASK; - switch_mask = PIXIS_VCFGEN1_MASK; - break; - } - - /* Toggle whether the switches or FPGA control the settings */ - if (!strcmp(argv[argc - 1], "switch")) - clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask); - else - setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask); - - /* If it's not the switches, enable or disable SGMII, as specified */ - if (!strcmp(argv[argc - 1], "on")) - clrbits_8(pixis_base + PIXIS_VSPEED2, mask); - else if (!strcmp(argv[argc - 1], "off")) - setbits_8(pixis_base + PIXIS_VSPEED2, mask); - - return 0; -} - -U_BOOT_CMD( - pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii, - "pixis_set_sgmii" - " - Enable or disable SGMII mode for a given TSEC \n", - "\npixis_set_sgmii [TSEC num] \n" - " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n" - " on - enables SGMII\n" - " off - disables SGMII\n" - " switch - use switch settings" -); - -#endif - /* * This function takes the non-integral cpu:mpx pll ratio * and converts it to an integer that can be used to assign diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 73e024eaa01..ec6e3a2d0ab 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -168,85 +168,3 @@ void lbc_sdram_init(void) #endif /* enable SDRAM init */ } - -#ifndef CONFIG_DM_ETH -static void configure_rgmii(void) -{ - unsigned short temp; - - /* Change the resistors for the PHY */ - /* This is needed to get the RGMII working for the 1.3+ - * CDS cards */ - if (get_board_version() == 0x13) { - miiphy_write(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 29, 18); - - miiphy_read(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 30, &temp); - - temp = (temp & 0xf03f); - temp |= 2 << 9; /* 36 ohm */ - temp |= 2 << 6; /* 39 ohm */ - - miiphy_write(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 30, temp); - - miiphy_write(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 29, 3); - - miiphy_write(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 30, 0x8000); - } - - return; -} - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif -#ifdef CONFIG_TSEC3 - /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */ - if (get_board_version() >= 0x13) { - SET_STD_TSEC_INFO(tsec_info[num], 3); - tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; - num++; - } -#endif -#ifdef CONFIG_TSEC4 - /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */ - if (get_board_version() >= 0x13) { - SET_STD_TSEC_INFO(tsec_info[num], 4); - tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; - num++; - } -#endif - - if (!num) { - printf("No TSECs initialized\n"); - - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - configure_rgmii(); -#endif - - return pci_eth_init(bis); -} -#endif diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 0f014823c93..d32274b2481 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -478,49 +478,6 @@ int checkboard(void) return 0; } -#ifndef CONFIG_DM_ETH -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - struct cpu_type *cpu; - int num = 0; - - cpu = gd->arch.cpu; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif -#ifdef CONFIG_TSEC3 - /* P1014 and it's derivatives do not support eTSEC3 */ - if (cpu->soc_ver != SVR_P1014) { - SET_STD_TSEC_INFO(tsec_info[num], 3); - num++; - } -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); -#endif - - return pci_eth_init(bis); -} -#endif - #if defined(CONFIG_OF_BOARD_SETUP) void fdt_del_flexcan(void *blob) { diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index ab797244297..df9f6ae4732 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -364,56 +364,6 @@ int board_early_init_r(void) return 0; } -#ifndef CONFIG_DM_ETH -int board_eth_init(struct bd_info *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - ccsr_gur_t *gur __attribute__((unused)) = - (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - printf("eTSEC2 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - num++; -#endif - - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1); - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - -#if defined(CONFIG_UEC_ETH) - /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */ - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0); - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3); - - uec_standard_init(bis); -#endif - - return pci_eth_init(bis); -} -#endif - #if defined(CONFIG_OF_BOARD_SETUP) || defined(CONFIG_OF_BOARD_FIXUP) static void fix_max6370_watchdog(void *blob) { diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 8b6f034ea16..f465409d8c8 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -22,34 +22,6 @@ #include #include -#ifndef CONFIG_DM_ETH -/* Default initializations for TSEC controllers. */ - -static struct tsec_info_struct tsec_info[] = { -#ifdef CONFIG_TSEC1 - STD_TSEC_INFO(1), /* TSEC1 */ -#endif -#ifdef CONFIG_TSEC2 - STD_TSEC_INFO(2), /* TSEC2 */ -#endif -#ifdef CONFIG_MPC85XX_FEC - { - .regs = TSEC_GET_REGS(2, 0x2000), - .devname = CONFIG_MPC85XX_FEC_NAME, - .phyaddr = FEC_PHY_ADDR, - .flags = FEC_FLAGS, - .mii_devname = DEFAULT_MII_NAME - }, /* FEC */ -#endif -#ifdef CONFIG_TSEC3 - STD_TSEC_INFO(3), /* TSEC3 */ -#endif -#ifdef CONFIG_TSEC4 - STD_TSEC_INFO(4), /* TSEC4 */ -#endif -}; -#endif /* CONFIG_DM_ETH */ - #define TBIANA_SETTINGS ( \ TBIANA_ASYMMETRIC_PAUSE \ | TBIANA_SYMMETRIC_PAUSE \ @@ -124,23 +96,14 @@ static u32 ether_crc(size_t len, unsigned char const *p) * for PowerPC (tm) is usually the case) in the register holds * the entry. */ -#ifndef CONFIG_DM_ETH -static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, - int join) -#else static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join) -#endif { struct tsec_private *priv; struct tsec __iomem *regs; u32 result, value; u8 whichbit, whichreg; -#ifndef CONFIG_DM_ETH - priv = (struct tsec_private *)dev->priv; -#else priv = dev_get_priv(dev); -#endif regs = priv->regs; result = ether_crc(MAC_ADDR_LEN, mcast_mac); whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */ @@ -271,11 +234,7 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) * do the same. Presumably, this would be zero if there were no * errors */ -#ifndef CONFIG_DM_ETH -static int tsec_send(struct eth_device *dev, void *packet, int length) -#else static int tsec_send(struct udevice *dev, void *packet, int length) -#endif { struct tsec_private *priv; struct tsec __iomem *regs; @@ -283,11 +242,7 @@ static int tsec_send(struct udevice *dev, void *packet, int length) u16 status; int i; -#ifndef CONFIG_DM_ETH - priv = (struct tsec_private *)dev->priv; -#else priv = dev_get_priv(dev); -#endif regs = priv->regs; /* Find an empty buffer descriptor */ for (i = 0; @@ -324,42 +279,6 @@ static int tsec_send(struct udevice *dev, void *packet, int length) return result; } -#ifndef CONFIG_DM_ETH -static int tsec_recv(struct eth_device *dev) -{ - struct tsec_private *priv = (struct tsec_private *)dev->priv; - struct tsec __iomem *regs = priv->regs; - - while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) { - int length = in_be16(&priv->rxbd[priv->rx_idx].length); - u16 status = in_be16(&priv->rxbd[priv->rx_idx].status); - uchar *packet = net_rx_packets[priv->rx_idx]; - - /* Send the packet up if there were no errors */ - if (!(status & RXBD_STATS)) - net_process_received_packet(packet, length - 4); - else - printf("Got error %x\n", (status & RXBD_STATS)); - - out_be16(&priv->rxbd[priv->rx_idx].length, 0); - - status = RXBD_EMPTY; - /* Set the wrap bit if this is the last element in the list */ - if ((priv->rx_idx + 1) == PKTBUFSRX) - status |= RXBD_WRAP; - out_be16(&priv->rxbd[priv->rx_idx].status, status); - - priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX; - } - - if (in_be32(®s->ievent) & IEVENT_BSY) { - out_be32(®s->ievent, IEVENT_BSY); - out_be32(®s->rstat, RSTAT_CLEAR_RHALT); - } - - return -1; -} -#else static int tsec_recv(struct udevice *dev, int flags, uchar **packetp) { struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev); @@ -406,22 +325,12 @@ static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length) return 0; } -#endif -/* Stop the interface */ -#ifndef CONFIG_DM_ETH -static void tsec_halt(struct eth_device *dev) -#else static void tsec_halt(struct udevice *dev) -#endif { struct tsec_private *priv; struct tsec __iomem *regs; -#ifndef CONFIG_DM_ETH - priv = (struct tsec_private *)dev->priv; -#else priv = dev_get_priv(dev); -#endif regs = priv->regs; clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); @@ -583,27 +492,15 @@ static void startup_tsec(struct tsec_private *priv) * that it returns success if the link is up, failure otherwise. * This allows U-Boot to find the first active controller. */ -#ifndef CONFIG_DM_ETH -static int tsec_init(struct eth_device *dev, struct bd_info *bd) -#else static int tsec_init(struct udevice *dev) -#endif { struct tsec_private *priv; struct tsec __iomem *regs; -#ifdef CONFIG_DM_ETH struct eth_pdata *pdata = dev_get_plat(dev); -#else - struct eth_device *pdata = dev; -#endif u32 tempval; int ret; -#ifndef CONFIG_DM_ETH - priv = (struct tsec_private *)dev->priv; -#else priv = dev_get_priv(dev); -#endif regs = priv->regs; /* Make sure the controller is stopped */ tsec_halt(dev); @@ -715,7 +612,7 @@ static int init_phy(struct tsec_private *priv) if (priv->interface == PHY_INTERFACE_MODE_SGMII) tsec_configure_serdes(priv); -#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO) +#if defined(CONFIG_DM_MDIO) phydev = dm_eth_phy_connect(priv->dev); #else phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev, @@ -734,99 +631,6 @@ static int init_phy(struct tsec_private *priv) return 1; } -#ifndef CONFIG_DM_ETH -/* - * Initialize device structure. Returns success if PHY - * initialization succeeded (i.e. if it recognizes the PHY) - */ -static int tsec_initialize(struct bd_info *bis, - struct tsec_info_struct *tsec_info) -{ - struct tsec_private *priv; - struct eth_device *dev; - int i; - - dev = (struct eth_device *)malloc(sizeof(*dev)); - - if (!dev) - return 0; - - memset(dev, 0, sizeof(*dev)); - - priv = (struct tsec_private *)malloc(sizeof(*priv)); - - if (!priv) { - free(dev); - return 0; - } - - priv->regs = tsec_info->regs; - priv->phyregs_sgmii = tsec_info->miiregs_sgmii; - - priv->phyaddr = tsec_info->phyaddr; - priv->tbiaddr = CFG_SYS_TBIPA_VALUE; - priv->flags = tsec_info->flags; - - strcpy(dev->name, tsec_info->devname); - priv->interface = tsec_info->interface; - priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname); - priv->dev = dev; - dev->iobase = 0; - dev->priv = priv; - dev->init = tsec_init; - dev->halt = tsec_halt; - dev->send = tsec_send; - dev->recv = tsec_recv; - dev->mcast = tsec_mcast_addr; - - /* Tell U-Boot to get the addr from the env */ - for (i = 0; i < 6; i++) - dev->enetaddr[i] = 0; - - eth_register(dev); - - /* Reset the MAC */ - setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); - udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ - clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); - - /* Try to initialize PHY here, and return */ - return init_phy(priv); -} - -/* - * Initialize all the TSEC devices - * - * Returns the number of TSEC devices that were initialized - */ -int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsecs, - int num) -{ - int i; - int count = 0; - - for (i = 0; i < num; i++) { - int ret = tsec_initialize(bis, &tsecs[i]); - - if (ret > 0) - count += ret; - } - - return count; -} - -int tsec_standard_init(struct bd_info *bis) -{ - struct fsl_pq_mdio_info info; - - info.regs = TSEC_GET_MDIO_REGS_BASE(1); - info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &info); - - return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); -} -#else /* CONFIG_DM_ETH */ int tsec_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); @@ -966,4 +770,3 @@ U_BOOT_DRIVER(eth_tsec) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif /* CONFIG_DM_ETH */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 95a90199a42..f312ffb37e2 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -41,8 +41,6 @@ #ifdef CONFIG_VSC7385_ENET -#define CONFIG_TSEC2 - /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 #define CONFIG_VSC7385_IMAGE_SIZE 8192 @@ -178,31 +176,6 @@ #define CFG_SYS_PCIE2_MEM_PHYS 0xC8000000 #define CFG_SYS_PCIE2_IO_PHYS 0xD8000000 -/* - * TSEC - */ -#ifdef CONFIG_TSEC_ENET - -#define CONFIG_GMII /* MII PHY management */ - -#define CONFIG_TSEC1 - -#ifdef CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CFG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 2 -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC1_PHYIDX 0 -#endif - -#ifdef CONFIG_TSEC2 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC2_PHY_ADDR 0x1c -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_PHYIDX 0 -#endif -#endif - #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC_PIN_MUX #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 780ee5ae865..34b876f829e 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -283,33 +283,6 @@ #endif #define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC1" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC2" -#define CONFIG_TSEC4 -#define CONFIG_TSEC4_NAME "eTSEC3" -#undef CONFIG_MPC85XX_FEC - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC3_PHY_ADDR 2 -#define TSEC4_PHY_ADDR 3 - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC4_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#endif /* CONFIG_TSEC_ENET */ - /* * Miscellaneous configurable options */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index b1d6b15811d..4418d516956 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -349,37 +349,6 @@ extern unsigned long get_sdram_size(void); /* eSPI - Enhanced SPI */ #endif -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 1 -#define TSEC2_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 2 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -/* TBI PHY configuration for SGMII mode */ -#define CONFIG_TSEC_TBICR_SETTINGS ( \ - TBICR_PHY_RESET \ - | TBICR_ANEG_ENABLE \ - | TBICR_FULL_DUPLEX \ - | TBICR_SPEED1_SET \ - ) - -#endif /* CONFIG_TSEC_ENET */ - #ifdef CONFIG_MMC #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 024a7185275..179c5128e3b 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -66,27 +66,6 @@ /* SPI */ -/* - * eTSEC - */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_MII_DEFAULT_TSEC 1 -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -#define TSEC1_PHY_ADDR 1 -#define TSEC2_PHY_ADDR 3 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#endif - #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" #define CONFIG_PEN_ADDR_BIG_ENDIAN diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5a91cc3efec..d6681e85987 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -247,32 +247,6 @@ * MMC */ -/* - * eTSEC - */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_MII_DEFAULT_TSEC 3 -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 1 -#define TSEC2_PHY_ADDR 2 -#define TSEC3_PHY_ADDR 3 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#endif - #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 9738e9fa9cb..49c5aef3059 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -366,27 +366,6 @@ #endif #endif /* CONFIG_PCI */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#endif /* CONFIG_TSEC_ENET */ - /* * Environment */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 95393d3ab25..2a076716023 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -111,22 +111,6 @@ #define CFG_SYS_PCI1_MEM_PHYS 0x80000000 #define CFG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC - -#define TSEC1_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC3_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0,1] */ - /* * Miscellaneous configurable options */ diff --git a/include/tsec.h b/include/tsec.h index de279b21171..153337837a9 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -19,56 +19,6 @@ #define TSEC_MDIO_REGS_OFFSET 0x520 -#ifndef CONFIG_DM_ETH - -#ifdef CONFIG_ARCH_LS1021A -#define TSEC_SIZE 0x40000 -#define TSEC_MDIO_OFFSET 0x40000 -#else -#define TSEC_SIZE 0x01000 -#define TSEC_MDIO_OFFSET 0x01000 -#endif - -#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + TSEC_MDIO_REGS_OFFSET) - -#define TSEC_GET_REGS(num, offset) \ - (struct tsec __iomem *)\ - (TSEC_BASE_ADDR + (((num) - 1) * (offset))) - -#define TSEC_GET_REGS_BASE(num) \ - TSEC_GET_REGS((num), TSEC_SIZE) - -#define TSEC_GET_MDIO_REGS(num, offset) \ - (struct tsec_mii_mng __iomem *)\ - (CONFIG_SYS_MDIO_BASE_ADDR + ((num) - 1) * (offset)) - -#define TSEC_GET_MDIO_REGS_BASE(num) \ - TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET) - -#define DEFAULT_MII_NAME "FSL_MDIO" - -#define STD_TSEC_INFO(num) \ -{ \ - .regs = TSEC_GET_REGS_BASE(num), \ - .miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \ - .devname = CONFIG_TSEC##num##_NAME, \ - .phyaddr = TSEC##num##_PHY_ADDR, \ - .flags = TSEC##num##_FLAGS, \ - .mii_devname = DEFAULT_MII_NAME \ -} - -#define SET_STD_TSEC_INFO(x, num) \ -{ \ - x.regs = TSEC_GET_REGS_BASE(num); \ - x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \ - x.devname = CONFIG_TSEC##num##_NAME; \ - x.phyaddr = TSEC##num##_PHY_ADDR; \ - x.flags = TSEC##num##_FLAGS;\ - x.mii_devname = DEFAULT_MII_NAME;\ -} - -#endif /* CONFIG_DM_ETH */ - #define MAC_ADDR_LEN 6 /* #define TSEC_TIMEOUT 1000000 */ @@ -414,11 +364,7 @@ struct tsec_private { u32 flags; uint rx_idx; /* index of the current RX buffer */ uint tx_idx; /* index of the current TX buffer */ -#ifndef CONFIG_DM_ETH - struct eth_device *dev; -#else struct udevice *dev; -#endif }; struct tsec_info_struct { @@ -431,10 +377,4 @@ struct tsec_info_struct { u32 flags; }; -#ifndef CONFIG_DM_ETH -int tsec_standard_init(struct bd_info *bis); -int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsec_info, - int num); -#endif - #endif /* __TSEC_H */ -- cgit v1.3.1 From ecca44805d9a00e8e9ac6c14d9e7293565900981 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:11 -0500 Subject: net: ethoc: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/ethoc.c | 85 ------------------------------------ include/dm/platform_data/net_ethoc.h | 4 -- 2 files changed, 89 deletions(-) (limited to 'include') diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index a219affb58a..29067e9e949 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -643,8 +643,6 @@ static inline int ethoc_phy_init(struct ethoc *priv, void *dev) #endif -#ifdef CONFIG_DM_ETH - static int ethoc_write_hwaddr(struct udevice *dev) { struct ethoc_eth_pdata *pdata = dev_get_plat(dev); @@ -753,86 +751,3 @@ U_BOOT_DRIVER(ethoc) = { .priv_auto = sizeof(struct ethoc), .plat_auto = sizeof(struct ethoc_eth_pdata), }; - -#else - -static int ethoc_init(struct eth_device *dev, struct bd_info *bd) -{ - struct ethoc *priv = (struct ethoc *)dev->priv; - - return ethoc_init_common(priv); -} - -static int ethoc_write_hwaddr(struct eth_device *dev) -{ - struct ethoc *priv = (struct ethoc *)dev->priv; - u8 *mac = dev->enetaddr; - - return ethoc_write_hwaddr_common(priv, mac); -} - -static int ethoc_send(struct eth_device *dev, void *packet, int length) -{ - return ethoc_send_common(dev->priv, packet, length); -} - -static void ethoc_halt(struct eth_device *dev) -{ - ethoc_disable_rx_and_tx(dev->priv); -} - -static int ethoc_recv(struct eth_device *dev) -{ - struct ethoc *priv = (struct ethoc *)dev->priv; - int count; - - if (!ethoc_is_new_packet_received(priv)) - return 0; - - for (count = 0; count < PKTBUFSRX; ++count) { - uchar *packetp; - int size = ethoc_rx_common(priv, &packetp); - - if (size < 0) - break; - if (size > 0) - net_process_received_packet(packetp, size); - ethoc_free_pkt_common(priv); - } - return 0; -} - -int ethoc_initialize(u8 dev_num, int base_addr) -{ - struct ethoc *priv; - struct eth_device *dev; - - priv = malloc(sizeof(*priv)); - if (!priv) - return 0; - dev = malloc(sizeof(*dev)); - if (!dev) { - free(priv); - return 0; - } - - memset(dev, 0, sizeof(*dev)); - dev->priv = priv; - dev->iobase = base_addr; - dev->init = ethoc_init; - dev->halt = ethoc_halt; - dev->send = ethoc_send; - dev->recv = ethoc_recv; - dev->write_hwaddr = ethoc_write_hwaddr; - sprintf(dev->name, "%s-%hu", "ETHOC", dev_num); - priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE); - - eth_register(dev); - - ethoc_mdio_init(dev->name, priv); - ethoc_phy_init(priv, dev); - - return 1; -} - -#endif diff --git a/include/dm/platform_data/net_ethoc.h b/include/dm/platform_data/net_ethoc.h index 855e9999a0a..44547d14f53 100644 --- a/include/dm/platform_data/net_ethoc.h +++ b/include/dm/platform_data/net_ethoc.h @@ -8,13 +8,9 @@ #include -#ifdef CONFIG_DM_ETH - struct ethoc_eth_pdata { struct eth_pdata eth_pdata; phys_addr_t packet_base; }; -#endif - #endif /* _ETHOC_H */ -- cgit v1.3.1 From 36af92ba85ad45dfb07f1d17e8b7d6945c1ac0b4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:20 -0500 Subject: net: phy: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/phy/aquantia.c | 2 -- drivers/net/phy/atheros.c | 2 -- drivers/net/phy/dp83867.c | 14 -------------- drivers/net/phy/dp83869.c | 14 -------------- drivers/net/phy/marvell.c | 7 ------- drivers/net/phy/micrel_ksz90x1.c | 18 ------------------ drivers/net/phy/phy.c | 13 ------------- include/phy.h | 41 ---------------------------------------- 8 files changed, 111 deletions(-) (limited to 'include') diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 79fbc115368..8eb6024829d 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -338,7 +338,6 @@ static int aquantia_set_proto(struct phy_device *phydev, static int aquantia_dts_config(struct phy_device *phydev) { -#ifdef CONFIG_DM_ETH ofnode node = phydev->node; u32 prop; u16 reg; @@ -374,7 +373,6 @@ static int aquantia_dts_config(struct phy_device *phydev) (u16)(prop << 1)); } -#endif return 0; } diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index fa1fe08518f..c6f9f916459 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -191,7 +191,6 @@ static int ar803x_regs_config(struct phy_device *phydev) static int ar803x_of_init(struct phy_device *phydev) { -#if defined(CONFIG_DM_ETH) struct ar803x_priv *priv; ofnode node, vddio_reg_node; u32 strength, freq, min_uV, max_uV; @@ -306,7 +305,6 @@ static int ar803x_of_init(struct phy_device *phydev) debug("%s: flags=%x clk_25m_reg=%04x clk_25m_mask=%04x\n", __func__, priv->flags, priv->clk_25m_reg, priv->clk_25m_mask); -#endif return 0; } diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 3d862636b6b..a45152bddc9 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -144,7 +144,6 @@ static int dp83867_config_port_mirroring(struct phy_device *phydev) return 0; } -#if defined(CONFIG_DM_ETH) /** * dp83867_data_init - Convenience function for setting PHY specific data * @@ -249,19 +248,6 @@ static int dp83867_of_init(struct phy_device *phydev) return 0; } -#else -static int dp83867_of_init(struct phy_device *phydev) -{ - struct dp83867_private *dp83867 = phydev->priv; - - dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_25_NS; - dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_75_NS; - dp83867->fifo_depth = DEFAULT_FIFO_DEPTH; - dp83867->io_impedance = -EINVAL; - - return 0; -} -#endif static int dp83867_config(struct phy_device *phydev) { diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index c9461185cfe..23dbf42b68c 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -157,7 +157,6 @@ static int dp83869_config_port_mirroring(struct phy_device *phydev) return 0; } -#ifdef CONFIG_DM_ETH static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250, 3500, 3750, 4000}; @@ -269,19 +268,6 @@ static int dp83869_of_init(struct phy_device *phydev) return 0; } -#else -static int dp83869_of_init(struct phy_device *phydev) -{ - struct dp83869_private *dp83869 = phydev->priv; - - dp83869->rx_int_delay = DP83869_RGMIIDCTL_2_25_NS; - dp83869->tx_int_delay = DP83869_RGMIIDCTL_2_75_NS; - dp83869->fifo_depth = DEFAULT_FIFO_DEPTH; - dp83869->io_impedance = -EINVAL; - - return 0; -} -#endif /* CONFIG_OF_MDIO */ static int dp83869_configure_rgmii(struct phy_device *phydev, struct dp83869_private *dp83869) diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 212a861596f..1a25775eee6 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -104,7 +104,6 @@ #define MIIM_88E151x_MODE_SGMII 1 #define MIIM_88E151x_RESET_OFFS 15 -#if IS_ENABLED(CONFIG_DM_ETH) static int marvell_read_page(struct phy_device *phydev) { return phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); @@ -179,12 +178,6 @@ static int marvell_of_reg_init(struct phy_device *phydev) err: return marvell_write_page(phydev, saved_page); } -#else -static int marvell_of_reg_init(struct phy_device *phydev) -{ - return 0; -} -#endif /* CONFIG_DM_ETH */ static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr, int devaddr, int regnum) diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index e5f578201f3..79ebdb5e82a 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -68,7 +68,6 @@ static int ksz90xx_startup(struct phy_device *phydev) } /* Common OF config bits for KSZ9021 and KSZ9031 */ -#ifdef CONFIG_DM_ETH struct ksz90x1_reg_field { const char *name; const u8 size; /* Size of the bitfield, in bits */ @@ -211,23 +210,6 @@ static int ksz9031_center_flp_timing(struct phy_device *phydev) return ret; } -#else /* !CONFIG_DM_ETH */ -static int ksz9021_of_config(struct phy_device *phydev) -{ - return 0; -} - -static int ksz9031_of_config(struct phy_device *phydev) -{ - return 0; -} - -static int ksz9031_center_flp_timing(struct phy_device *phydev) -{ - return 0; -} -#endif - /* * KSZ9021 */ diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 92143cf2369..80230b907c1 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -689,9 +689,7 @@ struct phy_device *phy_device_create(struct mii_dev *bus, int addr, dev->link = 0; dev->interface = PHY_INTERFACE_MODE_NA; -#ifdef CONFIG_DM_ETH dev->node = ofnode_null(); -#endif dev->autoneg = AUTONEG_ENABLE; @@ -922,13 +920,8 @@ struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask) return get_phy_device_by_mask(bus, phy_mask); } -#ifdef CONFIG_DM_ETH void phy_connect_dev(struct phy_device *phydev, struct udevice *dev, phy_interface_t interface) -#else -void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev, - phy_interface_t interface) -#endif { /* Soft Reset the PHY */ phy_reset(phydev); @@ -1011,15 +1004,9 @@ static struct phy_device *phy_connect_fixed(struct mii_dev *bus, } #endif -#ifdef CONFIG_DM_ETH struct phy_device *phy_connect(struct mii_dev *bus, int addr, struct udevice *dev, phy_interface_t interface) -#else -struct phy_device *phy_connect(struct mii_dev *bus, int addr, - struct eth_device *dev, - phy_interface_t interface) -#endif { struct phy_device *phydev = NULL; uint mask = (addr >= 0) ? (1 << addr) : 0xffffffff; diff --git a/include/phy.h b/include/phy.h index ff69536fca7..87aa86c2e78 100644 --- a/include/phy.h +++ b/include/phy.h @@ -138,12 +138,8 @@ struct phy_device { struct phy_driver *drv; void *priv; -#ifdef CONFIG_DM_ETH struct udevice *dev; ofnode node; -#else - struct eth_device *dev; -#endif /* forced speed & duplex (no autoneg) * partner speed & duplex & pause (autoneg) @@ -233,8 +229,6 @@ static inline struct phy_device *fixed_phy_create(ofnode node) #endif -#ifdef CONFIG_DM_ETH - /** * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices * @phydev: PHY device @@ -293,41 +287,6 @@ static inline ofnode phy_get_ofnode(struct phy_device *phydev) else return dev_ofnode(phydev->dev); } -#else - -/** - * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices - * @phydev: PHY device - * @dev: Ethernet device - * @interface: type of MAC-PHY interface - */ -void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev, - phy_interface_t interface); - -/** - * phy_connect() - Creates a PHY device for the Ethernet interface - * Creates a PHY device for the PHY at the given address, if one doesn't exist - * already, and associates it with the Ethernet device. - * The function may be called with addr <= 0, in this case addr value is ignored - * and the bus is scanned to detect a PHY. Scanning should only be used if only - * one PHY is expected to be present on the MDIO bus, otherwise it is undefined - * which PHY is returned. - * - * @bus: MII/MDIO bus that hosts the PHY - * @addr: PHY address on MDIO bus - * @dev: Ethernet device to associate to the PHY - * @interface: type of MAC-PHY interface - * @return: pointer to phy_device if a PHY is found, or NULL otherwise - */ -struct phy_device *phy_connect(struct mii_dev *bus, int addr, - struct eth_device *dev, - phy_interface_t interface); - -static inline ofnode phy_get_ofnode(struct phy_device *phydev) -{ - return ofnode_null(); -} -#endif int phy_read(struct phy_device *phydev, int devad, int regnum); int phy_write(struct phy_device *phydev, int devad, int regnum, u16 val); -- cgit v1.3.1 From b8daa6e9ee079fea7f9772e40b56147274c5726b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:33 -0500 Subject: usb: eth: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code fro usb_ether itself. Signed-off-by: Tom Rini --- drivers/usb/eth/usb_ether.c | 199 ------------------------------------------ drivers/usb/host/usb-uclass.c | 43 --------- include/usb.h | 15 ---- include/usb_ether.h | 44 +--------- 4 files changed, 1 insertion(+), 300 deletions(-) (limited to 'include') diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c index e368ecda0d7..2e9af54fd63 100644 --- a/drivers/usb/eth/usb_ether.c +++ b/drivers/usb/eth/usb_ether.c @@ -15,8 +15,6 @@ #include "usb_ether.h" -#ifdef CONFIG_DM_ETH - #define USB_BULK_RECV_TIMEOUT 500 int usb_ether_register(struct udevice *dev, struct ueth_data *ueth, int rxsize) @@ -137,200 +135,3 @@ int usb_ether_get_rx_bytes(struct ueth_data *ueth, uint8_t **ptrp) return ueth->rxlen - ueth->rxptr; } - -#else - -typedef void (*usb_eth_before_probe)(void); -typedef int (*usb_eth_probe)(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss); -typedef int (*usb_eth_get_info)(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *dev_desc); - -struct usb_eth_prob_dev { - usb_eth_before_probe before_probe; /* optional */ - usb_eth_probe probe; - usb_eth_get_info get_info; -}; - -/* driver functions go here, each bracketed by #ifdef CONFIG_USB_ETHER_xxx */ -static const struct usb_eth_prob_dev prob_dev[] = { -#ifdef CONFIG_USB_ETHER_ASIX - { - .before_probe = asix_eth_before_probe, - .probe = asix_eth_probe, - .get_info = asix_eth_get_info, - }, -#endif -#ifdef CONFIG_USB_ETHER_ASIX88179 - { - .before_probe = ax88179_eth_before_probe, - .probe = ax88179_eth_probe, - .get_info = ax88179_eth_get_info, - }, -#endif -#ifdef CONFIG_USB_ETHER_MCS7830 - { - .before_probe = mcs7830_eth_before_probe, - .probe = mcs7830_eth_probe, - .get_info = mcs7830_eth_get_info, - }, -#endif -#ifdef CONFIG_USB_ETHER_SMSC95XX - { - .before_probe = smsc95xx_eth_before_probe, - .probe = smsc95xx_eth_probe, - .get_info = smsc95xx_eth_get_info, - }, -#endif -#ifdef CONFIG_USB_ETHER_RTL8152 - { - .before_probe = r8152_eth_before_probe, - .probe = r8152_eth_probe, - .get_info = r8152_eth_get_info, - }, -#endif - { }, /* END */ -}; - -static int usb_max_eth_dev; /* number of highest available usb eth device */ -static struct ueth_data usb_eth[USB_MAX_ETH_DEV]; - -/******************************************************************************* - * tell if current ethernet device is a usb dongle - */ -int is_eth_dev_on_usb_host(void) -{ - int i; - struct eth_device *dev = eth_get_dev(); - - if (dev) { - for (i = 0; i < usb_max_eth_dev; i++) - if (&usb_eth[i].eth_dev == dev) - return 1; - } - return 0; -} - -/* - * Given a USB device, ask each driver if it can support it, and attach it - * to the first driver that says 'yes' - */ -static void probe_valid_drivers(struct usb_device *dev) -{ - struct eth_device *eth; - int j; - - for (j = 0; prob_dev[j].probe && prob_dev[j].get_info; j++) { - if (!prob_dev[j].probe(dev, 0, &usb_eth[usb_max_eth_dev])) - continue; - /* - * ok, it is a supported eth device. Get info and fill it in - */ - eth = &usb_eth[usb_max_eth_dev].eth_dev; - if (prob_dev[j].get_info(dev, - &usb_eth[usb_max_eth_dev], - eth)) { - /* found proper driver */ - /* register with networking stack */ - usb_max_eth_dev++; - - /* - * usb_max_eth_dev must be incremented prior to this - * call since eth_current_changed (internally called) - * relies on it - */ - eth_register(eth); - if (eth_write_hwaddr(eth, "usbeth", - usb_max_eth_dev - 1)) - puts("Warning: failed to set MAC address\n"); - break; - } - } - } - -/******************************************************************************* - * scan the usb and reports device info - * to the user if mode = 1 - * returns current device or -1 if no - */ -int usb_host_eth_scan(int mode) -{ - int i, old_async; - - if (mode == 1) - printf(" scanning usb for ethernet devices... "); - - old_async = usb_disable_asynch(1); /* asynch transfer not allowed */ - - /* unregister a previously detected device */ - for (i = 0; i < usb_max_eth_dev; i++) - eth_unregister(&usb_eth[i].eth_dev); - - memset(usb_eth, 0, sizeof(usb_eth)); - - for (i = 0; prob_dev[i].probe; i++) { - if (prob_dev[i].before_probe) - prob_dev[i].before_probe(); - } - - usb_max_eth_dev = 0; -#if CONFIG_IS_ENABLED(DM_USB) - /* - * TODO: We should add U_BOOT_USB_DEVICE() declarations to each USB - * Ethernet driver and then most of this file can be removed. - */ - struct udevice *bus; - struct uclass *uc; - int ret; - - ret = uclass_get(UCLASS_USB, &uc); - if (ret) - return ret; - uclass_foreach_dev(bus, uc) { - for (i = 0; i < USB_MAX_DEVICE; i++) { - struct usb_device *dev; - - dev = usb_get_dev_index(bus, i); /* get device */ - debug("i=%d, %s\n", i, dev ? dev->dev->name : "(done)"); - if (!dev) - break; /* no more devices available */ - - /* - * find valid usb_ether driver for this device, - * if any - */ - probe_valid_drivers(dev); - - /* check limit */ - if (usb_max_eth_dev == USB_MAX_ETH_DEV) - break; - } /* for */ - } -#else - for (i = 0; i < USB_MAX_DEVICE; i++) { - struct usb_device *dev; - - dev = usb_get_dev_index(i); /* get device */ - debug("i=%d\n", i); - if (!dev) - break; /* no more devices available */ - - /* find valid usb_ether driver for this device, if any */ - probe_valid_drivers(dev); - - /* check limit */ - if (usb_max_eth_dev == USB_MAX_ETH_DEV) - break; - } /* for */ -#endif - if (usb_max_eth_dev == USB_MAX_ETH_DEV) { - printf("max USB Ethernet Device reached: %d stopping\n", - usb_max_eth_dev); - } - usb_disable_asynch(old_async); /* restore asynch value */ - printf("%d Ethernet Device(s) found\n", usb_max_eth_dev); - if (usb_max_eth_dev > 0) - return 0; - return -1; -} -#endif diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index 060f3441df0..956e2a4e8e4 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -346,49 +346,6 @@ int usb_init(void) return usb_started ? 0 : -1; } -/* - * TODO(sjg@chromium.org): Remove this legacy function. At present it is needed - * to support boards which use driver model for USB but not Ethernet, and want - * to use USB Ethernet. - * - * The #if clause is here to ensure that remains the only case. - */ -#if !defined(CONFIG_DM_ETH) && defined(CONFIG_USB_HOST_ETHER) -static struct usb_device *find_child_devnum(struct udevice *parent, int devnum) -{ - struct usb_device *udev; - struct udevice *dev; - - if (!device_active(parent)) - return NULL; - udev = dev_get_parent_priv(parent); - if (udev->devnum == devnum) - return udev; - - for (device_find_first_child(parent, &dev); - dev; - device_find_next_child(&dev)) { - udev = find_child_devnum(dev, devnum); - if (udev) - return udev; - } - - return NULL; -} - -struct usb_device *usb_get_dev_index(struct udevice *bus, int index) -{ - struct udevice *dev; - int devnum = index + 1; /* Addresses are allocated from 1 on USB */ - - device_find_first_child(bus, &dev); - if (!dev) - return NULL; - - return find_child_devnum(dev, devnum); -} -#endif - int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp) { struct usb_plat *plat; diff --git a/include/usb.h b/include/usb.h index 7e3796bd5ba..80cb8467203 100644 --- a/include/usb.h +++ b/include/usb.h @@ -808,21 +808,6 @@ struct dm_usb_ops { #define usb_get_ops(dev) ((struct dm_usb_ops *)(dev)->driver->ops) #define usb_get_emul_ops(dev) ((struct dm_usb_ops *)(dev)->driver->ops) -/** - * usb_get_dev_index() - look up a device index number - * - * Look up devices using their index number (starting at 0). This works since - * in U-Boot device addresses are allocated starting at 1 with no gaps. - * - * TODO(sjg@chromium.org): Remove this function when usb_ether.c is modified - * to work better with driver model. - * - * @bus: USB bus to check - * @index: Index number of device to find (0=first). This is just the - * device address less 1. - */ -struct usb_device *usb_get_dev_index(struct udevice *bus, int index); - /** * usb_setup_device() - set up a device ready for use * diff --git a/include/usb_ether.h b/include/usb_ether.h index 8c7bd069064..18d7184711b 100644 --- a/include/usb_ether.h +++ b/include/usb_ether.h @@ -8,19 +8,13 @@ #include -/* TODO(sjg@chromium.org): Remove @pusb_dev when all boards use CONFIG_DM_ETH */ +/* TODO(sjg@chromium.org): Remove @pusb_dev now that all boards use CONFIG_DM_ETH */ struct ueth_data { /* eth info */ -#ifdef CONFIG_DM_ETH uint8_t *rxbuf; int rxsize; int rxlen; /* Total bytes available in rxbuf */ int rxptr; /* Current position in rxbuf */ -#else - struct eth_device eth_dev; /* used with eth_register */ - /* driver private */ - void *dev_priv; -#endif int phy_id; /* mii phy id */ /* usb info */ @@ -34,7 +28,6 @@ struct ueth_data { unsigned char irqinterval; /* Intervall for IRQ Pipe */ }; -#ifdef CONFIG_DM_ETH /** * usb_ether_register() - register a new USB ethernet device * @@ -92,40 +85,5 @@ int usb_ether_get_rx_bytes(struct ueth_data *ueth, uint8_t **ptrp); * @num_bytes: Number of bytes to skip, or -1 to skip all bytes */ void usb_ether_advance_rxbuf(struct ueth_data *ueth, int num_bytes); -#else -/* - * Function definitions for each USB ethernet driver go here - * (declaration is unconditional, compilation is conditional) - */ -void asix_eth_before_probe(void); -int asix_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss); -int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth); - -void ax88179_eth_before_probe(void); -int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss); -int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth); - -void mcs7830_eth_before_probe(void); -int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss); -int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth); - -void smsc95xx_eth_before_probe(void); -int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss); -int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth); - -void r8152_eth_before_probe(void); -int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss); -int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth); -#endif #endif /* __USB_ETHER_H__ */ -- cgit v1.3.1 From e524f3a449f58e2ef967fb9b64b01db3d099a27a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:36 -0500 Subject: net: Remove eth_legacy.c As there are no more non-DM_ETH cases for networking, remove this legacy file and update the Makefile to match current usage. Signed-off-by: Tom Rini --- boot/bootm.c | 3 - cmd/net.c | 2 - cmd/usb.c | 10 -- drivers/net/Kconfig | 4 + include/net.h | 71 --------- net/Makefile | 10 +- net/eth_internal.h | 4 - net/eth_legacy.c | 426 ---------------------------------------------------- 8 files changed, 7 insertions(+), 523 deletions(-) delete mode 100644 net/eth_legacy.c (limited to 'include') diff --git a/boot/bootm.c b/boot/bootm.c index a4c0870c0fe..15fce8ad95e 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -475,9 +475,6 @@ ulong bootm_disable_interrupts(void) #ifdef CONFIG_NETCONSOLE /* Stop the ethernet stack if NetConsole could have left it up */ eth_halt(); -# ifndef CONFIG_DM_ETH - eth_unregister(eth_get_dev()); -# endif #endif #if defined(CONFIG_CMD_USB) diff --git a/cmd/net.c b/cmd/net.c index 0e9f200ca97..dd50930a362 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -597,7 +597,6 @@ U_BOOT_CMD( #endif /* CONFIG_CMD_LINK_LOCAL */ -#ifdef CONFIG_DM_ETH static int do_net_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { const struct udevice *current = eth_get_dev(); @@ -640,7 +639,6 @@ U_BOOT_CMD( "NET sub-system", "list - list available devices\n" ); -#endif // CONFIG_DM_ETH #if defined(CONFIG_CMD_NCSI) static int do_ncsi(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) diff --git a/cmd/usb.c b/cmd/usb.c index 2ba056982c3..73addb04c49 100644 --- a/cmd/usb.c +++ b/cmd/usb.c @@ -591,16 +591,6 @@ static void do_usb_start(void) drv_usb_kbd_init(); # endif #endif /* !CONFIG_DM_USB */ -#ifdef CONFIG_USB_HOST_ETHER -# ifdef CONFIG_DM_ETH -# ifndef CONFIG_DM_USB -# error "You must use CONFIG_DM_USB if you want to use CONFIG_USB_HOST_ETHER with CONFIG_DM_ETH" -# endif -# else - /* try to recognize ethernet devices immediately */ - usb_ether_curr_dev = usb_host_eth_scan(1); -# endif -#endif } #ifdef CONFIG_DM_USB diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index db61c27e013..4e5da5ab72a 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -15,6 +15,10 @@ config DM_ETH This is currently implemented in net/eth-uclass.c Look in include/net.h for details. +config SPL_DM_ETH + depends on SPL_NET + def_bool y + config DM_MDIO bool "Enable Driver Model for MDIO devices" depends on PHYLIB diff --git a/include/net.h b/include/net.h index 1a99009959d..ee08f3307ec 100644 --- a/include/net.h +++ b/include/net.h @@ -101,7 +101,6 @@ enum eth_state_t { ETH_STATE_ACTIVE }; -#ifdef CONFIG_DM_ETH /** * struct eth_pdata - Platform data for Ethernet MAC controllers * @@ -180,76 +179,6 @@ unsigned char *eth_get_ethaddr(void); /* get the current device MAC */ int eth_is_active(struct udevice *dev); /* Test device for active state */ int eth_init_state_only(void); /* Set active state */ void eth_halt_state_only(void); /* Set passive state */ -#endif - -#ifndef CONFIG_DM_ETH -struct eth_device { -#define ETH_NAME_LEN 20 - char name[ETH_NAME_LEN]; - unsigned char enetaddr[ARP_HLEN]; - phys_addr_t iobase; - int state; - - int (*init)(struct eth_device *eth, struct bd_info *bd); - int (*send)(struct eth_device *, void *packet, int length); - int (*recv)(struct eth_device *); - void (*halt)(struct eth_device *); - int (*mcast)(struct eth_device *, const u8 *enetaddr, int join); - int (*write_hwaddr)(struct eth_device *eth); - struct eth_device *next; - int index; - void *priv; -}; - -int eth_register(struct eth_device *dev);/* Register network device */ -int eth_unregister(struct eth_device *dev);/* Remove network device */ - -extern struct eth_device *eth_current; - -static __always_inline struct eth_device *eth_get_dev(void) -{ - return eth_current; -} -struct eth_device *eth_get_dev_by_name(const char *devname); -struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */ - -/* get the current device MAC */ -static inline unsigned char *eth_get_ethaddr(void) -{ - if (eth_current) - return eth_current->enetaddr; - return NULL; -} - -/* Used only when NetConsole is enabled */ -int eth_is_active(struct eth_device *dev); /* Test device for active state */ -/* Set active state */ -static __always_inline int eth_init_state_only(void) -{ - eth_get_dev()->state = ETH_STATE_ACTIVE; - - return 0; -} -/* Set passive state */ -static __always_inline void eth_halt_state_only(void) -{ - eth_get_dev()->state = ETH_STATE_PASSIVE; -} - -/* - * Set the hardware address for an ethernet interface based on 'eth%daddr' - * environment variable (or just 'ethaddr' if eth_number is 0). - * Args: - * base_name - base name for device (normally "eth") - * eth_number - value of %d (0 for first device of this type) - * Returns: - * 0 is success, non-zero is error status from driver. - */ -int eth_write_hwaddr(struct eth_device *dev, const char *base_name, - int eth_number); - -int usb_eth_initialize(struct bd_info *bi); -#endif int eth_initialize(void); /* Initialize network subsystem */ void eth_try_another(int first_restart); /* Change the device */ diff --git a/net/Makefile b/net/Makefile index 13eef04029d..bea000b2067 100644 --- a/net/Makefile +++ b/net/Makefile @@ -10,18 +10,14 @@ obj-$(CONFIG_CMD_BOOTP) += bootp.o obj-$(CONFIG_CMD_CDP) += cdp.o obj-$(CONFIG_CMD_DNS) += dns.o obj-$(CONFIG_DM_DSA) += dsa-uclass.o -ifdef CONFIG_DM_ETH -obj-$(CONFIG_NET) += eth-uclass.o +obj-$(CONFIG_$(SPL_)DM_ETH) += eth-uclass.o obj-$(CONFIG_$(SPL_TPL_)BOOTDEV_ETH) += eth_bootdev.o -else -obj-$(CONFIG_NET) += eth_legacy.o -endif obj-$(CONFIG_DM_MDIO) += mdio-uclass.o obj-$(CONFIG_DM_MDIO_MUX) += mdio-mux-uclass.o -obj-$(CONFIG_NET) += eth_common.o +obj-$(CONFIG_$(SPL_)DM_ETH) += eth_common.o obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o obj-$(CONFIG_IPV6) += ndisc.o -obj-$(CONFIG_NET) += net.o +obj-$(CONFIG_$(SPL_)DM_ETH) += net.o obj-$(CONFIG_IPV6) += net6.o obj-$(CONFIG_CMD_NFS) += nfs.o obj-$(CONFIG_CMD_PING) += ping.o diff --git a/net/eth_internal.h b/net/eth_internal.h index 042e58a99ae..0b829a8d388 100644 --- a/net/eth_internal.h +++ b/net/eth_internal.h @@ -29,11 +29,7 @@ int eth_env_set_enetaddr_by_index(const char *base_name, int index, int eth_mac_skip(int index); void eth_current_changed(void); -#ifdef CONFIG_DM_ETH void eth_set_dev(struct udevice *dev); -#else -void eth_set_dev(struct eth_device *dev); -#endif void eth_set_current_to_next(void); #endif diff --git a/net/eth_legacy.c b/net/eth_legacy.c deleted file mode 100644 index 0b282d918be..00000000000 --- a/net/eth_legacy.c +++ /dev/null @@ -1,426 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2001-2015 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Joe Hershberger, National Instruments - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "eth_internal.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * CPU and board-specific Ethernet initializations. Aliased function - * signals caller to move on - */ -static int __def_eth_init(struct bd_info *bis) -{ - return -1; -} -int cpu_eth_init(struct bd_info *bis) __attribute__((weak, alias("__def_eth_init"))); -int board_eth_init(struct bd_info *bis) __attribute__((weak, alias("__def_eth_init"))); - -#ifdef CONFIG_API -static struct { - uchar data[PKTSIZE]; - int length; -} eth_rcv_bufs[PKTBUFSRX]; - -static unsigned int eth_rcv_current, eth_rcv_last; -#endif - -static struct eth_device *eth_devices; -struct eth_device *eth_current; - -void eth_set_current_to_next(void) -{ - eth_current = eth_current->next; -} - -void eth_set_dev(struct eth_device *dev) -{ - eth_current = dev; -} - -struct eth_device *eth_get_dev_by_name(const char *devname) -{ - struct eth_device *dev, *target_dev; - - BUG_ON(devname == NULL); - - if (!eth_devices) - return NULL; - - dev = eth_devices; - target_dev = NULL; - do { - if (strcmp(devname, dev->name) == 0) { - target_dev = dev; - break; - } - dev = dev->next; - } while (dev != eth_devices); - - return target_dev; -} - -struct eth_device *eth_get_dev_by_index(int index) -{ - struct eth_device *dev, *target_dev; - - if (!eth_devices) - return NULL; - - dev = eth_devices; - target_dev = NULL; - do { - if (dev->index == index) { - target_dev = dev; - break; - } - dev = dev->next; - } while (dev != eth_devices); - - return target_dev; -} - -int eth_get_dev_index(void) -{ - if (!eth_current) - return -1; - - return eth_current->index; -} - -static int on_ethaddr(const char *name, const char *value, enum env_op op, - int flags) -{ - int index; - struct eth_device *dev; - - if (!eth_devices) - return 0; - - /* look for an index after "eth" */ - index = dectoul(name + 3, NULL); - - dev = eth_devices; - do { - if (dev->index == index) { - switch (op) { - case env_op_create: - case env_op_overwrite: - string_to_enetaddr(value, dev->enetaddr); - eth_write_hwaddr(dev, "eth", dev->index); - break; - case env_op_delete: - memset(dev->enetaddr, 0, ARP_HLEN); - } - } - dev = dev->next; - } while (dev != eth_devices); - - return 0; -} -U_BOOT_ENV_CALLBACK(ethaddr, on_ethaddr); - -int eth_write_hwaddr(struct eth_device *dev, const char *base_name, - int eth_number) -{ - unsigned char env_enetaddr[ARP_HLEN]; - int ret = 0; - - eth_env_get_enetaddr_by_index(base_name, eth_number, env_enetaddr); - - if (!is_zero_ethaddr(env_enetaddr)) { - if (!is_zero_ethaddr(dev->enetaddr) && - memcmp(dev->enetaddr, env_enetaddr, ARP_HLEN)) { - printf("\nWarning: %s MAC addresses don't match:\n", - dev->name); - printf("Address in SROM is %pM\n", - dev->enetaddr); - printf("Address in environment is %pM\n", - env_enetaddr); - } - - memcpy(dev->enetaddr, env_enetaddr, ARP_HLEN); - } else if (is_valid_ethaddr(dev->enetaddr)) { - eth_env_set_enetaddr_by_index(base_name, eth_number, - dev->enetaddr); - } else if (is_zero_ethaddr(dev->enetaddr)) { -#ifdef CONFIG_NET_RANDOM_ETHADDR - net_random_ethaddr(dev->enetaddr); - printf("\nWarning: %s (eth%d) using random MAC address - %pM\n", - dev->name, eth_number, dev->enetaddr); - eth_env_set_enetaddr_by_index("eth", eth_number, - dev->enetaddr); -#else - printf("\nError: %s address not set.\n", - dev->name); - return -EINVAL; -#endif - } - - if (dev->write_hwaddr && !eth_mac_skip(eth_number)) { - if (!is_valid_ethaddr(dev->enetaddr)) { - printf("\nError: %s address %pM illegal value\n", - dev->name, dev->enetaddr); - return -EINVAL; - } - - ret = dev->write_hwaddr(dev); - if (ret) - printf("\nWarning: %s failed to set MAC address\n", - dev->name); - } - - return ret; -} - -int eth_register(struct eth_device *dev) -{ - struct eth_device *d; - static int index; - - assert(strlen(dev->name) < sizeof(dev->name)); - - if (!eth_devices) { - eth_devices = dev; - eth_current = dev; - eth_current_changed(); - } else { - for (d = eth_devices; d->next != eth_devices; d = d->next) - ; - d->next = dev; - } - - dev->state = ETH_STATE_INIT; - dev->next = eth_devices; - dev->index = index++; - - return 0; -} - -int eth_unregister(struct eth_device *dev) -{ - struct eth_device *cur; - - /* No device */ - if (!eth_devices) - return -ENODEV; - - for (cur = eth_devices; cur->next != eth_devices && cur->next != dev; - cur = cur->next) - ; - - /* Device not found */ - if (cur->next != dev) - return -ENODEV; - - cur->next = dev->next; - - if (eth_devices == dev) - eth_devices = dev->next == eth_devices ? NULL : dev->next; - - if (eth_current == dev) { - eth_current = eth_devices; - eth_current_changed(); - } - - return 0; -} - -int eth_initialize(void) -{ - int num_devices = 0; - - eth_devices = NULL; - eth_current = NULL; - eth_common_init(); - /* - * If board-specific initialization exists, call it. - * If not, call a CPU-specific one - */ - if (board_eth_init != __def_eth_init) { - if (board_eth_init(gd->bd) < 0) - printf("Board Net Initialization Failed\n"); - } else if (cpu_eth_init != __def_eth_init) { - if (cpu_eth_init(gd->bd) < 0) - printf("CPU Net Initialization Failed\n"); - } else { - printf("Net Initialization Skipped\n"); - } - - if (!eth_devices) { - log_err("No ethernet found.\n"); - bootstage_error(BOOTSTAGE_ID_NET_ETH_START); - } else { - struct eth_device *dev = eth_devices; - char *ethprime = env_get("ethprime"); - - bootstage_mark(BOOTSTAGE_ID_NET_ETH_INIT); - do { - if (dev->index) - puts(", "); - - printf("%s", dev->name); - - if (ethprime && strcmp(dev->name, ethprime) == 0) { - eth_current = dev; - puts(" [PRIME]"); - } - - if (strchr(dev->name, ' ')) - puts("\nWarning: eth device name has a space!" - "\n"); - - eth_write_hwaddr(dev, "eth", dev->index); - - dev = dev->next; - num_devices++; - } while (dev != eth_devices); - - eth_current_changed(); - putc('\n'); - } - - return num_devices; -} - -/* Multicast. - * mcast_addr: multicast ipaddr from which multicast Mac is made - * join: 1=join, 0=leave. - */ -int eth_mcast_join(struct in_addr mcast_ip, int join) -{ - u8 mcast_mac[ARP_HLEN]; - if (!eth_current || !eth_current->mcast) - return -1; - mcast_mac[5] = htonl(mcast_ip.s_addr) & 0xff; - mcast_mac[4] = (htonl(mcast_ip.s_addr)>>8) & 0xff; - mcast_mac[3] = (htonl(mcast_ip.s_addr)>>16) & 0x7f; - mcast_mac[2] = 0x5e; - mcast_mac[1] = 0x0; - mcast_mac[0] = 0x1; - return eth_current->mcast(eth_current, mcast_mac, join); -} - -int eth_init(void) -{ - struct eth_device *old_current; - - if (!eth_current) { - log_err("No ethernet found.\n"); - return -ENODEV; - } - - old_current = eth_current; - do { - debug("Trying %s\n", eth_current->name); - - if (eth_current->init(eth_current, gd->bd) >= 0) { - eth_current->state = ETH_STATE_ACTIVE; - - return 0; - } - debug("FAIL\n"); - - eth_try_another(0); - } while (old_current != eth_current); - - return -ETIMEDOUT; -} - -void eth_halt(void) -{ - if (!eth_current) - return; - - eth_current->halt(eth_current); - - eth_current->state = ETH_STATE_PASSIVE; -} - -int eth_is_active(struct eth_device *dev) -{ - return dev && dev->state == ETH_STATE_ACTIVE; -} - -int eth_send(void *packet, int length) -{ - int ret; - - if (!eth_current) - return -ENODEV; - - ret = eth_current->send(eth_current, packet, length); -#if defined(CONFIG_CMD_PCAP) - if (ret >= 0) - pcap_post(packet, length, true); -#endif - return ret; -} - -int eth_rx(void) -{ - if (!eth_current) - return -ENODEV; - - return eth_current->recv(eth_current); -} - -#ifdef CONFIG_API -static void eth_save_packet(void *packet, int length) -{ - char *p = packet; - int i; - - if ((eth_rcv_last+1) % PKTBUFSRX == eth_rcv_current) - return; - - if (PKTSIZE < length) - return; - - for (i = 0; i < length; i++) - eth_rcv_bufs[eth_rcv_last].data[i] = p[i]; - - eth_rcv_bufs[eth_rcv_last].length = length; - eth_rcv_last = (eth_rcv_last + 1) % PKTBUFSRX; -} - -int eth_receive(void *packet, int length) -{ - char *p = packet; - void *pp = push_packet; - int i; - - if (eth_rcv_current == eth_rcv_last) { - push_packet = eth_save_packet; - eth_rx(); - push_packet = pp; - - if (eth_rcv_current == eth_rcv_last) - return -1; - } - - length = min(eth_rcv_bufs[eth_rcv_current].length, length); - - for (i = 0; i < length; i++) - p[i] = eth_rcv_bufs[eth_rcv_current].data[i]; - - eth_rcv_current = (eth_rcv_current + 1) % PKTBUFSRX; - return length; -} -#endif /* CONFIG_API */ -- cgit v1.3.1 From 28f924f2650ed2229fd712620c36a41dc0610fcb Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 23 Nov 2022 12:55:33 +0100 Subject: tools: mkimage: add new image type "fdt_legacy" If the user select the image type "flat_dt" a FIT image will be build. This breaks the legacy use case of putting a Flat Device Tree into a legacy u-boot image. Add a new image type "fdt_legacy" to build a legacy u-boot image with a "flat_dt" type. Link: https://lore.kernel.org/all/20221028155205.ojw6tcso2fofgnhm@pengutronix.de Signed-off-by: Marc Kleine-Budde Reviewed-by: Sean Anderson --- boot/image.c | 1 + include/image.h | 1 + tools/default_image.c | 11 +++++++++-- 3 files changed, 11 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/boot/image.c b/boot/image.c index b33d1dfc6b3..958dbf85347 100644 --- a/boot/image.c +++ b/boot/image.c @@ -180,6 +180,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_COPRO, "copro", "Coprocessor Image"}, { IH_TYPE_SUNXI_EGON, "sunxi_egon", "Allwinner eGON Boot Image" }, { IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image" }, + { IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat Device Tree ", }, { -1, "", "", }, }; diff --git a/include/image.h b/include/image.h index 6f21dafba8c..b6a809834ad 100644 --- a/include/image.h +++ b/include/image.h @@ -229,6 +229,7 @@ enum image_type_t { IH_TYPE_COPRO, /* Coprocessor Image for remoteproc*/ IH_TYPE_SUNXI_EGON, /* Allwinner eGON Boot Image */ IH_TYPE_SUNXI_TOC0, /* Allwinner TOC0 Boot Image */ + IH_TYPE_FDT_LEGACY, /* Binary Flat Device Tree Blob in a Legacy Image */ IH_TYPE_COUNT, /* Number of image types */ }; diff --git a/tools/default_image.c b/tools/default_image.c index 4a067e65862..0ac3382003d 100644 --- a/tools/default_image.c +++ b/tools/default_image.c @@ -27,7 +27,8 @@ static struct legacy_img_hdr header; static int image_check_image_types(uint8_t type) { if (((type > IH_TYPE_INVALID) && (type < IH_TYPE_FLATDT)) || - (type == IH_TYPE_KERNEL_NOLOAD) || (type == IH_TYPE_FIRMWARE_IVT)) + (type == IH_TYPE_KERNEL_NOLOAD) || (type == IH_TYPE_FIRMWARE_IVT) || + (type == IH_TYPE_FDT_LEGACY)) return EXIT_SUCCESS; else return EXIT_FAILURE; @@ -94,6 +95,7 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd, uint32_t imagesize; uint32_t ep; uint32_t addr; + int type; struct legacy_img_hdr *hdr = (struct legacy_img_hdr *)ptr; checksum = crc32(0, @@ -113,6 +115,11 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd, else imagesize = sbuf->st_size - sizeof(struct legacy_img_hdr); + if (params->type == IH_TYPE_FDT_LEGACY) + type = IH_TYPE_FLATDT; + else + type = params->type; + if (params->os == IH_OS_TEE) { addr = optee_image_get_load_addr(hdr); ep = optee_image_get_entry_point(hdr); @@ -127,7 +134,7 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd, image_set_dcrc(hdr, checksum); image_set_os(hdr, params->os); image_set_arch(hdr, params->arch); - image_set_type(hdr, params->type); + image_set_type(hdr, type); image_set_comp(hdr, params->comp); image_set_name(hdr, params->imagename); -- cgit v1.3.1 From de32a2a32aec6ba82fc60c15bef4750ee6729826 Mon Sep 17 00:00:00 2001 From: Balamanikandan Gunasundar Date: Tue, 25 Oct 2022 16:21:03 +0530 Subject: mfd: syscon: Add atmel-matrix registers definition This file is copied from Linux. AT91 SoCs have a memory range reserved for internal bus configuration. Expose those registers so that drivers can make use of the matrix syscon declared in at91 DTs. Signed-off-by: Balamanikandan Gunasundar --- include/linux/mfd/syscon/atmel-matrix.h | 112 ++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) create mode 100644 include/linux/mfd/syscon/atmel-matrix.h (limited to 'include') diff --git a/include/linux/mfd/syscon/atmel-matrix.h b/include/linux/mfd/syscon/atmel-matrix.h new file mode 100644 index 00000000000..dd228cab67a --- /dev/null +++ b/include/linux/mfd/syscon/atmel-matrix.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Atmel Corporation. + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + */ + +#ifndef _LINUX_MFD_SYSCON_ATMEL_MATRIX_H +#define _LINUX_MFD_SYSCON_ATMEL_MATRIX_H + +#define AT91SAM9260_MATRIX_MCFG 0x00 +#define AT91SAM9260_MATRIX_SCFG 0x40 +#define AT91SAM9260_MATRIX_PRS 0x80 +#define AT91SAM9260_MATRIX_MRCR 0x100 +#define AT91SAM9260_MATRIX_EBICSA 0x11c + +#define AT91SAM9261_MATRIX_MRCR 0x0 +#define AT91SAM9261_MATRIX_SCFG 0x4 +#define AT91SAM9261_MATRIX_TCR 0x24 +#define AT91SAM9261_MATRIX_EBICSA 0x30 +#define AT91SAM9261_MATRIX_USBPUCR 0x34 + +#define AT91SAM9263_MATRIX_MCFG 0x00 +#define AT91SAM9263_MATRIX_SCFG 0x40 +#define AT91SAM9263_MATRIX_PRS 0x80 +#define AT91SAM9263_MATRIX_MRCR 0x100 +#define AT91SAM9263_MATRIX_TCR 0x114 +#define AT91SAM9263_MATRIX_EBI0CSA 0x120 +#define AT91SAM9263_MATRIX_EBI1CSA 0x124 + +#define AT91SAM9RL_MATRIX_MCFG 0x00 +#define AT91SAM9RL_MATRIX_SCFG 0x40 +#define AT91SAM9RL_MATRIX_PRS 0x80 +#define AT91SAM9RL_MATRIX_MRCR 0x100 +#define AT91SAM9RL_MATRIX_TCR 0x114 +#define AT91SAM9RL_MATRIX_EBICSA 0x120 + +#define AT91SAM9G45_MATRIX_MCFG 0x00 +#define AT91SAM9G45_MATRIX_SCFG 0x40 +#define AT91SAM9G45_MATRIX_PRS 0x80 +#define AT91SAM9G45_MATRIX_MRCR 0x100 +#define AT91SAM9G45_MATRIX_TCR 0x110 +#define AT91SAM9G45_MATRIX_DDRMPR 0x118 +#define AT91SAM9G45_MATRIX_EBICSA 0x128 + +#define AT91SAM9N12_MATRIX_MCFG 0x00 +#define AT91SAM9N12_MATRIX_SCFG 0x40 +#define AT91SAM9N12_MATRIX_PRS 0x80 +#define AT91SAM9N12_MATRIX_MRCR 0x100 +#define AT91SAM9N12_MATRIX_EBICSA 0x118 + +#define AT91SAM9X5_MATRIX_MCFG 0x00 +#define AT91SAM9X5_MATRIX_SCFG 0x40 +#define AT91SAM9X5_MATRIX_PRS 0x80 +#define AT91SAM9X5_MATRIX_MRCR 0x100 +#define AT91SAM9X5_MATRIX_EBICSA 0x120 + +#define SAMA5D3_MATRIX_MCFG 0x00 +#define SAMA5D3_MATRIX_SCFG 0x40 +#define SAMA5D3_MATRIX_PRS 0x80 +#define SAMA5D3_MATRIX_MRCR 0x100 + +#define AT91_MATRIX_MCFG(o, x) ((o) + ((x) * 0x4)) +#define AT91_MATRIX_ULBT GENMASK(2, 0) +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_SCFG(o, x) ((o) + ((x) * 0x4)) +#define AT91_MATRIX_SLOT_CYCLE GENMASK(7, 0) +#define AT91_MATRIX_DEFMSTR_TYPE GENMASK(17, 16) +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR GENMASK(20, 18) +#define AT91_MATRIX_ARBT GENMASK(25, 24) +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) + +#define AT91_MATRIX_ITCM_SIZE GENMASK(3, 0) +#define AT91_MATRIX_ITCM_0 (0 << 0) +#define AT91_MATRIX_ITCM_16 (5 << 0) +#define AT91_MATRIX_ITCM_32 (6 << 0) +#define AT91_MATRIX_ITCM_64 (7 << 0) +#define AT91_MATRIX_DTCM_SIZE GENMASK(7, 4) +#define AT91_MATRIX_DTCM_0 (0 << 4) +#define AT91_MATRIX_DTCM_16 (5 << 4) +#define AT91_MATRIX_DTCM_32 (6 << 4) +#define AT91_MATRIX_DTCM_64 (7 << 4) + +#define AT91_MATRIX_PRAS(o, x) ((o) + ((x) * 0x8)) +#define AT91_MATRIX_PRBS(o, x) ((o) + ((x) * 0x8) + 0x4) +#define AT91_MATRIX_MPR(x) GENMASK(((x) * 0x4) + 1, ((x) * 0x4)) + +#define AT91_MATRIX_RCB(x) BIT(x) + +#define AT91_MATRIX_CSA(cs, val) ((val) << (cs)) +#define AT91_MATRIX_DBPUC BIT(8) +#define AT91_MATRIX_DBPDC BIT(9) +#define AT91_MATRIX_VDDIOMSEL BIT(16) +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_EBI_IOSR BIT(17) +#define AT91_MATRIX_DDR_IOSR BIT(18) +#define AT91_MATRIX_NFD0_SELECT BIT(24) +#define AT91_MATRIX_DDR_MP_EN BIT(25) + +#define AT91_MATRIX_USBPUCR_PUON BIT(30) + +#endif /* _LINUX_MFD_SYSCON_ATMEL_MATRIX_H */ -- cgit v1.3.1 From 2dc1b8fe17b283db4e4485f01ba10dff6b37d693 Mon Sep 17 00:00:00 2001 From: Balamanikandan Gunasundar Date: Tue, 25 Oct 2022 16:21:05 +0530 Subject: mfd: syscon: atmel-smc: Add new helpers to ease SMC regs manipulation Add helper functions for atmel Static Memory Controller. The functions are required to configure SMC. This file is inherited from the work done by Boris Brezillon for Linux Signed-off-by: Balamanikandan Gunasundar --- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/mfd/Kconfig | 4 + drivers/mfd/Makefile | 1 + drivers/mfd/atmel-smc.c | 364 +++++++++++++++++++++++++++++++++++ include/linux/mfd/syscon/atmel-smc.h | 119 ++++++++++++ 6 files changed, 491 insertions(+) create mode 100644 drivers/mfd/Kconfig create mode 100644 drivers/mfd/Makefile create mode 100644 drivers/mfd/atmel-smc.c create mode 100644 include/linux/mfd/syscon/atmel-smc.h (limited to 'include') diff --git a/drivers/Kconfig b/drivers/Kconfig index 75ac149d311..9101e538b09 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -62,6 +62,8 @@ source "drivers/mailbox/Kconfig" source "drivers/memory/Kconfig" +source "drivers/mfd/Kconfig" + source "drivers/misc/Kconfig" source "drivers/mmc/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 6f1de58e003..83b14ef1fd3 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -103,6 +103,7 @@ obj-$(CONFIG_QE) += qe/ obj-$(CONFIG_U_QE) += qe/ obj-y += mailbox/ obj-y += memory/ +obj-y += mfd/ obj-y += mtd/ obj-y += pwm/ obj-y += reset/ diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig new file mode 100644 index 00000000000..ae53b02f27c --- /dev/null +++ b/drivers/mfd/Kconfig @@ -0,0 +1,4 @@ +config MFD_ATMEL_SMC + bool "Atmel Static Memory Controller driver" + help + Say yes here to support Atmel Static Memory Controller driver. diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile new file mode 100644 index 00000000000..4454815a981 --- /dev/null +++ b/drivers/mfd/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_MFD_ATMEL_SMC) += atmel-smc.o diff --git a/drivers/mfd/atmel-smc.c b/drivers/mfd/atmel-smc.c new file mode 100644 index 00000000000..15296f71a16 --- /dev/null +++ b/drivers/mfd/atmel-smc.c @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Atmel SMC (Static Memory Controller) helper functions. + * + * Copyright (C) 2022 Microchip Technology Inc. + * Copyright (C) 2017 Free Electrons + * + * Author: Boris Brezillon + */ + +#include +#include +#include +#include +#include +#include + +/** + * atmel_smc_cs_conf_init - initialize a SMC CS conf + * @conf: the SMC CS conf to initialize + * + * Set all fields to 0 so that one can start defining a new config. + */ +void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf) +{ + memset(conf, 0, sizeof(*conf)); +} +EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_init); + +/** + * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the + * format expected by the SMC engine + * @ncycles: number of MCK clk cycles + * @msbpos: position of the MSB part of the timing field + * @msbwidth: width of the MSB part of the timing field + * @msbfactor: factor applied to the MSB + * @encodedval: param used to store the encoding result + * + * This function encodes the @ncycles value as described in the datasheet + * (section "SMC Setup/Pulse/Cycle/Timings Register"). This is a generic + * helper which called with different parameter depending on the encoding + * scheme. + * + * If the @ncycles value is too big to be encoded, -ERANGE is returned and + * the encodedval is contains the maximum val. Otherwise, 0 is returned. + */ +static int atmel_smc_cs_encode_ncycles(unsigned int ncycles, + unsigned int msbpos, + unsigned int msbwidth, + unsigned int msbfactor, + unsigned int *encodedval) +{ + unsigned int lsbmask = GENMASK(msbpos - 1, 0); + unsigned int msbmask = GENMASK(msbwidth - 1, 0); + unsigned int msb, lsb; + int ret = 0; + + msb = ncycles / msbfactor; + lsb = ncycles % msbfactor; + + if (lsb > lsbmask) { + lsb = 0; + msb++; + } + + /* + * Let's just put the maximum we can if the requested setting does + * not fit in the register field. + * We still return -ERANGE in case the caller cares. + */ + if (msb > msbmask) { + msb = msbmask; + lsb = lsbmask; + ret = -ERANGE; + } + + *encodedval = (msb << msbpos) | lsb; + + return ret; +} + +/** + * atmel_smc_cs_conf_set_timing - set the SMC CS conf Txx parameter to a + * specific value + * @conf: SMC CS conf descriptor + * @shift: the position of the Txx field in the TIMINGS register + * @ncycles: value (expressed in MCK clk cycles) to assign to this Txx + * parameter + * + * This function encodes the @ncycles value as described in the datasheet + * (section "SMC Timings Register"), and then stores the result in the + * @conf->timings field at @shift position. + * + * Returns -EINVAL if shift is invalid, -ERANGE if ncycles does not fit in + * the field, and 0 otherwise. + */ +int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf, + unsigned int shift, unsigned int ncycles) +{ + unsigned int val; + int ret; + + if (shift != ATMEL_HSMC_TIMINGS_TCLR_SHIFT && + shift != ATMEL_HSMC_TIMINGS_TADL_SHIFT && + shift != ATMEL_HSMC_TIMINGS_TAR_SHIFT && + shift != ATMEL_HSMC_TIMINGS_TRR_SHIFT && + shift != ATMEL_HSMC_TIMINGS_TWB_SHIFT) + return -EINVAL; + + /* + * The formula described in atmel datasheets (section "HSMC Timings + * Register"): + * + * ncycles = (Txx[3] * 64) + Txx[2:0] + */ + ret = atmel_smc_cs_encode_ncycles(ncycles, 3, 1, 64, &val); + conf->timings &= ~GENMASK(shift + 3, shift); + conf->timings |= val << shift; + + return ret; +} +EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_timing); + +/** + * atmel_smc_cs_conf_set_setup - set the SMC CS conf xx_SETUP parameter to a + * specific value + * @conf: SMC CS conf descriptor + * @shift: the position of the xx_SETUP field in the SETUP register + * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_SETUP + * parameter + * + * This function encodes the @ncycles value as described in the datasheet + * (section "SMC Setup Register"), and then stores the result in the + * @conf->setup field at @shift position. + * + * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in + * the field, and 0 otherwise. + */ +int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf, + unsigned int shift, unsigned int ncycles) +{ + unsigned int val; + int ret; + + if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT && + shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT) + return -EINVAL; + + /* + * The formula described in atmel datasheets (section "SMC Setup + * Register"): + * + * ncycles = (128 * xx_SETUP[5]) + xx_SETUP[4:0] + */ + ret = atmel_smc_cs_encode_ncycles(ncycles, 5, 1, 128, &val); + conf->setup &= ~GENMASK(shift + 7, shift); + conf->setup |= val << shift; + + return ret; +} +EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_setup); + +/** + * atmel_smc_cs_conf_set_pulse - set the SMC CS conf xx_PULSE parameter to a + * specific value + * @conf: SMC CS conf descriptor + * @shift: the position of the xx_PULSE field in the PULSE register + * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_PULSE + * parameter + * + * This function encodes the @ncycles value as described in the datasheet + * (section "SMC Pulse Register"), and then stores the result in the + * @conf->setup field at @shift position. + * + * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in + * the field, and 0 otherwise. + */ +int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf, + unsigned int shift, unsigned int ncycles) +{ + unsigned int val; + int ret; + + if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT && + shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT) + return -EINVAL; + + /* + * The formula described in atmel datasheets (section "SMC Pulse + * Register"): + * + * ncycles = (256 * xx_PULSE[6]) + xx_PULSE[5:0] + */ + ret = atmel_smc_cs_encode_ncycles(ncycles, 6, 1, 256, &val); + conf->pulse &= ~GENMASK(shift + 7, shift); + conf->pulse |= val << shift; + + return ret; +} +EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_pulse); + +/** + * atmel_smc_cs_conf_set_cycle - set the SMC CS conf xx_CYCLE parameter to a + * specific value + * @conf: SMC CS conf descriptor + * @shift: the position of the xx_CYCLE field in the CYCLE register + * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_CYCLE + * parameter + * + * This function encodes the @ncycles value as described in the datasheet + * (section "SMC Cycle Register"), and then stores the result in the + * @conf->setup field at @shift position. + * + * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in + * the field, and 0 otherwise. + */ +int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf, + unsigned int shift, unsigned int ncycles) +{ + unsigned int val; + int ret; + + if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NRD_SHIFT) + return -EINVAL; + + /* + * The formula described in atmel datasheets (section "SMC Cycle + * Register"): + * + * ncycles = (xx_CYCLE[8:7] * 256) + xx_CYCLE[6:0] + */ + ret = atmel_smc_cs_encode_ncycles(ncycles, 7, 2, 256, &val); + conf->cycle &= ~GENMASK(shift + 15, shift); + conf->cycle |= val << shift; + + return ret; +} +EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_cycle); + +/** + * atmel_smc_cs_conf_apply - apply an SMC CS conf + * @regmap: the SMC regmap + * @cs: the CS id + * @conf: the SMC CS conf to apply + * + * Applies an SMC CS configuration. + * Only valid on at91sam9/avr32 SoCs. + */ +void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs, + const struct atmel_smc_cs_conf *conf) +{ + regmap_write(regmap, ATMEL_SMC_SETUP(cs), conf->setup); + regmap_write(regmap, ATMEL_SMC_PULSE(cs), conf->pulse); + regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle); + regmap_write(regmap, ATMEL_SMC_MODE(cs), conf->mode); +} +EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_apply); + +/** + * atmel_hsmc_cs_conf_apply - apply an SMC CS conf + * @regmap: the HSMC regmap + * @cs: the CS id + * @layout: the layout of registers + * @conf: the SMC CS conf to apply + * + * Applies an SMC CS configuration. + * Only valid on post-sama5 SoCs. + */ +void atmel_hsmc_cs_conf_apply(struct regmap *regmap, + const struct atmel_hsmc_reg_layout *layout, + int cs, const struct atmel_smc_cs_conf *conf) +{ + regmap_write(regmap, ATMEL_HSMC_SETUP(layout, cs), conf->setup); + regmap_write(regmap, ATMEL_HSMC_PULSE(layout, cs), conf->pulse); + regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle); + regmap_write(regmap, ATMEL_HSMC_TIMINGS(layout, cs), conf->timings); + regmap_write(regmap, ATMEL_HSMC_MODE(layout, cs), conf->mode); +} +EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_apply); + +/** + * atmel_smc_cs_conf_get - retrieve the current SMC CS conf + * @regmap: the SMC regmap + * @cs: the CS id + * @conf: the SMC CS conf object to store the current conf + * + * Retrieve the SMC CS configuration. + * Only valid on at91sam9/avr32 SoCs. + */ +void atmel_smc_cs_conf_get(struct regmap *regmap, int cs, + struct atmel_smc_cs_conf *conf) +{ + regmap_read(regmap, ATMEL_SMC_SETUP(cs), &conf->setup); + regmap_read(regmap, ATMEL_SMC_PULSE(cs), &conf->pulse); + regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle); + regmap_read(regmap, ATMEL_SMC_MODE(cs), &conf->mode); +} +EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_get); + +/** + * atmel_hsmc_cs_conf_get - retrieve the current SMC CS conf + * @regmap: the HSMC regmap + * @cs: the CS id + * @layout: the layout of registers + * @conf: the SMC CS conf object to store the current conf + * + * Retrieve the SMC CS configuration. + * Only valid on post-sama5 SoCs. + */ +void atmel_hsmc_cs_conf_get(struct regmap *regmap, + const struct atmel_hsmc_reg_layout *layout, + int cs, struct atmel_smc_cs_conf *conf) +{ + regmap_read(regmap, ATMEL_HSMC_SETUP(layout, cs), &conf->setup); + regmap_read(regmap, ATMEL_HSMC_PULSE(layout, cs), &conf->pulse); + regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle); + regmap_read(regmap, ATMEL_HSMC_TIMINGS(layout, cs), &conf->timings); + regmap_read(regmap, ATMEL_HSMC_MODE(layout, cs), &conf->mode); +} +EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_get); + +static const struct atmel_hsmc_reg_layout sama5d3_reg_layout = { + .timing_regs_offset = 0x600, +}; + +static const struct atmel_hsmc_reg_layout sama5d2_reg_layout = { + .timing_regs_offset = 0x700, +}; + +static const struct udevice_id atmel_smc_ids[] = { + { .compatible = "atmel,at91sam9260-smc", .data = (ulong)0 }, + { .compatible = "atmel,sama5d3-smc", .data = (ulong)&sama5d3_reg_layout }, + { .compatible = "atmel,sama5d2-smc", .data = (ulong)&sama5d2_reg_layout }, + { /* sentinel */ }, +}; + +/** + * atmel_hsmc_get_reg_layout - retrieve the layout of HSMC registers + * @np: the HSMC regmap + * + * Retrieve the layout of HSMC registers. + * + * Returns NULL in case of SMC, a struct atmel_hsmc_reg_layout pointer + * in HSMC case, otherwise ERR_PTR(-EINVAL). + */ +const struct atmel_hsmc_reg_layout * +atmel_hsmc_get_reg_layout(ofnode np) +{ + int i; + const struct udevice_id *match; + const char *name; + int len; + + name = ofnode_get_property(np, "compatible", &len); + + for (i = 0; i < ARRAY_SIZE(atmel_smc_ids); i++) { + if (!strcmp(name, atmel_smc_ids[i].compatible)) { + match = &atmel_smc_ids[i]; + break; + } + } + + return match ? (struct atmel_hsmc_reg_layout *)match->data : ERR_PTR(-EINVAL); +} diff --git a/include/linux/mfd/syscon/atmel-smc.h b/include/linux/mfd/syscon/atmel-smc.h new file mode 100644 index 00000000000..74be5a199fe --- /dev/null +++ b/include/linux/mfd/syscon/atmel-smc.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Atmel SMC (Static Memory Controller) register offsets and bit definitions. + * + * Copyright (C) 2014 Atmel + * Copyright (C) 2014 Free Electrons + * + * Author: Boris Brezillon + */ + +#ifndef _LINUX_MFD_SYSCON_ATMEL_SMC_H_ +#define _LINUX_MFD_SYSCON_ATMEL_SMC_H_ + +#include +#include +#include + +#define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) +#define ATMEL_HSMC_SETUP(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14)) +#define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) +#define ATMEL_HSMC_PULSE(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4) +#define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) +#define ATMEL_HSMC_CYCLE(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x8) +#define ATMEL_SMC_NWE_SHIFT 0 +#define ATMEL_SMC_NCS_WR_SHIFT 8 +#define ATMEL_SMC_NRD_SHIFT 16 +#define ATMEL_SMC_NCS_RD_SHIFT 24 + +#define ATMEL_SMC_MODE(cs) (((cs) * 0x10) + 0xc) +#define ATMEL_HSMC_MODE(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x10) +#define ATMEL_SMC_MODE_READMODE_MASK BIT(0) +#define ATMEL_SMC_MODE_READMODE_NCS (0 << 0) +#define ATMEL_SMC_MODE_READMODE_NRD (1 << 0) +#define ATMEL_SMC_MODE_WRITEMODE_MASK BIT(1) +#define ATMEL_SMC_MODE_WRITEMODE_NCS (0 << 1) +#define ATMEL_SMC_MODE_WRITEMODE_NWE (1 << 1) +#define ATMEL_SMC_MODE_EXNWMODE_MASK GENMASK(5, 4) +#define ATMEL_SMC_MODE_EXNWMODE_DISABLE (0 << 4) +#define ATMEL_SMC_MODE_EXNWMODE_FROZEN (2 << 4) +#define ATMEL_SMC_MODE_EXNWMODE_READY (3 << 4) +#define ATMEL_SMC_MODE_BAT_MASK BIT(8) +#define ATMEL_SMC_MODE_BAT_SELECT (0 << 8) +#define ATMEL_SMC_MODE_BAT_WRITE (1 << 8) +#define ATMEL_SMC_MODE_DBW_MASK GENMASK(13, 12) +#define ATMEL_SMC_MODE_DBW_8 (0 << 12) +#define ATMEL_SMC_MODE_DBW_16 (1 << 12) +#define ATMEL_SMC_MODE_DBW_32 (2 << 12) +#define ATMEL_SMC_MODE_TDF_MASK GENMASK(19, 16) +#define ATMEL_SMC_MODE_TDF(x) (((x) - 1) << 16) +#define ATMEL_SMC_MODE_TDF_MAX 16 +#define ATMEL_SMC_MODE_TDF_MIN 1 +#define ATMEL_SMC_MODE_TDFMODE_OPTIMIZED BIT(20) +#define ATMEL_SMC_MODE_PMEN BIT(24) +#define ATMEL_SMC_MODE_PS_MASK GENMASK(29, 28) +#define ATMEL_SMC_MODE_PS_4 (0 << 28) +#define ATMEL_SMC_MODE_PS_8 (1 << 28) +#define ATMEL_SMC_MODE_PS_16 (2 << 28) +#define ATMEL_SMC_MODE_PS_32 (3 << 28) + +#define ATMEL_HSMC_TIMINGS(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14) + 0xc) +#define ATMEL_HSMC_TIMINGS_OCMS BIT(12) +#define ATMEL_HSMC_TIMINGS_RBNSEL(x) ((x) << 28) +#define ATMEL_HSMC_TIMINGS_NFSEL BIT(31) +#define ATMEL_HSMC_TIMINGS_TCLR_SHIFT 0 +#define ATMEL_HSMC_TIMINGS_TADL_SHIFT 4 +#define ATMEL_HSMC_TIMINGS_TAR_SHIFT 8 +#define ATMEL_HSMC_TIMINGS_TRR_SHIFT 16 +#define ATMEL_HSMC_TIMINGS_TWB_SHIFT 24 + +struct atmel_hsmc_reg_layout { + unsigned int timing_regs_offset; +}; + +/** + * struct atmel_smc_cs_conf - SMC CS config as described in the datasheet. + * @setup: NCS/NWE/NRD setup timings (not applicable to at91rm9200) + * @pulse: NCS/NWE/NRD pulse timings (not applicable to at91rm9200) + * @cycle: NWE/NRD cycle timings (not applicable to at91rm9200) + * @timings: advanced NAND related timings (only applicable to HSMC) + * @mode: all kind of config parameters (see the fields definition above). + * The mode fields are different on at91rm9200 + */ +struct atmel_smc_cs_conf { + u32 setup; + u32 pulse; + u32 cycle; + u32 timings; + u32 mode; +}; + +void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf); +int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf, + unsigned int shift, + unsigned int ncycles); +int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf, + unsigned int shift, unsigned int ncycles); +int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf, + unsigned int shift, unsigned int ncycles); +int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf, + unsigned int shift, unsigned int ncycles); +void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs, + const struct atmel_smc_cs_conf *conf); +void atmel_hsmc_cs_conf_apply(struct regmap *regmap, + const struct atmel_hsmc_reg_layout *reglayout, + int cs, const struct atmel_smc_cs_conf *conf); +void atmel_smc_cs_conf_get(struct regmap *regmap, int cs, + struct atmel_smc_cs_conf *conf); +void atmel_hsmc_cs_conf_get(struct regmap *regmap, + const struct atmel_hsmc_reg_layout *reglayout, + int cs, struct atmel_smc_cs_conf *conf); +const struct atmel_hsmc_reg_layout * +atmel_hsmc_get_reg_layout(ofnode np); + +#endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */ -- cgit v1.3.1 From c41e05bab0b025691741d819ff372c08e285b99a Mon Sep 17 00:00:00 2001 From: Balamanikandan Gunasundar Date: Tue, 25 Oct 2022 16:21:09 +0530 Subject: board: sam9x60ek: remove nand init from board file Move this out of board file as this is done by the DM based NAND flash driver. The EBI chip select configuration, iomux and timings are handled by the driver Signed-off-by: Balamanikandan Gunasundar --- board/atmel/sam9x60ek/sam9x60ek.c | 59 --------------------------------------- include/configs/sam9x60ek.h | 9 ------ 2 files changed, 68 deletions(-) (limited to 'include') diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index a3e35f30666..04bf2bb5c96 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -24,62 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; void at91_prepare_cpu_var(void); -#ifdef CONFIG_CMD_NAND -static void sam9x60ek_nand_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; - unsigned int csa; - - at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */ - /* Enable NandFlash */ - at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); - /* Configure RDY/BSY */ - at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); - - at91_periph_clk_enable(ATMEL_ID_PIOD); - - /* Enable CS3 */ - csa = readl(&sfr->ebicsa); - csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16; - - /* Configure IO drive */ - csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60; - - writel(csa, &sfr->ebicsa); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup); - - writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) | - AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20), - &smc->cs[3].pulse); - - writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20), - &smc->cs[3].cycle); - - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | -#ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_MODE_DBW_16 | -#else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_MODE_DBW_8 | -#endif - AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15), - &smc->cs[3].mode); -} -#endif - #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { @@ -122,9 +66,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; -#ifdef CONFIG_CMD_NAND - sam9x60ek_nand_hw_init(); -#endif return 0; } diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 27b39ebf417..cb7f35c7ca4 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -26,13 +26,4 @@ #define CFG_SYS_SDRAM_BASE 0x20000000 #define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CFG_SYS_NAND_BASE 0x40000000 -#define CFG_SYS_NAND_MASK_ALE BIT(21) -#define CFG_SYS_NAND_MASK_CLE BIT(22) -#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5 -#endif - #endif -- cgit v1.3.1 From 640aecb416cff52cf8a89d786d41e6eee54c94ff Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Nov 2022 12:54:52 -0500 Subject: rtc: Add fallbacks for dm functions This adds fallbacks for the various dm_rtc_* functions. This allows common code to use these functions without ifdefs. Fixes: c8ce7ba87d1 ("misc: Add support for nvmem cells") Reviewed-by: Simon Glass Signed-off-by: Sean Anderson --- include/rtc.h | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/rtc.h b/include/rtc.h index 10104e3bf5a..b6fdbb60dc2 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -15,13 +15,12 @@ #include #include +#include typedef int64_t time64_t; - -#ifdef CONFIG_DM_RTC - struct udevice; +#if CONFIG_IS_ENABLED(DM_RTC) struct rtc_ops { /** * get() - get the current time @@ -222,6 +221,33 @@ int rtc_enable_32khz_output(int busnum, int chip_addr); #endif #else +static inline int dm_rtc_get(struct udevice *dev, struct rtc_time *time) +{ + return -ENOSYS; +} + +static inline int dm_rtc_set(struct udevice *dev, struct rtc_time *time) +{ + return -ENOSYS; +} + +static inline int dm_rtc_reset(struct udevice *dev) +{ + return -ENOSYS; +} + +static inline int dm_rtc_read(struct udevice *dev, unsigned int reg, u8 *buf, + unsigned int len) +{ + return -ENOSYS; +} + +static inline int dm_rtc_write(struct udevice *dev, unsigned int reg, + const u8 *buf, unsigned int len) +{ + return -ENOSYS; +} + int rtc_get (struct rtc_time *); int rtc_set (struct rtc_time *); void rtc_reset (void); -- cgit v1.3.1 From 253802912a65fde6ba9328462ef4b8574932c8f3 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 3 Nov 2022 19:13:51 -0500 Subject: arm: dts: introduce am62a7 dtbs from linux kernel Introduce the basic am62a7 SoC dtbs from the v6.1-rc3 tag of the linux kernel along with the new am62a specific pinmux definition that we will use to generate the dtbs for the u-boot-spl and u-boot binaries Co-developed-by: Vignesh Raghavendra Signed-off-by: Vignesh Raghavendra Signed-off-by: Bryan Brattlof --- arch/arm/dts/k3-am62a-main.dtsi | 298 ++++++++++++++++++++++++++++++++++++++ arch/arm/dts/k3-am62a-mcu.dtsi | 39 +++++ arch/arm/dts/k3-am62a-wakeup.dtsi | 54 +++++++ arch/arm/dts/k3-am62a.dtsi | 122 ++++++++++++++++ arch/arm/dts/k3-am62a7-sk.dts | 223 ++++++++++++++++++++++++++++ arch/arm/dts/k3-am62a7.dtsi | 103 +++++++++++++ include/dt-bindings/pinctrl/k3.h | 3 + 7 files changed, 842 insertions(+) create mode 100644 arch/arm/dts/k3-am62a-main.dtsi create mode 100644 arch/arm/dts/k3-am62a-mcu.dtsi create mode 100644 arch/arm/dts/k3-am62a-wakeup.dtsi create mode 100644 arch/arm/dts/k3-am62a.dtsi create mode 100644 arch/arm/dts/k3-am62a7-sk.dts create mode 100644 arch/arm/dts/k3-am62a7.dtsi (limited to 'include') diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi new file mode 100644 index 00000000000..bc4b50bcd17 --- /dev/null +++ b/arch/arm/dts/k3-am62a-main.dtsi @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62A SoC Family Main Domain peripherals + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + oc_sram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x00 0x70000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x70000000 0x10000>; + }; + + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = ; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_conf: syscon@100000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00100000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x20000>; + }; + + dmss: bus@48000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; + + ti,sci-dev-id = <25>; + + secure_proxy_main: mailbox@4d000000 { + compatible = "ti,am654-secure-proxy"; + reg = <0x00 0x4d000000 0x00 0x80000>, + <0x00 0x4a600000 0x00 0x80000>, + <0x00 0x4a400000 0x00 0x80000>; + reg-names = "target_data", "rt", "scfg"; + #mbox-cells = <1>; + interrupt-names = "rx_012"; + interrupts = ; + }; + }; + + dmsc: system-controller@44043000 { + compatible = "ti,k2g-sci"; + reg = <0x00 0x44043000 0x00 0xfe0>; + reg-names = "debug_messages"; + ti,host-id = <12>; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 12>, + <&secure_proxy_main 13>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + main_pmx0: pinctrl@f4000 { + compatible = "pinctrl-single"; + reg = <0x00 0xf4000 0x00 0x2ac>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 146 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 153 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart3: serial@2830000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 154 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart4: serial@2840000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 155 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart5: serial@2850000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart6: serial@2860000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_i2c0: i2c@20000000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20000000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c1: i2c@20010000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20010000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 103 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c2: i2c@20020000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20020000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 104 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c3: i2c@20030000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20030000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 105 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <3>; + ti,interrupt-ranges = <0 32 16>; + status = "disabled"; + }; + + main_gpio0: gpio@600000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00600000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <190>, <191>, <192>, + <193>, <194>, <195>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <87>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 77 0>; + clock-names = "gpio"; + status = "disabled"; + }; + + main_gpio1: gpio@601000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00601000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <180>, <181>, <182>, + <183>, <184>, <185>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <88>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 78 0>; + clock-names = "gpio"; + status = "disabled"; + }; + + sdhci1: mmc@fa00000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; + clock-names = "clk_ahb", "clk_xin"; + ti,trm-icp = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,clkbuf-sel = <0x7>; + bus-width = <4>; + no-1-8-v; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/k3-am62a-mcu.dtsi b/arch/arm/dts/k3-am62a-mcu.dtsi new file mode 100644 index 00000000000..6d1e501b94a --- /dev/null +++ b/arch/arm/dts/k3-am62a-mcu.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family MCU Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu { + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x04084000 0x00 0x88>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + status = "disabled"; + }; + + mcu_uart0: serial@4a00000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x04a00000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 149 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + mcu_i2c0: i2c@4900000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x04900000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 106 2>; + clock-names = "fck"; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/k3-am62a-wakeup.dtsi b/arch/arm/dts/k3-am62a-wakeup.dtsi new file mode 100644 index 00000000000..99afac40e8d --- /dev/null +++ b/arch/arm/dts/k3-am62a-wakeup.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_wakeup { + wkup_conf: syscon@43000000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x43000000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x43000000 0x20000>; + + chipid: chipid@14 { + compatible = "ti,am654-chipid"; + reg = <0x14 0x4>; + }; + }; + + wkup_uart0: serial@2b300000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x2b300000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + wkup_i2c0: i2c@2b200000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02b200000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 107 4>; + clock-names = "fck"; + status = "disabled"; + }; + + wkup_rtc0: rtc@2b1f0000 { + compatible = "ti,am62-rtc"; + reg = <0x00 0x2b1f0000 0x00 0x100>; + interrupts = ; + clocks = <&k3_clks 117 6> , <&k3_clks 117 0>; + clock-names = "vbus", "osc32k"; + power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; + wakeup-source; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/k3-am62a.dtsi b/arch/arm/dts/k3-am62a.dtsi new file mode 100644 index 00000000000..6eb87c3f9f3 --- /dev/null +++ b/arch/arm/dts/k3-am62a.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62A SoC Family + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include +#include + +/ { + model = "Texas Instruments K3 AM62A SoC"; + compatible = "ti,am62a7"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ + <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00100000>, /* C7x_0 */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */ + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */ + + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */ + + cbass_mcu: bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ + }; + + cbass_wakeup: bus@b00000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ + }; + }; +}; + +/* Now include the peripherals for each bus segments */ +#include "k3-am62a-main.dtsi" +#include "k3-am62a-mcu.dtsi" +#include "k3-am62a-wakeup.dtsi" diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts new file mode 100644 index 00000000000..576dbce80ad --- /dev/null +++ b/arch/arm/dts/k3-am62a7-sk.dts @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62A SK: https://www.ti.com/lit/zip/sprr459 + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include +#include +#include "k3-am62a7.dtsi" + +/ { + compatible = "ti,am62a7-sk", "ti,am62a7"; + model = "Texas Instruments AM62A7 SK"; + + aliases { + serial2 = &main_uart0; + mmc1 = &sdhci1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + }; + + vmain_pd: regulator-0 { + /* TPS25750 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_5v0: regulator-1 { + /* Output of TPS63070 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: regulator-2 { + /* output of LM5141-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-3 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62a-sk:green:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + }; +}; + +&main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ + AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ + AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ + AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ + AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ + AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ + AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ + >; + }; + + usr_led_pins_default: usr-led-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ + >; + }; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "BT_EN_SOC", "MMC1_SD_EN", + "VPP_EN", "EXP_PS_3V3_En", + "EXP_PS_5V0_En", "EXP_HAT_DETECT", + "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", + "UART1_FET_BUF_EN", "BT_UART_WAKE_SOC", + "GPIO_HDMI_RSTn", "CSI_GPIO0", + "CSI_GPIO1", "WLAN_ALERTn", + "HDMI_INTn", "TEST_GPIO2", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "UART1_FET_SEL", + "PD_I2C_IRQ", "IO_EXP_TEST_LED"; + }; +}; + +&sdhci1 { + /* SD/MMC */ + status = "okay"; + vmmc-supply = <&vdd_mmc1>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_gpio0 { + status = "okay"; +}; + +&main_gpio1 { + status = "okay"; +}; + +&main_gpio_intr { + status = "okay"; +}; + +&main_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; +}; diff --git a/arch/arm/dts/k3-am62a7.dtsi b/arch/arm/dts/k3-am62a7.dtsi new file mode 100644 index 00000000000..331d89fda29 --- /dev/null +++ b/arch/arm/dts/k3-am62a7.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62A7 SoC family in Quad core configuration + * + * TRM: https://www.ti.com/lit/zip/spruj16 + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am62a.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + }; +}; diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index a5204ab91d3..e8418318eb9 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -44,4 +44,7 @@ #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #endif -- cgit v1.3.1 From b6cbcd61556e0d9de4c389071e3a826e577b9f43 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 3 Nov 2022 19:13:56 -0500 Subject: arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof --- arch/arm/mach-k3/am62ax/Makefile | 6 + arch/arm/mach-k3/am62ax/clk-data.c | 317 +++++++++++++++++++++++++++++++++ arch/arm/mach-k3/am62ax/dev-data.c | 73 ++++++++ drivers/clk/ti/clk-k3.c | 6 + drivers/power/domain/ti-power-domain.c | 6 + include/k3-clk.h | 1 + include/k3-dev.h | 1 + 7 files changed, 410 insertions(+) create mode 100644 arch/arm/mach-k3/am62ax/Makefile create mode 100644 arch/arm/mach-k3/am62ax/clk-data.c create mode 100644 arch/arm/mach-k3/am62ax/dev-data.c (limited to 'include') diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile new file mode 100644 index 00000000000..c58e52df1fa --- /dev/null +++ b/arch/arm/mach-k3/am62ax/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/am62ax/clk-data.c b/arch/arm/mach-k3/am62ax/clk-data.c new file mode 100644 index 00000000000..d950b35e0be --- /dev/null +++ b/arch/arm/mach-k3/am62ax/clk-data.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62AX specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof . + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + NULL, + NULL, + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + NULL, +}; + +static const char * const clk_32k_rc_sel_out0_parents[] = { + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_hfosc0_clkout", + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_lfosc0_clkout", +}; + +static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = { + "board_0_mmc0_clklb_out", + "board_0_mmc0_clk_out", +}; + +static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = { + "board_0_mmc1_clklb_out", + "board_0_mmc1_clk_out", +}; + +static const char * const main_ospi_loopback_clk_sel_out0_parents[] = { + "board_0_ospi0_dqs_out", + "board_0_ospi0_lbclko_out", +}; + +static const char * const main_usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const main_usb1_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const clkout0_ctrl_out0_parents[] = { + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", +}; + +static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_gtcclk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout1_clk", + "postdiv1_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_clkout_sel_out0_parents[] = { + NULL, + "gluelogic_lfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "postdiv4_16ff_main_2_hsdivout9_clk", + "clk_32k_rc_sel_out0", + "gluelogic_rcosc_clkout", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clkout_sel_io_out0_parents[] = { + "wkup_clkout_sel_out0", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clksel_out0_parents[] = { + "hsdiv2_16fft_main_15_hsdivout0_clk", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const main_usart0_fclk_sel_out0_parents[] = { + "usart_programmable_clock_divider_out0", + "hsdiv4_16fft_main_1_hsdivout1_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0), + CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0), + CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0), + CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0), + CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0), + CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0), + CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0), + CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0), + CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0), + CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv2_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), + CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), + CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), + CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), + CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000), + CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0), + CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0), + CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0), + CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0), + CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 5, "board_0_ext_refclk1_out"), + DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"), + DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 9, "board_0_ext_refclk1_out"), + DEV_CLK(16, 10, "gluelogic_rcosc_clkout"), + DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"), + DEV_CLK(57, 1, "board_0_mmc0_clklb_out"), + DEV_CLK(57, 2, "board_0_mmc0_clk_out"), + DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"), + DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), + DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), + DEV_CLK(58, 2, "board_0_mmc1_clk_out"), + DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"), + DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(61, 0, "main_gtcclk_sel_out0"), + DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 6, "board_0_ext_refclk1_out"), + DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 9, "wkup_clksel_out0"), + DEV_CLK(61, 10, "hsdiv2_16fft_main_15_hsdivout0_clk"), + DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(75, 0, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"), + DEV_CLK(75, 3, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"), + DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"), + DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"), + DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(95, 0, "gluelogic_rcosc_clkout"), + DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"), + DEV_CLK(95, 2, "wkup_clksel_out0"), + DEV_CLK(95, 3, "hsdiv2_16fft_main_15_hsdivout0_clk"), + DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(102, 1, "board_0_i2c0_scl_out"), + DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"), + DEV_CLK(107, 0, "wkup_clksel_out0"), + DEV_CLK(107, 1, "hsdiv2_16fft_main_15_hsdivout0_clk"), + DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"), + DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"), + DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"), + DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 20, "clkout0_ctrl_out0"), + DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 25, "board_0_ddr0_ck0_out"), + DEV_CLK(157, 40, "mshsi2c_main_0_porscl"), + DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"), + DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"), + DEV_CLK(157, 160, "wkup_clkout_sel_out0"), + DEV_CLK(157, 161, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"), + DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(161, 10, "board_0_tck_out"), + DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"), + DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(162, 10, "board_0_tck_out"), + DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(170, 2, "board_0_tck_out"), + DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata am62ax_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 80, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 104, +}; diff --git a/arch/arm/mach-k3/am62ax/dev-data.c b/arch/arm/mach-k3/am62ax/dev-data.c new file mode 100644 index 00000000000..74739c63852 --- /dev/null +++ b/arch/arm/mach-k3/am62ax/dev-data.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62AX specific device platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof . + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x04000000), + [1] = PSC(1, 0x00400000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[1], NULL), + [1] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]), + [2] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[1]), + [3] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[5]), + [2] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[6]), + [3] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [4] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [5] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [6] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [7] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [8] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [9] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]), + [10] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[9]), + [11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]), + [12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]), + [13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(16, &soc_lpsc_list[0]), + PSC_DEV(77, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[0]), + PSC_DEV(95, &soc_lpsc_list[0]), + PSC_DEV(107, &soc_lpsc_list[0]), + PSC_DEV(178, &soc_lpsc_list[1]), + PSC_DEV(179, &soc_lpsc_list[2]), + PSC_DEV(57, &soc_lpsc_list[3]), + PSC_DEV(58, &soc_lpsc_list[4]), + PSC_DEV(161, &soc_lpsc_list[5]), + PSC_DEV(162, &soc_lpsc_list[6]), + PSC_DEV(75, &soc_lpsc_list[7]), + PSC_DEV(102, &soc_lpsc_list[8]), + PSC_DEV(146, &soc_lpsc_list[8]), + PSC_DEV(166, &soc_lpsc_list[9]), + PSC_DEV(135, &soc_lpsc_list[10]), + PSC_DEV(170, &soc_lpsc_list[11]), + PSC_DEV(177, &soc_lpsc_list[12]), + PSC_DEV(55, &soc_lpsc_list[13]), +}; + +const struct ti_k3_pd_platdata am62ax_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = 2, + .num_pd = 4, + .num_lpsc = 14, + .num_devs = 19, +}; diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index 0dd65934b36..ba925fa3c48 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -79,6 +79,12 @@ static const struct soc_attr ti_k3_soc_clk_data[] = { .family = "AM62X", .data = &am62x_clk_platdata, }, +#endif +#ifdef CONFIG_SOC_K3_AM62A7 + { + .family = "AM62AX", + .data = &am62ax_clk_platdata, + }, #endif { /* sentinel */ } }; diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c index a7f64d04f5c..9e7151307c8 100644 --- a/drivers/power/domain/ti-power-domain.c +++ b/drivers/power/domain/ti-power-domain.c @@ -92,6 +92,12 @@ static const struct soc_attr ti_k3_soc_pd_data[] = { .family = "AM62X", .data = &am62x_pd_platdata, }, +#endif +#ifdef CONFIG_SOC_K3_AM62A7 + { + .family = "AM62AX", + .data = &am62ax_pd_platdata, + }, #endif { /* sentinel */ } }; diff --git a/include/k3-clk.h b/include/k3-clk.h index 371f077c447..49ba53d20f7 100644 --- a/include/k3-clk.h +++ b/include/k3-clk.h @@ -175,6 +175,7 @@ extern const struct ti_k3_clk_platdata j721e_clk_platdata; extern const struct ti_k3_clk_platdata j7200_clk_platdata; extern const struct ti_k3_clk_platdata j721s2_clk_platdata; extern const struct ti_k3_clk_platdata am62x_clk_platdata; +extern const struct ti_k3_clk_platdata am62ax_clk_platdata; struct clk *clk_register_ti_pll(const char *name, const char *parent_name, void __iomem *reg); diff --git a/include/k3-dev.h b/include/k3-dev.h index 87e873b9ced..d288ae3be73 100644 --- a/include/k3-dev.h +++ b/include/k3-dev.h @@ -79,6 +79,7 @@ extern const struct ti_k3_pd_platdata j721e_pd_platdata; extern const struct ti_k3_pd_platdata j7200_pd_platdata; extern const struct ti_k3_pd_platdata j721s2_pd_platdata; extern const struct ti_k3_pd_platdata am62x_pd_platdata; +extern const struct ti_k3_pd_platdata am62ax_pd_platdata; u8 ti_pd_state(struct ti_pd *pd); u8 lpsc_get_state(struct ti_lpsc *lpsc); -- cgit v1.3.1 From 719bd650c30e86d43c9a6c1e289e82db802b0d3c Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 3 Nov 2022 19:13:58 -0500 Subject: configs: introduce configs for the am62a Introduce the minimum configs, only SD-MMC and UART boot related settings, to serve as a good starting point for the am62a as we add more functionality. Signed-off-by: Bryan Brattlof [trini: Disable CONFIG_NET as it's not used, in both platforms] Signed-off-by: Tom Rini --- configs/am62ax_evm_a53_defconfig | 77 ++++++++++++++++++++++++++++ configs/am62ax_evm_r5_defconfig | 106 +++++++++++++++++++++++++++++++++++++++ include/configs/am62ax_evm.h | 68 +++++++++++++++++++++++++ 3 files changed, 251 insertions(+) create mode 100644 configs/am62ax_evm_a53_defconfig create mode 100644 configs/am62ax_evm_r5_defconfig create mode 100644 include/configs/am62ax_evm.h (limited to 'include') diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig new file mode 100644 index 00000000000..0c2cf945c62 --- /dev/null +++ b/configs/am62ax_evm_a53_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM62A7=y +CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 +CONFIG_TARGET_AM62A7_A53_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-sk" +CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_CMD_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +# CONFIG_NET is not set +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_TI_SCI_PROTOCOL=y +# CONFIG_GPIO is not set +# CONFIG_I2C is not set +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig new file mode 100644 index 00000000000..59d5f4f80eb --- /dev/null +++ b/configs/am62ax_evm_r5_defconfig @@ -0,0 +1,106 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SOC_K3_AM62A7=y +CONFIG_TARGET_AM62A7_R5_EVM=y +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x680000 +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-r5-sk" +CONFIG_SPL_TEXT_BASE=0x43c00000 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SIZE_LIMIT=0x40000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7000ffff +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c37800 +CONFIG_SPL_BSS_MAX_SIZE=0x5000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DMA=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_THERMAL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +# CONFIG_NET is not set +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +# CONFIG_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y diff --git a/include/configs/am62ax_evm.h b/include/configs/am62ax_evm.h new file mode 100644 index 00000000000..5406c39350f --- /dev/null +++ b/include/configs/am62ax_evm.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 AM62Ax SoC family + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __CONFIG_AM62AX_EVM_H +#define __CONFIG_AM62AX_EVM_H + +#include +#include +#include +#include + +/* DDR Configuration */ +#define CFG_SYS_SDRAM_BASE1 0x880000000 + +#define PARTS_DEFAULT \ + /* Linux partitions */ \ + "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ + +/* U-Boot general configuration */ +#define EXTRA_ENV_AM62A7_BOARD_SETTINGS \ + "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "findfdt=" \ + "setenv name_fdt ${default_device_tree};" \ + "setenv fdtfile ${name_fdt}\0" \ + "name_kern=Image\0" \ + "console=ttyS2,115200n8\0" \ + "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \ + "${mtdparts}\0" \ + "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" + +/* U-Boot MMC-specific configuration */ +#define EXTRA_ENV_AM62A7_BOARD_SETTINGS_MMC \ + "boot=mmc\0" \ + "mmcdev=1\0" \ + "bootpart=1:2\0" \ + "bootdir=/boot\0" \ + "rd_spec=-\0" \ + "init_mmc=run args_all args_mmc\0" \ + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \ + "get_overlay_mmc=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $name_overlays;" \ + "do;" \ + "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \ + "fdt apply ${dtboaddr};" \ + "done;\0" \ + "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_kern}\0" \ + "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \ + "${bootdir}/${name_fit}\0" \ + "partitions=" PARTS_DEFAULT + +/* Incorporate settings into the U-Boot environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + EXTRA_ENV_AM62A7_BOARD_SETTINGS \ + EXTRA_ENV_AM62A7_BOARD_SETTINGS_MMC \ + +/* Now for the remaining common defines */ +#include + +#endif /* __CONFIG_AM62A7_EVM_H */ -- cgit v1.3.1 From a5dacef7380e4414e7fe5831298e31122d24b18d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 28 Oct 2022 11:01:19 +0200 Subject: cmd: pxe: support INITRD and FDT selection with FIT Since the commit d5ba6188dfbf ("cmd: pxe_utils: Check fdtcontroladdr in label_boot") the FDT or the FDTDIR label is required in extlinux.conf and the fallback done by bootm command when only the device tree present in this command parameters is no more performed when FIT is used for kernel. When the label FDT or FDTDIR are absent or if the device tree file is absent, the PXE command in U-Boot uses the default U-Boot device tree selected by fdtcontroladdr = gd->fdt_blob, it is the "Scenario 3". With this scenario the bootm FIP fallback is no more possible with the extlinux.conf when only "kernel" label is present and is a FIP: kernel #[##[##[##[# Reviewed-by: Neil Armstrong --- boot/pxe_utils.c | 17 ++++++++++++++--- doc/README.pxe | 8 ++++++++ include/pxe_utils.h | 2 ++ 3 files changed, 24 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index fc453bd5397..b59e959f715 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -258,6 +258,7 @@ static struct pxe_label *label_create(void) static void label_destroy(struct pxe_label *label) { free(label->name); + free(label->kernel_label); free(label->kernel); free(label->config); free(label->append); @@ -542,9 +543,11 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) kernel_addr = fit_addr; } - if (label->initrd) { + /* For FIT, the label can be identical to kernel one */ + if (label->initrd && !strcmp(label->kernel_label, label->initrd)) { + initrd_addr_str = kernel_addr; + } else if (label->initrd) { ulong size; - if (get_relfile_envaddr(ctx, label->initrd, "ramdisk_addr_r", &size) < 0) { printf("Skipping %s for failure retrieving initrd\n", @@ -622,8 +625,11 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) */ bootm_argv[3] = env_get("fdt_addr_r"); + /* For FIT, the label can be identical to kernel one */ + if (label->fdt && !strcmp(label->kernel_label, label->fdt)) { + bootm_argv[3] = kernel_addr; /* if fdt label is defined then get fdt from server */ - if (bootm_argv[3]) { + } else if (bootm_argv[3]) { char *fdtfile = NULL; char *fdtfilefree = NULL; @@ -1164,6 +1170,11 @@ static int parse_label_kernel(char **c, struct pxe_label *label) if (err < 0) return err; + /* copy the kernel label to compare with FDT / INITRD when FIT is used */ + label->kernel_label = strdup(label->kernel); + if (!label->kernel_label) + return -ENOMEM; + s = strstr(label->kernel, "#"); if (!s) return 1; diff --git a/doc/README.pxe b/doc/README.pxe index d14d2bdcc9b..172201093d0 100644 --- a/doc/README.pxe +++ b/doc/README.pxe @@ -179,11 +179,19 @@ initrd - if this label is chosen, use tftp to retrieve the initrd at . it will be stored at the address indicated in the initrd_addr_r environment variable, and that address will be passed to bootm. + For FIT image, the initrd can be provided with the same value than + kernel, including configuration: + #[# - if this label is chosen, use tftp to retrieve the fdt blob at . it will be stored at the address indicated in the fdt_addr_r environment variable, and that address will be passed to bootm. + For FIT image, the device tree can be provided with the same value + than kernel, including configuration: + #[# - if this label is chosen, use tftp to retrieve the fdt blob at . it will be stored at the address indicated in diff --git a/include/pxe_utils.h b/include/pxe_utils.h index 4a73b2aace3..1e5e8424f53 100644 --- a/include/pxe_utils.h +++ b/include/pxe_utils.h @@ -28,6 +28,7 @@ * Create these with the 'label_create' function given below. * * name - the name of the menu as given on the 'menu label' line. + * kernel_label - the kernel label, including FIT config if present. * kernel - the path to the kernel file to use for this label. * append - kernel command line to use when booting this label * initrd - path to the initrd to use for this label. @@ -40,6 +41,7 @@ struct pxe_label { char num[4]; char *name; char *menu; + char *kernel_label; char *kernel; char *config; char *append; -- cgit v1.3.1 From 828d7e6022f2ae827aa278fc6bc15efee0d0a6b6 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 7 Dec 2022 09:26:40 +0100 Subject: configs: am333x_guardian: move MTDIDS_DEFAULT in defconfif Replace MTDIDS_DEFAULT in config include file by CONFIG_MTDIDS_DEFAULT in defonfig to complete the Kconfig migration Signed-off-by: Patrick Delaunay --- configs/am335x_guardian_defconfig | 1 + include/configs/am335x_guardian.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index fef4fd15510..0feac53c350 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -64,6 +64,7 @@ CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_BMP=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(SPL),256k(SPL.backup1),256k(SPL.backup2),256k(SPL.backup3),1m(u-boot),1m(u-boot.backup1),1m(u-boot-2),1m(u-boot-2.backup1),256k(u-boot-env),256k(u-boot-env.backup1),256k(splash-screen),-(UBI)" CONFIG_CMD_UBI=y # CONFIG_SPL_DOS_PARTITION is not set diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index 7c5e7ce475e..a5b83b0c25d 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -115,7 +115,6 @@ } #define CFG_SYS_NAND_ECCSIZE 512 #define CFG_SYS_NAND_ECCBYTES 26 -#define MTDIDS_DEFAULT "nand0=nand.0" #endif /* CONFIG_MTD_RAW_NAND */ -- cgit v1.3.1 From bde4a407ea89704e5d2dd6d77140a4d2616c171d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 7 Dec 2022 09:26:41 +0100 Subject: configs: x530: move MTDPART/MTDIDS_DEFAULT in defconfig Replace MTDIDS_DEFAULT and MTDPARTS_DEFAULT in the config include file by CONFIG_MTDIDS_DEFAULT and CONFIG_MTDPARTS_DEFAULT in defconfig to complete the Kconfig migration. Signed-off-by: Patrick Delaunay --- configs/x530_defconfig | 2 ++ include/configs/x530.h | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/configs/x530_defconfig b/configs/x530_defconfig index 2f8be2fcd77..70c08adcde9 100644 --- a/configs/x530_defconfig +++ b/configs/x530_defconfig @@ -57,6 +57,8 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)" CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y CONFIG_ARP_TIMEOUT=200 diff --git a/include/configs/x530.h b/include/configs/x530.h index dee87cb7732..c213dc6074b 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -32,8 +32,6 @@ /* SPI NOR flash default params, used by sf commands */ -#define MTDIDS_DEFAULT "nand0=nand" -#define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)" #define MTDPARTS_MTDOOPS "errlog" /* Partition support */ -- cgit v1.3.1 From 91b9551fb3c877f5c35324f31736787b4c7228cd Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 7 Dec 2022 09:26:42 +0100 Subject: configs: SBx81LIFXCAT: move MTDPART_DEFAULT in defconfig Replace MTDPARTS_DEFAULT in the config include file by CONFIG_MTDPARTS_DEFAULT in defconfig to complete the Kconfig migration. Signed-off-by: Patrick Delaunay --- configs/SBx81LIFXCAT_defconfig | 1 + include/configs/SBx81LIFXCAT.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 125871301e3..80dbbb11c9b 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y # CONFIG_CMD_LED is not set +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" CONFIG_DOS_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 9a9663b34ba..23d37394e07 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -21,7 +21,6 @@ * for your console driver. */ -#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" #define MTDPARTS_MTDOOPS "errlog" /* -- cgit v1.3.1 From 72e79f998e79626a551d22c637abf4c5786e8046 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 7 Dec 2022 09:26:43 +0100 Subject: configs: SBx81LIFKW: move MTDPART_DEFAULT in defconfig Replace MTDPARTS_DEFAULT in the config include file by CONFIG_MTDPARTS_DEFAULT in defconfig to complete the Kconfig migration. Signed-off-by: Patrick Delaunay --- configs/SBx81LIFKW_defconfig | 1 + include/configs/SBx81LIFKW.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index fa7c35b9ef7..e53f2489c5d 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTP_NTPSERVER=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" CONFIG_DOS_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index bad34d9771e..d5c9c05767a 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -21,7 +21,6 @@ * for your console driver. */ -#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" #define MTDPARTS_MTDOOPS "errlog" /* -- cgit v1.3.1 From 553d7607c681806a40550696d56e15dcd9a2b0e6 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Dec 2022 18:22:37 +0100 Subject: board/km: move ls102xa boards to environment text files Create a common.env which we can use later on also for other boards. Signed-off-by: Holger Brunck --- board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env | 3 ++ board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env | 3 ++ configs/pg_wcom_expu1_defconfig | 2 +- configs/pg_wcom_expu1_update_defconfig | 2 +- configs/pg_wcom_seli8_defconfig | 2 +- configs/pg_wcom_seli8_update_defconfig | 2 +- include/configs/km/pg-wcom-ls102xa.h | 65 ----------------------- include/configs/pg-wcom-expu1.h | 4 -- include/configs/pg-wcom-seli8.h | 5 -- include/environment/pg-wcom/common.env | 68 +++++++++++++++++++++++++ include/environment/pg-wcom/ls102xa.env | 29 +++++++++++ 11 files changed, 107 insertions(+), 78 deletions(-) create mode 100644 board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env create mode 100644 board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env create mode 100644 include/environment/pg-wcom/common.env create mode 100644 include/environment/pg-wcom/ls102xa.env (limited to 'include') diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env b/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env new file mode 100644 index 00000000000..d960de6bfe0 --- /dev/null +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env @@ -0,0 +1,3 @@ +#include + +hostname=EXPU1 diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env b/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env new file mode 100644 index 00000000000..4031f8bee95 --- /dev/null +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env @@ -0,0 +1,3 @@ +#include + +hostname=SELI8 diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index d21e180d1fc..b57e588f4e9 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -20,7 +20,6 @@ CONFIG_ENV_ADDR=0x60060000 CONFIG_AHCI=y # CONFIG_DEEP_SLEEP is not set CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y @@ -64,6 +63,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index 54773b06339..9029e7babc8 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -19,7 +19,6 @@ CONFIG_ENV_ADDR=0x60220000 CONFIG_AHCI=y # CONFIG_DEEP_SLEEP is not set CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y @@ -62,6 +61,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index 8311b3a3a00..aa74e1746ab 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -20,7 +20,6 @@ CONFIG_ENV_ADDR=0x60060000 CONFIG_AHCI=y # CONFIG_DEEP_SLEEP is not set CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y @@ -64,6 +63,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index d6f4a054790..2b18a88d44f 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -19,7 +19,6 @@ CONFIG_ENV_ADDR=0x60220000 CONFIG_AHCI=y # CONFIG_DEEP_SLEEP is not set CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y @@ -62,6 +61,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index dfa81c037f4..7fe2ece8403 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -6,9 +6,6 @@ #ifndef __CONFIG_PG_WCOM_LS102XA_H #define __CONFIG_PG_WCOM_LS102XA_H -/* include common defines/options for all Keymile boards */ -#include "keymile-common.h" - #define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE @@ -168,68 +165,6 @@ #define HWCONFIG_BUFFER_SIZE 256 -/* - * Environment - */ - -#define CONFIG_ENV_TOTAL_SIZE 0x40000 -#define ENV_DEL_ADDR CONFIG_ENV_ADDR_REDUND /* direct for newenv */ - -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV -#endif - -#ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU -#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" -#endif - -#define CONFIG_KM_DEF_ENV_CPU \ - "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ - "cramfsloadfdt=" \ - "cramfsload ${fdt_addr_r} " \ - "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize} && " \ - "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize} && " \ - "cp.b ${load_addr_r} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ - "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize}\0" \ - "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \ - " +${filesize} && " \ - "erase " __stringify(CFG_SYS_FLASH_BASE) \ - " +${filesize} && " \ - "cp.b ${load_addr_r} " \ - __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \ - "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \ - "set_fdthigh=true\0" \ - "checkfdt=true\0" \ - "" - -#define CONFIG_KM_NEW_ENV \ - "newenv=protect off " __stringify(ENV_DEL_ADDR) \ - " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ - "erase " __stringify(ENV_DEL_ADDR) \ - " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ - "protect on " __stringify(ENV_DEL_ADDR) \ - " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0" - -#define CONFIG_HW_ENV_SETTINGS \ - "hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi," \ - "can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6," \ - "asrc,spdif,lpuart1,ftm1\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_NEW_ENV \ - CONFIG_KM_DEF_ENV \ - CONFIG_HW_ENV_SETTINGS \ - "EEprom_ivm=pca9547:70:9\0" \ - "ethrotate=no\0" \ - "" - #define CFG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ #endif diff --git a/include/configs/pg-wcom-expu1.h b/include/configs/pg-wcom-expu1.h index 1b72739d143..2c38cffa8a0 100644 --- a/include/configs/pg-wcom-expu1.h +++ b/include/configs/pg-wcom-expu1.h @@ -7,10 +7,6 @@ #define __CONFIG_PG_WCOM_EXPU1_H #define WCOM_EXPU1 -#define CONFIG_HOSTNAME "EXPU1" - -#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" -#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" /* CLIPS FPGA Definitions */ #define CFG_SYS_CSPR3_EXT (0x00) diff --git a/include/configs/pg-wcom-seli8.h b/include/configs/pg-wcom-seli8.h index e4bcae5bb5e..9474d3bd7bd 100644 --- a/include/configs/pg-wcom-seli8.h +++ b/include/configs/pg-wcom-seli8.h @@ -6,11 +6,6 @@ #ifndef __CONFIG_PG_WCOM_SELI8_H #define __CONFIG_PG_WCOM_SELI8_H -#define CONFIG_HOSTNAME "SELI8" - -#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" -#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" - /* PAXK FPGA Definitions */ #define CFG_SYS_CSPR3_EXT (0x00) #define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \ diff --git a/include/environment/pg-wcom/common.env b/include/environment/pg-wcom/common.env new file mode 100644 index 00000000000..4b660cebd67 --- /dev/null +++ b/include/environment/pg-wcom/common.env @@ -0,0 +1,68 @@ + +#ifndef WCOM_UBI_PARTITION_APP +/* one flash chip only called boot */ +# define WCOM_UBI_LINUX_MTD ubi.mtd=ubi0 +ubiattach=ubi part ubi0 +#else /* WCOM_UBI_PARTITION_APP */ +/* two flash chips called boot and app */ +# define WCOM_UBI_LINUX_MTD ubi.mtd=ubi0 ubi.mtd=ubi1 +ubiattach=if test ${boot_bank} -eq 0; + then; + ubi part ubi0; + else; + ubi part ubi1; + fi +#endif /* WCOMC_UBI_PARTITION_APP */ + +actual_bank=0 + +add_default=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off: + console=ttyS0,${baudrate} mem=${kernelmem} init=${init} + phram.phram=phvar,${varaddr},CONFIG_KM_PHRAM + WCOM_UBI_LINUX_MTD + +addpanic=setenv bootargs ${bootargs} panic=1 panic_on_oops=1 +altbootcmd=run bootcmd +backup_bank=0 +boot=bootm ${load_addr_r} - ${fdt_addr_r} + +bootcmd=km_checkbidhwk && + setenv bootcmd 'if km_checktestboot; + then; + setenv boot_bank ${test_bank}; + else; + setenv boot_bank ${actual_bank}; + fi; + run ${subbootcmds}; reset' && + setenv altbootcmd 'setenv boot_bank ${backup_bank}; + run ${subbootcmds}; + reset' && + saveenv && + saveenv && + boot + +cramfsaddr=CONFIG_KM_CRAMFS_ADDR +cramfsloadfdt=cramfsload ${fdt_addr_r} fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb +cramfsloadkernel=cramfsload ${load_addr_r} ${uimage} + +develop=tftp ${load_addr_r} scripts/develop-${arch}.txt && + env import -t ${load_addr_r} ${filesize} && + run setup_debug_env + +env_version=1 +fdt_addr_r=CONFIG_KM_FDT_ADDR +flashargs=setenv bootargs root=mtdblock:rootfs${boot_bank} rootfstype=squashfs ro +init=/sbin/init-overlay.sh +load=tftpboot ${load_addr_r} ${hostname}/u-boot.bin +load_addr_r=CONFIG_KM_KERNEL_ADDR +pnvramsize=CONFIG_KM_PNVRAM + +ramfs=tftp ${load_addr_r} scripts/ramfs-${arch}.txt && + env import -t ${load_addr_r} ${filesize} && + run setup_debug_env + +release=run newenv; reset +subbootcmds=ubiattach ubicopy checkfdt cramfsloadfdt set_fdthigh + cramfsloadkernel flashargs add_default addpanic boot +testbootcmd=setenv boot_bank ${test_bank}; run ${subbootcmds}; reset +ubicopy=ubi read ${cramfsaddr} bootfs${boot_bank} diff --git a/include/environment/pg-wcom/ls102xa.env b/include/environment/pg-wcom/ls102xa.env new file mode 100644 index 00000000000..5b5bda95e28 --- /dev/null +++ b/include/environment/pg-wcom/ls102xa.env @@ -0,0 +1,29 @@ +#define WCOM_UBI_PARTITION_APP + +#include + +EEprom_ivm=pca9547:70:9 +boot=bootm $load_addr_r - $fdt_addr_r +checkfdt=true +cramfsloadfdt=cramfsload $fdt_addr_r fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb +ethrotate=no +hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi,can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6,asrc,spdif,lpuart1,ftm1 +netdev=eth2 + +newenv=protect off CONFIG_ENV_ADDR_REDUND +0x40000 && + erase CONFIG_ENV_ADDR_REDUND +0x40000 && + protect on CONFIG_ENV_ADDR_REDUND +0x40000 + +set_fdthigh=true + +update=protect off CONFIG_SYS_MONITOR_BASE +${filesize} && + erase CONFIG_SYS_MONITOR_BASE +${filesize} && + cp.b ${load_addr_r} CONFIG_SYS_MONITOR_BASE ${filesize} && + protect on CONFIG_SYS_MONITOR_BASE +${filesize} + +update-nor=protect off CONFIG_SYS_FLASH_BASE +${filesize} && + erase CONFIG_SYS_FLASH_BASE +${filesize} && + cp.b ${load_addr_r} CONFIG_SYS_FLASH_BASE ${filesize} && + protect on CONFIG_SYS_MONITOR_BASE +0x100000 + +uimage=uImage -- cgit v1.3.1 From 0cc0c098c8fbbf61378081df9681e660829c48eb Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Dec 2022 18:22:38 +0100 Subject: km/powerpc: migrate to env.txt file Use already present common.env file and add a powerpc specific env so that we can move all the environment defines to text files. Signed-off-by: Holger Brunck --- board/keymile/km83xx/km83xx.env | 21 +++++++++++++++ configs/kmcoge5ne_defconfig | 2 +- configs/kmeter1_defconfig | 2 +- configs/kmopti2_defconfig | 1 + configs/kmsupx5_defconfig | 1 + configs/kmtepr2_defconfig | 1 + configs/tuge1_defconfig | 1 + configs/tuxx1_defconfig | 1 + include/configs/km/km-mpc83xx.h | 24 ----------------- include/configs/km/km-powerpc.h | 46 --------------------------------- include/configs/kmcoge5ne.h | 6 ----- include/configs/kmeter1.h | 4 --- include/configs/kmopti2.h | 7 ----- include/configs/kmsupx5.h | 7 ----- include/configs/kmtepr2.h | 7 ----- include/configs/tuge1.h | 7 ----- include/configs/tuxx1.h | 7 ----- include/environment/pg-wcom/powerpc.env | 14 ++++++++++ 18 files changed, 42 insertions(+), 117 deletions(-) create mode 100644 board/keymile/km83xx/km83xx.env delete mode 100644 include/configs/km/km-powerpc.h create mode 100644 include/environment/pg-wcom/powerpc.env (limited to 'include') diff --git a/board/keymile/km83xx/km83xx.env b/board/keymile/km83xx/km83xx.env new file mode 100644 index 00000000000..ed2487c028d --- /dev/null +++ b/board/keymile/km83xx/km83xx.env @@ -0,0 +1,21 @@ +#if CONFIG_TARGET_KMCOGE5NE +#define WCOM_UBI_PARTITION_APP +hostname=kmcoge5ne +netdev=eth1 +uimage=ecc_bch_uImage +#elif CONFIG_TARGET_KMETER1 +hostname=kmeter1 +netdev=eth2 +uimage=uImage +#else +hostname=kmeter1 +netdev=eth0 +uimage=uImage +#endif + +#include +#include + +#if CONFIG_TARGET_KMCOGE5NE +add_default+= eccmode=bch +#endif diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 013277c9bf1..6bfcee9ed2f 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -159,7 +159,6 @@ CONFIG_LCRR_DBYP_PLL_BYPASSED=y CONFIG_LCRR_EADC_2=y CONFIG_LCRR_CLKDIV_4=y CONFIG_83XX_PCICLK=0x3ef1480 -CONFIG_KM_DEF_NETDEV="eth1" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -197,6 +196,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot,nand0=app" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);app:-(ubi1);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set +CONFIG_ENV_SOURCE_FILE="km83xx" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 66ec936cce4..b0af9e051bb 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -129,7 +129,6 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_DBYP_PLL_BYPASSED=y CONFIG_LCRR_EADC_2=y CONFIG_LCRR_CLKDIV_4=y -CONFIG_KM_DEF_NETDEV="eth2" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -166,6 +165,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set +CONFIG_ENV_SOURCE_FILE="km83xx" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 3ba334c2401..9a1e7cbde30 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -178,6 +178,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set +CONFIG_ENV_SOURCE_FILE="km83xx" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 4a02e5e88fc..d981e512239 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -157,6 +157,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set +CONFIG_ENV_SOURCE_FILE="km83xx" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 55158864ea3..18a464c0aeb 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -177,6 +177,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set +CONFIG_ENV_SOURCE_FILE="km83xx" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 894a79df59e..dbd832c9b76 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -157,6 +157,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set +CONFIG_ENV_SOURCE_FILE="km83xx" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 6e66e6ce305..1b034a21a72 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -179,6 +179,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set +CONFIG_ENV_SOURCE_FILE="km83xx" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 840a4d5401f..7f1839f463d 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -67,30 +67,6 @@ */ #define CFG_SYS_BOOTMAPSZ (8 << 20) -/* - * Environment - */ - -/* - * Environment Configuration - */ -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off " __stringify(CONFIG_ENV_ADDR) " +0x40000 && " \ - "era " __stringify(CONFIG_ENV_ADDR) " +0x40000\0" \ - "unlock=yes\0" \ - "" - /* * QE UEC ethernet configuration */ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h deleted file mode 100644 index 424caa0df97..00000000000 --- a/include/configs/km/km-powerpc.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ - -#ifndef __CONFIG_KEYMILE_POWERPC_H -#define __CONFIG_KEYMILE_POWERPC_H - -/* Do boardspecific init for all boards */ - -/* Increase max size of compressed kernel */ - -/****************************************************************************** - * (PRAM usage) - * ... ------------------------------------------------------- - * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM - * ... |<------------------- pram -------------------------->| - * ... ------------------------------------------------------- - * @END_OF_RAM: - * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose - * @CONFIG_KM_PHRAM: address for /var - * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) - */ - -/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable - * is not valid yet, which is the case for when u-boot copies itself to RAM */ -#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) - -/* architecture specific default bootargs */ -#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" - -#define CONFIG_KM_DEF_ENV_CPU \ - "u-boot="CONFIG_HOSTNAME "/u-boot.bin\0" \ - "update=" \ - "protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\ - "erase " __stringify(BOOTFLASH_START) " +${filesize} && "\ - "cp.b ${load_addr_r} " __stringify(BOOTFLASH_START) \ - " ${filesize} && " \ - "protect on " __stringify(BOOTFLASH_START) " +${filesize}\0"\ - "set_fdthigh=true\0" \ - "checkfdt=true\0" \ - "bootm_mapsize=" __stringify(CONFIG_SYS_BOOTM_LEN) "\0" \ - "" - -#endif /* __CONFIG_KEYMILE_POWERPC_H */ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 6b30fb4b617..e0f94aead79 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -8,16 +8,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_HOSTNAME "kmcoge5ne" #define NAND_MAX_CHIPS 1 #define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ -#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" -#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" - /* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" #include "km/km-mpc83xx.h" #include "km/km-mpc8360.h" diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 910fc1b2cb2..6f67e5a98ab 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -8,11 +8,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_HOSTNAME "kmeter1" - /* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" #include "km/km-mpc83xx.h" #include "km/km-mpc8360.h" diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 5050c703039..d6a3844bcc5 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -20,14 +20,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_HOSTNAME "kmopti2" - /* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" #include "km/km-mpc83xx.h" #include "km/km-mpc832x.h" diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index e3de6c61e71..d6a3844bcc5 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -20,14 +20,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_HOSTNAME "kmsupx5" - /* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" #include "km/km-mpc83xx.h" #include "km/km-mpc832x.h" diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index a4ceb1c50d6..d6a3844bcc5 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -20,14 +20,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_HOSTNAME "kmtepr2" - /* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" #include "km/km-mpc83xx.h" #include "km/km-mpc832x.h" diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index d43ccbe8dd9..d6a3844bcc5 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -20,14 +20,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_HOSTNAME "tuge1" - /* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" #include "km/km-mpc83xx.h" #include "km/km-mpc832x.h" diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 7eed31c35f0..d6a3844bcc5 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -20,14 +20,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_HOSTNAME "tuxx1" - /* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" #include "km/km-mpc83xx.h" #include "km/km-mpc832x.h" diff --git a/include/environment/pg-wcom/powerpc.env b/include/environment/pg-wcom/powerpc.env new file mode 100644 index 00000000000..a57fd93092d --- /dev/null +++ b/include/environment/pg-wcom/powerpc.env @@ -0,0 +1,14 @@ +arch=ppc_82xx +bootm_mapsize=CONFIG_SYS_BOOTM_LEN +checkfdt=true +set_fdthigh=true + +update=protect off BOOTFLASH_START +${filesize} && + erase BOOTFLASH_START +${filesize} && + cp.b ${load_addr_r} BOOTFLASH_START ${filesize} && + protect on BOOTFLASH_START +${filesize} + +newenv=prot off CONFIG_ENV_ADDR +0x40000 && + era CONFIG_ENV_ADDR +0x40000 + +unlock=yes -- cgit v1.3.1 From 6f7c936fbdd40071716730d07083c7f596700478 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Dec 2022 18:22:39 +0100 Subject: board/km/cent2: migrate to environment text file Use like the other boards a text file for the environment. As this is the last user of keymile-common.h we can now remove this file completely. Signed-off-by: Holger Brunck --- board/keymile/Kconfig | 12 --- board/keymile/kmcent2/kmcent2.c | 2 +- board/keymile/kmcent2/kmcent2.env | 37 ++++++++ configs/kmcent2_defconfig | 2 +- include/configs/km/keymile-common.h | 174 ------------------------------------ include/configs/kmcent2.h | 74 --------------- scripts/config_whitelist.txt | 15 ---- 7 files changed, 39 insertions(+), 277 deletions(-) create mode 100644 board/keymile/kmcent2/kmcent2.env delete mode 100644 include/configs/km/keymile-common.h (limited to 'include') diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index b8f0578a286..46d08971087 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -77,18 +77,6 @@ config SYS_CLIPS_BASE help IFC Base Address for CLIPS FPGA. -config KM_CONSOLE_TTY - string "KM Console" - default "ttyS0" - help - TTY console to use on board. - -config KM_DEF_NETDEV - string "Default Netdevice" - default "eth0" - help - Default netdevice for debug interface - config KM_COMMON_ETH_INIT bool "Common Ethernet Initialization" default y if ARCH_KIRKWOOD || MPC83xx diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c index 9f68c215f38..ed552c57b5f 100644 --- a/board/keymile/kmcent2/kmcent2.c +++ b/board/keymile/kmcent2/kmcent2.c @@ -34,7 +34,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; int checkboard(void) { - printf("Board: Hitachi Power Grids %s\n", KM_BOARD_NAME); + printf("Board: Hitachi Power Grids kmcent2\n"); return 0; } diff --git a/board/keymile/kmcent2/kmcent2.env b/board/keymile/kmcent2/kmcent2.env new file mode 100644 index 00000000000..7c8f8306c54 --- /dev/null +++ b/board/keymile/kmcent2/kmcent2.env @@ -0,0 +1,37 @@ +#include + +EEprom_ivm=pca9547:70:9 +arch=ppc_82xx +boot=bootm ${load_addr_r} - ${fdt_addr_r} +checkfdt=true +cramfsloadfdt=cramfsload ${fdt_addr_r} fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb +fpgacfg=true +hostname=kmcent2 +hwconfig=fsl_ddr:ctlr_intlv=cacheline +netdev=eth2 + +newenv=protect off ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE && + erase ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE && + protect on ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE + +set_fdthigh=true +uimage=uImage + +update=protect off CONFIG_SYS_MONITOR_BASE +${filesize} && + erase CONFIG_SYS_MONITOR_BASE +${filesize} && + cp.b ${load_addr_r} CONFIG_SYS_MONITOR_BASE ${filesize} && + protect on CONFIG_SYS_MONITOR_BASE +${filesize} + update-nor=protect off CONFIG_SYS_FLASH_BASE +${filesize} && + erase CONFIG_SYS_FLASH_BASE +${filesize} && + cp.b ${load_addr_r} CONFIG_SYS_FLASH_BASE ${filesize} && + protect on CONFIG_SYS_MONITOR_BASE +CONFIG_SYS_MONITOR_LEN + +usb_phy_type=utmi +usb_dr_mode=host + +/* + * The Linux fsl_fman driver needs to be able to process frames with more + * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot + * parameters + */ +add_default+= fsl_dpaa_fman.fsl_fm_max_frm=1558 diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index 41b26287d56..2abda788939 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -17,7 +17,6 @@ CONFIG_SYS_CACHE_STASHING=y # CONFIG_DEEP_SLEEP is not set CONFIG_PCIE1=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 -CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_IVM_BUS=2 CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y @@ -54,6 +53,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:128k(RCW),128k(fman),128k(QE),12 CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_OF_CONTROL=y +CONFIG_ENV_SOURCE_FILE="kmcent2" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h deleted file mode 100644 index cc5ec219b8d..00000000000 --- a/include/configs/km/keymile-common.h +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008-2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ - -#ifndef __CONFIG_KEYMILE_H -#define __CONFIG_KEYMILE_H - -#include - -/* - * Miscellaneous configurable options - */ - -#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS -#define CONFIG_KM_DEF_ENV_BOOTPARAMS \ - "actual_bank=0\0" -#endif - -#ifndef CONFIG_KM_UBI_PARTITION_NAME_BOOT -#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" -#endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */ - -#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS -#define CONFIG_KM_UBI_PART_BOOT_OPTS "" -#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */ - -#ifndef CONFIG_KM_UBI_PARTITION_NAME_APP -/* one flash chip only called boot */ -/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ -# define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ - CONFIG_KM_UBI_PART_BOOT_OPTS -# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ - "ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0" -#else /* CONFIG_KM_UBI_PARTITION_NAME_APP */ -/* two flash chips called boot and app */ -/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ -/* app: CONFIG_KM_UBI_PARTITION_NAME_APP */ -# define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ - CONFIG_KM_UBI_PART_BOOT_OPTS " " \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP -# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ - "ubiattach=if test ${boot_bank} -eq 0; then; " \ - "ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "; else; " \ - "ubi part " CONFIG_KM_UBI_PARTITION_NAME_APP "; fi\0" -#endif /* CONFIG_KM_UBI_PARTITION_NAME_APP */ - -#ifdef CONFIG_NAND_ECC_BCH -#define CONFIG_KM_UIMAGE_NAME "ecc_bch_uImage\0" -#define CONFIG_KM_ECC_MODE " eccmode=bch" -#else -#define CONFIG_KM_UIMAGE_NAME "uImage\0" -#define CONFIG_KM_ECC_MODE -#endif - -/* - * boottargets - * - set 'subbootcmds' - * - set 'bootcmd' and 'altbootcmd' - * available targets: - * - 'release': for a standalone system kernel/rootfs from flash - */ -#define CONFIG_KM_DEF_ENV_BOOTTARGETS \ - "subbootcmds=ubiattach ubicopy checkfdt cramfsloadfdt " \ - "set_fdthigh cramfsloadkernel flashargs add_default " \ - "addpanic boot\0" \ - "develop=" \ - "tftp ${load_addr_r} scripts/develop-${arch}.txt && " \ - "env import -t ${load_addr_r} ${filesize} && " \ - "run setup_debug_env\0" \ - "ramfs=" \ - "tftp ${load_addr_r} scripts/ramfs-${arch}.txt && " \ - "env import -t ${load_addr_r} ${filesize} && " \ - "run setup_debug_env\0" \ - "" - -/* - * bootargs - * - modify 'bootargs' - * - * - 'add_default': default bootargs common for all arm/ppc boards - * - 'addpanic': add kernel panic options - * - 'flashargs': defaults arguments for flash base boot - * - */ -#define CONFIG_KM_DEF_ENV_BOOTARGS \ - "add_default=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off:" \ - " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}" \ - " mem=${kernelmem} init=${init}" \ - CONFIG_KM_ECC_MODE \ - " phram.phram=phvar,${varaddr}," __stringify(CONFIG_KM_PHRAM)\ - " " CONFIG_KM_UBI_LINUX_MTD " " \ - CONFIG_KM_DEF_BOOT_ARGS_CPU \ - "\0" \ - "addpanic=" \ - "setenv bootargs ${bootargs} panic=1 panic_on_oops=1\0" \ - "flashargs=" \ - "setenv bootargs " \ - "root=mtdblock:rootfs${boot_bank} " \ - "rootfstype=squashfs ro\0" \ - "" - -/* - * flash_boot - * - commands for booting from flash - * - * - 'cramfsloadkernel': copy kernel from a cramfs to ram - * - 'ubiattach': attach ubi partition - * - 'ubicopy': copy ubi volume to ram - * - volume names: bootfs0, bootfs1, bootfs2, ... - * - * processor specific settings - * - 'cramfsloadfdt': copy fdt from a cramfs to ram - */ -#define CONFIG_KM_DEF_ENV_FLASH_BOOT \ - "cramfsaddr=" __stringify(CONFIG_KM_CRAMFS_ADDR) "\0" \ - "cramfsloadkernel=cramfsload ${load_addr_r} ${uimage}\0" \ - "ubicopy=ubi read ${cramfsaddr} bootfs${boot_bank}\0" \ - "uimage=" CONFIG_KM_UIMAGE_NAME \ - CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI - -/* - * constants - * - KM specific constants and commands - * - * - 'default': setup default environment - */ -#define CONFIG_KM_DEF_ENV_CONSTANTS \ - "backup_bank=0\0" \ - "release=run newenv; reset\0" \ - "pnvramsize=" __stringify(CONFIG_KM_PNVRAM) "\0" \ - "testbootcmd=setenv boot_bank ${test_bank}; " \ - "run ${subbootcmds}; reset\0" \ - "env_version=1\0" \ - "" - -#ifndef CONFIG_KM_DEF_ENV -#define CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ENV_BOOTPARAMS \ - "netdev=" __stringify(CONFIG_KM_DEF_NETDEV) "\0" \ - CONFIG_KM_DEF_ENV_CPU \ - CONFIG_KM_DEF_ENV_BOOTTARGETS \ - CONFIG_KM_DEF_ENV_BOOTARGS \ - CONFIG_KM_DEF_ENV_FLASH_BOOT \ - CONFIG_KM_DEF_ENV_CONSTANTS \ - "altbootcmd=run bootcmd\0" \ - "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ - "bootcmd=km_checkbidhwk && " \ - "setenv bootcmd \'if km_checktestboot; then; " \ - "setenv boot_bank ${test_bank}; else; " \ - "setenv boot_bank ${actual_bank}; fi;" \ - "run ${subbootcmds}; reset\' && " \ - "setenv altbootcmd \'setenv boot_bank ${backup_bank}; " \ - "run ${subbootcmds}; reset\' && " \ - "saveenv && saveenv && boot\0" \ - "cramfsloadfdt=" \ - "cramfsload ${fdt_addr_r} " \ - "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ - "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ - "init=/sbin/init-overlay.sh\0" \ - "load_addr_r=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ - "load=tftpboot ${load_addr_r} ${u-boot}\0" \ - "" -#endif /* CONFIG_KM_DEF_ENV */ - -#endif /* __CONFIG_KEYMILE_H */ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 527f0383bc6..532370e9184 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -8,18 +8,6 @@ #ifndef __KMCENT2_H #define __KMCENT2_H -#define CONFIG_HOSTNAME "kmcent2" -#define KM_BOARD_NAME CONFIG_HOSTNAME - -/* - * The Linux fsl_fman driver needs to be able to process frames with more - * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot - * parameters - */ -#define CONFIG_KM_DEF_BOOT_ARGS_CPU "fsl_dpaa_fman.fsl_fm_max_frm=1558" - -#include "km/keymile-common.h" - /* Application IFC chip selects */ #define SYS_LAWAPP_BASE 0xc0000000 #define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE) @@ -387,66 +375,4 @@ int get_scl(void); */ #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -/* - * Environment Configuration - */ -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV -#endif - -#define __USB_PHY_TYPE utmi - -#define CONFIG_KM_DEF_ENV_CPU \ - "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ - "cramfsloadfdt=" \ - "cramfsload ${fdt_addr_r} " \ - "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize} && " \ - "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize} && " \ - "cp.b ${load_addr_r} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ - "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize}\0" \ - "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \ - " +${filesize} && " \ - "erase " __stringify(CFG_SYS_FLASH_BASE) \ - " +${filesize} && " \ - "cp.b ${load_addr_r} " \ - __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \ - "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \ - "set_fdthigh=true\0" \ - "checkfdt=true\0" \ - "fpgacfg=true\0" \ - "" - -#define CONFIG_HW_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ - "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ - "usb_dr_mode=host\0" - -#define CONFIG_KM_NEW_ENV \ - "newenv=protect off " __stringify(ENV_DEL_ADDR) \ - " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ - "erase " __stringify(ENV_DEL_ADDR) \ - " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ - "protect on " __stringify(ENV_DEL_ADDR) \ - " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0" - -/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - CONFIG_KM_NEW_ENV \ - CONFIG_HW_ENV_SETTINGS \ - "EEprom_ivm=pca9547:70:9\0" \ - "" - #endif /* __KMCENT2_H */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 12c23a5dfdf..f829a7927db 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -70,23 +70,8 @@ CONFIG_IRAM_BASE CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_IRAM_TOP -CONFIG_KM_DEF_ARCH -CONFIG_KM_DEF_BOOT_ARGS_CPU -CONFIG_KM_DEF_ENV -CONFIG_KM_DEF_ENV_BOOTARGS -CONFIG_KM_DEF_ENV_BOOTPARAMS CONFIG_KM_DEF_ENV_BOOTTARGETS -CONFIG_KM_DEF_ENV_CONSTANTS -CONFIG_KM_DEF_ENV_CPU -CONFIG_KM_DEF_ENV_FLASH_BOOT -CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI -CONFIG_KM_ECC_MODE CONFIG_KM_NEW_ENV -CONFIG_KM_UBI_LINUX_MTD -CONFIG_KM_UBI_PARTITION_NAME_APP -CONFIG_KM_UBI_PARTITION_NAME_BOOT -CONFIG_KM_UBI_PART_BOOT_OPTS -CONFIG_KM_UIMAGE_NAME CONFIG_KSNET_CPSW_NUM_PORTS CONFIG_KSNET_MAC_ID_BASE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE -- cgit v1.3.1 From 3bcf9c08a3de030438fcb91b27bf38e3235aafc5 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Dec 2022 18:22:40 +0100 Subject: board/km/secu: migrate to use environment text files Instead of having these defines in a header file, move them to a simple text file. Signed-off-by: Holger Brunck --- board/keymile/secu1/socfpga_secu.env | 50 ++++++++++++++++++++++++++++++++ configs/socfpga_secu1_defconfig | 4 +-- include/configs/socfpga_arria5_secu1.h | 53 ---------------------------------- scripts/config_whitelist.txt | 2 -- 4 files changed, 52 insertions(+), 57 deletions(-) create mode 100644 board/keymile/secu1/socfpga_secu.env (limited to 'include') diff --git a/board/keymile/secu1/socfpga_secu.env b/board/keymile/secu1/socfpga_secu.env new file mode 100644 index 00000000000..147c4170ef5 --- /dev/null +++ b/board/keymile/secu1/socfpga_secu.env @@ -0,0 +1,50 @@ +altbootcmd=run bootcmd; +bootlimit=6 +bootnum=1 +bootretry=CONFIG_BOOT_RETRY_TIME + +develop=tftp 0x200000 scripts/develop-secu.txt && + env import -t 0x200000 ${filesize} && + saveenv && + reset + +fdt_addr=CONFIG_KM_FDT_ADDR +load=tftpboot ${loadaddr} u-boot-with-nand-spl.sfp +loadaddr=CONFIG_KM_KERNEL_ADDR +newenv=nand erase 0x100000 0x40000 +release=run newenv; reset +socfpga_legacy_reset_compat=1 +update=nand erase 0x0 0x00100000 && nand write ${loadaddr} 0x0 ${filesize} + +userload=ubi part nand.ubi && + ubi check rootfs$bootnum && + ubi read $fdt_addr dtb$bootnum && + ubi read $loadaddr kernel$bootnum + +userboot=setenv bootargs console=ttyS0,115200 ubi.fm_autoconvert=1 uio_pdrv_genirq.of_id="idq,regbank" + ubi.mtd=1 ubi.block=0,rootfs$bootnum root=/dev/ubiblock0_$ubivolid ro + rootfstype=squashfs init=sbin/preinit; + bootz ${loadaddr} - ${fdt_addr} + +verify=y + +/* + * FPGA Remote Update related environment + * + * Note that since those commands access the FPGA, the HPS-to-FPGA bridges + * MUST have been previously enabled (for example with 'bridge enable'). + */ +rmtu_page=0xFF29000C +rmtu_reconfig=0xFF290018 +fpga_safebase=0x0 +fpga_userbase=0x2000000 + +_fpga_loaduser=echo "Loading FPGA USER image..." && + mw ${rmtu_page} ${fpga_userbase} && + mw ${rmtu_reconfig} 1 + +_fpga_loadsafe=echo "Loading FPGA SAFE image..." && + mw ${rmtu_page} ${fpga_safebase} && + mw ${rmtu_reconfig} 1 + + diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index 7a805df5a34..6e4fe588a15 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -3,7 +3,7 @@ CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x800 -CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_secu1" @@ -24,7 +24,6 @@ CONFIG_BOOT_RETRY=y CONFIG_BOOT_RETRY_TIME=45 CONFIG_RESET_TO_RETRY=y CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 ubi.fm_autoconvert=1 uio_pdrv_genirq.of_id=\"idq,regbank\"" CONFIG_BOOTCOMMAND="setenv bootcmd 'bridge enable; if test ${bootnum} = 'b'; then run _fpga_loadsafe; else if test ${bootcount} -eq 4; then echo 'Switching copy...'; setexpr x $bootnum % 2 && setexpr bootnum $x + 1; saveenv; fi; run _fpga_loaduser; fi;echo 'Booting bank $bootnum' && run userload && run userboot;' && setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && saveenv && saveenv && boot;" CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_secu1.dtb" CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -65,6 +64,7 @@ CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set +CONFIG_ENV_SOURCE_FILE="socfpga_secu" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h index 29b4b22b398..55168c2fb8f 100644 --- a/include/configs/socfpga_arria5_secu1.h +++ b/include/configs/socfpga_arria5_secu1.h @@ -7,7 +7,6 @@ #define __CONFIG_SOCFPGA_SECU1_H__ #include -#include /* Eternal oscillator */ #define CFG_SYS_TIMER_RATE 40000000 @@ -23,58 +22,6 @@ */ #define CFG_SYS_I2C_RTC_ADDR 0x68 -/* Environment settings */ - -/* - * FPGA Remote Update related environment - * - * Note that since those commands access the FPGA, the HPS-to-FPGA - * bridges MUST have been previously enabled (for example - * with 'bridge enable'). - */ -#define FPGA_RMTU_ENV \ - "rmtu_page=0xFF29000C\0" \ - "rmtu_reconfig=0xFF290018\0" \ - "fpga_safebase=0x0\0" \ - "fpga_userbase=0x2000000\0" \ - "_fpga_loaduser=echo Loading FPGA USER image..." \ - " && mw ${rmtu_page} ${fpga_userbase} && mw ${rmtu_reconfig} 1\0" \ - "_fpga_loadsafe=echo Loading FPGA SAFE image..." \ - " && mw ${rmtu_page} ${fpga_safebase} && mw ${rmtu_reconfig} 1\0" \ - -#define CONFIG_KM_NEW_ENV \ - "newenv=" \ - "nand erase 0x100000 0x40000\0" - -#define CONFIG_KM_DEF_ENV_BOOTTARGETS \ - "release=" \ - "run newenv; reset\0" \ - "develop=" \ - "tftp 0x200000 scripts/develop-secu.txt && env import -t 0x200000 ${filesize} && saveenv && reset\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - FPGA_RMTU_ENV \ - CONFIG_KM_DEF_ENV_BOOTTARGETS \ - CONFIG_KM_NEW_ENV \ - "socfpga_legacy_reset_compat=1\0" \ - "altbootcmd=run bootcmd;\0" \ - "bootlimit=6\0" \ - "bootnum=1\0" \ - "bootretry=" __stringify(CONFIG_BOOT_RETRY_TIME) "\0" \ - "fdt_addr=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ - "load=tftpboot ${loadaddr} u-boot-with-nand-spl.sfp\0" \ - "loadaddr=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ - "update=nand erase 0x0 0x00100000 && nand write ${loadaddr} 0x0 ${filesize}\0" \ - "userload=ubi part nand.ubi &&" \ - "ubi check rootfs$bootnum &&" \ - "ubi read $fdt_addr dtb$bootnum &&" \ - "ubi read $loadaddr kernel$bootnum\0" \ - "userboot=setenv bootargs " CONFIG_BOOTARGS \ - " ubi.mtd=1 ubi.block=0,rootfs$bootnum root=/dev/ubiblock0_$ubivolid" \ - " ro rootfstype=squashfs init=sbin/preinit;" \ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "verify=y\0" - /* The rest of the configuration is shared */ #include diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index f829a7927db..a863665b2f7 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -70,8 +70,6 @@ CONFIG_IRAM_BASE CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_IRAM_TOP -CONFIG_KM_DEF_ENV_BOOTTARGETS -CONFIG_KM_NEW_ENV CONFIG_KSNET_CPSW_NUM_PORTS CONFIG_KSNET_MAC_ID_BASE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE -- cgit v1.3.1 From 31464f9455ca16b6dd98e5469213c33d78fc0137 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Dec 2022 18:22:42 +0100 Subject: km/ppc: migrate all mpc83xx to DM_I2C Enable DM_I2C and I2C mux to get rid of the usage of the legacy i2c driver. Signed-off-by: Holger Brunck --- board/keymile/Kconfig | 3 +- board/keymile/km83xx/Makefile | 2 +- board/keymile/km83xx/km83xx_i2c.c | 73 --------------------------------------- configs/kmcoge5ne_defconfig | 9 ++--- configs/kmeter1_defconfig | 9 ++--- configs/kmopti2_defconfig | 9 ++--- configs/kmsupx5_defconfig | 9 ++--- configs/kmtepr2_defconfig | 9 ++--- configs/tuge1_defconfig | 9 ++--- configs/tuxx1_defconfig | 9 ++--- include/configs/km/km-mpc83xx.h | 8 ----- 11 files changed, 23 insertions(+), 126 deletions(-) delete mode 100644 board/keymile/km83xx/km83xx_i2c.c (limited to 'include') diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index cd8a06e2780..e5d7c80a869 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -100,8 +100,7 @@ config KM_MVEXTSW_ADDR config KM_IVM_BUS int "IVM I2C Bus" default 0 if ARCH_SOCFPGA - default 1 if MPC85xx || ARCH_LS1021A - default 2 if MPC83xx + default 1 if PPC || ARCH_LS1021A help Identifier number of I2C bus, where the inventory EEPROM is connected to. diff --git a/board/keymile/km83xx/Makefile b/board/keymile/km83xx/Makefile index 0aef6549873..bdb358e2d27 100644 --- a/board/keymile/km83xx/Makefile +++ b/board/keymile/km83xx/Makefile @@ -3,4 +3,4 @@ # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-y += km83xx.o ../common/common.o ../common/ivm.o km83xx_i2c.o +obj-y += km83xx.o ../common/common.o ../common/ivm.o diff --git a/board/keymile/km83xx/km83xx_i2c.c b/board/keymile/km83xx/km83xx_i2c.c deleted file mode 100644 index b80672d1b43..00000000000 --- a/board/keymile/km83xx/km83xx_i2c.c +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com - */ - -#include -#include -#include -#include -#include -#include "../common/common.h" - -static void i2c_write_start_seq(void) -{ - struct fsl_i2c_base *base; - base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + - CONFIG_SYS_FSL_I2C_OFFSET); - udelay(DELAY_ABORT_SEQ); - out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA)); - udelay(DELAY_ABORT_SEQ); - out_8(&base->cr, (I2C_CR_MEN)); -} - -int i2c_make_abort(void) -{ - struct fsl_i2c_base *base; - base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + - CONFIG_SYS_FSL_I2C_OFFSET); - uchar last; - int nbr_read = 0; - int i = 0; - int ret = 0; - - /* wait after each operation to finsh with a delay */ - out_8(&base->cr, (I2C_CR_MSTA)); - udelay(DELAY_ABORT_SEQ); - out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA)); - udelay(DELAY_ABORT_SEQ); - in_8(&base->dr); - udelay(DELAY_ABORT_SEQ); - last = in_8(&base->dr); - nbr_read++; - - /* - * do read until the last bit is 1, but stop if the full eeprom is - * read. - */ - while (((last & 0x01) != 0x01) && - (nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) { - udelay(DELAY_ABORT_SEQ); - last = in_8(&base->dr); - nbr_read++; - } - if ((last & 0x01) != 0x01) - ret = -2; - if ((last != 0xff) || (nbr_read > 1)) - printf("[INFO] i2c abort after %d bytes (0x%02x)\n", - nbr_read, last); - udelay(DELAY_ABORT_SEQ); - out_8(&base->cr, (I2C_CR_MEN)); - udelay(DELAY_ABORT_SEQ); - /* clear status reg */ - out_8(&base->sr, 0); - - for (i = 0; i < 5; i++) - i2c_write_start_seq(); - if (ret != 0) - printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n", - nbr_read, last); - - return ret; -} diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 6bfcee9ed2f..9609f58fb4d 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -219,13 +219,10 @@ CONFIG_SYS_OR3_PRELIM=0xF0000E25 CONFIG_SYS_BR4_PRELIM_BOOL=y CONFIG_SYS_BR4_PRELIM=0xB0000801 CONFIG_SYS_OR4_PRELIM=0xF0000E25 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index b0af9e051bb..bd3d6315b1f 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -185,13 +185,10 @@ CONFIG_SYS_OR1_PRELIM=0xFC000E25 CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xA0000801 CONFIG_SYS_OR3_PRELIM=0xF0000E25 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 9a1e7cbde30..de6d99e91ec 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -200,13 +200,10 @@ CONFIG_SYS_OR2_PRELIM=0xF0000C25 CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xB0001001 CONFIG_SYS_OR3_PRELIM=0xF0000040 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index d981e512239..a231510a76f 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -177,13 +177,10 @@ CONFIG_SYS_OR1_PRELIM=0xF8000E25 CONFIG_SYS_BR2_PRELIM_BOOL=y CONFIG_SYS_BR2_PRELIM=0xA0000801 CONFIG_SYS_OR2_PRELIM=0xF0000C25 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 18a464c0aeb..e6beb62f862 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -199,13 +199,10 @@ CONFIG_SYS_OR2_PRELIM=0xF0000C25 CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xB0001001 CONFIG_SYS_OR3_PRELIM=0xF0000040 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index dbd832c9b76..83120759b15 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -177,13 +177,10 @@ CONFIG_SYS_OR1_PRELIM=0xF8000E25 CONFIG_SYS_BR2_PRELIM_BOOL=y CONFIG_SYS_BR2_PRELIM=0xA0000801 CONFIG_SYS_OR2_PRELIM=0xF0000C25 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 1b034a21a72..ee1640608d2 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -201,13 +201,10 @@ CONFIG_SYS_OR2_PRELIM=0xF0000C25 CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xB0000801 CONFIG_SYS_OR3_PRELIM=0xF0000E24 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 7f1839f463d..1f03f95acef 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -48,14 +48,6 @@ #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } -/* I2C */ -#define CFG_SYS_NUM_I2C_BUSES 4 -#define CFG_SYS_I2C_MAX_HOPS 1 -#define CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - #if defined(CONFIG_CMD_NAND) #define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE #endif -- cgit v1.3.1 From aeb13924f4579bd200d538fcb82628101822a833 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Dec 2022 18:22:43 +0100 Subject: km/mpc8360: remove unused CONFIG_SYS_PAXE defines These are unused defines and can be dropped. Signed-off-by: Holger Brunck --- include/configs/km/km-mpc8360.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'include') diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h index 5c9f912383d..04d3d352ee2 100644 --- a/include/configs/km/km-mpc8360.h +++ b/include/configs/km/km-mpc8360.h @@ -66,9 +66,3 @@ #define CFG_SYS_DDR_TIMING_3 0x00000000 -/* EEprom support */ - -/* - * PAXE on the local bus CS3 - */ -#define CFG_SYS_PAXE_BASE 0xA0000000 -- cgit v1.3.1 From f2d6c888f471837c565719097ca96f8f2b9dd215 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Fri, 25 Nov 2022 09:54:51 +0200 Subject: dt-bindings: mfd: add at91-usart.h from Linux Copy include file dt-bindings/mfd/at91-usart.h from Linux Signed-off-by: Eugen Hristev Reviewed-by: Claudiu Beznea --- include/dt-bindings/mfd/at91-usart.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 include/dt-bindings/mfd/at91-usart.h (limited to 'include') diff --git a/include/dt-bindings/mfd/at91-usart.h b/include/dt-bindings/mfd/at91-usart.h new file mode 100644 index 00000000000..2de5bc312e1 --- /dev/null +++ b/include/dt-bindings/mfd/at91-usart.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides macros for AT91 USART DT bindings. + * + * Copyright (C) 2018 Microchip Technology + * + * Author: Radu Pirea + * + */ + +#ifndef __DT_BINDINGS_AT91_USART_H__ +#define __DT_BINDINGS_AT91_USART_H__ + +#define AT91_USART_MODE_SERIAL 0 +#define AT91_USART_MODE_SPI 1 + +#endif /* __DT_BINDINGS_AT91_USART_H__ */ -- cgit v1.3.1 From 4475d017c57f93dca61c08563b3ff4202d38a127 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:12 -0500 Subject: arm: exynos5: Migrate USB_BOOTING to Kconfig This symbol is enabled for all exynos5 platforms, move to Kconfig and select it. Cc: Jaehoon Chung Cc: Minkyu Kang Signed-off-by: Tom Rini --- arch/arm/mach-exynos/Kconfig | 4 ++++ include/configs/exynos5-common.h | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 29e35e443c6..383af83066e 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -4,6 +4,9 @@ config BOARD_COMMON def_bool y depends on !TARGET_SMDKV310 && !TARGET_ARNDALE +config USB_BOOTING + bool + choice prompt "EXYNOS architecture type select" optional @@ -24,6 +27,7 @@ config ARCH_EXYNOS5 select BOARD_EARLY_INIT_F select CPU_V7A select SHA_HW_ACCEL + select USB_BOOTING imply CMD_HASH imply CRC32_VERIFY imply HASH_VERIFY diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index dd322c2b3a7..9b5c329bda1 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -58,7 +58,6 @@ /* USB */ /* USB boot mode */ -#define CONFIG_USB_BOOTING #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 -- cgit v1.3.1 From b41eb5a27e8cf6d32e68ea70ab0b5226329db154 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:13 -0500 Subject: p1_p2_rdb: Remove unused environment sections The CONFIG_USB_FAT_BOOT, CONFIG_USB_EXT2_BOOT and CONFIG_NORBOOT defines are not referenced anywhere, so remove them. Signed-off-by: Tom Rini --- include/configs/p1_p2_rdb_pc.h | 25 ------------------------- 1 file changed, 25 deletions(-) (limited to 'include') diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 49c5aef3059..f86b96b2141 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -441,29 +441,4 @@ RST_PCIE_CMD(pciboot) \ RST_DEF_CMD(defboot) \ "" -#define CONFIG_USB_FAT_BOOT \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs " \ -"ramdisk_size=$ramdisk_size;" \ -"usb start;" \ -"fatload usb 0:2 $loadaddr $bootfile;" \ -"fatload usb 0:2 $fdtaddr $fdtfile;" \ -"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ -"bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_USB_EXT2_BOOT \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs " \ -"ramdisk_size=$ramdisk_size;" \ -"usb start;" \ -"ext2load usb 0:4 $loadaddr $bootfile;" \ -"ext2load usb 0:4 $fdtaddr $fdtfile;" \ -"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ -"bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_NORBOOT \ -"setenv bootargs root=/dev/$jffs2nor rw " \ -"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ -"bootm $norbootaddr - $norfdtaddr" - #endif /* __CONFIG_H */ -- cgit v1.3.1 From 5732cf24ddfe010cd18de2233b9f175fa11f004f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:14 -0500 Subject: x530: Remove unused symbols The symbols CONFIG_UBI_PART and CONFIG_UBIFS_VOLUME are not referenced anywhere, drop them. Signed-off-by: Tom Rini --- include/configs/x530.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/x530.h b/include/configs/x530.h index c213dc6074b..4cf41f52fd7 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -51,7 +51,4 @@ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -#define CONFIG_UBI_PART user -#define CONFIG_UBIFS_VOLUME user - #endif /* _CONFIG_X530_H */ -- cgit v1.3.1 From 5125e136a9a667ace526fbb968500ff39011e6b4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:15 -0500 Subject: arm: trats2: Set mmcdev directly Only this platform sets mmcdev via CONFIG_MMC_DEFAULT_DEV so we hard-code that default directly. Signed-off-by: Tom Rini --- include/configs/exynos4-common.h | 3 --- include/configs/s5p_goni.h | 3 --- include/configs/trats2.h | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 81f450cde6c..bf965e5cedb 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -10,9 +10,6 @@ #include "exynos-common.h" -/* SD/MMC configuration */ -#define CONFIG_MMC_DEFAULT_DEV 0 - #define DFU_DEFAULT_POLL_TIMEOUT 300 /* USB Samsung's IDs */ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index fdade1ee66f..97f5dd0e473 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -119,9 +119,6 @@ #define PHYS_SDRAM_3 0x50000000 /* mDDR DMC2 Bank #2 */ #define PHYS_SDRAM_3_SIZE (128 << 20) /* 128 MB in Bank #2 */ -/* FLASH and environment organization */ -#define CONFIG_MMC_DEFAULT_DEV 0 - #define CFG_SYS_ONENAND_BASE 0xB0000000 #endif /* __CONFIG_H */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 0aa331e3935..4d39b4005bd 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -81,7 +81,7 @@ "${kernelname}\0" \ "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ "${fdtfile}\0" \ - "mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \ + "mmcdev=0\0" \ "mmcbootpart=2\0" \ "mmcrootpart=5\0" \ "opts=always_resume=1\0" \ -- cgit v1.3.1 From 2440b5bb523b004af43a1090e1a4134231702416 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:16 -0500 Subject: Convert CONFIG_HSMMC2_8BIT to Kconfig This converts the following to Kconfig: CONFIG_HSMMC2_8BIT Signed-off-by: Tom Rini --- configs/am335x_shc_defconfig | 1 + configs/am335x_shc_ict_defconfig | 1 + configs/am335x_shc_netboot_defconfig | 1 + configs/am335x_shc_sdboot_defconfig | 1 + configs/am57xx_evm_defconfig | 1 + configs/am57xx_hs_evm_defconfig | 1 + configs/am57xx_hs_evm_usb_defconfig | 1 + configs/cm_t43_defconfig | 1 + configs/dra7xx_evm_defconfig | 1 + configs/dra7xx_hs_evm_defconfig | 1 + configs/dra7xx_hs_evm_usb_defconfig | 1 + configs/omap5_uevm_defconfig | 1 + drivers/mmc/Kconfig | 5 +++++ include/configs/am335x_shc.h | 2 -- include/configs/am57xx_evm.h | 3 --- include/configs/cm_t43.h | 2 -- include/configs/dra7xx_evm.h | 3 --- include/configs/omap5_uevm.h | 3 --- 18 files changed, 17 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig index 9d81f8d0ad7..5a6db3ce6a4 100644 --- a/configs/am335x_shc_defconfig +++ b/configs/am335x_shc_defconfig @@ -72,6 +72,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_SLAVE=0x1 CONFIG_SYS_I2C_SPEED=400000 CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y CONFIG_MII=y diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig index de83139d151..aa55a7a61e5 100644 --- a/configs/am335x_shc_ict_defconfig +++ b/configs/am335x_shc_ict_defconfig @@ -70,6 +70,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_SLAVE=0x1 CONFIG_SYS_I2C_SPEED=400000 CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y CONFIG_MII=y diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig index e1dfd6a9bd1..cb73b104d23 100644 --- a/configs/am335x_shc_netboot_defconfig +++ b/configs/am335x_shc_netboot_defconfig @@ -73,6 +73,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_SLAVE=0x1 CONFIG_SYS_I2C_SPEED=400000 CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y CONFIG_MII=y diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig index 74f0834466d..f28e6e6b160 100644 --- a/configs/am335x_shc_sdboot_defconfig +++ b/configs/am335x_shc_sdboot_defconfig @@ -72,6 +72,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_SLAVE=0x1 CONFIG_SYS_I2C_SPEED=400000 CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y CONFIG_MII=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 054e9747a8b..03f799506e1 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -92,6 +92,7 @@ CONFIG_MISC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=76800000 diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 02a2543a3f0..86bcfe85ae3 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -89,6 +89,7 @@ CONFIG_MISC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=76800000 diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 84eca42aac0..eedbfd0d865 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -88,6 +88,7 @@ CONFIG_MISC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=76800000 diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 867ca303205..6eda33ebbc0 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -76,6 +76,7 @@ CONFIG_SYS_RX_ETH_BUFFER=64 CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_ONFI_DETECTION=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index d91cf3e1301..41df92f3d28 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -101,6 +101,7 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 195bc0e4ee0..7392b730853 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -96,6 +96,7 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_ONFI_DETECTION=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 99cdbbc02f8..1bda6db7a36 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -92,6 +92,7 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=76800000 diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index 91878c11ed4..9d5c515a44c 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -52,6 +52,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_PALMAS_POWER=y CONFIG_SCSI=y CONFIG_SCSI_AHCI_PLAT=y diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index bf4d994ff69..698c91c57f4 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -385,6 +385,11 @@ config MMC_OMAP36XX_PINS If unsure, say N. +config HSMMC2_8BIT + bool "Enable 8-bit interface for eMMC (interface #2)" + depends on MMC_OMAP_HS && (OMAP44XX || OMAP54XX || DRA7XX || AM33XX || \ + AM43XX || ARCH_KEYSTONE) + config SH_SDHI bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support" depends on ARCH_RMOBILE diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 452887d6995..70645edcb14 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -20,8 +20,6 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#define CONFIG_HSMMC2_8BIT - #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index dacfd41cced..ba91f2b0545 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -35,9 +35,6 @@ #include -/* Enhance our eMMC support / experience. */ -#define CONFIG_HSMMC2_8BIT - /* CPSW Ethernet */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index fcc17fc6b7c..8a18d6f97ab 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -36,8 +36,6 @@ * we don't need to do it twice. */ -#define CONFIG_HSMMC2_8BIT - #include #define V_OSCK 24000000 /* Clock output from T2 */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index ac3fcacc68e..b8f518612ee 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -48,9 +48,6 @@ #include -/* Enhance our eMMC support / experience. */ -#define CONFIG_HSMMC2_8BIT - /* * Default to using SPI for environment, etc. * 0x000000 - 0x040000 : QSPI.SPL (256KiB) diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index d7fa2d43914..39d0b403139 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -32,9 +32,6 @@ /* MMC ENV related defines */ -/* Enhance our eMMC support / experience. */ -#define CONFIG_HSMMC2_8BIT - /* Required support for the TCA642X GPIO we have on the uEVM */ #define CFG_SYS_I2C_TCA642X_BUS_NUM 4 #define CFG_SYS_I2C_TCA642X_ADDR 0x22 -- cgit v1.3.1 From 6bd2372094ab4827547ec0d3e5a258b72810cafd Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:17 -0500 Subject: env: Rework ENV_IS_EMBEDDED and related logic slightly - Drop CONFIG_BUILD_ENVCRC as this is never set directly but instead means ENV_IS_EMBEDDED, so reference that in code and rename the Makefile usage to BUILD_ENVCRC. - Remove extra-$(CONFIG_ENV_IS_EMBEDDED) line as it could never be true, and likely why there is an extra- line for CONFIG_ENV_IS_IN_FLASH (the only use case today of embedded environments). - With these slight changes we can then see that using the calculated symbol of ENV_IS_EMBEDDED is the right thing to use in any code which needs to know this situation and can remove CONFIG_ENV_IS_EMBEDDED entirely. Signed-off-by: Tom Rini --- README | 5 ----- env/Makefile | 1 - env/embedded.c | 2 +- include/env_internal.h | 23 +---------------------- tools/Makefile | 5 ++--- tools/envcrc.c | 10 +++------- 6 files changed, 7 insertions(+), 39 deletions(-) (limited to 'include') diff --git a/README b/README index 103562bbbe8..3fef1d2afa0 100644 --- a/README +++ b/README @@ -1542,11 +1542,6 @@ The following definitions that deal with the placement and management of environment data (variable area); in general, we support the following configurations: -- CONFIG_BUILD_ENVCRC: - - Builds up envcrc with the target environment so that external utils - may easily extract it and embed it in final U-Boot images. - BE CAREFUL! The first access to the environment happens quite early in U-Boot initialization (when we try to get the setting of for the console baudrate). You *MUST* have mapped your NVRAM area then, or diff --git a/env/Makefile b/env/Makefile index c4ad6543286..bb6e24b396d 100644 --- a/env/Makefile +++ b/env/Makefile @@ -11,7 +11,6 @@ obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += flags.o ifndef CONFIG_SPL_BUILD obj-y += callback.o obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o -extra-$(CONFIG_ENV_IS_EMBEDDED) += embedded.o obj-$(CONFIG_ENV_IS_IN_EEPROM) += embedded.o extra-$(CONFIG_ENV_IS_IN_FLASH) += embedded.o obj-$(CONFIG_ENV_IS_IN_NVRAM) += embedded.o diff --git a/env/embedded.c b/env/embedded.c index 27fb45bf8c3..7cbe54c56e0 100644 --- a/env/embedded.c +++ b/env/embedded.c @@ -27,7 +27,7 @@ * Generate embedded environment table * inside U-Boot image, if needed. */ -#if defined(ENV_IS_EMBEDDED) || defined(CONFIG_BUILD_ENVCRC) +#if defined(ENV_IS_EMBEDDED) /* * Put the environment in the .text section when we are building * U-Boot proper. The host based program "tools/envcrc" does not need diff --git a/include/env_internal.h b/include/env_internal.h index f30fd6159d8..aee6b3e48fa 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -41,10 +41,6 @@ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) # define ENV_IS_EMBEDDED # endif -# ifdef CONFIG_ENV_IS_EMBEDDED -# error "do not define CONFIG_ENV_IS_EMBEDDED in your board config" -# error "it is calculated automatically for you" -# endif #endif /* CONFIG_ENV_IS_IN_FLASH */ #if defined(CONFIG_ENV_IS_IN_NAND) @@ -57,23 +53,6 @@ extern unsigned long nand_env_oob_offset; # endif /* CONFIG_ENV_OFFSET_OOB */ #endif /* CONFIG_ENV_IS_IN_NAND */ -/* - * For the flash types where embedded env is supported, but it cannot be - * calculated automatically (i.e. NAND), take the board opt-in. - */ -#if defined(CONFIG_ENV_IS_EMBEDDED) && !defined(ENV_IS_EMBEDDED) -# define ENV_IS_EMBEDDED -#endif - -/* The build system likes to know if the env is embedded */ -#ifdef DO_DEPS_ONLY -# ifdef ENV_IS_EMBEDDED -# ifndef CONFIG_ENV_IS_EMBEDDED -# define CONFIG_ENV_IS_EMBEDDED -# endif -# endif -#endif - #include "compiler.h" #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT @@ -88,7 +67,7 @@ extern unsigned long nand_env_oob_offset; * If the environment is in RAM, allocate extra space for it in the malloc * region. */ -#if defined(CONFIG_ENV_IS_EMBEDDED) +#if defined(ENV_IS_EMBEDDED) #define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN #elif (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE < CONFIG_SYS_MONITOR_BASE) || \ (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) || \ diff --git a/tools/Makefile b/tools/Makefile index 80bc62befcb..edfa40903d9 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -36,21 +36,20 @@ endif subdir-$(HOST_TOOLS_ALL) += gdb # Merge all the different vars for envcrc into one -ENVCRC-$(CONFIG_ENV_IS_EMBEDDED) = y ENVCRC-$(CONFIG_ENV_IS_IN_EEPROM) = y ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y ENVCRC-$(CONFIG_ENV_IS_IN_ONENAND) = y ENVCRC-$(CONFIG_ENV_IS_IN_NAND) = y ENVCRC-$(CONFIG_ENV_IS_IN_NVRAM) = y ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y -CONFIG_BUILD_ENVCRC ?= $(ENVCRC-y) +BUILD_ENVCRC ?= $(ENVCRC-y) hostprogs-$(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER) += atmel_pmecc_params hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo HOSTCFLAGS_bmp_logo.o := -pedantic -hostprogs-$(CONFIG_BUILD_ENVCRC) += envcrc +hostprogs-$(BUILD_ENVCRC) += envcrc envcrc-objs := envcrc.o lib/crc32.o env/embedded.o lib/sha1.o hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr diff --git a/tools/envcrc.c b/tools/envcrc.c index a021c785aee..550f31038bd 100644 --- a/tools/envcrc.c +++ b/tools/envcrc.c @@ -40,10 +40,6 @@ # endif #endif /* CONFIG_ENV_IS_IN_FLASH */ -#if defined(ENV_IS_EMBEDDED) && !defined(CONFIG_BUILD_ENVCRC) -# define CONFIG_BUILD_ENVCRC -#endif - #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT # define ENV_HEADER_SIZE (sizeof(uint32_t) + 1) #else @@ -53,17 +49,17 @@ #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) -#ifdef CONFIG_BUILD_ENVCRC +#ifdef ENV_IS_EMBEDDED # include extern unsigned int env_size; extern env_t embedded_environment; -#endif /* CONFIG_BUILD_ENVCRC */ +#endif /* ENV_IS_EMBEDDED */ extern uint32_t crc32(uint32_t, const unsigned char *, unsigned int); int main (int argc, char **argv) { -#ifdef CONFIG_BUILD_ENVCRC +#ifdef ENV_IS_EMBEDDED unsigned char pad = 0x00; uint32_t crc; unsigned char *envptr = (unsigned char *)&embedded_environment, -- cgit v1.3.1 From 9b0240f8c6a1caa42da73835090fcb6db60f3d23 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:18 -0500 Subject: Convert CONFIG_DM9000_BYTE_SWAPPED et al to Kconfig This converts the following to Kconfig: CONFIG_DM9000_BYTE_SWAPPED CONFIG_DM9000_NO_SROM CONFIG_DM9000_USE_16BIT CONFIG_DM9000_DEBUG CONFIG_MXC_GPT_HCLK CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC Signed-off-by: Tom Rini --- arch/arm/Kconfig | 2 ++ arch/arm/mach-imx/Kconfig | 3 +++ board/davinci/da8xxevm/Kconfig | 3 +++ board/timll/devkit8000/devkit8000.c | 7 +++---- configs/M5253DEMO_defconfig | 1 + configs/at91sam9261ek_dataflash_cs0_defconfig | 2 ++ configs/at91sam9261ek_dataflash_cs3_defconfig | 2 ++ configs/at91sam9261ek_nandflash_defconfig | 2 ++ configs/devkit8000_defconfig | 2 ++ drivers/net/Kconfig | 12 ++++++++++++ include/configs/M5253DEMO.h | 6 ------ include/configs/at91sam9261ek.h | 7 ------- include/configs/brppt2.h | 2 -- include/configs/ci20.h | 7 ------- include/configs/devkit8000.h | 11 ----------- include/configs/mx6_common.h | 1 - include/configs/mx7_common.h | 1 - include/configs/omapl138_lcdk.h | 1 - 18 files changed, 32 insertions(+), 40 deletions(-) (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d3b11b84959..8381e09e102 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -915,6 +915,7 @@ config ARCH_MX7 select CPU_V7A select GPIO_EXTRA_HEADER select MACH_IMX + select MXC_GPT_HCLK select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -928,6 +929,7 @@ config ARCH_MX6 select CPU_V7A select GPIO_EXTRA_HEADER select MACH_IMX + select MXC_GPT_HCLK select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index ee5f1996a83..3266545c266 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -18,6 +18,9 @@ config SYSCOUNTER_TIMER config GPT_TIMER bool +config MXC_GPT_HCLK + bool + config IMX_RDC bool "i.MX Resource domain controller driver" depends on ARCH_MX6 || ARCH_MX7 diff --git a/board/davinci/da8xxevm/Kconfig b/board/davinci/da8xxevm/Kconfig index c5499a63fd3..34055f69754 100644 --- a/board/davinci/da8xxevm/Kconfig +++ b/board/davinci/da8xxevm/Kconfig @@ -37,6 +37,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "omapl138_lcdk" +config NAND_6BYTES_OOB_FREE_10BYTES_ECC + def_bool y + endif source "board/ti/common/Kconfig" diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 0808ca1a54c..06009d8ad54 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -76,10 +76,11 @@ int board_init(void) } /* Configure GPMC registers for DM9000 */ +#define DM9000_BASE 0x2c000000 static void gpmc_dm9000_config(void) { enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], - CONFIG_DM9000_BASE, GPMC_SIZE_16M); + DM9000_BASE, GPMC_SIZE_16M); } /* @@ -100,9 +101,7 @@ int misc_init_r(void) #endif #ifdef CONFIG_DRIVER_DM9000 - /* Configure GPMC registers for DM9000 */ - enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], - CONFIG_DM9000_BASE, GPMC_SIZE_16M); + gpmc_dm9000_config(); /* Use OMAP DIE_ID as MAC address */ if (!eth_env_get_enetaddr("ethaddr", enetaddr)) { diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index 581023f967b..2684ce05f26 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -44,4 +44,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_MAX_FLASH_SECT=2048 CONFIG_USE_SYS_MAX_FLASH_BANKS=y CONFIG_DRIVER_DM9000=y +CONFIG_DM9000_BYTE_SWAPPED=y CONFIG_MCFUART=y diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig index c6c83b8da35..a398e6d97a1 100644 --- a/configs/at91sam9261ek_dataflash_cs0_defconfig +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -54,6 +54,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_DRIVER_DM9000=y +CONFIG_DM9000_NO_SROM=y +CONFIG_DM9000_USE_16BIT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig index 1c16d26c824..1b464ff2925 100644 --- a/configs/at91sam9261ek_dataflash_cs3_defconfig +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -54,6 +54,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_DRIVER_DM9000=y +CONFIG_DM9000_NO_SROM=y +CONFIG_DM9000_USE_16BIT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index 8dbcb27f95c..f2326249425 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -52,6 +52,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_DRIVER_DM9000=y +CONFIG_DM9000_NO_SROM=y +CONFIG_DM9000_USE_16BIT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index 8347b67681d..6fd4410df5b 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -84,4 +84,6 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 CONFIG_DRIVER_DM9000=y +CONFIG_DM9000_NO_SROM=y +CONFIG_DM9000_USE_16BIT=y CONFIG_JFFS2_NAND=y diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 4e5da5ab72a..0607f959da4 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -198,6 +198,18 @@ config DRIVER_DM9000 help The Davicom DM9000 parallel bus external ethernet interface chip. +config DM9000_BYTE_SWAPPED + bool "Byte swapped access for DM9000" + depends on DRIVER_DM9000 + +config DM9000_NO_SROM + bool "No SROM on DM9000" + depends on DRIVER_DM9000 + +config DM9000_USE_16BIT + bool "Use 16bit access in DM9000" + depends on DRIVER_DM9000 + config DWC_ETH_QOS bool "Synopsys DWC Ethernet QOS device support" select PHYLIB diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 7e37c6d1199..ad55938348e 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -20,12 +20,6 @@ env/embedded.o(.text*); #ifdef CONFIG_DRIVER_DM9000 -# define CONFIG_DM9000_BASE (CFG_SYS_CS1_BASE | 0x300) -# define DM9000_IO CONFIG_DM9000_BASE -# define DM9000_DATA (CONFIG_DM9000_BASE + 4) -# undef CONFIG_DM9000_DEBUG -# define CONFIG_DM9000_BYTE_SWAPPED - # define CONFIG_OVERWRITE_ETHADDR_ONCE # define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 56247e390bf..39f6ff8a725 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -34,13 +34,6 @@ #endif -/* Ethernet */ -#define CONFIG_DM9000_BASE 0x30000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 4) -#define CONFIG_DM9000_USE_16BIT -#define CONFIG_DM9000_NO_SROM - /* USB */ #define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index d35c7c4a591..80104b2d319 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -16,8 +16,6 @@ #define CFG_SYS_PL310_BASE L2_PL310_BASE #endif /* !CONFIG_SYS_L2CACHE_OFF */ -#define CONFIG_MXC_GPT_HCLK - /* MMC */ /* Boot */ diff --git a/include/configs/ci20.h b/include/configs/ci20.h index 3329c24fa68..446d5c4f3da 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -17,11 +17,4 @@ /* NS16550-ish UARTs */ #define CFG_SYS_NS16550_CLK 48000000 -/* Ethernet: davicom DM9000 */ -#define CONFIG_DM9000_BASE 0xb6000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 2) - -/* Miscellaneous configuration options */ - #endif /* __CONFIG_CI20_H__ */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 46410595c2b..e3621fd6f9c 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -16,17 +16,6 @@ #include -/* Hardware drivers */ -/* DM9000 */ -#define CONFIG_DM9000_BASE 0x2c000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) -#define CONFIG_DM9000_USE_16BIT 1 -#define CONFIG_DM9000_NO_SROM 1 -#undef CONFIG_DM9000_DEBUG - -/* TWL4030 */ - /* BOOTP/DHCP options */ #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 245530aa640..dd8cabc2e93 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -16,7 +16,6 @@ #endif #endif -#define CONFIG_MXC_GPT_HCLK #include #include diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index d5af6990107..6e14b4fbf05 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -14,7 +14,6 @@ #include /* Timer settings */ -#define CONFIG_MXC_GPT_HCLK #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ /* Miscellaneous configurable options */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 788a1113868..f19211fe647 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -109,7 +109,6 @@ #define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE #define CFG_SYS_NAND_MASK_CLE 0x10 #define CFG_SYS_NAND_MASK_ALE 0x8 -#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC #define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CFG_SYS_NAND_U_BOOT_DST 0xc1080000 #define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST -- cgit v1.3.1 From 21491883d2af674f698a94699a5a8b7356d02adf Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:19 -0500 Subject: fec_mxc: Remove CONFIG_FEC_FIXED_SPEED support This option is only used on one platform currently. However, with PHYLIB enabled, which this platform also does, this option is not checked and the functional use case is handled. Remove this code. Signed-off-by: Tom Rini --- doc/README.fec_mxc | 6 ------ drivers/net/fec_mxc.c | 4 ---- include/configs/brppt2.h | 3 --- 3 files changed, 13 deletions(-) (limited to 'include') diff --git a/doc/README.fec_mxc b/doc/README.fec_mxc index d17dfb676f7..4e890d348f4 100644 --- a/doc/README.fec_mxc +++ b/doc/README.fec_mxc @@ -22,12 +22,6 @@ CONFIG_FEC_MXC_PHYADDR Optional, selects the exact phy address that should be connected and function fecmxc_initialize will try to initialize it. -CONFIG_FEC_FIXED_SPEED - Optional, selects a fixed speed on the MAC interface without asking some - phy. This is usefull if there is a direct MAC <-> MAC connection, for - example if the CPU is connected directly via the RGMII interface to a - ethernet-switch. - Reading the ethaddr from the SoC eFuses: if CONFIG_FEC_MXC is defined and the U-Boot environment does not contain the ethaddr variable, then its value gets read from the corresponding eFuses in diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index a61a1fc7573..9cb235ad5e3 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -268,7 +268,6 @@ static int miiphy_restart_aneg(struct eth_device *dev) return ret; } -#ifndef CONFIG_FEC_FIXED_SPEED static int miiphy_wait_aneg(struct eth_device *dev) { uint32_t start; @@ -294,7 +293,6 @@ static int miiphy_wait_aneg(struct eth_device *dev) return 0; } -#endif /* CONFIG_FEC_FIXED_SPEED */ #endif static int fec_rx_task_enable(struct fec_priv *fec) @@ -536,8 +534,6 @@ static int fec_open(struct udevice *dev) } speed = fec->phydev->speed; } -#elif CONFIG_FEC_FIXED_SPEED - speed = CONFIG_FEC_FIXED_SPEED; #else miiphy_wait_aneg(edev); speed = miiphy_speed(edev->name, fec->phy_id); diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 80104b2d319..984602c2cf7 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -78,9 +78,6 @@ BUR_COMMON_ENV \ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* Ethernet */ -#define CONFIG_FEC_FIXED_SPEED _1000BASET - /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -- cgit v1.3.1 From 98fbad631f9973eb763d83571ec8dde00a94a76c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:20 -0500 Subject: Convert CONFIG_FLASH_SHOW_PROGRESS to Kconfig This converts the following to Kconfig: CONFIG_FLASH_SHOW_PROGRESS Signed-off-by: Tom Rini --- README | 5 ----- configs/3c120_defconfig | 1 + configs/M5208EVBE_defconfig | 1 + configs/M5235EVB_Flash32_defconfig | 1 + configs/M5235EVB_defconfig | 1 + configs/M5249EVB_defconfig | 1 + configs/M5272C3_defconfig | 1 + configs/M5275EVB_defconfig | 1 + configs/M5282EVB_defconfig | 1 + configs/M53017EVB_defconfig | 1 + configs/M5329AFEE_defconfig | 1 + configs/M5329BFEE_defconfig | 1 + configs/M5373EVB_defconfig | 1 + configs/MCR3000_defconfig | 1 + configs/MPC837XERDB_defconfig | 1 + configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/ae350_rv32_defconfig | 1 + configs/ae350_rv32_spl_defconfig | 1 + configs/ae350_rv32_spl_xip_defconfig | 1 + configs/ae350_rv32_xip_defconfig | 1 + configs/ae350_rv64_defconfig | 1 + configs/ae350_rv64_spl_defconfig | 1 + configs/ae350_rv64_spl_xip_defconfig | 1 + configs/ae350_rv64_xip_defconfig | 1 + configs/amcore_defconfig | 1 + configs/astro_mcf5373l_defconfig | 1 + configs/at91sam9263ek_norflash_boot_defconfig | 1 + configs/at91sam9263ek_norflash_defconfig | 1 + configs/boston32r2_defconfig | 1 + configs/boston32r2el_defconfig | 1 + configs/boston32r6_defconfig | 1 + configs/boston32r6el_defconfig | 1 + configs/boston64r2_defconfig | 1 + configs/boston64r2el_defconfig | 1 + configs/boston64r6_defconfig | 1 + configs/boston64r6el_defconfig | 1 + configs/comtrend_ct5361_ram_defconfig | 1 + configs/comtrend_wap5813n_ram_defconfig | 1 + configs/da850evm_direct_nor_defconfig | 1 + configs/devkit3250_defconfig | 1 + configs/gazerbeam_defconfig | 1 + configs/huawei_hg556a_ram_defconfig | 1 + configs/integratorap_cm720t_defconfig | 1 + configs/integratorap_cm920t_defconfig | 1 + configs/integratorap_cm926ejs_defconfig | 1 + configs/integratorap_cm946es_defconfig | 1 + configs/integratorcp_cm1136_defconfig | 1 + configs/integratorcp_cm920t_defconfig | 1 + configs/integratorcp_cm926ejs_defconfig | 1 + configs/integratorcp_cm946es_defconfig | 1 + configs/j7200_evm_a72_defconfig | 1 + configs/j7200_evm_r5_defconfig | 1 + configs/j7200_hs_evm_a72_defconfig | 1 + configs/j7200_hs_evm_r5_defconfig | 1 + configs/j721e_evm_a72_defconfig | 1 + configs/j721e_evm_r5_defconfig | 1 + configs/j721e_hs_evm_a72_defconfig | 1 + configs/j721e_hs_evm_r5_defconfig | 1 + configs/j721s2_evm_a72_defconfig | 1 + configs/j721s2_evm_r5_defconfig | 1 + configs/j721s2_hs_evm_a72_defconfig | 1 + configs/j721s2_hs_evm_r5_defconfig | 1 + configs/kmcent2_defconfig | 1 + configs/kmcoge5ne_defconfig | 1 + configs/kmeter1_defconfig | 1 + configs/kmopti2_defconfig | 1 + configs/kmsupx5_defconfig | 1 + configs/kmtepr2_defconfig | 1 + configs/malta64_defconfig | 1 + configs/malta64el_defconfig | 1 + configs/malta_defconfig | 1 + configs/maltael_defconfig | 1 + configs/mccmon6_nor_defconfig | 1 + configs/mccmon6_sd_defconfig | 1 + configs/microblaze-generic_defconfig | 1 + configs/octeon_ebb7304_defconfig | 1 + configs/omap35_logic_somlv_defconfig | 1 + configs/omap3_logic_somlv_defconfig | 1 + configs/pm9261_defconfig | 1 + configs/pm9263_defconfig | 1 + configs/qemu-riscv32_defconfig | 1 + configs/qemu-riscv32_smode_defconfig | 1 + configs/qemu-riscv32_spl_defconfig | 1 + configs/qemu-riscv64_defconfig | 1 + configs/qemu-riscv64_smode_defconfig | 1 + configs/qemu-riscv64_spl_defconfig | 1 + configs/qemu_arm64_defconfig | 1 + configs/qemu_arm_defconfig | 1 + configs/r2dplus_defconfig | 1 + configs/sama5d3xek_mmc_defconfig | 1 + configs/sama5d3xek_nandflash_defconfig | 1 + configs/sama5d3xek_spiflash_defconfig | 1 + configs/sfr_nb4-ser_ram_defconfig | 1 + configs/socrates_defconfig | 1 + configs/synquacer_developerbox_defconfig | 1 + configs/total_compute_defconfig | 1 + configs/tuge1_defconfig | 1 + configs/tuxx1_defconfig | 1 + configs/vexpress_aemv8a_juno_defconfig | 1 + configs/vexpress_aemv8a_semi_defconfig | 1 + configs/vexpress_ca9x4_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/xtfpga_defconfig | 1 + configs/zynq_cse_nor_defconfig | 1 + drivers/mtd/Kconfig | 9 +++++++++ drivers/mtd/cfi_flash.c | 4 ++-- include/configs/P1010RDB.h | 1 - include/configs/P2041RDB.h | 2 -- include/configs/T102xRDB.h | 2 -- include/configs/T104xRDB.h | 2 -- include/configs/T208xQDS.h | 2 -- include/configs/T208xRDB.h | 2 -- include/configs/T4240RDB.h | 2 -- include/configs/blanche.h | 1 - include/configs/draak.h | 1 - include/configs/eb_cpu5282.h | 1 - include/configs/ebisu.h | 1 - include/configs/km/pg-wcom-ls102xa.h | 2 -- include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 2 -- include/configs/ls1043a_common.h | 4 ---- include/configs/ls1046aqds.h | 4 ---- include/configs/ls1088aqds.h | 2 -- include/configs/ls1088ardb.h | 2 -- include/configs/ls2080aqds.h | 2 -- include/configs/ls2080ardb.h | 2 -- include/configs/p1_p2_rdb_pc.h | 1 - include/configs/salvator-x.h | 1 - include/configs/ulcb.h | 1 - include/configs/zynq-common.h | 3 --- 132 files changed, 116 insertions(+), 51 deletions(-) (limited to 'include') diff --git a/README b/README index 3fef1d2afa0..05835207426 100644 --- a/README +++ b/README @@ -1481,11 +1481,6 @@ Configuration Settings: s29ws-n MirrorBit flash has non-standard addresses for buffered write commands. -- CONFIG_FLASH_SHOW_PROGRESS - If defined (must be an integer), print out countdown - digits and dots. Recommended value: 45 (9..1) for 80 - column displays, 15 (3..1) for 40 column displays. - - CONFIG_FLASH_VERIFY If defined, the content of the flash (destination) is compared against the source after the write operation. An error message diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig index 3d62512ff9d..8c421f099be 100644 --- a/configs/3c120_defconfig +++ b/configs/3c120_defconfig @@ -39,6 +39,7 @@ CONFIG_MISC=y CONFIG_ALTERA_SYSID=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index 680c2d43671..20250c02a11 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -37,6 +37,7 @@ CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=254 diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index c0087aa67f9..38c5076d5f8 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -44,6 +44,7 @@ CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=137 diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index b099e986067..cb5bcb7221c 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -44,6 +44,7 @@ CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=137 diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig index b192839766e..de7f14165bd 100644 --- a/configs/M5249EVB_defconfig +++ b/configs/M5249EVB_defconfig @@ -27,6 +27,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_CHECKSUM=y diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index a321b1c5c24..f2d70a4e269 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_OR7_PRELIM=0xFFC0007C CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=137 diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index e7e799b7bdb..01961e5ae27 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_I2C_SLAVE=0x7F CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=11 CONFIG_MCFFEC=y diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index 5521cced6da..0ef2e7b4ffe 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_CHECKSUM=y diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index 32d19580880..8158cd4e84e 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index 9f0b4196392..6fede625fb8 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -39,6 +39,7 @@ CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=137 diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index 05388796fb1..fe70245497c 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -40,6 +40,7 @@ CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=137 diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index 90d83216489..b074cf520ff 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -40,6 +40,7 @@ CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=137 diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index d8d6417d21e..7d54807e645 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -83,6 +83,7 @@ CONFIG_SYS_OR7_PRELIM=0xFFFF810A CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=35 CONFIG_MTD_RAW_NAND=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 1a571cf6bce..40fc1d1da4a 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -197,6 +197,7 @@ CONFIG_SYS_I2C_SPEED=400000 CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 517fd785dd3..c6f5d87bb95 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -68,6 +68,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 5c83e808d57..b6ebac39805 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -67,6 +67,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index b354237db3e..d272ede8d4a 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -67,6 +67,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index d876602fa01..e5c8358e54d 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -34,6 +34,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 1c0b5345379..a66db656216 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -40,6 +40,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index dc584a6fd45..606962c0a71 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -41,6 +41,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index ec6299495d6..069a9d3982e 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -35,6 +35,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 65b3fc646f3..c373b99b956 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -34,6 +34,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 4c3e1beb005..f235db7990a 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -40,6 +40,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 3c6408a12ad..4cbfd52fb19 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -41,6 +41,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index f4deee6871c..4fed2ead1db 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -35,6 +35,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig index b8e8bc41b6a..cebb79f733c 100644 --- a/configs/amcore_defconfig +++ b/configs/amcore_defconfig @@ -34,6 +34,7 @@ CONFIG_ENV_IS_IN_FLASH=y # CONFIG_NET is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=1024 diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index 9e5665a12b8..a1a25622c77 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -42,6 +42,7 @@ CONFIG_SYS_I2C_SLAVE=0x7F CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index e7d32f09910..d5db0044815 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -50,6 +50,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=256 CONFIG_MTD_RAW_NAND=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index 794cf0e38d0..d82cd214721 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -51,6 +51,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=256 CONFIG_MTD_RAW_NAND=y diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig index d80152be0f3..708a3a39d88 100644 --- a/configs/boston32r2_defconfig +++ b/configs/boston32r2_defconfig @@ -42,6 +42,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig index 8624853ebac..41769be634c 100644 --- a/configs/boston32r2el_defconfig +++ b/configs/boston32r2el_defconfig @@ -43,6 +43,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig index 464b2559202..12abbb89985 100644 --- a/configs/boston32r6_defconfig +++ b/configs/boston32r6_defconfig @@ -43,6 +43,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig index 67abbb9f7fa..89d14b61fbf 100644 --- a/configs/boston32r6el_defconfig +++ b/configs/boston32r6el_defconfig @@ -44,6 +44,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig index 253d2323749..80031666f9c 100644 --- a/configs/boston64r2_defconfig +++ b/configs/boston64r2_defconfig @@ -43,6 +43,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig index 190c993725a..ad79c4e5851 100644 --- a/configs/boston64r2el_defconfig +++ b/configs/boston64r2el_defconfig @@ -44,6 +44,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig index f6e246e07f4..581ddfa5b33 100644 --- a/configs/boston64r6_defconfig +++ b/configs/boston64r6_defconfig @@ -43,6 +43,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig index 82e01bb21f7..9a5655fb027 100644 --- a/configs/boston64r6el_defconfig +++ b/configs/boston64r6el_defconfig @@ -44,6 +44,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig index 594bddea6e1..f3f09e593fe 100644 --- a/configs/comtrend_ct5361_ram_defconfig +++ b/configs/comtrend_ct5361_ram_defconfig @@ -51,6 +51,7 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/comtrend_wap5813n_ram_defconfig b/configs/comtrend_wap5813n_ram_defconfig index 69a958d8796..a8ce3000d8a 100644 --- a/configs/comtrend_wap5813n_ram_defconfig +++ b/configs/comtrend_wap5813n_ram_defconfig @@ -51,6 +51,7 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 9332c8cb3ff..137f9ec4f57 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -65,6 +65,7 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index 66300698a9f..cd5ddc4ad3f 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -65,6 +65,7 @@ CONFIG_SYS_I2C_LPC32XX=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=71 diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index d2946971b48..a852b96d4ef 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -192,6 +192,7 @@ CONFIG_IHS_FPGA=y CONFIG_FSL_ESDHC=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index 9fbec97d51d..fdff11e16fe 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -51,6 +51,7 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig index e2709ec5218..444953db91a 100644 --- a/configs/integratorap_cm720t_defconfig +++ b/configs/integratorap_cm720t_defconfig @@ -30,6 +30,7 @@ CONFIG_SYS_RX_ETH_BUFFER=8 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig index e8baca158b8..6eb912c1a14 100644 --- a/configs/integratorap_cm920t_defconfig +++ b/configs/integratorap_cm920t_defconfig @@ -30,6 +30,7 @@ CONFIG_SYS_RX_ETH_BUFFER=8 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig index 04032c8b946..023b84200ea 100644 --- a/configs/integratorap_cm926ejs_defconfig +++ b/configs/integratorap_cm926ejs_defconfig @@ -30,6 +30,7 @@ CONFIG_SYS_RX_ETH_BUFFER=8 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig index 3d910d3d48d..fab72740681 100644 --- a/configs/integratorap_cm946es_defconfig +++ b/configs/integratorap_cm946es_defconfig @@ -30,6 +30,7 @@ CONFIG_SYS_RX_ETH_BUFFER=8 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig index ea1f858135e..7417b53e86f 100644 --- a/configs/integratorcp_cm1136_defconfig +++ b/configs/integratorcp_cm1136_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTFILE="uImage" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig index 19c72c759e7..36b71fc4019 100644 --- a/configs/integratorcp_cm920t_defconfig +++ b/configs/integratorcp_cm920t_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTFILE="uImage" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig index e0ba5720f3f..947d21ef35e 100644 --- a/configs/integratorcp_cm926ejs_defconfig +++ b/configs/integratorcp_cm926ejs_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTFILE="uImage" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig index e4e960e72a3..630fe0d813d 100644 --- a/configs/integratorcp_cm946es_defconfig +++ b/configs/integratorcp_cm946es_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTFILE="uImage" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index e7cdd84ecba..053f29b11f5 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -138,6 +138,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 87101cbf53e..dc6c1b6935d 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -112,6 +112,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j7200_hs_evm_a72_defconfig b/configs/j7200_hs_evm_a72_defconfig index b9598ca1fe2..782a42b7465 100644 --- a/configs/j7200_hs_evm_a72_defconfig +++ b/configs/j7200_hs_evm_a72_defconfig @@ -139,6 +139,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j7200_hs_evm_r5_defconfig b/configs/j7200_hs_evm_r5_defconfig index 608778ade86..73979f4cc32 100644 --- a/configs/j7200_hs_evm_r5_defconfig +++ b/configs/j7200_hs_evm_r5_defconfig @@ -112,6 +112,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 48a24446941..5efaff26d22 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -140,6 +140,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index d6da4c6ae2e..9d333e49056 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -120,6 +120,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig index a1cc7da0bfb..ec66b18740e 100644 --- a/configs/j721e_hs_evm_a72_defconfig +++ b/configs/j721e_hs_evm_a72_defconfig @@ -141,6 +141,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721e_hs_evm_r5_defconfig b/configs/j721e_hs_evm_r5_defconfig index eb9df365538..e496ec85af1 100644 --- a/configs/j721e_hs_evm_r5_defconfig +++ b/configs/j721e_hs_evm_r5_defconfig @@ -120,6 +120,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 2b2f80c4aaa..99a0eee12d9 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -139,6 +139,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 2de5d87bdb2..cd250169980 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -118,6 +118,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721s2_hs_evm_a72_defconfig b/configs/j721s2_hs_evm_a72_defconfig index 3e0ec40fb2e..9fc90737da8 100644 --- a/configs/j721s2_hs_evm_a72_defconfig +++ b/configs/j721s2_hs_evm_a72_defconfig @@ -140,6 +140,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721s2_hs_evm_r5_defconfig b/configs/j721s2_hs_evm_r5_defconfig index bc8672f7096..d9988fc17fc 100644 --- a/configs/j721s2_hs_evm_r5_defconfig +++ b/configs/j721s2_hs_evm_r5_defconfig @@ -118,6 +118,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index 2abda788939..bd4943006c1 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -74,6 +74,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 9609f58fb4d..4ea7da8d32c 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -227,6 +227,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index bd3d6315b1f..96298ed0c38 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -193,6 +193,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index de6d99e91ec..db717e4a15d 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -208,6 +208,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index a231510a76f..69de685bafd 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -185,6 +185,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index e6beb62f862..92f2b0adecd 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -207,6 +207,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig index b635c651aae..03de1616840 100644 --- a/configs/malta64_defconfig +++ b/configs/malta64_defconfig @@ -37,6 +37,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig index 243213cb819..3ea9fa9857e 100644 --- a/configs/malta64el_defconfig +++ b/configs/malta64el_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 diff --git a/configs/malta_defconfig b/configs/malta_defconfig index ed41e298f44..317b422a6b6 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -36,6 +36,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index 63e5fcb6a5c..3e4d2beda2f 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -38,6 +38,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig index 2566bdef168..5f8a2873733 100644 --- a/configs/mccmon6_nor_defconfig +++ b/configs/mccmon6_nor_defconfig @@ -63,6 +63,7 @@ CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig index 43ffc3c6bc1..651eef5d06f 100644 --- a/configs/mccmon6_sd_defconfig +++ b/configs/mccmon6_sd_defconfig @@ -61,6 +61,7 @@ CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index f1b9cb461b9..186521aac6c 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -64,6 +64,7 @@ CONFIG_LED_GPIO=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index b966b1d24f0..a642a64d5c1 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -50,6 +50,7 @@ CONFIG_MMC_OCTEONTX=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index 471e0556fa8..fb9430b4541 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -74,6 +74,7 @@ CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index e18cbaa5c18..37708516f1d 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -75,6 +75,7 @@ CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig index d43043427a9..d30d07bcbf1 100644 --- a/configs/pm9261_defconfig +++ b/configs/pm9261_defconfig @@ -45,6 +45,7 @@ CONFIG_AT91_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=256 CONFIG_MTD_RAW_NAND=y diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig index 2e42ba08032..11ec775b38b 100644 --- a/configs/pm9263_defconfig +++ b/configs/pm9263_defconfig @@ -49,6 +49,7 @@ CONFIG_AT91_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=256 CONFIG_MTD_RAW_NAND=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 40ba25297f6..425bb37c988 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -20,4 +20,5 @@ CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index eb9bf9b918a..eeb90360cdb 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -21,4 +21,5 @@ CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index 756e7f35f68..04447e5ed3c 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -25,5 +25,6 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 # CONFIG_BINMAN_FDT is not set diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index d5eae95c80f..7430fa075d7 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -20,4 +20,5 @@ CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 1cb06b4b2cd..03ef58ba475 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -23,4 +23,5 @@ CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 68b16f0a2c8..840e0ff151c 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -24,5 +24,6 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 # CONFIG_BINMAN_FDT is not set diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 4123338b8dd..93352331526 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -45,6 +45,7 @@ CONFIG_DFU_RAM=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index f6c6c28764e..6373185f297 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -47,6 +47,7 @@ CONFIG_DFU_RAM=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig index 4217175345d..0653089ecae 100644 --- a/configs/r2dplus_defconfig +++ b/configs/r2dplus_defconfig @@ -44,6 +44,7 @@ CONFIG_IDE_RESET=y CONFIG_CLK=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=256 CONFIG_E1000=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index b3108fa64af..ba2e7dd76d4 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -81,6 +81,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=131 diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index f06c21fdf11..3afb2aaffba 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -80,6 +80,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=131 diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 2045146fb8d..8d71ba7d4f4 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -82,6 +82,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=131 diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index 5cf020a3ebb..61404246707 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -53,6 +53,7 @@ CONFIG_LED_BCM6358=y CONFIG_LED_GPIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index f45f570764c..4cc50d35589 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -77,6 +77,7 @@ CONFIG_SYS_I2C_FSL=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_QUIET_TEST=y CONFIG_SYS_MAX_FLASH_SECT=256 diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index f69b873a36a..a6fc65baeec 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -60,6 +60,7 @@ CONFIG_MMC_SDHCI_F_SDH30=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/total_compute_defconfig b/configs/total_compute_defconfig index 807e9ebd862..04d27058f38 100644 --- a/configs/total_compute_defconfig +++ b/configs/total_compute_defconfig @@ -53,6 +53,7 @@ CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 83120759b15..0c3381461eb 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -185,6 +185,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index ee1640608d2..4f192ad2624 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -209,6 +209,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 73b7363b68d..47841e8b6ca 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index 0b566b8005c..4b22d49b29a 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index 70ce13ecccf..83e15ddbe17 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -43,6 +43,7 @@ CONFIG_SYS_MMC_MAX_BLK_COUNT=127 CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index a4c555dac5c..50685657690 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -109,6 +109,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=10 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig index c58514669dd..f5eeea426bb 100644 --- a/configs/xtfpga_defconfig +++ b/configs/xtfpga_defconfig @@ -39,6 +39,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index f1c648a8f9a..c194e89b7ec 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -75,6 +75,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=10 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index d8e2dec0a8d..04ae45665e4 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -77,6 +77,15 @@ config SYS_FLASH_CFI_WIDTH help This must be kept in sync with the table in include/flash.h +config FLASH_SHOW_PROGRESS + int "Print out a countdown durinng writes" + depends on FLASH_CFI_DRIVER + default 45 + help + If set to a non-zero value, print out countdown digits and dots. + Recommended value: 45 (9..1) for 80 column displays, 15 (3..1) for 40 + column displays. + config CFI_FLASH bool "Enable Driver Model for CFI Flash driver" depends on DM_MTD diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index c1cdd2cbc3e..f378f6fb613 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1292,7 +1292,7 @@ void flash_print_info(flash_info_t *info) * effect updates to digit and dots. Repeated code is nasty too, so * we define it once here. */ -#ifdef CONFIG_FLASH_SHOW_PROGRESS +#if CONFIG_FLASH_SHOW_PROGRESS #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ if (flash_verbose) { \ dots -= dots_sub; \ @@ -1325,7 +1325,7 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE int buffered_size; #endif -#ifdef CONFIG_FLASH_SHOW_PROGRESS +#if CONFIG_FLASH_SHOW_PROGRESS int digit = CONFIG_FLASH_SHOW_PROGRESS; int scale = 0; int dots = 0; diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 4418d516956..f79c62adba3 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -161,7 +161,6 @@ extern unsigned long get_sdram_size(void); #define CFG_SYS_NOR_FTIM3 0x0 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ /* CFI for NOR Flash */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 8b901ca47a0..707157e4a9a 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -101,8 +101,6 @@ #define PIXIS_LBMAP_SHIFT 4 #define PIXIS_LBMAP_ALTBANK 0x40 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC #define CFG_SYS_NAND_BASE 0xffa00000 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 623d4cf5562..b590f127392 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -158,8 +158,6 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} #ifdef CONFIG_TARGET_T1024RDB diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index b6938056bbe..9d805f446b4 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -126,8 +126,6 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} /* CPLD on IFC */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index a93e05dd4d2..804b7ec4c1c 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -119,8 +119,6 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000, CFG_SYS_FLASH_BASE_PHYS} diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index cf65a0da188..d8213b4662f 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -114,8 +114,6 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS } /* CPLD on IFC */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index b51762264ad..958933689d3 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -184,8 +184,6 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000, CFG_SYS_FLASH_BASE_PHYS} diff --git a/include/configs/blanche.h b/include/configs/blanche.h index cb28ae28dd3..fe09997e178 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -25,7 +25,6 @@ #if !defined(CONFIG_MTD_NOR_FLASH) #define CONFIG_SH_QSPI_BASE 0xE6B10000 #else -#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CFG_SYS_FLASH_BASE 0x00000000 #define CFG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ #define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) } diff --git a/include/configs/draak.h b/include/configs/draak.h index 8140bc469c5..946f1d96469 100644 --- a/include/configs/draak.h +++ b/include/configs/draak.h @@ -13,7 +13,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } #define CFG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 21eab9b3a47..717f49ca29d 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -84,7 +84,6 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE #define CFG_SYS_INT_FLASH_BASE 0xF0000000 diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index d1882a9646b..ad5944230a6 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -15,7 +15,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } #define CFG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 7fe2ece8403..8d5b24d827d 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -58,8 +58,6 @@ FTIM2_NOR_TWP(0xb)) #define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } #define CFG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d6681e85987..e49588489c1 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -60,7 +60,6 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CFG_SYS_WRITE_SWAPPED_DATA #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 3c4c207edd0..b07978a999e 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -92,8 +92,6 @@ FTIM2_NOR_TWPH(0x0e)) #define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } #define CFG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index a3fa92d1ff4..e54e903a8a9 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -90,10 +90,6 @@ #define CFG_SYS_FLASH_BASE 0x60000000 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#endif #endif #endif diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 553ae841cab..e9b8ad0c0b7 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -41,10 +41,6 @@ #define CFG_SYS_FLASH_BASE 0x60000000 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#endif #endif /* LPUART */ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index a35045d640f..dc9cded49fd 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -62,8 +62,6 @@ #define CFG_SYS_IFC_CCR 0x01000000 #ifndef SYS_NO_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ CFG_SYS_FLASH_BASE + 0x40000000} #endif diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 7bc4fc6a665..e2444cd8eb4 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -47,8 +47,6 @@ #define CFG_SYS_IFC_CCR 0x01000000 #ifndef SYS_NO_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif #endif diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 924d4057d93..4e6d40afbf1 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -64,8 +64,6 @@ #define CFG_SYS_IFC_CCR 0x01000000 #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ CFG_SYS_FLASH_BASE + 0x40000000} #endif diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index c50b6030680..8f36958f710 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -61,8 +61,6 @@ #define CFG_SYS_IFC_CCR 0x01000000 #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ CFG_SYS_FLASH_BASE + 0x40000000} #endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index f86b96b2141..eb2c5a2d837 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -199,7 +199,6 @@ #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 2e422cd241e..8dc6702de48 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -13,7 +13,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } #define CFG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index ab199bc726a..6e03375c6c3 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -13,7 +13,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } #define CFG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index b8c142fed37..37b54289073 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -35,9 +35,6 @@ /* Ethernet driver */ /* NOR */ -#ifdef CONFIG_MTD_NOR_FLASH -# define CONFIG_FLASH_SHOW_PROGRESS 10 -#endif #ifdef CONFIG_USB_EHCI_ZYNQ # define DFU_DEFAULT_POLL_TIMEOUT 300 -- cgit v1.3.1 From 3a581af21af0bceb7e47650a19e3ddd3de87148a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:21 -0500 Subject: Convert CONFIG_FLASH_SPANSION_S29WS_N et al to Kconfig This converts the following to Kconfig: CONFIG_FLASH_SPANSION_S29WS_N CONFIG_FLASH_VERIFY CONFIG_FSL_FM_10GEC_REGULAR_NOTATION CONFIG_FSL_ISBC_KEY_EXT CONFIG_FSL_TRUST_ARCH_v1 CONFIG_FSL_SDHC_V2_3 CONFIG_MAX_DSP_CPUS CONFIG_MIU_2BIT_INTERLEAVED CONFIG_SERIAL_BOOT CONFIG_SPI_BOOTING CONFIG_X86EMU_RAW_IO Signed-off-by: Tom Rini --- README | 13 ------------- arch/Kconfig.nxp | 17 +++++++++++++++++ arch/arm/include/asm/fsl_secure_boot.h | 15 --------------- arch/arm/mach-exynos/Kconfig | 4 ++++ arch/powerpc/cpu/mpc85xx/Kconfig | 5 +++++ arch/powerpc/include/asm/config_mpc85xx.h | 7 ------- arch/powerpc/include/asm/fsl_secure_boot.h | 18 ------------------ board/freescale/common/fsl_validate.c | 18 +++++++++--------- board/google/Kconfig | 4 ++++ board/samsung/smdkv310/Kconfig | 3 +++ board/sysam/stmark2/Kconfig | 4 ++++ configs/M53017EVB_defconfig | 1 + configs/mccmon6_nor_defconfig | 1 + configs/mccmon6_sd_defconfig | 1 + doc/README.fsl-dpaa | 10 ---------- drivers/mmc/Kconfig | 5 +++++ drivers/mtd/Kconfig | 19 +++++++++++++++++++ drivers/net/Kconfig | 13 +++++++++++++ include/configs/M53017EVB.h | 1 - include/configs/conga-qeval20-qa3-e3845.h | 1 - include/configs/dfi-bt700.h | 1 - include/configs/exynos5-dt-common.h | 1 - include/configs/mccmon6.h | 1 - include/configs/minnowmax.h | 1 - include/configs/smdkv310.h | 3 --- include/configs/som-db5800-som-6867.h | 1 - include/configs/stmark2.h | 4 ---- include/configs/theadorable-x86-common.h | 1 - include/configs/x86-chromebook.h | 1 - 29 files changed, 86 insertions(+), 88 deletions(-) delete mode 100644 doc/README.fsl-dpaa (limited to 'include') diff --git a/README b/README index 05835207426..b833aca2e58 100644 --- a/README +++ b/README @@ -1477,19 +1477,6 @@ Configuration Settings: - CONFIG_SYS_FLASH_USE_BUFFER_WRITE Use buffered writes to flash. -- CONFIG_FLASH_SPANSION_S29WS_N - s29ws-n MirrorBit flash has non-standard addresses for buffered - write commands. - -- CONFIG_FLASH_VERIFY - If defined, the content of the flash (destination) is compared - against the source after the write operation. An error message - will be printed when the contents are not identical. - Please note that this option is useless in nearly all cases, - since such flash programming errors usually are detected earlier - while unprotecting/erasing/programming. Please only enable - this option if you really know what you are doing. - - CONFIG_ENV_FLAGS_LIST_DEFAULT - CONFIG_ENV_FLAGS_LIST_STATIC Enable validation of the values given to environment variables when diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index 805fe934a1f..ad61dabb31b 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -1,5 +1,10 @@ +config FSL_TRUST_ARCH_v1 + bool + config NXP_ESBC bool "NXP ESBC (secure boot) functionality" + select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \ + ARCH_P5040 || ARCH_P2041 help Enable Freescale Secure Boot feature. Normally selected by defconfig. If unsure, do not change. @@ -10,6 +15,7 @@ menu "Chain of trust / secure boot options" config CHAIN_OF_TRUST select FSL_CAAM select ARCH_MISC_INIT + select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT select FSL_SEC_MON select SPL_BOARD_INIT if (ARM && SPL) select SPL_HASH if (ARM && SPL) @@ -41,6 +47,17 @@ config ESBC_ADDR_64BIT help For Layerscape based platforms, ESBC image Address in Header is 64bit. +config FSL_ISBC_KEY_EXT + bool + help + The key used for verification of next level images is picked up from + an Extension Table which has been verified by the ISBC (Internal + Secure boot Code) in boot ROM of the SoC. The feature is only + applicable in case of NOR boot and is not applicable in case of + RAMBOOT (NAND, SD, SPI). For Layerscape, this feature is available + for all device if IE Table is copied to XIP memory Also, for + Layerscape, ISBC doesn't verify this table. + config SYS_FSL_SFP_BE def_bool y depends on PPC || FSL_LSCH2 || ARCH_LS1021A diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index a4f4961fc87..6a9d198cb81 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -9,21 +9,6 @@ #ifdef CONFIG_CHAIN_OF_TRUST #ifndef CONFIG_SPL_BUILD -#ifndef CONFIG_SYS_RAMBOOT -/* The key used for verification of next level images - * is picked up from an Extension Table which has - * been verified by the ISBC (Internal Secure boot Code) - * in boot ROM of the SoC. - * The feature is only applicable in case of NOR boot and is - * not applicable in case of RAMBOOT (NAND, SD, SPI). - * For LS, this feature is available for all device if IE Table - * is copied to XIP memory - * Also, for LS, ISBC doesn't verify this table. - */ -#define CONFIG_FSL_ISBC_KEY_EXT - -#endif - #ifdef CONFIG_FSL_LS_PPA /* Define the key hash here if SRK used for signing PPA image is * different from SRK hash put in SFP used for U-Boot. diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 383af83066e..8f3aee052c8 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -4,6 +4,9 @@ config BOARD_COMMON def_bool y depends on !TARGET_SMDKV310 && !TARGET_ARNDALE +config SPI_BOOTING + bool + config USB_BOOTING bool @@ -27,6 +30,7 @@ config ARCH_EXYNOS5 select BOARD_EARLY_INIT_F select CPU_V7A select SHA_HW_ACCEL + select SPI_BOOTING if EXYNOS5_DT select USB_BOOTING imply CMD_HASH imply CRC32_VERIFY diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index f2361560e9a..721dafc5ab1 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1324,6 +1324,11 @@ config SYS_ULB_CLK config SYS_ETVPE_CLK int default 1 + +config MAX_DSP_CPUS + int + default 12 if ARCH_B4860 + default 2 if ARCH_B4420 endif config SYS_L2_SIZE_256KB diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 1b5b4947f1a..edaf8baaaeb 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -23,7 +23,6 @@ #define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_ARCH_P1010) -#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #elif defined(CONFIG_ARCH_P1021) @@ -93,11 +92,9 @@ #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_BSC9131) -#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #elif defined(CONFIG_ARCH_BSC9132) -#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #elif defined(CONFIG_ARCH_T4240) @@ -136,7 +133,6 @@ #define CFG_SYS_FM_MURAM_SIZE 0x60000 #ifdef CONFIG_ARCH_B4860 -#define CONFIG_MAX_DSP_CPUS 12 #define CONFIG_NUM_DSP_CPUS 6 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CFG_SYS_NUM_FM1_DTSEC 6 @@ -145,7 +141,6 @@ #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #else -#define CONFIG_MAX_DSP_CPUS 2 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } #define CFG_SYS_NUM_FM1_DTSEC 4 #define CFG_SYS_NUM_FM1_10GEC 0 @@ -173,7 +168,6 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 4 #define CFG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CFG_SYS_FM1_CLK 0 #define CONFIG_QBMAN_CLK_DIV 1 @@ -204,7 +198,6 @@ #elif defined(CONFIG_ARCH_C29X) -#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000 diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index e8b26802062..09f37ec3e49 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -35,24 +35,6 @@ #define CFG_SYS_INIT_L3_ADDR 0xbff00000 #endif #endif - -#if defined(CONFIG_ARCH_P3041) || \ - defined(CONFIG_ARCH_P4080) || \ - defined(CONFIG_ARCH_P5040) || \ - defined(CONFIG_ARCH_P2041) - #define CONFIG_FSL_TRUST_ARCH_v1 -#endif - -#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT) -/* The key used for verification of next level images - * is picked up from an Extension Table which has - * been verified by the ISBC (Internal Secure boot Code) - * in boot ROM of the SoC. - * The feature is only applicable in case of NOR boot and is - * not applicable in case of RAMBOOT (NAND, SD, SPI). - */ -#define CONFIG_FSL_ISBC_KEY_EXT -#endif #endif /* #ifdef CONFIG_NXP_ESBC */ #ifdef CONFIG_CHAIN_OF_TRUST diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 285ed9afcc9..bfe6357b0d6 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -29,7 +29,7 @@ #define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \ ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \ ((key_len) == 2 * KEY_SIZE_BYTES)) -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) /* Global data structure */ static struct fsl_secboot_glb glb; #endif @@ -63,7 +63,7 @@ self: goto self; } -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) static u32 check_ie(struct fsl_secboot_img_priv *img) { if (img->hdr.ie_flag & IE_FLAG_MASK) @@ -188,7 +188,7 @@ static u32 check_srk(struct fsl_secboot_img_priv *img) { #ifdef CONFIG_ESBC_HDR_LS /* In LS, No SRK Flag as SRK is always present if IE not present*/ -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) return !check_ie(img); #endif return 1; @@ -278,7 +278,7 @@ static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) } #endif /* CONFIG_ESBC_HDR_LS */ -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) static void install_ie_tbl(uintptr_t ie_tbl_addr, struct fsl_secboot_img_priv *img) @@ -434,7 +434,7 @@ void fsl_secboot_handle_error(int error) case ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM: case ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN: #endif -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) /*@fallthrough@*/ case ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED: case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY: @@ -571,7 +571,7 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) key_hash = 1; } #endif -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) if (!key_hash && check_ie(img)) key_hash = 1; #endif @@ -705,7 +705,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) } #endif -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) if (!key_found && check_ie(img)) { ret = read_validate_ie_tbl(img); if (ret != 0) @@ -851,7 +851,7 @@ static int secboot_init(struct fsl_secboot_img_priv **img_ptr) return -ENOMEM; memset(img, 0, sizeof(struct fsl_secboot_img_priv)); -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) if (glb.ie_addr) img->ie_addr = glb.ie_addr; #endif @@ -952,7 +952,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, else ret = memcmp(srk_hash, img->img_key_hash, SHA256_BYTES); -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) if (!hash_cmd && check_ie(img)) ret = 0; #endif diff --git a/board/google/Kconfig b/board/google/Kconfig index c57e518c33f..0474b4e6938 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -6,6 +6,10 @@ if VENDOR_GOOGLE config BIOSEMU bool + select X86EMU_RAW_IO + +config X86EMU_RAW_IO + bool choice prompt "Mainboard model" diff --git a/board/samsung/smdkv310/Kconfig b/board/samsung/smdkv310/Kconfig index a6fd657697e..cf5ac170743 100644 --- a/board/samsung/smdkv310/Kconfig +++ b/board/samsung/smdkv310/Kconfig @@ -1,5 +1,8 @@ if TARGET_SMDKV310 +config MIU_2BIT_INTERLEAVED + def_bool y + config SYS_BOARD default "smdkv310" diff --git a/board/sysam/stmark2/Kconfig b/board/sysam/stmark2/Kconfig index 49d02744a9a..b2595059c68 100644 --- a/board/sysam/stmark2/Kconfig +++ b/board/sysam/stmark2/Kconfig @@ -6,6 +6,10 @@ config CF_SBF config EXTRA_CLOCK def_bool y +config SERIAL_BOOT + def_bool y + depends on CF_SBF + config SYS_INPUT_CLKSRC hex default 30000000 diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index 8158cd4e84e..b6783ab95ba 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -41,6 +41,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_SPANSION_S29WS_N=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=137 diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig index 5f8a2873733..1e6cec01213 100644 --- a/configs/mccmon6_nor_defconfig +++ b/configs/mccmon6_nor_defconfig @@ -69,6 +69,7 @@ CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_FLASH_VERIFY=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig index 651eef5d06f..20b6e03bdfd 100644 --- a/configs/mccmon6_sd_defconfig +++ b/configs/mccmon6_sd_defconfig @@ -67,6 +67,7 @@ CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_FLASH_VERIFY=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SPANSION=y diff --git a/doc/README.fsl-dpaa b/doc/README.fsl-dpaa deleted file mode 100644 index 3ef5eeb32e1..00000000000 --- a/doc/README.fsl-dpaa +++ /dev/null @@ -1,10 +0,0 @@ -This file documents Freescale DPAA-specific options. - -FMan (Frame Manager) - - CONFIG_FSL_FM_10GEC_REGULAR_NOTATION - on SoCs T4240, T2080, LS1043A, etc, the notation between 10GEC and MAC as below: - 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 - on SoCs T1024, etc, the notation between 10GEC and MAC as below: - 10GEC1->MAC1, 10GEC2->MAC2 - so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on - which 10GEC enumeration is consistent with MAC enumeration. diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 698c91c57f4..5a5a31c75ab 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -825,8 +825,13 @@ config MMC_MTK endif +config FSL_SDHC_V2_3 + bool + config FSL_ESDHC bool "Freescale/NXP eSDHC controller support" + select FSL_SDHC_V2_3 if ARCH_P1010 || ARCH_BSC9131 || ARCH_BSC9132 \ + || ARCH_C29X help This selects support for the eSDHC (Enhanced Secure Digital Host Controller) found on numerous Freescale/NXP SoCs. diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 04ae45665e4..af45ef00dae 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -119,6 +119,13 @@ config SYS_FLASH_EMPTY_INFO bool "Enable displaying empty sectors in flash info" depends on FLASH_CFI_DRIVER +config FLASH_SPANSION_S29WS_N + bool "Non-standard s29ws-n MirrorBit flash" + depends on FLASH_CFI_DRIVER + help + Enable this if the s29ws-n MirrorBit flash has non-standard addresses + for buffered write commands. + config FLASH_CFI_MTD bool "Enable CFI MTD driver" depends on FLASH_CFI_DRIVER @@ -156,6 +163,18 @@ config SYS_FLASH_CHECKSUM If the variable flashchecksum is set in the environment, perform a CRC of the flash and print the value to console. +config FLASH_VERIFY + bool "Compare writes to NOR flash with source location" + depends on MTD_NOR_FLASH + help + If enabled, the content of the flash (destination) is compared + against the source after the write operation. An error message will + be printed when the contents are not identical. Please note that + this option is useless in nearly all cases, since such flash + programming errors usually are detected earlier while + unprotecting/erasing/programming. Please only enable this option if + you really know what you are doing. + config ALTERA_QSPI bool "Altera Generic Quad SPI Controller" depends on DM_MTD diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 0607f959da4..53fb69f5260 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -372,6 +372,7 @@ config FMAN_ENET select SYS_FMAN_V3 if ARCH_B4420 || ARCH_B4860 || ARCH_LS1043A || \ ARCH_LS1046A || ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || \ ARCH_T2080 || ARCH_T4240 + select FSL_FM_10GEC_REGULAR_NOTATION if ARCH_T1024 help This driver support the Freescale FMan Ethernet controller @@ -391,6 +392,18 @@ config SYS_FMAN_V3 help SoC has FMan v3 with mEMAC +config FSL_FM_10GEC_REGULAR_NOTATION + bool + help + On SoCs T4240, T2080, LS1043A, etc, the notation between 10GEC and + MAC as below: + 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 + While on SoCs T1024, etc, the notation between 10GEC and MAC as below: + 10GEC1->MAC1, 10GEC2->MAC2 + so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the + new SoCs on which 10GEC enumeration is consistent with MAC + enumeration. + config FTMAC100 bool "Ftmac100 Ethernet Support" help diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 42b74aeb9b5..439ed93a237 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -93,7 +93,6 @@ * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_FLASH_SPANSION_S29WS_N 1 # define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ #endif diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h index 823d37fc38c..e9b85b4e1c7 100644 --- a/include/configs/conga-qeval20-qa3-e3845.h +++ b/include/configs/conga-qeval20-qa3-e3845.h @@ -17,7 +17,6 @@ "stderr=serial\0" #define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index 52f2d50118a..154c4f4f13f 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -21,7 +21,6 @@ "stderr=serial\0" #define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index c9e0c13172c..8f2dac61cba 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -17,6 +17,5 @@ #define CFG_SYS_SPI_BASE 0x12D30000 #define FLASH_SIZE (4 << 20) -#define CONFIG_SPI_BOOTING #endif diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 7c401a2cfd6..a7f55076926 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -25,7 +25,6 @@ /* NOR 16-bit mode */ #define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR -#define CONFIG_FLASH_VERIFY /* NOR Flash MTD */ #define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) } diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 50c52f8839b..6c15c72efda 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -18,6 +18,5 @@ "usb_pgood_delay=40\0" #define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO #endif /* __CONFIG_H */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index af0c8200fc2..601c16ea453 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -34,9 +34,6 @@ /* FLASH and environment organization */ -/* MIU (Memory Interleaving Unit) */ -#define CONFIG_MIU_2BIT_INTERLEAVED - #define RESERVE_BLOCK_SIZE (512) #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h index ee038d83bc0..f0970921367 100644 --- a/include/configs/som-db5800-som-6867.h +++ b/include/configs/som-db5800-som-6867.h @@ -17,6 +17,5 @@ "stderr=serial,vidconsole\0" #define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO #endif /* __CONFIG_H */ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index faff8d6ed6d..f81cef0a2c4 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -63,10 +63,6 @@ #define CFG_SYS_DRAM_TEST -#if defined(CONFIG_CF_SBF) -#define CONFIG_SERIAL_BOOT -#endif - /* Reserve 256 kB for Monitor */ /* diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h index af0a095dfc8..b57b1beaafe 100644 --- a/include/configs/theadorable-x86-common.h +++ b/include/configs/theadorable-x86-common.h @@ -16,7 +16,6 @@ "stderr=serial\0" #define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO /* Environment settings */ diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index ec87eddd4c7..9df3bfd527f 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -11,7 +11,6 @@ #define CONFIG_X86_REFCODE_RUN_ADDR 0 #define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ "stdout=vidconsole,serial\0" \ -- cgit v1.3.1 From 5388aa28511c75be387f6bfe868e03fa7505792a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:22 -0500 Subject: Convert CONFIG_FSL_ESDHC_PIN_MUX to Kconfig This converts the following to Kconfig: CONFIG_FSL_ESDHC_PIN_MUX Signed-off-by: Tom Rini --- configs/MPC837XERDB_defconfig | 1 + drivers/mmc/Kconfig | 4 ++++ drivers/mmc/fsl_esdhc_imx.c | 2 +- include/configs/MPC837XERDB.h | 1 - 4 files changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 40fc1d1da4a..a227ca86de7 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -195,6 +195,7 @@ CONFIG_SYS_FSL_I2C_OFFSET=0x3000 CONFIG_SYS_I2C_SLAVE=0x7F CONFIG_SYS_I2C_SPEED=400000 CONFIG_FSL_ESDHC=y +CONFIG_FSL_ESDHC_PIN_MUX=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_FLASH_SHOW_PROGRESS=0 diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 5a5a31c75ab..878f867c627 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -891,6 +891,10 @@ config FSL_USDHC help This enables the Ultra Secured Digital Host Controller enhancements +config FSL_ESDHC_PIN_MUX + bool "Perform esdhc device-tree fixup" + depends on (FSL_ESDHC || FSL_ESDHC_IMX) && OF_LIBFDT + endmenu config SYS_FSL_ERRATUM_ESDHC111 diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 5ee3ce78231..66caf683f74 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1360,7 +1360,7 @@ int fsl_esdhc_mmc_init(struct bd_info *bis) #if CONFIG_IS_ENABLED(OF_LIBFDT) __weak int esdhc_status_fixup(void *blob, const char *compat) { - if (IS_ENABLED(FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) { + if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) { do_fixup_by_compat(blob, compat, "status", "disabled", sizeof("disabled"), 1); return 1; diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index f312ffb37e2..dbfcdfb738b 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -177,7 +177,6 @@ #define CFG_SYS_PCIE2_IO_PHYS 0xD8000000 #ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC_PIN_MUX #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR #endif -- cgit v1.3.1 From b95de034c51bfeabde26e8ca6a11f25e91f2405b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:25 -0500 Subject: meson64: Fix missing CFG_SYS_BAUDRATE_TABLE migration CONFIG_SYS_BAUDRATE_TABLE has already been migrated to CFG_SYS but this instance was missed, correct. Signed-off-by: Tom Rini --- include/configs/meson64.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 6331b7615db..a22f7a81b00 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -18,7 +18,7 @@ /* Serial drivers */ /* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, \ 230400, 250000, 460800, 500000, 1000000, 2000000, 4000000, \ 8000000 } -- cgit v1.3.1 From 3f7a4965319920d0d029318399bbc0fe51ab0c08 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:26 -0500 Subject: Convert CONFIG_POWER_PCA9450 to Kconfig This converts the following to Kconfig: CONFIG_POWER_PCA9450 Signed-off-by: Tom Rini --- configs/imx8mp-icore-mx8mp-edimm2.2_defconfig | 1 + configs/imx8mp_evk_defconfig | 1 + configs/phycore-imx8mp_defconfig | 1 + configs/verdin-imx8mp_defconfig | 1 + drivers/power/pmic/Kconfig | 3 +++ include/configs/imx8mp_evk.h | 8 -------- include/configs/imx8mp_icore_mx8mp.h | 7 ------- include/configs/phycore_imx8mp.h | 6 ------ include/configs/verdin-imx8mp.h | 3 --- 9 files changed, 7 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig index f679fbe2514..e3588473d59 100644 --- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig +++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig @@ -99,6 +99,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 91ec39d0237..10802eb9619 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -99,6 +99,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 248631b7a8f..82e4f1ed970 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -107,6 +107,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index bae8179bfde..153c7c15197 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -143,6 +143,7 @@ CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_POWER_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index d94048db5f7..176fb07c651 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -416,6 +416,9 @@ config POWER_HI6553 config POWER_LTC3676 bool "Enable legacy driver for LTC3676 PMIC" +config POWER_PCA9450 + bool "Enable legacy driver for PCA9450 PMIC" + config POWER_PFUZE100 bool "Enable legacy driver for PFUZE100 PMIC" diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 738677ff37c..137bd3b0952 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -12,14 +12,6 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ - - -#define CONFIG_POWER_PCA9450 - -#endif - #if defined(CONFIG_CMD_NET) #define CONFIG_FEC_MXC_PHYADDR 1 diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index d67bad8971d..b261a81e44a 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -13,13 +13,6 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ - -#define CONFIG_POWER_PCA9450 - -#endif - #if defined(CONFIG_CMD_NET) #define CONFIG_FEC_MXC_PHYADDR 1 diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 11a833bb127..7a38382034a 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -13,12 +13,6 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD - -#define CONFIG_POWER_PCA9450 - -#endif - #define CONFIG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ "console=ttymxc0,115200\0" \ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 88839a6e561..22dc364223c 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -19,9 +19,6 @@ #define CONFIG_MALLOC_F_ADDR 0x184000 /* For RAW image gives a error info not panic */ -#define CONFIG_POWER_PCA9450 - -#define CONFIG_SYS_I2C #endif /* CONFIG_SPL_BUILD */ #define MEM_LAYOUT_ENV_SETTINGS \ -- cgit v1.3.1 From 54f80dd2908af0b851816cf062edf2d454948397 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:27 -0500 Subject: Convert CONFIG_HOSTNAME et al to Kconfig This converts the following to Kconfig: CONFIG_GATEWAYIP CONFIG_HOSTNAME CONFIG_IPADDR CONFIG_NETMASK CONFIG_ROOTPATH CONFIG_SERVERIP CONFIG_UBOOTPATH To do this, we introduce a CONFIG_USE_ form of each of the above and change include/env_default.h to test for that to be set before setting a value. Further, we don't want to stringify the IP address related values as they are now properly strings via Kconfig. Signed-off-by: Tom Rini --- README | 32 ------------- arch/powerpc/Kconfig | 12 +++++ configs/M5208EVBE_defconfig | 10 +++++ configs/M5235EVB_Flash32_defconfig | 10 +++++ configs/M5235EVB_defconfig | 10 +++++ configs/M5253DEMO_defconfig | 2 + configs/M5272C3_defconfig | 10 +++++ configs/M5282EVB_defconfig | 10 +++++ configs/M53017EVB_defconfig | 10 +++++ configs/M5329AFEE_defconfig | 10 +++++ configs/M5329BFEE_defconfig | 10 +++++ configs/M5373EVB_defconfig | 10 +++++ configs/MCR3000_defconfig | 6 +++ configs/MPC837XERDB_defconfig | 5 +++ configs/MPC8548CDS_36BIT_defconfig | 13 ++++++ configs/MPC8548CDS_defconfig | 13 ++++++ configs/MPC8548CDS_legacy_defconfig | 13 ++++++ configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PA_NAND_defconfig | 2 + configs/P1010RDB-PA_NOR_defconfig | 2 + configs/P1010RDB-PA_SDCARD_defconfig | 2 + configs/P1010RDB-PA_SPIFLASH_defconfig | 2 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PB_NAND_defconfig | 2 + configs/P1010RDB-PB_NOR_defconfig | 2 + configs/P1010RDB-PB_SDCARD_defconfig | 2 + configs/P1010RDB-PB_SPIFLASH_defconfig | 2 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 ++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 3 ++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 ++ configs/P1020RDB-PC_36BIT_defconfig | 3 ++ configs/P1020RDB-PC_NAND_defconfig | 3 ++ configs/P1020RDB-PC_SDCARD_defconfig | 3 ++ configs/P1020RDB-PC_SPIFLASH_defconfig | 3 ++ configs/P1020RDB-PC_defconfig | 3 ++ configs/P1020RDB-PD_NAND_defconfig | 3 ++ configs/P1020RDB-PD_SDCARD_defconfig | 3 ++ configs/P1020RDB-PD_SPIFLASH_defconfig | 3 ++ configs/P1020RDB-PD_defconfig | 3 ++ configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 ++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 ++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 ++ configs/P2020RDB-PC_36BIT_defconfig | 3 ++ configs/P2020RDB-PC_NAND_defconfig | 3 ++ configs/P2020RDB-PC_SDCARD_defconfig | 3 ++ configs/P2020RDB-PC_SPIFLASH_defconfig | 3 ++ configs/P2020RDB-PC_defconfig | 3 ++ configs/P2041RDB_NAND_defconfig | 2 + configs/P2041RDB_SDCARD_defconfig | 2 + configs/P2041RDB_SPIFLASH_defconfig | 2 + configs/P2041RDB_defconfig | 2 + configs/T1024RDB_NAND_defconfig | 2 + configs/T1024RDB_SDCARD_defconfig | 2 + configs/T1024RDB_SPIFLASH_defconfig | 2 + configs/T1024RDB_defconfig | 2 + configs/T1042D4RDB_NAND_defconfig | 2 + configs/T1042D4RDB_SDCARD_defconfig | 2 + configs/T1042D4RDB_SPIFLASH_defconfig | 2 + configs/T1042D4RDB_defconfig | 2 + configs/T2080QDS_NAND_defconfig | 2 + configs/T2080QDS_SDCARD_defconfig | 2 + configs/T2080QDS_SECURE_BOOT_defconfig | 2 + configs/T2080QDS_SPIFLASH_defconfig | 2 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 + configs/T2080QDS_defconfig | 2 + configs/T2080RDB_NAND_defconfig | 2 + configs/T2080RDB_SDCARD_defconfig | 2 + configs/T2080RDB_SPIFLASH_defconfig | 2 + configs/T2080RDB_defconfig | 2 + configs/T2080RDB_revD_NAND_defconfig | 2 + configs/T2080RDB_revD_SDCARD_defconfig | 2 + configs/T2080RDB_revD_SPIFLASH_defconfig | 2 + configs/T2080RDB_revD_defconfig | 2 + configs/T4240RDB_SDCARD_defconfig | 2 + configs/T4240RDB_defconfig | 2 + configs/amcore_defconfig | 2 + configs/apalis-imx8_defconfig | 6 +++ configs/apalis-tk1_defconfig | 6 +++ configs/apalis_imx6_defconfig | 6 +++ configs/aristainetos2c_defconfig | 2 + configs/aristainetos2ccslb_defconfig | 2 + configs/bayleybay_defconfig | 1 + configs/bcm_ns3_defconfig | 2 + configs/cherryhill_defconfig | 1 + configs/chromebook_coral_defconfig | 1 + configs/chromebook_link64_defconfig | 1 + configs/chromebook_link_defconfig | 1 + configs/chromebook_samus_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + configs/cobra5272_defconfig | 4 ++ configs/colibri-imx6ull-emmc_defconfig | 6 +++ configs/colibri-imx6ull_defconfig | 6 +++ configs/colibri-imx8x_defconfig | 6 +++ configs/colibri_imx6_defconfig | 6 +++ configs/colibri_imx7_defconfig | 6 +++ configs/colibri_imx7_emmc_defconfig | 6 +++ configs/colibri_vf_defconfig | 6 +++ ...conga-qeval20-qa3-e3845-internal-uart_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/controlcenterdc_defconfig | 3 ++ configs/coreboot64_defconfig | 1 + configs/coreboot_defconfig | 1 + configs/cougarcanyon2_defconfig | 1 + configs/crownbay_defconfig | 1 + configs/dfi-bt700-q7x-151_defconfig | 1 + configs/draco_defconfig | 2 + configs/efi-x86_app32_defconfig | 1 + configs/efi-x86_app64_defconfig | 1 + configs/efi-x86_payload32_defconfig | 1 + configs/efi-x86_payload64_defconfig | 1 + configs/etamin_defconfig | 2 + configs/galileo_defconfig | 1 + configs/gazerbeam_defconfig | 3 ++ configs/gwventana_emmc_defconfig | 4 ++ configs/gwventana_gw5904_defconfig | 4 ++ configs/gwventana_nand_defconfig | 4 ++ configs/imx28_xea_defconfig | 2 + configs/imx28_xea_sb_defconfig | 2 + configs/integratorcp_cm1136_defconfig | 4 ++ configs/integratorcp_cm920t_defconfig | 4 ++ configs/integratorcp_cm926ejs_defconfig | 4 ++ configs/integratorcp_cm946es_defconfig | 4 ++ configs/kontron-sl-mx6ul_defconfig | 2 + configs/kontron-sl-mx8mm_defconfig | 2 + configs/m53menlo_defconfig | 2 + configs/microblaze-generic_defconfig | 2 + configs/minnowmax_defconfig | 1 + configs/mt7622_rfb_defconfig | 4 ++ configs/mt7623a_unielec_u7623_02_defconfig | 4 ++ configs/mt7623n_bpir2_defconfig | 4 ++ configs/mt7629_rfb_defconfig | 4 ++ configs/mvebu_ac5_rd_defconfig | 10 +++++ configs/novena_defconfig | 2 + configs/opos6uldev_defconfig | 2 + configs/pg_wcom_expu1_defconfig | 2 + configs/pg_wcom_expu1_update_defconfig | 2 + configs/pg_wcom_seli8_defconfig | 2 + configs/pg_wcom_seli8_update_defconfig | 2 + configs/poleg_evb_defconfig | 6 +++ configs/pxm2_defconfig | 2 + configs/qemu-ppce500_defconfig | 2 + configs/qemu-x86_64_defconfig | 1 + configs/qemu-x86_defconfig | 1 + configs/rastaban_defconfig | 2 + configs/rut_defconfig | 2 + configs/seeed_npi_imx6ull_defconfig | 2 + configs/slimbootloader_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 2 + configs/som-db5800-som-6867_defconfig | 1 + configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig | 2 + .../stm32mp15-icore-stm32mp1-edimm2.2_defconfig | 2 + ...2mp15-microgea-stm32mp1-microdev2-of7_defconfig | 2 + ...stm32mp15-microgea-stm32mp1-microdev2_defconfig | 2 + configs/stm32mp15_basic_defconfig | 2 + configs/stm32mp15_defconfig | 2 + configs/stm32mp15_dhcom_basic_defconfig | 2 + configs/stm32mp15_dhcor_basic_defconfig | 2 + configs/stm32mp15_trusted_defconfig | 2 + configs/stmark2_defconfig | 2 + ...eadorable-x86-conga-qa3-e3845-pcie-x4_defconfig | 1 + configs/theadorable-x86-conga-qa3-e3845_defconfig | 1 + configs/theadorable-x86-dfi-bt700_defconfig | 1 + configs/thuban_defconfig | 2 + configs/uniphier_ld4_sld8_defconfig | 10 +++++ configs/uniphier_v7_defconfig | 10 +++++ configs/uniphier_v8_defconfig | 10 +++++ configs/usbarmory_defconfig | 2 + env/Kconfig | 10 +++++ include/configs/M5208EVBE.h | 8 ---- include/configs/M5235EVB.h | 9 +--- include/configs/M5253DEMO.h | 2 - include/configs/M5272C3.h | 8 ---- include/configs/M5282EVB.h | 8 ---- include/configs/M53017EVB.h | 8 ---- include/configs/M5329EVB.h | 8 ---- include/configs/M5373EVB.h | 8 ---- include/configs/MCR3000.h | 4 -- include/configs/MPC837XERDB.h | 4 -- include/configs/MPC8548CDS.h | 12 +---- include/configs/P1010RDB.h | 5 +-- include/configs/P2041RDB.h | 4 +- include/configs/T102xRDB.h | 4 +- include/configs/T104xRDB.h | 4 +- include/configs/T208xQDS.h | 4 +- include/configs/T208xRDB.h | 4 +- include/configs/T4240RDB.h | 4 +- include/configs/amcore.h | 2 - include/configs/apalis-imx8.h | 3 -- include/configs/apalis-tk1.h | 6 --- include/configs/apalis_imx6.h | 6 --- include/configs/aristainetos2.h | 2 - include/configs/bcm_ns3.h | 2 - include/configs/cobra5272.h | 3 -- include/configs/colibri-imx6ull.h | 4 -- include/configs/colibri-imx8x.h | 4 -- include/configs/colibri_imx6.h | 6 --- include/configs/colibri_imx7.h | 4 -- include/configs/colibri_vf.h | 4 -- include/configs/controlcenterdc.h | 3 -- include/configs/gazerbeam.h | 4 -- include/configs/gw_ventana.h | 2 - include/configs/integratorcp.h | 3 -- include/configs/kontron-sl-mx6ul.h | 1 - include/configs/kontron-sl-mx8mm.h | 1 - include/configs/m53menlo.h | 1 - include/configs/microblaze-generic.h | 2 - include/configs/mt7622.h | 2 - include/configs/mt7623.h | 2 - include/configs/mt7629.h | 2 - include/configs/mvebu_alleycat-5.h | 5 --- include/configs/novena.h | 1 - include/configs/npi_imx6ull.h | 2 - include/configs/opos6uldev.h | 2 - include/configs/p1_p2_rdb_pc.h | 5 +-- include/configs/poleg.h | 3 -- include/configs/qemu-ppce500.h | 2 - include/configs/siemens-am33x-common.h | 2 - include/configs/socfpga_vining_fpga.h | 1 - include/configs/stm32mp15_common.h | 3 -- include/configs/stmark2.h | 2 - include/configs/uniphier.h | 6 --- include/configs/usbarmory.h | 1 - include/configs/x86-common.h | 2 - include/configs/xea.h | 1 - include/env_default.h | 22 ++++----- net/Kconfig | 52 ++++++++++++++++++++++ 232 files changed, 644 insertions(+), 248 deletions(-) (limited to 'include') diff --git a/README b/README index b833aca2e58..c0f55b2586c 100644 --- a/README +++ b/README @@ -734,38 +734,6 @@ The following options need to be configured: Some PHY like Intel LXT971A need extra delay after command issued before MII status register can be read -- IP address: - CONFIG_IPADDR - - Define a default value for the IP address to use for - the default Ethernet interface, in case this is not - determined through e.g. bootp. - (Environment variable "ipaddr") - -- Server IP address: - CONFIG_SERVERIP - - Defines a default value for the IP address of a TFTP - server to contact when using the "tftboot" command. - (Environment variable "serverip") - -- Gateway IP address: - CONFIG_GATEWAYIP - - Defines a default value for the IP address of the - default router where packets to other networks are - sent to. - (Environment variable "gatewayip") - -- Subnet mask: - CONFIG_NETMASK - - Defines a default value for the subnet mask (or - routing prefix) which is used to determine if an IP - address belongs to the local subnet or needs to be - forwarded through a router. - (Environment variable "netmask") - - BOOTP Recovery Mode: CONFIG_BOOTP_RANDOM_DELAY diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 0fc4ceda000..e0801c25941 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -68,4 +68,16 @@ source "arch/powerpc/cpu/mpc85xx/Kconfig" source "arch/powerpc/cpu/mpc8xx/Kconfig" source "arch/powerpc/lib/Kconfig" +config USE_UBOOTPATH + bool "Set a default 'uboot' value in the environment" + help + Many default environment scripts will check the "uboot" variable + to determine the name of the file to load via tftp that will then + be written to flash. + +config UBOOTPATH + string "Value of the default 'uboot' value in the environment" + depends on USE_UBOOTPATH + default "u-boot.bin" + endmenu diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index 20250c02a11..263e57f46a0 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -26,8 +26,18 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5208EVBe" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_UDP_CHECKSUM=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index 38c5076d5f8..88c11162111 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -34,7 +34,17 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="u-boot.bin" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5235EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index cb5bcb7221c..255f3b9d2f1 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -34,7 +34,17 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="u-boot.bin" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5235EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index 2684ce05f26..4de6290b7d3 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -26,6 +26,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MAC_PARTITION=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5253DEMO" # CONFIG_BLOCK_CACHE is not set CONFIG_SYS_IDE_MAXBUS=1 CONFIG_SYS_ATA_STRIDE=4 diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index f2d70a4e269..324daa016ef 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -27,7 +27,17 @@ CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5272C3" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFFE00201 diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index 0ef2e7b4ffe..7988d250034 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -27,7 +27,17 @@ CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5282EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index b6783ab95ba..d7c07aa2ea9 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -28,8 +28,18 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_ENV_IS_IN_FLASH=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M53017" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_UDP_CHECKSUM=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index 6fede625fb8..989af925f74 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -27,8 +27,18 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5329EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_UDP_CHECKSUM=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index fe70245497c..7be2a27ba2b 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -28,8 +28,18 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5329EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_UDP_CHECKSUM=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index b074cf520ff..4b278a5b1c8 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -28,8 +28,18 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5373EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_UDP_CHECKSUM=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index 7d54807e645..3e16ffc2ef2 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -55,6 +55,12 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.0.3" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.0.0.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.0.1" CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0x4000801 CONFIG_SYS_OR0_PRELIM=0xFFC00926 diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index a227ca86de7..7287ca6b247 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -148,6 +148,7 @@ CONFIG_SPCR_TSECEP_3=y CONFIG_LCRR_DBYP_PLL_BYPASSED=y CONFIG_LCRR_CLKDIV_8=y CONFIG_FSL_SERDES=y +CONFIG_USE_UBOOTPATH=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -178,6 +179,10 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="TSEC0" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="mpc837x_rdb" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/nfsroot" CONFIG_FSL_SATA=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index c6f5d87bb95..241cb80fde9 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -14,6 +14,8 @@ CONFIG_SRIO1=y CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_USE_UBOOTPATH=y +CONFIG_UBOOTPATH="8548cds/u-boot.bin" CONFIG_PCIE1=y CONFIG_PHYS_64BIT=y CONFIG_SYS_MONITOR_LEN=524288 @@ -45,6 +47,17 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC0" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.168.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.253" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/nfsroot" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_SPD_EEPROM=y CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index b6ebac39805..5af056bd4f4 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -14,6 +14,8 @@ CONFIG_SRIO1=y CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_USE_UBOOTPATH=y +CONFIG_UBOOTPATH="8548cds/u-boot.bin" CONFIG_PCIE1=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_OF_BOARD_SETUP=y @@ -44,6 +46,17 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC0" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.168.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.253" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/nfsroot" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_SPD_EEPROM=y CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index d272ede8d4a..34d1938129f 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -15,6 +15,8 @@ CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_TARGET_MPC8548CDS_LEGACY=y +CONFIG_USE_UBOOTPATH=y +CONFIG_UBOOTPATH="8548cds/u-boot.bin" CONFIG_PCIE1=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_OF_BOARD_SETUP=y @@ -44,6 +46,17 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC0" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.168.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.253" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/nfsroot" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_SPD_EEPROM=y CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index b32837c778c..3fb993e201c 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -81,6 +82,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 575d5bffcb2..dc6dd717df9 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -11,6 +11,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -49,6 +50,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 21c752d9747..bc29526f636 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -71,6 +72,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index a514d4ba36d..5c42d5ee367 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -73,6 +74,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index db71e9bce4e..b6e68d27885 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -80,6 +81,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 291c4a40380..fe24faa1757 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -11,6 +11,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -48,6 +49,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 8237da39c27..110a9b4ad3d 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -70,6 +71,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index 9cb53d64e23..fcd60f7a4ef 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -72,6 +73,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 95746971087..76919c3881f 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -82,6 +83,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 7b3919dc162..b2972586946 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -11,6 +11,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -50,6 +51,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 3ad137dbd56..df80488cff1 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -72,6 +73,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index cde657ce007..d27ea17a0b6 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -74,6 +75,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 1faeab2c3b3..88de4f9b92e 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -81,6 +82,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 190d02fa504..2e86aec5958 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -11,6 +11,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -49,6 +50,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 5e32768c28d..d5bbd6dca54 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -71,6 +72,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index bce763c73bf..66efe739e99 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -73,6 +74,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index b9d52a755da..0f082f6e6e2 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -81,6 +82,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index f86bc553da4..88e10af29a3 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -72,6 +73,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 0b9e108ba58..729e93eae23 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -74,6 +75,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 9f68ede4bef..2860c286d71 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -51,6 +52,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 3dd2475643d..0958a0a94b5 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -80,6 +81,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index bd64dcc9ef4..81bb26cb8fd 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -71,6 +72,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 140d271a197..481009f3076 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -73,6 +74,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 3f653895abf..49207eb65a0 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -50,6 +51,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index abe064c04e9..7e22b4e34c5 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1020RDB_PD=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -83,6 +84,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 78a54dd461d..62b25f03983 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P1020RDB_PD=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -74,6 +75,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index a8bdb5a2209..f5864dea4db 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1020RDB_PD=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -76,6 +77,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 7a533ed41d7..ca040072884 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_P1020RDB_PD=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -53,6 +54,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 3abb9d7f75b..2420217b890 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -85,6 +86,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 551b5fca8e0..22b0023ec6c 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -76,6 +77,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 493e2c94c14..8c95203a4a0 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -78,6 +79,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index fc82fa8ab98..b87c965d50b 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -55,6 +56,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index b6ae81dd425..1d33cf6750b 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -84,6 +85,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index cfbb3c274ee..8d44e5b425c 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -75,6 +76,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 36c6c7e26e6..9155768c15c 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -77,6 +78,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 691df7cc21b..4f3be9eb242 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -54,6 +55,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index f495205f5bd..bf3365a4800 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -15,6 +15,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -60,6 +61,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 23a7b66fbcb..69f30d427f7 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -15,6 +15,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -60,6 +61,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 7dfbde04693..c2dc0f21eeb 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -62,6 +63,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index aea0b89f97d..306432e41b1 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -57,6 +58,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index e51db832637..bedea018ddc 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -87,6 +88,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 5472cccff8f..f06bb02a27c 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -18,6 +18,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -86,6 +87,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 0dd725128c5..4f91dce1094 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -20,6 +20,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -89,6 +90,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 8a2096c56d9..c9d771e44bf 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -12,6 +12,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -61,6 +62,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index cc6a80447c0..a55797eb9e4 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -80,6 +81,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_CHIP_SELECTS_PER_CTRL=2 diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index cb270adc37f..2f5a1a329d0 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -79,6 +80,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_CHIP_SELECTS_PER_CTRL=2 diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 79530eac8fd..afce81b1076 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -82,6 +83,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_CHIP_SELECTS_PER_CTRL=2 diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index a671ae3d879..29b240fc147 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -54,6 +55,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_CHIP_SELECTS_PER_CTRL=2 diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 637842cda21..ca960d368bd 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -89,6 +90,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 35ab9931e71..eba73ee989f 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -21,6 +21,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -88,6 +89,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 93b02a5e990..ae98a3586b7 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -13,6 +13,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_NXP_ESBC=y CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000 CONFIG_PCIE1=y @@ -63,6 +64,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_DYNAMIC_DDR_CLK_FREQ=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 7d25bbbb0ba..76a1e583007 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -23,6 +23,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -91,6 +92,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 2846f63d47f..fe440a469f9 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -15,6 +15,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SRIO_PCIE_BOOT_SLAVE=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -60,6 +61,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index a7dc88c0bf9..f4f90d5ab22 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -15,6 +15,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -63,6 +64,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index a881488dbea..18baf568121 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -85,6 +86,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 562a79955c4..df98e33f971 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -84,6 +85,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 00018033a35..efa48af3bf8 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -87,6 +88,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 0cb359de947..8e07b2a09c1 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -59,6 +60,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index cbe1bb4e3f6..69bebfacb07 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -86,6 +87,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 80a2c003e6a..179fc63705a 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -85,6 +86,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index 99bee8e5ead..1d8a6b5f41c 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -88,6 +89,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index aa6a053209e..a1332a99b43 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -12,6 +12,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_T2080RDB_REV_D=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -60,6 +61,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index b445b6bde1f..d906035a2bf 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -78,6 +79,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index a807ac83474..d2b270dd44f 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -53,6 +54,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig index cebb79f733c..6775379428f 100644 --- a/configs/amcore_defconfig +++ b/configs/amcore_defconfig @@ -31,6 +31,8 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y CONFIG_CMD_DIAG=y CONFIG_ENV_IS_IN_FLASH=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="AMCORE" # CONFIG_NET is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 6226d50c8ac..395202bc29f 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -48,6 +48,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_TFTP_TSIZE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_CLK_IMX8=y CONFIG_CPU=y CONFIG_MXC_GPIO=y diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 70ef62a778b..54b781b9c95 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -54,6 +54,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 CONFIG_TFTP_TSIZE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_SPL_DM=y CONFIG_SYS_I2C_TEGRA=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 68655cf15bf..28fc03d85ae 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -79,6 +79,12 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_LBA48=y diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 4c7ded9d22f..d7ac1301798 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -68,6 +68,8 @@ CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="aristainetos2" CONFIG_VERSION_VARIABLE=y CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index a23c77af897..562eb104537 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -68,6 +68,8 @@ CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="aristainetos2" CONFIG_VERSION_VARIABLE=y CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 503cee91a29..14d435076da 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 4928a203d0d..956e797e43f 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -41,6 +41,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y # CONFIG_DOS_PARTITION is not set CONFIG_OF_CONTROL=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="NS3" CONFIG_CLK=y CONFIG_CLK_CCF=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index 321121e3f72..83d5712e616 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -43,6 +43,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index a38b3b78c08..401506e2193 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -84,6 +84,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index 570c4e82a47..64ebef4b500 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -67,6 +67,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 43cf53045b4..3098857d6e1 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -57,6 +57,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index aa3d6f2b9d1..b933a2352e3 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -59,6 +59,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index e83f2dfe7f3..96c739cbfbc 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig index 2fdb882dc4e..377781f0bc9 100644 --- a/configs/cobra5272_defconfig +++ b/configs/cobra5272_defconfig @@ -25,6 +25,10 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_PING=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.100.2" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.100.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFFE00201 diff --git a/configs/colibri-imx6ull-emmc_defconfig b/configs/colibri-imx6ull-emmc_defconfig index c0248dca953..b4de88aeadf 100644 --- a/configs/colibri-imx6ull-emmc_defconfig +++ b/configs/colibri-imx6ull-emmc_defconfig @@ -54,6 +54,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 CONFIG_TFTP_TSIZE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index d16b66df7c8..f2a0d79ccca 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -63,6 +63,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 CONFIG_TFTP_TSIZE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index 6896236045b..e4c418958b2 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -47,6 +47,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_TFTP_TSIZE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_CLK_IMX8=y CONFIG_CPU=y CONFIG_FXL6408_GPIO=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index aa24dea1f04..bad7b8a54ee 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -79,6 +79,12 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 4428b555036..7e24dcd4009 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -61,6 +61,12 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index bc9abc82d51..fe785d7e319 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -52,6 +52,12 @@ CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 3352b8e9235..2642e8975b5 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -66,6 +66,12 @@ CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_VYBRID_GPIO=y diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 15b7f27ae69..3a84190bbfd 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -60,6 +60,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 8a1defd0438..bb8b9ef312a 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index e8fb032bbae..ffa48fcb93f 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -66,8 +66,11 @@ CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="ccdc.img" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="ccdc" CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 +CONFIG_USE_ROOTPATH=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_SCSI_AHCI=y CONFIG_DM_PCA953X=y diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index e4da59bae92..ec672e59e89 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index e297494663e..4db72899169 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -44,6 +44,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 8b47f2d89f8..8e53eec74e5 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -47,6 +47,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 038cbbe5b99..69ad017f987 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index 63b8c8f92da..bd8b2e1155d 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index cc1fb489eb1..8d1c6fd44a7 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -84,6 +84,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/opt/eldk" CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/efi-x86_app32_defconfig b/configs/efi-x86_app32_defconfig index 4ae74dbd2e3..905f375a3ef 100644 --- a/configs/efi-x86_app32_defconfig +++ b/configs/efi-x86_app32_defconfig @@ -36,6 +36,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_REGEX is not set diff --git a/configs/efi-x86_app64_defconfig b/configs/efi-x86_app64_defconfig index 3f1e80120c6..605d49ff8cb 100644 --- a/configs/efi-x86_app64_defconfig +++ b/configs/efi-x86_app64_defconfig @@ -36,6 +36,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_REGEX is not set diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig index 8d1fc22eb93..a5c629b46f3 100644 --- a/configs/efi-x86_payload32_defconfig +++ b/configs/efi-x86_payload32_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig index 89e6d1febc8..5cde04a5ac9 100644 --- a/configs/efi-x86_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index ee731f3c0a1..d42eda2055a 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -85,6 +85,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/opt/eldk" CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 141467bbe35..0d2ebdab926 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -46,6 +46,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index a852b96d4ef..9d09d9c37f2 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -162,6 +162,9 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xFE090000 CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="gazerbeam" +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_AXI=y CONFIG_IHS_AXI=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index f999b447755..5308a8e3e97 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -97,6 +97,10 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NETCONSOLE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.146" CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_LBA48=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 4c6291f0c51..37fc1e51430 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -97,6 +97,10 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NETCONSOLE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.146" CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_LBA48=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 4e062e477e8..f33625b2ca0 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -100,6 +100,10 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NETCONSOLE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.146" CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_LBA48=y diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index 48be3c5f4a6..b29c62fc59b 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -83,6 +83,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="xea" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_DEVRES=y diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig index 26227341d9f..b7edd3bae48 100644 --- a/configs/imx28_xea_sb_defconfig +++ b/configs/imx28_xea_sb_defconfig @@ -63,6 +63,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="xea" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_DEVRES=y diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig index 7417b53e86f..6d9d0e8999b 100644 --- a/configs/integratorcp_cm1136_defconfig +++ b/configs/integratorcp_cm1136_defconfig @@ -31,6 +31,10 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.104" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.100" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig index 36b71fc4019..2d40a5f9374 100644 --- a/configs/integratorcp_cm920t_defconfig +++ b/configs/integratorcp_cm920t_defconfig @@ -31,6 +31,10 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.104" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.100" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig index 947d21ef35e..4505123d4f2 100644 --- a/configs/integratorcp_cm926ejs_defconfig +++ b/configs/integratorcp_cm926ejs_defconfig @@ -31,6 +31,10 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.104" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.100" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig index 630fe0d813d..bbdf86baebd 100644 --- a/configs/integratorcp_cm946es_defconfig +++ b/configs/integratorcp_cm946es_defconfig @@ -31,6 +31,10 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.104" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.100" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index 7391e597642..02b963e7c33 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -66,6 +66,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="kontron-mx6ul" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DM_I2C=y diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 62fd984debd..4b54813415d 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -77,6 +77,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="kontron-mx8mm" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index e332de2aa9e..b70d10433d7 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -75,6 +75,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="boot/fitImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC0" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="m53menlo" CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 186521aac6c..be349418050 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -53,6 +53,8 @@ CONFIG_CMD_JFFS2=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="microblaze-generic" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index e8ef832f898..679b6e3de53 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -59,6 +59,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig index 3f18addd5a0..c09c2221a54 100644 --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig @@ -26,6 +26,10 @@ CONFIG_CMD_SMC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.3" CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig index c56b4bb82fe..8dd65d57e3d 100644 --- a/configs/mt7623a_unielec_u7623_02_defconfig +++ b/configs/mt7623a_unielec_u7623_02_defconfig @@ -35,6 +35,10 @@ CONFIG_CMD_READ=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index e36943b0fc8..cafac4278b3 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -36,6 +36,10 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig index d7669d55779..76fd135d93c 100644 --- a/configs/mt7629_rfb_defconfig +++ b/configs/mt7629_rfb_defconfig @@ -57,6 +57,10 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig index 9235a398c55..a27202eb23e 100644 --- a/configs/mvebu_ac5_rd_defconfig +++ b/configs/mvebu_ac5_rd_defconfig @@ -43,6 +43,16 @@ CONFIG_CMD_UBI=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="0.0.0.0" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="0.0.0.0" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/srv/nfs/" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="0.0.0.0" CONFIG_CLK=y CONFIG_CLK_MVEBU=y CONFIG_DM_PCA953X=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 3999ae1c829..cc74abfcd7c 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -59,6 +59,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="fitImage" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="novena" CONFIG_VERSION_VARIABLE=y CONFIG_NETCONSOLE=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index cdb246fc644..867b89d3fed 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -77,6 +77,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/tftpboot/opos6ul-root" CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index b57e588f4e9..b7c0b0d1e8e 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -70,6 +70,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0x60040000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="EXPU1" CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index 9029e7babc8..a5193cb463e 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -68,6 +68,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0x60200000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="EXPU1" CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index aa74e1746ab..1b9e0b6c913 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -70,6 +70,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0x60040000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="SELI8" CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index 2b18a88d44f..c193f7bb406 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -68,6 +68,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0x60200000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="SELI8" CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig index 914fc39a7e3..b7e39eb31fc 100644 --- a/configs/poleg_evb_defconfig +++ b/configs/poleg_evb_defconfig @@ -28,6 +28,12 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.0.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.0.1" CONFIG_CLK=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 6b361f82116..e655b18f027 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -82,6 +82,8 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/opt/eldk" CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index cdad1b09950..a19d555f7d5 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -8,6 +8,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_QEMU_PPCE500=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -39,6 +40,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_ROOTPATH=y CONFIG_SIMPLE_BUS_CORRECT_RANGE=y CONFIG_LBA48=y CONFIG_CHIP_SELECTS_PER_CTRL=0 diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 0f4811e5d7a..9f1cb2675de 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -58,6 +58,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_SYS_IDE_MAXDEVICE=4 diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index a8222122fc9..04528ad7cd2 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_SYS_IDE_MAXDEVICE=4 diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index 861f0f59bc8..fe09c34d5b8 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -84,6 +84,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/opt/eldk" CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 30c5d4a5ad5..6c3ba4cc724 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -83,6 +83,8 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/opt/eldk" CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig index 34d23fdb842..abcd63c7ece 100644 --- a/configs/seeed_npi_imx6ull_defconfig +++ b/configs/seeed_npi_imx6ull_defconfig @@ -49,6 +49,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig index f5d16f64d73..dbfed814ded 100644 --- a/configs/slimbootloader_defconfig +++ b/configs/slimbootloader_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index cdad36bbfd8..6d859b3274b 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -63,6 +63,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="fitImage" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="socfpga_vining_fpga" CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index a75ec667d51..c4752a2b0a5 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig index df90e64cbbf..41074d50ff4 100644 --- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig @@ -58,6 +58,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y CONFIG_DM_I2C=y diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig index a242f1b1580..c9dbd485bcd 100644 --- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig @@ -58,6 +58,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y CONFIG_DM_I2C=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig index 5f1fc901137..6f8293c7ee2 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig @@ -58,6 +58,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y CONFIG_DM_I2C=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig index 65d9b5a7294..a12a150f3b1 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig @@ -58,6 +58,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y CONFIG_DM_I2C=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 86ebbef0a6c..2d4b7cbc7b6 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -94,6 +94,8 @@ CONFIG_SYS_MMC_ENV_DEV=-1 # CONFIG_SPL_ENV_IS_NOWHERE is not set # CONFIG_SPL_ENV_IS_IN_SPI_FLASH is not set CONFIG_TFTP_TSIZE=y +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index caa79e68834..22cf538b410 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -66,6 +66,8 @@ CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 CONFIG_TFTP_TSIZE=y +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 26c2e73aa04..7db562c542e 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -106,6 +106,8 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y CONFIG_SPL_BLOCK_CACHE=y CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index f76e13eafd7..c94f03569f1 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -103,6 +103,8 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y CONFIG_SPL_BLOCK_CACHE=y CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 3309c2e7924..e00c00f3746 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -67,6 +67,8 @@ CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 CONFIG_TFTP_TSIZE=y +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig index 5ee2edcf5e4..ae7a9cf6da2 100644 --- a/configs/stmark2_defconfig +++ b/configs/stmark2_defconfig @@ -37,6 +37,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:1m(u-boot),7m(kernel),-(rootfs)" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_CS=1 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="stmark2" # CONFIG_NET is not set CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index 205ac877482..74c4a4967d0 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index b6d59215e73..194b0519ea2 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -55,6 +55,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index fea35cd915e..39c8a87fbee 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index aef524052bc..a9e37170f45 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -84,6 +84,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/opt/eldk" CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index 5665cf38798..b361e3f4034 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -50,6 +50,16 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="zImage" CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.168.11.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.11.10" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/nfs/root/path" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.11.1" CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index e3087a9109e..765d42a3e6c 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -51,6 +51,16 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="zImage" CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.168.11.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.11.10" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/nfs/root/path" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.11.1" CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index 1b0e0d0da74..6a0e2666cf1 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -38,6 +38,16 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="Image" CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.168.11.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.11.10" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/nfs/root/path" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.11.1" CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index ed2bcc69fc5..66c969f95e5 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -27,6 +27,8 @@ CONFIG_CMD_USB=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="usbarmory" CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_IIM=y diff --git a/env/Kconfig b/env/Kconfig index 4e506ae262b..c13a5b0d467 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -866,6 +866,16 @@ config ETHPRIME help The value to set the "ethprime" variable to. +config USE_HOSTNAME + bool "Set a default 'hostname' value in the environment" + default y if X86 + +config HOSTNAME + string "Value of the default 'hostname' value in the environment" + depends on USE_HOSTNAME + default "x86" if X86 + default "unknown" + config VERSION_VARIABLE bool "Add a 'ver' environment variable with the U-Boot version" help diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index b360238b332..e14650fe0d4 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -17,14 +17,6 @@ /* I2C */ -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* CONFIG_MCFFEC */ - -#define CONFIG_HOSTNAME "M5208EVBe" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=40010000\0" \ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index ed45eccb62c..220524bfaed 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -26,14 +26,7 @@ #define CFG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */ -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME "M5235EVB" + #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index ad55938348e..65a7aa04086 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -36,8 +36,6 @@ "" #endif -#define CONFIG_HOSTNAME "M5253DEMO" - /* I2C */ #define CFG_SYS_I2C_PINMUX_REG (*(u32 *) (CFG_SYS_MBAR+0x19C)) #define CFG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index a9339e50525..c58d19c810f 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -29,14 +29,6 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text); -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* CONFIG_MCFFEC */ - -#define CONFIG_HOSTNAME "M5272C3" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index bde9e770e52..e23439fd782 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -29,14 +29,6 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text*); -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* CONFIG_MCFFEC */ - -#define CONFIG_HOSTNAME "M5282EVB" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 439ed93a237..ac2bd0b2241 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -30,14 +30,6 @@ /* I2C */ -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME "M53017" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=40010000\0" \ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 72f0c63a1e2..a86a117fd8f 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -22,14 +22,6 @@ /* I2C */ -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME "M5329EVB" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=40010000\0" \ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 4e8b54e01f4..b2ad03cc3cb 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -24,14 +24,6 @@ /* I2C */ -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME "M5373EVB" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index 232cf9e9984..f8368823aac 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -52,10 +52,6 @@ "${ofl_args}; " \ "bootm ${loadaddr} - 0xf00000\0" -#define CONFIG_IPADDR 192.168.0.3 -#define CONFIG_SERVERIP 192.168.0.1 -#define CONFIG_NETMASK 255.0.0.0 - /* Miscellaneous configurable options */ /* Definitions for initial stack pointer and data area (in DPRAM) */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index dbfcdfb738b..7dff3cc6913 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -197,10 +197,6 @@ #define CONFIG_NETDEV "eth1" -#define CONFIG_HOSTNAME "mpc837x_rdb" -#define CONFIG_ROOTPATH "/nfsroot" - /* U-Boot image on TFTP server */ -#define CONFIG_UBOOTPATH "u-boot.bin" #define CONFIG_FDTFILE "mpc8379_rdb.dtb" #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 34b876f829e..1f1eacdb691 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -298,20 +298,10 @@ * Environment Configuration */ -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ecc=off\0" \ "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ "protect off " __stringify(CONFIG_TEXT_BASE) \ " +$filesize; " \ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f79c62adba3..d83563d6181 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -380,13 +380,10 @@ extern unsigned long get_sdram_size(void); * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "loadaddr=1000000\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 707157e4a9a..0f0cdb3a681 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -306,8 +306,6 @@ /* * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH u-boot.bin #define __USB_PHY_TYPE utmi @@ -315,7 +313,7 @@ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ "bank_intlv=cs0_cs1\0" \ "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ "protect off $ubootaddr +$filesize && " \ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index b590f127392..e815d9f81a1 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -421,8 +421,6 @@ /* * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define __USB_PHY_TYPE utmi #ifdef CONFIG_ARCH_T1024 @@ -441,7 +439,7 @@ ARCH_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ "netdev=eth0\0" \ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 9d805f446b4..6fe0bd68280 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -411,8 +411,6 @@ /* * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ #define __USB_PHY_TYPE utmi #define RAMDISKFILE "t104xrdb/ramdisk.uboot" @@ -434,7 +432,7 @@ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ "protect off $ubootaddr +$filesize && " \ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 804b7ec4c1c..79b3d7af4ea 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -419,8 +419,6 @@ /* * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ #define __USB_PHY_TYPE utmi @@ -430,7 +428,7 @@ "bank_intlv=auto;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ "protect off $ubootaddr +$filesize && " \ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index d8213b4662f..2a32fe37aa9 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -385,8 +385,6 @@ /* * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ #define __USB_PHY_TYPE utmi @@ -396,7 +394,7 @@ "bank_intlv=auto;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ "protect off $ubootaddr +$filesize && " \ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 958933689d3..d8c4de5b3d7 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -138,8 +138,6 @@ /* * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ #define HVBOOT \ "setenv bootargs config-addr=0x60000000; " \ @@ -386,7 +384,7 @@ "bank_intlv=auto;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ "protect off $ubootaddr +$filesize && " \ diff --git a/include/configs/amcore.h b/include/configs/amcore.h index ee0be972d24..ca29346fe64 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -8,8 +8,6 @@ #ifndef __AMCORE_CONFIG_H #define __AMCORE_CONFIG_H -#define CONFIG_HOSTNAME "AMCORE" - #define CFG_SYS_UART_PORT 0 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index cf23837863b..aa3dcf4a881 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -14,9 +14,6 @@ #define USDHC2_BASE_ADDR 0x5b020000 /* Networking */ -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 #define MEM_LAYOUT_ENV_SETTINGS \ "fdt_addr_r=0x84000000\0" \ diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index f0a02ae1795..1d478078b2c 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -33,12 +33,6 @@ func(PXE, pxe, na) \ func(DHCP, dhcp, na) -#undef CONFIG_IPADDR -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#undef CONFIG_SERVERIP -#define CONFIG_SERVERIP 192.168.10.1 - #define DFU_ALT_EMMC_INFO "apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \ "boot part 0 1 mmcpart 0; " \ "rootfs part 0 2 mmcpart 0; " \ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index a3c86545f07..25a84458f55 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -35,12 +35,6 @@ /* Command definition */ -#undef CONFIG_IPADDR -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#undef CONFIG_SERVERIP -#define CONFIG_SERVERIP 192.168.10.1 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 6faf544d21b..85413545715 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -11,8 +11,6 @@ #ifndef __ARISTAINETOS2_CONFIG_H #define __ARISTAINETOS2_CONFIG_H -#define CONFIG_HOSTNAME "aristainetos2" - #if (CONFIG_SYS_BOARD_VERSION == 5) #define CONSOLE_DEV "ttymxc1" #elif (CONFIG_SYS_BOARD_VERSION == 6) diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index b5469880fe2..fc176dc2014 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -9,8 +9,6 @@ #include -#define CONFIG_HOSTNAME "NS3" - /* Physical Memory Map */ #define V2M_BASE 0x80000000 #define PHYS_SDRAM_1 V2M_BASE diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 6d6e2fc6962..8c83c3ac06a 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -91,9 +91,6 @@ enter a valid image address in flash */ /* User network settings */ -#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */ -#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */ - #endif /*---*/ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index c0c3b4e0359..2f09a264cbe 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -20,10 +20,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_SYS_FSL_USDHC_NUM 1 -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - #if defined(CONFIG_TARGET_COLIBRI_IMX6ULL_EMMC) #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 6002d8d5c9f..215c633a4c9 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -14,10 +14,6 @@ #define USDHC1_BASE_ADDR 0x5b010000 #define USDHC2_BASE_ADDR 0x5b020000 -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - #define MEM_LAYOUT_ENV_SETTINGS \ "fdt_addr_r=0x83000000\0" \ "kernel_addr_r=0x81000000\0" \ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 60a3862a4d1..19daad21cb5 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -30,12 +30,6 @@ /* Command definition */ -#undef CONFIG_IPADDR -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#undef CONFIG_SERVERIP -#define CONFIG_SERVERIP 192.168.10.1 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 32a79b02554..48c3f015473 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -21,10 +21,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - #if defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index fa778ec9e2b..8a790400b46 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -16,10 +16,6 @@ /* NAND support */ -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - #define CONFIG_FDTADDR 0x84000000 #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 5da2778b67b..119a834fe74 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -21,9 +21,6 @@ * Environment Configuration */ -#define CONFIG_HOSTNAME "ccdc" -#define CONFIG_ROOTPATH "/opt/nfsroot" - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth1\0" \ "consoledev=ttyS1\0" \ diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 36dcee87c5f..671b75e6986 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -55,10 +55,6 @@ * Environment Configuration */ -/* TODO: Turn into string option and migrate to Kconfig */ -#define CONFIG_HOSTNAME "gazerbeam" -#define CONFIG_ROOTPATH "/opt/nfsroot" - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 4d0a78c6269..298a8f5aa2a 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -57,7 +57,5 @@ /* Persistent Environment Config */ /* Environment */ -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.146 #endif /* __CONFIG_H */ diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 25bb41ebc46..596e4ff8c3b 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -19,9 +19,6 @@ /* Integrator CP-specific configuration */ #define CFG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ -#define CONFIG_SERVERIP 192.168.1.100 -#define CONFIG_IPADDR 192.168.1.104 - /* * Miscellaneous configurable options */ diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index 6fcacdb0c66..7c5f673c0f4 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -23,7 +23,6 @@ /* Board and environment settings */ #define CONFIG_MXC_UART_BASE UART4_BASE -#define CONFIG_HOSTNAME "kontron-mx6ul" #ifdef CONFIG_USB_EHCI_HCD #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 80a32304606..beb1926c12a 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -23,7 +23,6 @@ #define CFG_SYS_INIT_RAM_SIZE 0x200000 /* Board and environment settings */ -#define CONFIG_HOSTNAME "kontron-mx8mm" #ifdef CONFIG_USB_EHCI_HCD #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 66591390d90..189b2113f75 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -84,7 +84,6 @@ /* * Extra Environments */ -#define CONFIG_HOSTNAME "m53menlo" #define CONFIG_EXTRA_ENV_SETTINGS \ "consdev=ttymxc0\0" \ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index edd2466caa9..b8b08974c7e 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -16,8 +16,6 @@ # define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -#define CONFIG_HOSTNAME "microblaze-generic" - /* architecture dependent code */ #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index 8c297266d8b..65415129534 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -18,7 +18,5 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 /* Ethernet */ -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.3 #endif diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 39a7ba76633..93161bd24f0 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -33,8 +33,6 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" /* Ethernet */ -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.2 #ifdef CONFIG_DISTRO_DEFAULTS diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index bfa44aacc72..99b09ad41e7 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -28,7 +28,5 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 /* Ethernet */ -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.2 #endif diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h index 5c9620371e3..3ad3aefa755 100644 --- a/include/configs/mvebu_alleycat-5.h +++ b/include/configs/mvebu_alleycat-5.h @@ -15,11 +15,6 @@ 115200, 230400, 460800, 921600 } /* Default Env vars */ -#define CONFIG_IPADDR 0.0.0.0 /* In order to cause an error */ -#define CONFIG_SERVERIP 0.0.0.0 /* In order to cause an error */ -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 0.0.0.0 -#define CONFIG_ROOTPATH "/srv/nfs/" /* Default Dir for NFS */ #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ diff --git a/include/configs/novena.h b/include/configs/novena.h index 4e46dfc526c..6e4bdce1c08 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -25,7 +25,6 @@ */ /* Booting Linux */ -#define CONFIG_HOSTNAME "novena" /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 09c4ddb6646..2eebd0c9a45 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -18,8 +18,6 @@ /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_NETMASK 255.255.255.0 - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index e42a736136b..5c44b9dcb20 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -27,6 +27,4 @@ /* LCD */ #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR -#define CONFIG_ROOTPATH "/tftpboot/opos6ul-root" - #endif /* __OPOS6ULDEV_CONFIG_H */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index eb2c5a2d837..ee25990b034 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -396,15 +396,12 @@ /* * Environment Configuration */ -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #include "p1_p2_bootsrc.h" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ +"uboot=" CONFIG_UBOOTPATH "\0" \ "loadaddr=1000000\0" \ "bootfile=uImage\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ diff --git a/include/configs/poleg.h b/include/configs/poleg.h index 518d7a3639c..075729e5d37 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -14,9 +14,6 @@ #define CFG_SYS_SDRAM_BASE 0x0 /* Default environemnt variables */ -#define CONFIG_SERVERIP 192.168.0.1 -#define CONFIG_IPADDR 192.168.0.2 -#define CONFIG_NETMASK 255.255.255.0 #define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ "stdin=serial\0" \ "stdout=serial\0" \ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 30a9eae8523..d0561899586 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -58,7 +58,5 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); /* * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ #endif /* __QEMU_PPCE500_H */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 5a001716fb0..1b1787a3d3c 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -17,8 +17,6 @@ /* commands to include */ -#define CONFIG_ROOTPATH "/opt/eldk" - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 70d9f3607a6..d88b07bc159 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -13,7 +13,6 @@ /* Booting Linux */ /* Extra Environment */ -#define CONFIG_HOSTNAME "socfpga_vining_fpga" /* * Active LOW GPIO buttons: diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index c9cfadd9ce0..9715dfad1c9 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -24,9 +24,6 @@ /* NAND support */ /* Ethernet need */ -#ifdef CONFIG_DWC_ETH_QOS -#define CONFIG_SERVERIP 192.168.1.1 -#endif #define STM32MP_FIP_IMAGE_GUID \ EFI_GUID(0x19d5df83, 0x11b0, 0x457b, 0xbe, 0x2c, \ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index f81cef0a2c4..ce941d832a5 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -8,8 +8,6 @@ #ifndef __STMARK2_CONFIG_H #define __STMARK2_CONFIG_H -#define CONFIG_HOSTNAME "stmark2" - #define CFG_SYS_UART_PORT 0 #define LDS_BOARD_TEXT \ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 8cd81f1cddd..7fee64029d8 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -46,10 +46,6 @@ /* * Network Configuration */ -#define CONFIG_SERVERIP 192.168.11.1 -#define CONFIG_IPADDR 192.168.11.10 -#define CONFIG_GATEWAYIP 192.168.11.1 -#define CONFIG_NETMASK 255.255.255.0 #if defined(CONFIG_ARM64) /* ARM Trusted Firmware */ @@ -62,8 +58,6 @@ "third_image=u-boot.bin\0" #endif -#define CONFIG_ROOTPATH "/nfs/root/path" - #ifdef CONFIG_FIT #define KERNEL_ADDR_R_OFFSET "0x05100000" #define LINUXBOOT_ENV_SETTINGS \ diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index a2bc3cd23a5..7f79c6342fc 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -28,7 +28,6 @@ #define CONFIG_MXC_USB_FLAGS 0 /* Linux boot */ -#define CONFIG_HOSTNAME "usbarmory" #define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0) diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 3e17b53dde2..9bf2462010d 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -41,8 +41,6 @@ */ /* Default environment */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_HOSTNAME "x86" #define CONFIG_RAMDISK_ADDR 0x4000000 #if defined(CONFIG_GENERATE_ACPI_TABLE) || defined(CONFIG_EFI_STUB) #define CONFIG_OTHBOOTARGS "othbootargs=\0" diff --git a/include/configs/xea.h b/include/configs/xea.h index b432ab2dc8e..a3dc0c74ebb 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -26,7 +26,6 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Extra Environment */ -#define CONFIG_HOSTNAME "xea" #define CONFIG_EXTRA_ENV_SETTINGS \ "bootmode=update\0" \ diff --git a/include/env_default.h b/include/env_default.h index 7c9c00a9692..3b7685ee26c 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -53,11 +53,11 @@ const char default_environment[] = { #ifdef CONFIG_ETHPRIME "ethprime=" CONFIG_ETHPRIME "\0" #endif -#ifdef CONFIG_IPADDR - "ipaddr=" __stringify(CONFIG_IPADDR) "\0" +#ifdef CONFIG_USE_IPADDR + "ipaddr=" CONFIG_IPADDR "\0" #endif -#ifdef CONFIG_SERVERIP - "serverip=" __stringify(CONFIG_SERVERIP) "\0" +#ifdef CONFIG_USE_SERVERIP + "serverip=" CONFIG_SERVERIP "\0" #endif #ifdef CONFIG_SYS_DISABLE_AUTOLOAD "autoload=0\0" @@ -65,17 +65,17 @@ const char default_environment[] = { #ifdef CONFIG_PREBOOT_DEFINED "preboot=" CONFIG_PREBOOT "\0" #endif -#ifdef CONFIG_ROOTPATH +#ifdef CONFIG_USE_ROOTPATH "rootpath=" CONFIG_ROOTPATH "\0" #endif -#ifdef CONFIG_GATEWAYIP - "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0" +#ifdef CONFIG_USE_GATEWAYIP + "gatewayip=" CONFIG_GATEWAYIP "\0" #endif -#ifdef CONFIG_NETMASK - "netmask=" __stringify(CONFIG_NETMASK) "\0" +#ifdef CONFIG_USE_NETMASK + "netmask=" CONFIG_NETMASK "\0" #endif -#ifdef CONFIG_HOSTNAME - "hostname=" CONFIG_HOSTNAME "\0" +#ifdef CONFIG_USE_HOSTNAME + "hostname=" CONFIG_HOSTNAME "\0" #endif #ifdef CONFIG_USE_BOOTFILE "bootfile=" CONFIG_BOOTFILE "\0" diff --git a/net/Kconfig b/net/Kconfig index a1ec3f8542e..4215889127c 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -174,6 +174,58 @@ config BOOTP_MAX_ROOT_PATH_LEN help Select maximal length of option 17 root path. +config USE_GATEWAYIP + bool "Set a default 'gateway' value in the environment" + help + Defines a default value for the IP address of the default router + where packets to other networks are sent to. (Environment variable + "gatewayip") + +config GATEWAYIP + string "Value of the default 'gateway' value in the environment" + depends on USE_GATEWAYIP + +config USE_IPADDR + bool "Set a default 'ipaddr' value in the environment" + help + Define a default value for the IP address to use for the default + Ethernet interface, in case this is not determined through e.g. + bootp. (Environment variable "ipaddr") + +config IPADDR + string "Value of the default 'ipaddr' value in the environment" + depends on USE_IPADDR + +config USE_NETMASK + bool "Set a default 'netmask' value in the environment" + help + Defines a default value for the subnet mask (or routing prefix) which + is used to determine if an IP address belongs to the local subnet or + needs to be forwarded through a router. (Environment variable "netmask") + +config NETMASK + string "Value of the default 'netmask' value in the environment" + depends on USE_NETMASK + +config USE_ROOTPATH + bool "Set a default 'rootpath' value in the environment" + +config ROOTPATH + string "Value of the default 'rootpath' value in the environment" + depends on USE_ROOTPATH + default "/opt/nfsroot" + +config USE_SERVERIP + bool "Set a default 'serverip' value in the environment" + help + Defines a default value for the IP address of a TFTP server to + contact when using the "tftboot" command. (Environment variable + "serverip") + +config SERVERIP + string "Value of the default 'serverip' value in the environment" + depends on USE_SERVERIP + config PROT_TCP bool "TCP stack" help -- cgit v1.3.1 From b5f7d8816225f869e3fd63d78d017308af0ac224 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:28 -0500 Subject: arm: samsung: Rename CONFIG_G_DNL_*_NUM variables Following how g_dnl_bind_fixup is used on other platforms, rename the unchanging defines used here to be prefixed with EXYNOS rather than Samsung, and define them here. Cc: Minkyu Kang Cc: Jaehoon Chung Signed-off-by: Tom Rini --- board/samsung/common/gadget.c | 14 ++++++++++---- include/configs/dh_imx6.h | 4 ---- include/configs/exynos4-common.h | 6 ------ include/configs/odroid_xu3.h | 8 -------- include/configs/s5p_goni.h | 7 ------- include/configs/socfpga_common.h | 4 ---- 6 files changed, 10 insertions(+), 33 deletions(-) (limited to 'include') diff --git a/board/samsung/common/gadget.c b/board/samsung/common/gadget.c index 6d783e61e0d..9487f9ec4e0 100644 --- a/board/samsung/common/gadget.c +++ b/board/samsung/common/gadget.c @@ -7,14 +7,20 @@ #include #include +#define EXYNOS_G_DNL_THOR_VENDOR_NUM 0x04E8 +#define EXYNOS_G_DNL_THOR_PRODUCT_NUM 0x685D + +#define EXYNOS_G_DNL_UMS_VENDOR_NUM 0x0525 +#define EXYNOS_G_DNL_UMS_PRODUCT_NUM 0xA4A5 + int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) { if (!strcmp(name, "usb_dnl_thor")) { - put_unaligned(CONFIG_G_DNL_THOR_VENDOR_NUM, &dev->idVendor); - put_unaligned(CONFIG_G_DNL_THOR_PRODUCT_NUM, &dev->idProduct); + put_unaligned(EXYNOS_G_DNL_THOR_VENDOR_NUM, &dev->idVendor); + put_unaligned(EXYNOS_G_DNL_THOR_PRODUCT_NUM, &dev->idProduct); } else if (!strcmp(name, "usb_dnl_ums")) { - put_unaligned(CONFIG_G_DNL_UMS_VENDOR_NUM, &dev->idVendor); - put_unaligned(CONFIG_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct); + put_unaligned(EXYNOS_G_DNL_UMS_VENDOR_NUM, &dev->idVendor); + put_unaligned(EXYNOS_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct); } else { put_unaligned(CONFIG_USB_GADGET_VENDOR_NUM, &dev->idVendor); put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct); diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index f9b3d19480e..3aed6299ed5 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -38,10 +38,6 @@ /* USB Gadget (DFU, UMS) */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) #define DFU_DEFAULT_POLL_TIMEOUT 300 - -/* USB IDs */ -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 #endif #endif diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index bf965e5cedb..e8c182bc2f3 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -12,12 +12,6 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 -/* USB Samsung's IDs */ -#define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8 -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 - /* Common environment variables */ #define ENV_ITB \ "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 5bbe7aadcb2..bf63a4de076 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -20,14 +20,6 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 #define DFU_MANIFEST_POLL_TIMEOUT 25000 -/* THOR */ -#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_USB_GADGET_VENDOR_NUM -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D - -/* UMS */ -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 - #define CONFIG_DFU_ALT_SYSTEM \ "uImage fat 0 1;" \ "zImage fat 0 1;" \ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 97f5dd0e473..da83db1f68a 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -24,13 +24,6 @@ /* USB Composite download gadget - g_dnl */ #define DFU_DEFAULT_POLL_TIMEOUT 300 -/* USB Samsung's IDs */ - -#define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8 -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 - /* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ /* partitions definitions */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index bbbdea6664c..088cd4d4f7f 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -83,10 +83,6 @@ */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) #define DFU_DEFAULT_POLL_TIMEOUT 300 - -/* USB IDs */ -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 #endif /* -- cgit v1.3.1 From 1353b25ec58eba4cd26f4101ebb1b6047838a105 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:30 -0500 Subject: i2c: Remove CONFIG_I2C_MULTI_BUS This functionality is part of the legacy I2C subsystem and is currently unused anywhere. Remove the remaining references. Signed-off-by: Tom Rini --- README | 10 +--------- cmd/i2c.c | 15 ++++++--------- drivers/i2c/mv_i2c.c | 33 --------------------------------- include/configs/display5.h | 3 --- include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/novena.h | 3 --- 6 files changed, 7 insertions(+), 58 deletions(-) (limited to 'include') diff --git a/README b/README index c0f55b2586c..12096331760 100644 --- a/README +++ b/README @@ -984,21 +984,13 @@ The following options need to be configured: CFG_SYS_I2C_NOPROBES This option specifies a list of I2C devices that will be skipped - when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS - is set, specify a list of bus-device pairs. Otherwise, specify - a 1D array of device addresses + when the 'i2c probe' command is issued. e.g. - #undef CONFIG_I2C_MULTI_BUS #define CFG_SYS_I2C_NOPROBES {0x50,0x68} will skip addresses 0x50 and 0x68 on a board with one I2C bus - #define CONFIG_I2C_MULTI_BUS - #define CFG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} - - will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 - CFG_SYS_RTC_BUS_NUM If defined, then this indicates the I2C bus number for the RTC. diff --git a/cmd/i2c.c b/cmd/i2c.c index da8b4c25555..f204061cf09 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -98,7 +98,7 @@ static uint i2c_mm_last_alen; * pairs. The following macros take care of this */ #if defined(CFG_SYS_I2C_NOPROBES) -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) static struct { uchar bus; @@ -1764,8 +1764,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, * Returns zero on success, CMD_RET_USAGE in case of misuse and negative * on error. */ -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) || \ - CONFIG_IS_ENABLED(DM_I2C) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -1915,10 +1914,9 @@ static struct cmd_tbl cmd_i2c_sub[] = { U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""), #endif U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""), -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || \ - defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""), -#endif /* CONFIG_I2C_MULTI_BUS */ +#endif #if defined(CONFIG_I2C_EDID) U_BOOT_CMD_MKENT(edid, 1, 1, do_edid, "", ""), #endif /* CONFIG_I2C_EDID */ @@ -1992,10 +1990,9 @@ static char i2c_help_text[] = "i2c " /* That's the prefix for the crc32 command below. */ #endif "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n" -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || \ - defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) "i2c dev [dev] - show or set current I2C bus\n" -#endif /* CONFIG_I2C_MULTI_BUS */ +#endif #if defined(CONFIG_I2C_EDID) "i2c edid chip - print EDID configuration information\n" #endif /* CONFIG_I2C_EDID */ diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c index 8ee17f0a450..5bc9cd7b295 100644 --- a/drivers/i2c/mv_i2c.c +++ b/drivers/i2c/mv_i2c.c @@ -374,45 +374,12 @@ static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen, static struct mv_i2c *base_glob; -#ifdef CONFIG_I2C_MULTI_BUS -static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG; -static unsigned int bus_initialized[CONFIG_MV_I2C_NUM]; -static unsigned int current_bus; - -int i2c_set_bus_num(unsigned int bus) -{ - if ((bus < 0) || (bus >= CONFIG_MV_I2C_NUM)) { - printf("Bad bus: %d\n", bus); - return -1; - } - - base_glob = (struct mv_i2c *)i2c_regs[bus]; - current_bus = bus; - - if (!bus_initialized[current_bus]) { - bus_initialized[current_bus] = 1; - } - - return 0; -} - -unsigned int i2c_get_bus_num(void) -{ - return current_bus; -} -#endif - /* API Functions */ void i2c_init(int speed, int slaveaddr) { u32 val; -#ifdef CONFIG_I2C_MULTI_BUS - current_bus = 0; - base_glob = (struct mv_i2c *)i2c_regs[current_bus]; -#else base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG; -#endif if (speed > I2C_SPEED_STANDARD_RATE) val = ICR_FM; diff --git a/include/configs/display5.h b/include/configs/display5.h index 7636d2869a9..5cbeb9224c3 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -36,9 +36,6 @@ #define CONFIG_MXC_UART_BASE UART5_BASE -/* I2C Configs */ -#define CONFIG_I2C_MULTI_BUS - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 8d5b24d827d..ffd394691a0 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -149,7 +149,6 @@ * I2C */ -#define CONFIG_I2C_MULTI_BUS #define CFG_SYS_I2C_MAX_HOPS 1 #define CFG_SYS_NUM_I2C_BUSES 3 #define I2C_MUX_PCA_ADDR 0x70 diff --git a/include/configs/novena.h b/include/configs/novena.h index 6e4bdce1c08..79e49c74f85 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -33,9 +33,6 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* I2C */ -#define CONFIG_I2C_MULTI_BUS - /* I2C EEPROM */ /* MMC Configs */ -- cgit v1.3.1 From 308520b8f2b11b3427fe8a02171839992bc85da6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:31 -0500 Subject: global: Remove unused CONFIG symbols This removes the following unreferenced CONFIG symbols: CONFIG_FDTADDR CONFIG_FDTFILE CONFIG_FLASH_SECTOR_SIZE CONFIG_FSL_CPLD CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_I2C_MVTWSI CONFIG_I2C_RTC_ADDR CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE CONFIG_L1_INIT_RAM CONFIG_MACB_SEARCH_PHY CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MVGBE_PORTS CONFIG_NETDEV CONFIG_NUM_DSP_CPUS CONFIG_PHY_BASE_ADR CONFIG_PHY_INTERFACE_MODE CONFIG_PSRAM_SCFG CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RD_LVL CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_SETUP_INITRD_TAG CONFIG_SH_QSPI_BASE CONFIG_SMDK5420 CONFIG_SOCRATES CONFIG_SPI_ADDR CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET CONFIG_TEGRA_SLINK_CTRLS CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM And also: BL1_SIZE PHY_NO RESERVE_BLOCK_SIZE Signed-off-by: Tom Rini --- README | 11 ----------- arch/arm/include/asm/arch-ls102xa/config.h | 1 - arch/arm/mach-mvebu/include/mach/config.h | 9 --------- arch/powerpc/include/asm/config_mpc85xx.h | 1 - arch/xtensa/include/asm/config.h | 1 - board/Marvell/openrd/openrd.c | 2 +- drivers/net/mvgbe.c | 4 ---- drivers/net/mvgbe.h | 7 ------- drivers/ram/mpc83xx_sdram.c | 7 +------ include/configs/MPC837XERDB.h | 8 +++----- include/configs/P1010RDB.h | 1 - include/configs/P2041RDB.h | 9 ++------- include/configs/SBx81LIFKW.h | 9 --------- include/configs/SBx81LIFXCAT.h | 9 --------- include/configs/T102xRDB.h | 2 -- include/configs/T104xRDB.h | 4 ---- include/configs/T208xQDS.h | 2 -- include/configs/T208xRDB.h | 2 -- include/configs/T4240RDB.h | 3 --- include/configs/alt.h | 3 --- include/configs/ax25-ae350.h | 3 --- include/configs/beaver.h | 4 ---- include/configs/blanche.h | 4 +--- include/configs/cardhu.h | 4 ---- include/configs/cei-tk1-som.h | 3 --- include/configs/colibri_vf.h | 4 ---- include/configs/dalmore.h | 3 --- include/configs/dns325.h | 7 ------- include/configs/dockstar.h | 6 ------ include/configs/dra7xx_evm.h | 1 - include/configs/dreamplug.h | 6 ------ include/configs/ds109.h | 8 -------- include/configs/eb_cpu5282.h | 8 -------- include/configs/efi-x86_app.h | 2 -- include/configs/embestmx6boards.h | 6 +++--- include/configs/ethernut5.h | 1 - include/configs/exynos5-common.h | 2 -- include/configs/exynos5420-common.h | 2 -- include/configs/exynos7420-common.h | 4 ---- include/configs/goflexhome.h | 6 ------ include/configs/guruplug.h | 8 -------- include/configs/ib62x0.h | 8 -------- include/configs/iconnect.h | 10 ---------- include/configs/jetson-tk1.h | 5 ----- include/configs/k2e_evm.h | 1 - include/configs/k2g_evm.h | 1 - include/configs/k2l_evm.h | 1 - include/configs/kmcent2.h | 1 - include/configs/kontron_sl28.h | 1 - include/configs/lacie_kw.h | 7 ------- include/configs/legoev3.h | 1 - include/configs/ls1028a_common.h | 1 - include/configs/ls1043a_common.h | 1 - include/configs/ls1043aqds.h | 1 - include/configs/ls1043ardb.h | 1 - include/configs/ls1046a_common.h | 1 - include/configs/ls1046afrwy.h | 1 - include/configs/ls1046aqds.h | 1 - include/configs/ls1046ardb.h | 1 - include/configs/ls1088a_common.h | 1 - include/configs/ls1088aqds.h | 1 - include/configs/ls1088ardb.h | 1 - include/configs/ls2080a_common.h | 1 - include/configs/ls2080aqds.h | 1 - include/configs/ls2080ardb.h | 1 - include/configs/lx2160a_common.h | 1 - include/configs/malta.h | 2 -- include/configs/mt7621.h | 1 - include/configs/mt7629.h | 5 +---- include/configs/mxs.h | 5 ----- include/configs/nas220.h | 12 ------------ include/configs/nsa310s.h | 4 ---- include/configs/nyan-big.h | 3 --- include/configs/openrd.h | 22 ---------------------- include/configs/origen.h | 6 ------ include/configs/p2371-0000.h | 3 --- include/configs/p2371-2180.h | 3 --- include/configs/p2571.h | 3 --- include/configs/p3450-0000.h | 3 --- include/configs/pm9263.h | 5 ----- include/configs/pogo_e02.h | 6 ------ include/configs/pogo_v4.h | 6 ------ include/configs/porter.h | 3 --- include/configs/qemu-ppce500.h | 1 - include/configs/rcar-gen3-common.h | 1 - include/configs/rk3399_common.h | 10 ---------- include/configs/sheevaplug.h | 6 ------ include/configs/silk.h | 3 --- include/configs/smdk5420.h | 2 -- include/configs/smdkv310.h | 3 --- include/configs/socfpga_sr1500.h | 6 ------ include/configs/socrates.h | 4 ---- include/configs/stout.h | 3 --- include/configs/synquacer.h | 1 - include/configs/tec-ng.h | 6 ------ include/configs/venice2.h | 3 --- include/configs/vinco.h | 3 --- include/configs/x86-common.h | 16 ---------------- include/configs/xpress.h | 7 ++----- 99 files changed, 14 insertions(+), 391 deletions(-) (limited to 'include') diff --git a/README b/README index 12096331760..9e2627863ce 100644 --- a/README +++ b/README @@ -373,12 +373,6 @@ The following options need to be configured: such as ARM architectural timer initialization. - Linux Kernel Interface: - CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only] - - When transferring memsize parameter to Linux, some versions - expect it to be in bytes, others in MB. - Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes. - CONFIG_OF_LIBFDT New kernel versions are expecting firmware settings to be @@ -585,11 +579,6 @@ The following options need to be configured: Support for generic parallel port TPM devices. Only one device per system is supported at this time. - CONFIG_TPM_TIS_BASE_ADDRESS - Base address where the generic TPM device is mapped - to. Contemporary x86 systems usually map it at - 0xfed40000. - CONFIG_TPM Define this to enable the TPM support library which provides functional interfaces to some TPM commands. diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 14f86df5ed5..4a4d6424414 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -70,7 +70,6 @@ /* SATA */ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) #ifdef CONFIG_DDR_SPD -#define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #endif diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 2e06f2bdaee..96a08104ff4 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -30,13 +30,4 @@ /* Needed for SPI NOR booting in SPL */ #define CONFIG_DM_SEQ_ALIAS 1 -/* - * I2C related stuff - */ -#ifdef CONFIG_CMD_I2C -#ifndef CONFIG_SYS_I2C_SOFT -#define CONFIG_I2C_MVTWSI -#endif -#endif - #endif /* __MVEBU_CONFIG_H */ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index edaf8baaaeb..e8059910606 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -133,7 +133,6 @@ #define CFG_SYS_FM_MURAM_SIZE 0x60000 #ifdef CONFIG_ARCH_B4860 -#define CONFIG_NUM_DSP_CPUS 6 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CFG_SYS_NUM_FM1_DTSEC 6 #define CFG_SYS_NUM_FM1_10GEC 2 diff --git a/arch/xtensa/include/asm/config.h b/arch/xtensa/include/asm/config.h index a1096ab1961..21b334b9389 100644 --- a/arch/xtensa/include/asm/config.h +++ b/arch/xtensa/include/asm/config.h @@ -14,7 +14,6 @@ * restricting used physical memory to the first 128MB. */ #if XCHAL_HAVE_PTP_MMU -#define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED (128 << 20) #endif diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index f44ac3315eb..581e2e084d6 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -140,7 +140,7 @@ void mv_phy_init(char *name) /* reset the phy */ miiphy_reset(name, devadr); - printf(PHY_NO" Initialized on %s\n", name); + printf("Initialized on %s\n", name); } void reset_phy(void) diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 58363fce057..3587ca2124e 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -37,10 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_MVGBE_PORTS -# define CONFIG_MVGBE_PORTS {0, 0} -#endif - #define MV_PHY_ADR_REQUEST 0xee #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) #define MVGBE_PGADR_REG 22 diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h index e3f5ac06399..6514ab67bab 100644 --- a/drivers/net/mvgbe.h +++ b/drivers/net/mvgbe.h @@ -11,13 +11,6 @@ #ifndef __MVGBE_H__ #define __MVGBE_H__ -/* PHY_BASE_ADR is board specific and can be configured */ -#if defined (CONFIG_PHY_BASE_ADR) -#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR -#else -#define PHY_BASE_ADR 0x08 /* default phy base addr */ -#endif - /* Constants */ #define INT_CAUSE_UNMASK_ALL 0x0007ffff #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index a53ff93a6b0..11676d4fae7 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -118,12 +118,7 @@ int dram_init(void) phys_size_t get_effective_memsize(void) { - if (!IS_ENABLED(CONFIG_VERY_BIG_RAM)) - return gd->ram_size; - - /* Limit stack to what we can reasonable map */ - return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : gd->ram_size); + return gd->ram_size; } /** diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 7dff3cc6913..7b932eb3890 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -195,12 +195,10 @@ * Environment Configuration */ -#define CONFIG_NETDEV "eth1" - -#define CONFIG_FDTFILE "mpc8379_rdb.dtb" +#define FDTFILE "mpc8379_rdb.dtb" #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" CONFIG_NETDEV "\0" \ + "netdev=eth1\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \ "tftpflash=tftp $loadaddr $uboot;" \ "protect off " __stringify(CONFIG_TEXT_BASE) \ @@ -214,7 +212,7 @@ "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \ " $filesize\0" \ "fdtaddr=780000\0" \ - "fdtfile=" CONFIG_FDTFILE "\0" \ + "fdtfile=" FDTFILE "\0" \ "ramdiskaddr=1000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ "console=ttyS0\0" \ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index d83563d6181..02d49c3d340 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -24,7 +24,6 @@ #ifdef CONFIG_SPIFLASH #ifdef CONFIG_NXP_ESBC -#define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #else #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 0f0cdb3a681..1a157a7da05 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -12,7 +12,6 @@ #define __CONFIG_H #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif @@ -46,10 +45,9 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CFG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CFG_SYS_INIT_L3_ADDR CONFIG_TEXT_BASE #ifdef CONFIG_PHYS_64BIT -#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ - CONFIG_RAMBOOT_TEXT_BASE) +#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_TEXT_BASE) #else #define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR #endif @@ -62,7 +60,6 @@ /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE @@ -88,7 +85,6 @@ #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CONFIG_FSL_CPLD #define CPLD_BASE 0xffdf0000 /* CPLD registers */ #ifdef CONFIG_PHYS_64BIT #define CPLD_BASE_PHYS 0xfffdf0000ull @@ -131,7 +127,6 @@ #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000} /* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index d5c9c05767a..19ae6399476 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -36,14 +36,5 @@ /* size in bytes reserved for initial data */ #include -/* There is no PHY directly connected so don't ask it for link status */ - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */ -#define CONFIG_PHY_BASE_ADR 0x01 -#endif /* CONFIG_CMD_NET */ #endif /* _CONFIG_SBX81LIFKW_H */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 23d37394e07..bdbf9d4758b 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -41,14 +41,5 @@ /* size in bytes reserved for initial data */ #include -/* There is no PHY directly connected so don't ask it for link status */ - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */ -#define CONFIG_PHY_BASE_ADR 0x01 -#endif /* CONFIG_CMD_NET */ #endif /* _CONFIG_SBX81LIFXCAT_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e815d9f81a1..4b443c75042 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -112,7 +112,6 @@ /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #if defined(CONFIG_TARGET_T1024RDB) @@ -269,7 +268,6 @@ #endif /* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 6fe0bd68280..dfad76e16f1 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -86,7 +86,6 @@ /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE @@ -247,7 +246,6 @@ #endif /* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 @@ -285,8 +283,6 @@ */ #define CFG_SYS_I2C_RTC_ADDR 0x68 -/*DVI encoder*/ -#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 #endif /* diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 79b3d7af4ea..24c1daf9985 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -78,7 +78,6 @@ /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ @@ -245,7 +244,6 @@ #endif /* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 2a32fe37aa9..c825e7fa0c6 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -78,7 +78,6 @@ /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ @@ -210,7 +209,6 @@ #endif /* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index d8c4de5b3d7..95735f3fcb1 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -16,7 +16,6 @@ #ifdef CONFIG_RAMBOOT_PBL #ifndef CONFIG_SDCARD -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #else #define RESET_VECTOR_OFFSET 0x27FFC @@ -60,7 +59,6 @@ /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE @@ -71,7 +69,6 @@ #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) /* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 diff --git a/include/configs/alt.h b/include/configs/alt.h index fe303fda78a..f2774001692 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -20,9 +20,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* FLASH */ -#define CONFIG_SPI_FLASH_QUAD - /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index 03e04e6e680..d70f0382300 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -49,9 +49,6 @@ */ #define CFG_SYS_FLASH_BANKS_SIZES {0x4000000} -/* max number of sectors on one chip */ -#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) - /* environments */ /* SPI FLASH */ diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 6b5f650811b..7078c2745c8 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -20,10 +20,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* SPI */ -#define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/blanche.h b/include/configs/blanche.h index fe09997e178..d4e0f677e67 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -22,9 +22,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* FLASH */ -#if !defined(CONFIG_MTD_NOR_FLASH) -#define CONFIG_SH_QSPI_BASE 0xE6B10000 -#else +#if defined(CONFIG_MTD_NOR_FLASH) #define CFG_SYS_FLASH_BASE 0x00000000 #define CFG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ #define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) } diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 35c5a4f1226..5cca1e18348 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -24,10 +24,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* SPI */ -#define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index 55e2d744c4a..e3519ed7516 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -22,9 +22,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 8a790400b46..e8918df69e0 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -14,10 +14,6 @@ #include #include -/* NAND support */ - -#define CONFIG_FDTADDR 0x84000000 - #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "fdt_addr_r=0x82000000\0" \ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 24cf554649b..82b2efdfe89 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -19,9 +19,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/dns325.h b/include/configs/dns325.h index 015bc78648f..1bfb741346a 100644 --- a/include/configs/dns325.h +++ b/include/configs/dns325.h @@ -16,13 +16,6 @@ /* Remove or override few declarations from mv-common.h */ -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#endif - /* * Enable GPI0 support */ diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index 33ae7d654b0..a6c1e9c6d02 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -28,10 +28,4 @@ "initrd=/boot/uInitrd\0" \ "bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0" -/* - * Ethernet Driver configuration - */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 - #endif /* _CONFIG_DOCKSTAR_H */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index b8f518612ee..f8afcc7826e 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -13,7 +13,6 @@ #include -#define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED 0x80000000 #ifndef CONFIG_QSPI_BOOT diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index fbd83d629c0..98322a54f63 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -24,10 +24,4 @@ "x_bootargs=console=ttyS0,115200\0" \ "x_bootargs_root=root=/dev/sda2 rootdelay=10\0" -/* - * Ethernet Driver configuration - */ -#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -#define CONFIG_PHY_BASE_ADR 0 - #endif /* _CONFIG_DREAMPLUG_H */ diff --git a/include/configs/ds109.h b/include/configs/ds109.h index 8553ea0b95f..8e7a86e0626 100644 --- a/include/configs/ds109.h +++ b/include/configs/ds109.h @@ -35,12 +35,4 @@ "ipaddr=192.168.1.5\0" \ "usb0Mode=host\0" -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable one port */ -#define CONFIG_PHY_BASE_ADR 8 -#endif /* CONFIG_CMD_NET */ - #endif /* _CONFIG_DS109_H */ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 717f49ca29d..029f13dad36 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -144,13 +144,5 @@ #define CFG_SYS_DDRUA 0x05 #define CFG_SYS_PJPAR 0xFF -/*----------------------------------------------------------------------- - * I2C - */ - -#ifdef CONFIG_CMD_DATE -#define CONFIG_I2C_RTC_ADDR 0x68 -#endif - #endif /* _CONFIG_M5282EVB_H */ /*---------------------------------------------------------------------*/ diff --git a/include/configs/efi-x86_app.h b/include/configs/efi-x86_app.h index 6061a6db0a4..17a78514026 100644 --- a/include/configs/efi-x86_app.h +++ b/include/configs/efi-x86_app.h @@ -8,8 +8,6 @@ #include -#undef CONFIG_TPM_TIS_BASE_ADDRESS - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=vidconsole\0" \ "stderr=vidconsole\0" diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 22e0fa5aabf..1742b1192fb 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -35,11 +35,11 @@ #if defined(CONFIG_ENV_IS_IN_MMC) /* RiOTboard */ -#define CONFIG_FDTFILE "imx6dl-riotboard.dtb" +#define FDTFILE "imx6dl-riotboard.dtb" #define CFG_SYS_FSL_USDHC_NUM 3 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) /* MarSBoard */ -#define CONFIG_FDTFILE "imx6q-marsboard.dtb" +#define FDTFILE "imx6q-marsboard.dtb" #define CFG_SYS_FSL_USDHC_NUM 2 #endif @@ -79,7 +79,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ CONSOLE_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ - "fdtfile=" CONFIG_FDTFILE "\0" \ + "fdtfile=" FDTFILE "\0" \ "finduuid=part uuid mmc 0:1 uuid\0" \ BOOTENV diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 52eb0be6761..3fd58d6bd4a 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -49,7 +49,6 @@ /* Ethernet */ #define CONFIG_PHY_ID 0 -#define CONFIG_MACB_SEARCH_PHY /* MMC */ #ifdef CONFIG_CMD_MMC diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 9b5c329bda1..8e277ce7ff2 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -27,8 +27,6 @@ /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 -#define CONFIG_RD_LVL - #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE #define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 7a9307ccc3d..934a4ef9d1f 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -8,8 +8,6 @@ #ifndef __CONFIG_EXYNOS5420_H #define __CONFIG_EXYNOS5420_H -#define CONFIG_VAR_SIZE_SPL - #define CONFIG_IRAM_TOP 0x02074000 #define CONFIG_PHY_IRAM_BASE 0x02020000 diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index cff910c1bd5..e22dd036ccb 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -15,10 +15,6 @@ /* select serial console configuration */ -/* IRAM Layout */ -#define CONFIG_IRAM_BASE 0x02100000 -#define CONFIG_IRAM_SIZE 0x58000 -#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE) #define CPU_RELEASE_ADDR secondary_boot_addr /* select serial console configuration */ diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 66eed9e14f8..1c86dcb1f6d 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -36,10 +36,4 @@ "kernel=/boot/uImage\0" \ "bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0" -/* - * Ethernet Driver configuration - */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 - #endif /* _CONFIG_GOFLEXHOME_H */ diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index 4954c5ca080..d196c4eda53 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -30,12 +30,4 @@ "fdt=/boot/guruplug-server-plus.dtb\0" \ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -#define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */ - #endif /* _CONFIG_GURUPLUG_H */ diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index 05192218d22..76fc4ac8b66 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -24,14 +24,6 @@ "fdt=/boot/ib62x0.dtb\0" \ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" -/* - * Ethernet driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */ - /* * SATA driver configuration */ diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index f2e3608d3a3..6d2104b3a1c 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -16,14 +16,4 @@ "kernel=/boot/uImage\0" \ "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" -/* - * Ethernet driver configuration - * - * This board has PCIe Wifi card, so allow Ethernet to be disabled - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 11 -#endif /* CONFIG_CMD_NET */ - #endif /* _CONFIG_ICONNECT_H */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index b846889541c..ea4964b13d6 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -18,11 +18,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index bbc58be511e..174a91c83e1 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -39,6 +39,5 @@ /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 9 -#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE #endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index bb91751d5d9..dc06d5943e5 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -53,7 +53,6 @@ /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 2 -#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE #define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */ #define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index a18158a7eb3..5d629452bae 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -39,6 +39,5 @@ /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 -#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE #endif /* __CONFIG_K2L_EVM_H */ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 532370e9184..80bff4b8937 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -149,7 +149,6 @@ /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 9c3174d0e02..f7bb97aa0e6 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -18,7 +18,6 @@ /* DDR */ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 828f9109634..7a66df548a3 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -14,13 +14,6 @@ * Enable platform initialisation via misc_init_r() function */ -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#endif - /* * Enable GPI0 support */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index abe470fe890..794c1fcbed0 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -48,7 +48,6 @@ * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_SETUP_INITRD_TAG #define CONFIG_EXTRA_ENV_SETTINGS \ "bootenvfile=uEnv.txt\0" \ "fdtfile=da850-lego-ev3.dtb\0" \ diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index b190bfe9c8e..2ccb20192d4 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -12,7 +12,6 @@ /* Link Definitions */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e54e903a8a9..d0380b33732 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -31,7 +31,6 @@ /* Link Definitions */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index dab57382edd..1dca7f0aa6b 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -107,7 +107,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE #endif #ifdef CONFIG_NAND_BOOT diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 12c4853ea96..043904197f0 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -82,7 +82,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE #ifdef CONFIG_NAND_BOOT #define CFG_SYS_NAND_U_BOOT_SIZE (1024 << 10) diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 4ed5481c3e7..250891e9e30 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -31,7 +31,6 @@ /* Link Definitions */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 1759d25f3a3..5e03a962d10 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -45,7 +45,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE /* IFC Timing Params */ #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index e9b8ad0c0b7..c4e5f4928d2 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -123,7 +123,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE #endif #ifdef CONFIG_NAND_BOOT diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index f3904e7b3f7..ad766b034b1 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -50,7 +50,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE /* * CPLD diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 57429d4bbe3..bcba8d81c04 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -29,7 +29,6 @@ /* Link Definitions */ #define CFG_SYS_FSL_QSPI_BASE 0x20000000 -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index dc9cded49fd..49ad1469262 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -97,7 +97,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index e2444cd8eb4..9033f6e937c 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -81,7 +81,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_BRDCFG4_OFFSET 0x54 diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index e82456fd814..bd78bdb793a 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -16,7 +16,6 @@ /* Link Definitions */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 4e6d40afbf1..7d3e8912c3b 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -98,7 +98,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE #define QIXIS_LBMAP_SWITCH 0x06 #define QIXIS_LBMAP_MASK 0x0f diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 8f36958f710..4573906115e 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -95,7 +95,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE #define QIXIS_LBMAP_SWITCH 0x06 #define QIXIS_LBMAP_MASK 0x0f diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index a469c83fa4e..3347920f03f 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -13,7 +13,6 @@ #define CFG_SYS_FLASH_BASE 0x20000000 /* DDR */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL diff --git a/include/configs/malta.h b/include/configs/malta.h index 65f4b05649b..8ba04b4e6c3 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -11,8 +11,6 @@ */ #define CONFIG_MALTA -#define CONFIG_MEMSIZE_IN_BYTES - /* * CPU Configuration */ diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 7c8c67f4469..b6e680bcc78 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -10,7 +10,6 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED 0x1c000000 #define CFG_SYS_INIT_SP_OFFSET 0x800000 diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index 99b09ad41e7..f6ab486fa29 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -15,10 +15,7 @@ /* Environment */ -/* Defines for SPL */ - -#define CONFIG_SPI_ADDR 0x30000000 -#define CFG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) +#define CFG_SYS_UBOOT_BASE (0x30000000 + CONFIG_SPL_PAD_TO) /* SPL -> Uboot */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 30f27e7f0c1..32e0e06617e 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -86,9 +86,4 @@ #define CFG_SYS_NAND_BASE 0x60000000 #endif -/* SPI */ -#ifdef CONFIG_CMD_SPI -#define CONFIG_SPI_HALF_DUPLEX -#endif - #endif /* __CONFIGS_MXS_H__ */ diff --git a/include/configs/nas220.h b/include/configs/nas220.h index 1b7eb343348..85691ca94f0 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -39,16 +39,4 @@ "bootargs=console=ttyS0,115200\0" \ "autostart=no\0" -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 8 -#endif /* CONFIG_CMD_NET */ - -/* - * EFI partition - */ - #endif /* _CONFIG_NAS220_H */ diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index 62f07011809..e2ad77072cd 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -46,8 +46,4 @@ #endif /* CONFIG_SPL_BUILD */ -/* Ethernet driver configuration */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 1 - #endif /* _CONFIG_NSA310S_H */ diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index baa452156ec..21002f99dc8 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -18,9 +18,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 006f06e6af5..2cec20ca425 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -33,26 +33,4 @@ "x_bootcmd_usb=usb start\0" \ "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -# ifdef CONFIG_BOARD_IS_OPENRD_BASE -# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -# else -# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -# endif -# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE -# define CONFIG_PHY_BASE_ADR 0x0 -# define PHY_NO "88E1121" -# else -# define CONFIG_PHY_BASE_ADR 0x8 -# define PHY_NO "88E1116" -# endif -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ - #endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/origen.h b/include/configs/origen.h index 6633d541a31..a608df44e80 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -38,10 +38,4 @@ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ "source ${loadaddr}\0" -/* MIU (Memory Interleaving Unit) */ -#define CONFIG_MIU_2BIT_21_7_INTERLEAVED - -#define RESERVE_BLOCK_SIZE (512) -#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ - #endif /* __CONFIG_H */ diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index ecd0405d297..653b4c583ad 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -19,9 +19,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* _P2371_0000_H */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 7f942888e74..2913d5304be 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -19,9 +19,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* _P2371_2180_H */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 50cddb4a4ac..e78e3c4d6b0 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -19,9 +19,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* _P2571_H */ diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h index ec1a8634e71..bab02dc2d6e 100644 --- a/include/configs/p3450-0000.h +++ b/include/configs/p3450-0000.h @@ -23,9 +23,6 @@ func(PXE, pxe, na) \ func(DHCP, dhcp, na) -/* Environment at end of QSPI, in the VER partition */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #define BOARD_EXTRA_ENV_SETTINGS \ "preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \ "load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 9fd897958a4..fa08744b6fe 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -159,11 +159,6 @@ /* PSRAM */ #define PHYS_PSRAM 0x70000000 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ -/* Slave EBI1, PSRAM connected */ -#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ - AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ - AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ - AT91_MATRIX_SCFG_SLOT_CYCLE(255)) /* USB */ #define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h index 085732214e5..fc9f113dee6 100644 --- a/include/configs/pogo_e02.h +++ b/include/configs/pogo_e02.h @@ -23,10 +23,4 @@ "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \ "ext2load usb 0:1 0x01100000 /uInitrd\0" -/* - * Ethernet Driver configuration - */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 - #endif /* _CONFIG_POGO_E02_H */ diff --git a/include/configs/pogo_v4.h b/include/configs/pogo_v4.h index b5ce2dd13d0..239d33d8e9d 100644 --- a/include/configs/pogo_v4.h +++ b/include/configs/pogo_v4.h @@ -69,10 +69,4 @@ BOOTENV #endif /* CONFIG_SPL_BUILD */ -/* - * Ethernet Driver configuration - */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 - #endif /* _CONFIG_POGO_V4_H */ diff --git a/include/configs/porter.h b/include/configs/porter.h index 88fa65e0ffc..e0f77f358b9 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -21,9 +21,6 @@ #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) -/* FLASH */ -#define CONFIG_SPI_FLASH_QUAD - /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index d0561899586..20be4af4628 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -29,7 +29,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index e9cbd253824..86012adfb36 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -28,7 +28,6 @@ #define DRAM_RSV_SIZE 0x08000000 #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) -#define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) /* ENV setting */ diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index e4595817156..a721f27ec00 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -10,16 +10,6 @@ #define CONFIG_IRAM_BASE 0xff8c0000 -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) -#else -/* BSS setup */ -#endif - -/* MMC/SD IP block */ -#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000 - -/* RAW SD card / eMMC locations. */ - /* FAT sd card locations. */ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000 diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 19701ccce22..d7923967a72 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -21,10 +21,4 @@ "x_bootcmd_usb=usb start\0" \ "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" -/* - * Ethernet Driver configuration - */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 - #endif /* _CONFIG_SHEEVAPLUG_H */ diff --git a/include/configs/silk.h b/include/configs/silk.h index 58613effaf4..6d605edf788 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -21,9 +21,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* FLASH */ -#define CONFIG_SPI_FLASH_QUAD - /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 0392530c0ad..0cb70762d92 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -12,8 +12,6 @@ #include #include -#define CONFIG_SMDK5420 /* which is in a SMDK5420 */ - #define CFG_SYS_SDRAM_BASE 0x20000000 /* DRAM Memory Banks */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 601c16ea453..38de1fa9849 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -34,9 +34,6 @@ /* FLASH and environment organization */ -#define RESERVE_BLOCK_SIZE (512) -#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ - /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_ENV_SROM_BANK 1 diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index 432144cb40c..caff0cf2523 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -11,15 +11,9 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ /* Ethernet on SoC (EMAC) */ -#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII /* The PHY is autodetected, so no MII PHY address is needed here */ #define PHY_ANEG_TIMEOUT 8000 -/* Enable SPI NOR flash reset, needed for SPI booting */ -#define CONFIG_SPI_N25Q256A_RESET - -/* Environment setting for SPI flash */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 2a076716023..11d84022331 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -16,9 +16,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ -#define CONFIG_SOCRATES 1 - /* * Only possible on E500 Version 2 or newer cores. */ @@ -55,7 +52,6 @@ #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM /* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ diff --git a/include/configs/stout.h b/include/configs/stout.h index f49e88cb17c..977c0adc5f0 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -25,9 +25,6 @@ /* SCIF */ #define CONFIG_SCIF_A -/* SPI */ -#define CONFIG_SPI_FLASH_QUAD - /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 69926890010..a2b6a1f57d7 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -14,7 +14,6 @@ #define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ #define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */ -#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */ #define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE #define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index 09879663701..c98322cf084 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -16,12 +16,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -/* SPI */ -#define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h index b2dc04a975a..a4eb4bf4aaf 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -20,9 +20,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/vinco.h b/include/configs/vinco.h index 9f72bdde816..1c1789ac3fb 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -39,9 +39,6 @@ /* USB device */ -/* Ethernet Hardware */ -#define CONFIG_MACB_SEARCH_PHY - #ifdef CONFIG_SPI_BOOT /* bootstrap + u-boot + env + linux in serial flash */ /* Use our own mapping for the VInCo platform */ diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 9bf2462010d..d71108dd318 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -10,22 +10,6 @@ #ifndef __CONFIG_X86_COMMON_H #define __CONFIG_X86_COMMON_H -/* - * High Level Configuration Options - * (easy to change) - */ - -/* Generic TPM interfaced through LPC bus */ -#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 - -/*----------------------------------------------------------------------- - * Serial Configuration - */ - -/* - * Miscellaneous configurable options - */ - /*----------------------------------------------------------------------- * CPU Features */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 3e604894ad4..9f1f2d90dbe 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -34,9 +34,6 @@ #define CONFIG_FEC_ENET_DEV 0 #define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_UBOOT_SECTOR_START 0x2 -#define CONFIG_UBOOT_SECTOR_COUNT 0x3fe - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ @@ -75,8 +72,8 @@ "bootz; " \ "fi;\0" \ "uboot=ccv/u-boot.imx\0" \ - "uboot_start="__stringify(CONFIG_UBOOT_SECTOR_START)"\0" \ - "uboot_size="__stringify(CONFIG_UBOOT_SECTOR_COUNT)"\0" \ + "uboot_start=0x2\0" \ + "uboot_size=0x3fe\0" \ "update_uboot=if tftp ${uboot}; then " \ "if itest ${filesize} > 0; then " \ "mmc dev 0 1;" \ -- cgit v1.3.1 From acdf89ec060931ae4c87780ab0e65a6783ccd94b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:32 -0500 Subject: Convert CONFIG_KSNET_NETCP_V1_0 et al to Kconfig This converts the following to Kconfig: CONFIG_KSNET_NETCP_V1_0 CONFIG_KSNET_NETCP_V1_5 Signed-off-by: Tom Rini --- configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + drivers/net/ti/Kconfig | 13 +++++++++++++ include/configs/k2e_evm.h | 1 - include/configs/k2g_evm.h | 1 - include/configs/k2hk_evm.h | 1 - include/configs/k2l_evm.h | 1 - 7 files changed, 15 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index b0069fd60b0..2bcf2265c7e 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -87,6 +87,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_MII=y CONFIG_DRIVER_TI_KEYSTONE_NET=y +CONFIG_KSNET_NETCP_V1_0=y CONFIG_PHY=y CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 9ca26ae61f5..94ab680343b 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -62,6 +62,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_MII=y CONFIG_DRIVER_TI_KEYSTONE_NET=y +CONFIG_KSNET_NETCP_V1_0=y CONFIG_PHY=y CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index 59c96d862dd..e13dbc94018 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -25,6 +25,19 @@ config DRIVER_TI_KEYSTONE_NET help This driver supports the TI Keystone 2 Ethernet subsystem +choice + prompt "TI Keystone 2 Ethernet NETCP IP revision" + depends on DRIVER_TI_KEYSTONE_NET + default KSNET_NETCP_V1_5 + +config KSNET_NETCP_V1_0 + bool "NETCP version 1.0" + +config KSNET_NETCP_V1_5 + bool "NETCP version 1.5" + +endchoice + config TI_AM65_CPSW_NUSS bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver" depends on ARCH_K3 diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 174a91c83e1..1283f450b32 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -37,7 +37,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* Network */ -#define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 9 #endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index dc06d5943e5..fd3708ba81a 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -51,7 +51,6 @@ "name_fs=arago-base-tisdk-image-k2g-evm.cpio\0" /* Network */ -#define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 2 #define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 68cbe98b553..36e3c59d1c5 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -37,7 +37,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* Network */ -#define CONFIG_KSNET_NETCP_V1_0 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 #endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 5d629452bae..cb7b0367810 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -37,7 +37,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* Network */ -#define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 #endif /* __CONFIG_K2L_EVM_H */ -- cgit v1.3.1 From 960379d4501fcb64ca20810c4fc4fe74806ede7b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:33 -0500 Subject: Convert CONFIG_L2_CACHE to Kconfig This converts the following to Kconfig: CONFIG_L2_CACHE Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/Kconfig | 3 +++ configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PA_NAND_defconfig | 1 + configs/P1010RDB-PA_NOR_defconfig | 1 + configs/P1010RDB-PA_SDCARD_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_NAND_defconfig | 1 + configs/P1010RDB-PB_NOR_defconfig | 1 + configs/P1010RDB-PB_SDCARD_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 1 + configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 1 + configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig | 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 1 + configs/P2020RDB-PC_SDCARD_defconfig | 1 + configs/P2020RDB-PC_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_defconfig | 1 + configs/socrates_defconfig | 1 + include/configs/MPC8548CDS.h | 5 ----- include/configs/P1010RDB.h | 5 ----- include/configs/p1_p2_rdb_pc.h | 5 ----- include/configs/socrates.h | 5 ----- 45 files changed, 43 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 721dafc5ab1..36519613a2c 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1297,6 +1297,9 @@ config SYS_NUM_TLBCAMS Number of TLB CAM entries for Book-E chips. 64 for E500MC, 16 for other E500 SoCs. +config L2_CACHE + bool "Enable L2 cache support" + if HETROGENOUS_CLUSTERS config SYS_MAPLE diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 241cb80fde9..05034ce2e46 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -13,6 +13,7 @@ CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_USE_UBOOTPATH=y CONFIG_UBOOTPATH="8548cds/u-boot.bin" diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 5af056bd4f4..965c37e45ec 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -13,6 +13,7 @@ CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_USE_UBOOTPATH=y CONFIG_UBOOTPATH="8548cds/u-boot.bin" diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 34d1938129f..004175c8048 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -13,6 +13,7 @@ CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_TARGET_MPC8548CDS_LEGACY=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 3fb993e201c..c12948ae7c8 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index dc6dd717df9..6a320713ebd 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -9,6 +9,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index bc29526f636..e3b786d4efd 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 5c42d5ee367..e6ce59e2971 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index b6e68d27885..99b94a061df 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index fe24faa1757..071123362f5 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -9,6 +9,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 110a9b4ad3d..9f2afcdadc9 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index fcd60f7a4ef..7c64fdcf6f0 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 76919c3881f..87953b8f190 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index b2972586946..bf7078015e2 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -9,6 +9,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index df80488cff1..4dbf8695e4e 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index d27ea17a0b6..f5bcffbd490 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 88de4f9b92e..82f29bed54e 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 2e86aec5958..985243cebd8 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -9,6 +9,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index d5bbd6dca54..3dfb509c8ad 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 66efe739e99..f3d399f84f7 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 0f082f6e6e2..de04556b224 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 88e10af29a3..2d201bf55e9 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 729e93eae23..a6b7a4abf50 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 2860c286d71..58f24755714 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 0958a0a94b5..cf47bd49c7a 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 81bb26cb8fd..3a86a9ef525 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 481009f3076..9fe2b1d88f5 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 49207eb65a0..17bde92263b 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 7e22b4e34c5..2f768c06705 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 62b25f03983..6cb3be08dc2 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index f5864dea4db..0eb2b3ab74b 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index ca040072884..b0ccaa1cfde 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 2420217b890..c53c4c6c7cc 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 22b0023ec6c..0ac74287fde 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 8c95203a4a0..9da9ef0c691 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index b87c965d50b..bb5df66c749 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 1d33cf6750b..4758e0e3715 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 8d44e5b425c..1584a8a7c3a 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 9155768c15c..6acb0bcb12e 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 4f3be9eb242..2afef4a5eb0 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 4cc50d35589..46be662037e 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -10,6 +10,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_SOCRATES=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MONITOR_LEN=393216 CONFIG_FIT=y diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 1f1eacdb691..3d0c2192ee1 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -17,11 +17,6 @@ #include #endif -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ - /* * Only possible on E500 Version 2 or newer cores. */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 02d49c3d340..c398ece7845 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -95,11 +95,6 @@ #endif #endif -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ - /* DDR Setup */ #define SPD_EEPROM_ADDRESS 0x52 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index ee25990b034..c05904a813d 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -109,11 +109,6 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE - #define CFG_SYS_CCSRBAR 0xffe00000 #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 11d84022331..0547ed02563 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -34,11 +34,6 @@ * in the README.mpc85xxads. */ -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ - #define CFG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ #undef CFG_SYS_DRAM_TEST /* memory test, takes time */ -- cgit v1.3.1 From 2cc61a631bb8ae1acfadac9840abaa803091b7ac Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:34 -0500 Subject: malta: Rename CONFIG_MALTA to CONFIG_TARGET_MALTA Fixup this last remnant of CONFIG_MALTA. Cc: Paul Burton Signed-off-by: Tom Rini --- drivers/rtc/mc146818.c | 2 +- include/configs/malta.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index 122691b9784..03ce081d576 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -13,7 +13,7 @@ #include #include -#if defined(CONFIG_X86) || defined(CONFIG_MALTA) +#if defined(CONFIG_X86) || defined(CONFIG_TARGET_MALTA) #include #define in8(p) inb(p) #define out8(p, v) outb(v, p) diff --git a/include/configs/malta.h b/include/configs/malta.h index 8ba04b4e6c3..c17a4a4a8e5 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -9,7 +9,6 @@ /* * System configuration */ -#define CONFIG_MALTA /* * CPU Configuration -- cgit v1.3.1 From 829e9d223657f5779668bb7a46e902a85e09b664 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:35 -0500 Subject: ddr: fsl: Remove CONFIG_MEM_INIT_VALUE The way all of the memory init code here works is that we pass 0xDEADBEEF around for the initial value (as it's a well known 'poison' value and so easily recognized in debuggers, etc). The only point of this CONFIG symbol was to pass in a different value for that purpose. Drop this symbol and cleanup the code slightly. Signed-off-by: Tom Rini --- arch/powerpc/include/asm/fsl_dma.h | 2 +- drivers/ddr/fsl/ctrl_regs.c | 17 ++--------------- drivers/ddr/fsl/mpc85xx_ddr_gen1.c | 2 +- drivers/dma/fsl_dma.c | 4 ++-- include/configs/MPC8548CDS.h | 2 -- include/configs/P1010RDB.h | 2 -- include/configs/T102xRDB.h | 3 --- include/configs/T104xRDB.h | 3 --- include/configs/T208xQDS.h | 7 ------- include/configs/T208xRDB.h | 7 ------- include/configs/T4240RDB.h | 7 ------- include/configs/kontron_sl28.h | 3 --- include/configs/ls1021aqds.h | 4 ---- include/configs/ls1043aqds.h | 4 ---- include/configs/ls1043ardb.h | 6 ------ include/configs/ls1046aqds.h | 4 ---- include/configs/ls1046ardb.h | 2 -- include/configs/ls1088aqds.h | 1 - include/configs/ls1088ardb.h | 1 - include/configs/ls2080aqds.h | 1 - include/configs/ls2080ardb.h | 1 - include/configs/lx2160a_common.h | 1 - include/configs/socrates.h | 3 --- 23 files changed, 6 insertions(+), 81 deletions(-) (limited to 'include') diff --git a/arch/powerpc/include/asm/fsl_dma.h b/arch/powerpc/include/asm/fsl_dma.h index 727f4a7e92c..1459db74bee 100644 --- a/arch/powerpc/include/asm/fsl_dma.h +++ b/arch/powerpc/include/asm/fsl_dma.h @@ -117,7 +117,7 @@ typedef struct fsl_dma { void dma_init(void); int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n); #if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) -void dma_meminit(uint val, uint size); +void dma_meminit(uint size); #endif #endif diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index df7ec484651..759921bc582 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -938,7 +938,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num, #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* Use the DDR controller to auto initialize memory. */ d_init = popts->ecc_init_using_memctl; - ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; + ddr->ddr_data_init = 0xDEADBEEF; debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); #else /* Memory will be initialized via DMA, or not at all. */ @@ -1842,19 +1842,6 @@ static void set_ddr_sdram_mode(const unsigned int ctrl_num, } #endif -/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */ -static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int init_value; /* Initialization value */ - -#ifdef CONFIG_MEM_INIT_VALUE - init_value = CONFIG_MEM_INIT_VALUE; -#else - init_value = 0xDEADBEEF; -#endif - ddr->ddr_data_init = init_value; -} - /* * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) * The old controller on the 8540/60 doesn't have this register. @@ -2537,7 +2524,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num, set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm); set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm); - set_ddr_data_init(ddr); + ddr->ddr_data_init = 0xDEADBEEF; set_ddr_sdram_clk_cntl(ddr, popts); set_ddr_init_addr(ddr); set_ddr_init_ext_addr(ddr); diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c index 0f1e99eeb03..16186bdbae7 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -73,7 +73,7 @@ ddr_enable_ecc(unsigned int dram_size) struct ccsr_ddr __iomem *ddr = (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR); - dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); + dma_meminit(dram_size); /* * Enable errors for ECC. diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index cd78e45d888..700df2236bd 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -133,7 +133,7 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) { */ #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \ !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))) -void dma_meminit(uint val, uint size) +void dma_meminit(uint size) { uint *p = 0; uint i = 0; @@ -142,7 +142,7 @@ void dma_meminit(uint val, uint size) if (((uint)p & 0x1f) == 0) ppcDcbz((ulong)p); - *p = (uint)CONFIG_MEM_INIT_VALUE; + *p = (uint)0xDEADBEEF; if (((uint)p & 0x1c) == 0x1c) ppcDcbf((ulong)p); diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 3d0c2192ee1..1e3ba6de6e7 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -26,8 +26,6 @@ /* DDR Setup */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index c398ece7845..2267a7a9c8b 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -98,8 +98,6 @@ /* DDR Setup */ #define SPD_EEPROM_ADDRESS 0x52 -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - #ifndef __ASSEMBLY__ extern unsigned long get_sdram_size(void); #endif diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 4b443c75042..4794c5a84d1 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -94,9 +94,6 @@ * These can be toggled for performance analysis, otherwise use default. */ #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif /* * Config the L3 Cache as L3 SRAM diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index dfad76e16f1..5bdc2105f56 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -64,9 +64,6 @@ * These can be toggled for performance analysis, otherwise use default. */ #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif /* * Config the L3 Cache as L3 SRAM diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 24c1daf9985..4b6bdaa3440 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -59,13 +59,6 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index c825e7fa0c6..fab40f792af 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -59,13 +59,6 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 95735f3fcb1..41565f284c6 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -40,13 +40,6 @@ #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index f7bb97aa0e6..a073a06c827 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -15,9 +15,6 @@ #undef CFG_SYS_MEM_RESERVE_SECURE #endif -/* DDR */ -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef - #define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index e49588489c1..fead9edeccd 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -22,10 +22,6 @@ #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - /* * IFC Definitions */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 1dca7f0aa6b..7ccbb20bf2e 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -12,10 +12,6 @@ #define SPD_EEPROM_ADDRESS 0x51 -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - #ifdef CONFIG_SYS_DPAA_FMAN #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 043904197f0..c8a6f0146aa 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -9,12 +9,6 @@ #include "ls1043a_common.h" -/* Physical Memory Map */ - -#ifndef CONFIG_SPL -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - /* * NOR Flash Definitions */ diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index c4e5f4928d2..4b4bd7cbe48 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -12,10 +12,6 @@ #define SPD_EEPROM_ADDRESS 0x51 -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - #ifdef CONFIG_SYS_DPAA_FMAN #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index ad766b034b1..0e42a51fc59 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -13,8 +13,6 @@ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef - #if defined(CONFIG_QSPI_BOOT) #define CFG_SYS_UBOOT_BASE 0x40100000 #endif diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 49ad1469262..3391540c6e3 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -14,7 +14,6 @@ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4) -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS 0x51 diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 9033f6e937c..1ddf0687f43 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -15,7 +15,6 @@ #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS 0x51 diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 7d3e8912c3b..4a52fcdfddb 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -16,7 +16,6 @@ #define CFG_SYS_I2C_FPGA_ADDR 0x66 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4) -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS3 0x53 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 4573906115e..b8ab501c98e 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -21,7 +21,6 @@ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4) -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS3 0x53 diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 3347920f03f..c1a98fd3e4c 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -18,7 +18,6 @@ #define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL #define CFG_SYS_SDRAM_SIZE 0x200000000UL #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS3 0x53 diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 0547ed02563..4c752091fb5 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -42,9 +42,6 @@ #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE -- cgit v1.3.1 From e52fca2236153341c495bff3c5631fcced291ffe Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:36 -0500 Subject: Convert CONFIG_MONITOR_IS_IN_RAM to Kconfig This converts the following to Kconfig: CONFIG_MONITOR_IS_IN_RAM As part of this, reword some of the documentation slightly to reflect that this is in Kconfig and not a define now. Signed-off-by: Tom Rini --- arch/Kconfig | 4 ++++ board/cobra5272/README | 27 +++++++++------------------ configs/10m50_defconfig | 1 + configs/3c120_defconfig | 1 + doc/arch/m68k.rst | 4 ++-- include/configs/10m50_devboard.h | 1 - include/configs/3c120_devboard.h | 1 - include/configs/M5249EVB.h | 2 -- include/configs/M5272C3.h | 2 -- include/configs/M5282EVB.h | 2 -- include/configs/astro_mcf5373l.h | 25 ------------------------- include/configs/cobra5272.h | 21 --------------------- include/configs/eb_cpu5282.h | 2 -- 13 files changed, 17 insertions(+), 76 deletions(-) (limited to 'include') diff --git a/arch/Kconfig b/arch/Kconfig index 5ffbdc6a3f7..5f2b72f5350 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -380,6 +380,10 @@ config SYS_IMMR Address for the Internal Memory-Mapped Registers (IMMR) window used to configure the features of many Freescale / NXP SoCs. +config MONITOR_IS_IN_RAM + bool "U-Boot is loaded in to RAM by a pre-loader" + depends on M68K || NIOS2 + config SKIP_LOWLEVEL_INIT bool "Skip the calls to certain low level initialization functions" depends on ARM || MIPS || RISCV diff --git a/board/cobra5272/README b/board/cobra5272/README index ac62e557a07..11abcfacdb6 100644 --- a/board/cobra5272/README +++ b/board/cobra5272/README @@ -77,21 +77,16 @@ in dir ./u-boot-x-x-x/ please first check: - in ./include/configs/cobra5272.h + in ./configs/cobra5272_defconfig - CONFIG_MONITOR_IS_IN_RAM has to be undefined, e. g. as follows: - - #if 0 - #define CONFIG_MONITOR_IS_IN_RAM - /* define if monitor is started from a pre-loader */ - #endif + CONFIG_MONITOR_IS_IN_RAM has to be not present in the file => u-boot as single bootloader starting from flash - in board/cobra5272/config.mk CONFIG_TEXT_BASE should be + in configs/cobra5272_defconfig CONFIG_TEXT_BASE should be - CONFIG_TEXT_BASE = 0xffe00000 + CONFIG_TEXT_BASE=0xffe00000 => linking address for u-boot as single bootloader stored in flash @@ -115,22 +110,18 @@ in dir ./u-boot-x-x-x/ host> make distclean please modify the settings: + in ./configs/cobra5272_defconfig - in ./include/configs/cobra5272.h - - CONFIG_MONITOR_IS_IN_RAM now has to be defined, e. g. as follows: + CONFIG_MONITOR_IS_IN_RAM now has to be enabled, e. g. as follows: - #if 1 - #define CONFIG_MONITOR_IS_IN_RAM - /*define if monitor is started from a pre-loader */ - #endif + CONFIG_MONITOR_IS_IN_RAM=y => u-boot as RAM version, chainloaded by another bootloader or using bdm cable - in board/cobra5272/config.mk CONFIG_TEXT_BASE should be + in configs/cobra5272_defconfig CONFIG_TEXT_BASE should be - CONFIG_TEXT_BASE = 0x00020000 + CONFIG_TEXT_BASE=0x00020000 => target linking address for RAM diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig index 28966e0d0a4..7dc9d2ed27b 100644 --- a/configs/10m50_defconfig +++ b/configs/10m50_defconfig @@ -1,5 +1,6 @@ CONFIG_NIOS2=y CONFIG_SYS_CONFIG_NAME="10m50_devboard" +CONFIG_MONITOR_IS_IN_RAM=y CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig index 8c421f099be..46dfaf827ac 100644 --- a/configs/3c120_defconfig +++ b/configs/3c120_defconfig @@ -1,5 +1,6 @@ CONFIG_NIOS2=y CONFIG_SYS_CONFIG_NAME="3c120_devboard" +CONFIG_MONITOR_IS_IN_RAM=y CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=1 diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst index 770327fea21..a9180fd7850 100644 --- a/doc/arch/m68k.rst +++ b/doc/arch/m68k.rst @@ -93,10 +93,10 @@ Configuration to use a pre-loader ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ If U-Boot should be loaded to RAM and started by a pre-loader -CONFIG_MONITOR_IS_IN_RAM must be defined. If it is defined the +CONFIG_MONITOR_IS_IN_RAM must be enabled. If it is enabled the initial vector table and basic processor initialization will not be compiled in. The start address of U-Boot must be adjusted in -the boards config header file (CONFIG_SYS_MONITOR_BASE) and Makefile +the boards defconfig file (CONFIG_SYS_MONITOR_BASE) and Makefile (CONFIG_TEXT_BASE) to the load address. ColdFire CPU specific options/settings diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 3a4fbc6eab8..b898ec0cc3e 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -32,6 +32,5 @@ */ #define CFG_SYS_SDRAM_BASE 0xc8000000 #define CFG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_MONITOR_IS_IN_RAM #endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index ab889180eed..e67338c202c 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -28,6 +28,5 @@ */ #define CFG_SYS_SDRAM_BASE 0xD0000000 #define CFG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_MONITOR_IS_IN_RAM #endif /* __CONFIG_H */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 0e38eeb4a36..c71130909fc 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -20,8 +20,6 @@ #define CFG_SYS_UART_PORT (0) -#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ - /* * Clock configuration: enable only one of the following options */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index c58d19c810f..6aae584afda 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -19,8 +19,6 @@ #define CFG_SYS_UART_PORT (0) -#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ - /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index e23439fd782..7cfe7a2da3e 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -19,8 +19,6 @@ #define CFG_SYS_UART_PORT (0) -#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ - /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 62aa99342a0..6aef3bd86f7 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -38,16 +38,6 @@ #error No card type defined! #endif -/* - * CONFIG_RAM defines if u-boot is loaded via BDM (or started from - * a different bootloader that has already performed RAM setup) or - * started directly from flash, which is the regular case for production - * boards. - */ -#ifdef CONFIG_RAM -#define CONFIG_MONITOR_IS_IN_RAM -#endif - /* I2C */ /* @@ -69,21 +59,6 @@ #define CFG_SYS_UART_PORT (2) #define CFG_SYS_UART2_ALT3_GPIO -/* - * Configuration for environment - * Environment is located in the last sector of the flash - */ - -#ifndef CONFIG_MONITOR_IS_IN_RAM -#else -/* - * environment in RAM - This is used to use a single PC-based application - * to load an image, load U-Boot, load an environment and then start U-Boot - * to execute the commands from the environment. Feedback is done via setting - * and reading memory locations. - */ -#endif - /* here we put our FPGA configuration... */ /* Define user parameters that have to be customized most likely */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 8c83c3ac06a..cd50ffe98d0 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -42,27 +42,6 @@ #define CFG_SYS_UART_PORT (0) -/* --- - * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different - * bootloader residing in flash ('chainloading'); if you want to use - * chainloading or want to compile a u-boot binary that can be loaded into - * RAM via BDM set - * "#if 0" to "#if 1" - * You will need a first stage bootloader then, e. g. colilo or a working BDM - * cable (Background Debug Mode) - * - * Setting #if 0: u-boot will start from flash and relocate itself to RAM - * - * Please do not forget to modify the setting of CONFIG_TEXT_BASE - * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000) - * - * --- - */ - -#if 0 -#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */ -#endif - /* --- * Configuration for environment * Environment is embedded in u-boot in the second sector of the flash diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 029f13dad36..b267b74b159 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -14,8 +14,6 @@ #define CFG_SYS_UART_PORT (0) -#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ - /*----------------------------------------------------------------------* * Options * *----------------------------------------------------------------------*/ -- cgit v1.3.1 From 71894173bb15fffacb166bdc04168a0fcb86cbbf Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:37 -0500 Subject: Convert CONFIG_MXC_NAND_HWECC to Kconfig This converts the following to Kconfig: CONFIG_MXC_NAND_HWECC Signed-off-by: Tom Rini --- configs/m53menlo_defconfig | 1 + drivers/mtd/nand/raw/Kconfig | 4 ++++ include/configs/m53menlo.h | 1 - 3 files changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index b70d10433d7..70df2b5fd24 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -88,6 +88,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_MXC=y +CONFIG_MXC_NAND_HWECC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 25b829f11cd..1e4e5c92067 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -479,6 +479,10 @@ config SYS_NAND_SIZE depends on NAND_MXC && SPL_NAND_SUPPORT default 268435456 +config MXC_NAND_HWECC + bool "Hardware ECC support in MXC NAND" + depends on NAND_MXC + config NAND_MXS bool "MXS NAND support" depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 189b2113f75..d42ad9acb40 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -48,7 +48,6 @@ #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CFG_SYS_NAND_LARGEPAGE -#define CONFIG_MXC_NAND_HWECC #endif /* -- cgit v1.3.1 From 3348c6b6a5cbf71bde837bf80cf962ee6aaeff20 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:38 -0500 Subject: etamin: Rework CONFIG_NAND_CS_INIT Enable this in the board Kconfig file, but then check for it via CONFIG_IS_ENABLED so that it will only be true in the non-SPL case, as is done today. As part of this we move some defines local to where they are used as it's board specific. Cc: Samuel Egli Signed-off-by: Tom Rini --- board/siemens/common/board.c | 2 +- board/siemens/draco/Kconfig | 2 ++ board/siemens/draco/board.c | 9 ++++++++- include/configs/etamin.h | 12 +----------- 4 files changed, 12 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 2efede62aa5..8fa9197a6df 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -93,7 +93,7 @@ int board_init(void) gpmc_init(); -#ifdef CONFIG_NAND_CS_INIT +#if CONFIG_IS_ENABLED(NAND_CS_INIT) board_nand_cs_init(); #endif diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig index a699c7d46f7..1eb8a4886f4 100644 --- a/board/siemens/draco/Kconfig +++ b/board/siemens/draco/Kconfig @@ -60,4 +60,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "etamin" +config NAND_CS_INIT + def_bool y endif diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c index f898bba4b0e..8874659013f 100644 --- a/board/siemens/draco/board.c +++ b/board/siemens/draco/board.c @@ -370,7 +370,14 @@ U_BOOT_CMD( #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ -#ifdef CONFIG_NAND_CS_INIT +#if CONFIG_IS_ENABLED(NAND_CS_INIT) +#define ETAMIN_NAND_GPMC_CONFIG1 0x00000800 +#define ETAMIN_NAND_GPMC_CONFIG2 0x001e1e00 +#define ETAMIN_NAND_GPMC_CONFIG3 0x001e1e00 +#define ETAMIN_NAND_GPMC_CONFIG4 0x16051807 +#define ETAMIN_NAND_GPMC_CONFIG5 0x00151e1e +#define ETAMIN_NAND_GPMC_CONFIG6 0x16000f80 + /* GPMC definitions for second nand cs1 */ static const u32 gpmc_nand_config[] = { ETAMIN_NAND_GPMC_CONFIG1, diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 6647148c96f..811c7cb9618 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -127,16 +127,6 @@ "bootm ${kloadaddr} - ${loadaddr}\0" \ COMMON_ENV_NAND_CMDS -#ifndef CONFIG_SPL_BUILD - -#define CONFIG_NAND_CS_INIT -#define ETAMIN_NAND_GPMC_CONFIG1 0x00000800 -#define ETAMIN_NAND_GPMC_CONFIG2 0x001e1e00 -#define ETAMIN_NAND_GPMC_CONFIG3 0x001e1e00 -#define ETAMIN_NAND_GPMC_CONFIG4 0x16051807 -#define ETAMIN_NAND_GPMC_CONFIG5 0x00151e1e -#define ETAMIN_NAND_GPMC_CONFIG6 0x16000f80 - /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=etamin\0" \ @@ -147,5 +137,5 @@ CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 -#endif /* CONFIG_SPL_BUILD */ + #endif /* ! __CONFIG_ETAMIN_H */ -- cgit v1.3.1 From 0a69d6afcab9b2fa364cd78aa67340185c5f75a0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:39 -0500 Subject: Convert CONFIG_OVERWRITE_ETHADDR_ONCE to Kconfig This converts the following to Kconfig: CONFIG_OVERWRITE_ETHADDR_ONCE Signed-off-by: Tom Rini --- README | 7 ------- configs/M5253DEMO_defconfig | 1 + configs/M5275EVB_defconfig | 1 + configs/eb_cpu5282_defconfig | 1 + configs/eb_cpu5282_internal_defconfig | 1 + env/Kconfig | 9 +++++++++ include/configs/M5253DEMO.h | 2 -- include/configs/M5275EVB.h | 4 ---- include/configs/eb_cpu5282.h | 4 ---- 9 files changed, 13 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/README b/README index 9e2627863ce..3ebee1cb375 100644 --- a/README +++ b/README @@ -1071,13 +1071,6 @@ The following options need to be configured: completely disabled. Anybody can change or delete these parameters. - Alternatively, if you define _both_ an ethaddr in the - default env _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default - Ethernet address is installed in the environment, - which can be changed exactly ONCE by the user. [The - serial# is unaffected by this, i. e. it remains - read-only.] - The same can be accomplished in a more flexible way for any variable by configuring the type of access to allow for those variables in the ".flags" variable diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index 4de6290b7d3..ea079972c9b 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MAC_PARTITION=y +CONFIG_OVERWRITE_ETHADDR_ONCE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="M5253DEMO" diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index 01961e5ae27..d84d9d98c5a 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_MII=y CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y +CONFIG_OVERWRITE_ETHADDR_ONCE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_RX_ETH_BUFFER=8 diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index a831c1c5d2a..7304b493872 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -32,6 +32,7 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y CONFIG_MII_INIT=y CONFIG_CMD_DATE=y +CONFIG_OVERWRITE_ETHADDR_ONCE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index 6a673c91811..5ecdda418aa 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -30,6 +30,7 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y CONFIG_MII_INIT=y CONFIG_CMD_DATE=y +CONFIG_OVERWRITE_ETHADDR_ONCE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y diff --git a/env/Kconfig b/env/Kconfig index c28d9e89f68..7ca992aa1d4 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -30,6 +30,15 @@ config ENV_OVERWRITE Use this to permit overriding of certain environmental variables like Ethernet and Serial +config OVERWRITE_ETHADDR_ONCE + bool "Enable overwriting ethaddr environment variables once" + depends on !ENV_OVERWRITE + help + Enable this to allow for the ethaddr environment variables to be + overwritten one time per boot, only. This allows for a default + to be installed in the environment, which can be changed exactly ONCE + by the user. + config ENV_MIN_ENTRIES int "Minimum number of entries in the environment hashtable" default 64 diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 65a7aa04086..bc156df20d5 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -20,8 +20,6 @@ env/embedded.o(.text*); #ifdef CONFIG_DRIVER_DM9000 -# define CONFIG_OVERWRITE_ETHADDR_ONCE - # define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index ff9f8535896..41974cff410 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -38,10 +38,6 @@ #define CFG_SYS_I2C_PINMUX_CLR (0xFFF0) #define CFG_SYS_I2C_PINMUX_SET (0x000F) -#ifdef CONFIG_MCFFEC -# define CONFIG_OVERWRITE_ETHADDR_ONCE -#endif /* FEC_ENET */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index b267b74b159..26e4ade34ee 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -42,10 +42,6 @@ * Network * *----------------------------------------------------------------------*/ -#ifdef CONFIG_MCFFEC -#define CONFIG_OVERWRITE_ETHADDR_ONCE -#endif - /*------------------------------------------------------------------------- * Low Level Configuration Settings * (address mappings, register initial values, etc.) -- cgit v1.3.1 From 2b210540b13ab528fbccc0122605ef07a57881af Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:40 -0500 Subject: Convert CONFIG_PEN_ADDR_BIG_ENDIAN to Kconfig This converts the following to Kconfig: CONFIG_PEN_ADDR_BIG_ENDIAN Signed-off-by: Tom Rini --- arch/arm/Kconfig | 3 +++ arch/arm/cpu/armv7/ls102xa/Kconfig | 3 +++ include/configs/ls1021aiot.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - 5 files changed, 6 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8381e09e102..6e191e41d5b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1599,6 +1599,7 @@ config TARGET_LS1021AQDS select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select LS1_DEEP_SLEEP + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select SYS_FSL_DDR select FSL_DDR_INTERACTIVE @@ -1617,6 +1618,7 @@ config TARGET_LS1021ATWR select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select LS1_DEEP_SLEEP + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI select GPIO_EXTRA_HEADER @@ -1681,6 +1683,7 @@ config TARGET_LS1021AIOT select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI select GPIO_EXTRA_HEADER diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 7e138e0cc5b..a83eb7e8fdd 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -51,6 +51,9 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. +config PEN_ADDR_BIG_ENDIAN + bool + config SYS_CCI400_OFFSET hex "Offset for CCI400 base" depends on SYS_FSL_HAS_CCI400 diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 179c5128e3b..0e3ff3c5b7a 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -68,7 +68,6 @@ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index fead9edeccd..76e75335c58 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -242,7 +242,6 @@ * MMC */ -#define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b07978a999e..281b26fa2ba 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -152,7 +152,6 @@ /* GPIO */ -#define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 -- cgit v1.3.1 From f55281665af3980e5151552fd126fb7293253e96 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:41 -0500 Subject: arm: ti814x: Remove remaining support code When the ti814x_evm config was removed most, but not all, of the relevant support code was remove. Get rid of what was missed. Fixes: 50b532686849 ("ti814x: Remove platform") Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/clock.h | 2 +- arch/arm/include/asm/arch-am33xx/clock_ti81xx.h | 36 +- arch/arm/include/asm/arch-am33xx/hardware.h | 2 - arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 60 --- arch/arm/include/asm/arch-am33xx/mmc_host_def.h | 5 +- arch/arm/include/asm/arch-am33xx/mux.h | 2 - arch/arm/include/asm/arch-am33xx/mux_ti814x.h | 311 ---------------- arch/arm/include/asm/arch-am33xx/omap.h | 2 +- arch/arm/include/asm/arch-am33xx/spl.h | 16 +- arch/arm/mach-omap2/Kconfig | 8 - arch/arm/mach-omap2/am33xx/Kconfig | 10 - arch/arm/mach-omap2/am33xx/Makefile | 1 - arch/arm/mach-omap2/am33xx/clock_ti814x.c | 410 --------------------- arch/arm/mach-omap2/am33xx/emif4.c | 20 - arch/arm/mach-omap2/boot-common.c | 2 +- drivers/i2c/Kconfig | 2 +- drivers/net/ti/cpsw.c | 4 - include/configs/ti814x_evm.h | 102 ----- 18 files changed, 12 insertions(+), 983 deletions(-) delete mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h delete mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti814x.h delete mode 100644 arch/arm/mach-omap2/am33xx/clock_ti814x.c delete mode 100644 include/configs/ti814x_evm.h (limited to 'include') diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 79e3b8c7d9f..ad25b3e8aa0 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -13,7 +13,7 @@ #include #include -#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X) +#if defined(CONFIG_TI816X) #include #endif diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h index f0699229a33..d22d9587063 100644 --- a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h +++ b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h @@ -44,9 +44,7 @@ struct cm_alwon { unsigned int mmu_clkstctrl; unsigned int mmucfg_clkstctrl; unsigned int ocmc0clkstctrl; -#if defined(CONFIG_TI814X) - unsigned int vcpclkstctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int ocmc1clkstctrl; #endif unsigned int mpuclkstctrl; @@ -67,16 +65,7 @@ struct cm_alwon { unsigned int gpio1clkctrl; unsigned int i2c0clkctrl; unsigned int i2c1clkctrl; -#if defined(CONFIG_TI814X) - unsigned int mcasp345clkctrl; - unsigned int atlclkctrl; - unsigned int mlbclkctrl; - unsigned int pataclkctrl; - unsigned int resv1[1]; - unsigned int uart3clkctrl; - unsigned int uart4clkctrl; - unsigned int uart5clkctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int resv1[1]; unsigned int timer1clkctrl; unsigned int timer2clkctrl; @@ -93,16 +82,12 @@ struct cm_alwon { unsigned int mmudataclkctrl; unsigned int resv2[2]; unsigned int mmucfgclkctrl; -#if defined(CONFIG_TI814X) - unsigned int resv3[2]; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int resv3[1]; unsigned int sdioclkctrl; #endif unsigned int ocmc0clkctrl; -#if defined(CONFIG_TI814X) - unsigned int vcpclkctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int ocmc1clkctrl; #endif unsigned int resv4[2]; @@ -112,9 +97,7 @@ struct cm_alwon { unsigned int ethernet0clkctrl; unsigned int ethernet1clkctrl; unsigned int mpuclkctrl; -#if defined(CONFIG_TI814X) - unsigned int debugssclkctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int resv6[1]; #endif unsigned int l3clkctrl; @@ -126,14 +109,7 @@ struct cm_alwon { unsigned int tptc1clkctrl; unsigned int tptc2clkctrl; unsigned int tptc3clkctrl; -#if defined(CONFIG_TI814X) - unsigned int resv6[4]; - unsigned int dcan01clkctrl; - unsigned int mmchs0clkctrl; - unsigned int mmchs1clkctrl; - unsigned int mmchs2clkctrl; - unsigned int custefuseclkctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int sr0clkctrl; unsigned int sr1clkctrl; #endif diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 0508b8c912a..2d7f9da3652 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -16,8 +16,6 @@ #include #elif defined(CONFIG_TI816X) #include -#elif defined(CONFIG_TI814X) -#include #elif defined(CONFIG_AM43XX) #include #endif diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h deleted file mode 100644 index b00d592bc31..00000000000 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * hardware_ti814x.h - * - * TI814x hardware specific header - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef __AM33XX_HARDWARE_TI814X_H -#define __AM33XX_HARDWARE_TI814X_H - -/* Module base addresses */ - -/* UART Base Address */ -#define UART0_BASE 0x48020000 - -/* Watchdog Timer */ -#define WDT_BASE 0x481C7000 - -/* Control Module Base Address */ -#define CTRL_BASE 0x48140000 -#define CTRL_DEVICE_BASE 0x48140600 - -/* PRCM Base Address */ -#define PRCM_BASE 0x48180000 -#define CM_PER 0x44E00000 -#define CM_WKUP 0x44E00400 - -#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) -#define PRM_RSTST (PRM_RSTCTRL + 8) - -/* PLL Subsystem Base Address */ -#define PLL_SUBSYS_BASE 0x481C5000 - -/* VTP Base address */ -#define VTP0_CTRL_ADDR 0x48140E0C -#define VTP1_CTRL_ADDR 0x48140E10 - -/* DDR Base address */ -#define DDR_PHY_CMD_ADDR 0x47C0C400 -#define DDR_PHY_DATA_ADDR 0x47C0C4C8 -#define DDR_PHY_CMD_ADDR2 0x47C0C800 -#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 -#define DDR_DATA_REGS_NR 4 - -#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) -#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE - -/* CPSW Config space */ -#define CPSW_MDIO_BASE 0x4A100800 - -/* RTC base address */ -#define RTC_BASE 0x480C0000 - -/* OTG */ -#define USB0_OTG_BASE 0x47401000 -#define USB1_OTG_BASE 0x47401800 - -#endif /* __AM33XX_HARDWARE_TI814X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index 5a2ea8faefd..ed15d15c5b3 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -24,10 +24,7 @@ #define OMAP_HSMMC1_BASE 0x48060000 #define OMAP_HSMMC2_BASE 0x481D8000 -#if defined(CONFIG_TI814X) -#undef MMC_CLOCK_REFERENCE -#define MMC_CLOCK_REFERENCE 192 /* MHz */ -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) #undef MMC_CLOCK_REFERENCE #define MMC_CLOCK_REFERENCE 48 /* MHz */ #endif diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index b16b1847336..7cf973710d1 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -20,8 +20,6 @@ #ifdef CONFIG_AM33XX #include -#elif defined(CONFIG_TI814X) -#include #elif defined(CONFIG_TI816X) #include #elif defined(CONFIG_AM43XX) diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti814x.h b/arch/arm/include/asm/arch-am33xx/mux_ti814x.h deleted file mode 100644 index a26e5038f71..00000000000 --- a/arch/arm/include/asm/arch-am33xx/mux_ti814x.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - * mux_ti814x.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MUX_TI814X_H_ -#define _MUX_TI814X_H_ - -/* PAD Control Fields */ -#define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */ -#define PULLUP_EN (0x1 << 17) /* Pull UP Selection */ -#define PULLUDEN (0x0 << 16) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 16) /* Pull up disabled */ -#define MODE(val) val /* used for Readability */ - -#define MUX_CFG(value, offset) \ -{ \ - int tmp; \ - tmp = __raw_readl(CTRL_BASE + offset); \ - tmp &= PINCNTL_RSV_MSK; \ - __raw_writel(tmp | value, (CTRL_BASE + offset));\ -} - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int pincntl1; - int pincntl2; - int pincntl3; - int pincntl4; - int pincntl5; - int pincntl6; - int pincntl7; - int pincntl8; - int pincntl9; - int pincntl10; - int pincntl11; - int pincntl12; - int pincntl13; - int pincntl14; - int pincntl15; - int pincntl16; - int pincntl17; - int pincntl18; - int pincntl19; - int pincntl20; - int pincntl21; - int pincntl22; - int pincntl23; - int pincntl24; - int pincntl25; - int pincntl26; - int pincntl27; - int pincntl28; - int pincntl29; - int pincntl30; - int pincntl31; - int pincntl32; - int pincntl33; - int pincntl34; - int pincntl35; - int pincntl36; - int pincntl37; - int pincntl38; - int pincntl39; - int pincntl40; - int pincntl41; - int pincntl42; - int pincntl43; - int pincntl44; - int pincntl45; - int pincntl46; - int pincntl47; - int pincntl48; - int pincntl49; - int pincntl50; - int pincntl51; - int pincntl52; - int pincntl53; - int pincntl54; - int pincntl55; - int pincntl56; - int pincntl57; - int pincntl58; - int pincntl59; - int pincntl60; - int pincntl61; - int pincntl62; - int pincntl63; - int pincntl64; - int pincntl65; - int pincntl66; - int pincntl67; - int pincntl68; - int pincntl69; - int pincntl70; - int pincntl71; - int pincntl72; - int pincntl73; - int pincntl74; - int pincntl75; - int pincntl76; - int pincntl77; - int pincntl78; - int pincntl79; - int pincntl80; - int pincntl81; - int pincntl82; - int pincntl83; - int pincntl84; - int pincntl85; - int pincntl86; - int pincntl87; - int pincntl88; - int pincntl89; - int pincntl90; - int pincntl91; - int pincntl92; - int pincntl93; - int pincntl94; - int pincntl95; - int pincntl96; - int pincntl97; - int pincntl98; - int pincntl99; - int pincntl100; - int pincntl101; - int pincntl102; - int pincntl103; - int pincntl104; - int pincntl105; - int pincntl106; - int pincntl107; - int pincntl108; - int pincntl109; - int pincntl110; - int pincntl111; - int pincntl112; - int pincntl113; - int pincntl114; - int pincntl115; - int pincntl116; - int pincntl117; - int pincntl118; - int pincntl119; - int pincntl120; - int pincntl121; - int pincntl122; - int pincntl123; - int pincntl124; - int pincntl125; - int pincntl126; - int pincntl127; - int pincntl128; - int pincntl129; - int pincntl130; - int pincntl131; - int pincntl132; - int pincntl133; - int pincntl134; - int pincntl135; - int pincntl136; - int pincntl137; - int pincntl138; - int pincntl139; - int pincntl140; - int pincntl141; - int pincntl142; - int pincntl143; - int pincntl144; - int pincntl145; - int pincntl146; - int pincntl147; - int pincntl148; - int pincntl149; - int pincntl150; - int pincntl151; - int pincntl152; - int pincntl153; - int pincntl154; - int pincntl155; - int pincntl156; - int pincntl157; - int pincntl158; - int pincntl159; - int pincntl160; - int pincntl161; - int pincntl162; - int pincntl163; - int pincntl164; - int pincntl165; - int pincntl166; - int pincntl167; - int pincntl168; - int pincntl169; - int pincntl170; - int pincntl171; - int pincntl172; - int pincntl173; - int pincntl174; - int pincntl175; - int pincntl176; - int pincntl177; - int pincntl178; - int pincntl179; - int pincntl180; - int pincntl181; - int pincntl182; - int pincntl183; - int pincntl184; - int pincntl185; - int pincntl186; - int pincntl187; - int pincntl188; - int pincntl189; - int pincntl190; - int pincntl191; - int pincntl192; - int pincntl193; - int pincntl194; - int pincntl195; - int pincntl196; - int pincntl197; - int pincntl198; - int pincntl199; - int pincntl200; - int pincntl201; - int pincntl202; - int pincntl203; - int pincntl204; - int pincntl205; - int pincntl206; - int pincntl207; - int pincntl208; - int pincntl209; - int pincntl210; - int pincntl211; - int pincntl212; - int pincntl213; - int pincntl214; - int pincntl215; - int pincntl216; - int pincntl217; - int pincntl218; - int pincntl219; - int pincntl220; - int pincntl221; - int pincntl222; - int pincntl223; - int pincntl224; - int pincntl225; - int pincntl226; - int pincntl227; - int pincntl228; - int pincntl229; - int pincntl230; - int pincntl231; - int pincntl232; - int pincntl233; - int pincntl234; - int pincntl235; - int pincntl236; - int pincntl237; - int pincntl238; - int pincntl239; - int pincntl240; - int pincntl241; - int pincntl242; - int pincntl243; - int pincntl244; - int pincntl245; - int pincntl246; - int pincntl247; - int pincntl248; - int pincntl249; - int pincntl250; - int pincntl251; - int pincntl252; - int pincntl253; - int pincntl254; - int pincntl255; - int pincntl256; - int pincntl257; - int pincntl258; - int pincntl259; - int pincntl260; - int pincntl261; - int pincntl262; - int pincntl263; - int pincntl264; - int pincntl265; - int pincntl266; - int pincntl267; - int pincntl268; - int pincntl269; - int pincntl270; -}; - -#endif /* endif _MUX_TI814X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index bc9f0a1146a..4c71dbf3ab6 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -20,7 +20,7 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 #define NON_SECURE_SRAM_IMG_END 0x4030B800 -#elif defined(CONFIG_TI816X) || defined(CONFIG_TI814X) +#elif defined(CONFIG_TI816X) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 #define NON_SECURE_SRAM_IMG_END 0x4031B800 diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index f3910c2123a..6bd3ca0d076 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -9,21 +9,7 @@ #define BOOT_DEVICE_NONE 0x00 #define BOOT_DEVICE_MMC2_2 0xFF -#if defined(CONFIG_TI814X) -#define BOOT_DEVICE_XIP 0x01 -#define BOOT_DEVICE_XIPWAIT 0x02 -#define BOOT_DEVICE_NAND 0x05 -#define BOOT_DEVICE_NAND_I2C 0x06 -#define BOOT_DEVICE_MMC2 0x08 /* ROM only supports 2nd instance. */ -#define BOOT_DEVICE_MMC1 0x09 -#define BOOT_DEVICE_SPI 0x15 -#define BOOT_DEVICE_UART 0x41 -#define BOOT_DEVICE_USBETH 0x44 -#define BOOT_DEVICE_CPGMAC 0x46 - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) #define BOOT_DEVICE_XIP 0x01 #define BOOT_DEVICE_XIPWAIT 0x02 #define BOOT_DEVICE_NAND 0x03 diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 3bf97205226..1db71df2721 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -75,14 +75,6 @@ config OMAP54XX imply SPL_SERIAL imply SYS_I2C_OMAP24XX -config TI814X - bool "TI814X SoC" - select SPECIFY_CONSOLE_INDEX - help - Support for AM335x SOC from Texas Instruments. - The AM335x high performance SOC features a Cortex-A8 - ARM core and more. - config TI816X bool "TI816X SoC" select SPECIFY_CONSOLE_INDEX diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index b666e811104..1299aec055e 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -8,16 +8,6 @@ config TARGET_TI816X_EVM endif -if TI814X - -config TARGET_TI814X_EVM - bool "Support ti814x_evm" - help - This option specifies support for the TI8148 - EVM development platform. - -endif - if AM33XX config AM33XX_CHILISOM diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile index 4e4f98ea903..bf94d345dae 100644 --- a/arch/arm/mach-omap2/am33xx/Makefile +++ b/arch/arm/mach-omap2/am33xx/Makefile @@ -3,7 +3,6 @@ # Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ obj-$(CONFIG_AM33XX) += clock_am33xx.o -obj-$(CONFIG_TI814X) += clock_ti814x.o obj-$(CONFIG_AM43XX) += clock_am43xx.o ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),) diff --git a/arch/arm/mach-omap2/am33xx/clock_ti814x.c b/arch/arm/mach-omap2/am33xx/clock_ti814x.c deleted file mode 100644 index 27abaff48fc..00000000000 --- a/arch/arm/mach-omap2/am33xx/clock_ti814x.c +++ /dev/null @@ -1,410 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * clock_ti814x.c - * - * Clocks for TI814X based boards - * - * Copyright (C) 2013, Texas Instruments, Incorporated - */ - -#include -#include -#include -#include -#include -#include - -/* PRCM */ -#define PRCM_MOD_EN 0x2 - -/* CLK_SRC */ -#define OSC_SRC0 0 -#define OSC_SRC1 1 - -#define L3_OSC_SRC OSC_SRC0 - -#define OSC_0_FREQ 20 - -#define DCO_HS2_MIN 500 -#define DCO_HS2_MAX 1000 -#define DCO_HS1_MIN 1000 -#define DCO_HS1_MAX 2000 - -#define SELFREQDCO_HS2 0x00000801 -#define SELFREQDCO_HS1 0x00001001 - -#define MPU_N 0x1 -#define MPU_M 0x3C -#define MPU_M2 1 -#define MPU_CLKCTRL 0x1 - -#define L3_N 19 -#define L3_M 880 -#define L3_M2 4 -#define L3_CLKCTRL 0x801 - -#define DDR_N 19 -#define DDR_M 666 -#define DDR_M2 2 -#define DDR_CLKCTRL 0x801 - -/* ADPLLJ register values */ -#define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */ -#define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */ -#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29) -#define ADPLLJ_CLKCTRL_IDLE (1 << 23) -#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20) -#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19) -#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17) -#define ADPLLJ_CLKCTRL_LPMODE (1 << 12) -#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11) -#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10) -#define ADPLLJ_CLKCTRL_TINITZ (1 << 0) -#define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \ - ADPLLJ_CLKCTRL_CLKOUTEN | \ - ADPLLJ_CLKCTRL_CLKOUTLDOEN | \ - ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ) - -#define ADPLLJ_STATUS_PHASELOCK (1 << 10) -#define ADPLLJ_STATUS_FREQLOCK (1 << 9) -#define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \ - ADPLLJ_STATUS_FREQLOCK) -#define ADPLLJ_STATUS_BYPASSACK (1 << 8) -#define ADPLLJ_STATUS_BYPASS (1 << 0) -#define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \ - ADPLLJ_STATUS_BYPASS) - -#define ADPLLJ_TENABLE_ENB (1 << 0) -#define ADPLLJ_TENABLEDIV_ENB (1 << 0) - -#define ADPLLJ_M2NDIV_M2SHIFT 16 - -#define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048) -#define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110) -#define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290) - -struct ad_pll { - unsigned int pwrctrl; - unsigned int clkctrl; - unsigned int tenable; - unsigned int tenablediv; - unsigned int m2ndiv; - unsigned int mn2div; - unsigned int fracdiv; - unsigned int bwctrl; - unsigned int fracctrl; - unsigned int status; - unsigned int m3div; - unsigned int rampctrl; -}; - -#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0) - -#define ENET_CLKCTRL_CMPL 0x30000 - -#define SATA_PLL_BASE (CTRL_BASE + 0x0720) - -struct sata_pll { - unsigned int pllcfg0; - unsigned int pllcfg1; - unsigned int pllcfg2; - unsigned int pllcfg3; - unsigned int pllcfg4; - unsigned int pllstatus; - unsigned int rxstatus; - unsigned int txstatus; - unsigned int testcfg; -}; - -#define SEL_IN_FREQ (0x1 << 31) -#define DIGCLRZ (0x1 << 30) -#define ENDIGLDO (0x1 << 4) -#define APLL_CP_CURR (0x1 << 3) -#define ENBGSC_REF (0x1 << 2) -#define ENPLLLDO (0x1 << 1) -#define ENPLL (0x1 << 0) - -#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF) -#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF) -#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO) -#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \ - ENPLLLDO | ENPLL) - -#define PLL_LOCK (0x1 << 0) - -#define ENSATAMODE (0x1 << 31) -#define PLLREFSEL (0x1 << 30) -#define MDIVINT (0x4b << 18) -#define EN_CLKAUX (0x1 << 5) -#define EN_CLK125M (0x1 << 4) -#define EN_CLK100M (0x1 << 3) -#define EN_CLK50M (0x1 << 2) - -#define SATA_PLLCFG1 (ENSATAMODE | \ - PLLREFSEL | \ - MDIVINT | \ - EN_CLKAUX | \ - EN_CLK125M | \ - EN_CLK100M | \ - EN_CLK50M) - -#define DIGLDO_EN_CAPLESSMODE (0x1 << 22) -#define PLLDO_EN_LDO_STABLE (0x1 << 11) -#define PLLDO_EN_BUF_CUR (0x1 << 7) -#define PLLDO_EN_LP (0x1 << 6) -#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1) - -#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \ - PLLDO_EN_LDO_STABLE | \ - PLLDO_EN_BUF_CUR | \ - PLLDO_EN_LP | \ - PLLDO_CTRL_TRIM_1_4V) - -const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; -const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; -const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE; - -/* - * Enable the peripheral clock for required peripherals - */ -static void enable_per_clocks(void) -{ - /* HSMMC1 */ - writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl); - while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN) - ; - - /* Ethernet */ - writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); - writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); - while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0) - ; - writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); - while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0) - ; - - /* RTC clocks */ - writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl); - writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl); - while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN) - ; -} - -/* - * select the HS1 or HS2 for DCO Freq - * return : CLKCTRL - */ -static u32 pll_dco_freq_sel(u32 clkout_dco) -{ - if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX) - return SELFREQDCO_HS2; - else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX) - return SELFREQDCO_HS1; - else - return -1; -} - -/* - * select the sigma delta config - * return: sigma delta val - */ -static u32 pll_sigma_delta_val(u32 clkout_dco) -{ - u32 sig_val = 0; - - sig_val = (clkout_dco + 225) / 250; - sig_val = sig_val << 24; - - return sig_val; -} - -/* - * configure individual ADPLLJ - */ -static void pll_config(u32 base, u32 n, u32 m, u32 m2, - u32 clkctrl_val, int adpllj) -{ - const struct ad_pll *adpll = (struct ad_pll *)base; - u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0; - u32 sig_val = 0, hs_mod = 0; - - m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n; - mn2val = m; - - /* calculate clkout_dco */ - clkout_dco = ((OSC_0_FREQ / (n+1)) * m); - - /* sigma delta & Hs mode selection skip for ADPLLS*/ - if (adpllj) { - sig_val = pll_sigma_delta_val(clkout_dco); - hs_mod = pll_dco_freq_sel(clkout_dco); - } - - /* by-pass pll */ - read_clkctrl = readl(&adpll->clkctrl); - writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl); - while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK) - != ADPLLJ_STATUS_BYPASSANDACK) - ; - - /* clear TINITZ */ - read_clkctrl = readl(&adpll->clkctrl); - writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl); - - /* - * ref_clk = 20/(n + 1); - * clkout_dco = ref_clk * m; - * clk_out = clkout_dco/m2; - */ - read_clkctrl = readl(&adpll->clkctrl) & - ~(ADPLLJ_CLKCTRL_LPMODE | - ADPLLJ_CLKCTRL_DRIFTGUARDIAN | - ADPLLJ_CLKCTRL_REGM4XEN); - writel(m2nval, &adpll->m2ndiv); - writel(mn2val, &adpll->mn2div); - - /* Skip for modena(ADPLLS) */ - if (adpllj) { - writel(sig_val, &adpll->fracdiv); - writel((read_clkctrl | hs_mod), &adpll->clkctrl); - } - - /* Load M2, N2 dividers of ADPLL */ - writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv); - writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv); - - /* Load M, N dividers of ADPLL */ - writel(ADPLLJ_TENABLE_ENB, &adpll->tenable); - writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable); - - /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */ - read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO; - if (adpllj) - writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO), - &adpll->clkctrl); - - /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */ - read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE; - writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl); - - /* Wait for phase and freq lock */ - while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) != - ADPLLJ_STATUS_PHSFRQLOCK) - ; -} - -static void unlock_pll_control_mmr(void) -{ - /* TRM 2.10.1.4 and 3.2.7-3.2.11 */ - writel(0x1EDA4C3D, 0x481C5040); - writel(0x2FF1AC2B, 0x48140060); - writel(0xF757FDC0, 0x48140064); - writel(0xE2BC3A6D, 0x48140068); - writel(0x1EBF131D, 0x4814006c); - writel(0x6F361E05, 0x48140070); -} - -static void mpu_pll_config(void) -{ - pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0); -} - -static void l3_pll_config(void) -{ - u32 l3_osc_src, rd_osc_src = 0; - - l3_osc_src = L3_OSC_SRC; - rd_osc_src = readl(OSC_SRC_CTRL); - - if (OSC_SRC0 == l3_osc_src) - writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL); - else - writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL); - - pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1); -} - -void ddr_pll_config(unsigned int ddrpll_m) -{ - pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1); -} - -void sata_pll_config(void) -{ - /* - * This sequence for configuring the SATA PLL - * resident in the control module is documented - * in TI8148 TRM section 21.3.1 - */ - writel(SATA_PLLCFG1, &spll->pllcfg1); - udelay(50); - - writel(SATA_PLLCFG3, &spll->pllcfg3); - udelay(50); - - writel(SATA_PLLCFG0_1, &spll->pllcfg0); - udelay(50); - - writel(SATA_PLLCFG0_2, &spll->pllcfg0); - udelay(50); - - writel(SATA_PLLCFG0_3, &spll->pllcfg0); - udelay(50); - - writel(SATA_PLLCFG0_4, &spll->pllcfg0); - udelay(50); - - while (((readl(&spll->pllstatus) & PLL_LOCK) == 0)) - ; -} - -void enable_dmm_clocks(void) -{ - writel(PRCM_MOD_EN, &cmdef->fwclkctrl); - writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); - writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); - while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN) - ; - writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); - while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN) - ; - while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) - ; - writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); - while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN) - ; - writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); - while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) - ; -} - -void setup_clocks_for_console(void) -{ - unlock_pll_control_mmr(); - /* UART0 */ - writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); - while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) - ; -} - -void setup_early_clocks(void) -{ - setup_clocks_for_console(); -} - -/* - * Configure the PLL/PRCM for necessary peripherals - */ -void prcm_init(void) -{ - /* Enable the control module */ - writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); - - /* Configure PLLs */ - mpu_pll_config(); - l3_pll_config(); - sata_pll_config(); - - /* Enable the required peripherals */ - enable_per_clocks(); -} diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c index a5fdb0433dc..bf3da43ed98 100644 --- a/arch/arm/mach-omap2/am33xx/emif4.c +++ b/arch/arm/mach-omap2/am33xx/emif4.c @@ -28,26 +28,6 @@ static struct cm_device_inst *cm_device = (struct cm_device_inst *)CM_DEVICE_INST; #endif -#ifdef CONFIG_TI814X -void config_dmm(const struct dmm_lisa_map_regs *regs) -{ - struct dmm_lisa_map_regs *hw_lisa_map_regs = - (struct dmm_lisa_map_regs *)DMM_BASE; - - enable_dmm_clocks(); - - writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); - - writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); -} -#endif - static void config_vtp(int nr) { writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index f955d494718..d104f23b3e2 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -183,7 +183,7 @@ void save_omap_boot_params(void) gd->arch.omap_boot_mode = boot_mode; -#if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \ +#if !defined(CONFIG_TI816X) && \ !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX) /* CH flags */ diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 08b6c7bdcc4..76e19918aad 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -704,7 +704,7 @@ config SYS_I2C_BUS_MAX depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA default 2 if TI816X default 3 if OMAP34XX || AM33XX || AM43XX - default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X + default 4 if ARCH_SOCFPGA || OMAP44XX default 5 if OMAP54XX help Define the maximum number of available I2C buses. diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c index a19dc38e525..3a8cc9c52a5 100644 --- a/drivers/net/ti/cpsw.c +++ b/drivers/net/ti/cpsw.c @@ -79,10 +79,6 @@ struct cpsw_slave_regs { u32 tx_pri_map; #ifdef CONFIG_AM33XX u32 gap_thresh; -#elif defined(CONFIG_TI814X) - u32 ts_ctl; - u32 ts_seq_ltype; - u32 ts_vlan; #endif u32 sa_lo; u32 sa_hi; diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h deleted file mode 100644 index 03849adb5ab..00000000000 --- a/include/configs/ti814x_evm.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * ti814x_evm.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __CONFIG_TI814X_EVM_H -#define __CONFIG_TI814X_EVM_H - -#include - -/* commands to include */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "fdtaddr=0x80F80000\0" \ - "rdaddr=0x81000000\0" \ - "bootfile=/boot/uImage\0" \ - "fdtfile=\0" \ - "console=ttyO0,115200n8\0" \ - "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 ro\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ - "ramrootfstype=ext2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "ramargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${ramroot} " \ - "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ - "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "ramboot=echo Booting from ramdisk ...; " \ - "run ramargs; " \ - "bootm ${loadaddr}\0" \ - "fdtfile=ti814x-evm.dtb\0" \ - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - - -/* Console I/O Buffer Size */ - -/** - * Physical Memory Map - */ -#define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */ - -#define CFG_SYS_SDRAM_BASE 0x80000000 - -/** - * Platform/Board specific defs - */ -#define CFG_SYS_TIMERBASE 0x4802E000 - -/* NS16550 Configuration */ -#define CFG_SYS_NS16550_CLK (48000000) -#define CFG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ - -/* CPU */ - -/* Defines for SPL */ - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80800000 should not be used for any - * other needs. - */ - -/* - * Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ - -/* Ethernet */ -#define CONFIG_PHY_ET1011C_TX_CLK_FIX - -#endif /* ! __CONFIG_TI814X_EVM_H */ -- cgit v1.3.1 From 32b7e39db4d3af0d94f1387a7641152f375b23ac Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:44 -0500 Subject: Convert CONFIG_STANDALONE_LOAD_ADDR to Kconfig This converts the following to Kconfig: CONFIG_STANDALONE_LOAD_ADDR Signed-off-by: Tom Rini --- README | 7 ------- api/Kconfig | 19 +++++++++++++++++++ arch/arc/config.mk | 3 --- arch/arm/config.mk | 8 -------- arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 -- arch/m68k/config.mk | 2 -- arch/microblaze/config.mk | 2 -- arch/mips/config.mk | 2 -- arch/nios2/config.mk | 2 -- arch/powerpc/config.mk | 1 - arch/riscv/config.mk | 2 -- arch/sh/config.mk | 1 - arch/x86/config.mk | 2 -- configs/display5_defconfig | 1 + configs/display5_factory_defconfig | 1 + configs/microchip_mpfs_icicle_defconfig | 1 + configs/qemu-riscv32_defconfig | 1 + configs/qemu-riscv32_smode_defconfig | 1 + configs/qemu-riscv32_spl_defconfig | 1 + configs/qemu-riscv64_defconfig | 1 + configs/qemu-riscv64_smode_defconfig | 1 + configs/qemu-riscv64_spl_defconfig | 1 + configs/sifive_unleashed_defconfig | 1 + configs/sifive_unmatched_defconfig | 1 + configs/xtfpga_defconfig | 1 + include/configs/display5.h | 2 -- include/configs/microchip_mpfs_icicle.h | 2 -- include/configs/opos6uldev.h | 1 - include/configs/qemu-riscv.h | 2 -- include/configs/sifive-unleashed.h | 2 -- include/configs/sifive-unmatched.h | 2 -- include/configs/sunxi-common.h | 3 --- include/configs/xtfpga.h | 16 ---------------- 33 files changed, 31 insertions(+), 64 deletions(-) (limited to 'include') diff --git a/README b/README index 3ebee1cb375..c8f6b21e2d9 100644 --- a/README +++ b/README @@ -1166,13 +1166,6 @@ The following options need to be configured: this is instead controlled by the value of /config/load-environment. - CONFIG_STANDALONE_LOAD_ADDR - - This option defines a board specific value for the - address where standalone program gets loaded, thus - overwriting the architecture dependent default - settings. - - Automatic software updates via TFTP server CONFIG_UPDATE_TFTP CONFIG_UPDATE_TFTP_CNT_MAX diff --git a/api/Kconfig b/api/Kconfig index eb8d5d0596a..d9362724e5f 100644 --- a/api/Kconfig +++ b/api/Kconfig @@ -11,3 +11,22 @@ config SYS_MMC_MAX_DEVICE default 1 endmenu + +config STANDALONE_LOAD_ADDR + hex "Address in memory to link standalone applications to" + default 0xffffffff80200000 if MIPS && 64BIT + default 0x8c000000 if SH + default 0x82000000 if ARC + default 0x80f00000 if MICROBLAZE + default 0x80300000 if ARCH_OMAP2PLUS || FSL_LSCH2 || FSL_LSCH3 + default 0x80200000 if MIPS && 32BIT + default 0x0c100000 if ARM + default 0x02000000 if NIOS2 + default 0x00040000 if PPC || X86 + default 0x00020000 if M68K + default 0x0 if RISCV + default SYS_LOAD_ADDR + help + This option defines a board specific value for the address where + standalone program gets loaded, thus overwriting the architecture + dependent default settings. diff --git a/arch/arc/config.mk b/arch/arc/config.mk index 2b70945ac34..b713fa3054c 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -21,6 +21,3 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -fno-common # Needed for relocation LDFLAGS_FINAL += -pie --gc-sections - -# Load address for standalone apps -CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000 diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 2065438d053..bf781f10262 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -3,14 +3,6 @@ # (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifndef CONFIG_STANDALONE_LOAD_ADDR -ifneq ($(CONFIG_ARCH_OMAP2PLUS),) -CONFIG_STANDALONE_LOAD_ADDR = 0x80300000 -else -CONFIG_STANDALONE_LOAD_ADDR = 0xc100000 -endif -endif - CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \ -fstack-protector-strong CFLAGS_EFI := -fpic -fshort-wchar diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index c9c72e32717..57d92f65520 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -14,8 +14,6 @@ #include #endif -#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 - /* * Reserve secure memory * To be aligned with MMU block size diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk index ed592334af2..3ccbe492202 100644 --- a/arch/m68k/config.mk +++ b/arch/m68k/config.mk @@ -3,8 +3,6 @@ # (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000 - PLATFORM_CPPFLAGS += -D__M68K__ KBUILD_LDFLAGS += -n PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index d35b4f6db7a..467c5ca1b12 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -6,8 +6,6 @@ # (C) Copyright 2004 Atmark Techno, Inc. # Yasushi SHOJI -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000 - PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ PLATFORM_CPPFLAGS += -fdata-sections -ffunction-sections diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 04f36278058..745f03190e9 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -25,14 +25,12 @@ ifdef CONFIG_32BIT PLATFORM_CPPFLAGS += -mabi=32 KBUILD_LDFLAGS += -m $(32bit-emul) OBJCOPYFLAGS += -O $(32bit-bfd) -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 endif ifdef CONFIG_64BIT PLATFORM_CPPFLAGS += -mabi=64 KBUILD_LDFLAGS += -m$(64bit-emul) OBJCOPYFLAGS += -O $(64bit-bfd) -CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 endif PLATFORM_CPPFLAGS += -D__MIPS__ diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index 44260b1431c..b18b9b78ab6 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -4,8 +4,6 @@ # Psyent Corporation # Scott McNutt -CONFIG_STANDALONE_LOAD_ADDR ?= 0x02000000 - PLATFORM_CPPFLAGS += -D__NIOS2__ PLATFORM_CPPFLAGS += -G0 diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 307ca65745c..725a4f48aad 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -3,7 +3,6 @@ # (C) Copyright 2000-2010 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 LDFLAGS_FINAL += --gc-sections LDFLAGS_FINAL += --bss-plt PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections \ diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index 1ebce5bd674..a8ed3faf28c 100644 --- a/arch/riscv/config.mk +++ b/arch/riscv/config.mk @@ -23,8 +23,6 @@ KBUILD_LDFLAGS += -m $(64bit-emul) EFI_LDS := elf_riscv64_efi.lds endif -CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 - PLATFORM_CPPFLAGS += -ffixed-gp -fpic PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections \ -fdata-sections diff --git a/arch/sh/config.mk b/arch/sh/config.mk index 78bb2660e1e..a408264d4b1 100644 --- a/arch/sh/config.mk +++ b/arch/sh/config.mk @@ -3,7 +3,6 @@ # (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -CONFIG_STANDALONE_LOAD_ADDR ?= 0x8C000000 ifeq ($(CPU),sh2) LDFLAGS_STANDALONE += -EB endif diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 889497b6bd7..a4a694ddf31 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -3,8 +3,6 @@ # (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 - PLATFORM_CPPFLAGS += -fomit-frame-pointer PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \ $(call cc-option, -fno-unit-at-a-time)) diff --git a/configs/display5_defconfig b/configs/display5_defconfig index dbd917b4ddb..c46a0a0b699 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -30,6 +30,7 @@ CONFIG_ENV_OFFSET_REDUND=0x130000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_MONITOR_LEN=409600 +CONFIG_STANDALONE_LOAD_ADDR=0x10001000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 7508702eb95..cacdf33d53e 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -27,6 +27,7 @@ CONFIG_ENV_OFFSET_REDUND=0x130000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_MONITOR_LEN=409600 +CONFIG_STANDALONE_LOAD_ADDR=0x10001000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index fbb2df4a749..c2b938e7e7e 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -12,6 +12,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 425bb37c988..844c95380e6 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -9,6 +9,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index eeb90360cdb..2be349ada76 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -10,6 +10,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index 04447e5ed3c..894b6d5d174 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -12,6 +12,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISPLAY_CPUINFO=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index 7430fa075d7..8b558e6bc27 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH_RV64I=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 03ef58ba475..6ed88de2342 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -10,6 +10,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 840e0ff151c..adc6f730d2a 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -11,6 +11,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISPLAY_CPUINFO=y diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig index 99faabaa2ff..6c85962cbb2 100644 --- a/configs/sifive_unleashed_defconfig +++ b/configs/sifive_unleashed_defconfig @@ -16,6 +16,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 CONFIG_USE_PREBOOT=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index c390af26897..3d96aa54119 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -19,6 +19,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 CONFIG_USE_PREBOOT=y diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig index f5eeea426bb..d3a350f5400 100644 --- a/configs/xtfpga_defconfig +++ b/configs/xtfpga_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_ENV_ADDR=0xF7FE0000 CONFIG_XTFPGA_KC705=y CONFIG_SYS_MONITOR_LEN=262144 +CONFIG_STANDALONE_LOAD_ADDR=0x00800000 CONFIG_SYS_MONITOR_BASE=0xF6000000 CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_SHOW_BOOT_PROGRESS=y diff --git a/include/configs/display5.h b/include/configs/display5.h index 5cbeb9224c3..4401515a65e 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -276,8 +276,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_STANDALONE_LOAD_ADDR 0x10001000 - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 3def93d61e8..c73c5a1d9fe 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -11,8 +11,6 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 - /* Environment options */ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 5c44b9dcb20..459134b93f8 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -11,7 +11,6 @@ #include "mx6_common.h" /* Miscellaneous configurable options */ -#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR /* Physical Memory Map */ #define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 72f35cc0542..35172da3ff1 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -10,8 +10,6 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 - #define RISCV_MMODE_TIMERBASE 0x2000000 #define RISCV_MMODE_TIMER_FREQ 1000000 diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index 5ad2124bdda..4a453a9df40 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -13,8 +13,6 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 - #define RISCV_MMODE_TIMERBASE 0x2000000 #define RISCV_MMODE_TIMER_FREQ 1000000 diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index f4b1a16019e..ac42108620f 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -13,8 +13,6 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 - /* Environment options */ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 496139f3463..5d82e7e560f 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -73,9 +73,6 @@ * Miscellaneous configurable options */ -/* standalone support */ -#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR - /* FLASH and environment organization */ /* diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 9201dac7abc..e0189c58f04 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -53,22 +53,6 @@ /* Memory test is destructive so default must not overlap vectors or U-Boot*/ -/* Load address for stand-alone applications. - * MEMADDR cannot be used here, because the definition needs to be - * a plain number as it's used as -Ttext argument for ld in standalone - * example makefile. - * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually. - */ -#if XCHAL_HAVE_PTP_MMU -#if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR -#define CONFIG_STANDALONE_LOAD_ADDR 0x00800000 -#else -#define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000 -#endif -#else -#define CONFIG_STANDALONE_LOAD_ADDR 0x60800000 -#endif - #if defined(CONFIG_MAX_MEM_MAPPED) && \ CONFIG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE #define XTENSA_SYS_TEXT_ADDR \ -- cgit v1.3.1 From d14f3f272519a5525d93ec98cbdd4d9eec7db6e9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:45 -0500 Subject: Convert CONFIG_TEGRA_ENABLE_UARTA et al to Kconfig This converts the following to Kconfig: CONFIG_TEGRA_ENABLE_UARTA CONFIG_TEGRA_ENABLE_UARTB CONFIG_TEGRA_ENABLE_UARTC CONFIG_TEGRA_ENABLE_UARTD CONFIG_TEGRA_SPI CONFIG_TEGRA_UARTA_GPU CONFIG_TEGRA_UARTA_SDIO1 CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 Signed-off-by: Tom Rini --- arch/arm/mach-tegra/Kconfig | 23 +++++++++++++++++++++++ arch/arm/mach-tegra/tegra20/Kconfig | 8 ++++++++ arch/arm/mach-tegra/tegra30/Kconfig | 8 ++++++++ configs/cei-tk1-som_defconfig | 1 + configs/dalmore_defconfig | 1 + configs/harmony_defconfig | 1 + configs/jetson-tk1_defconfig | 1 + configs/medcom-wide_defconfig | 1 + configs/plutux_defconfig | 1 + configs/seaboard_defconfig | 1 + configs/tec-ng_defconfig | 1 + configs/tec_defconfig | 1 + configs/ventana_defconfig | 1 + include/configs/apalis-tk1.h | 1 - include/configs/apalis_t30.h | 1 - include/configs/beaver.h | 4 ---- include/configs/cardhu.h | 4 ---- include/configs/cei-tk1-som.h | 1 - include/configs/colibri_t20.h | 2 -- include/configs/colibri_t30.h | 1 - include/configs/dalmore.h | 1 - include/configs/harmony.h | 1 - include/configs/jetson-tk1.h | 1 - include/configs/medcom-wide.h | 1 - include/configs/nyan-big.h | 1 - include/configs/p2371-0000.h | 1 - include/configs/p2371-2180.h | 1 - include/configs/p2571.h | 1 - include/configs/p3450-0000.h | 1 - include/configs/paz00.h | 1 - include/configs/plutux.h | 1 - include/configs/seaboard.h | 1 - include/configs/tec-ng.h | 1 - include/configs/tec.h | 1 - include/configs/tegra-common-post.h | 4 ---- include/configs/trimslice.h | 2 -- include/configs/venice2.h | 1 - include/configs/ventana.h | 1 - 38 files changed, 49 insertions(+), 36 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index edcf967afd9..1b575cc0f45 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -177,6 +177,29 @@ source "arch/arm/mach-tegra/tegra124/Kconfig" source "arch/arm/mach-tegra/tegra210/Kconfig" source "arch/arm/mach-tegra/tegra186/Kconfig" +config TEGRA_SPI + def_bool y + depends on TEGRA20_SFLASH || TEGRA20_SLINK || TEGRA114_SPI + +choice + prompt "UART to use for console" + depends on TEGRA_PINCTRL + default TEGRA_ENABLE_UARTA + +config TEGRA_ENABLE_UARTA + bool "Use UARTA" + +config TEGRA_ENABLE_UARTB + bool "Use UARTB" + +config TEGRA_ENABLE_UARTC + bool "Use UARTC" + +config TEGRA_ENABLE_UARTD + bool "Use UARTD" + +endchoice + config TEGRA_GPU bool "Enable setting up the GPU" depends on TEGRA124 || TEGRA210 diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index 345563fc789..955786c0c48 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -10,6 +10,12 @@ config TEGRA_PMU config TEGRA_CLOCK_SCALING bool +config TEGRA_UARTA_GPU + bool + +config TEGRA_UARTA_SDIO1 + bool + choice prompt "Tegra20 board select" optional @@ -43,6 +49,7 @@ config TARGET_TEC config TARGET_TRIMSLICE bool "Compulab TrimSlice board" select BOARD_LATE_INIT + select TEGRA_UARTA_GPU config TARGET_VENTANA bool "NVIDIA Tegra20 Ventana evaluation board" @@ -51,6 +58,7 @@ config TARGET_VENTANA config TARGET_COLIBRI_T20 bool "Toradex Colibri T20 board" select BOARD_LATE_INIT + select TEGRA_UARTA_SDIO1 endchoice diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index 85b8ce294f2..5619d1cd42f 100644 --- a/arch/arm/mach-tegra/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig @@ -1,5 +1,11 @@ if TEGRA30 +config TEGRA_VDD_CORE_TPS62361B_SET3 + bool + +config TEGRA_VDD_CORE_TPS62366A_SET1 + bool + choice prompt "Tegra30 board select" optional @@ -11,10 +17,12 @@ config TARGET_APALIS_T30 config TARGET_BEAVER bool "NVIDIA Tegra30 Beaver evaluation board" select BOARD_LATE_INIT + select TEGRA_VDD_CORE_TPS62366A_SET1 config TARGET_CARDHU bool "NVIDIA Tegra30 Cardhu evaluation board" select BOARD_LATE_INIT + select TEGRA_VDD_CORE_TPS62361B_SET3 config TARGET_COLIBRI_T30 bool "Toradex Colibri T30 board" diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index 58d75a52a08..0c4627aff05 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_SYS_PROMPT="Tegra124 (TK1-SOM) # " CONFIG_TEGRA124=y CONFIG_TARGET_CEI_TK1_SOM=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_TEGRA_GPU=y CONFIG_ARMV7_PSCI_0_1=y CONFIG_SYS_LOAD_ADDR=0x81000000 diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index cc46f4eda41..5d29dae3411 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # " CONFIG_TEGRA114=y CONFIG_TARGET_DALMORE=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index 353d1a33fab..c8694bba681 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Tegra20 (Harmony) # " CONFIG_TEGRA20=y CONFIG_TARGET_HARMONY=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index b391a86c022..d935e784ab4 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # " CONFIG_TEGRA124=y CONFIG_TARGET_JETSON_TK1=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index 76e4eb3078c..563e01459af 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # " CONFIG_TEGRA20=y CONFIG_TARGET_MEDCOM_WIDE=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig index 170ac86468d..789b5d93982 100644 --- a/configs/plutux_defconfig +++ b/configs/plutux_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Tegra20 (Plutux) # " CONFIG_TEGRA20=y CONFIG_TARGET_PLUTUX=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index 2375040a9ec..dc9225188fa 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # " CONFIG_TEGRA20=y CONFIG_TARGET_SEABOARD=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig index 02d6b496f96..8c3f8d5e065 100644 --- a/configs/tec-ng_defconfig +++ b/configs/tec-ng_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # " CONFIG_TEGRA30=y CONFIG_TARGET_TEC_NG=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/tec_defconfig b/configs/tec_defconfig index 967d3050eff..a1900f0181d 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Tegra20 (TEC) # " CONFIG_TEGRA20=y CONFIG_TARGET_TEC=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index 3c924ec9eae..3d94f454be2 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Tegra20 (Ventana) # " CONFIG_TEGRA20=y CONFIG_TARGET_VENTANA=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 1d478078b2c..71d4727ca98 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -13,7 +13,6 @@ #include "tegra124-common.h" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define FDT_MODULE "apalis-v1.2" diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 4f00b3bad3f..80204d706d1 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -20,7 +20,6 @@ * Apalis UART3: NVIDIA UARTB * Apalis UART4: NVIDIA UARTC */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define UBOOT_UPDATE \ diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 7078c2745c8..7e0e4779607 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -10,14 +10,10 @@ #include "tegra30-common.h" -/* VDD core PMIC */ -#define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 - /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Beaver" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #include "tegra-common-post.h" diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 5cca1e18348..64d713a1969 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -10,9 +10,6 @@ #include "tegra30-common.h" -/* VDD core PMIC */ -#define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 - /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu" @@ -21,7 +18,6 @@ "fdtfile=tegra30-cardhu-a04.dtb\0" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #include "tegra-common-post.h" diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index e3519ed7516..e49eb602081 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -19,7 +19,6 @@ #define CONFIG_TEGRA_BOARD_STRING "CEI tk1-som" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #include "tegra-common-post.h" diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index 2ba3c3bc87d..ea7d648eb6a 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -11,8 +11,6 @@ #include "tegra20-common.h" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_TEGRA_UARTA_SDIO1 #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* NAND support */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index ffed71a2e82..7edb2c0b26d 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -21,7 +21,6 @@ * Colibri UART-B: NVIDIA UARTD * Colibri UART-C: NVIDIA UARTB */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define UBOOT_UPDATE \ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 82b2efdfe89..c9009e39623 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -14,7 +14,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Dalmore" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 211dab4d233..a1a66bfb64e 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -14,7 +14,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: keyboard satellite board UART, default */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index ea4964b13d6..aa9e1d811a5 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #include "tegra-common-post.h" diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index a8d8d8b09e0..efac0febdf8 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 21002f99dc8..e885526e625 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #include "tegra-common-post.h" diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index 653b4c583ad..f426889e1c4 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 2913d5304be..24adf4e13f0 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-2180" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h index e78e3c4d6b0..8a1e7d9b968 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h index bab02dc2d6e..078d35dde2c 100644 --- a/include/configs/p3450-0000.h +++ b/include/configs/p3450-0000.h @@ -14,7 +14,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-0000" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA /* Only MMC/PXE/DHCP for now, add USB back in later when supported */ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index a945f4e9b28..898167009f6 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -16,7 +16,6 @@ #define CONFIG_TEGRA_BOARD_STRING "Compal Paz00" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 99db59c489e..1d8ac618c0b 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index f272fe9bf8f..e5d672746b1 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index c98322cf084..ae879abe3f8 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -13,7 +13,6 @@ #define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #include "tegra-common-post.h" diff --git a/include/configs/tec.h b/include/configs/tec.h index ddf753da4a9..e8a9df756d5 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 69acabf19fd..2c668e0611b 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -73,8 +73,4 @@ BOOTENV \ BOARD_EXTRA_ENV_SETTINGS -#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) -#define CONFIG_TEGRA_SPI -#endif - #endif /* __TEGRA_COMMON_POST_H */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index e4cbc7da843..b5bf9912201 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -14,8 +14,6 @@ #define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_TEGRA_UARTA_GPU #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* SPI */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h index a4eb4bf4aaf..970893ca17b 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h index f7a507768ec..e7b7b911d9b 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -14,7 +14,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ -- cgit v1.3.1 From 60910a3f0267ccf2f87f1205aa3fb76491e674b5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:46 -0500 Subject: Convert CONFIG_THOR_RESET_OFF to Kconfig This converts the following to Kconfig: CONFIG_THOR_RESET_OFF Signed-off-by: Tom Rini --- cmd/Kconfig | 4 ++++ configs/topic_miami_defconfig | 1 + configs/topic_miamilite_defconfig | 1 + configs/topic_miamiplus_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + include/configs/xilinx_versal.h | 1 - include/configs/xilinx_versal_net.h | 1 - include/configs/xilinx_zynqmp.h | 1 - include/configs/zynq-common.h | 1 - 10 files changed, 9 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/cmd/Kconfig b/cmd/Kconfig index d93731f2af6..47d2ef04a2a 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -526,6 +526,10 @@ config CMD_THOR_DOWNLOAD There is no documentation about this within the U-Boot source code but you should be able to find something on the interwebs. +config THOR_RESET_OFF + bool "thor: Disable reset on completion" + depends on CMD_THOR_DOWNLOAD + config CMD_ZBOOT bool "zboot - x86 boot command" help diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index ece625f6292..2ae1fb82797 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -40,6 +40,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=2077 CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_THOR_RESET_OFF=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y CONFIG_CMD_I2C=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index 693a602ea39..510ff2ebd87 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -40,6 +40,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=2077 CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_THOR_RESET_OFF=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y CONFIG_CMD_I2C=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 97624e69e72..0b708cccf6e 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -40,6 +40,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=2077 CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_THOR_RESET_OFF=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y CONFIG_CMD_I2C=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 50685657690..610d9de2a63 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_PBSIZE=2071 CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_IMLS=y CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_THOR_RESET_OFF=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 4732c39bdbe..ab2a5426518 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -55,6 +55,7 @@ CONFIG_SYS_PBSIZE=2073 CONFIG_SYS_BOOTM_LEN=0x6400000 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_THOR_RESET_OFF=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_MEMTEST=y diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index ee3130ed327..6ee6786e054 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -25,7 +25,6 @@ #if defined(CONFIG_CMD_DFU) #define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_THOR_RESET_OFF #endif /* Ethernet driver */ diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h index 7d77189693e..37bdb214629 100644 --- a/include/configs/xilinx_versal_net.h +++ b/include/configs/xilinx_versal_net.h @@ -25,7 +25,6 @@ #if defined(CONFIG_CMD_DFU) #define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_THOR_RESET_OFF #define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ "setenv dfu_alt_info " \ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index efe241df97e..f71cd660993 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -31,7 +31,6 @@ #if defined(CONFIG_ZYNQMP_USB) #define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_THOR_RESET_OFF # define PARTS_DEFAULT \ "partitions=uuid_disk=${uuid_gpt_disk};" \ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 37b54289073..d95178eb642 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -38,7 +38,6 @@ #ifdef CONFIG_USB_EHCI_ZYNQ # define DFU_DEFAULT_POLL_TIMEOUT 300 -# define CONFIG_THOR_RESET_OFF #endif /* enable preboot to be loaded before CONFIG_BOOTDELAY */ -- cgit v1.3.1 From 4fd9373bbb3f160c2975fc9de2fab49040141833 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:47 -0500 Subject: net: Remove more legacy functions Remove some of the board and arch specific non-DM_ETH helper code. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/ls102xa/cpu.c | 9 --------- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 --- arch/powerpc/cpu/mpc83xx/cpu.c | 18 ------------------ arch/powerpc/cpu/mpc8xxx/cpu.c | 26 -------------------------- drivers/net/qe/uec.h | 1 - include/configs/km/km-mpc83xx.h | 5 ----- include/fm_eth.h | 1 - include/netdev.h | 1 - 8 files changed, 64 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 25e4b49c70e..c455969609f 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -302,15 +302,6 @@ int cpu_mmc_init(struct bd_info *bis) } #endif -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH) - tsec_standard_init(bis); -#endif - - return 0; -} - int arch_cpu_init(void) { void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 99413ef52e2..2aeec7dea7b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1057,9 +1057,6 @@ int cpu_eth_init(struct bd_info *bis) #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) error = fsl_mc_ldpaa_init(bis); -#endif -#ifdef CONFIG_FMAN_ENET - fm_standard_init(bis); #endif return error; } diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 8d531898bd8..a6c063556e8 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -180,24 +180,6 @@ void watchdog_reset (void) } #endif -#ifndef CONFIG_DM_ETH -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_UEC_ETH) - uec_standard_init(bis); -#endif - -#if defined(CONFIG_TSEC_ENET) - tsec_standard_init(bis); -#endif - return 0; -} -#endif /* !CONFIG_DM_ETH */ - /* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 7f201909229..73d28f2a4e2 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -343,29 +343,3 @@ int fixup_cpu(void) #endif return 0; } - -#ifndef CONFIG_DM_ETH -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_UEC_ETH) - uec_standard_init(bis); -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) - tsec_standard_init(bis); -#endif - -#ifdef CONFIG_FMAN_ENET - fm_standard_init(bis); -#endif - -#ifdef CONFIG_VSC9953 - vsc9953_init(bis); -#endif - return 0; -} -#endif diff --git a/drivers/net/qe/uec.h b/drivers/net/qe/uec.h index 551d7061ccc..4510205da32 100644 --- a/drivers/net/qe/uec.h +++ b/drivers/net/qe/uec.h @@ -689,5 +689,4 @@ struct uec_priv { int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info); int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num); -int uec_standard_init(struct bd_info *bis); #endif /* __UEC_H__ */ diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 1f03f95acef..c939caf2a1f 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -58,8 +58,3 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_SYS_BOOTMAPSZ (8 << 20) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH diff --git a/include/fm_eth.h b/include/fm_eth.h index aeb640925ee..6012a449fd2 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -202,7 +202,6 @@ struct memac_mdio_info { int fm_tgec_mdio_init(struct bd_info *bis, struct tgec_mdio_info *info); int fm_memac_mdio_init(struct bd_info *bis, struct memac_mdio_info *info); -int fm_standard_init(struct bd_info *bis); void fman_enet_init(void); void fdt_fixup_fman_ethernet(void *fdt); phy_interface_t fm_info_get_enet_if(enum fm_port port); diff --git a/include/netdev.h b/include/netdev.h index b3f8584e900..2b4e474ed08 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -70,7 +70,6 @@ int sh_eth_initialize(struct bd_info *bis); int skge_initialize(struct bd_info *bis); int smc91111_initialize(u8 dev_num, phys_addr_t base_addr); int smc911x_initialize(u8 dev_num, phys_addr_t base_addr); -int uec_standard_init(struct bd_info *bis); int uli526x_initialize(struct bd_info *bis); int armada100_fec_register(unsigned long base_addr); -- cgit v1.3.1 From 0c3a6d443f4751b681566e8a752d12e04f4369f4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:49 -0500 Subject: usb: Remove CONFIG_USBD_HS This define is not enabled by the only platform which currently enables the legacy option of CONFIG_USB_DEVICE. We can drop this code. Signed-off-by: Tom Rini --- README | 8 ------ drivers/serial/usbtty.c | 50 ---------------------------------- drivers/serial/usbtty.h | 4 --- drivers/usb/gadget/ep0.c | 19 ------------- include/configs/apalis_imx6.h | 2 -- include/configs/colibri-imx6ull.h | 2 -- include/configs/colibri_imx6.h | 2 -- include/configs/colibri_imx7.h | 2 -- include/configs/ge_b1x5v2.h | 1 - include/configs/gw_ventana.h | 1 - include/configs/imx7-cm.h | 2 -- include/configs/librem5.h | 2 -- include/configs/mx6sabre_common.h | 2 -- include/configs/mx7dsabresd.h | 2 -- include/configs/nitrogen6x.h | 2 -- include/configs/novena.h | 2 -- include/configs/pico-imx6ul.h | 2 -- include/configs/siemens-am33x-common.h | 3 -- include/configs/tbs2910.h | 3 -- include/configs/warp7.h | 2 -- include/usbdescriptors.h | 15 ---------- include/usbdevice.h | 19 ------------- 22 files changed, 147 deletions(-) (limited to 'include') diff --git a/README b/README index c8f6b21e2d9..2944646665a 100644 --- a/README +++ b/README @@ -618,14 +618,6 @@ The following options need to be configured: variable usbtty to be cdc_acm should suffice. The following might be defined in YourBoardName.h - CONFIG_USBD_HS - Define this to enable the high speed support for usb - device and usbtty. If this feature is enabled, a routine - int is_usbd_high_speed(void) - also needs to be defined by the driver to dynamically poll - whether the enumeration has succeded at high speed or full - speed. - If you have a USB-IF assigned VendorID then you may wish to define your own vendor specific values either in BoardName.h or directly in usbd_vendor_info.h. If you don't define diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c index 4f4eb02de08..07a59ec9607 100644 --- a/drivers/serial/usbtty.c +++ b/drivers/serial/usbtty.c @@ -120,20 +120,6 @@ static struct usb_device_descriptor device_descriptor = { .bNumConfigurations = NUM_CONFIGS }; - -#if defined(CONFIG_USBD_HS) -static struct usb_qualifier_descriptor qualifier_descriptor = { - .bLength = sizeof(struct usb_qualifier_descriptor), - .bDescriptorType = USB_DT_QUAL, - .bcdUSB = cpu_to_le16(USB_BCD_VERSION), - .bDeviceClass = COMMUNICATIONS_DEVICE_CLASS, - .bDeviceSubClass = 0x00, - .bDeviceProtocol = 0x00, - .bMaxPacketSize0 = EP0_MAX_PACKET_SIZE, - .bNumConfigurations = NUM_CONFIGS -}; -#endif - /* * Static CDC ACM specific descriptors */ @@ -639,9 +625,6 @@ static void usbtty_init_instances (void) memset (device_instance, 0, sizeof (struct usb_device_instance)); device_instance->device_state = STATE_INIT; device_instance->device_descriptor = &device_descriptor; -#if defined(CONFIG_USBD_HS) - device_instance->qualifier_descriptor = &qualifier_descriptor; -#endif device_instance->event = usbtty_event_handler; device_instance->cdc_recv_setup = usbtty_cdc_setup; device_instance->bus = bus_instance; @@ -755,10 +738,6 @@ static void usbtty_init_terminal_type(short type) device_descriptor.idProduct = cpu_to_le16(CONFIG_USBD_PRODUCTID_CDCACM); -#if defined(CONFIG_USBD_HS) - qualifier_descriptor.bDeviceClass = - COMMUNICATIONS_DEVICE_CLASS; -#endif /* Assign endpoint indices */ tx_endpoint = ACM_TX_ENDPOINT; rx_endpoint = ACM_RX_ENDPOINT; @@ -787,9 +766,6 @@ static void usbtty_init_terminal_type(short type) device_descriptor.bDeviceClass = 0xFF; device_descriptor.idProduct = cpu_to_le16(CONFIG_USBD_PRODUCTID_GSERIAL); -#if defined(CONFIG_USBD_HS) - qualifier_descriptor.bDeviceClass = 0xFF; -#endif /* Assign endpoint indices */ tx_endpoint = GSERIAL_TX_ENDPOINT; rx_endpoint = GSERIAL_RX_ENDPOINT; @@ -937,9 +913,6 @@ static int usbtty_configured (void) static void usbtty_event_handler (struct usb_device_instance *device, usb_device_event_t event, int data) { -#if defined(CONFIG_USBD_HS) - int i; -#endif switch (event) { case DEVICE_RESET: case DEVICE_BUS_INACTIVE: @@ -950,29 +923,6 @@ static void usbtty_event_handler (struct usb_device_instance *device, break; case DEVICE_ADDRESS_ASSIGNED: -#if defined(CONFIG_USBD_HS) - /* - * is_usbd_high_speed routine needs to be defined by - * specific gadget driver - * It returns true if device enumerates at High speed - * Retuns false otherwise - */ - for (i = 0; i < NUM_ENDPOINTS; i++) { - if (((ep_descriptor_ptrs[i]->bmAttributes & - USB_ENDPOINT_XFERTYPE_MASK) == - USB_ENDPOINT_XFER_BULK) - && is_usbd_high_speed()) { - - ep_descriptor_ptrs[i]->wMaxPacketSize = - CONFIG_USBD_SERIAL_BULK_HS_PKTSIZE; - } - - endpoint_instance[i + 1].tx_packetSize = - ep_descriptor_ptrs[i]->wMaxPacketSize; - endpoint_instance[i + 1].rcv_packetSize = - ep_descriptor_ptrs[i]->wMaxPacketSize; - } -#endif usbtty_init_endpoints (); default: diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index e27aa368c9a..ac4d22044d3 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -51,10 +51,6 @@ #define CONFIG_USBD_SERIAL_INT_PKTSIZE UDC_INT_PACKET_SIZE #define CONFIG_USBD_SERIAL_BULK_PKTSIZE UDC_BULK_PACKET_SIZE -#if defined(CONFIG_USBD_HS) -#define CONFIG_USBD_SERIAL_BULK_HS_PKTSIZE UDC_BULK_HS_PACKET_SIZE -#endif - #define USBTTY_DEVICE_CLASS COMMUNICATIONS_DEVICE_CLASS #define USBTTY_BCD_DEVICE 0x00 diff --git a/drivers/usb/gadget/ep0.c b/drivers/usb/gadget/ep0.c index 6624f61b763..c256cc31fbd 100644 --- a/drivers/usb/gadget/ep0.c +++ b/drivers/usb/gadget/ep0.c @@ -371,26 +371,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device, } break; case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER: -#if defined(CONFIG_USBD_HS) - { - struct usb_qualifier_descriptor *qualifier_descriptor = - device->qualifier_descriptor; - - if (!qualifier_descriptor) - return -1; - - /* copy descriptor for this device */ - copy_config(urb, qualifier_descriptor, - sizeof(struct usb_qualifier_descriptor), - max); - - } - dbg_ep0(3, "copied qualifier descriptor, actual_length: 0x%x", - urb->actual_length); -#else return -1; -#endif - break; default: return -1; diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 25a84458f55..07587c7609b 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -28,8 +28,6 @@ /* Host */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Client */ -#define CONFIG_USBD_HS /* Framebuffer and LCD */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 2f09a264cbe..6f3524deb56 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -126,8 +126,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USBD_HS - /* USB Device Firmware Update support */ #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 19daad21cb5..4e51df123a6 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -25,8 +25,6 @@ /* Host */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Client */ -#define CONFIG_USBD_HS /* Command definition */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 48c3f015473..89546b857fe 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -170,6 +170,4 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USBD_HS - #endif diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 1458b187de2..1aaa3e67d60 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -26,7 +26,6 @@ /* USB */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USBD_HS /* Memory */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 298a8f5aa2a..5a78c68e2fc 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -38,7 +38,6 @@ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USBD_HS /* Miscellaneous configurable options */ diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 76771fd66ce..8e9dbefc496 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -81,6 +81,4 @@ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USBD_HS - #endif /* __CONFIG_H */ diff --git a/include/configs/librem5.h b/include/configs/librem5.h index 11b3fa6c857..377e3e7b3fa 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -27,8 +27,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_USBD_HS - #define CONSOLE_ON_UART1 #ifdef CONSOLE_ON_UART1 diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 6294fd1e2c4..96a48a97a30 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -145,6 +145,4 @@ /* Environment organization */ -#define CONFIG_USBD_HS - #endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 6c165521f7a..bd70b62bd20 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -101,6 +101,4 @@ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USBD_HS - #endif /* __CONFIG_H */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 5020b3bb71d..1d101977c28 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -11,8 +11,6 @@ #include "mx6_common.h" -#define CONFIG_USBD_HS - #define CONFIG_MXC_UART_BASE UART2_BASE /* MMC Configs */ diff --git a/include/configs/novena.h b/include/configs/novena.h index 79e49c74f85..b0d473eeee3 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -55,8 +55,6 @@ #ifdef CONFIG_CMD_USB #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Gadget part */ -#define CONFIG_USBD_HS #endif /* Extra U-Boot environment. */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 8af8883fad6..faf11d5a72a 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -26,8 +26,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USBD_HS - #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_DFU_ENV_SETTINGS \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 1b1787a3d3c..406a179842e 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -70,9 +70,6 @@ * we don't need to do it twice. */ -/* USB DRACO ID as default */ -#define CONFIG_USBD_HS - /* USB Device Firmware Update support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index fcc96749422..689914cb187 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -28,9 +28,6 @@ /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#ifdef CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USBD_HS -#endif /* CONFIG_CMD_USB_MASS_STORAGE */ #endif /* CONFIG_CMD_USB */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 56c90aa1032..a985c6f28f3 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -95,8 +95,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USBD_HS - /* USB Device Firmware Update support */ #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/usbdescriptors.h b/include/usbdescriptors.h index 9a503874511..641b4a3e6f2 100644 --- a/include/usbdescriptors.h +++ b/include/usbdescriptors.h @@ -227,21 +227,6 @@ struct usb_device_descriptor { u8 bNumConfigurations; } __attribute__ ((packed)); -#if defined(CONFIG_USBD_HS) -struct usb_qualifier_descriptor { - u8 bLength; - u8 bDescriptorType; - - u16 bcdUSB; - u8 bDeviceClass; - u8 bDeviceSubClass; - u8 bDeviceProtocol; - u8 bMaxPacketSize0; - u8 bNumConfigurations; - u8 breserved; -} __attribute__ ((packed)); -#endif - struct usb_string_descriptor { u8 bLength; u8 bDescriptorType; /* 0x03 */ diff --git a/include/usbdevice.h b/include/usbdevice.h index 611cd6e4abf..80c5af0cbcd 100644 --- a/include/usbdevice.h +++ b/include/usbdevice.h @@ -196,10 +196,6 @@ struct usb_bus_instance; #define USB_DT_INTERFACE 0x04 #define USB_DT_ENDPOINT 0x05 -#if defined(CONFIG_USBD_HS) -#define USB_DT_QUAL 0x06 -#endif - #define USB_DT_HID (USB_TYPE_CLASS | 0x01) #define USB_DT_REPORT (USB_TYPE_CLASS | 0x02) #define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03) @@ -279,11 +275,7 @@ struct usb_bus_instance; * USB Spec Release number */ -#if defined(CONFIG_USBD_HS) -#define USB_BCD_VERSION 0x0200 -#else #define USB_BCD_VERSION 0x0110 -#endif /* @@ -552,9 +544,6 @@ struct usb_device_instance { /* generic */ char *name; struct usb_device_descriptor *device_descriptor; /* per device descriptor */ -#if defined(CONFIG_USBD_HS) - struct usb_qualifier_descriptor *qualifier_descriptor; -#endif void (*event) (struct usb_device_instance *device, usb_device_event_t event, int data); @@ -644,14 +633,6 @@ struct usb_string_descriptor *usbd_get_string (u8); struct usb_device_descriptor *usbd_device_device_descriptor(struct usb_device_instance *, int); -#if defined(CONFIG_USBD_HS) -/* - * is_usbd_high_speed routine needs to be defined by specific gadget driver - * It returns true if device enumerates at High speed - * Retuns false otherwise - */ -int is_usbd_high_speed(void); -#endif int usbd_endpoint_halted (struct usb_device_instance *device, int endpoint); void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad); void usbd_tx_complete (struct usb_endpoint_instance *endpoint); -- cgit v1.3.1 From 46df77669ec4d8f04b0faf770d661f79971775a6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:50 -0500 Subject: nxp: Rename CONFIG_U_BOOT_HDR_SIZE to FSL_U_BOOT_HDR_SIZE This is always defined to 16K, so we move this over to include/fsl_validate.h to start with. Next, we rename this from CONFIG_ to FSL_. Coalesce the various comments around this definition to be in fsl_validate.h as well to explain the usage. Signed-off-by: Tom Rini --- board/freescale/common/fsl_chain_of_trust.c | 2 +- drivers/mtd/nand/raw/fsl_ifc_spl.c | 6 +++--- include/configs/T104xRDB.h | 8 +------- include/configs/ls1021atsn.h | 15 --------------- include/configs/ls1021atwr.h | 19 ------------------- include/configs/ls1043a_common.h | 27 --------------------------- include/configs/ls1046a_common.h | 13 ------------- include/configs/ls1088a_common.h | 13 ------------- include/fsl_validate.h | 7 +++++++ 9 files changed, 12 insertions(+), 98 deletions(-) (limited to 'include') diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 9ca350ed468..029d06bbf9d 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -143,7 +143,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) (image_entry_noargs_t)(unsigned long)spl_image->entry_point; hdr_addr = (spl_image->entry_point + spl_image->size - - CONFIG_U_BOOT_HDR_SIZE); + FSL_U_BOOT_HDR_SIZE); spl_validate_uboot(hdr_addr, (uintptr_t)spl_image->entry_point); /* * In case of failure in validation, spl_validate_uboot would diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index 3b464ce10ce..60a865b5667 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -278,11 +278,11 @@ void nand_boot(void) * U-Boot header is appended at end of U-boot image, so * calculate U-boot header address using U-boot header size. */ -#define CONFIG_U_BOOT_HDR_ADDR \ +#define FSL_U_BOOT_HDR_ADDR \ ((CFG_SYS_NAND_U_BOOT_START + \ CFG_SYS_NAND_U_BOOT_SIZE) - \ - CONFIG_U_BOOT_HDR_SIZE) - spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR, + FSL_U_BOOT_HDR_SIZE) + spl_validate_uboot(FSL_U_BOOT_HDR_ADDR, CFG_SYS_NAND_U_BOOT_START); /* * In case of failure in validation, spl_validate_uboot would diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 5bdc2105f56..7a5bf937e4c 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -20,13 +20,7 @@ #ifdef CONFIG_MTD_RAW_NAND #ifdef CONFIG_NXP_ESBC -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. - */ -#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ - CONFIG_U_BOOT_HDR_SIZE) +#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + (16 << 10)) #else #define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10) #endif diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 5612c60ae90..b15c4a238bc 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -38,21 +38,6 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001 -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_NXP_ESBC -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -#endif /* ifdef CONFIG_NXP_ESBC */ - -#ifdef CONFIG_U_BOOT_HDR_SIZE -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw U-Boot image instead of FIT image. - */ -#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ -#endif - #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 281b26fa2ba..9b22a2db21a 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -37,25 +37,6 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001 -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_NXP_ESBC -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. - */ -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -#endif /* ifdef CONFIG_NXP_ESBC */ - -#ifdef CONFIG_U_BOOT_HDR_SIZE -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ -#endif - #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index d0380b33732..685e7e65d15 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -41,37 +41,10 @@ /* Serial Port */ #define CFG_SYS_NS16550_CLK (get_serial_clock()) -/* SD boot SPL */ -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_NXP_ESBC -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#endif /* ifdef CONFIG_NXP_ESBC */ -#endif - /* NAND SPL */ #ifdef CONFIG_NAND_BOOT #define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE #define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE - -#ifdef CONFIG_NXP_ESBC -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -#endif /* ifdef CONFIG_NXP_ESBC */ - -#ifdef CONFIG_U_BOOT_HDR_SIZE -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ - #endif /* GPIO */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 250891e9e30..ae9dc0c73b0 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -41,19 +41,6 @@ /* Serial Port */ #define CFG_SYS_NS16550_CLK (get_serial_clock()) -/* SD boot SPL */ -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_NXP_ESBC -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#endif /* ifdef CONFIG_NXP_ESBC */ -#endif - /* NAND SPL */ #ifdef CONFIG_NAND_BOOT #define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index bcba8d81c04..86c5d48c0de 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -133,17 +133,4 @@ unsigned long long get_qixis_addr(void); " 0x580e00000 \0" #endif -#ifdef CONFIG_SPL -#ifdef CONFIG_NXP_ESBC -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#endif /* ifdef CONFIG_NXP_ESBC */ - -#endif - #endif /* __LS1088_COMMON_H */ diff --git a/include/fsl_validate.h b/include/fsl_validate.h index 252d499e7b1..fbcbd424967 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -280,4 +280,11 @@ int fsl_setenv_chain_of_trust(void); * Architecture header (appended to U-boot image). */ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr); + +/* + * This header is appended at end of image and copied to DDR along + * with the U-Boot image and later used as part of the validation + * flow + */ +#define FSL_U_BOOT_HDR_SIZE (16 << 10) #endif -- cgit v1.3.1 From 8214b772cf213f1f02e5e33f4a5158f52d9d2c23 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:51 -0500 Subject: T104xRDB: Remove non-TARGET_T1042D4RDB variants At this point only the TARGET_T1042D4RDB variant of this is supported in tree, so remove the remaining parts of the other platforms. Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/Kconfig | 17 ---------- arch/powerpc/include/asm/fsl_secure_boot.h | 2 -- board/freescale/t104xrdb/Kconfig | 4 +-- board/freescale/t104xrdb/cpld.h | 2 +- board/freescale/t104xrdb/eth.c | 19 ----------- board/freescale/t104xrdb/t104xrdb.c | 19 +---------- include/configs/T104xRDB.h | 52 +++--------------------------- 7 files changed, 7 insertions(+), 108 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 03373bf8692..3275d4fa9b8 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -200,14 +200,6 @@ config TARGET_T1024RDB imply CMD_EEPROM imply PANIC_HANG -config TARGET_T1042RDB - bool "Support T1042RDB" - select ARCH_T1042 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - select SUPPORT_SPL - select PHYS_64BIT - select SYS_L3_SIZE_256KB - config TARGET_T1042D4RDB bool "Support T1042D4RDB" select ARCH_T1042 @@ -217,15 +209,6 @@ config TARGET_T1042D4RDB select SYS_L3_SIZE_256KB imply PANIC_HANG -config TARGET_T1042RDB_PI - bool "Support T1042RDB_PI" - select ARCH_T1042 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - select SUPPORT_SPL - select PHYS_64BIT - select SYS_L3_SIZE_256KB - imply PANIC_HANG - config TARGET_T2080QDS bool "Support T2080QDS" select ARCH_T2080 diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 09f37ec3e49..236098e718e 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -17,9 +17,7 @@ #if defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ - defined(CONFIG_TARGET_T1042RDB) || \ defined(CONFIG_TARGET_T1042D4RDB) || \ - defined(CONFIG_TARGET_T1042RDB_PI) || \ defined(CONFIG_ARCH_T1024) #undef CFG_SYS_INIT_L3_ADDR #define CFG_SYS_INIT_L3_ADDR 0xbff00000 diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig index e33d3173650..e4814915e33 100644 --- a/board/freescale/t104xrdb/Kconfig +++ b/board/freescale/t104xrdb/Kconfig @@ -1,6 +1,4 @@ -if TARGET_T1040RDB || TARGET_T1040D4RDB || \ - TARGET_T1042RDB || TARGET_T1042D4RDB || \ - TARGET_T1042RDB_PI +if TARGET_T1042D4RDB config SYS_BOARD default "t104xrdb" diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h index 769883f9461..0384202fbcb 100644 --- a/board/freescale/t104xrdb/cpld.h +++ b/board/freescale/t104xrdb/cpld.h @@ -20,7 +20,7 @@ struct cpld_data { u8 int_status; /* 0x12 - Interrupt status Register */ u8 flash_ctl_status; /* 0x13 - Flash control and status register */ u8 fan_ctl_status; /* 0x14 - Fan control and status register */ -#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) +#if defined(CONFIG_TARGET_T1042D4RDB) u8 int_mask; /* 0x15 - Interrupt mask Register */ #else u8 led_ctl_status; /* 0x15 - LED control and status register */ diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index c011aa96fbe..3906c8381e0 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -39,25 +39,6 @@ int board_eth_init(struct bd_info *bis) int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { -#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) - case PHY_INTERFACE_MODE_SGMII: - /* T1040RDB & T1040D4RDB only supports SGMII on - * DTSEC3 - */ - fm_info_set_phy_address(FM1_DTSEC3, - CFG_SYS_SGMII1_PHY_ADDR); - break; -#endif -#ifdef CONFIG_TARGET_T1042RDB - case PHY_INTERFACE_MODE_SGMII: - /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */ - if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i)) - fm_info_set_phy_address(i, 0); - /* T1042RDB only supports SGMII on DTSEC3 */ - fm_info_set_phy_address(FM1_DTSEC3, - CFG_SYS_SGMII1_PHY_ADDR); - break; -#endif #ifdef CONFIG_TARGET_T1042D4RDB case PHY_INTERFACE_MODE_SGMII: /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 45ebdd30004..8cec71217a7 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -34,7 +34,7 @@ int checkboard(void) struct cpu_type *cpu = gd->arch.cpu; u8 sw; -#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) +#if defined(CONFIG_TARGET_T1042D4RDB) printf("Board: %sD4RDB\n", cpu->name); #else printf("Board: %sRDB\n", cpu->name); @@ -110,23 +110,6 @@ int misc_init_r(void) CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); -#if defined(CONFIG_TARGET_T1040D4RDB) - if (hwconfig("qe-tdm")) { - CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) | - MISC_MUX_QE_TDM); - printf("QECSR : 0x%02x, mux to qe-tdm\n", - CPLD_READ(sfp_ctl_status)); - } - /* Mask all CPLD interrupt sources, except QSGMII interrupts */ - if (CPLD_READ(sw_ver) < 0x03) { - debug("CPLD SW version 0x%02x doesn't support int_mask\n", - CPLD_READ(sw_ver)); - } else { - CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL & - ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2)); - } -#endif - return 0; } diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 7a5bf937e4c..cfde8ecf9c6 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -127,24 +127,10 @@ #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 -#if defined(CONFIG_TARGET_T1042RDB_PI) -#define CPLD_DIU_SEL_DFP 0x80 -#elif defined(CONFIG_TARGET_T1042D4RDB) +#if defined(CONFIG_TARGET_T1042D4RDB) #define CPLD_DIU_SEL_DFP 0xc0 #endif -#if defined(CONFIG_TARGET_T1040D4RDB) -#define CPLD_INT_MASK_ALL 0xFF -#define CPLD_INT_MASK_THERM 0x80 -#define CPLD_INT_MASK_DVI_DFP 0x40 -#define CPLD_INT_MASK_QSGMII1 0x20 -#define CPLD_INT_MASK_QSGMII2 0x10 -#define CPLD_INT_MASK_SGMI1 0x08 -#define CPLD_INT_MASK_SGMI2 0x04 -#define CPLD_INT_MASK_TDMR1 0x02 -#define CPLD_INT_MASK_TDMR2 0x01 -#endif - #define CFG_SYS_CPLD_BASE 0xffdf0000 #define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) #define CFG_SYS_CSPR2_EXT (0xf) @@ -266,9 +252,7 @@ #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x8 -#if defined(CONFIG_TARGET_T1042RDB_PI) || \ - defined(CONFIG_TARGET_T1040D4RDB) || \ - defined(CONFIG_TARGET_T1042D4RDB) +#if defined(CONFIG_TARGET_T1042D4RDB) /* * RTC configuration */ @@ -350,36 +334,16 @@ #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_FMAN_ENET -#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) -#define CFG_SYS_SGMII1_PHY_ADDR 0x03 -#elif defined(CONFIG_TARGET_T1040D4RDB) -#define CFG_SYS_SGMII1_PHY_ADDR 0x01 -#elif defined(CONFIG_TARGET_T1042D4RDB) +#if defined(CONFIG_TARGET_T1042D4RDB) #define CFG_SYS_SGMII1_PHY_ADDR 0x02 #define CFG_SYS_SGMII2_PHY_ADDR 0x03 #define CFG_SYS_SGMII3_PHY_ADDR 0x01 #endif -#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) -#define CFG_SYS_RGMII1_PHY_ADDR 0x04 -#define CFG_SYS_RGMII2_PHY_ADDR 0x05 -#else #define CFG_SYS_RGMII1_PHY_ADDR 0x01 #define CFG_SYS_RGMII2_PHY_ADDR 0x02 #endif -/* Enable VSC9953 L2 Switch driver on T1040 SoC */ -#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) -#ifdef CONFIG_TARGET_T1040RDB -#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 -#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 -#else -#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 -#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c -#endif -#endif -#endif - /* * Miscellaneous configurable options */ @@ -402,15 +366,7 @@ #define __USB_PHY_TYPE utmi #define RAMDISKFILE "t104xrdb/ramdisk.uboot" -#ifdef CONFIG_TARGET_T1040RDB -#define FDTFILE "t1040rdb/t1040rdb.dtb" -#elif defined(CONFIG_TARGET_T1042RDB_PI) -#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" -#elif defined(CONFIG_TARGET_T1042RDB) -#define FDTFILE "t1042rdb/t1042rdb.dtb" -#elif defined(CONFIG_TARGET_T1040D4RDB) -#define FDTFILE "t1042rdb/t1040d4rdb.dtb" -#elif defined(CONFIG_TARGET_T1042D4RDB) +#if defined(CONFIG_TARGET_T1042D4RDB) #define FDTFILE "t1042rdb/t1042d4rdb.dtb" #endif -- cgit v1.3.1 From 7ee2f977b7913ac7c1eda11051fe7401ab73ab89 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:28 -0500 Subject: Convert CONFIG_NEVER_ASSERT_ODT_TO_CPU to Kconfig This converts the following to Kconfig: CONFIG_NEVER_ASSERT_ODT_TO_CPU Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc83xx/Kconfig | 3 +++ include/configs/MPC837XERDB.h | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 563f52c5fdb..b695c7e4d81 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -200,6 +200,9 @@ config FSL_SERDES bool "SerDes initialization" depends on !MPC83XX_SERDES +config NEVER_ASSERT_ODT_TO_CPU + bool "Never assert ODT to internal IOs" + source "board/freescale/mpc837xerdb/Kconfig" source "board/gdsys/mpc8308/Kconfig" diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 7b932eb3890..e0ac9338d32 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -55,8 +55,6 @@ #define CFG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) -#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ - /* * Manually set up DDR parameters */ -- cgit v1.3.1 From 2c065aeeee8c4033f41836eafef0d949c94bf769 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:30 -0500 Subject: mtd: ubi: Finish moving configuration to Kconfig We have some unused and undefined symbols to remove references to, so do that. Move the final things that we do set (or need to keep unset) to Kconfig instead. Signed-off-by: Tom Rini --- drivers/mtd/ubi/Kconfig | 12 ++++++++++++ include/ubi_uboot.h | 22 ---------------------- 2 files changed, 12 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index 67a3cf1d7a5..5783d36c048 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -20,6 +20,18 @@ config MTD_UBI if MTD_UBI +config MTD_UBI_BLOCK + def_bool n + +config MTD_UBI_MODULE + def_bool y + help + ubi_init() disables returning error codes when built into the Linux + kernel so that it doesn't hang the Linux kernel boot process. Since + the U-Boot driver code depends on getting valid error codes from this + function we just tell the UBI layer that we are building as a module + (which only enables the additional error reporting). + config MTD_UBI_WL_THRESHOLD int "UBI wear-leveling threshold" default 4096 diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index 0770228cd89..6da348eb628 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -34,28 +34,6 @@ #include -/* configurable */ -#define CONFIG_MTD_UBI_BEB_RESERVE 1 - -/* debug options (Linux: drivers/mtd/ubi/Kconfig.debug) */ -#undef CONFIG_MTD_UBI_DEBUG -#undef CONFIG_MTD_UBI_DEBUG_PARANOID -#undef CONFIG_MTD_UBI_DEBUG_MSG -#undef CONFIG_MTD_UBI_DEBUG_MSG_EBA -#undef CONFIG_MTD_UBI_DEBUG_MSG_WL -#undef CONFIG_MTD_UBI_DEBUG_MSG_IO -#undef CONFIG_MTD_UBI_DEBUG_MSG_BLD - -#undef CONFIG_MTD_UBI_BLOCK - -/* ubi_init() disables returning error codes when built into the Linux - * kernel so that it doesn't hang the Linux kernel boot process. Since - * the U-Boot driver code depends on getting valid error codes from this - * function we just tell the UBI layer that we are building as a module - * (which only enables the additional error reporting). - */ -#define CONFIG_MTD_UBI_MODULE - /* build.c */ #define get_device(...) #define put_device(...) -- cgit v1.3.1 From dc2c451a94e11e0b5ac006fd603b746632734d5c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:32 -0500 Subject: valgrind: Rework test for unsupported platforms Change things so that on an unsupported platform we will #error rather than undef the feature. Signed-off-by: Tom Rini --- include/valgrind/valgrind.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/valgrind/valgrind.h b/include/valgrind/valgrind.h index e59a7fde321..5d4fa5f43b4 100644 --- a/include/valgrind/valgrind.h +++ b/include/valgrind/valgrind.h @@ -121,7 +121,9 @@ #else /* If we're not compiling for our target platform, don't generate any inline asms. */ -# undef CONFIG_VALGRIND +# if IS_ENABLED(CONFIG_VALGRIND) +# error "Unsupported platform for valgrind" +# endif #endif -- cgit v1.3.1 From 218ce3695bfd02f048443f888137e134dbcfcbfc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:34 -0500 Subject: global: Remove undef CONFIG_... for unused values We have a number of places that undef CONFIG_... while we never reference CONFIG_... in the first place. Remove these lines. Signed-off-by: Tom Rini --- common/cli_hush.c | 1 - drivers/ddr/marvell/axp/ddr3_axp_config.h | 2 -- include/configs/P1010RDB.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/s5p4418_nanopi2.h | 2 -- 5 files changed, 7 deletions(-) (limited to 'include') diff --git a/common/cli_hush.c b/common/cli_hush.c index 1467ff81b35..a80b84756bb 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -112,7 +112,6 @@ #define applet_name "hush" #include "standalone.h" #define hush_main main -#undef CONFIG_FEATURE_SH_FANCY_PROMPT #define BB_BANNER #endif #endif diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h index ab09e72623a..04bb4ed8f34 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_config.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h @@ -59,12 +59,10 @@ /* Marvell boards specific configurations */ #if defined(DB_78X60_PCAC) -#undef CONFIG_SPD_EEPROM #define STATIC_TRAINING #endif #if defined(DB_78X60_AMC) -#undef CONFIG_SPD_EEPROM #undef DRAM_ECC #define DRAM_ECC 1 #endif diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 2267a7a9c8b..afb602c5bce 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -309,7 +309,6 @@ extern unsigned long get_sdram_size(void); #endif /* Serial Port */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_SYS_NS16550_CLK get_bus_freq(0) #define CFG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index c05904a813d..74627b2e630 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -302,7 +302,6 @@ * open - index 2 * shorted - index 1 */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_SYS_NS16550_CLK get_bus_freq(0) #define CFG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index e071d4da5e8..b4b2dbd0386 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -66,8 +66,6 @@ /*----------------------------------------------------------------------- * High Level System Configuration */ -/* Not used: not need IRQ/FIQ stuff */ -#undef CONFIG_USE_IRQ /* decrementer freq: 1ms ticks */ /*----------------------------------------------------------------------- -- cgit v1.3.1 From 04501ecca26d0f3ad10065775c1bddda02a02db0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:36 -0500 Subject: global: Migrate CONFIG_ARM_GIC_BASE_ADDRESS to CFG Perform a simple rename of CONFIG_ARM_GIC_BASE_ADDRESS to CFG_ARM_GIC_BASE_ADDRESS Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- arch/arm/cpu/armv7/virt-v7.c | 4 ++-- include/configs/arndale.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 5ee6577c2c3..a303039ba50 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -112,8 +112,8 @@ ENTRY(_do_nonsec_entry) ENDPROC(_do_nonsec_entry) .macro get_cbar_addr addr -#ifdef CONFIG_ARM_GIC_BASE_ADDRESS - ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS +#ifdef CFG_ARM_GIC_BASE_ADDRESS + ldr \addr, =CFG_ARM_GIC_BASE_ADDRESS #else mrc p15, 4, \addr, c15, c0, 0 @ read CBAR bfc \addr, #0, #15 @ clear reserved bits diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 5ffeca13d91..c82b215b6f9 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -26,8 +26,8 @@ static unsigned int read_id_pfr1(void) static unsigned long get_gicd_base_address(void) { -#ifdef CONFIG_ARM_GIC_BASE_ADDRESS - return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; +#ifdef CFG_ARM_GIC_BASE_ADDRESS + return CFG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; #else unsigned periphbase; diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 7a244769e30..8acc525b11c 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -19,6 +19,6 @@ #define CONFIG_SMP_PEN_ADDR 0x02020000 /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ -#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 +#define CFG_ARM_GIC_BASE_ADDRESS 0x10480000 #endif /* __CONFIG_H */ -- cgit v1.3.1 From b8089c6d688dd031d07274fc07678a2005b466e9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:38 -0500 Subject: global: Migrate CONFIG_DFU_ALT et al to CFG Perform simple renames of: CONFIG_DFU_ALT to CFG_DFU_ALT CONFIG_DFU_ALT_BOOT_EMMC to CFG_DFU_ALT_BOOT_EMMC CONFIG_DFU_ALT_BOOT_SD to CFG_DFU_ALT_BOOT_SD CONFIG_DFU_ALT_SYSTEM to CFG_DFU_ALT_SYSTEM CONFIG_DFU_ENV_SETTINGS to CFG_DFU_ENV_SETTINGS Signed-off-by: Tom Rini --- board/samsung/common/exynos5-dt.c | 4 ++-- board/samsung/odroid/odroid.c | 4 ++-- include/configs/mx7dsabresd.h | 4 ++-- include/configs/odroid.h | 8 ++++---- include/configs/odroid_xu3.h | 8 ++++---- include/configs/pico-imx6.h | 4 ++-- include/configs/pico-imx6ul.h | 4 ++-- include/configs/pico-imx7d.h | 4 ++-- include/configs/s5p_goni.h | 4 ++-- include/configs/trats.h | 4 ++-- include/configs/trats2.h | 4 ++-- include/configs/warp7.h | 4 ++-- 12 files changed, 28 insertions(+), 28 deletions(-) (limited to 'include') diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index 0d77a57f808..cde77d79a0f 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -179,9 +179,9 @@ char *get_dfu_alt_boot(char *interface, char *devstr) return NULL; if (IS_SD(mmc)) - alt_boot = CONFIG_DFU_ALT_BOOT_SD; + alt_boot = CFG_DFU_ALT_BOOT_SD; else - alt_boot = CONFIG_DFU_ALT_BOOT_EMMC; + alt_boot = CFG_DFU_ALT_BOOT_EMMC; return alt_boot; } diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 35e4cee74f4..39a60e4ad29 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -94,8 +94,8 @@ char *get_dfu_alt_boot(char *interface, char *devstr) if (mmc_init(mmc)) return NULL; - alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD : - CONFIG_DFU_ALT_BOOT_EMMC; + alt_boot = IS_SD(mmc) ? CFG_DFU_ALT_BOOT_SD : + CFG_DFU_ALT_BOOT_EMMC; return alt_boot; } diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index bd70b62bd20..e56b6101af4 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -44,7 +44,7 @@ "initrd_high=0xffffffff\0" \ "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ -#define CONFIG_DFU_ENV_SETTINGS \ +#define CFG_DFU_ENV_SETTINGS \ "dfu_alt_info=image raw 0 0x800000;"\ "u-boot raw 0 0x4000;"\ "bootimg part 0 1;"\ @@ -53,7 +53,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ UPDATE_M4_ENV \ CONFIG_MFG_ENV_SETTINGS \ - CONFIG_DFU_ENV_SETTINGS \ + CFG_DFU_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index f252b349437..e2331e45cdf 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -27,7 +27,7 @@ #define PARTS_BOOT "boot" #define PARTS_ROOT "platform" -#define CONFIG_DFU_ALT \ +#define CFG_DFU_ALT \ "uImage fat 0 1;" \ "zImage fat 0 1;" \ "Image.itb fat 0 1;" \ @@ -39,13 +39,13 @@ #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) -#define CONFIG_DFU_ALT_BOOT_EMMC \ +#define CFG_DFU_ALT_BOOT_EMMC \ "u-boot raw 0x3e 0x800 mmcpart 1;" \ "bl1 raw 0x0 0x1e mmcpart 1;" \ "bl2 raw 0x1e 0x1d mmcpart 1;" \ "tzsw raw 0x83e 0x138 mmcpart 1\0" -#define CONFIG_DFU_ALT_BOOT_SD \ +#define CFG_DFU_ALT_BOOT_SD \ "u-boot raw 0x3f 0x800;" \ "bl1 raw 0x1 0x1e;" \ "bl2 raw 0x1f 0x1d;" \ @@ -132,7 +132,7 @@ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \ - "dfu_alt_system="CONFIG_DFU_ALT \ + "dfu_alt_system="CFG_DFU_ALT \ "dfu_alt_info=Please reset the board\0" \ "consoleon=set console console=ttySAC1,115200n8; save; reset\0" \ "consoleoff=set console console=ram; save; reset\0" \ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index bf63a4de076..e4a81499a72 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -20,7 +20,7 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 #define DFU_MANIFEST_POLL_TIMEOUT 25000 -#define CONFIG_DFU_ALT_SYSTEM \ +#define CFG_DFU_ALT_SYSTEM \ "uImage fat 0 1;" \ "zImage fat 0 1;" \ "Image.itb fat 0 1;" \ @@ -34,14 +34,14 @@ "boot part 0 1;" \ "root part 0 2\0" -#define CONFIG_DFU_ALT_BOOT_EMMC \ +#define CFG_DFU_ALT_BOOT_EMMC \ "u-boot raw 0x3e 0x800 mmcpart 1;" \ "bl1 raw 0x0 0x1e mmcpart 1;" \ "bl2 raw 0x1e 0x1d mmcpart 1;" \ "tzsw raw 0x83e 0x200 mmcpart 1;" \ "params.bin raw 0x1880 0x20\0" -#define CONFIG_DFU_ALT_BOOT_SD \ +#define CFG_DFU_ALT_BOOT_SD \ "u-boot raw 0x3f 0x800;" \ "bl1 raw 0x1 0x1e;" \ "bl2 raw 0x1f 0x1d;" \ @@ -75,7 +75,7 @@ "mmcrootdev=0\0" \ "mmcbootpart=1\0" \ "mmcrootpart=2\0" \ - "dfu_alt_system="CONFIG_DFU_ALT_SYSTEM \ + "dfu_alt_system="CFG_DFU_ALT_SYSTEM \ "dfu_alt_info=Autoset by THOR/DFU command run.\0" #endif /* __CONFIG_H */ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 6d7873daa0a..719b7014405 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -21,7 +21,7 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_DFU_ENV_SETTINGS \ +#define CFG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ "spl raw 0x2 0x400;" \ "u-boot raw 0x8a 0x1000;" \ @@ -47,7 +47,7 @@ "fdt_addr_r=0x18000000\0" \ "fdt_addr=0x18000000\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - CONFIG_DFU_ENV_SETTINGS \ + CFG_DFU_ENV_SETTINGS \ "finduuid=part uuid mmc 0:1 uuid\0" \ "findfdt="\ "if test $baseboard = hobbit && test $board_rev = MX6Q ; then " \ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index faf11d5a72a..36f648f6340 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -28,7 +28,7 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_DFU_ENV_SETTINGS \ +#define CFG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ "spl raw 0x2 0x400;" \ "u-boot raw 0x8a 0x400;" \ @@ -63,7 +63,7 @@ "ramdiskaddr=0x83000000\0" \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "mmcautodetect=yes\0" \ - CONFIG_DFU_ENV_SETTINGS \ + CFG_DFU_ENV_SETTINGS \ "findfdt=" \ "if test $fdtfile = ask ; then " \ "bootmenu -1; fi;" \ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 83907b06ebb..58192151042 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -15,7 +15,7 @@ /* MMC Config */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_DFU_ENV_SETTINGS \ +#define CFG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ "spl raw 0x2 0x400;" \ "u-boot raw 0x8a 0x1000;" \ @@ -67,7 +67,7 @@ "ramdisk_addr_r=0x83000000\0" \ "ramdiskaddr=0x83000000\0" \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - CONFIG_DFU_ENV_SETTINGS \ + CFG_DFU_ENV_SETTINGS \ "findfdt=" \ "if test $fdtfile = ask ; then " \ "bootmenu -1; fi;" \ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index da83db1f68a..555bedb93d6 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -35,7 +35,7 @@ #define PARTS_CSC "csc" #define PARTS_UMS "ums" -#define CONFIG_DFU_ALT \ +#define CFG_DFU_ALT \ "u-boot raw 0x80 0x400;" \ "uImage ext4 0 2;" \ "exynos3-goni.dtb ext4 0 2;" \ @@ -102,7 +102,7 @@ "ubiblock=8\0" \ "ubi=enabled\0" \ "opts=always_resume=1\0" \ - "dfu_alt_info=" CONFIG_DFU_ALT "\0" + "dfu_alt_info=" CFG_DFU_ALT "\0" /* Goni has 3 banks of DRAM, but swap the bank */ #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ diff --git a/include/configs/trats.h b/include/configs/trats.h index ec18842bbe8..3eac66539df 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -39,7 +39,7 @@ "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ -#define CONFIG_DFU_ALT \ +#define CFG_DFU_ALT \ "u-boot raw 0x80 0x400;" \ "/uImage ext4 0 2;" \ "/modem.bin ext4 0 2;" \ @@ -98,7 +98,7 @@ "mmcrootpart=5\0" \ "opts=always_resume=1\0" \ "partitions=" PARTS_DEFAULT \ - "dfu_alt_info=" CONFIG_DFU_ALT \ + "dfu_alt_info=" CFG_DFU_ALT \ "spladdr=0x40000100\0" \ "splsize=0x200\0" \ "splfile=falcon.bin\0" \ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 4d39b4005bd..18fca09a380 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -40,7 +40,7 @@ "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ -#define CONFIG_DFU_ALT \ +#define CFG_DFU_ALT \ "u-boot raw 0x80 0x800;" \ "/uImage ext4 0 2;" \ "/modem.bin ext4 0 2;" \ @@ -86,7 +86,7 @@ "mmcrootpart=5\0" \ "opts=always_resume=1\0" \ "partitions=" PARTS_DEFAULT \ - "dfu_alt_info=" CONFIG_DFU_ALT \ + "dfu_alt_info=" CFG_DFU_ALT \ "uartpath=ap\0" \ "usbpath=ap\0" \ "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index a985c6f28f3..188180da54e 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -16,7 +16,7 @@ /* MMC Config*/ #define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR -#define CONFIG_DFU_ENV_SETTINGS \ +#define CFG_DFU_ENV_SETTINGS \ "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \ /* When booting with FIT specify the node entry containing boot.scr */ @@ -27,7 +27,7 @@ #endif #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_DFU_ENV_SETTINGS \ + CFG_DFU_ENV_SETTINGS \ "script=boot.scr\0" \ "bootscr_fitimage_name=bootscr\0" \ "script_signed=boot.scr.imx-signed\0" \ -- cgit v1.3.1 From 42119de8b51ca703d5e6c489b59c99aa3db7ab30 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:39 -0500 Subject: global: Migrate CONFIG_DW_WDT_CLOCK_KHZ to CFG Perform a simple rename of CONFIG_DW_WDT_CLOCK_KHZ to CFG_DW_WDT_CLOCK_KHZ Signed-off-by: Tom Rini --- drivers/watchdog/designware_wdt.c | 2 +- include/configs/socfpga_common.h | 2 +- include/configs/socfpga_soc64_common.h | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index f8df1916b5f..447a22d3b36 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -132,7 +132,7 @@ static int designware_wdt_probe(struct udevice *dev) goto err; } #else - priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ; + priv->clk_khz = CFG_DW_WDT_CLOCK_KHZ; #endif if (CONFIG_IS_ENABLED(DM_RESET) && diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 088cd4d4f7f..d0f5331d451 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -64,7 +64,7 @@ /* * L4 Watchdog */ -#define CONFIG_DW_WDT_CLOCK_KHZ 25000 +#define CFG_DW_WDT_CLOCK_KHZ 25000 /* * NAND Support diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 47089f312d2..df3927297bb 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -90,10 +90,10 @@ #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 #ifndef __ASSEMBLY__ unsigned int cm_get_l4_sys_free_clk_hz(void); -#define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) +#define CFG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) #endif #else -#define CONFIG_DW_WDT_CLOCK_KHZ 100000 +#define CFG_DW_WDT_CLOCK_KHZ 100000 #endif /* -- cgit v1.3.1 From acf29d8ccb56e1c366a8c360cfa7cc8f44d4d281 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:40 -0500 Subject: global: Migrate CONFIG_ENV_FLAGS_LIST_STATIC to CFG Perform a simple rename of CONFIG_ENV_FLAGS_LIST_STATIC to CFG_ENV_FLAGS_LIST_STATIC Signed-off-by: Tom Rini --- README | 6 +++--- include/configs/aristainetos2.h | 2 +- include/configs/imx6q-bosch-acc.h | 2 +- include/env_flags.h | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/README b/README index 2944646665a..e19aa1f722c 100644 --- a/README +++ b/README @@ -1066,7 +1066,7 @@ The following options need to be configured: The same can be accomplished in a more flexible way for any variable by configuring the type of access to allow for those variables in the ".flags" variable - or define CONFIG_ENV_FLAGS_LIST_STATIC. + or define CFG_ENV_FLAGS_LIST_STATIC. - Protected RAM: CONFIG_PRAM @@ -1405,7 +1405,7 @@ Configuration Settings: Use buffered writes to flash. - CONFIG_ENV_FLAGS_LIST_DEFAULT -- CONFIG_ENV_FLAGS_LIST_STATIC +- CFG_ENV_FLAGS_LIST_STATIC Enable validation of the values given to environment variables when calling env set. Variables can be restricted to only decimal, hexadecimal, or boolean. If CONFIG_CMD_NET is also defined, @@ -1436,7 +1436,7 @@ Configuration Settings: Define this to a list (string) to define the ".flags" environment variable in the default or embedded environment. - - CONFIG_ENV_FLAGS_LIST_STATIC + - CFG_ENV_FLAGS_LIST_STATIC Define this to a list (string) to define validation that should be done if an entry is not found in the ".flags" environment variable. To override a setting in the static diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 85413545715..ff213a41b8f 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -418,7 +418,7 @@ /* UBI support */ -#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ +#define CFG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ "sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" #endif /* __ARISTAINETOS2_CONFIG_H */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 99da081cdae..392f97050a6 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -45,7 +45,7 @@ "save_env=env save; env save\0" \ "altbootcmd=run handle_ustate; run switch_bootset; run save_env; run bootcmd\0" -#define CONFIG_ENV_FLAGS_LIST_STATIC \ +#define CFG_ENV_FLAGS_LIST_STATIC \ "bootset:bw," \ "clone_pending:bw," \ "endurance_test:bw," \ diff --git a/include/env_flags.h b/include/env_flags.h index 718d72773ca..6bd574c2bdb 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -35,8 +35,8 @@ enum env_flags_varaccess { #define ENV_FLAGS_VARTYPE_LOC 0 #define ENV_FLAGS_VARACCESS_LOC 1 -#ifndef CONFIG_ENV_FLAGS_LIST_STATIC -#define CONFIG_ENV_FLAGS_LIST_STATIC "" +#ifndef CFG_ENV_FLAGS_LIST_STATIC +#define CFG_ENV_FLAGS_LIST_STATIC "" #endif #ifdef CONFIG_NET @@ -87,7 +87,7 @@ enum env_flags_varaccess { NET_FLAGS \ NET6_FLAGS \ SERIAL_FLAGS \ - CONFIG_ENV_FLAGS_LIST_STATIC + CFG_ENV_FLAGS_LIST_STATIC #ifdef CONFIG_CMD_ENV_FLAGS /* -- cgit v1.3.1 From 7c5b8c7c643be917230c1b75da4267d76f484443 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:41 -0500 Subject: global: Migrate CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS to CFG Perform a simple rename of CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS to CFG_ENV_SETTINGS_BUTTONS_AND_LEDS Signed-off-by: Tom Rini --- include/configs/draco.h | 4 ++-- include/configs/etamin.h | 4 ++-- include/configs/pxm2.h | 4 ++-- include/configs/rastaban.h | 4 ++-- include/configs/thuban.h | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/configs/draco.h b/include/configs/draco.h index 4869008da44..d1c7abe1b39 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -19,7 +19,7 @@ #define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */ #define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ +#define CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "button_dfu0=27\0" \ "led0=103,1,0\0" \ "led1=64,0,1\0" @@ -34,7 +34,7 @@ "nand_img_size=0x400000\0" \ "optargs=\0" \ "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 811c7cb9618..8bfc9c9f629 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -56,7 +56,7 @@ #define BOARD_DFU_BUTTON_GPIO 27 #define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ /* In dfu mode keep led1 on */ -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ +#define CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "button_dfu0=27\0" \ "button_dfu1=87\0" \ "led0=3,0,1\0" \ @@ -134,7 +134,7 @@ "nand_img_size=0x400000\0" \ "optargs=\0" \ "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 586a7edcbb5..eafa6ae9a9a 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -18,7 +18,7 @@ #define DDR_IOCTRL_VAL 0x18b #define DDR_PLL_FREQ 266 -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ +#define CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "button_dfu0=59\0" \ "led0=117,0,1\0" \ @@ -34,7 +34,7 @@ "nand_img_size=0x500000\0" \ "optargs=\0" \ "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "splashpos=m,m\0" \ CONFIG_ENV_SETTINGS_V1 \ CONFIG_ENV_SETTINGS_NAND_V1 \ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 49cd11c17b4..2e002faf2e6 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -21,7 +21,7 @@ #define BOARD_DFU_BUTTON_GPIO 27 #define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ /* In dfu mode keep led1 on */ -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ +#define CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "button_dfu0=27\0" \ "button_dfu1=87\0" \ "led0=3,0,1\0" \ @@ -44,7 +44,7 @@ "nand_img_size=0x400000\0" \ "optargs=\0" \ "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 696306e4659..25c5a8ccd20 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -19,7 +19,7 @@ #define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */ #define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ +#define CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "button_dfu0=27\0" \ "led0=103,1,0\0" \ "led1=64,0,1\0" @@ -37,7 +37,7 @@ "nand_img_size=0x400000\0" \ "optargs=\0" \ "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 -- cgit v1.3.1 From fe5a5393bdf4cd2acad715b1ffa80f37c304b843 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:42 -0500 Subject: global: Migrate CONFIG_ENV_SETTINGS_NAND_V1 to CFG Perform a simple rename of CONFIG_ENV_SETTINGS_NAND_V1 to CFG_ENV_SETTINGS_NAND_V1 Signed-off-by: Tom Rini --- include/configs/pxm2.h | 2 +- include/configs/rut.h | 2 +- include/configs/siemens-am33x-common.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index eafa6ae9a9a..c6a01270a54 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -37,7 +37,7 @@ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "splashpos=m,m\0" \ CONFIG_ENV_SETTINGS_V1 \ - CONFIG_ENV_SETTINGS_NAND_V1 \ + CFG_ENV_SETTINGS_NAND_V1 \ "mmc_dev=0\0" \ "mmc_root=/dev/mmcblk0p2 rw\0" \ "mmc_root_fs_type=ext4 rootwait\0" \ diff --git a/include/configs/rut.h b/include/configs/rut.h index ac48372b6c0..f51771f9ca4 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -34,7 +34,7 @@ "splashpos=m,m\0" \ "optargs=fixrtc --no-log consoleblank=0 \0" \ CONFIG_ENV_SETTINGS_V1 \ - CONFIG_ENV_SETTINGS_NAND_V1 \ + CFG_ENV_SETTINGS_NAND_V1 \ "mmc_dev=0\0" \ "mmc_root=/dev/mmcblk0p2 rw\0" \ "mmc_root_fs_type=ext4 rootwait\0" \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 406a179842e..296ac34da63 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -196,7 +196,7 @@ "kernel_b part 0 8;" \ "rootfs partubi 0 10" -#define CONFIG_ENV_SETTINGS_NAND_V1 \ +#define CFG_ENV_SETTINGS_NAND_V1 \ "nand_active_ubi_vol=rootfs_a\0" \ "nand_active_ubi_vol_A=rootfs_a\0" \ "nand_active_ubi_vol_B=rootfs_b\0" \ -- cgit v1.3.1 From 4a609781d514456980654079407dad0a801ff485 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:43 -0500 Subject: global: Migrate CONFIG_ENV_SETTINGS_NAND_V2 to CFG Perform a simple rename of CONFIG_ENV_SETTINGS_NAND_V2 to CFG_ENV_SETTINGS_NAND_V2 Signed-off-by: Tom Rini --- include/configs/draco.h | 2 +- include/configs/etamin.h | 6 +++--- include/configs/rastaban.h | 2 +- include/configs/siemens-am33x-common.h | 2 +- include/configs/thuban.h | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/draco.h b/include/configs/draco.h index d1c7abe1b39..5b0daec11a6 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -36,6 +36,6 @@ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ - CONFIG_ENV_SETTINGS_NAND_V2 + CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_DRACO_H */ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 8bfc9c9f629..c68d0df02a2 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -93,8 +93,8 @@ "u-boot.env1 mtddev;" \ "rootfs mtddevubi" \ -#undef CONFIG_ENV_SETTINGS_NAND_V2 -#define CONFIG_ENV_SETTINGS_NAND_V2 \ +#undef CFG_ENV_SETTINGS_NAND_V2 +#define CFG_ENV_SETTINGS_NAND_V2 \ "nand_active_ubi_vol=rootfs_a\0" \ "rootfs_name=rootfs\0" \ "kernel_name=uImage\0"\ @@ -136,6 +136,6 @@ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ - CONFIG_ENV_SETTINGS_NAND_V2 + CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_ETAMIN_H */ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 2e002faf2e6..f3435b2b8c6 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -46,6 +46,6 @@ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ - CONFIG_ENV_SETTINGS_NAND_V2 + CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_RASTABAN_H */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 296ac34da63..7e9a55ec610 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -273,7 +273,7 @@ "u-boot.env1 part 0 7;" \ "rootfs partubi 0 9" \ -#define CONFIG_ENV_SETTINGS_NAND_V2 \ +#define CFG_ENV_SETTINGS_NAND_V2 \ "nand_active_ubi_vol=rootfs_a\0" \ "rootfs_name=rootfs\0" \ "kernel_name=uImage\0"\ diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 25c5a8ccd20..960b42dffd0 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -39,6 +39,6 @@ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ - CONFIG_ENV_SETTINGS_NAND_V2 + CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_THUBAN_H */ -- cgit v1.3.1 From 10bb746127f2bf8d7b4475dd7528b10712e07d8e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:44 -0500 Subject: global: Migrate CONFIG_ENV_SETTINGS_V1 to CFG Perform a simple rename of CONFIG_ENV_SETTINGS_V1 to CFG_ENV_SETTINGS_V1 Signed-off-by: Tom Rini --- include/configs/pxm2.h | 2 +- include/configs/rut.h | 2 +- include/configs/siemens-am33x-common.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index c6a01270a54..48f49906b84 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -36,7 +36,7 @@ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "splashpos=m,m\0" \ - CONFIG_ENV_SETTINGS_V1 \ + CFG_ENV_SETTINGS_V1 \ CFG_ENV_SETTINGS_NAND_V1 \ "mmc_dev=0\0" \ "mmc_root=/dev/mmcblk0p2 rw\0" \ diff --git a/include/configs/rut.h b/include/configs/rut.h index f51771f9ca4..b07d0c50604 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -33,7 +33,7 @@ "nand_img_size=0x500000\0" \ "splashpos=m,m\0" \ "optargs=fixrtc --no-log consoleblank=0 \0" \ - CONFIG_ENV_SETTINGS_V1 \ + CFG_ENV_SETTINGS_V1 \ CFG_ENV_SETTINGS_NAND_V1 \ "mmc_dev=0\0" \ "mmc_root=/dev/mmcblk0p2 rw\0" \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 7e9a55ec610..4f277f08a44 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -229,7 +229,7 @@ "${nand_img_size}; bootm ${kloadaddr}\0" \ COMMON_ENV_NAND_CMDS -#define CONFIG_ENV_SETTINGS_V1 \ +#define CFG_ENV_SETTINGS_V1 \ COMMON_ENV_SETTINGS \ "net_args=run bootargs_defaults;" \ "mtdparts default;" \ -- cgit v1.3.1 From d6ae6c7076b3f34b7e40b3570ccc7bdf8a0937f7 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:45 -0500 Subject: global: Migrate CONFIG_ENV_SETTINGS_V2 to CFG Perform a simple rename of CONFIG_ENV_SETTINGS_V2 to CFG_ENV_SETTINGS_V2 Signed-off-by: Tom Rini --- include/configs/draco.h | 2 +- include/configs/etamin.h | 2 +- include/configs/rastaban.h | 2 +- include/configs/siemens-am33x-common.h | 2 +- include/configs/thuban.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/draco.h b/include/configs/draco.h index 5b0daec11a6..ab3cf10d779 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -35,7 +35,7 @@ "optargs=\0" \ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - CONFIG_ENV_SETTINGS_V2 \ + CFG_ENV_SETTINGS_V2 \ CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_DRACO_H */ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index c68d0df02a2..57f619f55ff 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -135,7 +135,7 @@ "optargs=\0" \ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - CONFIG_ENV_SETTINGS_V2 \ + CFG_ENV_SETTINGS_V2 \ CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_ETAMIN_H */ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index f3435b2b8c6..59d56d66624 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -45,7 +45,7 @@ "optargs=\0" \ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - CONFIG_ENV_SETTINGS_V2 \ + CFG_ENV_SETTINGS_V2 \ CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_RASTABAN_H */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 4f277f08a44..7def657bcd1 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -306,7 +306,7 @@ "bootm ${kloadaddr} - ${loadaddr}\0" \ COMMON_ENV_NAND_CMDS -#define CONFIG_ENV_SETTINGS_V2 \ +#define CFG_ENV_SETTINGS_V2 \ COMMON_ENV_SETTINGS \ "net_args=run bootargs_defaults;" \ "mtdparts default;" \ diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 960b42dffd0..c8b27263e85 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -38,7 +38,7 @@ "optargs=\0" \ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - CONFIG_ENV_SETTINGS_V2 \ + CFG_ENV_SETTINGS_V2 \ CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_THUBAN_H */ -- cgit v1.3.1 From 3673a47b55c67359dc883bdf7be372d32ae6dbe6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:46 -0500 Subject: global: Migrate CONFIG_ENV_SROM_BANK to CFG Perform a simple rename of CONFIG_ENV_SROM_BANK to CFG_ENV_SROM_BANK Signed-off-by: Tom Rini --- board/samsung/smdkc100/smdkc100.c | 6 +++--- board/samsung/smdkv310/smdkv310.c | 6 +++--- include/configs/exynos5-common.h | 2 +- include/configs/smdkc100.h | 2 +- include/configs/smdkv310.h | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index b944e44c1ac..4f46911b0b4 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -25,16 +25,16 @@ static void smc9115_pre_init(void) u32 smc_bw_conf, smc_bc_conf; /* gpio configuration GPK0CON */ - gpio_cfg_pin(S5PC100_GPIO_K00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(S5PC100_GPIO_K00 + CFG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ - smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); + smc_bw_conf = SMC_DATA16_WIDTH(CFG_ENV_SROM_BANK); smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe) | SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4) | SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0); /* Select and configure the SROMC bank */ - s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); + s5p_config_sromc(CFG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); } int board_init(void) diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index bb61ba1f81c..47483a26a62 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -24,17 +24,17 @@ static void smc9115_pre_init(void) u32 smc_bw_conf, smc_bc_conf; /* gpio configuration GPK0CON */ - gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CFG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ - smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); + smc_bw_conf = SROMC_DATA16_WIDTH(CFG_ENV_SROM_BANK); smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F) | SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F) | SROMC_BC_TAH(0x0F) | SROMC_BC_TACP(0x0F) | SROMC_BC_PMC(0x0F); /* Select and configure the SROMC bank */ - s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); + s5p_config_sromc(CFG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); } int board_init(void) diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 8e277ce7ff2..43ea34db7b6 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -48,7 +48,7 @@ /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET -#define CONFIG_ENV_SROM_BANK 1 +#define CFG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ /* Enable Time Command */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index ffa1a1fcb0e..ccb7ec38d03 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -94,7 +94,7 @@ * Ethernet Contoller driver */ #ifdef CONFIG_CMD_NET -#define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ +#define CFG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ #endif /* CONFIG_CMD_NET */ #endif /* __CONFIG_H */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 38de1fa9849..f0604195ad9 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -36,7 +36,7 @@ /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET -#define CONFIG_ENV_SROM_BANK 1 +#define CFG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ #endif /* __CONFIG_H */ -- cgit v1.3.1 From ef2e1745da9151083c197d6077d0a14498eec13b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:47 -0500 Subject: global: Migrate CONFIG_ENV_TOTAL_SIZE to CFG Perform a simple rename of CONFIG_ENV_TOTAL_SIZE to CFG_ENV_TOTAL_SIZE Signed-off-by: Tom Rini --- board/keymile/kmcent2/kmcent2.env | 6 +++--- include/configs/kmcent2.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/board/keymile/kmcent2/kmcent2.env b/board/keymile/kmcent2/kmcent2.env index 7c8f8306c54..6b676a4ceb8 100644 --- a/board/keymile/kmcent2/kmcent2.env +++ b/board/keymile/kmcent2/kmcent2.env @@ -10,9 +10,9 @@ hostname=kmcent2 hwconfig=fsl_ddr:ctlr_intlv=cacheline netdev=eth2 -newenv=protect off ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE && - erase ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE && - protect on ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE +newenv=protect off ENV_DEL_ADDR +CFG_ENV_TOTAL_SIZE && + erase ENV_DEL_ADDR +CFG_ENV_TOTAL_SIZE && + protect on ENV_DEL_ADDR +CFG_ENV_TOTAL_SIZE set_fdthigh=true uimage=uImage diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 80bff4b8937..a4b6a6e555d 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -127,7 +127,7 @@ #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS /* Environment in parallel NOR-Flash */ -#define CONFIG_ENV_TOTAL_SIZE 0x040000 +#define CFG_ENV_TOTAL_SIZE 0x040000 #define ENV_DEL_ADDR 0xebf00000 /*direct for newenv*/ /* -- cgit v1.3.1 From b9abcb8c9fc196ef502eb8b2909bbb92a109deab Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:48 -0500 Subject: global: Migrate CONFIG_ET1100_BASE to CFG Perform a simple rename of CONFIG_ET1100_BASE to CFG_ET1100_BASE Signed-off-by: Tom Rini --- board/esd/meesc/meesc.c | 2 +- include/configs/meesc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 21f4ba98b53..9e362104224 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -163,7 +163,7 @@ int checkboard(void) u_char hw_type; /* hardware type */ /* read the "Type" register of the ET1100 controller */ - hw_type = readb(CONFIG_ET1100_BASE); + hw_type = readb(CFG_ET1100_BASE); switch (hw_type) { case 0x11: diff --git a/include/configs/meesc.h b/include/configs/meesc.h index d190e4b5039..38da55c70bf 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -60,6 +60,6 @@ #endif /* hw-controller addresses */ -#define CONFIG_ET1100_BASE 0x70000000 +#define CFG_ET1100_BASE 0x70000000 #endif -- cgit v1.3.1 From fb55ac2cfe017b5f83d97f25e3ed2ceaa9946405 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:49 -0500 Subject: global: Migrate CONFIG_ETHBASE to CFG Perform a simple rename of CONFIG_ETHBASE to CFG_ETHBASE Signed-off-by: Tom Rini --- board/cadence/xtfpga/xtfpga.c | 2 +- include/configs/xtfpga.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c index f38f5564a06..8e4081b4c6d 100644 --- a/board/cadence/xtfpga/xtfpga.c +++ b/board/cadence/xtfpga/xtfpga.c @@ -89,7 +89,7 @@ int misc_init_r(void) char *s = env_get("ethaddr"); if (s == 0) { unsigned int x; - char s[] = __stringify(CONFIG_ETHBASE); + char s[] = __stringify(CFG_ETHBASE); x = (*(volatile u32 *)CFG_SYS_FPGAREG_DIPSW) & FPGAREG_MAC_MASK; sprintf(&s[15], "%02x", x); diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index e0189c58f04..83a0539d8f2 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -120,7 +120,7 @@ /* Ethernet Driver Info */ /*======================*/ -#define CONFIG_ETHBASE 00:50:C2:13:6f:00 +#define CFG_ETHBASE 00:50:C2:13:6f:00 #define CFG_SYS_ETHOC_BASE IOADDR(0x0d030000) #define CFG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) -- cgit v1.3.1 From 0613c36a7a5973d58a50b764ee647099e80cc97d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:50 -0500 Subject: global: Migrate CONFIG_EXTRA_ENV_SETTINGS to CFG Perform a simple rename of CONFIG_EXTRA_ENV_SETTINGS to CFG_EXTRA_ENV_SETTINGS Signed-off-by: Tom Rini --- README | 4 ++-- doc/README.fsl-ddr | 4 ++-- doc/README.link-local | 2 +- doc/arch/x86.rst | 4 ++-- doc/develop/devicetree/control.rst | 2 +- doc/develop/distro.rst | 2 +- doc/usage/environment.rst | 2 +- env/Kconfig | 4 ++-- include/configs/M5208EVBE.h | 2 +- include/configs/M5235EVB.h | 2 +- include/configs/M5253DEMO.h | 2 +- include/configs/M5272C3.h | 2 +- include/configs/M5275EVB.h | 2 +- include/configs/M5282EVB.h | 2 +- include/configs/M53017EVB.h | 2 +- include/configs/M5329EVB.h | 2 +- include/configs/M5373EVB.h | 2 +- include/configs/MCR3000.h | 2 +- include/configs/MPC837XERDB.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/P1010RDB.h | 2 +- include/configs/P2041RDB.h | 2 +- include/configs/T102xRDB.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- include/configs/alt.h | 2 +- include/configs/am335x_evm.h | 2 +- include/configs/am335x_guardian.h | 2 +- include/configs/am335x_igep003x.h | 2 +- include/configs/am335x_shc.h | 2 +- include/configs/am335x_sl50.h | 2 +- include/configs/am3517_evm.h | 2 +- include/configs/am43xx_evm.h | 2 +- include/configs/am62ax_evm.h | 2 +- include/configs/am62x_evm.h | 2 +- include/configs/am64x_evm.h | 2 +- include/configs/am65x_evm.h | 2 +- include/configs/amcore.h | 2 +- include/configs/apalis-imx8.h | 2 +- include/configs/apalis_imx6.h | 2 +- include/configs/apple.h | 2 +- include/configs/arbel.h | 2 +- include/configs/aristainetos2.h | 2 +- include/configs/astro_mcf5373l.h | 2 +- include/configs/at91sam9263ek.h | 2 +- include/configs/at91sam9n12ek.h | 2 +- include/configs/ax25-ae350.h | 2 +- include/configs/axs10x.h | 2 +- include/configs/baltos.h | 2 +- include/configs/bcm_ns3.h | 2 +- include/configs/bcmstb.h | 2 +- include/configs/beacon-rzg2m.h | 4 ++-- include/configs/bitmain_antminer_s9.h | 2 +- include/configs/bk4r1.h | 2 +- include/configs/brppt1.h | 2 +- include/configs/brppt2.h | 2 +- include/configs/brsmarc1.h | 2 +- include/configs/brxre1.h | 2 +- include/configs/capricorn-common.h | 2 +- include/configs/cgtqmx8.h | 2 +- include/configs/chiliboard.h | 2 +- include/configs/cl-som-imx7.h | 4 ++-- include/configs/clearfog.h | 2 +- include/configs/cm_fx6.h | 2 +- include/configs/cm_t43.h | 2 +- include/configs/colibri-imx6ull.h | 2 +- include/configs/colibri-imx8x.h | 2 +- include/configs/colibri_imx6.h | 2 +- include/configs/colibri_imx7.h | 2 +- include/configs/colibri_vf.h | 2 +- include/configs/conga-qeval20-qa3-e3845.h | 4 ++-- include/configs/controlcenterdc.h | 2 +- include/configs/crs3xx-98dx3236.h | 2 +- include/configs/da850evm.h | 2 +- include/configs/dart_6ul.h | 2 +- include/configs/db-88f6820-amc.h | 2 +- include/configs/db-88f6820-gp.h | 2 +- include/configs/db-xc3-24g4xg.h | 2 +- include/configs/devkit3250.h | 2 +- include/configs/devkit8000.h | 2 +- include/configs/dfi-bt700.h | 4 ++-- include/configs/dh_imx6.h | 2 +- include/configs/display5.h | 2 +- include/configs/dns325.h | 2 +- include/configs/dockstar.h | 2 +- include/configs/draco.h | 2 +- include/configs/dragonboard410c.h | 2 +- include/configs/dragonboard820c.h | 2 +- include/configs/dragonboard845c.h | 2 +- include/configs/dreamplug.h | 2 +- include/configs/ds109.h | 2 +- include/configs/ds414.h | 2 +- include/configs/durian.h | 2 +- include/configs/el6x_common.h | 2 +- include/configs/embestmx6boards.h | 2 +- include/configs/emsdp.h | 2 +- include/configs/etamin.h | 2 +- include/configs/evb_ast2500.h | 2 +- include/configs/evb_ast2600.h | 2 +- include/configs/evb_rv1108.h | 4 ++-- include/configs/exynos5-common.h | 2 +- include/configs/exynos7420-common.h | 2 +- include/configs/exynos78x0-common.h | 2 +- include/configs/gazerbeam.h | 2 +- include/configs/ge_b1x5v2.h | 2 +- include/configs/ge_bx50v3.h | 2 +- include/configs/goflexhome.h | 2 +- include/configs/gose.h | 2 +- include/configs/guruplug.h | 2 +- include/configs/helios4.h | 2 +- include/configs/highbank.h | 2 +- include/configs/hikey.h | 2 +- include/configs/hikey960.h | 2 +- include/configs/hsdk-4xd.h | 2 +- include/configs/hsdk.h | 2 +- include/configs/ib62x0.h | 2 +- include/configs/iconnect.h | 2 +- include/configs/imx6-engicam.h | 2 +- include/configs/imx6_logic.h | 2 +- include/configs/imx6dl-mamoj.h | 2 +- include/configs/imx6q-bosch-acc.h | 2 +- include/configs/imx6ulz_smm_m2.h | 2 +- include/configs/imx7-cm.h | 4 ++-- include/configs/imx8mm-cl-iot-gate.h | 2 +- include/configs/imx8mm-mx8menlo.h | 4 ++-- include/configs/imx8mm_beacon.h | 2 +- include/configs/imx8mm_data_modul_edm_sbc.h | 2 +- include/configs/imx8mm_evk.h | 2 +- include/configs/imx8mm_icore_mx8mm.h | 2 +- include/configs/imx8mm_venice.h | 2 +- include/configs/imx8mn_beacon.h | 2 +- include/configs/imx8mn_bsh_smm_s2.h | 2 +- include/configs/imx8mn_bsh_smm_s2pro.h | 2 +- include/configs/imx8mn_evk.h | 2 +- include/configs/imx8mn_var_som.h | 2 +- include/configs/imx8mn_venice.h | 2 +- include/configs/imx8mp_dhcom_pdk2.h | 2 +- include/configs/imx8mp_evk.h | 2 +- include/configs/imx8mp_icore_mx8mp.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/imx8mp_venice.h | 2 +- include/configs/imx8mq_cm.h | 2 +- include/configs/imx8mq_evk.h | 2 +- include/configs/imx8mq_phanbell.h | 2 +- include/configs/imx8qm_mek.h | 2 +- include/configs/imx8qm_rom7720.h | 2 +- include/configs/imx8qxp_mek.h | 2 +- include/configs/imx8ulp_evk.h | 2 +- include/configs/imx93_evk.h | 2 +- include/configs/imxrt1050-evk.h | 2 +- include/configs/iot2050.h | 2 +- include/configs/j721e_evm.h | 2 +- include/configs/j721s2_evm.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/kontron-sl-mx6ul.h | 2 +- include/configs/kontron-sl-mx8mm.h | 2 +- include/configs/kontron_pitx_imx8m.h | 2 +- include/configs/kontron_sl28.h | 2 +- include/configs/kp_imx53.h | 2 +- include/configs/kp_imx6q_tpc.h | 2 +- include/configs/lacie_kw.h | 2 +- include/configs/lager.h | 2 +- include/configs/legoev3.h | 2 +- include/configs/librem5.h | 2 +- include/configs/liteboard.h | 2 +- include/configs/ls1012a2g5rdb.h | 4 ++-- include/configs/ls1012a_common.h | 2 +- include/configs/ls1012afrdm.h | 4 ++-- include/configs/ls1012afrwy.h | 4 ++-- include/configs/ls1012aqds.h | 4 ++-- include/configs/ls1012ardb.h | 4 ++-- include/configs/ls1021aiot.h | 2 +- include/configs/ls1021aqds.h | 4 ++-- include/configs/ls1021atsn.h | 2 +- include/configs/ls1021atwr.h | 4 ++-- include/configs/ls1028aqds.h | 4 ++-- include/configs/ls1028ardb.h | 4 ++-- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- include/configs/ls1088a_common.h | 2 +- include/configs/ls1088aqds.h | 20 ++++++++++---------- include/configs/ls1088ardb.h | 6 +++--- include/configs/ls2080a_common.h | 2 +- include/configs/ls2080aqds.h | 10 +++++----- include/configs/ls2080ardb.h | 6 +++--- include/configs/lsxl.h | 2 +- include/configs/lx2160aqds.h | 2 +- include/configs/lx2160ardb.h | 2 +- include/configs/lx2162aqds.h | 2 +- include/configs/m53menlo.h | 2 +- include/configs/mccmon6.h | 2 +- include/configs/meson64.h | 4 ++-- include/configs/meson64_android.h | 2 +- include/configs/microblaze-generic.h | 4 ++-- include/configs/microchip_mpfs_icicle.h | 2 +- include/configs/msc_sm2s_imx8mp.h | 2 +- include/configs/mt7623.h | 2 +- include/configs/mt8183.h | 2 +- include/configs/mt8512.h | 2 +- include/configs/mt8516.h | 2 +- include/configs/mt8518.h | 2 +- include/configs/mvebu_alleycat-5.h | 2 +- include/configs/mvebu_armada-37xx.h | 2 +- include/configs/mvebu_armada-8k.h | 2 +- include/configs/mx23_olinuxino.h | 2 +- include/configs/mx23evk.h | 2 +- include/configs/mx28evk.h | 2 +- include/configs/mx51evk.h | 2 +- include/configs/mx53cx9020.h | 2 +- include/configs/mx53loco.h | 2 +- include/configs/mx53ppd.h | 2 +- include/configs/mx6cuboxi.h | 2 +- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/mx6sllevk.h | 2 +- include/configs/mx6sxsabreauto.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/mx6ul_14x14_evk.h | 2 +- include/configs/mx6ullevk.h | 2 +- include/configs/mx7dsabresd.h | 2 +- include/configs/mx7ulp_com.h | 2 +- include/configs/mx7ulp_evk.h | 2 +- include/configs/mys_6ulx.h | 2 +- include/configs/nas220.h | 2 +- include/configs/nitrogen6x.h | 2 +- include/configs/nokia_rx51.h | 2 +- include/configs/novena.h | 2 +- include/configs/npi_imx6ull.h | 2 +- include/configs/nsa310s.h | 2 +- include/configs/o4-imx6ull-nano.h | 2 +- include/configs/octeontx2_common.h | 2 +- include/configs/octeontx_common.h | 4 ++-- include/configs/odroid.h | 2 +- include/configs/odroid_xu3.h | 4 ++-- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_igep00x0.h | 2 +- include/configs/omap3_logic.h | 2 +- include/configs/omapl138_lcdk.h | 2 +- include/configs/openpiton-riscv64.h | 2 +- include/configs/openrd.h | 2 +- include/configs/origen.h | 2 +- include/configs/p1_p2_rdb_pc.h | 2 +- include/configs/pcl063.h | 2 +- include/configs/pcl063_ull.h | 2 +- include/configs/pcm052.h | 2 +- include/configs/pcm058.h | 2 +- include/configs/pdu001.h | 2 +- include/configs/phycore_am335x_r2.h | 2 +- include/configs/phycore_imx8mm.h | 2 +- include/configs/phycore_imx8mp.h | 2 +- include/configs/pic32mzdask.h | 2 +- include/configs/pico-imx6.h | 2 +- include/configs/pico-imx6ul.h | 2 +- include/configs/pico-imx7d.h | 2 +- include/configs/pico-imx8mq.h | 2 +- include/configs/pm9261.h | 2 +- include/configs/pm9263.h | 2 +- include/configs/pogo_e02.h | 2 +- include/configs/pogo_v4.h | 2 +- include/configs/poleg.h | 2 +- include/configs/pomelo.h | 2 +- include/configs/poplar.h | 2 +- include/configs/porter.h | 2 +- include/configs/presidio_asic.h | 2 +- include/configs/px30_common.h | 2 +- include/configs/pxm2.h | 2 +- include/configs/qcs404-evb.h | 2 +- include/configs/qemu-arm.h | 2 +- include/configs/qemu-riscv.h | 2 +- include/configs/rastaban.h | 2 +- include/configs/rcar-gen3-common.h | 2 +- include/configs/rk3036_common.h | 2 +- include/configs/rk3066_common.h | 2 +- include/configs/rk3128_common.h | 2 +- include/configs/rk3188_common.h | 2 +- include/configs/rk322x_common.h | 2 +- include/configs/rk3288_common.h | 2 +- include/configs/rk3308_common.h | 2 +- include/configs/rk3328_common.h | 2 +- include/configs/rk3368_common.h | 2 +- include/configs/rk3399_common.h | 2 +- include/configs/rk3568_common.h | 2 +- include/configs/rpi.h | 2 +- include/configs/rut.h | 2 +- include/configs/rv1108_common.h | 2 +- include/configs/s5p4418_nanopi2.h | 2 +- include/configs/s5p_goni.h | 2 +- include/configs/s5pc210_universal.h | 2 +- include/configs/sdm845.h | 2 +- include/configs/sheevaplug.h | 2 +- include/configs/sifive-unleashed.h | 2 +- include/configs/sifive-unmatched.h | 2 +- include/configs/silk.h | 2 +- include/configs/sipeed-maix.h | 4 ++-- include/configs/slimbootloader.h | 6 +++--- include/configs/smartweb.h | 2 +- include/configs/smdkc100.h | 2 +- include/configs/smegw01.h | 2 +- include/configs/snapper9g45.h | 2 +- include/configs/sniper.h | 2 +- include/configs/socfpga_chameleonv3.h | 2 +- include/configs/socfpga_common.h | 4 ++-- include/configs/socfpga_dbm_soc1.h | 2 +- include/configs/socfpga_mcvevk.h | 2 +- include/configs/socfpga_n5x_socdk.h | 4 ++-- include/configs/socfpga_soc64_common.h | 2 +- include/configs/socfpga_vining_fpga.h | 2 +- include/configs/socrates.h | 2 +- include/configs/somlabs_visionsom_6ull.h | 2 +- include/configs/stemmy.h | 2 +- include/configs/stih410-b2260.h | 2 +- include/configs/stm32f429-discovery.h | 2 +- include/configs/stm32f429-evaluation.h | 2 +- include/configs/stm32f469-discovery.h | 2 +- include/configs/stm32f746-disco.h | 2 +- include/configs/stm32h743-disco.h | 2 +- include/configs/stm32h743-eval.h | 2 +- include/configs/stm32h750-art-pi.h | 2 +- include/configs/stm32mp13_common.h | 2 +- include/configs/stm32mp15_common.h | 2 +- include/configs/stm32mp15_dh_dhsom.h | 2 +- include/configs/stm32mp15_st_common.h | 6 +++--- include/configs/stmark2.h | 2 +- include/configs/stout.h | 2 +- include/configs/sunxi-common.h | 2 +- include/configs/synquacer.h | 2 +- include/configs/syzygy_hub.h | 2 +- include/configs/taurus.h | 2 +- include/configs/tbs2910.h | 2 +- include/configs/tegra-common-post.h | 2 +- include/configs/ten64.h | 4 ++-- include/configs/theadorable-x86-common.h | 4 ++-- include/configs/theadorable.h | 2 +- include/configs/thuban.h | 2 +- include/configs/thunderx_88xx.h | 2 +- include/configs/ti816x_evm.h | 2 +- include/configs/ti_armv7_keystone2.h | 2 +- include/configs/ti_omap4_common.h | 2 +- include/configs/ti_omap5_common.h | 2 +- include/configs/topic_miami.h | 4 ++-- include/configs/total_compute.h | 2 +- include/configs/tqma6.h | 2 +- include/configs/trats.h | 2 +- include/configs/trats2.h | 2 +- include/configs/turris_mox.h | 2 +- include/configs/turris_omnia.h | 2 +- include/configs/udoo.h | 2 +- include/configs/udoo_neo.h | 2 +- include/configs/uniphier.h | 2 +- include/configs/usb_a9263.h | 2 +- include/configs/usbarmory.h | 2 +- include/configs/vcoreiii.h | 2 +- include/configs/verdin-imx8mm.h | 2 +- include/configs/verdin-imx8mp.h | 2 +- include/configs/vexpress_aemv8.h | 2 +- include/configs/vexpress_common.h | 2 +- include/configs/vf610twr.h | 2 +- include/configs/vinco.h | 2 +- include/configs/wandboard.h | 2 +- include/configs/warp7.h | 2 +- include/configs/x530.h | 2 +- include/configs/x86-common.h | 2 +- include/configs/xea.h | 2 +- include/configs/xenguest_arm64.h | 6 +++--- include/configs/xilinx_versal.h | 4 ++-- include/configs/xilinx_versal_mini.h | 4 ++-- include/configs/xilinx_versal_net.h | 4 ++-- include/configs/xilinx_versal_net_mini.h | 4 ++-- include/configs/xilinx_zynqmp.h | 8 ++++---- include/configs/xilinx_zynqmp_mini.h | 4 ++-- include/configs/xilinx_zynqmp_r5.h | 2 +- include/configs/xpress.h | 2 +- include/configs/zynq-common.h | 4 ++-- include/configs/zynq_cse.h | 2 +- include/env_default.h | 4 ++-- 378 files changed, 441 insertions(+), 441 deletions(-) (limited to 'include') diff --git a/README b/README index e19aa1f722c..a278825bbcc 100644 --- a/README +++ b/README @@ -1124,7 +1124,7 @@ The following options need to be configured: symbols. - Default Environment: - CONFIG_EXTRA_ENV_SETTINGS + CFG_EXTRA_ENV_SETTINGS Define this to contain any number of null terminated strings (variable = value pairs) that will be part of @@ -1133,7 +1133,7 @@ The following options need to be configured: For example, place something like this in your board's config file: - #define CONFIG_EXTRA_ENV_SETTINGS \ + #define CFG_EXTRA_ENV_SETTINGS \ "myvar1=value1\0" \ "myvar2=value2\0" diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 10e63f3be1d..f44bb2aa25d 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -56,8 +56,8 @@ Table of 2-way interleaving modes supported in cpu/8xxx/ddr/ The ways to configure the ddr interleaving mode ============================================== 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting - under "CONFIG_EXTRA_ENV_SETTINGS", like: - #define CONFIG_EXTRA_ENV_SETTINGS \ + under "CFG_EXTRA_ENV_SETTINGS", like: + #define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=bank" \ ...... diff --git a/doc/README.link-local b/doc/README.link-local index 148b4987f27..ec2ef940e4c 100644 --- a/doc/README.link-local +++ b/doc/README.link-local @@ -51,7 +51,7 @@ by env variables. It depends on CONFIG_CMD_LINK_LOCAL, CONFIG_CMD_DHCP, and CONFIG_BOOTP_MAY_FAIL. If both fail or are disabled, static settings are used. -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "ipconfigcmd=if test \\\"$dhcpenabled\\\" -ne 0;" \ "then " \ "dhcpfail=0;dhcp || dhcpfail=1;" \ diff --git a/doc/arch/x86.rst b/doc/arch/x86.rst index 634387ac095..725a1ae5863 100644 --- a/doc/arch/x86.rst +++ b/doc/arch/x86.rst @@ -355,8 +355,8 @@ environment variables if you add this to minnowmax.h: "ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; " \ "run boot" - #undef CONFIG_EXTRA_ENV_SETTINGS - #define CONFIG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}" + #undef CFG_EXTRA_ENV_SETTINGS + #define CFG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}" and change CONFIG_BOOTARGS value in configs/minnowmax_defconfig to:: diff --git a/doc/develop/devicetree/control.rst b/doc/develop/devicetree/control.rst index c71570d64b4..0b3b32be1bb 100644 --- a/doc/develop/devicetree/control.rst +++ b/doc/develop/devicetree/control.rst @@ -135,7 +135,7 @@ control the boot process of Linux with bootm/bootz commands. To use this, put something like this in your board header file:: - #define CONFIG_EXTRA_ENV_SETTINGS "fdtcontroladdr=10000\0" + #define CFG_EXTRA_ENV_SETTINGS "fdtcontroladdr=10000\0" Build: diff --git a/doc/develop/distro.rst b/doc/develop/distro.rst index bc72aa951ef..8016acad098 100644 --- a/doc/develop/distro.rst +++ b/doc/develop/distro.rst @@ -214,7 +214,7 @@ Required Environment Variables The U-Boot "syslinux" and "pxe boot" commands require a number of environment variables be set. Default values for these variables are often hard-coded into -CONFIG_EXTRA_ENV_SETTINGS in the board's U-Boot configuration file, so that +CFG_EXTRA_ENV_SETTINGS in the board's U-Boot configuration file, so that the user doesn't have to configure them. fdt_addr: diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index 83f210d2d05..2c44e5da6aa 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -89,7 +89,7 @@ Old-style C environment Traditionally, the default environment is created in `include/env_default.h`, and can be augmented by various `CONFIG` defines. See that file for details. In -particular you can define `CONFIG_EXTRA_ENV_SETTINGS` in your board file +particular you can define `CFG_EXTRA_ENV_SETTINGS` in your board file to add environment variables. Board maintainers are encouraged to migrate to the text-based environment as it diff --git a/env/Kconfig b/env/Kconfig index 7ca992aa1d4..f73f0b8bc04 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -19,7 +19,7 @@ config ENV_SOURCE_FILE If this CONFIG is empty, U-Boot uses CONFIG SYS_BOARD as a default, if the file board///.env exists. Otherwise the environment is assumed to come from the ad-hoc - CONFIG_EXTRA_ENV_SETTINGS #define + CFG_EXTRA_ENV_SETTINGS #define config SAVEENV def_bool y if CMD_SAVEENV @@ -657,7 +657,7 @@ config USE_DEFAULT_ENV_FILE help Normally, the default environment is automatically generated based on the settings of various CONFIG_* options, as well - as the CONFIG_EXTRA_ENV_SETTINGS. By selecting this option, + as the CFG_EXTRA_ENV_SETTINGS. By selecting this option, you can instead define the entire default environment in an external file. diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index e14650fe0d4..f7aba6e417f 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -17,7 +17,7 @@ /* I2C */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=40010000\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 220524bfaed..049516edf4a 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -27,7 +27,7 @@ /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index bc156df20d5..a6349fc0861 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -20,7 +20,7 @@ env/embedded.o(.text*); #ifdef CONFIG_DRIVER_DM9000 -# define CONFIG_EXTRA_ENV_SETTINGS \ +# define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ "loadaddr=10000\0" \ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 6aae584afda..33c2fc08706 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -27,7 +27,7 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text); -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 41974cff410..607c5dee2fb 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -38,7 +38,7 @@ #define CFG_SYS_I2C_PINMUX_CLR (0xFFF0) #define CFG_SYS_I2C_PINMUX_SET (0x000F) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ "uboot=u-boot.bin\0" \ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 7cfe7a2da3e..31699a40b6f 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -27,7 +27,7 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text*); -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index ac2bd0b2241..b6d82c730c6 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -30,7 +30,7 @@ /* I2C */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=40010000\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index a86a117fd8f..d74a636fd7f 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -22,7 +22,7 @@ /* I2C */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=40010000\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index b2ad03cc3cb..fa6f2d23e74 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -24,7 +24,7 @@ /* I2C */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index f8368823aac..c6929c1b987 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -9,7 +9,7 @@ /* High Level Configuration Options */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "sdram_type=SDRAM\0" \ "flash_type=AM29LV160DB\0" \ "loadaddr=0x400000\0" \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index e0ac9338d32..fad161597e6 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -195,7 +195,7 @@ #define FDTFILE "mpc8379_rdb.dtb" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth1\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \ "tftpflash=tftp $loadaddr $uboot;" \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 1e3ba6de6e7..6f3e298a249 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -291,7 +291,7 @@ * Environment Configuration */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ecc=off\0" \ "netdev=eth0\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index afb602c5bce..b57e8638ab7 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -371,7 +371,7 @@ extern unsigned long get_sdram_size(void); * Environment Configuration */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ "netdev=eth0\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 1a157a7da05..6e755fc0a8f 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -304,7 +304,7 @@ #define __USB_PHY_TYPE utmi -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ "bank_intlv=cs0_cs1\0" \ "netdev=eth0\0" \ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 4794c5a84d1..063b864f9ff 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -430,7 +430,7 @@ "fdtfile=t1023rdb/t1023rdb.dtb\0" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ARCH_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index cfde8ecf9c6..9d04d30a538 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -370,7 +370,7 @@ #define FDTFILE "t1042rdb/t1042d4rdb.dtb" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 4b6bdaa3440..7f332cf2e3b 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -413,7 +413,7 @@ #define __USB_PHY_TYPE utmi -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:" \ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ "bank_intlv=auto;" \ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index fab40f792af..d6dd9c07b73 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -379,7 +379,7 @@ #define __USB_PHY_TYPE utmi -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:" \ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ "bank_intlv=auto;" \ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 41565f284c6..22cbf92efb8 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -368,7 +368,7 @@ #define CTRL_INTLV_PREFERED cacheline #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:" \ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ "bank_intlv=auto;" \ diff --git a/include/configs/alt.h b/include/configs/alt.h index f2774001692..29f4d06b7f8 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -30,7 +30,7 @@ /* Board Clock */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "usb_pgood_delay=2000\0" diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 755f7fae3e4..1f473b5a150 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -78,7 +78,7 @@ #ifndef CONFIG_SPL_BUILD #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "fdtfile=undefined\0" \ "finduuid=part uuid mmc 0:2 uuid\0" \ diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index a5b83b0c25d..a8fa61c7e50 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -45,7 +45,7 @@ "main_pcba_aux_3=0\0" \ "main_pcba_aux_4=0\0" \ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ AM335XX_BOARD_FDTFILE \ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV \ diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h index abd868c1453..e2beaf27185 100644 --- a/include/configs/am335x_igep003x.h +++ b/include/configs/am335x_igep003x.h @@ -20,7 +20,7 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "bootdir=/boot\0" \ "bootfile=zImage\0" \ diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 70645edcb14..ee6f62275a8 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -21,7 +21,7 @@ #define V_SCLK (V_OSCK) #ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "kloadaddr=0x84000000\0" \ "fdtaddr=0x85000000\0" \ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index 342a068c855..f3d3d18c055 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -30,7 +30,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ AM335XX_BOARD_FDTFILE \ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index c57a0ddc21d..b75c6483883 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -38,7 +38,7 @@ #endif /* CONFIG_MTD_RAW_NAND */ /* Environment information */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyS2,115200n8\0" \ "fdtfile=am3517-evm.dtb\0" \ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 7659c1cc061..3a6ffd9de0b 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -66,7 +66,7 @@ #ifndef CONFIG_SPL_BUILD #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "fdtfile=undefined\0" \ "finduuid=part uuid mmc 0:2 uuid\0" \ diff --git a/include/configs/am62ax_evm.h b/include/configs/am62ax_evm.h index 5406c39350f..1bd900df7a9 100644 --- a/include/configs/am62ax_evm.h +++ b/include/configs/am62ax_evm.h @@ -56,7 +56,7 @@ "partitions=" PARTS_DEFAULT /* Incorporate settings into the U-Boot environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ EXTRA_ENV_AM62A7_BOARD_SETTINGS \ diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h index 57f3f37908d..809d89119c4 100644 --- a/include/configs/am62x_evm.h +++ b/include/configs/am62x_evm.h @@ -55,7 +55,7 @@ "partitions=" PARTS_DEFAULT /* Incorporate settings into the U-Boot environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ EXTRA_ENV_AM625_BOARD_SETTINGS \ diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 25c71f00a20..26a7f2521ec 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -95,7 +95,7 @@ DFU_ALT_INFO_OSPI /* Incorporate settings into the U-Boot environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ EXTRA_ENV_AM642_BOARD_SETTINGS \ diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 0307426e4ab..33dd6cfdfa4 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -88,7 +88,7 @@ #endif /* Incorporate settings into the U-Boot environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ diff --git a/include/configs/amcore.h b/include/configs/amcore.h index ca29346fe64..648d30a5b24 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -10,7 +10,7 @@ #define CFG_SYS_UART_PORT 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "upgrade_uboot=loady; " \ "protect off 0xffc00000 0xffc1ffff; " \ "erase 0xffc00000 0xffc1ffff; " \ diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index aa3dcf4a881..73d8d245a96 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -31,7 +31,7 @@ #define BOOTENV_RUN_NET_USB_START "" /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ "boot_file=Image\0" \ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 07587c7609b..d46159076f2 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -62,7 +62,7 @@ "ramdisk_addr_r=0x18400000\0" \ "scriptaddr=0x18280000\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "boot_file=zImage\0" \ "boot_script_dhcp=boot.scr\0" \ diff --git a/include/configs/apple.h b/include/configs/apple.h index b06660add4f..fe7d11bcdb3 100644 --- a/include/configs/apple.h +++ b/include/configs/apple.h @@ -27,7 +27,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_DEVICE_SETTINGS \ BOOTENV diff --git a/include/configs/arbel.h b/include/configs/arbel.h index 60758b0ca02..8e27fb52a1c 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -12,7 +12,7 @@ #define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Default environemnt variables */ -#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ +#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" \ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index ff213a41b8f..a6e9d2bb65f 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -94,7 +94,7 @@ "done\0" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "disable_giga=yes\0" \ "usb_pgood_delay=2000\0" \ "nor_bootdelay=-2\0" \ diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 6aef3bd86f7..65224324fbc 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -71,7 +71,7 @@ * u-boot: 'set' command */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loaderversion=11\0" \ "card_id="__stringify(ASTRO_ID)"\0" \ "alterafile=0\0" \ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index afdb74785f8..4101440ff5d 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -36,7 +36,7 @@ /* Address and size of Primary Environment Sector */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ "update=" \ "protect off ${monitor_base} +${filesize};" \ diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 0f9e2cfb582..c59d4bb38ca 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -28,7 +28,7 @@ #define CFG_SYS_NAND_READY_PIN GPIO_PIN_PD(5) #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\ "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0" diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index d70f0382300..b566ecf296f 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -82,7 +82,7 @@ func(RAM, ram, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x00080000\0" \ "pxefile_addr_r=0x01f00000\0" \ "scriptaddr=0x01f00000\0" \ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 04dc50b1cb2..a82dfc90294 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -39,7 +39,7 @@ /* * Environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "upgrade=if mmc rescan && " \ "fatload mmc 0:1 ${loadaddr} u-boot-update.img && " \ "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 6f6552e6dc3..e7946389eff 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -49,7 +49,7 @@ #define NANDARGS "" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "boot_fdt=try\0" \ "bootpart=0:2\0" \ diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index fc176dc2014..47de4bc2013 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -793,7 +793,7 @@ QSPI_FLASH \ FLASH_IMAGES -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ARCH_ENV_SETTINGS #endif /* __BCM_NS3_H */ diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 57360b60ca9..d1de3561af6 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -131,7 +131,7 @@ extern phys_addr_t prior_stage_fdt_address; /* * Enable in-place RFS with this initrd_high setting. */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdtsaveaddr=" __stringify(CONFIG_SYS_FDT_SAVE_ADDRESS) "\0" \ "initrd_high=0xffffffff\0" \ "fdt_high=0xffffffff\0" diff --git a/include/configs/beacon-rzg2m.h b/include/configs/beacon-rzg2m.h index 2713b158438..65c01835cc6 100644 --- a/include/configs/beacon-rzg2m.h +++ b/include/configs/beacon-rzg2m.h @@ -8,9 +8,9 @@ #include "rcar-gen3-common.h" -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "usb_pgood_delay=2000\0" \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h index 556bfa08ebb..3662668c6a6 100644 --- a/include/configs/bitmain_antminer_s9.h +++ b/include/configs/bitmain_antminer_s9.h @@ -9,7 +9,7 @@ #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 0x40000000 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "pxefile_addr_r=0x2000000\0" \ "scriptaddr=0x3000000\0" \ "kernel_addr_r=0x2000000\0" \ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index 0842a4a8f54..5df8d03c706 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -57,7 +57,7 @@ /* boot command, including the target-defined one if any */ /* Extra env settings (including the target-defined ones if any) */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BK4_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index 2c5236aa58b..236d720a55a 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -67,7 +67,7 @@ MMC_TGTS \ #define LOAD_OFFSET(x) 0x8##x -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ "verify=no\0" \ "scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \ diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 984602c2cf7..32d9f503d9f 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -24,7 +24,7 @@ /* Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ "cfgaddr=0x106F0000\0" \ "scraddr=0x10700000\0" \ diff --git a/include/configs/brsmarc1.h b/include/configs/brsmarc1.h index f9908352b0d..ffb4cd3027a 100644 --- a/include/configs/brsmarc1.h +++ b/include/configs/brsmarc1.h @@ -24,7 +24,7 @@ #define V_SCLK (V_OSCK) /* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ "scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "cfgscr=mw ${dtbaddr} 0;" \ diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index 410b3e641c5..9ca6d6f863d 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -20,7 +20,7 @@ #define V_SCLK (V_OSCK) /* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ "scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootaddr=0x80001100\0" \ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 474ad69d996..a8273a7fcd8 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -67,7 +67,7 @@ "emmc_dev=0\0" /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ CONFIG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ AHAB_ENV \ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 6f3396bad4c..263981860e8 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -55,7 +55,7 @@ "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ CONFIG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ "script=boot.scr\0" \ diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index 1e5154af0a1..850eb892db7 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -25,7 +25,7 @@ "nand read ${loadaddr} NAND.kernel; " \ "bootz ${loadaddr} - ${fdt_addr}\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "fdt_addr=0x87800000\0" \ "boot_fdt=try\0" \ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 5c9004cbd93..2d56d37f06f 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -24,9 +24,9 @@ #define CFG_SYS_I2C_PCA953X_ADDR 0x20 #define CFG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \ "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \ diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index 9c9e9506dc6..062d3d87026 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -110,7 +110,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ RELOCATION_LIMITS_ENV_SETTINGS \ LOAD_ADDRESS_ENV_SETTINGS \ "console=ttyS0,115200\0" \ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 9df8baa8a96..c66cf721870 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -30,7 +30,7 @@ /* Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_addr_r=0x18000000\0" \ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 8a18d6f97ab..aa17c9cbe2c 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -41,7 +41,7 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "fdtaddr=0x81200000\0" \ "bootm_size=0x8000000\0" \ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 6f3524deb56..5b802aa92a9 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -79,7 +79,7 @@ #endif #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ UBI_BOOTCMD \ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 215c633a4c9..13bc4e7e682 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -56,7 +56,7 @@ "${fdt_addr};\0" \ /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ AHAB_ENV \ BOOTENV \ CONFIG_MFG_ENV_SETTINGS \ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 4e51df123a6..bf2a9bbaaff 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -56,7 +56,7 @@ "ramdisk_addr_r=0x18400000\0" \ "scriptaddr=0x18280000\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "boot_file=zImage\0" \ "boot_script_dhcp=boot.scr\0" \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 89546b857fe..91f87ea283f 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -119,7 +119,7 @@ #endif #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ MODULE_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index e8918df69e0..60f31389fd4 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -47,7 +47,7 @@ #define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ UBI_BOOTCMD \ diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h index e9b85b4e1c7..6f431725269 100644 --- a/include/configs/conga-qeval20-qa3-e3845.h +++ b/include/configs/conga-qeval20-qa3-e3845.h @@ -18,8 +18,8 @@ #define VIDEO_IO_OFFSET 0 -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "kernel-ver=4.4.0-22\0" \ "boot=zboot 03000000 0 04000000 ${filesize}\0" \ "upd_uboot=tftp 100000 conga/u-boot.rom;" \ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 119a834fe74..0e922b96644 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -21,7 +21,7 @@ * Environment Configuration */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth1\0" \ "consoledev=ttyS1\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/crs3xx-98dx3236.h b/include/configs/crs3xx-98dx3236.h index 25bcc2a6841..6535730731a 100644 --- a/include/configs/crs3xx-98dx3236.h +++ b/include/configs/crs3xx-98dx3236.h @@ -13,7 +13,7 @@ /* Environment in SPI NOR flash */ /* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index a818a4b39f8..cfc8330e35a 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -145,7 +145,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ "bootpart=0:2\0" \ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index 4b31bbf4e11..323703ac5c9 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -68,7 +68,7 @@ "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \ /* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "console=ttymxc0,115200n8\0" \ "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index b9d03d253d9..c4ae397e3e6 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -17,7 +17,7 @@ /* NAND */ /* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index bba2b607aa8..6dbf582d733 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -18,7 +18,7 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ /* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h index 84ea1baa997..0ee914e91d0 100644 --- a/include/configs/db-xc3-24g4xg.h +++ b/include/configs/db-xc3-24g4xg.h @@ -11,7 +11,7 @@ /* NAND */ /* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 66aa6d5c3c4..ab10101f20a 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -67,7 +67,7 @@ * Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "ethaddr=00:01:90:00:C0:81\0" \ "dtbaddr=0x81000000\0" \ "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index e3621fd6f9c..c522d334dcc 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -22,7 +22,7 @@ DEFAULT_LINUX_BOOT_ENV /* Environment information */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "console=ttyO2,115200n8\0" \ "mmcdev=0\0" \ diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index 154c4f4f13f..d10422b6c1c 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -22,8 +22,8 @@ #define VIDEO_IO_OFFSET 0 -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "kernel-ver=4.4.0-24\0" \ "boot=zboot 03000000 0 04000000 ${filesize}\0" \ "upd_uboot=usb reset;tftp 100000 dfi/u-boot.rom;" \ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 3aed6299ed5..6aef15c658c 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -41,7 +41,7 @@ #endif #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_addr=0x18000000\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/display5.h b/include/configs/display5.h index 4401515a65e..70ad88c9075 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -164,7 +164,7 @@ "sf write ${loadaddr} 0x0 ${filesize};" \ "fi\0" \ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ PARTS_DEFAULT \ "gpio_recovery=93\0" \ "check_em_pad=gpio input ${gpio_recovery};test $? -eq 0;\0" \ diff --git a/include/configs/dns325.h b/include/configs/dns325.h index 1bfb741346a..4842eccf40d 100644 --- a/include/configs/dns325.h +++ b/include/configs/dns325.h @@ -28,7 +28,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" \ diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index a6c1e9c6d02..999389197c6 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -22,7 +22,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "kernel=/boot/uImage\0" \ "initrd=/boot/uInitrd\0" \ diff --git a/include/configs/draco.h b/include/configs/draco.h index ab3cf10d779..b56ba9132af 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -28,7 +28,7 @@ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hostname=draco\0" \ "ubi_off=2048\0"\ "nand_img_size=0x400000\0" \ diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index daf7ecd7975..73aec348458 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -28,6 +28,6 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV +#define CFG_EXTRA_ENV_SETTINGS BOOTENV #endif diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h index 31cd8536de4..49970837111 100644 --- a/include/configs/dragonboard820c.h +++ b/include/configs/dragonboard820c.h @@ -26,7 +26,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x95000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h index bd88c42a3ba..c1e590fae2a 100644 --- a/include/configs/dragonboard845c.h +++ b/include/configs/dragonboard845c.h @@ -13,7 +13,7 @@ #define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x5000000\0" \ "bootm_low=0x80000000\0" \ "bootcmd=bootm $prevbl_initrd_start_addr\0" diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 98322a54f63..85b47a15d71 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -17,7 +17,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "x_bootcmd_ethernet=ping 192.168.2.1\0" \ "x_bootcmd_usb=usb start\0" \ "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \ diff --git a/include/configs/ds109.h b/include/configs/ds109.h index 8e7a86e0626..ea77abb4746 100644 --- a/include/configs/ds109.h +++ b/include/configs/ds109.h @@ -26,7 +26,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "x_bootcmd_ethernet=ping 192.168.1.2\0" \ "x_bootcmd_usb=usb start\0" \ "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index 76d1713fdc6..e69883ba73b 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -43,7 +43,7 @@ /* Default Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "initrd_high=0xffffffff\0" \ "ramdisk_addr_r=0x8000000\0" \ "usb0Mode=host\0usb1Mode=host\0usb2Mode=device\0" \ diff --git a/include/configs/durian.h b/include/configs/durian.h index 001596c00a4..9f11e18d34a 100644 --- a/include/configs/durian.h +++ b/include/configs/durian.h @@ -15,7 +15,7 @@ /* BOOT */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "load_kernel=ext4load scsi 0:1 0x90100000 uImage-2004\0" \ "load_fdt=ext4load scsi 0:1 0x95000000 ft2004-pci-64.dtb\0"\ "boot_fdt=bootm 0x90100000 -:- 0x95000000\0" \ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index 89e071c0df6..a5e2dc063a7 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -23,7 +23,7 @@ #define CONFIG_MXC_UART_BASE UART2_BASE -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "board=EL6Q\0" \ "cma_size="__stringify(EL6Q_CMA_SIZE)"\0" \ "chp_size="__stringify(EL6Q_COHERENT_POOL_SIZE)"\0" \ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 1742b1192fb..c1748fc2602 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -76,7 +76,7 @@ CONSOLE_STDIN_SETTINGS \ CONSOLE_STDOUT_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ CONSOLE_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "fdtfile=" FDTFILE "\0" \ diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h index c2b921e7cb8..83aaa09cdbb 100644 --- a/include/configs/emsdp.h +++ b/include/configs/emsdp.h @@ -15,7 +15,7 @@ * Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "upgrade_image=u-boot.bin\0" \ "upgrade=emsdp rom unlock && " \ "fatload mmc 0 ${loadaddr} ${upgrade_image} && " \ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 57f619f55ff..8d8e717b38d 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -128,7 +128,7 @@ COMMON_ENV_NAND_CMDS /* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hostname=etamin\0" \ "ubi_off=4096\0"\ "nand_img_size=0x400000\0" \ diff --git a/include/configs/evb_ast2500.h b/include/configs/evb_ast2500.h index bec1660cf48..f304929263e 100644 --- a/include/configs/evb_ast2500.h +++ b/include/configs/evb_ast2500.h @@ -14,7 +14,7 @@ #define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* Misc */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "" #endif /* __CONFIG_H */ diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h index c9c988b9374..e1cce58fa93 100644 --- a/include/configs/evb_ast2600.h +++ b/include/configs/evb_ast2600.h @@ -14,7 +14,7 @@ #define STR_HELPER(s) #s #define STR(s) STR_HELPER(s) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=" STR(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootspi=fdt addr 20100000 && fdt header get fitsize totalsize && " \ "cp.b 20100000 ${loadaddr} ${fitsize} && bootm; " \ diff --git a/include/configs/evb_rv1108.h b/include/configs/evb_rv1108.h index 13e3cb2ffeb..e7d866551a5 100644 --- a/include/configs/evb_rv1108.h +++ b/include/configs/evb_rv1108.h @@ -11,8 +11,8 @@ /* * Default environment settings */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "ipaddr=172.16.12.50\0" \ "serverip=172.16.12.69\0" \ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 43ea34db7b6..ec09f6cc5de 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -91,7 +91,7 @@ #define EXYNOS_FDTFILE_SETTING #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS \ EXYNOS_FDTFILE_SETTING \ MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index e22dd036ccb..9971385848a 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -63,7 +63,7 @@ #define EXYNOS_FDTFILE_SETTING #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS \ EXYNOS_FDTFILE_SETTING \ MEM_LAYOUT_ENV_SETTINGS diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h index 8672b9e9527..92c84cd8ce0 100644 --- a/include/configs/exynos78x0-common.h +++ b/include/configs/exynos78x0-common.h @@ -74,7 +74,7 @@ EXYNOS_FDTFILE_SETTING \ MEM_LAYOUT_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS #endif /* __CONFIG_EXYNOS78x0_COMMON_H */ diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 671b75e6986..855aaa1aa57 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -55,7 +55,7 @@ * Environment Configuration */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 1aaa3e67d60..0523ff9a64b 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -35,7 +35,7 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Command definition */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=/boot/fitImage\0" \ "fdt_addr_r=0x18000000\0" \ "splash_addr_r=0x20000000\0" \ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index f62b8f175e1..32960fb9325 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -41,7 +41,7 @@ #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ NETWORKBOOT \ "image=/boot/fitImage\0" \ "dev=mmc\0" \ diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 1c86dcb1f6d..b7de159c865 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -31,7 +31,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "kernel=/boot/uImage\0" \ "bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0" diff --git a/include/configs/gose.h b/include/configs/gose.h index d1fe375a2c1..45f0ec6f6a0 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -29,7 +29,7 @@ /* Board Clock */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" #endif /* __GOSE_H */ diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index d196c4eda53..44b4595440e 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -23,7 +23,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "mtdids=nand0=orion_nand\0" \ "kernel=/boot/zImage\0" \ diff --git a/include/configs/helios4.h b/include/configs/helios4.h index fc32487e1c7..7d81d1cf1e4 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -110,7 +110,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ RELOCATION_LIMITS_ENV_SETTINGS \ LOAD_ADDRESS_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 4aef0b4abd1..76e6054b0cc 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -16,7 +16,7 @@ #define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x20000000\0" \ "initrd_high=0x20000000\0" diff --git a/include/configs/hikey.h b/include/configs/hikey.h index d4280decc9f..36bf22b1870 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -42,7 +42,7 @@ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_name=Image\0" \ "kernel_addr_r=0x00080000\0" \ "fdtfile=hi6220-hikey.dtb\0" \ diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index fad1f980481..40d5e653c3f 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -28,7 +28,7 @@ func(MMC, mmc, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ "fdtfile=hi3660-hikey960.dtb\0" \ "fdt_addr_r=0x10000000\0" \ diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index 59ea8960071..f59da417731 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -37,7 +37,7 @@ /* * Environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "upgrade=if mmc rescan && " \ "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \ "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index fbfcded4712..2177fafcdc0 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -36,7 +36,7 @@ /* * Environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "upgrade=if mmc rescan && " \ "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \ "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index 76fc4ac8b66..e1b62f78b21 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -18,7 +18,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "kernel=/boot/zImage\0" \ "fdt=/boot/ib62x0.dtb\0" \ diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index 6d2104b3a1c..d372ffb802c 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -11,7 +11,7 @@ #include "mv-common.h" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "kernel=/boot/uImage\0" \ "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index 36b6b95b84d..4208ba95915 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -24,7 +24,7 @@ #endif /* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "splashpos=m,m\0" \ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 4e23f1a2dc5..0df61916b7d 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -21,7 +21,7 @@ /* Ethernet Configs */ #define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "bootm_size=0x10000000\0" \ diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index 402f83c18ea..b6006c021d5 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -20,7 +20,7 @@ /* Environment in MMC */ #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x14000000\0" \ "fdt_addr_r=0x13000000\0" \ "kernel_addr_r=0x10008000\0" \ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 392f97050a6..e28185f24dd 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -72,7 +72,7 @@ #endif /* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootconf=conf-imx6q-bosch-acc.dtb\0"\ "mmcfit_name=fitImage\0" \ "mmcloadfit=ext4load mmc ${mmcdev}:${fitpart} ${fit_addr} ${mmcfit_name}\0" \ diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index 2d9d3c34b0d..c95038eaa53 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -54,7 +54,7 @@ #devtypel #instance " " /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ NANDARGS \ BOOTENV diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 8e9dbefc496..66cf5b463fc 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -12,7 +12,7 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS /* * Use: @@ -22,7 +22,7 @@ */ #define MY_CONFIG_BOOT_MODE "boot-mode=sd\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MY_CONFIG_BOOT_MODE \ "image=zImage\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index c228cf7f37b..00ce7fb62a9 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -63,7 +63,7 @@ BOOT_TARGET_DHCP(func) /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/imx8mm-mx8menlo.h b/include/configs/imx8mm-mx8menlo.h index 938c5406b82..a86bd76a3c7 100644 --- a/include/configs/imx8mm-mx8menlo.h +++ b/include/configs/imx8mm-mx8menlo.h @@ -9,8 +9,8 @@ #include /* Custom initial environment variables */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ "devtype=mmc\0" \ diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 03325e6c3a7..ee524f0e63f 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -20,7 +20,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=Image\0" \ "console=ttymxc1,115200\0" \ diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 80321cf2d8d..44d74bb1a78 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -34,7 +34,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ "bootlimit=3\0" \ "devtype=mmc\0" \ diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 8a694c88a53..d28f3f1972b 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -37,7 +37,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index 41ab9307793..e718daa07c3 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -30,7 +30,7 @@ "ramdisk_addr_r=0x46400000\0" \ "scriptaddr=0x46000000\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "console=ttymxc1,115200\0" \ diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 28ce834769c..c490e3829f9 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -25,7 +25,7 @@ func(USB, usb, 1) \ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "splblk=0x42\0" \ BOOTENV diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 85fd5e2371f..bb3dfe3fa0d 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -13,7 +13,7 @@ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=Image\0" \ "ramdiskimage=rootfs.cpio.uboot\0" \ diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h index a768ff35510..e97b8e871d2 100644 --- a/include/configs/imx8mn_bsh_smm_s2.h +++ b/include/configs/imx8mn_bsh_smm_s2.h @@ -35,7 +35,7 @@ #devtypel #instance " " /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ NANDARGS \ BOOTENV diff --git a/include/configs/imx8mn_bsh_smm_s2pro.h b/include/configs/imx8mn_bsh_smm_s2pro.h index 035e5c7bd90..8619fdde7fd 100644 --- a/include/configs/imx8mn_bsh_smm_s2pro.h +++ b/include/configs/imx8mn_bsh_smm_s2pro.h @@ -22,7 +22,7 @@ "emmc_ack=1\0" \ /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ EMMCARGS \ BOOTENV diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 024b86c7f1d..b759b834b80 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -32,7 +32,7 @@ "scriptaddr=0x40000000\0" \ "pxefile_addr_r=0x40100000\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ BOOTENV \ "console=ttymxc1,115200\0" \ diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index 4633843d1bb..205337948cf 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -37,7 +37,7 @@ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index a585cbf87e4..80c2df9f30f 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -19,7 +19,7 @@ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "splblk=0x40\0" \ BOOTENV diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index 5443022b04c..b8fdedefa21 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -28,7 +28,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "altbootcmd=run bootcmd ; reset\0" \ "bootlimit=3\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 137bd3b0952..c6e3b105a8a 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -26,7 +26,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index b261a81e44a..c3abcee40e8 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -29,7 +29,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 58f7dc6518c..ed4da0e69b5 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -71,7 +71,7 @@ BOOT_TARGET_DHCP(func) /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index e79aa570753..4b32d5a77ef 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -19,7 +19,7 @@ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "splblk=0x40\0" \ BOOTENV diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 4df98e3f373..f6f356d27ba 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -30,7 +30,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=0x43500000\0" \ "kernel_addr_r=0x40880000\0" \ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 688c0bf7008..c40448715f8 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -35,7 +35,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 3b4cd656223..8fed3e31964 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -29,7 +29,7 @@ "initrd_high=0xffffffff\0" \ /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ CONFIG_MFG_ENV_SETTINGS \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index f1f907f3e5a..7772e71013e 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -23,7 +23,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ AHAB_ENV \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 2e2e5ed43cd..5692e3d0000 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -47,7 +47,7 @@ "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ CONFIG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ "script=boot.scr\0" \ diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index d75b8bf0c18..669da591fa2 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -23,7 +23,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ AHAB_ENV \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index d313bdc2a44..30dd5af03b0 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -34,7 +34,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 895c50f6025..5cd6492dd50 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -28,7 +28,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=0x83500000\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index 84228676c7f..7688464841e 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -19,7 +19,7 @@ DMAMEM_SZ_ALL) #ifdef CONFIG_VIDEO -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "stdin=serial\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h index 0f6150fc9c7..7d087413362 100644 --- a/include/configs/iot2050.h +++ b/include/configs/iot2050.h @@ -40,7 +40,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ BOOTENV \ EXTRA_ENV_IOT2050_BOARD_SETTINGS diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index e66f994a375..a7210b5cf3a 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -170,7 +170,7 @@ #include /* Incorporate settings into the U-Boot environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index ab204c62b7d..54dfea6952e 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -127,7 +127,7 @@ DFU_ALT_INFO_OSPI /* Incorporate settings into the U-Boot environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 736865ad80a..61ff80d2c98 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -29,7 +29,7 @@ /* Board Clock */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" /* SPL support */ diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index 7c5f673c0f4..e3ae91089ff 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -45,6 +45,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV +#define CFG_EXTRA_ENV_SETTINGS BOOTENV #endif /* __KONTRON_MX6UL_CONFIG_H */ diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index beb1926c12a..e4d6a8a1540 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -49,6 +49,6 @@ #define CONFIG_MALLOC_F_ADDR 0x930000 #endif -#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV +#define CFG_EXTRA_ENV_SETTINGS BOOTENV #endif /* __KONTRON_MX8MM_CONFIG_H */ diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 17c63d83410..d909bbbbcfd 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -50,7 +50,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ "console=ttymxc2,115200\0" \ "boot_fdt=try\0" \ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index a073a06c827..0d293f316b7 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -61,7 +61,7 @@ func(PXE, pxe, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "env_addr=0x203e0004\0" \ "envload=env import -d -b ${env_addr}\0" \ "install_rcw=source 20200000\0" \ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index c551585a206..da8a67b4ab6 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -16,7 +16,7 @@ /* Command definition */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc1,115200\0" \ "fdt_addr=0x75000000\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 136e228682a..99321b320f5 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -22,7 +22,7 @@ #define CONFIG_MXC_USB_FLAGS 0 #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_addr=0x18000000\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 7a66df548a3..7ad29f92997 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -44,7 +44,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" \ diff --git a/include/configs/lager.h b/include/configs/lager.h index f3feaa539fc..777d5b94d1c 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -30,7 +30,7 @@ /* Board Clock */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" /* SPL support */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 794c1fcbed0..687ac89b857 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -48,7 +48,7 @@ * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootenvfile=uEnv.txt\0" \ "fdtfile=da850-lego-ev3.dtb\0" \ "memsize=64M\0" \ diff --git a/include/configs/librem5.h b/include/configs/librem5.h index 377e3e7b3fa..7417f8582a4 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -62,7 +62,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x80000000\0" \ "pxefile_addr_r=0x80100000\0" \ "kernel_addr_r=0x80800000\0" \ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 721da818633..938ab5ade9a 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -20,7 +20,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index f0a9e9ab315..d1e0ed5817e 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -11,8 +11,8 @@ /* DDR */ #define CFG_SYS_SDRAM_SIZE 0x40000000 -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr=0x01000000\0" \ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 9e4f949016e..a5f680db2d3 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -34,7 +34,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "loadaddr=0x80100000\0" \ "kernel_addr=0x100000\0" \ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index c19ed2f43ec..4243a21f1f1 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -16,8 +16,8 @@ #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "fdt_high=0xffffffffffffffff\0" \ "kernel_addr=0x01000000\0" \ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 1b417c72e70..872296749c0 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -25,8 +25,8 @@ func(USB, usb, 0) \ func(DHCP, dhcp, na) -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr=0x01000000\0" \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 495bb3911b3..35e8ff05798 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -55,8 +55,8 @@ #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "kernel_addr=0x01000000\0" \ "kernelheader_addr=0x600000\0" \ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index d74936d1281..1e843f896c7 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -36,8 +36,8 @@ #define __PHY_ETH2_MASK 0xFB #define __PHY_ETH1_MASK 0xFD -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr=0x01000000\0" \ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 0e3ff3c5b7a..8b5fba51c6f 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -72,7 +72,7 @@ #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 76e75335c58..78432e55811 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -247,12 +247,12 @@ #define HWCONFIG_BUFFER_SIZE 256 #ifdef CONFIG_LPUART -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #else -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index b15c4a238bc..b722586dd6b 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -60,7 +60,7 @@ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" \ "kernel_addr=0x61000000\0" \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 9b22a2db21a..a387eeab472 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -144,7 +144,7 @@ #include #ifdef CONFIG_LPUART -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \ "cma=64M@0x0-0xb0000000\0" \ "initrd_high=0xffffffff\0" \ @@ -200,7 +200,7 @@ "cp.b $kernel_addr $load_addr " \ "$kernel_size && bootm $load_addr#$board\0" #else -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \ "cma=64M@0x0-0xb0000000\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 228fb122f5f..769ece901c1 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -61,8 +61,8 @@ /* SATA */ #ifndef SPL_NO_ENV -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "board=ls1028aqds\0" \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 5c134612576..8c53636beac 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -56,8 +56,8 @@ /* Initial environment variables */ #ifndef SPL_NO_ENV -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "board=ls1028ardb\0" \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 685e7e65d15..ac2319c1b42 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -88,7 +88,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index ae9dc0c73b0..38fb1d45bcb 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -84,7 +84,7 @@ #endif #ifndef SPL_NO_MISC /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 86c5d48c0de..720a95d2f53 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -117,7 +117,7 @@ unsigned long long get_qixis_addr(void); #ifndef SPL_NO_ENV /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ "kernel_addr=0x100000\0" \ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 3391540c6e3..084ee064ae6 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -293,8 +293,8 @@ /* Initial environment variables */ #ifdef CONFIG_NXP_ESBC -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ @@ -325,8 +325,8 @@ #define IFC_MC_INIT_CMD \ "fsl_mc start mc 0x580A00000 0x580E00000\0" -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ @@ -387,8 +387,8 @@ "$kernel_size && bootm $kernel_load#$BOARD\0" #else #if defined(CONFIG_QSPI_BOOT) -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ @@ -405,8 +405,8 @@ "fsl_mc start mc 0x80a00000 0x80e00000\0" \ "mcmemsize=0x70000000 \0" #elif defined(CONFIG_SD_BOOT) -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ @@ -423,8 +423,8 @@ "fsl_mc start mc 0x80a00000 0x80e00000\0" \ "mcmemsize=0x70000000 \0" #else /* NOR BOOT */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 1ddf0687f43..a1749149e50 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -234,9 +234,9 @@ #endif #endif /* CONFIG_TFABOOT */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS #ifdef CONFIG_TFABOOT -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "BOARD=ls1088ardb\0" \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ @@ -304,7 +304,7 @@ " && esbc_validate ${kernelheader_addr_r};" \ "bootm $load_addr#$BOARD\0" #else -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "BOARD=ls1088ardb\0" \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index bd78bdb793a..f51eb31ed06 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -109,7 +109,7 @@ unsigned long long get_qixis_addr(void); #define HWCONFIG_BUFFER_SIZE 128 /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ "kernel_addr=0x100000\0" \ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 4a52fcdfddb..7ad2432a775 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -226,9 +226,9 @@ #define CFG_SYS_I2C_RTC_ADDR 0x68 /* Initial environment variables */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS #ifdef CONFIG_NXP_ESBC -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ "kernel_addr=0x100000\0" \ @@ -253,7 +253,7 @@ #define IFC_MC_INIT_CMD \ "fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ "loadaddr_sd=0x90100000\0" \ @@ -309,7 +309,7 @@ "$kernel_addr_sd $kernel_size_sd && " \ "bootm $load_addr#$BOARD\0" #elif defined(CONFIG_SD_BOOT) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x800\0" \ @@ -325,7 +325,7 @@ "fsl_mc start mc 0x80a00000 0x80e00000\0" \ "mcmemsize=0x70000000 \0" #else -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ "kernel_addr=0x100000\0" \ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index b8ab501c98e..794ea84852e 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -275,9 +275,9 @@ #endif /* Initial environment variables */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS #ifdef CONFIG_TFABOOT -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ @@ -339,7 +339,7 @@ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ "bootm $load_addr#$board\0" #else -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index c82eb8b04bf..47d7ec57b80 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -22,7 +22,7 @@ /* * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootsource=legacy\0" \ "hdpart=0:1\0" \ "kernel_addr_r=0x00800000\0" \ diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 9f891064bd5..3a316e73308 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -14,7 +14,7 @@ /* MAC/PHY configuration */ /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS \ "boot_scripts=lx2160aqds_boot.scr\0" \ "boot_script_hdr=hdr_lx2160aqds_bs.out\0" \ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 58c0ff36571..8cc4e0db03f 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -18,7 +18,7 @@ #define I2C_EMC2305_PWM 0x80 /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS \ "boot_scripts=lx2160ardb_boot.scr\0" \ "boot_script_hdr=hdr_lx2160ardb_bs.out\0" \ diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index 157688ef7d7..54d7cea4c59 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -14,7 +14,7 @@ #define CFG_SYS_RTC_BUS_NUM 0 /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS \ "boot_scripts=lx2162aqds_boot.scr\0" \ "boot_script_hdr=hdr_lx2162aqds_bs.out\0" \ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index d42ad9acb40..0deb7672f9e 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -84,7 +84,7 @@ * Extra Environments */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "consdev=ttymxc0\0" \ "baudrate=115200\0" \ "bootscript=boot.scr\0" \ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index a7f55076926..436f5f0059d 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -33,7 +33,7 @@ /* Ethernet Configuration */ #define CONFIG_FEC_MXC_PHYADDR 1 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200 quiet\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/meson64.h b/include/configs/meson64.h index a22f7a81b00..9244601284b 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -83,8 +83,8 @@ #include -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "stdin=" STDIN_CFG "\0" \ "stdout=" STDOUT_CFG "\0" \ "stderr=" STDOUT_CFG "\0" \ diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h index 1266851196d..c0e977abb01 100644 --- a/include/configs/meson64_android.h +++ b/include/configs/meson64_android.h @@ -279,7 +279,7 @@ "fi;" \ "fi;" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ EXTRA_ANDROID_ENV_SETTINGS \ "partitions=" PARTS_DEFAULT "\0" \ "mmcdev=2\0" \ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index b8b08974c7e..6740ab2be3e 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -76,8 +76,8 @@ #include -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "unlock=yes\0"\ "nor0=flash-0\0"\ "mtdparts=mtdparts=flash-0:"\ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index c73c5a1d9fe..5ced45b88b2 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -19,7 +19,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "kernel_addr_r=0x84000000\0" \ "fdt_addr_r=0x88000000\0" \ diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index cfe926c0a14..ef2111cd20a 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -30,7 +30,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 93161bd24f0..db12377b004 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -42,7 +42,7 @@ #include /* Extra environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index 3da7619d78d..1f973829bba 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -21,7 +21,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x40000000\0" \ BOOTENV diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h index 3a35527da10..c0fc8688ca6 100644 --- a/include/configs/mt8512.h +++ b/include/configs/mt8512.h @@ -26,7 +26,7 @@ #define ENV_BOOT_CMD \ "mtk_boot=run boot_rd_img;bootm;\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x6c000000\0" \ ENV_DEVICE_SETTINGS \ ENV_BOOT_READ_IMAGE \ diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index 0f7981a5661..73776e3705b 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -21,7 +21,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x40000000\0" \ BOOTENV diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index 8a8bc85ca70..d6bd1a10386 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -33,7 +33,7 @@ "serial#=1234567890ABCDEF\0" \ "board=mt8518\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x6c000000\0" \ ENV_DEVICE_SETTINGS \ ENV_BOOT_READ_IMAGE \ diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h index 3ad3aefa755..39e37ffbf7c 100644 --- a/include/configs/mvebu_alleycat-5.h +++ b/include/configs/mvebu_alleycat-5.h @@ -22,7 +22,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "kernel_addr_r=0x202000000\0" \ "fdt_addr_r=0x201000000\0" \ diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 9bfc48c52d9..76e148f55eb 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -89,7 +89,7 @@ "" /* fdt_addr and kernel_addr are needed for existing distribution boot scripts */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x6d00000\0" \ "pxefile_addr_r=0x6e00000\0" \ "fdt_addr=0x6f00000\0" \ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index beac3ae6496..239a09763ae 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -41,7 +41,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x6d00000\0" \ "pxefile_addr_r=0x6e00000\0" \ "fdt_addr_r=0x6f00000\0" \ diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index aa3d7a1a3fc..e769ba2e837 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -19,7 +19,7 @@ /* Ethernet */ /* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "update_sd_firmware_filename=u-boot.sd\0" \ "update_sd_firmware=" /* Update the SD firmware partition */ \ "if mmc rescan ; then " \ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index f597cdb3056..5ceba8b15fa 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -16,7 +16,7 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Extra Environments */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "update_sd_firmware_filename=u-boot.sd\0" \ "update_sd_firmware=" /* Update the SD firmware partition */ \ "if mmc rescan ; then " \ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index c740d853327..f9f65f6968e 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -18,7 +18,7 @@ /* UBI and NAND partitioning */ /* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "ubifs_file=filesystem.ubifs\0" \ "update_nand_full_filename=u-boot.nand\0" \ "update_nand_firmware_filename=u-boot.sb\0" \ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index ddd37b3936f..8ab1ee79a79 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -39,7 +39,7 @@ /* Framebuffer and LCD */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "fdt_file=imx51-babbage.dtb\0" \ diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index cd806cb698e..baffe65c369 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -37,7 +37,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_addr_r=0x75000000\0" \ "pxefile_addr_r=0x73000000\0" \ "scriptaddr=0x74000000\0" \ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index d0107fcc8cb..0ac93d6e043 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -27,7 +27,7 @@ /* Command definition */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "fdt_addr=0x71000000\0" \ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 9464d6e44ae..94d2191af91 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -35,7 +35,7 @@ "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \ "${nfsserver}:${image}; bootm ${loadaddr}\0" \ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ PPD_CONFIG_NFS \ "image=/boot/fitImage\0" \ "dev=mmc\0" \ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index f7f209c20b5..d4af96b51ea 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -21,7 +21,7 @@ #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "som_rev=undefined\0" \ "has_emmc=undefined\0" \ "fdtfile=undefined\0" \ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 96a48a97a30..9c61350a33b 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -35,7 +35,7 @@ #define EMMC_ENV "" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "fdtfile=undefined\0" \ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 358d9f47c0f..4fbd06783a6 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -15,7 +15,7 @@ /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 8731f6a3e4a..cf4871cbae3 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -12,7 +12,7 @@ #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "epdc_waveform=epdc_splash.bin\0" \ "script=boot.scr\0" \ "image=zImage\0" \ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 0dd40563c29..9d8737c1942 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -12,7 +12,7 @@ #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 6f5dffe4fbb..8372f979dc8 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -34,7 +34,7 @@ #define UPDATE_M4_ENV "" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ UPDATE_M4_ENV \ "script=boot.scr\0" \ "image=zImage\0" \ diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index cb1019bd56a..90c78846871 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -30,7 +30,7 @@ #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 0e986093f35..4a27fd22902 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -24,7 +24,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index e56b6101af4..e56083f8e61 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -50,7 +50,7 @@ "bootimg part 0 1;"\ "rootfs part 0 2\0" \ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ UPDATE_M4_ENV \ CONFIG_MFG_ENV_SETTINGS \ CFG_DFU_ENV_SETTINGS \ diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index 85922fa436c..5ee5129801d 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -28,7 +28,7 @@ #define PHYS_SDRAM 0x60000000 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ "console=ttyLP0\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 99e01896c71..5f4cd930623 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -28,7 +28,7 @@ #define PHYS_SDRAM_SIZE SZ_1G #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttyLP0\0" \ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index a32fcd57f8f..43261824d3c 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -33,7 +33,7 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "fdt_addr_r=0x82000000\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/nas220.h b/include/configs/nas220.h index 85691ca94f0..358c3bb85a5 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -35,7 +35,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs=console=ttyS0,115200\0" \ "autostart=no\0" diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 1d101977c28..496a3164f40 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -64,7 +64,7 @@ #include #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc1\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index caaa9ed86b3..97d08685290 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -58,7 +58,7 @@ #define CFG_SYS_ONENAND_BASE ONENAND_MAP /* Environment information */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "usbtty=cdc_acm\0" \ "stdin=usbtty,serial,keyboard\0" \ "stdout=usbtty,serial,vidconsole\0" \ diff --git a/include/configs/novena.h b/include/configs/novena.h index b0d473eeee3..3ffb44ab725 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -58,7 +58,7 @@ #endif /* Extra U-Boot environment. */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "consdev=ttymxc1\0" \ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 2eebd0c9a45..a12e34b6e60 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -38,7 +38,7 @@ #define CONFIG_FEC_ENET_DEV 1 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "image=zImage\0" \ "fdtfile=imx6ull-seeed-npi-dev-board.dtb\0" \ diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index e2ad77072cd..fa029a176bd 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -36,7 +36,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "kernel=/boot/zImage\0" \ "fdt=/boot/nsa310s.dtb\0" \ diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index ea1edab9fc1..0e1083a2130 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -15,7 +15,7 @@ # define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* CONFIG_CMD_USB */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "mmcdev=0\0" \ "mmcpart=2\0" \ "mmcargs=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcpart} console=ttymxc0,${baudrate} panic=30\0" \ diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index 03d1a8e7b5f..c4db38562d8 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -15,7 +15,7 @@ /** Stack starting address */ /** Extra environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=20080000\0" \ "ethrotate=yes\0" diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 58275ccffa0..0be26ef3287 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -17,7 +17,7 @@ #include /* Extra environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x20080000\0" \ "kernel_addr_r=0x02000000\0" \ "ramdisk_addr_r=0x03000000\0" \ @@ -27,7 +27,7 @@ #else /** Extra environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=20080000\0" \ "autoload=0\0" diff --git a/include/configs/odroid.h b/include/configs/odroid.h index e2331e45cdf..3ac13a65d63 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -71,7 +71,7 @@ * 1. BOOT: 100MiB 2MiB * 2. ROOT: - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadbootscript=load mmc ${mmcbootdev}:${mmcbootpart} ${scriptaddr} " \ "boot.scr\0" \ "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kernel_addr_r} " \ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index e4a81499a72..2bac017ea08 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -60,8 +60,8 @@ */ /* Define new extra env settings, including DFU settings */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS \ EXYNOS_FDTFILE_SETTING \ MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index f4e23bbb0f3..efeb7bf1007 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -73,7 +73,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 8bb8521f1c1..adb25a62970 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -69,7 +69,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index a6b5e55b541..93d36353ffb 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -59,7 +59,7 @@ "if test ${fdtfile} = ''; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_FINDFDT \ ENV_DEVICE_SETTINGS \ MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 38955377510..957f1c369e6 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -30,7 +30,7 @@ /* Environment information */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "mmcdev=0\0" \ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index f19211fe647..5e71ebcba85 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -137,7 +137,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ "bootpart=0:2\0" \ diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h index 5b097e9fef2..5adfc671958 100644 --- a/include/configs/openpiton-riscv64.h +++ b/include/configs/openpiton-riscv64.h @@ -20,7 +20,7 @@ * Board boot configuration */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_addr_r=0x86000000\0" \ "kernel_addr_r=0x80200000\0" \ "image=boot/Image\0" \ diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 2cec20ca425..1e6b16b4e70 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -27,7 +27,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console=ttyS0,115200 " \ +#define CFG_EXTRA_ENV_SETTINGS "x_bootargs=console=ttyS0,115200 " \ CONFIG_MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ "x_bootcmd_usb=usb start\0" \ diff --git a/include/configs/origen.h b/include/configs/origen.h index a608df44e80..fd4cc70a670 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -23,7 +23,7 @@ /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x40007000\0" \ "rdaddr=0x48000000\0" \ "kerneladdr=0x40007000\0" \ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 74627b2e630..a353c16f74b 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -393,7 +393,7 @@ #include "p1_p2_bootsrc.h" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \ "loadaddr=1000000\0" \ diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 2a1660bf188..146f87e9ce3 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -45,7 +45,7 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "fdt_addr_r=0x82000000\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 4421e740d9e..0890c115700 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -65,7 +65,7 @@ "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \ /* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "console=ttymxc0,115200n8\0" \ "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 5c2ff5d02ee..34994016c54 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -29,7 +29,7 @@ /* boot command, including the target-defined one if any */ /* Extra env settings (including the target-defined ones if any) */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ PCM052_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 3674e4cddae..2991076c50a 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -39,7 +39,7 @@ "nandloadfit=ubi part rootfs;ubi readvol ${loadaddr} fit\0" \ "nandboot=run nandloadfit;run nandargs;bootm ${loadaddr}\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x30000000\0" \ "optargs=rw rootwait\0" \ ENV_MMC \ diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index 71807837673..80b14b002a9 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -32,7 +32,7 @@ #define CONSOLE_DEV "ttyO5" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "fdtfile=am335x-pdu001.dtb\0" \ "bootfile=zImage\0" \ diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index f922491637d..4e6dc79f41b 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -62,7 +62,7 @@ #include #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_MMC_TI_ARGS \ DEFAULT_LINUX_BOOT_ENV \ "bootfile=zImage\0" \ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 7f73117ac1c..9160c78c046 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -20,7 +20,7 @@ /* For RAW image gives a error info not panic */ #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ "console=ttymxc2,115200\0" \ "fdt_addr=0x48000000\0" \ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 7a38382034a..d79d364c8e2 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -13,7 +13,7 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ "console=ttymxc0,115200\0" \ "fdt_addr=0x48000000\0" \ diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 3cc2a693cee..60c74732758 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -69,7 +69,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ CONFIG_LEGACY_BOOTCMD_ENV \ BOOTENV diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 719b7014405..66258a3ab73 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -38,7 +38,7 @@ "bootmenu_3=Boot using PICO-Nymph baseboard=" \ "setenv baseboard nymph; saveenv; run base_boot\0" \ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ BOOTMENU_ENV \ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 36f648f6340..45fc6126c87 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -45,7 +45,7 @@ "bootmenu_2=Boot using PICO-Pi baseboard=" \ "setenv fdtfile imx6ul-pico-pi.dtb\0" \ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "splashpos=m,m\0" \ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 58192151042..7fc6211ff73 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -51,7 +51,7 @@ BOOTENV #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ "splashpos=m,m\0" \ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index f9301a5524b..ac25991703f 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -25,7 +25,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=Image\0" \ "console=ttymxc0,115200\0" \ diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index a233fb8ed74..f4a34f261a6 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -144,7 +144,7 @@ /* USB */ #define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "partition=nand0,0\0" \ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index fa08744b6fe..cd9d21e420b 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -163,7 +163,7 @@ /* USB */ #define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "partition=nand0,0\0" \ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h index fc9f113dee6..b1354219c9f 100644 --- a/include/configs/pogo_e02.h +++ b/include/configs/pogo_e02.h @@ -18,7 +18,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs_console=console=ttyS0,115200\0" \ "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \ "ext2load usb 0:1 0x01100000 /uInitrd\0" diff --git a/include/configs/pogo_v4.h b/include/configs/pogo_v4.h index 239d33d8e9d..33715790233 100644 --- a/include/configs/pogo_v4.h +++ b/include/configs/pogo_v4.h @@ -61,7 +61,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ LOAD_ADDRESS_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ diff --git a/include/configs/poleg.h b/include/configs/poleg.h index 075729e5d37..c3f1d3393cb 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -14,7 +14,7 @@ #define CFG_SYS_SDRAM_BASE 0x0 /* Default environemnt variables */ -#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ +#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" \ diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h index 1c11685f49e..8e74dc48887 100644 --- a/include/configs/pomelo.h +++ b/include/configs/pomelo.h @@ -21,7 +21,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ BOOTENV \ "scriptaddr=0x90100000\0" \ diff --git a/include/configs/poplar.h b/include/configs/poplar.h index c58105597e4..6e8adf91877 100644 --- a/include/configs/poplar.h +++ b/include/configs/poplar.h @@ -31,7 +31,7 @@ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loader_mmc_blknum=0x0\0" \ "loader_mmc_nblks=0x780\0" \ "env_mmc_blknum=0xf80\0" \ diff --git a/include/configs/porter.h b/include/configs/porter.h index e0f77f358b9..202bd914d50 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -31,7 +31,7 @@ /* Board Clock */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" /* SPL support */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index 2b25c31b1d8..df07df6a5a7 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -54,7 +54,7 @@ #define GLOBAL_IO_DRIVE_CONTROL_OFFSET 0x4c /* max command args */ -#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0" +#define CFG_EXTRA_ENV_SETTINGS "silent=y\0" /* nand driver parameters */ #ifdef CONFIG_TARGET_PRESIDIO_ASIC diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 99376155b49..003686930a4 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -27,7 +27,7 @@ "ramdisk_addr_r=0x0a200000\0" #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 48f49906b84..10eaeb49de6 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -28,7 +28,7 @@ /* Use common default */ /* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hostname=pxm2\0" \ "ubi_off=2048\0"\ "nand_img_size=0x500000\0" \ diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h index c41bb341d82..8ea59aa21ca 100644 --- a/include/configs/qcs404-evb.h +++ b/include/configs/qcs404-evb.h @@ -13,7 +13,7 @@ #define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x5000000\0" \ "bootm_low=0x80000000\0" \ "bootcmd=bootm $prevbl_initrd_start_addr\0" diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index a67af73fd56..45bd94ee5c7 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -76,7 +76,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_addr=0x40000000\0" \ diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 35172da3ff1..20135f569eb 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -34,7 +34,7 @@ #define BOOTENV_DEV_NAME_QEMU(devtypeu, devtypel, instance) \ "qemu " -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr_r=0x84000000\0" \ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 59d56d66624..777df4c1125 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -38,7 +38,7 @@ #define EEPROM_ADDR_CHIP 0x120 /* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hostname=rastaban\0" \ "ubi_off=2048\0"\ "nand_img_size=0x400000\0" \ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 86012adfb36..8e0837a3027 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -32,7 +32,7 @@ /* ENV setting */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" #endif /* __RCAR_GEN3_COMMON_H */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index a4cae697181..ea6073f2944 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -25,7 +25,7 @@ /* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board, * so limit the fdt reallocation to that */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_high=0x7fffffff\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index 99c86edeaa4..c4758e148ba 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -24,7 +24,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x6fffffff\0" \ "initrd_high=0x6fffffff\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 302546630ac..5b0ec370004 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -27,7 +27,7 @@ "ramdisk_addr_r=0x64000000\0" #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 334fb3affa5..58f491c2f32 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -31,7 +31,7 @@ /* Linux fails to load the fdt if it's loaded above 256M on a Rock board, * so limit the fdt reallocation to that */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_high=0x6fffffff\0" \ "initrd_high=0x6fffffff\0" \ diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 58ad62afe16..b95268df87c 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -27,7 +27,7 @@ /* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board, * so limit the fdt reallocation to that */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_high=0x7fffffff\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 6b55c57dd77..d3b8a5150f6 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -30,7 +30,7 @@ /* Linux fails to load the fdt if it's loaded above 256M on a Rock 2 board, so * limit the fdt reallocation to that */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x0fffffff\0" \ "initrd_high=0x0fffffff\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 4b510b13991..bc03e113fef 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -22,7 +22,7 @@ "ramdisk_addr_r=0x04000000\0" #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "partitions=" PARTS_DEFAULT \ ROCKCHIP_DEVICE_SETTINGS \ diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 132b7d0fe9b..85d2186f23e 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -22,7 +22,7 @@ "ramdisk_addr_r=0x06000000\0" #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 92cdc1a51fb..17636250510 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -25,7 +25,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index a721f27ec00..2278b6215d4 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -50,7 +50,7 @@ #include #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index d43dc2580e4..750f16d0399 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -21,7 +21,7 @@ "ramdisk_addr_r=0x0a200000\0" #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/rpi.h b/include/configs/rpi.h index e3549275138..c3f8e7bf85c 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -157,7 +157,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \ ENV_DEVICE_SETTINGS \ ENV_DFU_SETTINGS \ diff --git a/include/configs/rut.h b/include/configs/rut.h index b07d0c50604..99799f8494e 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -27,7 +27,7 @@ /* Use common default */ /* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hostname=rut\0" \ "ubi_off=2048\0"\ "nand_img_size=0x500000\0" \ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 84a5ae6965d..6e17b23b624 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -26,7 +26,7 @@ "ramdisk_addr_r=0x64000000\0" #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index b4b2dbd0386..bfe559f6e2c 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -140,7 +140,7 @@ #define EXTRA_ENV_BOOT_LOGO EXTRA_ENV_DTB_RESERVE #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "rootdev=" __stringify(CONFIG_ROOT_DEV) "\0" \ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 555bedb93d6..d1ff00a27f8 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -54,7 +54,7 @@ #define COMMON_BOOT "${console} ${meminfo} ${mtdparts}" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "updateb=" \ "onenand erase 0x0 0x100000;" \ "onenand write 0x32008000 0x0 0x100000\0" \ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 80d3fc9258c..bf2d04a169b 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -29,7 +29,7 @@ ",100M(swap)"\ ",-(UMS)\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "updateb=" \ "onenand erase 0x0 0x100000;" \ "onenand write 0x42008000 0x0 0x100000\0" \ diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h index f7cdd5a1956..9a4fe530a20 100644 --- a/include/configs/sdm845.h +++ b/include/configs/sdm845.h @@ -13,7 +13,7 @@ #define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x4000000\0" \ "bootm_low=0x80000000\0" \ "stdout=vidconsole\0" \ diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index d7923967a72..4e0b3c663c7 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -15,7 +15,7 @@ /* * Environment variables configurations */ -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ +#define CFG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ "=ttyS0,115200 mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \ "x_bootcmd_usb=usb start\0" \ diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index 4a453a9df40..de3a0dcdd59 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -37,7 +37,7 @@ "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \ "name=system,size=-,bootable,type=${type_guid_gpt_system};" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr_r=0x84000000\0" \ diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index ac42108620f..24904aa2387 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -34,7 +34,7 @@ "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \ "name=system,size=-,bootable,type=${type_guid_gpt_system};" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x84000000\0" \ "kernel_comp_addr_r=0x88000000\0" \ "kernel_comp_size=0x4000000\0" \ diff --git a/include/configs/silk.h b/include/configs/silk.h index 6d605edf788..9114a057582 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -31,7 +31,7 @@ /* Board Clock */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" /* SPL support */ diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index 974531ea0d8..760a0a5b913 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -11,8 +11,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define CFG_SYS_SDRAM_SIZE SZ_8M -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80060000\0" \ "fdt_addr_r=0x80400000\0" \ "scriptaddr=0x80020000\0" \ diff --git a/include/configs/slimbootloader.h b/include/configs/slimbootloader.h index ff0ed180e92..748a423b083 100644 --- a/include/configs/slimbootloader.h +++ b/include/configs/slimbootloader.h @@ -14,10 +14,10 @@ "stderr=serial\0" /* - * Override CONFIG_EXTRA_ENV_SETTINGS in x86-common.h + * Override CFG_EXTRA_ENV_SETTINGS in x86-common.h */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ CONFIG_STD_DEVICES_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index b988b96e58d..762f61470b1 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -73,7 +73,7 @@ * Predefined environment variables. * Usefull to define some easy to use boot commands. */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ \ "basicargs=console=ttyS0,115200\0" \ \ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index ccb7ec38d03..c148757915a 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -28,7 +28,7 @@ " mem=128M " \ " " CONFIG_MTDPARTS_DEFAULT -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "updateb=" \ "onenand erase 0x0 0x40000;" \ "onenand write 0x32008000 0x0 0x40000\0" \ diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index 14f9cf56028..11031744bef 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -17,7 +17,7 @@ /* MMC Config*/ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ "console=ttymxc0\0" \ "fdtfile=imx7d-smegw01.dtb\0" \ diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index b7aa49ce435..df8ed451a43 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -41,7 +41,7 @@ /* Environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "ethaddr=00:00:00:00:00:00\0" \ "serial=0\0" \ "stdout=serial_atmel\0" \ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index afca7e18e9b..eaee8dd3739 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -62,7 +62,7 @@ * Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x82000000\0" \ "loadaddr=0x82000000\0" \ "fdt_addr_r=0x88000000\0" \ diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h index aa13878177e..2ce7011529a 100644 --- a/include/configs/socfpga_chameleonv3.h +++ b/include/configs/socfpga_chameleonv3.h @@ -19,7 +19,7 @@ */ #define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "autoload=no\0" \ "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw rootwait\0" \ "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index d0f5331d451..0c96c9c24fe 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -144,8 +144,8 @@ #include -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "bootm_size=0xa000000\0" \ "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ diff --git a/include/configs/socfpga_dbm_soc1.h b/include/configs/socfpga_dbm_soc1.h index 8f1c2de998e..565a661258f 100644 --- a/include/configs/socfpga_dbm_soc1.h +++ b/include/configs/socfpga_dbm_soc1.h @@ -13,7 +13,7 @@ /* Environment is in MMC */ /* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "consdev=ttyS0\0" \ "baudrate=115200\0" \ "bootscript=boot.scr\0" \ diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index e76438e228d..ac70d91e208 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -13,7 +13,7 @@ /* Environment is in MMC */ /* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "consdev=ttyS0\0" \ "baudrate=115200\0" \ "bootscript=boot.scr\0" \ diff --git a/include/configs/socfpga_n5x_socdk.h b/include/configs/socfpga_n5x_socdk.h index c295e91e3d3..fe5286e12cd 100644 --- a/include/configs/socfpga_n5x_socdk.h +++ b/include/configs/socfpga_n5x_socdk.h @@ -9,8 +9,8 @@ #include -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootfile=" CONFIG_BOOTFILE "\0" \ "fdt_addr=1100000\0" \ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index df3927297bb..66ecb168a0a 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -36,7 +36,7 @@ /* * Environment variable */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootfile=" CONFIG_BOOTFILE "\0" \ "fdt_addr=8000000\0" \ diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index d88b07bc159..4bb15cf4629 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -27,7 +27,7 @@ * Linux system after 5 seconds */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ "consdev=ttyS0\0" \ "baudrate=115200\0" \ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 4c752091fb5..2b35be83ec6 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -111,7 +111,7 @@ #define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consdev=ttyS0\0" \ "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index de0f48b79a1..e1328056351 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -20,7 +20,7 @@ #define CFG_SYS_FSL_USDHC_NUM 1 #endif /* CONFIG_FSL_USDHC */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "console=ttymxc0\0" \ "initrd_addr=0x86800000\0" \ diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h index a5987c5e17a..e58ddd752cd 100644 --- a/include/configs/stemmy.h +++ b/include/configs/stemmy.h @@ -38,7 +38,7 @@ #define BOOTCMD_ENV \ "fastbootcmd=echo '*** FASTBOOT MODE ***'; fastboot usb 0\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOT_ENV \ CONSOLE_ENV \ FASTBOOT_ENV \ diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 9294d57ca84..b3fce503168 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -29,7 +29,7 @@ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x40000000\0" \ "fdtfile=stih410-b2260.dtb\0" \ "fdt_addr_r=0x47000000\0" \ diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index afd7d50428b..de5019a364a 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -15,7 +15,7 @@ #define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ "bootm 0x08044000 - 0x08042000\0" diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index c8aad47966f..a4f3e43dc5a 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -24,7 +24,7 @@ func(MMC, mmc, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x00008000\0" \ "fdtfile=stm32429i-eval.dtb\0" \ "fdt_addr_r=0x00408000\0" \ diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index 573a6b17956..62a7e9af0c5 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -24,7 +24,7 @@ func(MMC, mmc, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x00008000\0" \ "fdtfile=stm32f469-disco.dtb\0" \ "fdt_addr_r=0x00408000\0" \ diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 14e883a3589..34856d30040 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -24,7 +24,7 @@ func(MMC, mmc, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0xC0008000\0" \ "fdtfile="CONFIG_DEFAULT_DEVICE_TREE".dtb\0" \ "fdt_addr_r=0xC0408000\0" \ diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index 67e6a3a19d2..d36cd6fdd44 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -21,7 +21,7 @@ func(MMC, mmc, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0xD0008000\0" \ "fdtfile=stm32h743i-disco.dtb\0" \ "fdt_addr_r=0xD0408000\0" \ diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index 4786eb001bc..8f242bf0ff6 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -21,7 +21,7 @@ func(MMC, mmc, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0xD0008000\0" \ "fdtfile=stm32h743i-eval.dtb\0" \ "fdt_addr_r=0xD0408000\0" \ diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h index e667fe6f6ac..d27b6a3d1de 100644 --- a/include/configs/stm32h750-art-pi.h +++ b/include/configs/stm32h750-art-pi.h @@ -21,7 +21,7 @@ func(MMC, mmc, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0xC0008000\0" \ "fdtfile=stm32h750i-art-pi.dtb\0" \ "fdt_addr_r=0xC0408000\0" \ diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index c259a616133..7c59c69e0bd 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -81,7 +81,7 @@ "fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \ "ramdisk_addr_r=" __RAMDISK_ADDR_R "\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ STM32MP_MEM_LAYOUT \ STM32MP_BOOTCMD \ BOOTENV \ diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 9715dfad1c9..7db72a19ed9 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -135,7 +135,7 @@ "fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \ "ramdisk_addr_r=" __RAMDISK_ADDR_R "\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ STM32MP_MEM_LAYOUT \ STM32MP_BOOTCMD \ STM32MP_PARTS_DEFAULT \ diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index 910d7ef107b..91921690624 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -12,7 +12,7 @@ #define PHY_ANEG_TIMEOUT 20000 #ifdef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "dfu_alt_info_ram=u-boot.itb ram " \ __stringify(CONFIG_SPL_LOAD_FIT_ADDRESS) \ " 0x800000\0" diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 38b5aa7319c..d0cd4130cec 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -18,7 +18,7 @@ 230400, 460800, 921600, \ 1000000, 2000000 } -#ifdef CONFIG_EXTRA_ENV_SETTINGS +#ifdef CFG_EXTRA_ENV_SETTINGS /* * default bootcmd for stm32mp1 STMicroelectronics boards: * for serial/usb: execute the stm32prog command @@ -42,8 +42,8 @@ "run distro_bootcmd;" \ "fi;\0" -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ STM32MP_MEM_LAYOUT \ ST_STM32MP1_BOOTCMD \ STM32MP_PARTS_DEFAULT \ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index ce941d832a5..fe2ba9a03b4 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -13,7 +13,7 @@ #define LDS_BOARD_TEXT \ board/sysam/stmark2/sbf_dram_init.o (.text*) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kern_size=0x700000\0" \ "loadaddr=0x40001000\0" \ "-(rootfs)\0" \ diff --git a/include/configs/stout.h b/include/configs/stout.h index 977c0adc5f0..ee1abe691bf 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -35,7 +35,7 @@ /* Board Clock */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" /* SPL support */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 5d82e7e560f..eae107fe5ec 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -318,7 +318,7 @@ #define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ CONSOLE_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ MEM_LAYOUT_ENV_EXTRA_SETTINGS \ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index a2b6a1f57d7..a62d1d32547 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -91,7 +91,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_addr_r=0x9fe00000\0" \ "kernel_addr_r=0x90000000\0" \ "ramdisk_addr_r=0xa0000000\0" \ diff --git a/include/configs/syzygy_hub.h b/include/configs/syzygy_hub.h index 7af7b08eb48..e8a207f5416 100644 --- a/include/configs/syzygy_hub.h +++ b/include/configs/syzygy_hub.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_SYZYGY_HUB_H #define __CONFIG_SYZYGY_HUB_H -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fit_image=fit.itb\0" \ "bitstream_image=download.bit\0" \ "loadbit_addr=0x1000000\0" \ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 30f84255820..855218a8901 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -72,7 +72,7 @@ /* bootstrap in spi flash , u-boot + env + linux in nandflash */ #if defined(CONFIG_BOARD_AXM) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ "${gatewayip}:${netmask}:${hostname}:${netdev}::off\0" \ "addtest=setenv bootargs ${bootargs} loglevel=4 test\0" \ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 689914cb187..9b396e6e73b 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -30,7 +30,7 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* CONFIG_CMD_USB */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 2c668e0611b..0fdb5a81605 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -65,7 +65,7 @@ #define INITRD_HIGH "ffffffff" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "fdt_high=" FDT_HIGH "\0" \ diff --git a/include/configs/ten64.h b/include/configs/ten64.h index 57724719a9d..e86c1631329 100644 --- a/include/configs/ten64.h +++ b/include/configs/ten64.h @@ -34,9 +34,9 @@ func(PXE, pxe, 0) #include -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "BOARD=ten64\0" \ "fdt_addr_r=0x90000000\0" \ "fdt_high=0xa0000000\0" \ diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h index b57b1beaafe..746995179f9 100644 --- a/include/configs/theadorable-x86-common.h +++ b/include/configs/theadorable-x86-common.h @@ -19,9 +19,9 @@ /* Environment settings */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "tftpdir=" DEF_ENV_TFTPDIR "\0" \ "eth_init=" DEF_ENV_ETH_INIT "\0" \ "ubuntu_part=" __stringify(DEF_ENV_UBUNTU_PART) "\0" \ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 76b496303f3..9722b0db72a 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -35,7 +35,7 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ /* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" diff --git a/include/configs/thuban.h b/include/configs/thuban.h index c8b27263e85..1753fa410d1 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -31,7 +31,7 @@ #define EEPROM_ADDR_CHIP 0x120 /* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hostname=thuban\0" \ "ubi_off=2048\0"\ "nand_img_size=0x400000\0" \ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 7becf1eb7cb..8ba40546b2c 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -35,7 +35,7 @@ /* Initial environment variables */ #define UBOOT_IMG_HEAD_SIZE 0x40 /* C80000 - 0x40 */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr=08007ffc0\0" \ "fdt_addr=0x94C00000\0" \ "fdt_high=0x9fffffff\0" diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 7b04292d218..2d9d2fd66e9 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -12,7 +12,7 @@ #include #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV /* Clock Defines */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index ea45bba409c..479ab46e4ed 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -106,7 +106,7 @@ "rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; " \ "rproc start ${dev_pmmc}\0" \ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ ENV_KS2_BOARD_SETTINGS \ DFUARGS \ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 64ec59d78eb..49f4263e16b 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -58,7 +58,7 @@ #include #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 37ab2e44672..e9723ed5b3d 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -247,7 +247,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index 83abaeddf12..3795e6152fa 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -44,8 +44,8 @@ # define EXTRA_ENV_USB #endif -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_image=uImage\0" \ "kernel_addr=0x2080000\0" \ "ramdisk_image=uramdisk.image.gz\0" \ diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index 0f28690612a..e007be8e456 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -28,7 +28,7 @@ #define PHYS_SDRAM_2 0x8080000000 #define PHYS_SDRAM_2_SIZE 0x180000000 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x20000000\0" \ "load_addr=0xa0000000\0" \ "kernel_addr_r=0x80080000\0" \ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 7a1ad9544a3..14d7730f67b 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -197,7 +197,7 @@ /* set to a resonable value, changeable by user */ #define TQMA6_CMA_SIZE 160M -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "board=tqma6\0" \ "uimage=uImage\0" \ "zimage=zImage\0" \ diff --git a/include/configs/trats.h b/include/configs/trats.h index 3eac66539df..2067327918a 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -54,7 +54,7 @@ "params.bin raw 0x38 0x8;" \ "/Image.itb ext4 0 2\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootk=" \ "run loaduimage;" \ "if run loaddtb; then " \ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 18fca09a380..9925531aba4 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -55,7 +55,7 @@ "params.bin raw 0x38 0x8;" \ "/Image.itb ext4 0 2\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootk=" \ "run loaduimage;" \ "if run loaddtb; then " \ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index fdb420ed874..3443c80d06e 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -35,7 +35,7 @@ "lzmadec 0x5000000 0x5800000 && " \ "bootm 0x5800000" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_addr=0x4c00000\0" \ "scriptaddr=0x4d00000\0" \ "pxefile_addr_r=0x4e00000\0" \ diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 52de4cdc789..47b220ff9ee 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -80,7 +80,7 @@ "fi; " \ "bootz 0x1000000" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ RELOCATION_LIMITS_ENV_SETTINGS \ LOAD_ADDRESS_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index fac8c1eeb4e..f0092eff149 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -15,7 +15,7 @@ /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc1,115200\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index d4c92233aca..5d7d734daa2 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -19,7 +19,7 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* Linux only */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 7fee64029d8..ecf0d2ac44a 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -86,7 +86,7 @@ "run boot_common\0" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_addr_r_offset=0x05100000\0" \ "kernel_addr_r_offset=" KERNEL_ADDR_R_OFFSET "\0" \ "ramdisk_addr_r_offset=0x06000000\0" \ diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 657dbadd339..b90e047955b 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -43,6 +43,6 @@ #endif /* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ #endif diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 7f79c6342fc..11706148f1e 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -40,7 +40,7 @@ "pxefile_addr_r=0x70800000\0" \ "ramdisk_addr_r=0x73000000\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "bootargs_default=root=/dev/mmcblk0p1 rootwait rw\0" \ "fdtfile=imx53-usbarmory.dtb\0" \ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index b03159805c1..2e150276e7a 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -25,7 +25,7 @@ #error Unknown DDR size - please add! #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x81000000\0" \ "spi_image_off=0x00100000\0" \ "console=ttyS0,115200\0" \ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 18ac6b2b089..7f3fa795afd 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -34,7 +34,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ "bootcmd_mfg=fastboot 0\0" \ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 22dc364223c..2cb076cabac 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -43,7 +43,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ "bootcmd_mfg=fastboot 0\0" \ diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 30c1f5025b0..87b8c5d57ee 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -244,7 +244,7 @@ #include /* Default load addresses and names for the different payloads. */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=" __stringify(VEXPRESS_KERNEL_ADDR) "\0" \ "ramdisk_addr_r=" __stringify(VEXPRESS_RAMDISK_ADDR) "\0" \ "pxefile_addr_r=" __stringify(VEXPRESS_PXEFILE_ADDR) "\0" \ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index e8b6acf8b8f..705a941e360 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -145,7 +145,7 @@ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x60100000\0" \ "fdt_addr_r=0x60000000\0" \ "bootargs=console=tty0 console=ttyAMA0,38400n8\0" \ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 14e6b2bac91..0e0b3a7b594 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -44,7 +44,7 @@ "rdaddr=0x84080000\0" \ "ramdisk_addr_r=0x84080000\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ diff --git a/include/configs/vinco.h b/include/configs/vinco.h index 1c1789ac3fb..0698ae1d1c6 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -45,7 +45,7 @@ /* Update the bootcommand according to our mapping for the VInCo platform */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_start=0x20000\0" \ "kernel_size=0x800000\0" \ "mmcblksize=0x200\0" \ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 6923009d459..1e765439fab 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -20,7 +20,7 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ "splashpos=m,m\0" \ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 188180da54e..0826e0bbe02 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -26,7 +26,7 @@ #define BOOT_SCR_STRING "source ${bootscriptaddr}\0" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ CFG_DFU_ENV_SETTINGS \ "script=boot.scr\0" \ "bootscr_fitimage_name=bootscr\0" \ diff --git a/include/configs/x530.h b/include/configs/x530.h index 4cf41f52fd7..fddf00d3d13 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -47,7 +47,7 @@ #include /* Keep device tree and initrd in low memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index d71108dd318..65a1e63e00e 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -42,7 +42,7 @@ #define SPLASH_SETTINGS #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DISTRO_BOOTENV \ CONFIG_STD_DEVICES_SETTINGS \ SPLASH_SETTINGS \ diff --git a/include/configs/xea.h b/include/configs/xea.h index a3dc0c74ebb..04ca5aa12ac 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -27,7 +27,7 @@ /* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootmode=update\0" \ "bootpri=mmc_mmc\0" \ "bootsec=sf_swu\0" \ diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h index 612436aeb48..bc268d25dc3 100644 --- a/include/configs/xenguest_arm64.h +++ b/include/configs/xenguest_arm64.h @@ -9,12 +9,12 @@ #include #endif -#define CONFIG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS #undef CFG_SYS_SDRAM_BASE -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "loadimage=ext4load pvblock 0 0x90000000 /boot/Image;\0" \ "pvblockboot=run loadimage;" \ "booti 0x90000000 - 0x88000000;\0" diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 6ee6786e054..e70acd93bac 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -126,8 +126,8 @@ #include /* Initial environment variables */ -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV #endif diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h index e1f95de3c34..23655a47522 100644 --- a/include/configs/xilinx_versal_mini.h +++ b/include/configs/xilinx_versal_mini.h @@ -10,11 +10,11 @@ #ifndef __CONFIG_VERSAL_MINI_H #define __CONFIG_VERSAL_MINI_H -#define CONFIG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS #include /* Undef unneeded configs */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS #endif /* __CONFIG_VERSAL_MINI_H */ diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h index 37bdb214629..424ead038e3 100644 --- a/include/configs/xilinx_versal_net.h +++ b/include/configs/xilinx_versal_net.h @@ -123,8 +123,8 @@ #include /* Initial environment variables */ -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV \ DFU_ALT_INFO diff --git a/include/configs/xilinx_versal_net_mini.h b/include/configs/xilinx_versal_net_mini.h index 1939832a848..50bacc39ac5 100644 --- a/include/configs/xilinx_versal_net_mini.h +++ b/include/configs/xilinx_versal_net_mini.h @@ -11,11 +11,11 @@ #ifndef __CONFIG_VERSAL_NET_MINI_H #define __CONFIG_VERSAL_NET_MINI_H -#define CONFIG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS #include /* Undef unneeded configs */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS #endif /* __CONFIG_VERSAL_NET_MINI_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index f71cd660993..011f0034c50 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -173,16 +173,16 @@ #include /* Initial environment variables */ -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV #endif /* SPL can't handle all huge variables - define just DFU */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) -#undef CONFIG_EXTRA_ENV_SETTINGS -# define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +# define CFG_EXTRA_ENV_SETTINGS \ "dfu_alt_info_ram=uboot.bin ram 0x8000000 0x1000000;" \ "atf-uboot.ub ram 0x10000000 0x1000000;" \ "Image ram 0x80000 0x3f80000;" \ diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index 1c0ab25c644..9af05456640 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -10,11 +10,11 @@ #ifndef __CONFIG_ZYNQMP_MINI_H #define __CONFIG_ZYNQMP_MINI_H -#define CONFIG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS #include /* Undef unneeded configs */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS #endif /* __CONFIG_ZYNQMP_MINI_H */ diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h index 3a7b7e03d6a..918aa3d7402 100644 --- a/include/configs/xilinx_zynqmp_r5.h +++ b/include/configs/xilinx_zynqmp_r5.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_ZYNQMP_R5_H #define __CONFIG_ZYNQMP_R5_H -#define CONFIG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS /* Serial drivers */ /* The following table includes the supported baudrates */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 9f1f2d90dbe..0d72008bb46 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -34,7 +34,7 @@ #define CONFIG_FEC_ENET_DEV 0 #define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc6\0" \ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index d95178eb642..e372e903170 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -170,8 +170,8 @@ #endif /* CONFIG_SPL_BUILD */ /* Default environment */ -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x20000\0" \ "script_size_f=0x40000\0" \ "fdt_addr_r=0x1f00000\0" \ diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h index ac6e8c4ff86..a9bb5bb90ad 100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@ -12,7 +12,7 @@ #include /* Undef unneeded configs */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS #undef CFG_SYS_INIT_RAM_ADDR #undef CFG_SYS_INIT_RAM_SIZE diff --git a/include/env_default.h b/include/env_default.h index 3b7685ee26c..c0df39d62f9 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -118,8 +118,8 @@ const char default_environment[] = { /* This is created in the Makefile */ CONFIG_EXTRA_ENV_TEXT #endif -#ifdef CONFIG_EXTRA_ENV_SETTINGS - CONFIG_EXTRA_ENV_SETTINGS +#ifdef CFG_EXTRA_ENV_SETTINGS + CFG_EXTRA_ENV_SETTINGS #endif "\0" #else /* CONFIG_USE_DEFAULT_ENV_FILE */ -- cgit v1.3.1 From 4daffb58e6ccd36f9fdab8ef45cde8548226c4f6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:52 -0500 Subject: global: Migrate CONFIG_FEC_ENET_DEV to CFG Perform a simple rename of CONFIG_FEC_ENET_DEV to CFG_FEC_ENET_DEV Signed-off-by: Tom Rini --- board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 2 +- board/freescale/mx6ullevk/mx6ullevk.c | 2 +- board/seeed/npi_imx6ull/npi_imx6ull.c | 2 +- board/variscite/dart_6ul/dart_6ul.c | 2 +- include/configs/capricorn-common.h | 2 +- include/configs/dart_6ul.h | 2 +- include/configs/liteboard.h | 2 +- include/configs/mx6ul_14x14_evk.h | 6 +++--- include/configs/mx6ullevk.h | 2 +- include/configs/npi_imx6ull.h | 2 +- include/configs/xpress.h | 2 +- 11 files changed, 13 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 1eec048a66f..570b5014dbb 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -281,7 +281,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_FEC_MXC - setup_fec(CONFIG_FEC_ENET_DEV); + setup_fec(CFG_FEC_ENET_DEV); #endif #ifdef CONFIG_USB_EHCI_MX6 diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c index 86c11c7bd3a..e2473806475 100644 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -110,7 +110,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_FEC_MXC - setup_fec(CONFIG_FEC_ENET_DEV); + setup_fec(CFG_FEC_ENET_DEV); #endif return 0; diff --git a/board/seeed/npi_imx6ull/npi_imx6ull.c b/board/seeed/npi_imx6ull/npi_imx6ull.c index eb9ee555c85..c610d2c3069 100644 --- a/board/seeed/npi_imx6ull/npi_imx6ull.c +++ b/board/seeed/npi_imx6ull/npi_imx6ull.c @@ -100,7 +100,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_FEC_MXC - setup_fec(CONFIG_FEC_ENET_DEV); + setup_fec(CFG_FEC_ENET_DEV); #endif return 0; diff --git a/board/variscite/dart_6ul/dart_6ul.c b/board/variscite/dart_6ul/dart_6ul.c index 7326daa1798..98d8d1c3120 100644 --- a/board/variscite/dart_6ul/dart_6ul.c +++ b/board/variscite/dart_6ul/dart_6ul.c @@ -147,7 +147,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_FEC_MXC - setup_fec(CONFIG_FEC_ENET_DEV); + setup_fec(CFG_FEC_ENET_DEV); #endif #ifdef CONFIG_NAND_MXS diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index a8273a7fcd8..63afa6e1896 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -19,7 +19,7 @@ #endif /* CONFIG_SPL_BUILD */ /* ENET1 connects to base board and MUX with ESAI */ -#define CONFIG_FEC_ENET_DEV 1 +#define CFG_FEC_ENET_DEV 1 #define CONFIG_FEC_MXC_PHYADDR 0x0 /* EEPROM */ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index 323703ac5c9..c2ed9c7c56a 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -18,7 +18,7 @@ #endif #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_ENET_DEV 0 +#define CFG_FEC_ENET_DEV 0 #endif /* Environment settings */ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 938ab5ade9a..7200c69bd9e 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -100,7 +100,7 @@ #endif #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_ENET_DEV 0 +#define CFG_FEC_ENET_DEV 0 #define CONFIG_FEC_MXC_PHYADDR 0x0 #endif diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 90c78846871..efc599f37a6 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -121,11 +121,11 @@ #endif #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_ENET_DEV 1 +#define CFG_FEC_ENET_DEV 1 -#if (CONFIG_FEC_ENET_DEV == 0) +#if (CFG_FEC_ENET_DEV == 0) #define CONFIG_FEC_MXC_PHYADDR 0x2 -#elif (CONFIG_FEC_ENET_DEV == 1) +#elif (CFG_FEC_ENET_DEV == 1) #define CONFIG_FEC_MXC_PHYADDR 0x1 #endif #endif diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 4a27fd22902..58d1a744ae9 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -109,7 +109,7 @@ /* environment organization */ #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_ENET_DEV 1 +#define CFG_FEC_ENET_DEV 1 #endif #endif diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index a12e34b6e60..979512c0a09 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -36,7 +36,7 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1 #endif -#define CONFIG_FEC_ENET_DEV 1 +#define CFG_FEC_ENET_DEV 1 #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 0d72008bb46..13f0ee62b89 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -31,7 +31,7 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_FEC_ENET_DEV 0 +#define CFG_FEC_ENET_DEV 0 #define CONFIG_FEC_MXC_PHYADDR 0x0 #define CFG_EXTRA_ENV_SETTINGS \ -- cgit v1.3.1 From fa760c3240c1498f20eaf5f4a7d6007d7df0c61a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:53 -0500 Subject: global: Migrate CONFIG_FEC_MXC_PHYADDR to CFG Perform a simple rename of CONFIG_FEC_MXC_PHYADDR to CFG_FEC_MXC_PHYADDR Signed-off-by: Tom Rini --- board/compulab/cl-som-imx7/cl-som-imx7.c | 2 +- board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 2 +- doc/README.fec_mxc | 2 +- drivers/net/fec_mxc.c | 4 ++-- include/configs/aristainetos2.h | 2 +- include/configs/capricorn-common.h | 2 +- include/configs/cgtqmx8.h | 2 +- include/configs/cl-som-imx7.h | 2 +- include/configs/cm_fx6.h | 2 +- include/configs/imx6_logic.h | 2 +- include/configs/imx6dl-mamoj.h | 2 +- include/configs/imx8mm-cl-iot-gate.h | 2 +- include/configs/imx8mm_evk.h | 2 +- include/configs/imx8mp_evk.h | 2 +- include/configs/imx8mp_icore_mx8mp.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/imx8mq_evk.h | 2 +- include/configs/imx8mq_phanbell.h | 2 +- include/configs/imx8ulp_evk.h | 2 +- include/configs/kontron_pitx_imx8m.h | 2 +- include/configs/liteboard.h | 2 +- include/configs/m53menlo.h | 2 +- include/configs/mccmon6.h | 2 +- include/configs/msc_sm2s_imx8mp.h | 2 +- include/configs/mx6sxsabreauto.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/mx6ul_14x14_evk.h | 4 ++-- include/configs/nitrogen6x.h | 2 +- include/configs/npi_imx6ull.h | 2 +- include/configs/pico-imx6.h | 2 +- include/configs/pico-imx6ul.h | 2 +- include/configs/pico-imx8mq.h | 2 +- include/configs/somlabs_visionsom_6ull.h | 2 +- include/configs/tqma6_mba6.h | 2 +- include/configs/tqma6_wru4.h | 2 +- include/configs/vf610twr.h | 2 +- include/configs/vining_2000.h | 2 +- include/configs/xpress.h | 2 +- 38 files changed, 40 insertions(+), 40 deletions(-) (limited to 'include') diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c index 9733a33ee2c..1b08a2c5abf 100644 --- a/board/compulab/cl-som-imx7/cl-som-imx7.c +++ b/board/compulab/cl-som-imx7/cl-som-imx7.c @@ -214,7 +214,7 @@ int board_eth_init(struct bd_info *bis) gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1); /* MAC initialization */ return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI, - CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE); } /* diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 7340a344023..9205d5ef6dd 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -104,7 +104,7 @@ int board_eth_init(struct bd_info *bis) setup_fec(); ret = fecmxc_initialize_multi(bis, 1, - CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE); if (ret) printf("FEC%d MXC: %s:failed\n", 1, __func__); diff --git a/doc/README.fec_mxc b/doc/README.fec_mxc index 4e890d348f4..2ccd4288d28 100644 --- a/doc/README.fec_mxc +++ b/doc/README.fec_mxc @@ -18,7 +18,7 @@ CONFIG_PHYLIB CONFIG_FEC_MXC_NO_ANEG Relevant only if PHYLIB not used. Skips auto-negotiation restart. -CONFIG_FEC_MXC_PHYADDR +CFG_FEC_MXC_PHYADDR Optional, selects the exact phy address that should be connected and function fecmxc_initialize will try to initialize it. diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 9cb235ad5e3..ab52cc119f4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1086,8 +1086,8 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) int addr; addr = device_get_phy_addr(priv, dev); -#ifdef CONFIG_FEC_MXC_PHYADDR - addr = CONFIG_FEC_MXC_PHYADDR; +#ifdef CFG_FEC_MXC_PHYADDR + addr = CFG_FEC_MXC_PHYADDR; #endif phydev = phy_connect(priv->bus, addr, dev, priv->interface); diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index a6e9d2bb65f..be1478ea8b6 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -26,7 +26,7 @@ /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 #ifdef CONFIG_IMX_HAB #define HAB_EXTRA_SETTINGS \ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 63afa6e1896..19c7fca03b2 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -20,7 +20,7 @@ /* ENET1 connects to base board and MUX with ESAI */ #define CFG_FEC_ENET_DEV 1 -#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CFG_FEC_MXC_PHYADDR 0x0 /* EEPROM */ #define EEPROM_I2C_BUS 0 /* I2C0 */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 263981860e8..caa1498acea 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -118,6 +118,6 @@ #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ /* Networking */ -#define CONFIG_FEC_MXC_PHYADDR -1 +#define CFG_FEC_MXC_PHYADDR -1 #endif /* __CGTQMX8_H */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 2d56d37f06f..cde7d3c891a 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -13,7 +13,7 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* Network */ -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 /* ENET1 */ #define IMX_FEC_BASE ENET_IPS_BASE_ADDR diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index c66cf721870..47b76c9371e 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -132,7 +132,7 @@ /* APBH DMA is required for NAND support */ /* Ethernet */ -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 /* USB */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 0df61916b7d..121b34ae96d 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -19,7 +19,7 @@ /* Ethernet Configs */ -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 #define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index b6006c021d5..162b0b8a69b 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -40,7 +40,7 @@ /* MMC */ /* Ethernet */ -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 /* USB */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 00ce7fb62a9..7785bdc7cbe 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -136,7 +136,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index d28f3f1972b..c364e06dc45 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -61,6 +61,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 #endif diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index c6e3b105a8a..1fea5b72deb 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -13,7 +13,7 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 #define PHY_ANEG_TIMEOUT 20000 diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index c3abcee40e8..bbbd91776fe 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -14,7 +14,7 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 #define DWC_NET_PHYADDR 1 diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index ed4da0e69b5..38ae5f13702 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -39,7 +39,7 @@ /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 4 +#define CFG_FEC_MXC_PHYADDR 4 #define PHY_ANEG_TIMEOUT 20000 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index c40448715f8..d9ce5d5d0f1 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -24,7 +24,7 @@ /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 #endif #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 8fed3e31964..eb7059f0648 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -21,7 +21,7 @@ /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 #endif #define CONFIG_MFG_ENV_SETTINGS \ diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 30dd5af03b0..b7397f6038f 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -21,7 +21,7 @@ #if defined(CONFIG_FEC_MXC) #define PHY_ANEG_TIMEOUT 20000 -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 #endif #ifdef CONFIG_DISTRO_DEFAULTS diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index d909bbbbcfd..4dd51c7f1d7 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -25,7 +25,7 @@ /* ENET1 Config */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 #define PHY_ANEG_TIMEOUT 20000 diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 7200c69bd9e..0b8781d7bf3 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -102,7 +102,7 @@ #ifdef CONFIG_CMD_NET #define CFG_FEC_ENET_DEV 0 -#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CFG_FEC_MXC_PHYADDR 0x0 #endif #endif diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 0deb7672f9e..de6928d2973 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -54,7 +54,7 @@ * Ethernet on SOC (FEC) */ #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CFG_FEC_MXC_PHYADDR 0x0 #endif #define CFG_SYS_RTC_BUS_NUM 1 /* I2C2 */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 436f5f0059d..6cc49378fed 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -31,7 +31,7 @@ #define CFG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } /* Ethernet Configuration */ -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200 quiet\0" \ diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index ef2111cd20a..1cd0b3cf737 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -17,7 +17,7 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 #define PHY_ANEG_TIMEOUT 20000 #endif diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 9d8737c1942..3399cdd16fa 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -93,7 +93,7 @@ /* Network */ #define IMX_FEC_BASE ENET2_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CFG_FEC_MXC_PHYADDR 0x0 #ifdef CONFIG_CMD_USB #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 8372f979dc8..c99d99abc17 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -115,7 +115,7 @@ /* Network */ -#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CFG_FEC_MXC_PHYADDR 0x1 #ifdef CONFIG_CMD_USB #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index efc599f37a6..5e3695ecc97 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -124,9 +124,9 @@ #define CFG_FEC_ENET_DEV 1 #if (CFG_FEC_ENET_DEV == 0) -#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CFG_FEC_MXC_PHYADDR 0x2 #elif (CFG_FEC_ENET_DEV == 1) -#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CFG_FEC_MXC_PHYADDR 0x1 #endif #endif diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 496a3164f40..aca15be64b1 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -18,7 +18,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 6 +#define CFG_FEC_MXC_PHYADDR 6 /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 979512c0a09..4b47e4fbb37 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -33,7 +33,7 @@ #define CONFIG_MXC_USB_FLAGS 0 #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CFG_FEC_MXC_PHYADDR 0x1 #endif #define CFG_FEC_ENET_DEV 1 diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 66258a3ab73..e1f7b700319 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -98,6 +98,6 @@ /* Environment organization */ /* Ethernet Configuration */ -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 #endif /* __CONFIG_H * */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 45fc6126c87..1cb8fa63e72 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -15,7 +15,7 @@ /* Network support */ -#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CFG_FEC_MXC_PHYADDR 0x1 #define CONFIG_MXC_UART_BASE UART6_BASE_ADDR diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index ac25991703f..1d8709180c8 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -21,7 +21,7 @@ /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 #endif /* Initial environment variables */ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index e1328056351..3418d4e2b55 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -66,7 +66,7 @@ #endif #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CFG_FEC_MXC_PHYADDR 0x1 #endif #endif diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h index 899c218727f..a5f14dc4267 100644 --- a/include/configs/tqma6_mba6.h +++ b/include/configs/tqma6_mba6.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_TQMA6_MBA6_H #define __CONFIG_TQMA6_MBA6_H -#define CONFIG_FEC_MXC_PHYADDR 0x03 +#define CFG_FEC_MXC_PHYADDR 0x03 #define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 4d8839b6e60..34c9b6a2f97 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -7,7 +7,7 @@ #define __CONFIG_TQMA6_WRU4_H /* Ethernet */ -#define CONFIG_FEC_MXC_PHYADDR 0x01 +#define CFG_FEC_MXC_PHYADDR 0x01 /* UART */ #define CONFIG_MXC_UART_BASE UART4_BASE diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 0e0b3a7b594..d10b88f1575 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -21,7 +21,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 /* I2C Configs */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 1a71b300fc5..c84353ebea6 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -34,7 +34,7 @@ #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* Network */ -#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CFG_FEC_MXC_PHYADDR 0x0 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 13f0ee62b89..96996ac1f0f 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -32,7 +32,7 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CFG_FEC_ENET_DEV 0 -#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CFG_FEC_MXC_PHYADDR 0x0 #define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ -- cgit v1.3.1 From 8938f59d545ab6e4ca0f265b008252822e747d30 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:54 -0500 Subject: global: Migrate CONFIG_FLASH_BR_PRELIM to CFG Perform a simple rename of CONFIG_FLASH_BR_PRELIM to CFG_FLASH_BR_PRELIM Signed-off-by: Tom Rini --- include/configs/p1_p2_rdb_pc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index a353c16f74b..f328eda416e 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -188,7 +188,7 @@ #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \ +#define CFG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \ | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 -- cgit v1.3.1 From c20d7cc95c512c7a57720c1481619db7baa4a263 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:55 -0500 Subject: global: Migrate CONFIG_FLASH_OR_PRELIM to CFG Perform a simple rename of CONFIG_FLASH_OR_PRELIM to CFG_FLASH_OR_PRELIM Signed-off-by: Tom Rini --- include/configs/p1_p2_rdb_pc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index f328eda416e..41e7f53bd57 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -191,7 +191,7 @@ #define CFG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \ | BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 +#define CFG_FLASH_OR_PRELIM 0xfc000ff7 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} -- cgit v1.3.1 From e3e4efc04f8f49feb9486f4b5a8a28c917568718 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:58 -0500 Subject: global: Migrate CONFIG_FSL_PMIC_BITLEN to CFG Perform a simple rename of CONFIG_FSL_PMIC_BITLEN to CFG_FSL_PMIC_BITLEN Signed-off-by: Tom Rini --- drivers/power/power_fsl.c | 2 +- include/configs/mx51evk.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index 9bb7e39f2cc..eace4dd7e43 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -42,7 +42,7 @@ int pmic_init(unsigned char bus) p->hw.spi.cs = CONFIG_FSL_PMIC_CS; p->hw.spi.clk = CONFIG_FSL_PMIC_CLK; p->hw.spi.mode = CONFIG_FSL_PMIC_MODE; - p->hw.spi.bitlen = CONFIG_FSL_PMIC_BITLEN; + p->hw.spi.bitlen = CFG_FSL_PMIC_BITLEN; p->hw.spi.flags = SPI_XFER_BEGIN | SPI_XFER_END; p->hw.spi.prepare_tx = pmic_spi_prepare_tx; #elif defined(CONFIG_POWER_I2C) diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 8ab1ee79a79..d4cca8d516a 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -25,7 +25,7 @@ #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 2500000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 +#define CFG_FSL_PMIC_BITLEN 32 /* * MMC Configs -- cgit v1.3.1 From eaaca4245e610e90afae88a70307535a48fefcb5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:59 -0500 Subject: global: Migrate CONFIG_FSL_PMIC_BUS to CFG Perform a simple rename of CONFIG_FSL_PMIC_BUS to CFG_FSL_PMIC_BUS Signed-off-by: Tom Rini --- board/freescale/mx51evk/mx51evk.c | 2 +- include/configs/mx51evk.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 86364acf8ca..95edb359944 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -86,7 +86,7 @@ static void power_init(void) struct pmic *p; int ret; - ret = pmic_init(CONFIG_FSL_PMIC_BUS); + ret = pmic_init(CFG_FSL_PMIC_BUS); if (ret) return; diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index d4cca8d516a..1aaa76240de 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -21,7 +21,7 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* PMIC Controller */ -#define CONFIG_FSL_PMIC_BUS 0 +#define CFG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 2500000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -- cgit v1.3.1 From 3a8be4da79b0aafbfff1e1655ac89f9ab4cc4fcc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:00 -0500 Subject: global: Migrate CONFIG_FSL_PMIC_CLK to CFG Perform a simple rename of CONFIG_FSL_PMIC_CLK to CFG_FSL_PMIC_CLK Signed-off-by: Tom Rini --- drivers/power/power_fsl.c | 2 +- include/configs/mx51evk.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index eace4dd7e43..a576d1570b1 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -40,7 +40,7 @@ int pmic_init(unsigned char bus) #if defined(CONFIG_POWER_SPI) p->interface = PMIC_SPI; p->hw.spi.cs = CONFIG_FSL_PMIC_CS; - p->hw.spi.clk = CONFIG_FSL_PMIC_CLK; + p->hw.spi.clk = CFG_FSL_PMIC_CLK; p->hw.spi.mode = CONFIG_FSL_PMIC_MODE; p->hw.spi.bitlen = CFG_FSL_PMIC_BITLEN; p->hw.spi.flags = SPI_XFER_BEGIN | SPI_XFER_END; diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 1aaa76240de..ee0782ebfeb 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -23,7 +23,7 @@ /* PMIC Controller */ #define CFG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 2500000 +#define CFG_FSL_PMIC_CLK 2500000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CFG_FSL_PMIC_BITLEN 32 -- cgit v1.3.1 From f200d710d83a78e6309d88c365fc33cd322015df Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:01 -0500 Subject: global: Migrate CONFIG_FSL_PMIC_CS to CFG Perform a simple rename of CONFIG_FSL_PMIC_CS to CFG_FSL_PMIC_CS Signed-off-by: Tom Rini --- drivers/power/power_fsl.c | 2 +- include/configs/mx51evk.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index a576d1570b1..9ead212f380 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -39,7 +39,7 @@ int pmic_init(unsigned char bus) #if defined(CONFIG_POWER_SPI) p->interface = PMIC_SPI; - p->hw.spi.cs = CONFIG_FSL_PMIC_CS; + p->hw.spi.cs = CFG_FSL_PMIC_CS; p->hw.spi.clk = CFG_FSL_PMIC_CLK; p->hw.spi.mode = CONFIG_FSL_PMIC_MODE; p->hw.spi.bitlen = CFG_FSL_PMIC_BITLEN; diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index ee0782ebfeb..15bc4c706fd 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -22,7 +22,7 @@ /* PMIC Controller */ #define CFG_FSL_PMIC_BUS 0 -#define CONFIG_FSL_PMIC_CS 0 +#define CFG_FSL_PMIC_CS 0 #define CFG_FSL_PMIC_CLK 2500000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CFG_FSL_PMIC_BITLEN 32 -- cgit v1.3.1 From 193d7ab1e3396bac10f00d4b9b2d8dab6158390c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:02 -0500 Subject: global: Migrate CONFIG_FSL_PMIC_MODE to CFG Perform a simple rename of CONFIG_FSL_PMIC_MODE to CFG_FSL_PMIC_MODE Signed-off-by: Tom Rini --- drivers/power/power_fsl.c | 2 +- include/configs/mx51evk.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index 9ead212f380..9dc930fb305 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -41,7 +41,7 @@ int pmic_init(unsigned char bus) p->interface = PMIC_SPI; p->hw.spi.cs = CFG_FSL_PMIC_CS; p->hw.spi.clk = CFG_FSL_PMIC_CLK; - p->hw.spi.mode = CONFIG_FSL_PMIC_MODE; + p->hw.spi.mode = CFG_FSL_PMIC_MODE; p->hw.spi.bitlen = CFG_FSL_PMIC_BITLEN; p->hw.spi.flags = SPI_XFER_BEGIN | SPI_XFER_END; p->hw.spi.prepare_tx = pmic_spi_prepare_tx; diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 15bc4c706fd..740e357e00e 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -24,7 +24,7 @@ #define CFG_FSL_PMIC_BUS 0 #define CFG_FSL_PMIC_CS 0 #define CFG_FSL_PMIC_CLK 2500000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) +#define CFG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CFG_FSL_PMIC_BITLEN 32 /* -- cgit v1.3.1 From da495570030b07483af1d84eaba995b9bb43de3f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:03 -0500 Subject: global: Migrate CONFIG_FSL_SERDES1 to CFG Perform a simple rename of CONFIG_FSL_SERDES1 to CFG_FSL_SERDES1 Signed-off-by: Tom Rini --- board/freescale/mpc837xerdb/mpc837xerdb.c | 4 ++-- include/configs/MPC837XERDB.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 4a145540265..9c08a2bfef0 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -146,7 +146,7 @@ int board_early_init_f(void) /* we check only part num, and don't look for CPU revisions */ switch (PARTID_NO_E(spridr)) { case SPR_8377: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); @@ -156,7 +156,7 @@ int board_early_init_f(void) FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8379: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index fad161597e6..9fc12dabb5c 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -149,7 +149,7 @@ #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) /* SERDES */ -#define CONFIG_FSL_SERDES1 0xe3000 +#define CFG_FSL_SERDES1 0xe3000 #define CONFIG_FSL_SERDES2 0xe3100 /* I2C */ -- cgit v1.3.1 From 315390e4674e8cff60becca9aa882570d780d8ec Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:04 -0500 Subject: global: Migrate CONFIG_FSL_SERDES2 to CFG Perform a simple rename of CONFIG_FSL_SERDES2 to CFG_FSL_SERDES2 Signed-off-by: Tom Rini --- board/freescale/mpc837xerdb/mpc837xerdb.c | 6 +++--- include/configs/MPC837XERDB.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 9c08a2bfef0..8b1bfe0a9f9 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -148,17 +148,17 @@ int board_early_init_f(void) case SPR_8377: fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8378: - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8379: fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, + fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; default: diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 9fc12dabb5c..07c989d9890 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -150,7 +150,7 @@ /* SERDES */ #define CFG_FSL_SERDES1 0xe3000 -#define CONFIG_FSL_SERDES2 0xe3100 +#define CFG_FSL_SERDES2 0xe3100 /* I2C */ #define CFG_SYS_I2C_NOPROBES { {0, 0x51} } -- cgit v1.3.1 From e06b9b8d75f3f367db115fbcd902ee2d22ddcdba Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:08 -0500 Subject: global: Migrate CONFIG_I2C_MULTI_BUS to CFG Perform a simple rename of CONFIG_I2C_MULTI_BUS to CFG_I2C_MULTI_BUS Signed-off-by: Tom Rini --- README | 2 +- include/configs/omap3_beagle.h | 2 +- include/configs/sniper.h | 2 +- include/configs/tqma6.h | 2 +- include/i2c.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/README b/README index 84086764d81..05618352fa9 100644 --- a/README +++ b/README @@ -955,7 +955,7 @@ The following options need to be configured: You should define these to the GPIO value as given directly to the generic GPIO functions. - CONFIG_I2C_MULTI_BUS + CFG_I2C_MULTI_BUS This option allows the use of multiple I2C buses, each of which must have a controller. At any point in time, only one bus is diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index efeb7bf1007..af7cb3513f8 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -29,7 +29,7 @@ #endif /* CONFIG_MTD_RAW_NAND */ /* Enable Multi Bus support for I2C */ -#define CONFIG_I2C_MULTI_BUS +#define CFG_I2C_MULTI_BUS /* DSS Support */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index eaee8dd3739..45a3102aeee 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -38,7 +38,7 @@ * I2C */ -#define CONFIG_I2C_MULTI_BUS +#define CFG_I2C_MULTI_BUS /* * Input diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 14d7730f67b..cb5f7fc25af 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -28,7 +28,7 @@ #define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K /* I2C Configs */ -#define CONFIG_I2C_MULTI_BUS +#define CFG_I2C_MULTI_BUS #if !defined(CONFIG_DM_PMIC) #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 diff --git a/include/i2c.h b/include/i2c.h index 51390f8fd84..3811b26c08e 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -930,7 +930,7 @@ unsigned int i2c_get_bus_speed(void); * only for backwardcompatibility, should go away if we switched * completely to new multibus support. */ -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CFG_I2C_MULTI_BUS) # if !defined(CFG_SYS_MAX_I2C_BUS) # define CFG_SYS_MAX_I2C_BUS 2 # endif -- cgit v1.3.1 From 45ede979e86573e8b9362ceb1bfa9c397979ae1a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:09 -0500 Subject: global: Migrate CONFIG_I2C_MVTWSI_BASE0 to CFG Perform a simple rename of CONFIG_I2C_MVTWSI_BASE0 to CFG_I2C_MVTWSI_BASE0 Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-sunxi/i2c.h | 2 +- arch/arm/mach-kirkwood/include/mach/config.h | 2 +- drivers/i2c/mvtwsi.c | 6 +++--- include/configs/db-88f6720.h | 2 +- include/configs/db-88f6820-gp.h | 2 +- include/configs/db-mv784mp-gp.h | 2 +- include/configs/ds414.h | 2 +- include/configs/maxbcm.h | 2 +- include/configs/theadorable.h | 2 +- 9 files changed, 11 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index 241b44928a9..2c2d6b7d31d 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -8,7 +8,7 @@ #include #ifdef CONFIG_I2C0_ENABLE -#define CONFIG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE +#define CFG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE #endif #ifdef CONFIG_I2C1_ENABLE #define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index a6de7676294..fbef9c99b1d 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -24,7 +24,7 @@ #include -#define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 KW_TWSI_BASE #define MV_UART_CONSOLE_BASE KW_UART0_BASE #define MV_SATA_BASE KW_SATA_BASE #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index a9c7d6e1bc2..076525d6c4d 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -197,9 +197,9 @@ inline uint calc_tick(uint speed) static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) { switch (adap->hwadapnr) { -#ifdef CONFIG_I2C_MVTWSI_BASE0 +#ifdef CFG_I2C_MVTWSI_BASE0 case 0: - return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0; + return (struct mvtwsi_registers *)CFG_I2C_MVTWSI_BASE0; #endif #ifdef CONFIG_I2C_MVTWSI_BASE1 case 1: @@ -737,7 +737,7 @@ static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, 10000); } -#ifdef CONFIG_I2C_MVTWSI_BASE0 +#ifdef CFG_I2C_MVTWSI_BASE0 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe, twsi_i2c_read, twsi_i2c_write, twsi_i2c_set_bus_speed, diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index ef9c457e102..54de2d0d833 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -17,7 +17,7 @@ */ /* I2C */ -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* USB/EHCI configuration */ diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 6dbf582d733..2cbe4eb440b 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -11,7 +11,7 @@ */ /* I2C */ -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* Environment in SPI NOR flash */ diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index bf8b35102ad..5c6d7fa1b77 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -13,7 +13,7 @@ */ /* I2C */ -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* USB/EHCI configuration */ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index e69883ba73b..9446acba792 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -17,7 +17,7 @@ */ /* I2C */ -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* * mv-common.h should be defined after CMD configs since it used them diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 5ad945b5589..413597e09b2 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -19,7 +19,7 @@ */ /* I2C */ -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* SPI NOR flash default params, used by sf commands */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 9722b0db72a..412698d3fe9 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -25,7 +25,7 @@ */ /* I2C */ -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE /* USB/EHCI configuration */ -- cgit v1.3.1 From 35661f86eb0e647953d6a588059d1387b5be5ae5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:10 -0500 Subject: global: Migrate CONFIG_I2C_MVTWSI_BASE1 to CFG Perform a simple rename of CONFIG_I2C_MVTWSI_BASE1 to CFG_I2C_MVTWSI_BASE1 Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-sunxi/i2c.h | 2 +- drivers/i2c/mvtwsi.c | 6 +++--- include/configs/theadorable.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index 2c2d6b7d31d..e3dcfdf3708 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -11,7 +11,7 @@ #define CFG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE #endif #ifdef CONFIG_I2C1_ENABLE -#define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE +#define CFG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE #endif #ifdef CONFIG_R_I2C_ENABLE #define CONFIG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index 076525d6c4d..2822749971a 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -201,9 +201,9 @@ static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) case 0: return (struct mvtwsi_registers *)CFG_I2C_MVTWSI_BASE0; #endif -#ifdef CONFIG_I2C_MVTWSI_BASE1 +#ifdef CFG_I2C_MVTWSI_BASE1 case 1: - return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1; + return (struct mvtwsi_registers *)CFG_I2C_MVTWSI_BASE1; #endif #ifdef CONFIG_I2C_MVTWSI_BASE2 case 2: @@ -743,7 +743,7 @@ U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe, twsi_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) #endif -#ifdef CONFIG_I2C_MVTWSI_BASE1 +#ifdef CFG_I2C_MVTWSI_BASE1 U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe, twsi_i2c_read, twsi_i2c_write, twsi_i2c_set_bus_speed, diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 412698d3fe9..2ce92845f1c 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -26,7 +26,7 @@ /* I2C */ #define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE +#define CFG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE /* USB/EHCI configuration */ -- cgit v1.3.1 From cdbf8459d017143dba1e798fecbd1046f98a7ece Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:11 -0500 Subject: global: Migrate CONFIG_ICS307_REFCLK_HZ to CFG Perform a simple rename of CONFIG_ICS307_REFCLK_HZ to CFG_ICS307_REFCLK_HZ Signed-off-by: Tom Rini --- board/freescale/common/ics307_clk.c | 4 ++-- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c index 01662d36e9f..5f95571d24c 100644 --- a/board/freescale/common/ics307_clk.c +++ b/board/freescale/common/ics307_clk.c @@ -50,7 +50,7 @@ static u8 ics307_s_to_od[] = { */ unsigned long ics307_sysclk_calculator(unsigned long out_freq) { - const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; + const unsigned long input_freq = CFG_ICS307_REFCLK_HZ; unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od; unsigned long tmp_out, diff, result = 0; int found = 0; @@ -101,7 +101,7 @@ unsigned long ics307_sysclk_calculator(unsigned long out_freq) */ static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) { - const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; + const unsigned long input_freq = CFG_ICS307_REFCLK_HZ; unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); unsigned long rdw = cw2 & 0x7F; unsigned long od = ics307_s_to_od[cw0 & 0x7]; diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 7f332cf2e3b..3b98d25aa47 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -13,7 +13,7 @@ #include -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ +#define CFG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ /* High Level Configuration Options */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index d6dd9c07b73..60c2947bfc1 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -13,7 +13,7 @@ #include -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ +#define CFG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ /* High Level Configuration Options */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 22cbf92efb8..01a9f43cbae 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -12,7 +12,7 @@ #include -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ +#define CFG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #ifdef CONFIG_RAMBOOT_PBL #ifndef CONFIG_SDCARD -- cgit v1.3.1 From e6014294dd5930f3573b9b5883349b209df6f3e2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:12 -0500 Subject: global: Migrate CONFIG_IMX6_PWM_PER_CLK to CFG Perform a simple rename of CONFIG_IMX6_PWM_PER_CLK to CFG_IMX6_PWM_PER_CLK Signed-off-by: Tom Rini --- drivers/pwm/pwm-imx.c | 2 +- include/configs/vining_2000.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index 9b8a8c189d0..8fbb40cc276 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -76,7 +76,7 @@ int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c, * value here as a define. Replace it when we have the clock * framework. */ - c = CONFIG_IMX6_PWM_PER_CLK; + c = CFG_IMX6_PWM_PER_CLK; c = c * period_ns; do_div(c, 1000000000); *period_c = c; diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index c84353ebea6..cdd2eeef0ac 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -43,7 +43,7 @@ #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) #endif -#define CONFIG_IMX6_PWM_PER_CLK 66000000 +#define CFG_IMX6_PWM_PER_CLK 66000000 #ifdef CONFIG_ENV_IS_IN_MMC /* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */ -- cgit v1.3.1 From 7b5f75cffabaa475add3c2f66d5ca0aa95588b5a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:13 -0500 Subject: global: Migrate CONFIG_IRAM_BASE to CFG Perform a simple rename of CONFIG_IRAM_BASE to CFG_IRAM_BASE Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-rockchip/bootrom.h | 2 +- include/configs/px30_common.h | 2 +- include/configs/rk3066_common.h | 2 +- include/configs/rk3128_common.h | 2 +- include/configs/rk3188_common.h | 2 +- include/configs/rk322x_common.h | 2 +- include/configs/rk3288_common.h | 2 +- include/configs/rk3308_common.h | 2 +- include/configs/rk3328_common.h | 2 +- include/configs/rk3368_common.h | 2 +- include/configs/rk3399_common.h | 2 +- include/configs/rk3568_common.h | 2 +- include/configs/rv1108_common.h | 2 +- 13 files changed, 13 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index 0da78f30b61..4276a0f6811 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -57,6 +57,6 @@ extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1]; /** * Locations of the boot-device identifier in SRAM */ -#define BROM_BOOTSOURCE_ID_ADDR (CONFIG_IRAM_BASE + 0x10) +#define BROM_BOOTSOURCE_ID_ADDR (CFG_IRAM_BASE + 0x10) #endif diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 003686930a4..3f1595cdc95 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -9,7 +9,7 @@ #include "rockchip-common.h" /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ -#define CONFIG_IRAM_BASE 0xff020000 +#define CFG_IRAM_BASE 0xff020000 #define GICD_BASE 0xff131000 #define GICC_BASE 0xff132000 diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index c4758e148ba..1a6d3678df3 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -9,7 +9,7 @@ #include #include "rockchip-common.h" -#define CONFIG_IRAM_BASE 0x10080000 +#define CFG_IRAM_BASE 0x10080000 #define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (1024UL << 20UL) diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 5b0ec370004..8aa17bfbd36 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -10,7 +10,7 @@ #define CFG_SYS_HZ_CLOCK 24000000 -#define CONFIG_IRAM_BASE 0x10080000 +#define CFG_IRAM_BASE 0x10080000 /* RAW SD card / eMMC locations. */ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 58f491c2f32..ac9195672fb 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -9,7 +9,7 @@ #include #include "rockchip-common.h" -#define CONFIG_IRAM_BASE 0x10080000 +#define CFG_IRAM_BASE 0x10080000 /* spl size 32kb sram - 2kb bootrom */ diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index b95268df87c..fcaf9c52c4b 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -10,7 +10,7 @@ #define CFG_SYS_HZ_CLOCK 24000000 -#define CONFIG_IRAM_BASE 0x10080000 +#define CFG_IRAM_BASE 0x10080000 #define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index d3b8a5150f6..5f29432be10 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -11,7 +11,7 @@ #define CFG_SYS_HZ_CLOCK 24000000 -#define CONFIG_IRAM_BASE 0xff700000 +#define CFG_IRAM_BASE 0xff700000 /* RAW SD card / eMMC locations. */ diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index bc03e113fef..55a0dfecb21 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -8,7 +8,7 @@ #include "rockchip-common.h" -#define CONFIG_IRAM_BASE 0xfff80000 +#define CFG_IRAM_BASE 0xfff80000 #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 85d2186f23e..fadcb93a5f7 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -8,7 +8,7 @@ #include "rockchip-common.h" -#define CONFIG_IRAM_BASE 0xff090000 +#define CFG_IRAM_BASE 0xff090000 /* FAT sd card locations. */ #define CFG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 17636250510..9aa256b5959 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -14,7 +14,7 @@ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 -#define CONFIG_IRAM_BASE 0xff8c0000 +#define CFG_IRAM_BASE 0xff8c0000 #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 2278b6215d4..95cb27c8951 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -8,7 +8,7 @@ #include "rockchip-common.h" -#define CONFIG_IRAM_BASE 0xff8c0000 +#define CFG_IRAM_BASE 0xff8c0000 /* FAT sd card locations. */ #define CFG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index 750f16d0399..ae360105d50 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -8,7 +8,7 @@ #include "rockchip-common.h" -#define CONFIG_IRAM_BASE 0xfdcc0000 +#define CFG_IRAM_BASE 0xfdcc0000 #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000 diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 6e17b23b624..63551b47e20 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -8,7 +8,7 @@ #include #include "rockchip-common.h" -#define CONFIG_IRAM_BASE 0x10080000 +#define CFG_IRAM_BASE 0x10080000 #define CFG_SYS_TIMER_RATE (24 * 1000 * 1000) /* TIMER1,initialized by ddr initialize code */ -- cgit v1.3.1 From 7201b769784fd474f7e24c3fd2048588c69fb285 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:14 -0500 Subject: global: Migrate CONFIG_IRAM_TOP to CFG Perform a simple rename of CONFIG_IRAM_TOP to CFG_IRAM_TOP Signed-off-by: Tom Rini --- arch/arm/mach-exynos/lowlevel_init.c | 2 +- arch/arm/mach-exynos/sec_boot.S | 2 +- include/configs/exynos5420-common.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 1ff5fcac1b3..9225d2cc1f2 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -51,7 +51,7 @@ enum { #ifdef CONFIG_EXYNOS5420 /* Address for relocating helper code (Last 4 KB of IRAM) */ -#define EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000) +#define EXYNOS_RELOCATE_CODE_BASE (CFG_IRAM_TOP - 0x1000) /* * Power up secondary CPUs. diff --git a/arch/arm/mach-exynos/sec_boot.S b/arch/arm/mach-exynos/sec_boot.S index 40c07209e47..1303544d83b 100644 --- a/arch/arm/mach-exynos/sec_boot.S +++ b/arch/arm/mach-exynos/sec_boot.S @@ -21,7 +21,7 @@ relocate_wait_code: .ltorg /* * Secondary core waits here until Primary wake it up. - * Below code is copied to (CONFIG_IRAM_TOP - 0x1000) + * Below code is copied to (CFG_IRAM_TOP - 0x1000) * This is a workaround code which is supposed to act as a * substitute/supplement to the iROM code. * diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 934a4ef9d1f..99ab1a174f7 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_EXYNOS5420_H #define __CONFIG_EXYNOS5420_H -#define CONFIG_IRAM_TOP 0x02074000 +#define CFG_IRAM_TOP 0x02074000 #define CONFIG_PHY_IRAM_BASE 0x02020000 -- cgit v1.3.1 From 21bd204239ff6cf62d6aca1f8ac4941702030e51 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:25 -0500 Subject: global: Migrate CONFIG_KSNET_CPSW_NUM_PORTS to CFG Perform a simple rename of CONFIG_KSNET_CPSW_NUM_PORTS to CFG_KSNET_CPSW_NUM_PORTS Signed-off-by: Tom Rini --- arch/arm/include/asm/ti-common/keystone_net.h | 2 +- include/configs/k2e_evm.h | 2 +- include/configs/k2g_evm.h | 2 +- include/configs/k2hk_evm.h | 2 +- include/configs/k2l_evm.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index 0852ce80a64..21cac6ea312 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -117,7 +117,7 @@ struct mac_sl_cfg { #define CPSW_CTL_VLAN_AWARE BIT(1) #define CPSW_CTL_FIFO_LOOPBACK BIT(0) -#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS +#define DEVICE_CPSW_NUM_PORTS CFG_KSNET_CPSW_NUM_PORTS #define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1) #ifdef CONFIG_KSNET_NETCP_V1_0 diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 1283f450b32..929c9a26de1 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -37,6 +37,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* Network */ -#define CONFIG_KSNET_CPSW_NUM_PORTS 9 +#define CFG_KSNET_CPSW_NUM_PORTS 9 #endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index fd3708ba81a..d0634a99f49 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -51,7 +51,7 @@ "name_fs=arago-base-tisdk-image-k2g-evm.cpio\0" /* Network */ -#define CONFIG_KSNET_CPSW_NUM_PORTS 2 +#define CFG_KSNET_CPSW_NUM_PORTS 2 #define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */ #define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 36e3c59d1c5..05b4a3c204d 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -37,6 +37,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* Network */ -#define CONFIG_KSNET_CPSW_NUM_PORTS 5 +#define CFG_KSNET_CPSW_NUM_PORTS 5 #endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index cb7b0367810..b1b839b5043 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -37,6 +37,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* Network */ -#define CONFIG_KSNET_CPSW_NUM_PORTS 5 +#define CFG_KSNET_CPSW_NUM_PORTS 5 #endif /* __CONFIG_K2L_EVM_H */ -- cgit v1.3.1 From f060d1885c4468f8a2723cd172c2144259b638f0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:26 -0500 Subject: global: Migrate CONFIG_KSNET_MAC_ID_BASE to CFG Perform a simple rename of CONFIG_KSNET_MAC_ID_BASE to CFG_KSNET_MAC_ID_BASE Signed-off-by: Tom Rini --- arch/arm/include/asm/ti-common/keystone_net.h | 2 +- include/configs/ti_armv7_keystone2.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index 21cac6ea312..f191c909f41 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -49,7 +49,7 @@ #define KEYSTONE2_EMAC_GIG_ENABLE -#define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE +#define MAC_ID_BASE_ADDR CFG_KSNET_MAC_ID_BASE /* MDIO module input frequency */ #ifdef CONFIG_SOC_K2G diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 479ab46e4ed..e46d635ca03 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -47,7 +47,7 @@ #define CFG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) /* Keystone net */ -#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR +#define CFG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE -- cgit v1.3.1 From d4e4bc898b7d14576f0c3b281d0c552954ee0dda Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:27 -0500 Subject: global: Migrate CONFIG_KSNET_NETCP_BASE to CFG Perform a simple rename of CONFIG_KSNET_NETCP_BASE to CFG_KSNET_NETCP_BASE Signed-off-by: Tom Rini --- arch/arm/include/asm/ti-common/keystone_net.h | 8 ++++---- include/configs/ti_armv7_keystone2.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index f191c909f41..bedbcdc8bac 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -18,7 +18,7 @@ /* EMAC */ #ifdef CONFIG_KSNET_NETCP_V1_0 -#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000) +#define GBETH_BASE (CFG_KSNET_NETCP_BASE + 0x00090000) #define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900) #define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300) #define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100) @@ -32,7 +32,7 @@ #elif defined CONFIG_KSNET_NETCP_V1_5 -#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000) +#define GBETH_BASE (CFG_KSNET_NETCP_BASE + 0x00200000) #define CPGMACSL_REG_RX_PRI_MAP 0x020 #define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000) #define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00) @@ -190,14 +190,14 @@ struct mac_sl_cfg { /* PSS */ #ifdef CONFIG_KSNET_NETCP_V1_0 -#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604) +#define DEVICE_PSTREAM_CFG_REG_ADDR (CFG_KSNET_NETCP_BASE + 0x604) #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606 #define hw_config_streaming_switch()\ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR); #elif defined CONFIG_KSNET_NETCP_V1_5 -#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500) +#define DEVICE_PSTREAM_CFG_REG_ADDR (CFG_KSNET_NETCP_BASE + 0x500) #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0 #define hw_config_streaming_switch()\ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index e46d635ca03..c21fabc36ed 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -48,7 +48,7 @@ /* Keystone net */ #define CFG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR -#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE +#define CFG_KSNET_NETCP_BASE KS2_NETCP_BASE #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES -- cgit v1.3.1 From d036606142a0164646ace465a20ba5e632de887e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:28 -0500 Subject: global: Migrate CONFIG_KSNET_SERDES_LANES_PER_SGMII to CFG Perform a simple rename of CONFIG_KSNET_SERDES_LANES_PER_SGMII to CFG_KSNET_SERDES_LANES_PER_SGMII Signed-off-by: Tom Rini --- drivers/net/ti/keystone_net.c | 4 ++-- include/configs/ti_armv7_keystone2.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index 679a0450f1d..114eb854d72 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -372,12 +372,12 @@ static void keystone2_net_serdes_setup(void) { ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, &ks2_serdes_sgmii_156p25mhz, - CONFIG_KSNET_SERDES_LANES_PER_SGMII); + CFG_KSNET_SERDES_LANES_PER_SGMII); #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, &ks2_serdes_sgmii_156p25mhz, - CONFIG_KSNET_SERDES_LANES_PER_SGMII); + CFG_KSNET_SERDES_LANES_PER_SGMII); #endif /* wait till setup */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index c21fabc36ed..cb4ea394eb8 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -51,7 +51,7 @@ #define CFG_KSNET_NETCP_BASE KS2_NETCP_BASE #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE -#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES +#define CFG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES /* EEPROM definitions */ -- cgit v1.3.1 From 81d239aede3ccab6ccdac70478d99d064baabdb0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:29 -0500 Subject: global: Migrate CONFIG_KSNET_SERDES_SGMII2_BASE to CFG Perform a simple rename of CONFIG_KSNET_SERDES_SGMII2_BASE to CFG_KSNET_SERDES_SGMII2_BASE Signed-off-by: Tom Rini --- drivers/net/ti/keystone_net.c | 2 +- include/configs/ti_armv7_keystone2.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index 114eb854d72..90b8821a2ca 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -375,7 +375,7 @@ static void keystone2_net_serdes_setup(void) CFG_KSNET_SERDES_LANES_PER_SGMII); #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) - ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, + ks2_serdes_init(CFG_KSNET_SERDES_SGMII2_BASE, &ks2_serdes_sgmii_156p25mhz, CFG_KSNET_SERDES_LANES_PER_SGMII); #endif diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index cb4ea394eb8..1429faa534e 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -50,7 +50,7 @@ #define CFG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CFG_KSNET_NETCP_BASE KS2_NETCP_BASE #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE -#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE +#define CFG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE #define CFG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES /* EEPROM definitions */ -- cgit v1.3.1 From e9f508cf019ae3056747ee2560b66267de6a6bea Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:30 -0500 Subject: global: Migrate CONFIG_KSNET_SERDES_SGMII_BASE to CFG Perform a simple rename of CONFIG_KSNET_SERDES_SGMII_BASE to CFG_KSNET_SERDES_SGMII_BASE Signed-off-by: Tom Rini --- drivers/net/ti/keystone_net.c | 2 +- include/configs/ti_armv7_keystone2.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index 90b8821a2ca..89b04b6fbda 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -370,7 +370,7 @@ struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { #ifndef CONFIG_SOC_K2G static void keystone2_net_serdes_setup(void) { - ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, + ks2_serdes_init(CFG_KSNET_SERDES_SGMII_BASE, &ks2_serdes_sgmii_156p25mhz, CFG_KSNET_SERDES_LANES_PER_SGMII); diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 1429faa534e..7142d30a599 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -49,7 +49,7 @@ /* Keystone net */ #define CFG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CFG_KSNET_NETCP_BASE KS2_NETCP_BASE -#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE +#define CFG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE #define CFG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE #define CFG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES -- cgit v1.3.1 From 1cd60b3cc021fb8bfa537a393151871515b512b2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:31 -0500 Subject: global: Migrate CONFIG_LEGACY_BOOTCMD_ENV to CFG Perform a simple rename of CONFIG_LEGACY_BOOTCMD_ENV to CFG_LEGACY_BOOTCMD_ENV Signed-off-by: Tom Rini --- include/configs/pic32mzdask.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 60c74732758..0ae4fc55a97 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -52,7 +52,7 @@ "fdt_addr_r=0x89d00000\0" \ "scriptaddr=0x88300000\0" \ -#define CONFIG_LEGACY_BOOTCMD_ENV \ +#define CFG_LEGACY_BOOTCMD_ENV \ "legacy_bootcmd= " \ "if load mmc 0 ${scriptaddr} uEnv.txt; then " \ "env import -tr ${scriptaddr} ${filesize}; " \ @@ -71,7 +71,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ - CONFIG_LEGACY_BOOTCMD_ENV \ + CFG_LEGACY_BOOTCMD_ENV \ BOOTENV #endif /* __PIC32MZDASK_CONFIG_H */ -- cgit v1.3.1 From 77db07ce1c8ca359c500f66d38e0d9d572d214a9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:32 -0500 Subject: global: Migrate CONFIG_LOWPOWER_ADDR to CFG Perform a simple rename of CONFIG_LOWPOWER_ADDR to CFG_LOWPOWER_ADDR Signed-off-by: Tom Rini --- arch/arm/mach-exynos/lowlevel_init.c | 2 +- include/configs/exynos5420-common.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 9225d2cc1f2..02a79962af2 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -161,7 +161,7 @@ static void secondary_cores_configure(void) /* set lowpower flag and address */ writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG); - writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR); + writel((uint32_t)&low_power_start, CFG_LOWPOWER_ADDR); writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE); /* Store jump address for power down */ writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4); diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 99ab1a174f7..164cdb0fa15 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -16,6 +16,6 @@ * Low Power settings */ #define CONFIG_LOWPOWER_FLAG 0x02020028 -#define CONFIG_LOWPOWER_ADDR 0x0202002C +#define CFG_LOWPOWER_ADDR 0x0202002C #endif /* __CONFIG_EXYNOS5420_H */ -- cgit v1.3.1 From 8000ac874c727004958d0fdec250681ba6b236f9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:33 -0500 Subject: global: Migrate CONFIG_LOWPOWER_FLAG to CFG Perform a simple rename of CONFIG_LOWPOWER_FLAG to CFG_LOWPOWER_FLAG Signed-off-by: Tom Rini --- arch/arm/mach-exynos/lowlevel_init.c | 4 ++-- include/configs/exynos5420-common.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 02a79962af2..243b5c80c90 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -73,7 +73,7 @@ static void low_power_start(void) reg_val = readl(EXYNOS5420_SPARE_BASE); if (reg_val != CPU_RST_FLAG_VAL) { - writel(0x0, CONFIG_LOWPOWER_FLAG); + writel(0x0, CFG_LOWPOWER_FLAG); branch_bx(0x0); } @@ -160,7 +160,7 @@ static void secondary_cores_configure(void) writel(0x0, (EXYNOS_RELOCATE_CODE_BASE + 0x1C)); /* set lowpower flag and address */ - writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG); + writel(CPU_RST_FLAG_VAL, CFG_LOWPOWER_FLAG); writel((uint32_t)&low_power_start, CFG_LOWPOWER_ADDR); writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE); /* Store jump address for power down */ diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 164cdb0fa15..bd43efa553c 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -15,7 +15,7 @@ /* * Low Power settings */ -#define CONFIG_LOWPOWER_FLAG 0x02020028 +#define CFG_LOWPOWER_FLAG 0x02020028 #define CFG_LOWPOWER_ADDR 0x0202002C #endif /* __CONFIG_EXYNOS5420_H */ -- cgit v1.3.1 From dff9de5c2c1eb0a4b62f1ea67dee3f0db117bc1a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:34 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY to CFG_LPC32XX_NAND_MLC_BUSY_DELAY Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- include/configs/work_92105.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index a884c65d18b..dd3f35def0f 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -142,7 +142,7 @@ static void lpc32xx_nand_init(void) writel( clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | + clkdiv(CFG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | clkdiv(CONFIG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 010da1531ff..a1ecd8ceef0 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -28,7 +28,7 @@ */ #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 -#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 +#define CFG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 -- cgit v1.3.1 From ea93286e5f068b85dd3a0d05bef534ad86d3d16f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:35 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_MLC_NAND_TA to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_NAND_TA to CFG_LPC32XX_NAND_MLC_NAND_TA Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- include/configs/work_92105.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index dd3f35def0f..cd3831b5ffe 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -143,7 +143,7 @@ static void lpc32xx_nand_init(void) writel( clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | clkdiv(CFG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | + clkdiv(CFG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index a1ecd8ceef0..d345382545e 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -29,7 +29,7 @@ #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 #define CFG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 -#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 +#define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 -- cgit v1.3.1 From ab8c6e370c6407a8b6117d933cc4ece5ad5383be Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:36 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_MLC_RD_HIGH to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_RD_HIGH to CFG_LPC32XX_NAND_MLC_RD_HIGH Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- include/configs/work_92105.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index cd3831b5ffe..388be16e2e7 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -144,7 +144,7 @@ static void lpc32xx_nand_init(void) clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | clkdiv(CFG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | clkdiv(CFG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | + clkdiv(CFG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index d345382545e..3959051a4ca 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -30,7 +30,7 @@ #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 #define CFG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 #define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818 -#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 +#define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 -- cgit v1.3.1 From 3c35c036add440f73cfb24cbfab7098e949c2167 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:37 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_MLC_RD_LOW to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_RD_LOW to CFG_LPC32XX_NAND_MLC_RD_LOW Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- include/configs/work_92105.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index 388be16e2e7..e75ed1f2ae9 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -145,7 +145,7 @@ static void lpc32xx_nand_init(void) clkdiv(CFG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | clkdiv(CFG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | clkdiv(CFG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | + clkdiv(CFG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), &lpc32xx_nand_mlc_registers->time_reg); diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 3959051a4ca..1a4617c5c02 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -31,7 +31,7 @@ #define CFG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 #define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818 #define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000 -#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 +#define CFG_LPC32XX_NAND_MLC_RD_LOW 45454545 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 -- cgit v1.3.1 From 259ec2ce11f47a1a33675e258d81bbe72429945e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:38 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY to CFG_LPC32XX_NAND_MLC_TCEA_DELAY Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- include/configs/work_92105.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index e75ed1f2ae9..088fdb7981d 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -141,7 +141,7 @@ static void lpc32xx_nand_init(void) clk = get_hclk_clk_rate(); writel( - clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | + clkdiv(CFG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | clkdiv(CFG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | clkdiv(CFG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | clkdiv(CFG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 1a4617c5c02..34af515037f 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -27,7 +27,7 @@ * NAND chip timings for FIXME: which one? */ -#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 +#define CFG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 #define CFG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 #define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818 #define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000 -- cgit v1.3.1 From 196690dfdadeb99ee7903e121bce10908b9ec6fb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:39 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_MLC_WR_HIGH to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_WR_HIGH to CFG_LPC32XX_NAND_MLC_WR_HIGH Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- include/configs/work_92105.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index 088fdb7981d..31a9a22ba31 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -146,7 +146,7 @@ static void lpc32xx_nand_init(void) clkdiv(CFG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | clkdiv(CFG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | clkdiv(CFG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | + clkdiv(CFG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), &lpc32xx_nand_mlc_registers->time_reg); } diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 34af515037f..c67a0bb6e1a 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -32,7 +32,7 @@ #define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818 #define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000 #define CFG_LPC32XX_NAND_MLC_RD_LOW 45454545 -#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 +#define CFG_LPC32XX_NAND_MLC_WR_HIGH 40000000 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 /* -- cgit v1.3.1 From 39fa17718f4ccdc252ca96a56186931b4fd6f3fb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:40 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_MLC_WR_LOW to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_WR_LOW to CFG_LPC32XX_NAND_MLC_WR_LOW Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- include/configs/work_92105.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index 31a9a22ba31..28541177609 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -147,7 +147,7 @@ static void lpc32xx_nand_init(void) clkdiv(CFG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | clkdiv(CFG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | clkdiv(CFG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), + clkdiv(CFG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), &lpc32xx_nand_mlc_registers->time_reg); } diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index c67a0bb6e1a..f1a7853a80e 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -33,7 +33,7 @@ #define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000 #define CFG_LPC32XX_NAND_MLC_RD_LOW 45454545 #define CFG_LPC32XX_NAND_MLC_WR_HIGH 40000000 -#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 +#define CFG_LPC32XX_NAND_MLC_WR_LOW 83333333 /* * NAND -- cgit v1.3.1 From c102eb5ca7281dd3b449fd9eaf50e8f8c6b205fd Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:41 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_SLC_RDR_CLKS to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_RDR_CLKS to CFG_LPC32XX_NAND_SLC_RDR_CLKS Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index f4f1b22f5e2..0f12201aa0e 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -130,7 +130,7 @@ static void lpc32xx_nand_init(void) TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) | TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | - TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) | + TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) | TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) | TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP), diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index ab10101f20a..e1789684135 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -45,7 +45,7 @@ #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 -#define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14 +#define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 -- cgit v1.3.1 From bba52ab080f5446fabaf3c98772a2254064a7adf Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:42 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_SLC_RHOLD to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_RHOLD to CFG_LPC32XX_NAND_SLC_RHOLD Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index 0f12201aa0e..1fdc80989fa 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -132,7 +132,7 @@ static void lpc32xx_nand_init(void) TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) | - TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) | + TAC_R_HOLD(hclk / CFG_LPC32XX_NAND_SLC_RHOLD) | TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP), &lpc32xx_nand_slc_regs->tac); } diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index e1789684135..0b815ded732 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -47,7 +47,7 @@ #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 #define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 -#define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 +#define CFG_LPC32XX_NAND_SLC_RHOLD 200000000 #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 /* -- cgit v1.3.1 From 416ef8c7c6c7fb371a3d0acdafbc4c851a229076 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:43 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_SLC_RSETUP to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_RSETUP to CFG_LPC32XX_NAND_SLC_RSETUP Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index 1fdc80989fa..71e8286d1c8 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -133,7 +133,7 @@ static void lpc32xx_nand_init(void) TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) | TAC_R_HOLD(hclk / CFG_LPC32XX_NAND_SLC_RHOLD) | - TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP), + TAC_R_SETUP(hclk / CFG_LPC32XX_NAND_SLC_RSETUP), &lpc32xx_nand_slc_regs->tac); } diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 0b815ded732..72cf031e05d 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -48,7 +48,7 @@ #define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 #define CFG_LPC32XX_NAND_SLC_RHOLD 200000000 -#define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 +#define CFG_LPC32XX_NAND_SLC_RSETUP 50000000 /* * USB -- cgit v1.3.1 From fa0e72a34eeb6b82faa4ac0156fd3e5a21750329 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:44 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_SLC_RWIDTH to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_RWIDTH to CFG_LPC32XX_NAND_SLC_RWIDTH Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index 71e8286d1c8..fb1fb2d7dcc 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -131,7 +131,7 @@ static void lpc32xx_nand_init(void) TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) | TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | - TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) | + TAC_R_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_RWIDTH) | TAC_R_HOLD(hclk / CFG_LPC32XX_NAND_SLC_RHOLD) | TAC_R_SETUP(hclk / CFG_LPC32XX_NAND_SLC_RSETUP), &lpc32xx_nand_slc_regs->tac); diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 72cf031e05d..5ba8c1bb20e 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -46,7 +46,7 @@ #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 #define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14 -#define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 +#define CFG_LPC32XX_NAND_SLC_RWIDTH 66666666 #define CFG_LPC32XX_NAND_SLC_RHOLD 200000000 #define CFG_LPC32XX_NAND_SLC_RSETUP 50000000 -- cgit v1.3.1 From fa32dc7d15c576e7bf1a04c44ac993c05e06a081 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:45 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_SLC_WDR_CLKS to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_WDR_CLKS to CFG_LPC32XX_NAND_SLC_WDR_CLKS Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index fb1fb2d7dcc..7de5c840ed9 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -126,7 +126,7 @@ static void lpc32xx_nand_init(void) &lpc32xx_nand_slc_regs->icr); /* Configure NAND flash timings */ - writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) | + writel(TAC_W_RDY(CFG_LPC32XX_NAND_SLC_WDR_CLKS) | TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) | TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 5ba8c1bb20e..dc16ed84c52 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -41,7 +41,7 @@ /* * NAND chip timings */ -#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14 +#define CFG_LPC32XX_NAND_SLC_WDR_CLKS 14 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 -- cgit v1.3.1 From b0c548273e1e2d20b9b200faae964a0aff348c21 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:46 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_SLC_WHOLD to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_WHOLD to CFG_LPC32XX_NAND_SLC_WHOLD Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index 7de5c840ed9..dee8fd24b94 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -128,7 +128,7 @@ static void lpc32xx_nand_init(void) /* Configure NAND flash timings */ writel(TAC_W_RDY(CFG_LPC32XX_NAND_SLC_WDR_CLKS) | TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | - TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) | + TAC_W_HOLD(hclk / CFG_LPC32XX_NAND_SLC_WHOLD) | TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | TAC_R_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_RWIDTH) | diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index dc16ed84c52..24312c848e2 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -43,7 +43,7 @@ */ #define CFG_LPC32XX_NAND_SLC_WDR_CLKS 14 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 -#define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 +#define CFG_LPC32XX_NAND_SLC_WHOLD 200000000 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 #define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14 #define CFG_LPC32XX_NAND_SLC_RWIDTH 66666666 -- cgit v1.3.1 From 308ed808399b72de9bd947c26426d6a6f53ab28d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:47 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_SLC_WSETUP to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_WSETUP to CFG_LPC32XX_NAND_SLC_WSETUP Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index dee8fd24b94..a070df81d7c 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -129,7 +129,7 @@ static void lpc32xx_nand_init(void) writel(TAC_W_RDY(CFG_LPC32XX_NAND_SLC_WDR_CLKS) | TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | TAC_W_HOLD(hclk / CFG_LPC32XX_NAND_SLC_WHOLD) | - TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | + TAC_W_SETUP(hclk / CFG_LPC32XX_NAND_SLC_WSETUP) | TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | TAC_R_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_RWIDTH) | TAC_R_HOLD(hclk / CFG_LPC32XX_NAND_SLC_RHOLD) | diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 24312c848e2..5719e422da9 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -44,7 +44,7 @@ #define CFG_LPC32XX_NAND_SLC_WDR_CLKS 14 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 #define CFG_LPC32XX_NAND_SLC_WHOLD 200000000 -#define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 +#define CFG_LPC32XX_NAND_SLC_WSETUP 50000000 #define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14 #define CFG_LPC32XX_NAND_SLC_RWIDTH 66666666 #define CFG_LPC32XX_NAND_SLC_RHOLD 200000000 -- cgit v1.3.1 From bd79d3d616dea43b9d6de6f352144709a62a4090 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:48 -0500 Subject: global: Migrate CONFIG_LPC32XX_NAND_SLC_WWIDTH to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_WWIDTH to CFG_LPC32XX_NAND_SLC_WWIDTH Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index a070df81d7c..356f8d9440b 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -127,7 +127,7 @@ static void lpc32xx_nand_init(void) /* Configure NAND flash timings */ writel(TAC_W_RDY(CFG_LPC32XX_NAND_SLC_WDR_CLKS) | - TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | + TAC_W_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_WWIDTH) | TAC_W_HOLD(hclk / CFG_LPC32XX_NAND_SLC_WHOLD) | TAC_W_SETUP(hclk / CFG_LPC32XX_NAND_SLC_WSETUP) | TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 5719e422da9..9cfee381d4a 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -42,7 +42,7 @@ * NAND chip timings */ #define CFG_LPC32XX_NAND_SLC_WDR_CLKS 14 -#define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 +#define CFG_LPC32XX_NAND_SLC_WWIDTH 66666666 #define CFG_LPC32XX_NAND_SLC_WHOLD 200000000 #define CFG_LPC32XX_NAND_SLC_WSETUP 50000000 #define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14 -- cgit v1.3.1 From dd5b58c49129016a02e41d6fda2213888d13c115 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:49 -0500 Subject: global: Migrate CONFIG_MALLOC_F_ADDR to CFG Perform a simple rename of CONFIG_MALLOC_F_ADDR to CFG_MALLOC_F_ADDR Signed-off-by: Tom Rini --- arch/sandbox/cpu/start.c | 2 +- common/init/board_init.c | 2 +- common/spl/spl.c | 4 ++-- doc/arch/sandbox/sandbox.rst | 2 +- include/configs/capricorn-common.h | 2 +- include/configs/cgtqmx8.h | 2 +- include/configs/imx8mm-cl-iot-gate.h | 2 +- include/configs/imx8mm_beacon.h | 2 +- include/configs/imx8mm_data_modul_edm_sbc.h | 2 +- include/configs/imx8mm_evk.h | 2 +- include/configs/imx8mm_icore_mx8mm.h | 2 +- include/configs/imx8mm_venice.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/imx8mq_cm.h | 2 +- include/configs/imx8mq_evk.h | 2 +- include/configs/imx8mq_phanbell.h | 2 +- include/configs/imx8qm_mek.h | 2 +- include/configs/imx8qxp_mek.h | 2 +- include/configs/imx8ulp_evk.h | 2 +- include/configs/imx93_evk.h | 2 +- include/configs/kontron-sl-mx8mm.h | 2 +- include/configs/kontron_pitx_imx8m.h | 2 +- include/configs/kontron_sl28.h | 2 +- include/configs/phycore_imx8mm.h | 2 +- include/configs/pico-imx8mq.h | 2 +- include/configs/sandbox.h | 2 +- include/configs/verdin-imx8mm.h | 2 +- include/configs/verdin-imx8mp.h | 2 +- 28 files changed, 29 insertions(+), 29 deletions(-) (limited to 'include') diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 622df41f54c..234652872ec 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -535,7 +535,7 @@ int sandbox_main(int argc, char *argv[]) } #if CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_base = CONFIG_MALLOC_F_ADDR; + gd->malloc_base = CFG_MALLOC_F_ADDR; #endif #if CONFIG_IS_ENABLED(LOG) gd->default_log_level = state->default_log_level; diff --git a/common/init/board_init.c b/common/init/board_init.c index 6a550261778..96ffb79a986 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -78,7 +78,7 @@ __weak void board_init_f_init_stack_protection(void) ulong board_init_f_alloc_reserve(ulong top) { /* Reserve early malloc arena */ -#ifndef CONFIG_MALLOC_F_ADDR +#ifndef CFG_MALLOC_F_ADDR #if CONFIG_VAL(SYS_MALLOC_F_LEN) top -= CONFIG_VAL(SYS_MALLOC_F_LEN); #endif diff --git a/common/spl/spl.c b/common/spl/spl.c index 1d2e8fda728..4668367b680 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -527,8 +527,8 @@ static int spl_common_init(bool setup_malloc) #if CONFIG_VAL(SYS_MALLOC_F_LEN) if (setup_malloc) { -#ifdef CONFIG_MALLOC_F_ADDR - gd->malloc_base = CONFIG_MALLOC_F_ADDR; +#ifdef CFG_MALLOC_F_ADDR + gd->malloc_base = CFG_MALLOC_F_ADDR; #endif gd->malloc_limit = CONFIG_VAL(SYS_MALLOC_F_LEN); gd->malloc_ptr = 0; diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst index e6d84036516..cd7f8a2cb0d 100644 --- a/doc/arch/sandbox/sandbox.rst +++ b/doc/arch/sandbox/sandbox.rst @@ -615,7 +615,7 @@ Addr Config Usage ======= ======================== =============================== 0 CONFIG_SYS_FDT_LOAD_ADDR Device tree c000 CONFIG_BLOBLIST_ADDR Blob list - 10000 CONFIG_MALLOC_F_ADDR Early memory allocation + 10000 CFG_MALLOC_F_ADDR Early memory allocation f0000 CONFIG_PRE_CON_BUF_ADDR Pre-console buffer 100000 CONFIG_TRACE_EARLY_ADDR Early trace buffer (if enabled). Also used as the SPL load buffer in spl_test_load(). diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 19c7fca03b2..9e7322cdb93 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -14,7 +14,7 @@ /* SPL config */ #ifdef CONFIG_SPL_BUILD -#define CONFIG_MALLOC_F_ADDR 0x00120000 +#define CFG_MALLOC_F_ADDR 0x00120000 #endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index caa1498acea..a6332597384 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -13,7 +13,7 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 -#define CONFIG_MALLOC_F_ADDR 0x00120000 +#define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 7785bdc7cbe..64cdc401d03 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -16,7 +16,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x912000 +#define CFG_MALLOC_F_ADDR 0x912000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index ee524f0e63f..d85ae21e231 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -14,7 +14,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 44d74bb1a78..0723d27ab70 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -11,7 +11,7 @@ #include #ifdef CONFIG_SPL_BUILD -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index c364e06dc45..d5642b96495 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -24,7 +24,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index e718daa07c3..2158b0af74f 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -15,7 +15,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -# define CONFIG_MALLOC_F_ADDR 0x930000 +# define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ #endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index c490e3829f9..5579a05d165 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -14,7 +14,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CFG_MALLOC_F_ADDR 0x930000 #endif /* Enable Distro Boot */ diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 38ae5f13702..e4e24b522fd 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -24,7 +24,7 @@ 0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9) #ifdef CONFIG_SPL_BUILD -#define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before \ +#define CFG_MALLOC_F_ADDR 0x184000 /* malloc f used before \ * GD_FLG_FULL_MALLOC_INIT \ * set \ */ diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index f6f356d27ba..f7ae1b47d06 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -14,7 +14,7 @@ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 +#define CFG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index d9ce5d5d0f1..4b46321e851 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -15,7 +15,7 @@ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 +#define CFG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index eb7059f0648..5158f2cc605 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -14,7 +14,7 @@ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 +#define CFG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 7772e71013e..a25efbb16bd 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -12,7 +12,7 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 -#define CONFIG_MALLOC_F_ADDR 0x00120000 +#define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 669da591fa2..4f55ae49403 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -12,7 +12,7 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 -#define CONFIG_MALLOC_F_ADDR 0x00120000 +#define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index b7397f6038f..d77510e1685 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -12,7 +12,7 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_MALLOC_F_ADDR 0x22040000 +#define CFG_MALLOC_F_ADDR 0x22040000 #endif diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 5cd6492dd50..7b7bef3ca75 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -14,7 +14,7 @@ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_MALLOC_F_ADDR 0x204D0000 +#define CFG_MALLOC_F_ADDR 0x204D0000 #endif #ifdef CONFIG_DISTRO_DEFAULTS diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index e4d6a8a1540..d80238bd02f 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -46,7 +46,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CFG_MALLOC_F_ADDR 0x930000 #endif #define CFG_EXTRA_ENV_SETTINGS BOOTENV diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 4dd51c7f1d7..5a3c9f76a43 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -16,7 +16,7 @@ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 +#define CFG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 0d293f316b7..940bfd2b336 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -28,7 +28,7 @@ /* generic timer */ /* early heap for SPL DM */ -#define CONFIG_MALLOC_F_ADDR CFG_SYS_FSL_OCRAM_BASE +#define CFG_MALLOC_F_ADDR CFG_SYS_FSL_OCRAM_BASE /* serial port */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 9160c78c046..ce6dc87c69c 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -16,7 +16,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 1d8709180c8..37ade717ae9 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -14,7 +14,7 @@ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 +#define CFG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 8d9af7f088d..4e5653dc886 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MALLOC_F_ADDR 0x0010000 +#define CFG_MALLOC_F_ADDR 0x0010000 /* Size of our emulated memory */ #define SB_CONCAT(x, y) x ## y diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 7f3fa795afd..27d7efb883d 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -14,7 +14,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 2cb076cabac..942081ab84d 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -16,7 +16,7 @@ /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x184000 +#define CFG_MALLOC_F_ADDR 0x184000 /* For RAW image gives a error info not panic */ #endif /* CONFIG_SPL_BUILD */ -- cgit v1.3.1 From 1d457dbb9151f50176f7548d00ed37e13dc81e00 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:50 -0500 Subject: global: Migrate CONFIG_MAX_MEM_MAPPED to CFG Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED Signed-off-by: Tom Rini --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 +++--- arch/arm/include/asm/arch-fsl-layerscape/config.h | 14 +++++++------- arch/arm/include/asm/arch-ls102xa/config.h | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 14 +++++++------- arch/powerpc/cpu/mpc85xx/mp.c | 4 ++-- arch/powerpc/cpu/mpc85xx/tlb.c | 8 ++++---- arch/powerpc/cpu/mpc8xxx/pamu_table.c | 2 +- arch/powerpc/include/asm/config.h | 6 +++--- arch/xtensa/include/asm/config.h | 2 +- board/ti/dra7xx/evm.c | 14 +++++++------- common/memsize.c | 6 +++--- drivers/ddr/fsl/util.c | 6 +++--- include/configs/dra7xx_evm.h | 2 +- include/configs/mt7621.h | 2 +- include/configs/rcar-gen3-common.h | 2 +- include/configs/synquacer.h | 2 +- include/configs/xtfpga.h | 8 ++++---- 17 files changed, 50 insertions(+), 50 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 2aeec7dea7b..5c45c2a5ed5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1308,13 +1308,13 @@ phys_size_t get_effective_memsize(void) * allocated from first region. If the memory extends to the second * region (or the third region if applicable), Management Complex (MC) * memory should be put into the highest region, i.e. the end of DDR - * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so + * memory. CFG_MAX_MEM_MAPPED is set to the size of first region so * U-Boot doesn't relocate itself into higher address. Should DDR be * configured to skip the first region, this function needs to be * adjusted. */ - if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { - ea_size = CONFIG_MAX_MEM_MAPPED; + if (gd->ram_size > CFG_MAX_MEM_MAPPED) { + ea_size = CFG_MAX_MEM_MAPPED; rem = gd->ram_size - ea_size; } else { ea_size = gd->ram_size; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 57d92f65520..12758c8dd1c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -36,7 +36,7 @@ /* DDR */ #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -121,7 +121,7 @@ /* DDR */ #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* DCFG - GUR */ #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ @@ -147,7 +147,7 @@ /* DDR */ #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -191,7 +191,7 @@ /* DDR */ #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* SEC */ @@ -211,7 +211,7 @@ #define CFG_SYS_NUM_FM1_DTSEC 7 #define CFG_SYS_NUM_FM1_10GEC 1 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -250,14 +250,14 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #elif defined(CONFIG_ARCH_LS1046A) #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 8 #define CFG_SYS_NUM_FM1_10GEC 2 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* SMMU Defintions */ #define SMMU_BASE 0x09000000 diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 4a4d6424414..d0abbdadf08 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -70,7 +70,7 @@ /* SATA */ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) #ifdef CONFIG_DDR_SPD -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #endif #define DCU_LAYER_MAX_NUM 16 diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index be85c54e480..0abcc01b857 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -616,12 +616,12 @@ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) /* * slide the testing window up to test another area * for 32_bit system, the maximum testable memory is limited to - * CONFIG_MAX_MEM_MAPPED + * CFG_MAX_MEM_MAPPED */ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { phys_addr_t test_cap, p_addr; - phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); + phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED); #if !defined(CONFIG_PHYS_64BIT) || \ !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ @@ -632,7 +632,7 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) #endif p_addr = (*vstart) + (*size) + (*phys_offset); if (p_addr < test_cap - 1) { - p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); + p_size = min(test_cap - p_addr, CFG_MAX_MEM_MAPPED); if (reset_tlb(p_addr, p_size, phys_offset) == -1) return -1; *vstart = CFG_SYS_DDR_SDRAM_BASE; @@ -649,18 +649,18 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) /* initialization for testing area */ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { - phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); + phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED); *vstart = CFG_SYS_DDR_SDRAM_BASE; - *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ + *size = (u32) p_size; /* CFG_MAX_MEM_MAPPED < 4G */ *phys_offset = 0; #if !defined(CONFIG_PHYS_64BIT) || \ !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) - if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + if (gd->ram_size > CFG_MAX_MEM_MAPPED) { puts("Cannot test more than "); - print_size(CONFIG_MAX_MEM_MAPPED, + print_size(CFG_MAX_MEM_MAPPED, " without proper 36BIT support.\n"); } #endif diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 44f8ed8a19a..7c47e415f05 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -193,8 +193,8 @@ u32 determine_mp_bootpg(unsigned int *pagesize) /* use last 4K of mapped memory */ - bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : gd->ram_size) + + bootpg = ((gd->ram_size > CFG_MAX_MEM_MAPPED) ? + CFG_MAX_MEM_MAPPED : gd->ram_size) + CFG_SYS_SDRAM_BASE - 4096; if (pagesize) *pagesize = 4096; diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 5d21bef5878..2a78f0fe502 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -306,12 +306,12 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, u64 memsize = (u64)memsize_in_meg << 20; u64 size; - size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED); + size = min(memsize, (u64)CFG_MAX_MEM_MAPPED); size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM); - if (size || memsize > CONFIG_MAX_MEM_MAPPED) { - print_size(memsize > CONFIG_MAX_MEM_MAPPED ? - memsize - CONFIG_MAX_MEM_MAPPED + size : size, + if (size || memsize > CFG_MAX_MEM_MAPPED) { + print_size(memsize > CFG_MAX_MEM_MAPPED ? + memsize - CFG_MAX_MEM_MAPPED + size : size, " of DDR memory left unmapped in U-Boot\n"); #ifndef CONFIG_SPL_BUILD puts(" "); diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index caad6670cc9..b906279226a 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -17,7 +17,7 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) tbl->start_addr[i] = (uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE); - tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED)); + tbl->size[i] = (phys_size_t)(min(gd->ram_size, CFG_MAX_MEM_MAPPED)); tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; i++; diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 983c6f70cfe..f0702cab143 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -14,13 +14,13 @@ #define HWCONFIG_BUFFER_SIZE 256 #endif -#ifndef CONFIG_MAX_MEM_MAPPED +#ifndef CFG_MAX_MEM_MAPPED #if defined(CONFIG_E500) || \ defined(CONFIG_MPC86xx) || \ defined(CONFIG_E300) -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #else -#define CONFIG_MAX_MEM_MAPPED (256 << 20) +#define CFG_MAX_MEM_MAPPED (256 << 20) #endif #endif diff --git a/arch/xtensa/include/asm/config.h b/arch/xtensa/include/asm/config.h index 21b334b9389..268c5688b3d 100644 --- a/arch/xtensa/include/asm/config.h +++ b/arch/xtensa/include/asm/config.h @@ -14,7 +14,7 @@ * restricting used physical memory to the first 128MB. */ #if XCHAL_HAVE_PTP_MMU -#define CONFIG_MAX_MEM_MAPPED (128 << 20) +#define CFG_MAX_MEM_MAPPED (128 << 20) #endif #endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 9cb7e21a9f7..568c8fb0411 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -277,13 +277,13 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) case DRA752_ES2_0: switch (emif_nr) { case 1: - if (ram_size > CONFIG_MAX_MEM_MAPPED) + if (ram_size > CFG_MAX_MEM_MAPPED) *regs = &emif1_ddr3_532_mhz_1cs_2G; else *regs = &emif1_ddr3_532_mhz_1cs; break; case 2: - if (ram_size > CONFIG_MAX_MEM_MAPPED) + if (ram_size > CFG_MAX_MEM_MAPPED) *regs = &emif2_ddr3_532_mhz_1cs_2G; else *regs = &emif2_ddr3_532_mhz_1cs; @@ -301,7 +301,7 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) case DRA722_ES1_0: case DRA722_ES2_0: case DRA722_ES2_1: - if (ram_size < CONFIG_MAX_MEM_MAPPED) + if (ram_size < CFG_MAX_MEM_MAPPED) *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; else *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2; @@ -360,7 +360,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: - if (ram_size > CONFIG_MAX_MEM_MAPPED) + if (ram_size > CFG_MAX_MEM_MAPPED) *dmm_lisa_regs = &lisa_map_dra7_2GB; else *dmm_lisa_regs = &lisa_map_dra7_1536MB; @@ -369,7 +369,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) case DRA722_ES2_0: case DRA722_ES2_1: default: - if (ram_size < CONFIG_MAX_MEM_MAPPED) + if (ram_size < CFG_MAX_MEM_MAPPED) *dmm_lisa_regs = &lisa_map_2G_x_2; else *dmm_lisa_regs = &lisa_map_2G_x_4; @@ -644,9 +644,9 @@ int dram_init_banksize(void) gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = get_effective_memsize(); - if (ram_size > CONFIG_MAX_MEM_MAPPED) { + if (ram_size > CFG_MAX_MEM_MAPPED) { gd->bd->bi_dram[1].start = 0x200000000; - gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED; + gd->bd->bi_dram[1].size = ram_size - CFG_MAX_MEM_MAPPED; } return 0; diff --git a/common/memsize.c b/common/memsize.c index 3c80ad2c834..ad9ddf67ac5 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -106,11 +106,11 @@ phys_size_t __weak get_effective_memsize(void) if (gd->ram_base + ram_size < gd->ram_base) ram_size = ((phys_size_t)~0xfffULL) - gd->ram_base; -#ifndef CONFIG_MAX_MEM_MAPPED +#ifndef CFG_MAX_MEM_MAPPED return ram_size; #else /* limit stack to what we can reasonable map */ - return ((ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : ram_size); + return ((ram_size > CFG_MAX_MEM_MAPPED) ? + CFG_MAX_MEM_MAPPED : ram_size); #endif } diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index e49cf6e8e3d..60051392e71 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -139,10 +139,10 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, } #if !defined(CONFIG_PHYS_64BIT) - if (base >= CONFIG_MAX_MEM_MAPPED) + if (base >= CFG_MAX_MEM_MAPPED) return; - if ((base + size) >= CONFIG_MAX_MEM_MAPPED) - size = CONFIG_MAX_MEM_MAPPED - base; + if ((base + size) >= CFG_MAX_MEM_MAPPED) + size = CFG_MAX_MEM_MAPPED - base; #endif if (set_ddr_laws(base, size, law_memctl) < 0) { printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index f8afcc7826e..ef1d5a11260 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -13,7 +13,7 @@ #include -#define CONFIG_MAX_MEM_MAPPED 0x80000000 +#define CFG_MAX_MEM_MAPPED 0x80000000 #ifndef CONFIG_QSPI_BOOT /* MMC ENV related defines */ diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index b6e680bcc78..a9574940d42 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -10,7 +10,7 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_MAX_MEM_MAPPED 0x1c000000 +#define CFG_MAX_MEM_MAPPED 0x1c000000 #define CFG_SYS_INIT_SP_OFFSET 0x800000 diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 8e0837a3027..213caa75238 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -28,7 +28,7 @@ #define DRAM_RSV_SIZE 0x08000000 #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) -#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) +#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) /* ENV setting */ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index a62d1d32547..e65d6238163 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -14,7 +14,7 @@ #define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ #define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */ -#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE +#define CFG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE #define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */ diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 83a0539d8f2..9655b666eda 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -27,7 +27,7 @@ #else #define CFG_SYS_MEMORY_BASE 0x60000000 #define CFG_SYS_IO_BASE 0x90000000 -#define CONFIG_MAX_MEM_MAPPED 0x10000000 +#define CFG_MAX_MEM_MAPPED 0x10000000 #endif /* Onboard RAM sizes: @@ -53,10 +53,10 @@ /* Memory test is destructive so default must not overlap vectors or U-Boot*/ -#if defined(CONFIG_MAX_MEM_MAPPED) && \ - CONFIG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE +#if defined(CFG_MAX_MEM_MAPPED) && \ + CFG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE #define XTENSA_SYS_TEXT_ADDR \ - (MEMADDR(CONFIG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) + (MEMADDR(CFG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) #else #define XTENSA_SYS_TEXT_ADDR \ (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) -- cgit v1.3.1 From 8a897c4f971ec7ecfd114c5118ccd22e4273a6be Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:51 -0500 Subject: global: Migrate CONFIG_MAX_RAM_BANK_SIZE to CFG Perform a simple rename of CONFIG_MAX_RAM_BANK_SIZE to CFG_MAX_RAM_BANK_SIZE Signed-off-by: Tom Rini --- arch/arm/mach-davinci/misc.c | 2 +- arch/arm/mach-omap2/am33xx/board.c | 4 ++-- arch/arm/mach-omap2/sec-common.c | 2 +- arch/arm/mach-orion5x/dram.c | 4 ++-- arch/arm/mach-orion5x/include/mach/orion5x.h | 2 +- board/phytec/phycore_am335x_r2/board.c | 2 +- board/ti/ks2_evm/board.c | 2 +- include/configs/am43xx_evm.h | 2 +- include/configs/bur_am335x_common.h | 2 +- include/configs/cm_t43.h | 2 +- include/configs/da850evm.h | 2 +- include/configs/draco.h | 2 +- include/configs/etamin.h | 2 +- include/configs/legoev3.h | 2 +- include/configs/omapl138_lcdk.h | 2 +- include/configs/pxm2.h | 2 +- include/configs/rastaban.h | 2 +- include/configs/rut.h | 2 +- include/configs/thuban.h | 2 +- include/configs/ti816x_evm.h | 2 +- include/configs/ti_am335x_common.h | 2 +- include/configs/ti_armv7_keystone2.h | 2 +- 22 files changed, 24 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 42078b39f8a..cfad28c43d0 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -27,7 +27,7 @@ int dram_init(void) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( (void *)CFG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); return 0; } diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 86755d6d954..a52d04d85c8 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -73,7 +73,7 @@ int dram_init(void) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( (void *)CFG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); return 0; } @@ -521,7 +521,7 @@ void board_init_f(ulong dummy) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( (void *)CFG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); } #endif diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 0f9b915ea3d..64560b21e3f 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -203,7 +203,7 @@ u32 get_sec_mem_start(void) omap_sdram_size() #else get_ram_size((void *)CFG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE) + CFG_MAX_RAM_BANK_SIZE) #endif - sec_mem_size)); return sec_mem_start; diff --git a/arch/arm/mach-orion5x/dram.c b/arch/arm/mach-orion5x/dram.c index c9a3750e48d..5647f847d78 100644 --- a/arch/arm/mach-orion5x/dram.c +++ b/arch/arm/mach-orion5x/dram.c @@ -39,7 +39,7 @@ int dram_init (void) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( (long *) orion5x_sdram_bar(0), - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); return 0; } @@ -51,7 +51,7 @@ int dram_init_banksize(void) gd->bd->bi_dram[i].start = orion5x_sdram_bar(i); gd->bd->bi_dram[i].size = get_ram_size( (long *) (gd->bd->bi_dram[i].start), - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); } return 0; diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 4b1b0b0f371..e41d07e18cc 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -53,7 +53,7 @@ #define MVCPU_WIN_ENABLE ORION5X_WIN_ENABLE #define MVCPU_WIN_DISABLE ORION5X_WIN_DISABLE -#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024) +#define CFG_MAX_RAM_BANK_SIZE (64*1024*1024) /* include here SoC variants. 5181, 5281, 6183 should go here when adding support for them, and this comment should then be updated. */ diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c index e84dd251c25..eb573d076dd 100644 --- a/board/phytec/phycore_am335x_r2/board.c +++ b/board/phytec/phycore_am335x_r2/board.c @@ -167,7 +167,7 @@ void sdram_init(void) /* Detect memory physically present */ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); /* Reconfigure memory for actual detected size */ switch (gd->ram_size) { diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 1683f780a33..5dcda12105b 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -47,7 +47,7 @@ int dram_init(void) ddr3_size = ddr3_init(); gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); #if defined(CONFIG_TI_AEMIF) if (!(board_is_k2g_ice() || board_is_k2g_i1())) aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 3a6ffd9de0b..f43e00e8a2b 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_AM43XX_EVM_H #define __CONFIG_AM43XX_EVM_H -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ +#define CFG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ #define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 3e0b4250788..ab57e14392d 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -19,7 +19,7 @@ #endif /* CONFIG_DM */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Timer information */ #define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index aa17c9cbe2c..743c8c86922 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_CM_T43_H #define __CONFIG_CM_T43_H -#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ +#define CFG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ #define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index cfc8330e35a..736af88a024 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -31,7 +31,7 @@ */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ +#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ /* memtest start addr */ /* memtest will be run on 16MB */ diff --git a/include/configs/draco.h b/include/configs/draco.h index b56ba9132af..4c67174572f 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -25,7 +25,7 @@ "led1=64,0,1\0" /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Default env settings */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 8d8e717b38d..d07b4e95364 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -67,7 +67,7 @@ "led5=63,0,1\0" /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 687ac89b857..ff966586ba6 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -27,7 +27,7 @@ */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ +#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ /* memtest start addr */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 5e71ebcba85..af0093511a0 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -26,7 +26,7 @@ */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ +#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ /* memtest start addr */ diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 10eaeb49de6..b701e52076d 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -23,7 +23,7 @@ "led0=117,0,1\0" \ /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ +#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ /* Use common default */ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 777df4c1125..2efb4d23cdd 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -32,7 +32,7 @@ "led5=63,0,1\0" /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 diff --git a/include/configs/rut.h b/include/configs/rut.h index 99799f8494e..4002bc4b6c8 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -19,7 +19,7 @@ #define DDR_PLL_FREQ 303 /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ +#define CFG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ /* Watchdog */ #define WATCHDOG_TRIGGER_GPIO 14 diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 1753fa410d1..a5913e1e7d2 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -25,7 +25,7 @@ "led1=64,0,1\0" /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 2d9d2fd66e9..ac6d46f917b 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -19,7 +19,7 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ +#define CFG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ #define CFG_SYS_SDRAM_BASE 0x80000000 /** diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index ed17b429209..20f8643771d 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -11,7 +11,7 @@ #ifndef __CONFIG_TI_AM335X_COMMON_H__ #define __CONFIG_TI_AM335X_COMMON_H__ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ #define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 7142d30a599..a47f0902a26 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -15,7 +15,7 @@ /* Memory Configuration */ #define CFG_SYS_LPAE_SDRAM_BASE 0x800000000 -#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ +#define CFG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ #ifdef CONFIG_SYS_MALLOC_F_LEN #define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN -- cgit v1.3.1 From 8f52920a4a36d905725a6945694ab0d2df6fac59 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:52 -0500 Subject: global: Migrate CONFIG_MFG_ENV_SETTINGS to CFG Perform a simple rename of CONFIG_MFG_ENV_SETTINGS to CFG_MFG_ENV_SETTINGS Signed-off-by: Tom Rini --- include/configs/capricorn-common.h | 4 ++-- include/configs/cgtqmx8.h | 4 ++-- include/configs/colibri-imx8x.h | 4 ++-- include/configs/imx8mq_phanbell.h | 4 ++-- include/configs/imx8qm_rom7720.h | 4 ++-- include/configs/mx7dsabresd.h | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 9e7322cdb93..9dcacad2fc0 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -60,7 +60,7 @@ "${loadaddr} ${m4_0_image}\0" \ "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ -#define CONFIG_MFG_ENV_SETTINGS \ +#define CFG_MFG_ENV_SETTINGS \ MFG_ENV_SETTINGS_DEFAULT \ "initrd_addr=0x83100000\0" \ "initrd_high=0xffffffffffffffff\0" \ @@ -68,7 +68,7 @@ /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ - CONFIG_MFG_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ AHAB_ENV \ ENV_COMMON \ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index a6332597384..91454df1972 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -42,7 +42,7 @@ #define FEC0_RESET IMX_GPIO_NR(2, 5) #define FEC0_PDOMAIN "conn_enet0" -#define CONFIG_MFG_ENV_SETTINGS \ +#define CFG_MFG_ENV_SETTINGS \ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ "rdinit=/linuxrc " \ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ @@ -56,7 +56,7 @@ /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ - CONFIG_MFG_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 13bc4e7e682..2de116c59da 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -43,7 +43,7 @@ #undef BOOTENV_RUN_NET_USB_START #define BOOTENV_RUN_NET_USB_START "" -#define CONFIG_MFG_ENV_SETTINGS \ +#define CFG_MFG_ENV_SETTINGS \ "mfgtool_args=setenv bootargs ${consoleargs} " \ "rdinit=/linuxrc g_mass_storage.stall=0 " \ "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \ @@ -59,7 +59,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ AHAB_ENV \ BOOTENV \ - CONFIG_MFG_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ MEM_LAYOUT_ENV_SETTINGS \ "boot_file=Image\0" \ diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 5158f2cc605..6d0c4531118 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -24,13 +24,13 @@ #define CFG_FEC_MXC_PHYADDR 0 #endif -#define CONFIG_MFG_ENV_SETTINGS \ +#define CFG_MFG_ENV_SETTINGS \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffff\0" \ /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ - CONFIG_MFG_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS \ "script=boot.scr\0" \ "image=Image\0" \ "console=ttymxc0,115200\0" \ diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 5692e3d0000..df2cb8d9ced 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -33,7 +33,7 @@ #define MFG_NAND_PARTITION "" #endif -#define CONFIG_MFG_ENV_SETTINGS \ +#define CFG_MFG_ENV_SETTINGS \ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ "rdinit=/linuxrc " \ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ @@ -48,7 +48,7 @@ /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ - CONFIG_MFG_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index e56083f8e61..9c938f04e93 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -32,7 +32,7 @@ #define UPDATE_M4_ENV "" #endif -#define CONFIG_MFG_ENV_SETTINGS \ +#define CFG_MFG_ENV_SETTINGS \ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ "rdinit=/linuxrc " \ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ @@ -52,7 +52,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ UPDATE_M4_ENV \ - CONFIG_MFG_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS \ CFG_DFU_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ -- cgit v1.3.1 From 55eef1d62958592b363240813b866216797d8141 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:53 -0500 Subject: global: Migrate CONFIG_MXC_NAND_IP_REGS_BASE to CFG Perform a simple rename of CONFIG_MXC_NAND_IP_REGS_BASE to CFG_MXC_NAND_IP_REGS_BASE Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/mxc_nand.c | 2 +- include/configs/m53menlo.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index 8aa5f734213..10679b2aa10 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -1175,7 +1175,7 @@ int board_nand_init(struct nand_chip *this) host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; #ifdef MXC_NFC_V3_2 host->ip_regs = - (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE; + (struct mxc_nand_ip_regs __iomem *)CFG_MXC_NAND_IP_REGS_BASE; #endif host->clk_act = 1; diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index de6928d2973..3ac67b0f489 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -46,7 +46,7 @@ #ifdef CONFIG_CMD_NAND #define CFG_SYS_NAND_BASE NFC_BASE_ADDR_AXI #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI -#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR +#define CFG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CFG_SYS_NAND_LARGEPAGE #endif -- cgit v1.3.1 From d1c723895bfcc335bd3b674facd38b02586e6cac Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:54 -0500 Subject: global: Migrate CONFIG_MXC_NAND_REGS_BASE to CFG Perform a simple rename of CONFIG_MXC_NAND_REGS_BASE to CFG_MXC_NAND_REGS_BASE Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/mxc_nand.c | 2 +- include/configs/m53menlo.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index 10679b2aa10..051ded6a240 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -1172,7 +1172,7 @@ int board_nand_init(struct nand_chip *this) this->write_buf = mxc_nand_write_buf; this->read_buf = mxc_nand_read_buf; - host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; + host->regs = (struct mxc_nand_regs __iomem *)CFG_MXC_NAND_REGS_BASE; #ifdef MXC_NFC_V3_2 host->ip_regs = (struct mxc_nand_ip_regs __iomem *)CFG_MXC_NAND_IP_REGS_BASE; diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 3ac67b0f489..ee19c8936b9 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -45,7 +45,7 @@ */ #ifdef CONFIG_CMD_NAND #define CFG_SYS_NAND_BASE NFC_BASE_ADDR_AXI -#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI +#define CFG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI #define CFG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CFG_SYS_NAND_LARGEPAGE #endif -- cgit v1.3.1 From 4db386655a889b6466d2c3f40839ad21205c6d21 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:55 -0500 Subject: global: Migrate CONFIG_MXC_UART_BASE to CFG Perform a simple rename of CONFIG_MXC_UART_BASE to CFG_MXC_UART_BASE Signed-off-by: Tom Rini --- board/ge/b1x5v2/spl.c | 4 ++-- drivers/serial/serial_mxc.c | 6 +++--- include/configs/apalis_imx6.h | 2 +- include/configs/cl-som-imx7.h | 2 +- include/configs/cm_fx6.h | 2 +- include/configs/colibri_imx6.h | 2 +- include/configs/dart_6ul.h | 2 +- include/configs/dh_imx6.h | 2 +- include/configs/display5.h | 2 +- include/configs/el6x_common.h | 2 +- include/configs/embestmx6boards.h | 2 +- include/configs/ge_b1x5v2.h | 4 ++-- include/configs/gw_ventana.h | 2 +- include/configs/imx6-engicam.h | 4 ++-- include/configs/imx6_logic.h | 2 +- include/configs/imx6dl-mamoj.h | 2 +- include/configs/imx6ulz_smm_m2.h | 2 +- include/configs/imx7-cm.h | 2 +- include/configs/imx8mm_data_modul_edm_sbc.h | 2 +- include/configs/imx8mp_dhcom_pdk2.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/imx8mq_cm.h | 2 +- include/configs/imx8mq_evk.h | 2 +- include/configs/imx8mq_phanbell.h | 2 +- include/configs/kontron-sl-mx6ul.h | 2 +- include/configs/kontron_pitx_imx8m.h | 2 +- include/configs/librem5.h | 10 +++++----- include/configs/liteboard.h | 2 +- include/configs/m53menlo.h | 2 +- include/configs/mccmon6.h | 2 +- include/configs/msc_sm2s_imx8mp.h | 2 +- include/configs/mx51evk.h | 2 +- include/configs/mx53cx9020.h | 2 +- include/configs/mx53loco.h | 2 +- include/configs/mx6cuboxi.h | 2 +- include/configs/mx6memcal.h | 6 +++--- include/configs/mx6sabreauto.h | 2 +- include/configs/mx6sabresd.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/mx6sllevk.h | 2 +- include/configs/mx6sxsabreauto.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/mx6ul_14x14_evk.h | 2 +- include/configs/mx6ullevk.h | 2 +- include/configs/mys_6ulx.h | 2 +- include/configs/nitrogen6x.h | 2 +- include/configs/novena.h | 2 +- include/configs/npi_imx6ull.h | 2 +- include/configs/pcl063.h | 2 +- include/configs/pcl063_ull.h | 2 +- include/configs/pico-imx6.h | 2 +- include/configs/pico-imx6ul.h | 2 +- include/configs/pico-imx7d.h | 2 +- include/configs/pico-imx8mq.h | 2 +- include/configs/tqma6_mba6.h | 2 +- include/configs/tqma6_wru4.h | 2 +- include/configs/udoo.h | 2 +- include/configs/udoo_neo.h | 2 +- include/configs/usbarmory.h | 2 +- include/configs/vining_2000.h | 2 +- include/configs/wandboard.h | 2 +- include/configs/xpress.h | 2 +- 62 files changed, 73 insertions(+), 73 deletions(-) (limited to 'include') diff --git a/board/ge/b1x5v2/spl.c b/board/ge/b1x5v2/spl.c index 52c80f792d3..460d3be1d83 100644 --- a/board/ge/b1x5v2/spl.c +++ b/board/ge/b1x5v2/spl.c @@ -565,9 +565,9 @@ void board_init_f(ulong dummy) timer_init(); /* iomux */ - if (CONFIG_MXC_UART_BASE == UART2_BASE) + if (CFG_MXC_UART_BASE == UART2_BASE) SETUP_IOMUX_PADS(uart2_pads); - else if (CONFIG_MXC_UART_BASE == UART3_BASE) + else if (CFG_MXC_UART_BASE == UART3_BASE) SETUP_IOMUX_PADS(uart3_pads); /* UART clocks enabled and gd valid - init serial console */ diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 82c0d84628d..8bcbbf2bbfc 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -194,11 +194,11 @@ static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk, #if !CONFIG_IS_ENABLED(DM_SERIAL) -#ifndef CONFIG_MXC_UART_BASE -#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver" +#ifndef CFG_MXC_UART_BASE +#error "define CFG_MXC_UART_BASE to use the MXC UART driver" #endif -#define mxc_base ((struct mxc_uart *)CONFIG_MXC_UART_BASE) +#define mxc_base ((struct mxc_uart *)CFG_MXC_UART_BASE) static void mxc_serial_setbrg(void) { diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index d46159076f2..2fb4cfa5e9a 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -15,7 +15,7 @@ #include #include -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index cde7d3c891a..b7920c7b305 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -10,7 +10,7 @@ #include "mx7_common.h" -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR +#define CFG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* Network */ #define CFG_FEC_MXC_PHYADDR 0 diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 47b76c9371e..90ebec4a94c 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -26,7 +26,7 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Serial console */ -#define CONFIG_MXC_UART_BASE UART4_BASE +#define CFG_MXC_UART_BASE UART4_BASE /* Environment */ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index bf2a9bbaaff..3c67aab04c1 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -15,7 +15,7 @@ #include #include -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index c2ed9c7c56a..fb619105a76 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -28,7 +28,7 @@ #define MMC_ROOTFS_PART 2 /* Console configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 6aef15c658c..348be5a6ec6 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -28,7 +28,7 @@ #define CFG_SYS_FSL_USDHC_NUM 3 /* UART */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* USB Configs */ #ifdef CONFIG_CMD_USB diff --git a/include/configs/display5.h b/include/configs/display5.h index 70ad88c9075..cd1544be039 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -34,7 +34,7 @@ #define CFG_SYS_SPI_ARGS_OFFS 0x140000 #define CFG_SYS_SPI_ARGS_SIZE 0x10000 -#define CONFIG_MXC_UART_BASE UART5_BASE +#define CFG_MXC_UART_BASE UART5_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index a5e2dc063a7..6913a91c4c1 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -21,7 +21,7 @@ /* Commands */ -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE #define CFG_EXTRA_ENV_SETTINGS \ "board=EL6Q\0" \ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index c1748fc2602..81a92c9bb97 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -12,7 +12,7 @@ #ifndef __RIOTBOARD_CONFIG_H #define __RIOTBOARD_CONFIG_H -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 0523ff9a64b..529b8fc53e5 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -13,9 +13,9 @@ #include "mx6_common.h" /* UART */ -#define CONFIG_MXC_UART_BASE UART3_BASE +#define CFG_MXC_UART_BASE UART3_BASE -#if CONFIG_MXC_UART_BASE == UART2_BASE +#if CFG_MXC_UART_BASE == UART2_BASE /* UART2 requires CONFIG_DEBUG_UART_BASE=0x21e8000 */ #define CONSOLE_DEVICE "ttymxc1" /* System on Module debug connector */ #else diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 5a78c68e2fc..c6ace9d65eb 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -16,7 +16,7 @@ #include "mx6_common.h" /* Serial */ -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE /* NAND */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index 4208ba95915..786b70fe064 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -116,9 +116,9 @@ /* UART */ #ifdef CONFIG_MXC_UART # ifdef CONFIG_MX6UL -# define CONFIG_MXC_UART_BASE UART1_BASE +# define CFG_MXC_UART_BASE UART1_BASE # else -# define CONFIG_MXC_UART_BASE UART4_BASE +# define CFG_MXC_UART_BASE UART4_BASE # endif #endif diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 121b34ae96d..f9544cd430c 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -8,7 +8,7 @@ #ifndef __IMX6LOGIC_CONFIG_H #define __IMX6LOGIC_CONFIG_H -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" #include "mx6_common.h" diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index 162b0b8a69b..db08e43f0d8 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -35,7 +35,7 @@ #include /* UART */ -#define CONFIG_MXC_UART_BASE UART3_BASE +#define CFG_MXC_UART_BASE UART3_BASE /* MMC */ diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index c95038eaa53..9da98d0af27 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -12,7 +12,7 @@ #include #include -#define CONFIG_MXC_UART_BASE UART4_BASE +#define CFG_MXC_UART_BASE UART4_BASE #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 66cf5b463fc..84fb1bfb759 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -10,7 +10,7 @@ #include "mx7_common.h" -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR +#define CFG_MXC_UART_BASE UART1_IPS_BASE_ADDR #undef CFG_EXTRA_ENV_SETTINGS diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 0723d27ab70..f7d2b660c1f 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -25,7 +25,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */ -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR +#define CFG_MXC_UART_BASE UART3_BASE_ADDR /* PHY needs a longer autonegotiation timeout after reset */ #define PHY_ANEG_TIMEOUT 20000 diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index b8fdedefa21..d022faaa91a 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -18,7 +18,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x20000000 /* Minimum 512 MiB DDR */ -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR +#define CFG_MXC_UART_BASE UART1_BASE_ADDR /* PHY needs a longer autonegotiation timeout after reset */ #define PHY_ANEG_TIMEOUT 20000 diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index e4e24b522fd..495ca313db2 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -148,7 +148,7 @@ #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ #endif -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR +#define CFG_MXC_UART_BASE UART3_BASE_ADDR #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index f7ae1b47d06..828bd672372 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -54,7 +54,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) +#define CFG_MXC_UART_BASE UART_BASE_ADDR(1) #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 4b46321e851..a7a51907f5c 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -59,7 +59,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) +#define CFG_MXC_UART_BASE UART_BASE_ADDR(1) #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 6d0c4531118..bfde15e6240 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -92,7 +92,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) +#define CFG_MXC_UART_BASE UART_BASE_ADDR(1) #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index e3ae91089ff..4354f3945e8 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -22,7 +22,7 @@ #define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* Board and environment settings */ -#define CONFIG_MXC_UART_BASE UART4_BASE +#define CFG_MXC_UART_BASE UART4_BASE #ifdef CONFIG_USB_EHCI_HCD #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 5a3c9f76a43..bf590efb434 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -67,7 +67,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) +#define CFG_MXC_UART_BASE UART_BASE_ADDR(3) #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/librem5.h b/include/configs/librem5.h index 7417f8582a4..9e4d373e56d 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -30,23 +30,23 @@ #define CONSOLE_ON_UART1 #ifdef CONSOLE_ON_UART1 -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR +#define CFG_MXC_UART_BASE UART1_BASE_ADDR #define CONSOLE_UART_CLK 0 #define CONSOLE "ttymxc0" #elif defined(CONSOLE_ON_UART2) -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR +#define CFG_MXC_UART_BASE UART2_BASE_ADDR #define CONSOLE_UART_CLK 1 #define CONSOLE "ttymxc1" #elif defined(CONSOLE_ON_UART3) -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR +#define CFG_MXC_UART_BASE UART3_BASE_ADDR #define CONSOLE_UART_CLK 2 #define CONSOLE "ttymxc2" #elif defined(CONSOLE_ON_UART4) -#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR +#define CFG_MXC_UART_BASE UART4_BASE_ADDR #define CONSOLE_UART_CLK 3 #define CONSOLE "ttymxc3" #else -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR +#define CFG_MXC_UART_BASE UART1_BASE_ADDR #define CONSOLE_UART_CLK 0 #define CONSOLE "ttymxc0" #endif diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 0b8781d7bf3..63e5dbfab77 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -13,7 +13,7 @@ #include #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #ifdef CONFIG_FSL_USDHC diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index ee19c8936b9..9aac5677fb7 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -31,7 +31,7 @@ /* * Serial Driver */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* * MMC Driver diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 6cc49378fed..b64bf93bcb7 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -17,7 +17,7 @@ * mode from SD card (SD2) */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index 1cd0b3cf737..c1c1fd5a784 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -55,7 +55,7 @@ #define PHYS_SDRAM_2 0xc0000000 #define PHYS_SDRAM_2_SIZE 0x0 -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR +#define CFG_MXC_UART_BASE UART2_BASE_ADDR #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 740e357e00e..123b7a533b1 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -18,7 +18,7 @@ * Hardware drivers */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* PMIC Controller */ #define CFG_FSL_PMIC_BUS 0 diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index baffe65c369..1a3ec6e0cdb 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -14,7 +14,7 @@ #include -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 0ac93d6e043..d87f9e942c5 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -11,7 +11,7 @@ #include -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index d4af96b51ea..871d52c343f 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -19,7 +19,7 @@ /* Command definition */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #define CFG_EXTRA_ENV_SETTINGS \ "som_rev=undefined\0" \ diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index f6d3b2eeb9c..b664962a26a 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -14,12 +14,12 @@ #ifdef CONFIG_SERIAL_CONSOLE_UART1 #if defined(CONFIG_MX6SL) -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR +#define CFG_MXC_UART_BASE UART1_IPS_BASE_ADDR #else -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #endif #elif defined(CONFIG_SERIAL_CONSOLE_UART2) -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE #else #error please define serial console (CONFIG_SERIAL_CONSOLE_UARTx) #endif diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 888da7ce365..274c14bbd38 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -8,7 +8,7 @@ #ifndef __MX6SABREAUTO_CONFIG_H #define __MX6SABREAUTO_CONFIG_H -#define CONFIG_MXC_UART_BASE UART4_BASE +#define CFG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" /* USB Configs */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 78a554d0ccb..af9978e02c8 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -8,7 +8,7 @@ #ifndef __MX6SABRESD_CONFIG_H #define __MX6SABRESD_CONFIG_H -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" #include "mx6sabre_common.h" diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 4fbd06783a6..f6d9ac20821 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -10,7 +10,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR +#define CFG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index cf4871cbae3..aec3e51bff8 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -10,7 +10,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #define CFG_EXTRA_ENV_SETTINGS \ "epdc_waveform=epdc_splash.bin\0" \ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 3399cdd16fa..3d0f6e452d6 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -10,7 +10,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index c99d99abc17..8c39e6d6cf4 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -12,7 +12,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #ifdef CONFIG_IMX_BOOTAUX diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 5e3695ecc97..3f8a90b626d 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -15,7 +15,7 @@ #define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #ifdef CONFIG_FSL_USDHC diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 58d1a744ae9..2c3cd32cefa 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -16,7 +16,7 @@ #define PHYS_SDRAM_SIZE SZ_512M -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #ifdef CONFIG_FSL_USDHC diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 43261824d3c..0c0235b4298 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -13,7 +13,7 @@ #define CFG_SYS_FSL_USDHC_NUM 1 /* Console configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index aca15be64b1..5625771bad1 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -11,7 +11,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/novena.h b/include/configs/novena.h index 3ffb44ab725..7243549b68d 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -49,7 +49,7 @@ #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE /* USB Configs */ #ifdef CONFIG_CMD_USB diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 4b47e4fbb37..24d7b0c26e8 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -13,7 +13,7 @@ #define CFG_SYS_FSL_USDHC_NUM 1 /* Console configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 146f87e9ce3..e8c48cf8365 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -22,7 +22,7 @@ #define CFG_SYS_FSL_USDHC_NUM 1 /* Console configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 0890c115700..bd04268a3ef 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -22,7 +22,7 @@ #define MMC_ROOTFS_PART 2 /* Console configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index e1f7b700319..a1d0dd93c52 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -10,7 +10,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 1cb8fa63e72..64e0a556481 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -17,7 +17,7 @@ #define CFG_FEC_MXC_PHYADDR 0x1 -#define CONFIG_MXC_UART_BASE UART6_BASE_ADDR +#define CFG_MXC_UART_BASE UART6_BASE_ADDR /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 7fc6211ff73..dbeaeea77f7 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -10,7 +10,7 @@ #include "mx7_common.h" -#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR +#define CFG_MXC_UART_BASE UART5_IPS_BASE_ADDR /* MMC Config */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 37ade717ae9..4b602ea0302 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -71,7 +71,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) +#define CFG_MXC_UART_BASE UART_BASE_ADDR(1) #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h index a5f14dc4267..b5871424bc6 100644 --- a/include/configs/tqma6_mba6.h +++ b/include/configs/tqma6_mba6.h @@ -11,7 +11,7 @@ #define CFG_FEC_MXC_PHYADDR 0x03 -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" #endif /* __CONFIG_TQMA6_MBA6_H */ diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 34c9b6a2f97..e06fc7fe155 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -10,7 +10,7 @@ #define CFG_FEC_MXC_PHYADDR 0x01 /* UART */ -#define CONFIG_MXC_UART_BASE UART4_BASE +#define CFG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" /* Watchdog */ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index f0092eff149..d85cf7808c7 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -10,7 +10,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 5d7d734daa2..842abb7b7a2 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -16,7 +16,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR /* Command definition */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* Linux only */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 11706148f1e..00b45cc3d2a 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -17,7 +17,7 @@ /* U-Boot general configurations */ /* UART */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* SD/MMC */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index cdd2eeef0ac..7954ed9910c 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -50,7 +50,7 @@ #endif #ifdef CONFIG_SPL_BUILD -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #endif #endif /* __CONFIG_H */ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 1e765439fab..8853bcd7be2 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -10,7 +10,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 96996ac1f0f..c8ae047e62c 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -10,7 +10,7 @@ #include "mx6_common.h" #include -#define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR +#define CFG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -- cgit v1.3.1 From dd11fdc31fb82f63258c1970a6d8d22b8ffd3173 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:56 -0500 Subject: global: Migrate CONFIG_MXC_USB_FLAGS et al to CFG Perform simple renames of: CONFIG_MXC_USB_FLAGS to CFG_MXC_USB_FLAGS CONFIG_MXC_USB_PORT to CFG_MXC_USB_PORT CONFIG_MXC_USB_PORTSC to CFG_MXC_USB_PORTSC Signed-off-by: Tom Rini --- drivers/usb/host/ehci-mx5.c | 4 ++-- drivers/usb/host/ehci-mx6.c | 8 ++++---- include/configs/apalis_imx6.h | 4 ++-- include/configs/aristainetos2.h | 4 ++-- include/configs/brppt2.h | 2 +- include/configs/cl-som-imx7.h | 4 ++-- include/configs/cm_fx6.h | 4 ++-- include/configs/colibri-imx6ull.h | 4 ++-- include/configs/colibri_imx6.h | 4 ++-- include/configs/colibri_imx7.h | 4 ++-- include/configs/dart_6ul.h | 4 ++-- include/configs/dh_imx6.h | 4 ++-- include/configs/display5.h | 2 +- include/configs/embestmx6boards.h | 4 ++-- include/configs/ge_b1x5v2.h | 4 ++-- include/configs/gw_ventana.h | 4 ++-- include/configs/imx6_logic.h | 4 ++-- include/configs/imx6dl-mamoj.h | 4 ++-- include/configs/imx6q-bosch-acc.h | 4 ++-- include/configs/imx7-cm.h | 2 +- include/configs/imx8mm-cl-iot-gate.h | 2 +- include/configs/kontron-sl-mx6ul.h | 4 ++-- include/configs/kontron-sl-mx8mm.h | 4 ++-- include/configs/kp_imx53.h | 4 ++-- include/configs/kp_imx6q_tpc.h | 4 ++-- include/configs/liteboard.h | 4 ++-- include/configs/m53menlo.h | 6 +++--- include/configs/meerkat96.h | 2 +- include/configs/mx51evk.h | 6 +++--- include/configs/mx53cx9020.h | 6 +++--- include/configs/mx53loco.h | 6 +++--- include/configs/mx53ppd.h | 6 +++--- include/configs/mx6cuboxi.h | 2 +- include/configs/mx6memcal.h | 2 +- include/configs/mx6sabreauto.h | 4 ++-- include/configs/mx6sabresd.h | 4 ++-- include/configs/mx6slevk.h | 4 ++-- include/configs/mx6sllevk.h | 2 +- include/configs/mx6sxsabreauto.h | 4 ++-- include/configs/mx6sxsabresd.h | 4 ++-- include/configs/mx6ul_14x14_evk.h | 4 ++-- include/configs/mx7dsabresd.h | 2 +- include/configs/mx7ulp_com.h | 2 +- include/configs/mys_6ulx.h | 4 ++-- include/configs/nitrogen6x.h | 4 ++-- include/configs/novena.h | 4 ++-- include/configs/npi_imx6ull.h | 4 ++-- include/configs/o4-imx6ull-nano.h | 2 +- include/configs/opos6uldev.h | 4 ++-- include/configs/pcl063.h | 4 ++-- include/configs/pcl063_ull.h | 4 ++-- include/configs/pico-imx6.h | 4 ++-- include/configs/pico-imx6ul.h | 4 ++-- include/configs/pico-imx7d.h | 4 ++-- include/configs/somlabs_visionsom_6ull.h | 4 ++-- include/configs/tbs2910.h | 2 +- include/configs/tqma6.h | 2 +- include/configs/usbarmory.h | 6 +++--- include/configs/verdin-imx8mm.h | 2 +- include/configs/vining_2000.h | 4 ++-- include/configs/wandboard.h | 4 ++-- include/configs/warp7.h | 2 +- include/configs/xpress.h | 4 ++-- 63 files changed, 119 insertions(+), 119 deletions(-) (limited to 'include') diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index 964a53bb7c0..c11279867c7 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -299,10 +299,10 @@ static int ehci_usb_probe(struct udevice *dev) HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); - __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + __raw_writel(CFG_MXC_USB_PORTSC, &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); - mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS); + mxc_set_usbcontrol(priv->portnr, CFG_MXC_USB_FLAGS); mdelay(10); return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0, diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index fa2ca2a1d91..0a12db614ff 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -70,8 +70,8 @@ DECLARE_GLOBAL_DATA_PTR; #define UCMD_RESET (1 << 1) /* controller reset */ /* If this is not defined, assume MX6/MX7/MX8M SoC default */ -#ifndef CONFIG_MXC_USB_PORTSC -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#ifndef CFG_MXC_USB_PORTSC +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* Base address for this IP block is 0x02184800 */ @@ -411,7 +411,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, return 0; setbits_le32(&ehci->usbmode, CM_HOST); - writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + writel(CFG_MXC_USB_PORTSC, &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); mdelay(10); @@ -454,7 +454,7 @@ static u32 mx6_portsc(enum usb_phy_interface phy_type) case USBPHY_INTERFACE_MODE_HSIC: return PORT_PTS_HSIC; default: - return CONFIG_MXC_USB_PORTSC; + return CFG_MXC_USB_PORTSC; } } diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 2fb4cfa5e9a..8a9f3ef75a7 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -26,8 +26,8 @@ /* USB Configs */ /* Host */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Framebuffer and LCD */ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index be1478ea8b6..286435d6f84 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -413,8 +413,8 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* UBI support */ diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 32d9f503d9f..38c98c5e21c 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -79,6 +79,6 @@ BUR_COMMON_ENV \ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_BRPP2_IMX6_H */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index b7920c7b305..0a667c60b61 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -96,7 +96,7 @@ #endif /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* __CONFIG_H */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 90ebec4a94c..7d0f2b6dc13 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -135,8 +135,8 @@ #define CFG_FEC_MXC_PHYADDR 0 /* USB */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Boot */ #define CFG_SYS_BOOTMAPSZ (8 << 20) diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 5b802aa92a9..ba45ee4efd3 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -123,8 +123,8 @@ /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* USB Device Firmware Update support */ #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 3c67aab04c1..4b2841833b5 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -23,8 +23,8 @@ /* USB Configs */ /* Host */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Command definition */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 91f87ea283f..c568643977c 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -167,7 +167,7 @@ /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index fb619105a76..c5781670864 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -47,8 +47,8 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 348be5a6ec6..5cf73274d5e 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -32,8 +32,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* USB Gadget (DFU, UMS) */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) diff --git a/include/configs/display5.h b/include/configs/display5.h index cd1544be039..3b96fff7d6f 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -288,5 +288,5 @@ /* The 0x120000 value corresponds to above SPI-NOR memory MAP */ #endif -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 81a92c9bb97..31c7e104f6b 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -18,8 +18,8 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 529b8fc53e5..49b058cb10d 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -24,8 +24,8 @@ #endif /* USB */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Memory */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index c6ace9d65eb..0a9dfe736f7 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -36,8 +36,8 @@ /* Various command support */ /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Miscellaneous configurable options */ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index f9544cd430c..85c054451f3 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -117,8 +117,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* Falcon Mode */ diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index db08e43f0d8..6c61b3f4480 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -43,8 +43,8 @@ #define CFG_FEC_MXC_PHYADDR 1 /* USB */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Falcon */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index e28185f24dd..2c998cdcfc7 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -110,7 +110,7 @@ #endif #endif -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* __IMX6Q_ACC_H */ diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 84fb1bfb759..106fbdb9053 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -79,6 +79,6 @@ /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 64cdc401d03..2641d7bc960 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -139,6 +139,6 @@ #define CFG_FEC_MXC_PHYADDR 0 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /*__IMX8MM_CL_IOT_GATE_H*/ diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index 4354f3945e8..1c92cd78767 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -25,8 +25,8 @@ #define CFG_MXC_UART_BASE UART4_BASE #ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* Boot order for distro boot */ diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index d80238bd02f..eee3d2ddb03 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -25,8 +25,8 @@ /* Board and environment settings */ #ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* GUID for capsule updatable firmware image */ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index da8a67b4ab6..6e383cbe75f 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -11,8 +11,8 @@ #include /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Command definition */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 99321b320f5..1aa4b8ab598 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -18,8 +18,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 63e5dbfab77..5811059c8e2 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -95,8 +95,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #ifdef CONFIG_CMD_NET diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 9aac5677fb7..1ecbba1b58f 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -70,9 +70,9 @@ * USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORT 1 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* LVDS display */ diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index 9e480fe0558..6ffc1282411 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -24,6 +24,6 @@ /* Environment configs */ /* USB configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 123b7a533b1..dff54d04a67 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -33,9 +33,9 @@ #define CFG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR /* USB Configs */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI -#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED +#define CFG_MXC_USB_PORT 1 +#define CFG_MXC_USB_PORTSC PORT_PTS_ULPI +#define CFG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED /* Framebuffer and LCD */ diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 1a3ec6e0cdb..e995776d30d 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -23,9 +23,9 @@ /* USB Configs */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORT 1 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Command definition */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index d87f9e942c5..7398804e6b5 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -17,9 +17,9 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* USB Configs */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORT 1 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* PMIC Controller */ #define CFG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 94d2191af91..df65dbeea41 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -12,9 +12,9 @@ #include /* USB Configs */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORT 1 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Command definition */ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 871d52c343f..f0d6405d301 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -15,7 +15,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR /* USB */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) /* Command definition */ diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index b664962a26a..f2edd13eb88 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -31,6 +31,6 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_MXC_USB_PORTSC PORT_PTS_UTMI +#define CFG_MXC_USB_PORTSC PORT_PTS_UTMI #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 274c14bbd38..da98139d7d7 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -12,8 +12,8 @@ #define CONSOLE_DEV "ttymxc3" /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index af9978e02c8..2b028e3aa2b 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -29,8 +29,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #endif /* __MX6SABRESD_CONFIG_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index f6d9ac20821..39c8ef060c7 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -90,8 +90,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #define CFG_SYS_FSL_USDHC_NUM 3 diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index aec3e51bff8..290996b51bc 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -94,7 +94,7 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif #include diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 3d0f6e452d6..1c14a6beb0a 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -96,8 +96,8 @@ #define CFG_FEC_MXC_PHYADDR 0x0 #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 8c39e6d6cf4..8b02c3b6310 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -118,8 +118,8 @@ #define CFG_FEC_MXC_PHYADDR 0x1 #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #ifdef CONFIG_CMD_PCI diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 3f8a90b626d..635ae78abcb 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -116,8 +116,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #ifdef CONFIG_CMD_NET diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 9c938f04e93..94bee75fdea 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -99,6 +99,6 @@ #endif /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index 5ee5129801d..a310c64e794 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -51,5 +51,5 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE SZ_256K -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 0c0235b4298..2571098d06c 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -30,8 +30,8 @@ #define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 5625771bad1..c9c599d0762 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -21,8 +21,8 @@ #define CFG_FEC_MXC_PHYADDR 6 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #ifdef CONFIG_CMD_MMC #define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) diff --git a/include/configs/novena.h b/include/configs/novena.h index 7243549b68d..dc5b0431290 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -53,8 +53,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* Extra U-Boot environment. */ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 24d7b0c26e8..5f933391cc0 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -29,8 +29,8 @@ #define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #ifdef CONFIG_CMD_NET #define CFG_FEC_MXC_PHYADDR 0x1 diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index 0e1083a2130..9050da8738b 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -12,7 +12,7 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #if IS_ENABLED(CONFIG_CMD_USB) -# define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +# define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* CONFIG_CMD_USB */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 459134b93f8..1edb1826c4e 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -19,8 +19,8 @@ /* USB */ #ifdef CONFIG_USB_EHCI_MX6 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* LCD */ diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index e8c48cf8365..38dcee05359 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -42,8 +42,8 @@ #define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index bd04268a3ef..d742201ce43 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -44,8 +44,8 @@ #define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index a1d0dd93c52..d806d7d9c57 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -16,8 +16,8 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 64e0a556481..4caa8233758 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -23,8 +23,8 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index dbeaeea77f7..fd8962e9f75 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -107,7 +107,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 3418d4e2b55..041a83b057d 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -61,8 +61,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #ifdef CONFIG_CMD_NET diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 9b396e6e73b..535859792d3 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -27,7 +27,7 @@ /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* CONFIG_CMD_USB */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index cb5f7fc25af..af5a474cf31 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -39,7 +39,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #if defined(CONFIG_TQMA6X_MMC_BOOT) diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 00b45cc3d2a..27e61f5b8f4 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -23,9 +23,9 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* USB */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORT 1 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Linux boot */ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 27d7efb883d..8cb1f1aff35 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -67,6 +67,6 @@ #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __VERDIN_IMX8MM_H */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 7954ed9910c..6db68c1e700 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -36,8 +36,8 @@ /* Network */ #define CFG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #ifdef CONFIG_CMD_PCI #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 8853bcd7be2..7b8c5cbe7a8 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -17,8 +17,8 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 0826e0bbe02..5d2956a5963 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -93,7 +93,7 @@ #define CFG_SYS_FSL_USDHC_NUM 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) /* USB Device Firmware Update support */ #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/xpress.h b/include/configs/xpress.h index c8ae047e62c..a2aa31008ec 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -28,8 +28,8 @@ /* Environment is in stored in the eMMC boot partition */ /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define CFG_FEC_ENET_DEV 0 #define CFG_FEC_MXC_PHYADDR 0x0 -- cgit v1.3.1 From 1c3ba55798e3552739f06356aaeb18e66ec49a3c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:23 -0500 Subject: global: Migrate CONFIG_ODROID_REV_AIN to CFG Perform a simple rename of CONFIG_ODROID_REV_AIN to CFG_ODROID_REV_AIN Signed-off-by: Tom Rini --- board/samsung/common/exynos5-dt-types.c | 4 ++-- include/configs/odroid_xu3.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/samsung/common/exynos5-dt-types.c b/board/samsung/common/exynos5-dt-types.c index 554fc91cc1a..9294d36ba35 100644 --- a/board/samsung/common/exynos5-dt-types.c +++ b/board/samsung/common/exynos5-dt-types.c @@ -57,7 +57,7 @@ static int odroid_get_adc_val(unsigned int *adcval) unsigned int adcval_prev = 0; int ret, retries = 20; - ret = adc_channel_single_shot("adc@12D10000", CONFIG_ODROID_REV_AIN, + ret = adc_channel_single_shot("adc@12D10000", CFG_ODROID_REV_AIN, &adcval_prev); if (ret) return ret; @@ -66,7 +66,7 @@ static int odroid_get_adc_val(unsigned int *adcval) mdelay(5); ret = adc_channel_single_shot("adc@12D10000", - CONFIG_ODROID_REV_AIN, adcval); + CFG_ODROID_REV_AIN, adcval); if (ret) return ret; diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 2bac017ea08..7304851d0f3 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -52,7 +52,7 @@ #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) /* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ -#define CONFIG_ODROID_REV_AIN 9 +#define CFG_ODROID_REV_AIN 9 /* * Need to override existing one (smdk5420) with odroid so set_board_info will -- cgit v1.3.1 From a2c164cbb46c6400d93d08e634a1987bfce0e79f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:24 -0500 Subject: global: Migrate CONFIG_OTHBOOTARGS to CFG Perform a simple rename of CONFIG_OTHBOOTARGS to CFG_OTHBOOTARGS Signed-off-by: Tom Rini --- include/configs/x86-common.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 65a1e63e00e..5d461e8d0c6 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -27,9 +27,9 @@ /* Default environment */ #define CONFIG_RAMDISK_ADDR 0x4000000 #if defined(CONFIG_GENERATE_ACPI_TABLE) || defined(CONFIG_EFI_STUB) -#define CONFIG_OTHBOOTARGS "othbootargs=\0" +#define CFG_OTHBOOTARGS "othbootargs=\0" #else -#define CONFIG_OTHBOOTARGS "othbootargs=acpi=off\0" +#define CFG_OTHBOOTARGS "othbootargs=acpi=off\0" #endif #if defined(CONFIG_DISTRO_DEFAULTS) @@ -49,7 +49,7 @@ "pciconfighost=1\0" \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - CONFIG_OTHBOOTARGS \ + CFG_OTHBOOTARGS \ "scriptaddr=0x7000000\0" \ "kernel_addr_r=0x1000000\0" \ "ramdisk_addr_r=0x4000000\0" \ -- cgit v1.3.1 From 7906f91789de1f0ceed87d53a39ca2d7ca80150c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:25 -0500 Subject: global: Migrate CONFIG_PCIE_IMX_PERST_GPIO to CFG Perform a simple rename of CONFIG_PCIE_IMX_PERST_GPIO to CFG_PCIE_IMX_PERST_GPIO Signed-off-by: Tom Rini --- drivers/pci/pcie_imx.c | 12 ++++++------ include/configs/mx6sabresd.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/novena.h | 2 +- include/configs/tbs2910.h | 2 +- include/configs/vining_2000.h | 2 +- 6 files changed, 11 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 46ac01713ff..902507aaae3 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -566,7 +566,7 @@ int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high) * do self-initialisation. * * In case your #PERST pin is connected to a plain GPIO pin of the - * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's + * CPU, you can define CFG_PCIE_IMX_PERST_GPIO in your board's * configuration file and the condition below will handle the rest * of the reset toggling. * @@ -578,13 +578,13 @@ int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high) * Linux at all in the first place since it's in some non-reset * state due to being previously used in U-Boot. */ -#ifdef CONFIG_PCIE_IMX_PERST_GPIO - gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset"); - gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0); +#ifdef CFG_PCIE_IMX_PERST_GPIO + gpio_request(CFG_PCIE_IMX_PERST_GPIO, "pcie_reset"); + gpio_direction_output(CFG_PCIE_IMX_PERST_GPIO, 0); mdelay(20); - gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1); + gpio_set_value(CFG_PCIE_IMX_PERST_GPIO, 1); mdelay(20); - gpio_free(CONFIG_PCIE_IMX_PERST_GPIO); + gpio_free(CFG_PCIE_IMX_PERST_GPIO); #else if (dm_gpio_is_valid(gpio)) { /* Assert PERST# for 20ms then de-assert */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 2b028e3aa2b..116a9c6abcf 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -20,7 +20,7 @@ #define CFG_SYS_FSL_USDHC_NUM 3 #ifdef CONFIG_CMD_PCI -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) +#define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 8b02c3b6310..85e5cfbb58d 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -123,7 +123,7 @@ #endif #ifdef CONFIG_CMD_PCI -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) +#define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif diff --git a/include/configs/novena.h b/include/configs/novena.h index dc5b0431290..6f4353e7df7 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -41,7 +41,7 @@ /* PCI express */ #ifdef CONFIG_CMD_PCI -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) +#define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) #endif diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 535859792d3..256331ae173 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -22,7 +22,7 @@ /* PCI */ #ifdef CONFIG_CMD_PCI -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) +#define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #endif /* USB */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 6db68c1e700..7bfc22c043f 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -40,7 +40,7 @@ #define CFG_MXC_USB_FLAGS 0 #ifdef CONFIG_CMD_PCI -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) +#define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) #endif #define CFG_IMX6_PWM_PER_CLK 66000000 -- cgit v1.3.1 From 52139620be4084ac00e3c628616599c4a88c4191 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:26 -0500 Subject: global: Migrate CONFIG_PCIE_IMX_POWER_GPIO to CFG Perform a simple rename of CONFIG_PCIE_IMX_POWER_GPIO to CFG_PCIE_IMX_POWER_GPIO Signed-off-by: Tom Rini --- drivers/pci/pcie_imx.c | 10 +++++----- include/configs/mx6sabresd.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/novena.h | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 902507aaae3..da48466480c 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -534,13 +534,13 @@ static int imx6_pcie_init_phy(void) int imx6_pcie_toggle_power(struct udevice *vpcie) { -#ifdef CONFIG_PCIE_IMX_POWER_GPIO - gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power"); - gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0); +#ifdef CFG_PCIE_IMX_POWER_GPIO + gpio_request(CFG_PCIE_IMX_POWER_GPIO, "pcie_power"); + gpio_direction_output(CFG_PCIE_IMX_POWER_GPIO, 0); mdelay(20); - gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1); + gpio_set_value(CFG_PCIE_IMX_POWER_GPIO, 1); mdelay(20); - gpio_free(CONFIG_PCIE_IMX_POWER_GPIO); + gpio_free(CFG_PCIE_IMX_POWER_GPIO); #endif #if CONFIG_IS_ENABLED(DM_REGULATOR) diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 116a9c6abcf..1aa8a56cceb 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -21,7 +21,7 @@ #ifdef CONFIG_CMD_PCI #define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) +#define CFG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif /* PMIC */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 85e5cfbb58d..fe0ad34ef9c 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -124,7 +124,7 @@ #ifdef CONFIG_CMD_PCI #define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) +#define CFG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif #define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR diff --git a/include/configs/novena.h b/include/configs/novena.h index 6f4353e7df7..5e8b7fa6217 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -42,7 +42,7 @@ /* PCI express */ #ifdef CONFIG_CMD_PCI #define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) +#define CFG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) #endif /* PMIC */ -- cgit v1.3.1 From 52d596eabbd3ce80c2e1ce0e860d588cd219bd0b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:28 -0500 Subject: global: Migrate CONFIG_PHY_ID to CFG Perform a simple rename of CONFIG_PHY_ID to CFG_PHY_ID Signed-off-by: Tom Rini --- board/egnite/ethernut5/ethernut5.c | 2 +- include/configs/ethernut5.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index ceb0d2cf0aa..9953df017e1 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -160,7 +160,7 @@ int board_eth_init(struct bd_info *bis) /* Set peripheral pins. */ at91_macb_hw_init(); /* Basic EMAC initialization. */ - if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID)) + if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CFG_PHY_ID)) return -1; /* * Early board revisions have a pull-down at the PHY's MODE0 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 3fd58d6bd4a..182369def91 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -48,7 +48,7 @@ /* JFFS2 */ /* Ethernet */ -#define CONFIG_PHY_ID 0 +#define CFG_PHY_ID 0 /* MMC */ #ifdef CONFIG_CMD_MMC -- cgit v1.3.1 From 830fd095a348d8390c23d93605e438ac24153be9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:29 -0500 Subject: global: Migrate CONFIG_PHY_IRAM_BASE to CFG Perform a simple rename of CONFIG_PHY_IRAM_BASE to CFG_PHY_IRAM_BASE Signed-off-by: Tom Rini --- arch/arm/mach-exynos/lowlevel_init.c | 6 +++--- include/configs/exynos5420-common.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 243b5c80c90..c57b8aee798 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -77,10 +77,10 @@ static void low_power_start(void) branch_bx(0x0); } - reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4); + reg_val = readl(CFG_PHY_IRAM_BASE + 0x4); if (reg_val != (uint32_t)&low_power_start) { /* Store jump address as low_power_start if not present */ - writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4); + writel((uint32_t)&low_power_start, CFG_PHY_IRAM_BASE + 0x4); dsb(); sev(); } @@ -164,7 +164,7 @@ static void secondary_cores_configure(void) writel((uint32_t)&low_power_start, CFG_LOWPOWER_ADDR); writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE); /* Store jump address for power down */ - writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4); + writel((uint32_t)&power_down_core, CFG_PHY_IRAM_BASE + 0x4); /* Need all core power down check */ dsb(); diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index bd43efa553c..b75fe1b0a86 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -10,7 +10,7 @@ #define CFG_IRAM_TOP 0x02074000 -#define CONFIG_PHY_IRAM_BASE 0x02020000 +#define CFG_PHY_IRAM_BASE 0x02020000 /* * Low Power settings -- cgit v1.3.1 From f410d0ac8a90d16870d33cc7944e98445f7e168d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:30 -0500 Subject: global: Migrate CONFIG_PL011_CLOCK to CFG Perform a simple rename of CONFIG_PL011_CLOCK to CFG_PL011_CLOCK Signed-off-by: Tom Rini --- README | 2 +- arch/arm/cpu/armv7/s5p4418/cpu.c | 2 +- board/armltd/total_compute/total_compute.c | 2 +- board/armltd/vexpress64/vexpress64.c | 2 +- drivers/serial/serial_pl01x.c | 8 ++++---- include/configs/corstone1000.h | 2 +- include/configs/highbank.h | 2 +- include/configs/lx2160a_common.h | 2 +- include/configs/mxs.h | 2 +- include/configs/s5p4418_nanopi2.h | 2 +- include/configs/synquacer.h | 2 +- include/configs/thunderx_88xx.h | 2 +- include/configs/total_compute.h | 2 +- include/configs/vexpress_aemv8.h | 4 ++-- include/configs/vexpress_common.h | 2 +- 15 files changed, 19 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/README b/README index 05618352fa9..8354cf5699b 100644 --- a/README +++ b/README @@ -413,7 +413,7 @@ The following options need to be configured: controller register space - Serial Ports: - CONFIG_PL011_CLOCK + CFG_PL011_CLOCK If you have Amba PrimeCell PL011 UARTs, set this variable to the clock speed of the UARTs. diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 3baa761ec7a..7ba9c0b0323 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -64,7 +64,7 @@ static void serial_device_init(void) /* set clock */ clk_disable(clk); - clk_set_rate(clk, CONFIG_PL011_CLOCK); + clk_set_rate(clk, CFG_PL011_CLOCK); clk_enable(clk); } #endif diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index b7772f79a31..53941b5f5f2 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -13,7 +13,7 @@ static const struct pl01x_serial_plat serial_plat = { .base = UART0_BASE, .type = TYPE_PL011, - .clock = CONFIG_PL011_CLOCK, + .clock = CFG_PL011_CLOCK, }; U_BOOT_DRVINFO(total_compute_serials) = { diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 4ca544f1017..99fb67ecedc 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; static const struct pl01x_serial_plat serial_plat = { .base = V2M_UART0, .type = TYPE_PL011, - .clock = CONFIG_PL011_CLOCK, + .clock = CFG_PL011_CLOCK, }; U_BOOT_DRVINFO(vexpress_serials) = { diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index d3c3d3e2d18..dd2881931df 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -193,7 +193,7 @@ static void pl01x_serial_init_baud(int baudrate) #if defined(CONFIG_PL011_SERIAL) pl01x_type = TYPE_PL011; - clock = CONFIG_PL011_CLOCK; + clock = CFG_PL011_CLOCK; #endif base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX]; @@ -343,8 +343,8 @@ static const struct udevice_id pl01x_serial_id[] ={ {} }; -#ifndef CONFIG_PL011_CLOCK -#define CONFIG_PL011_CLOCK 0 +#ifndef CFG_PL011_CLOCK +#define CFG_PL011_CLOCK 0 #endif int pl01x_serial_of_to_plat(struct udevice *dev) @@ -359,7 +359,7 @@ int pl01x_serial_of_to_plat(struct udevice *dev) return -EINVAL; plat->base = addr; - plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK); + plat->clock = dev_read_u32_default(dev, "clock", CFG_PL011_CLOCK); ret = clk_get_by_index(dev, 0, &clk); if (!ret) { ret = clk_enable(&clk); diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h index 8aec52d508e..3347c11792d 100644 --- a/include/configs/corstone1000.h +++ b/include/configs/corstone1000.h @@ -16,7 +16,7 @@ #define V2M_BASE 0x80000000 -#define CONFIG_PL011_CLOCK 50000000 +#define CFG_PL011_CLOCK 50000000 /* Physical Memory Map */ #define PHYS_SDRAM_1 (V2M_BASE) diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 76e6054b0cc..97bb439f735 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -8,7 +8,7 @@ #define CFG_SYS_BOOTMAPSZ (16 << 20) -#define CONFIG_PL011_CLOCK 150000000 +#define CFG_PL011_CLOCK 150000000 /* * Miscellaneous configurable options diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index c1a98fd3e4c..f8a20ea16f9 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -39,7 +39,7 @@ /* Serial Port */ -#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) +#define CFG_PL011_CLOCK (get_bus_freq(0) / 4) #define CFG_SYS_SERIAL0 0x21c0000 #define CFG_SYS_SERIAL1 0x21d0000 #define CFG_SYS_SERIAL2 0x21e0000 diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 32e0e06617e..90cb1a5e4a0 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -77,7 +77,7 @@ * DUART Serial Driver. * Conflicts with AUART driver which can be set by board. */ -#define CONFIG_PL011_CLOCK 24000000 +#define CFG_PL011_CLOCK 24000000 #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } /* Default baudrate can be overridden by board! */ diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index bfe559f6e2c..0e7d01925ee 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -76,7 +76,7 @@ /*----------------------------------------------------------------------- * serial console configuration */ -#define CONFIG_PL011_CLOCK 50000000 +#define CFG_PL011_CLOCK 50000000 #define CONFIG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \ (void *)PHY_BASEADDR_UART1, \ (void *)PHY_BASEADDR_UART2, \ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index e65d6238163..350cc69c28d 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -31,7 +31,7 @@ /* Serial (pl011) */ #define UART_CLK (62500000) -#define CONFIG_PL011_CLOCK UART_CLK +#define CFG_PL011_CLOCK UART_CLK #define CONFIG_PL01x_PORTS {(void *)(0x2a400000)} /* Support MTD */ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 8ba40546b2c..2bca86bed93 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -17,7 +17,7 @@ /* PL011 Serial Configuration */ -#define CONFIG_PL011_CLOCK 24000000 +#define CFG_PL011_CLOCK 24000000 /* Generic Interrupt Controller Definitions */ #define GICD_BASE (0x801000000000) diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index e007be8e456..436bf622e17 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -14,7 +14,7 @@ #define UART0_BASE 0x7ff80000 /* PL011 Serial Configuration */ -#define CONFIG_PL011_CLOCK 7372800 +#define CFG_PL011_CLOCK 7372800 /* Miscellaneous configurable options */ diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 87b8c5d57ee..43f7e454d81 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -86,9 +86,9 @@ /* PL011 Serial Configuration */ #ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_PL011_CLOCK 7372800 +#define CFG_PL011_CLOCK 7372800 #else -#define CONFIG_PL011_CLOCK 24000000 +#define CFG_PL011_CLOCK 24000000 #endif /* Physical Memory Map */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 705a941e360..3fc70de5771 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -116,7 +116,7 @@ #define CFG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) /* PL011 Serial Configuration */ -#define CONFIG_PL011_CLOCK 24000000 +#define CFG_PL011_CLOCK 24000000 #define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ (void *)CFG_SYS_SERIAL1} -- cgit v1.3.1 From b861574bd9e7c480ceec47b77a59ed5a52b57937 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:31 -0500 Subject: global: Migrate CONFIG_PL01x_PORTS to CFG Perform a simple rename of CONFIG_PL01x_PORTS to CFG_PL01x_PORTS Signed-off-by: Tom Rini --- README | 2 +- drivers/serial/serial_pl01x.c | 2 +- include/configs/lx2160a_common.h | 2 +- include/configs/mxs.h | 2 +- include/configs/s5p4418_nanopi2.h | 2 +- include/configs/synquacer.h | 2 +- include/configs/vexpress_common.h | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/README b/README index 8354cf5699b..12672d2bfb0 100644 --- a/README +++ b/README @@ -418,7 +418,7 @@ The following options need to be configured: If you have Amba PrimeCell PL011 UARTs, set this variable to the clock speed of the UARTs. - CONFIG_PL01x_PORTS + CFG_PL01x_PORTS If you have Amba PrimeCell PL010 or PL011 UARTs on your board, define this to a list of base addresses for each (supported) diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index dd2881931df..7449e9b9043 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_DM_SERIAL -static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; +static volatile unsigned char *const port[] = CFG_PL01x_PORTS; static enum pl01x_type pl01x_type __section(".data"); static struct pl01x_regs *base_regs __section(".data"); #define NUM_PORTS (sizeof(port)/sizeof(port[0])) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index f8a20ea16f9..6f46ca78d4d 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -45,7 +45,7 @@ #define CFG_SYS_SERIAL2 0x21e0000 #define CFG_SYS_SERIAL3 0x21f0000 /*below might needs to be removed*/ -#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ +#define CFG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ (void *)CFG_SYS_SERIAL1, \ (void *)CFG_SYS_SERIAL2, \ (void *)CFG_SYS_SERIAL3 } diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 90cb1a5e4a0..6ebfee69271 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -78,7 +78,7 @@ * Conflicts with AUART driver which can be set by board. */ #define CFG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } +#define CFG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } /* Default baudrate can be overridden by board! */ /* NAND */ diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index 0e7d01925ee..2fa44e65fc1 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -77,7 +77,7 @@ * serial console configuration */ #define CFG_PL011_CLOCK 50000000 -#define CONFIG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \ +#define CFG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \ (void *)PHY_BASEADDR_UART1, \ (void *)PHY_BASEADDR_UART2, \ (void *)PHY_BASEADDR_UART3} diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 350cc69c28d..8f44c6f66a9 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -32,7 +32,7 @@ /* Serial (pl011) */ #define UART_CLK (62500000) #define CFG_PL011_CLOCK UART_CLK -#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)} +#define CFG_PL01x_PORTS {(void *)(0x2a400000)} /* Support MTD */ #define CFG_SYS_FLASH_BASE (0x08000000) diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 3fc70de5771..ba7731bfca6 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -117,7 +117,7 @@ /* PL011 Serial Configuration */ #define CFG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ +#define CFG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ (void *)CFG_SYS_SERIAL1} #define CFG_SYS_SERIAL0 V2M_UART0 -- cgit v1.3.1 From 2adbb297471b39741e3e6e2ef04c56187ccaaf68 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:33 -0500 Subject: global: Migrate CONFIG_POSTBOOTMENU to CFG Perform a simple rename of CONFIG_POSTBOOTMENU to CFG_POSTBOOTMENU Signed-off-by: Tom Rini --- cmd/bootmenu.c | 4 ++-- include/configs/nokia_rx51.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c index 3340be16325..e5a10f5d5c4 100644 --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c @@ -577,8 +577,8 @@ cleanup: free(command); } -#ifdef CONFIG_POSTBOOTMENU - run_command(CONFIG_POSTBOOTMENU, 0); +#ifdef CFG_POSTBOOTMENU + run_command(CFG_POSTBOOTMENU, 0); #endif if (efi_ret != EFI_SUCCESS || cmd_ret != CMD_RET_SUCCESS) diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 97d08685290..a64b7b34dc1 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -128,7 +128,7 @@ "bootmenu_delay=30\0" \ "" -#define CONFIG_POSTBOOTMENU \ +#define CFG_POSTBOOTMENU \ "echo;" \ "echo Extra commands:;" \ "echo run sdboot - Boot from SD card slot.;" \ -- cgit v1.3.1 From 6d38c69e835b5a918d324da16c34a697aeb3276f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:34 -0500 Subject: global: Migrate CONFIG_POWER_LTC3676_I2C_ADDR to CFG Perform a simple rename of CONFIG_POWER_LTC3676_I2C_ADDR to CFG_POWER_LTC3676_I2C_ADDR Signed-off-by: Tom Rini --- board/gateworks/gw_ventana/gw_ventana_spl.c | 4 ++-- drivers/power/pmic/pmic_ltc3676.c | 2 +- include/configs/gw_ventana.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index e85a00954ce..6ad994af1c6 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -851,8 +851,8 @@ void setup_pmic(void) } /* configure LTC3676 PMIC */ - else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) { - debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR); + else if (!i2c_probe(CFG_POWER_LTC3676_I2C_ADDR)) { + debug("probed LTC3676@0x%x\n", CFG_POWER_LTC3676_I2C_ADDR); power_ltc3676_init(i2c_pmic); p = pmic_get("LTC3676_PMIC"); if (!p || pmic_probe(p)) diff --git a/drivers/power/pmic/pmic_ltc3676.c b/drivers/power/pmic/pmic_ltc3676.c index 00c3e201cd5..af94f37b0f1 100644 --- a/drivers/power/pmic/pmic_ltc3676.c +++ b/drivers/power/pmic/pmic_ltc3676.c @@ -23,7 +23,7 @@ int power_ltc3676_init(unsigned char bus) p->name = name; p->interface = PMIC_I2C; p->number_of_regs = LTC3676_NUM_OF_REGS; - p->hw.i2c.addr = CONFIG_POWER_LTC3676_I2C_ADDR; + p->hw.i2c.addr = CFG_POWER_LTC3676_I2C_ADDR; p->hw.i2c.tx_num = 1; p->bus = bus; diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 0a9dfe736f7..85a2ad21dc0 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -31,7 +31,7 @@ * PMIC */ #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 -#define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c +#define CFG_POWER_LTC3676_I2C_ADDR 0x3c /* Various command support */ -- cgit v1.3.1 From aa3efb6c64513ad3d5eb876488a90b2ee2b8ccc0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:35 -0500 Subject: global: Migrate CONFIG_POWER_PFUZE100_I2C_ADDR to CFG Perform a simple rename of CONFIG_POWER_PFUZE100_I2C_ADDR to CFG_POWER_PFUZE100_I2C_ADDR Signed-off-by: Tom Rini --- board/gateworks/gw_ventana/gw_ventana_spl.c | 4 ++-- drivers/power/pmic/pmic_pfuze100.c | 2 +- include/configs/el6x_common.h | 2 +- include/configs/gw_ventana.h | 2 +- include/configs/imx8mq_evk.h | 2 +- include/configs/kontron_pitx_imx8m.h | 2 +- include/configs/mx6sabreauto.h | 2 +- include/configs/mx6sabresd.h | 2 +- include/configs/novena.h | 2 +- include/configs/tqma6.h | 2 +- include/configs/vining_2000.h | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 6ad994af1c6..2f046c9c0b3 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -791,8 +791,8 @@ void setup_pmic(void) i2c_set_bus_num(i2c_pmic); /* configure PFUZE100 PMIC */ - if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) { - debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR); + if (!i2c_probe(CFG_POWER_PFUZE100_I2C_ADDR)) { + debug("probed PFUZE100@0x%x\n", CFG_POWER_PFUZE100_I2C_ADDR); power_pfuze100_init(i2c_pmic); p = pmic_get("PFUZE100"); if (p && !pmic_probe(p)) { diff --git a/drivers/power/pmic/pmic_pfuze100.c b/drivers/power/pmic/pmic_pfuze100.c index c646a0c31f8..5115b55e49d 100644 --- a/drivers/power/pmic/pmic_pfuze100.c +++ b/drivers/power/pmic/pmic_pfuze100.c @@ -23,7 +23,7 @@ int power_pfuze100_init(unsigned char bus) p->name = name; p->interface = PMIC_I2C; p->number_of_regs = PFUZE100_NUM_OF_REGS; - p->hw.i2c.addr = CONFIG_POWER_PFUZE100_I2C_ADDR; + p->hw.i2c.addr = CFG_POWER_PFUZE100_I2C_ADDR; p->hw.i2c.tx_num = 1; p->bus = bus; diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index 6913a91c4c1..78af42d0450 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -17,7 +17,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 /* PMIC */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 /* Commands */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 85a2ad21dc0..ebc5d03d0d5 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -30,7 +30,7 @@ /* * PMIC */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 #define CFG_POWER_LTC3676_I2C_ADDR 0x3c /* Various command support */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index a7a51907f5c..d2de2900c06 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -18,7 +18,7 @@ #define CFG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 #endif /* ENET Config */ diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index bf590efb434..e3a021c987c 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -20,7 +20,7 @@ /* For RAW image gives a error info not panic */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 #endif /* ENET1 Config */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index da98139d7d7..05ae2fce1fd 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -36,6 +36,6 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ /* PMIC */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 #endif /* __MX6SABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 1aa8a56cceb..30d3b9d9307 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -25,7 +25,7 @@ #endif /* PMIC */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 /* USB Configs */ #ifdef CONFIG_CMD_USB diff --git a/include/configs/novena.h b/include/configs/novena.h index 5e8b7fa6217..39d3afd1c8e 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -46,7 +46,7 @@ #endif /* PMIC */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 /* UART */ #define CFG_MXC_UART_BASE UART2_BASE diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index af5a474cf31..8c75a75a9e5 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -31,7 +31,7 @@ #define CFG_I2C_MULTI_BUS #if !defined(CONFIG_DM_PMIC) -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 #define TQMA6_PFUZE100_I2C_BUS 2 #endif diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 7bfc22c043f..30654191a26 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -31,7 +31,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR /* PMIC */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 /* Network */ #define CFG_FEC_MXC_PHYADDR 0x0 -- cgit v1.3.1 From 193b3fe1756b7fcb5fa4432ef6642ba5c5004115 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:36 -0500 Subject: global: Migrate CONFIG_POWER_PFUZE3000_I2C_ADDR to CFG Perform a simple rename of CONFIG_POWER_PFUZE3000_I2C_ADDR to CFG_POWER_PFUZE3000_I2C_ADDR Signed-off-by: Tom Rini --- drivers/power/pmic/pmic_pfuze3000.c | 2 +- include/configs/cl-som-imx7.h | 2 +- include/configs/pico-imx7d.h | 2 +- include/configs/udoo_neo.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/drivers/power/pmic/pmic_pfuze3000.c b/drivers/power/pmic/pmic_pfuze3000.c index 1077fa5e9d9..a6d97252bc9 100644 --- a/drivers/power/pmic/pmic_pfuze3000.c +++ b/drivers/power/pmic/pmic_pfuze3000.c @@ -23,7 +23,7 @@ int power_pfuze3000_init(unsigned char bus) p->name = name; p->interface = PMIC_I2C; p->number_of_regs = PFUZE3000_NUM_OF_REGS; - p->hw.i2c.addr = CONFIG_POWER_PFUZE3000_I2C_ADDR; + p->hw.i2c.addr = CFG_POWER_PFUZE3000_I2C_ADDR; p->hw.i2c.tx_num = 1; p->bus = bus; diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 0a667c60b61..280ae1e9cca 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -19,7 +19,7 @@ #define IMX_FEC_BASE ENET_IPS_BASE_ADDR /* PMIC */ -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE3000_I2C_ADDR 0x08 #define CFG_SYS_I2C_PCA953X_ADDR 0x20 #define CFG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index fd8962e9f75..5774184300c 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -98,7 +98,7 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* PMIC */ -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE3000_I2C_ADDR 0x08 /* FLASH and environment organization */ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 842abb7b7a2..80386414f89 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -62,7 +62,7 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* PMIC */ -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE3000_I2C_ADDR 0x08 #define PFUZE3000_I2C_BUS 0 #endif /* __CONFIG_H */ -- cgit v1.3.1 From 7c5c137c4101c309d5c6ac2d29b202e5450960bb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:37 -0500 Subject: global: Migrate CONFIG_PRAM to CFG Perform a simple rename of CONFIG_PRAM to CFG_PRAM Signed-off-by: Tom Rini --- README | 4 ++-- common/board_f.c | 8 ++++---- common/board_r.c | 6 +++--- include/configs/M5208EVBE.h | 2 +- include/configs/M5235EVB.h | 2 +- include/configs/M5249EVB.h | 2 +- include/configs/M53017EVB.h | 2 +- include/configs/M5329EVB.h | 2 +- include/configs/M5373EVB.h | 2 +- include/configs/am43xx_evm.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/kmcent2.h | 2 +- include/configs/nokia_rx51.h | 2 +- include/configs/stmark2.h | 2 +- include/configs/ti_omap5_common.h | 2 +- 15 files changed, 21 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/README b/README index 12672d2bfb0..2d3a48e88a5 100644 --- a/README +++ b/README @@ -1069,11 +1069,11 @@ The following options need to be configured: or define CFG_ENV_FLAGS_LIST_STATIC. - Protected RAM: - CONFIG_PRAM + CFG_PRAM Define this variable to enable the reservation of "protected RAM", i. e. RAM which is not overwritten - by U-Boot. Define CONFIG_PRAM to hold the number of + by U-Boot. Define CFG_PRAM to hold the number of kB you want to reserve for pRAM. You can overwrite this default value by defining an environment variable "pram" to the number of kB you want to diff --git a/common/board_f.c b/common/board_f.c index e027248db56..2b4edf30c93 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -380,19 +380,19 @@ static int setup_dest_addr(void) return arch_setup_dest_addr(); } -#ifdef CONFIG_PRAM +#ifdef CFG_PRAM /* reserve protected RAM */ static int reserve_pram(void) { ulong reg; - reg = env_get_ulong("pram", 10, CONFIG_PRAM); + reg = env_get_ulong("pram", 10, CFG_PRAM); gd->relocaddr -= (reg << 10); /* size is in kB */ debug("Reserving %ldk for protected RAM at %08lx\n", reg, gd->relocaddr); return 0; } -#endif /* CONFIG_PRAM */ +#endif /* CFG_PRAM */ /* Round memory pointer down to next 4 kB limit */ static int reserve_round_4k(void) @@ -925,7 +925,7 @@ static const init_fnc_t init_sequence_f[] = { #ifdef CONFIG_OF_BOARD_FIXUP fix_fdt, #endif -#ifdef CONFIG_PRAM +#ifdef CFG_PRAM reserve_pram, #endif reserve_round_4k, diff --git a/common/board_r.c b/common/board_r.c index 347bb7f7c02..42060ee709d 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -533,7 +533,7 @@ static int initr_ide(void) } #endif -#if defined(CONFIG_PRAM) +#if defined(CFG_PRAM) /* * Export available size of memory for Linux, taking into account the * protected RAM at top of memory @@ -543,7 +543,7 @@ int initr_mem(void) ulong pram = 0; char memsz[32]; - pram = env_get_ulong("pram", 10, CONFIG_PRAM); + pram = env_get_ulong("pram", 10, CFG_PRAM); sprintf(memsz, "%ldk", (long int)((gd->ram_size / 1024) - pram)); env_set("mem", memsz); @@ -791,7 +791,7 @@ static init_fnc_t init_sequence_r[] = { */ last_stage_init, #endif -#if defined(CONFIG_PRAM) +#if defined(CFG_PRAM) initr_mem, #endif run_main_loop, diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index f7aba6e417f..a4fda551f1f 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -29,7 +29,7 @@ "save\0" \ "" -#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PRAM 512 /* 512 KB */ #define CFG_SYS_CLK 166666666 /* CPU Core Clock */ #define CFG_SYS_PLL_ODR 0x36 diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 049516edf4a..8939c8e7ab9 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -39,7 +39,7 @@ "save\0" \ "" -#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PRAM 512 /* 512 KB */ #define CFG_SYS_CLK 75000000 #define CFG_SYS_CPU_CLK CFG_SYS_CLK * 2 diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index c71130909fc..4fd539c0174 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -57,7 +57,7 @@ #define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) #if 0 /* test-only */ -#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ +#define CFG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ #endif /* diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index b6d82c730c6..6359915e09a 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -42,7 +42,7 @@ "save\0" \ "" -#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PRAM 512 /* 512 KB */ #define CFG_SYS_CLK 80000000 #define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index d74a636fd7f..456135bdc64 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -34,7 +34,7 @@ "save\0" \ "" -#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PRAM 512 /* 512 KB */ #define CFG_SYS_CLK 80000000 #define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index fa6f2d23e74..4e8dcb5ef7f 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -36,7 +36,7 @@ "save\0" \ "" -#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PRAM 512 /* 512 KB */ #define CFG_SYS_CLK 80000000 #define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index f43e00e8a2b..a2f73c47543 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -152,7 +152,7 @@ #if defined(CONFIG_TI_SECURE_DEVICE) /* Avoid relocating onto firewalled area at end of DRAM */ -#define CONFIG_PRAM (64 * 1024) +#define CFG_PRAM (64 * 1024) #endif /* CONFIG_TI_SECURE_DEVICE */ #endif /* __CONFIG_AM43XX_EVM_H */ diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index ffd394691a0..423bb773e93 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -9,7 +9,7 @@ #define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE -#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \ +#define CFG_PRAM ((CONFIG_KM_PNVRAM + \ CONFIG_KM_PHRAM + \ CONFIG_KM_RESERVED_PRAM) >> 10) diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index a4b6a6e555d..33ee23ece1d 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -170,7 +170,7 @@ /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable * is not valid yet, which is the case for when u-boot copies itself to RAM */ -#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10) +#define CFG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10) /* * IFC Definitions diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index a64b7b34dc1..54eea322dd3 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -169,6 +169,6 @@ #define KERNEL_ADDRESS (SDRAM_END-KERNEL_MAXSIZE) /* Reserve protected RAM for attached kernel */ -#define CONFIG_PRAM ((KERNEL_MAXSIZE >> 10)+1) +#define CFG_PRAM ((KERNEL_MAXSIZE >> 10)+1) #endif /* __CONFIG_H */ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index fe2ba9a03b4..19589be270f 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -36,7 +36,7 @@ /* Input, PCI, Flexbus, and VCO */ -#define CONFIG_PRAM 2048 /* 2048 KB */ +#define CFG_PRAM 2048 /* 2048 KB */ #define CFG_SYS_MBAR 0xFC000000 diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index e9723ed5b3d..74a39c40785 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -279,7 +279,7 @@ * firewall violation, we tell u-boot that memory is protected RAM (PRAM) */ #if (CONFIG_TI_SECURE_EMIF_REGION_START == 0) -#define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10 +#define CFG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10 #endif #else /* -- cgit v1.3.1 From d4c8dd1e6f7ca7740acd20eb3c97e051be94c375 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:39 -0500 Subject: global: Migrate CONFIG_RAMDISK_ADDR to CFG Perform a simple rename of CONFIG_RAMDISK_ADDR to CFG_RAMDISK_ADDR Signed-off-by: Tom Rini --- cmd/qfw.c | 4 ++-- doc/usage/cmd/qfw.rst | 2 +- include/configs/x86-common.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/cmd/qfw.c b/cmd/qfw.c index 95ddc4b79ec..0c49c6074e1 100644 --- a/cmd/qfw.c +++ b/cmd/qfw.c @@ -130,8 +130,8 @@ static int qemu_fwcfg_do_load(struct cmd_tbl *cmdtp, int flag, env = env_get("ramdiskaddr"); initrd_addr = env ? (void *)hextoul(env, NULL) : -#ifdef CONFIG_RAMDISK_ADDR - (void *)CONFIG_RAMDISK_ADDR; +#ifdef CFG_RAMDISK_ADDR + (void *)CFG_RAMDISK_ADDR; #else NULL; #endif diff --git a/doc/usage/cmd/qfw.rst b/doc/usage/cmd/qfw.rst index b3704b92d6d..cc0e27c2779 100644 --- a/doc/usage/cmd/qfw.rst +++ b/doc/usage/cmd/qfw.rst @@ -31,7 +31,7 @@ kernel_addr initrd_addr address to which the file specified by the -initrd parameter of QEMU shall be loaded. Defaults to environment variable *ramdiskaddr* and further to - the value of *CONFIG_RAMDISK_ADDR*. + the value of *CFG_RAMDISK_ADDR*. Examples -------- diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 5d461e8d0c6..f421ec58034 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -25,7 +25,7 @@ */ /* Default environment */ -#define CONFIG_RAMDISK_ADDR 0x4000000 +#define CFG_RAMDISK_ADDR 0x4000000 #if defined(CONFIG_GENERATE_ACPI_TABLE) || defined(CONFIG_EFI_STUB) #define CFG_OTHBOOTARGS "othbootargs=\0" #else -- cgit v1.3.1 From 3db78c830fda7cac7ef1a9b739f1a603bcfb58be Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:40 -0500 Subject: global: Migrate CONFIG_RESET_VECTOR_ADDRESS to CFG Perform a simple rename of CONFIG_RESET_VECTOR_ADDRESS to CFG_RESET_VECTOR_ADDRESS Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/Kconfig | 2 +- arch/powerpc/cpu/mpc85xx/u-boot.lds | 4 ++-- arch/powerpc/dts/kmcent2-u-boot.dtsi | 2 +- arch/powerpc/dts/u-boot.dtsi | 6 +++--- board/freescale/p1_p2_rdb_pc/README | 2 +- board/freescale/p2041rdb/README | 2 +- board/freescale/t104xrdb/README | 2 +- board/freescale/t208xqds/README | 2 +- board/freescale/t208xrdb/README | 2 +- include/configs/P1010RDB.h | 8 ++++---- include/configs/P2041RDB.h | 8 ++++---- include/configs/T102xRDB.h | 10 +++++----- include/configs/T104xRDB.h | 8 ++++---- include/configs/T208xQDS.h | 10 +++++----- include/configs/T208xRDB.h | 10 +++++----- include/configs/T4240RDB.h | 8 ++++---- include/configs/kmcent2.h | 2 +- include/configs/p1_p2_rdb_pc.h | 4 ++-- 18 files changed, 46 insertions(+), 46 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 3275d4fa9b8..6ab8a5249a4 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -931,7 +931,7 @@ config ARCH_T4240 imply FSL_SATA config MPC85XX_HAVE_RESET_VECTOR - bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc" + bool "Indicate reset vector at CFG_RESET_VECTOR_ADDRESS - 0xffc" depends on MPC85xx config BTB diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index fa3aa954cbb..3af0dfdf336 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -5,8 +5,8 @@ #include "config.h" -#ifdef CONFIG_RESET_VECTOR_ADDRESS -#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS +#ifdef CFG_RESET_VECTOR_ADDRESS +#define RESET_VECTOR_ADDRESS CFG_RESET_VECTOR_ADDRESS #else #define RESET_VECTOR_ADDRESS 0xfffffffc #endif diff --git a/arch/powerpc/dts/kmcent2-u-boot.dtsi b/arch/powerpc/dts/kmcent2-u-boot.dtsi index 28f303b749e..53bac5533f2 100644 --- a/arch/powerpc/dts/kmcent2-u-boot.dtsi +++ b/arch/powerpc/dts/kmcent2-u-boot.dtsi @@ -91,7 +91,7 @@ align = <256>; }; powerpc-mpc85xx-bootpg-resetvec { - offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; + offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>; }; }; }; diff --git a/arch/powerpc/dts/u-boot.dtsi b/arch/powerpc/dts/u-boot.dtsi index b4b5257362e..6b7375cff21 100644 --- a/arch/powerpc/dts/u-boot.dtsi +++ b/arch/powerpc/dts/u-boot.dtsi @@ -23,11 +23,11 @@ u-boot-dtb-with-ucode { align = <4>; }; -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #endif powerpc-mpc85xx-bootpg-resetvec { - offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; + offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>; }; }; }; diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README index f542decec79..fd849bfc29a 100644 --- a/board/freescale/p1_p2_rdb_pc/README +++ b/board/freescale/p1_p2_rdb_pc/README @@ -57,7 +57,7 @@ enabled in relative defconfig file, 1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required) 2. CONFIG_OF_CONTROL 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CONFIG_RESET_VECTOR_ADDRESS - 0xffc + CFG_RESET_VECTOR_ADDRESS - 0xffc If device tree support is enabled in defconfig, 1. use 'u-boot.bin' for NOR boot. diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README index 96612daeeb1..ae770277372 100644 --- a/board/freescale/p2041rdb/README +++ b/board/freescale/p2041rdb/README @@ -98,7 +98,7 @@ enabled in relative defconfig file, 1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) 2. CONFIG_OF_CONTROL 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CONFIG_RESET_VECTOR_ADDRESS - 0xffc + CFG_RESET_VECTOR_ADDRESS - 0xffc CPLD command ============ diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index e90dca41663..f312e6a3e32 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -379,7 +379,7 @@ enabled in relative defconfig file, 1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required) 2. CONFIG_OF_CONTROL 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CONFIG_RESET_VECTOR_ADDRESS - 0xffc + CFG_RESET_VECTOR_ADDRESS - 0xffc If device tree support is enabled in defconfig, 1. use 'u-boot.bin' for NOR boot. diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README index 63953d6b9b6..0d80c6901fb 100755 --- a/board/freescale/t208xqds/README +++ b/board/freescale/t208xqds/README @@ -285,7 +285,7 @@ enabled in relative defconfig file, 1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required) 2. CONFIG_OF_CONTROL 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CONFIG_RESET_VECTOR_ADDRESS - 0xffc + CFG_RESET_VECTOR_ADDRESS - 0xffc If device tree support is enabled in defconfig, 1. use 'u-boot.bin' for NOR boot. diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README index 60551f6723e..533054bfe19 100644 --- a/board/freescale/t208xrdb/README +++ b/board/freescale/t208xrdb/README @@ -281,7 +281,7 @@ enabled in relative defconfig file, 1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required) 2. CONFIG_OF_CONTROL 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CONFIG_RESET_VECTOR_ADDRESS - 0xffc + CFG_RESET_VECTOR_ADDRESS - 0xffc If device tree support is enabled in defconfig, 1. use 'u-boot.bin' for NOR boot. diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index b57e8638ab7..9efae58ce90 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -24,7 +24,7 @@ #ifdef CONFIG_SPIFLASH #ifdef CONFIG_NXP_ESBC -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc +#define CFG_RESET_VECTOR_ADDRESS 0x110bfffc #else #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) @@ -52,11 +52,11 @@ #endif #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc +#define CFG_RESET_VECTOR_ADDRESS 0x110bfffc #endif -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif /* High Level Configuration Options */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 6e755fc0a8f..28f53ae78a1 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -12,7 +12,7 @@ #define __CONFIG_H #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -20,13 +20,13 @@ #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #endif /* High Level Configuration Options */ -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 063b864f9ff..7ee46abffdb 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -28,7 +28,7 @@ #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) @@ -36,7 +36,7 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CFG_SYS_MMC_U_BOOT_DST (0x30000000) #define CFG_SYS_MMC_U_BOOT_START (0x30000000) @@ -45,8 +45,8 @@ #endif /* CONFIG_RAMBOOT_PBL */ -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif /* @@ -87,7 +87,7 @@ #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #endif /* diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 9d04d30a538..f196bd76e6e 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -29,7 +29,7 @@ #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) @@ -37,7 +37,7 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CFG_SYS_MMC_U_BOOT_DST (0x30000000) #define CFG_SYS_MMC_U_BOOT_START (0x30000000) @@ -48,8 +48,8 @@ /* High Level Configuration Options */ -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 3b98d25aa47..2023d7497f6 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -30,7 +30,7 @@ #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CFG_RESET_VECTOR_ADDRESS 0x200FFC #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) @@ -38,7 +38,7 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CFG_RESET_VECTOR_ADDRESS 0x200FFC #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CFG_SYS_MMC_U_BOOT_DST (0x00200000) #define CFG_SYS_MMC_U_BOOT_START (0x00200000) @@ -52,11 +52,11 @@ #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #endif -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif /* diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 60c2947bfc1..f213d2de770 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -30,7 +30,7 @@ #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CFG_RESET_VECTOR_ADDRESS 0x200FFC #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) @@ -38,7 +38,7 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CFG_RESET_VECTOR_ADDRESS 0x200FFC #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CFG_SYS_MMC_U_BOOT_DST (0x00200000) #define CFG_SYS_MMC_U_BOOT_START (0x00200000) @@ -52,11 +52,11 @@ #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #endif -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif /* diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 01a9f43cbae..506f1b7e268 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -16,13 +16,13 @@ #ifdef CONFIG_RAMBOOT_PBL #ifndef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #else #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CFG_RESET_VECTOR_ADDRESS 0x200FFC #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CFG_SYS_MMC_U_BOOT_DST 0x00200000 #define CFG_SYS_MMC_U_BOOT_START 0x00200000 @@ -34,8 +34,8 @@ /* High Level Configuration Options */ -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 33ee23ece1d..58dff495ac5 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -122,7 +122,7 @@ /* High Level Configuration Options */ -#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc +#define CFG_RESET_VECTOR_ADDRESS 0xebfffffc #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 41e7f53bd57..832ad9c3ece 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -105,8 +105,8 @@ #endif /* not CONFIG_TPL_BUILD */ #endif -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif #define CFG_SYS_CCSRBAR 0xffe00000 -- cgit v1.3.1 From dbfaeecf597b1fb1322f357b8253cc6198081f17 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:43 -0500 Subject: global: Migrate CONFIG_SCIF_A to CFG Perform a simple rename of CONFIG_SCIF_A to CFG_SCIF_A Signed-off-by: Tom Rini --- drivers/serial/serial_sh.c | 2 +- drivers/serial/serial_sh.h | 8 ++++---- include/configs/stout.h | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index e6c23cedff1..4671217b59a 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -274,7 +274,7 @@ U_BOOT_DRIVER(serial_sh) = { # error "Default SCIF doesn't set....." #endif -#if defined(CONFIG_SCIF_A) +#if defined(CFG_SCIF_A) #define SCIF_BASE_PORT PORT_SCIFA #elif defined(CONFIG_SCI) #define SCIF_BASE_PORT PORT_SCI diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 11deaa95116..e6ab6f1b9b7 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -92,7 +92,7 @@ struct uart_port { # define SCIF_ORER 0x0001 /* overrun error bit */ #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \ defined(CONFIG_R7S72100) -# if defined(CONFIG_SCIF_A) +# if defined(CFG_SCIF_A) # define SCIF_ORER 0x0200 # else # define SCIF_ORER 0x0001 @@ -164,7 +164,7 @@ struct uart_port { # define SCIF2_TXROOM_MAX 16 #elif defined(CONFIG_RCAR_GEN2) # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) -# if defined(CONFIG_SCIF_A) +# if defined(CFG_SCIF_A) # define SCIF_RFDC_MASK 0x007f # else # define SCIF_RFDC_MASK 0x001f @@ -380,7 +380,7 @@ SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) SCIF_FNS(DL, 0, 0, 0x30, 16) SCIF_FNS(CKS, 0, 0, 0x34, 16) -#if defined(CONFIG_SCIF_A) +#if defined(CFG_SCIF_A) SCIF_FNS(SCLSR, 0, 0, 0x14, 16) #else SCIF_FNS(SCLSR, 0, 0, 0x24, 16) @@ -491,7 +491,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk) #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) #elif defined(CONFIG_RCAR_GEN2) #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ - #if defined(CONFIG_SCIF_A) + #if defined(CFG_SCIF_A) #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */ #else #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ diff --git a/include/configs/stout.h b/include/configs/stout.h index ee1abe691bf..ea5828b950b 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -23,7 +23,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SCIF */ -#define CONFIG_SCIF_A +#define CFG_SCIF_A /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -- cgit v1.3.1 From 77d0870c2901b28e003fa256c00d8570b2066cae Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:44 -0500 Subject: global: Migrate CONFIG_SCSI_DEV_LIST to CFG Perform a simple rename of CONFIG_SCSI_DEV_LIST to CFG_SCSI_DEV_LIST Signed-off-by: Tom Rini --- drivers/scsi/scsi.c | 4 ++-- include/configs/ls1021aiot.h | 2 +- include/configs/ls1028ardb.h | 2 +- include/configs/ls1043ardb.h | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 3e769b0843f..a020a7da23a 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -18,8 +18,8 @@ #include #if !defined(CONFIG_DM_SCSI) -# ifdef CONFIG_SCSI_DEV_LIST -# define SCSI_DEV_LIST CONFIG_SCSI_DEV_LIST +# ifdef CFG_SCSI_DEV_LIST +# define SCSI_DEV_LIST CFG_SCSI_DEV_LIST # else # ifdef CONFIG_SATA_ULI5288 diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 8b5fba51c6f..53d9936f4e7 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -61,7 +61,7 @@ #ifndef PCI_DEVICE_ID_FREESCALE_AHCI #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 #endif -#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ +#define CFG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ PCI_DEVICE_ID_FREESCALE_AHCI} /* SPI */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 8c53636beac..ee4f885c534 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -52,7 +52,7 @@ /* SATA */ #define SCSI_VEND_ID 0x1b4b #define SCSI_DEV_ID 0x9170 -#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#define CFG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} /* Initial environment variables */ #ifndef SPL_NO_ENV diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index c8a6f0146aa..60362b6a4d0 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -203,7 +203,7 @@ #ifndef SPL_NO_SATA #define SCSI_VEND_ID 0x1b4b #define SCSI_DEV_ID 0x9170 -#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#define CFG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} #endif #include -- cgit v1.3.1 From 3cdd6302a5c6cc2f6b59b845f6f1fc31061b1dd2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:45 -0500 Subject: global: Migrate CONFIG_SC_TIMER_CLK to CFG Perform a simple rename of CONFIG_SC_TIMER_CLK to CFG_SC_TIMER_CLK Signed-off-by: Tom Rini --- arch/arm/mach-imx/syscounter.c | 2 +- include/configs/mx6_common.h | 2 +- include/configs/mx7_common.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c index df478a23263..129efac6fa6 100644 --- a/arch/arm/mach-imx/syscounter.c +++ b/arch/arm/mach-imx/syscounter.c @@ -65,7 +65,7 @@ int timer_init(void) struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; unsigned long val, freq; - freq = CONFIG_SC_TIMER_CLK; + freq = CFG_SC_TIMER_CLK; asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); writel(freq, &sctr->cntfid0); diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index dd8cabc2e93..0b8233de8c4 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -9,7 +9,7 @@ #include #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) -#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ +#define CFG_SC_TIMER_CLK 8000000 /* 8Mhz */ #else #ifndef CONFIG_SYS_L2CACHE_OFF #define CFG_SYS_PL310_BASE L2_PL310_BASE diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 6e14b4fbf05..a542839ce1d 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -14,7 +14,7 @@ #include /* Timer settings */ -#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ +#define CFG_SC_TIMER_CLK 8000000 /* 8Mhz */ /* Miscellaneous configurable options */ -- cgit v1.3.1 From ddc418703353f00215962bc083523784a1c01c32 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:46 -0500 Subject: global: Migrate CONFIG_SET_DFU_ALT_BUF_LEN to CFG Perform a simple rename of CONFIG_SET_DFU_ALT_BUF_LEN to CFG_SET_DFU_ALT_BUF_LEN Signed-off-by: Tom Rini --- board/samsung/common/misc.c | 2 +- include/configs/odroid.h | 2 +- include/configs/odroid_xu3.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 9c0ec29c937..5ffa216e2e5 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SET_DFU_ALT_INFO void set_dfu_alt_info(char *interface, char *devstr) { - size_t buf_size = CONFIG_SET_DFU_ALT_BUF_LEN; + size_t buf_size = CFG_SET_DFU_ALT_BUF_LEN; ALLOC_CACHE_ALIGN_BUFFER(char, buf, buf_size); char *alt_info = "Settings not found!"; char *status = "error!\n"; diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 3ac13a65d63..560a23c23ef 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -37,7 +37,7 @@ ""PARTS_BOOT" part 0 1;" \ ""PARTS_ROOT" part 0 2\0" \ -#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) +#define CFG_SET_DFU_ALT_BUF_LEN (SZ_1K) #define CFG_DFU_ALT_BOOT_EMMC \ "u-boot raw 0x3e 0x800 mmcpart 1;" \ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 7304851d0f3..58b5ee6ea0a 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -49,7 +49,7 @@ "params.bin raw 0x1880 0x20\0" /* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */ -#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) +#define CFG_SET_DFU_ALT_BUF_LEN (SZ_1K) /* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ #define CFG_ODROID_REV_AIN 9 -- cgit v1.3.1 From 24513c3ac85456e8c8256b83ecc44ccaedcee65a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:47 -0500 Subject: global: Migrate CONFIG_SH_ETHER_ALIGNE_SIZE to CFG Perform a simple rename of CONFIG_SH_ETHER_ALIGNE_SIZE to CFG_SH_ETHER_ALIGNE_SIZE Signed-off-by: Tom Rini --- drivers/net/sh_eth.c | 4 ++-- drivers/net/sh_eth.h | 16 ++++++++-------- include/configs/alt.h | 2 +- include/configs/condor.h | 2 +- include/configs/gose.h | 2 +- include/configs/grpeach.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/lager.h | 2 +- include/configs/porter.h | 2 +- include/configs/silk.h | 2 +- include/configs/stout.h | 2 +- 11 files changed, 19 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 0c584a23b97..90e47d93aad 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -41,7 +41,7 @@ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #define flush_cache_wback(addr, len) \ flush_dcache_range((unsigned long)addr, \ - (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE))) + (unsigned long)(addr + ALIGN(len, CFG_SH_ETHER_ALIGNE_SIZE))) #else #define flush_cache_wback(...) #endif @@ -49,7 +49,7 @@ #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) #define invalidate_cache(addr, len) \ { \ - unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \ + unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE; \ unsigned long start, end; \ \ start = (unsigned long)addr; \ diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 520f7f73257..1c07610e1ac 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -29,8 +29,8 @@ #endif /* defined(CONFIG_SH) */ /* base padding size is 16 */ -#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 16 +#ifndef CFG_SH_ETHER_ALIGNE_SIZE +#define CFG_SH_ETHER_ALIGNE_SIZE 16 #endif /* Number of supported ports */ @@ -47,7 +47,7 @@ /* The size of the tx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) +#define TX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12) /* Tx descriptor. We always use 3 bytes of padding */ struct tx_desc_s { @@ -62,9 +62,9 @@ struct tx_desc_s { /* The size of the rx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) +#define RX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12) /* aligned cache line size */ -#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) +#define RX_BUF_ALIGNE_SIZE (CFG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) /* Rx descriptor. We always use 4 bytes of padding */ struct rx_desc_s { @@ -388,11 +388,11 @@ enum DMAC_M_BIT { #endif }; -#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64 +#if CFG_SH_ETHER_ALIGNE_SIZE == 64 # define EMDR_DESC EDMR_DL1 -#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32 +#elif CFG_SH_ETHER_ALIGNE_SIZE == 32 # define EMDR_DESC EDMR_DL0 -#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ +#elif CFG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ # define EMDR_DESC 0 #endif diff --git a/include/configs/alt.h b/include/configs/alt.h index 29f4d06b7f8..f06ceed47f0 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -26,7 +26,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/condor.h b/include/configs/condor.h index 819184996e6..6d7c788163d 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -19,7 +19,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ /* XTAL_CLK : 33.33MHz */ diff --git a/include/configs/gose.h b/include/configs/gose.h index 45f0ec6f6a0..93157de470b 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -25,7 +25,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index dd6b22de7ba..5b91e6ff039 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -22,6 +22,6 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 #endif /* __GRPEACH_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 61ff80d2c98..ff02a875013 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -25,7 +25,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/lager.h b/include/configs/lager.h index 777d5b94d1c..83e8705dfe7 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -26,7 +26,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/porter.h b/include/configs/porter.h index 202bd914d50..8f834f2c7eb 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -27,7 +27,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/silk.h b/include/configs/silk.h index 9114a057582..80fce05b399 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -27,7 +27,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/stout.h b/include/configs/stout.h index ea5828b950b..d8f0fb18563 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -31,7 +31,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ -- cgit v1.3.1 From c253cea724555890f533c8446fc53eff01ec39a0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:48 -0500 Subject: global: Migrate CONFIG_SH_ETHER_CACHE_INVALIDATE to CFG Perform a simple rename of CONFIG_SH_ETHER_CACHE_INVALIDATE to CFG_SH_ETHER_CACHE_INVALIDATE Signed-off-by: Tom Rini --- drivers/net/sh_eth.c | 2 +- include/configs/alt.h | 2 +- include/configs/condor.h | 2 +- include/configs/gose.h | 2 +- include/configs/grpeach.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/lager.h | 2 +- include/configs/porter.h | 2 +- include/configs/silk.h | 2 +- include/configs/stout.h | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 90e47d93aad..63b21969d5c 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -46,7 +46,7 @@ #define flush_cache_wback(...) #endif -#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) +#if defined(CFG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) #define invalidate_cache(addr, len) \ { \ unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE; \ diff --git a/include/configs/alt.h b/include/configs/alt.h index f06ceed47f0..7a29157ef44 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -25,7 +25,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/condor.h b/include/configs/condor.h index 6d7c788163d..fa3edef9b30 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -18,7 +18,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/gose.h b/include/configs/gose.h index 93157de470b..e54f4b24e04 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -24,7 +24,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 5b91e6ff039..5ae17f70e90 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -21,7 +21,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 #endif /* __GRPEACH_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index ff02a875013..1d8aa6def88 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -24,7 +24,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/lager.h b/include/configs/lager.h index 83e8705dfe7..bb8cc5fecb7 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -25,7 +25,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/porter.h b/include/configs/porter.h index 8f834f2c7eb..143e9a4672f 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -26,7 +26,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/silk.h b/include/configs/silk.h index 80fce05b399..2d1e23c2745 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -26,7 +26,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/stout.h b/include/configs/stout.h index d8f0fb18563..9e05a7ae6f9 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -30,7 +30,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ -- cgit v1.3.1 From ff53ecc3877c6f4b1cc035a44b43b9c50e1fabc8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:49 -0500 Subject: global: Migrate CONFIG_SH_ETHER_CACHE_WRITEBACK to CFG Perform a simple rename of CONFIG_SH_ETHER_CACHE_WRITEBACK to CFG_SH_ETHER_CACHE_WRITEBACK Signed-off-by: Tom Rini --- README | 2 +- drivers/net/sh_eth.c | 2 +- include/configs/alt.h | 2 +- include/configs/condor.h | 2 +- include/configs/gose.h | 2 +- include/configs/grpeach.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/lager.h | 2 +- include/configs/porter.h | 2 +- include/configs/silk.h | 2 +- include/configs/stout.h | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/README b/README index 2d3a48e88a5..5f688d70f32 100644 --- a/README +++ b/README @@ -547,7 +547,7 @@ The following options need to be configured: CONFIG_SH_ETHER_PHY_ADDR Define the ETH PHY's address - CONFIG_SH_ETHER_CACHE_WRITEBACK + CFG_SH_ETHER_CACHE_WRITEBACK If this option is set, the driver enables cache flush. - TPM Support: diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 63b21969d5c..0053733075e 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -37,7 +37,7 @@ # error "Please define CONFIG_SH_ETHER_PHY_ADDR" #endif -#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \ +#if defined(CFG_SH_ETHER_CACHE_WRITEBACK) && \ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #define flush_cache_wback(addr, len) \ flush_dcache_range((unsigned long)addr, \ diff --git a/include/configs/alt.h b/include/configs/alt.h index 7a29157ef44..2b783252734 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -24,7 +24,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/condor.h b/include/configs/condor.h index fa3edef9b30..3f99cbf9dab 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -17,7 +17,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/gose.h b/include/configs/gose.h index e54f4b24e04..45a537341b0 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -23,7 +23,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 5ae17f70e90..3fde6140709 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -20,7 +20,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 1d8aa6def88..b3b6f03e08d 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -23,7 +23,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/lager.h b/include/configs/lager.h index bb8cc5fecb7..16d15ccdd91 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -24,7 +24,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/porter.h b/include/configs/porter.h index 143e9a4672f..f217141af8c 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -25,7 +25,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/silk.h b/include/configs/silk.h index 2d1e23c2745..09c23d379e9 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -25,7 +25,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/stout.h b/include/configs/stout.h index 9e05a7ae6f9..dd44b3e6d00 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -29,7 +29,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 -- cgit v1.3.1 From 7c480bab146f830220f1feef00ad1b9a5a64c6cb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:50 -0500 Subject: global: Migrate CONFIG_SH_ETHER_PHY_ADDR to CFG Perform a simple rename of CONFIG_SH_ETHER_PHY_ADDR to CFG_SH_ETHER_PHY_ADDR Signed-off-by: Tom Rini --- README | 2 +- drivers/net/sh_eth.c | 6 +++--- include/configs/alt.h | 2 +- include/configs/condor.h | 2 +- include/configs/gose.h | 2 +- include/configs/grpeach.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/lager.h | 2 +- include/configs/porter.h | 2 +- include/configs/silk.h | 2 +- include/configs/stout.h | 2 +- 11 files changed, 13 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/README b/README index 5f688d70f32..217fbaf5575 100644 --- a/README +++ b/README @@ -544,7 +544,7 @@ The following options need to be configured: CONFIG_SH_ETHER_USE_PORT Define the number of ports to be used - CONFIG_SH_ETHER_PHY_ADDR + CFG_SH_ETHER_PHY_ADDR Define the ETH PHY's address CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 0053733075e..3bf94cb2f7e 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -33,8 +33,8 @@ #ifndef CONFIG_SH_ETHER_USE_PORT # error "Please define CONFIG_SH_ETHER_USE_PORT" #endif -#ifndef CONFIG_SH_ETHER_PHY_ADDR -# error "Please define CONFIG_SH_ETHER_PHY_ADDR" +#ifndef CFG_SH_ETHER_PHY_ADDR +# error "Please define CFG_SH_ETHER_PHY_ADDR" #endif #if defined(CFG_SH_ETHER_CACHE_WRITEBACK) && \ @@ -694,7 +694,7 @@ static int sh_ether_probe(struct udevice *udev) priv->bus = miiphy_get_dev_by_name(udev->name); eth->port = CONFIG_SH_ETHER_USE_PORT; - eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; + eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR; eth->port_info[eth->port].iobase = (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port); diff --git a/include/configs/alt.h b/include/configs/alt.h index 2b783252734..06ab5ce669b 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -22,7 +22,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/condor.h b/include/configs/condor.h index 3f99cbf9dab..43b88f12721 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -15,7 +15,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/gose.h b/include/configs/gose.h index 45a537341b0..5184db41061 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -21,7 +21,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 3fde6140709..8ba9b73672c 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -18,7 +18,7 @@ /* Network interface */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0 +#define CFG_SH_ETHER_PHY_ADDR 0 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index b3b6f03e08d..2910336def6 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -21,7 +21,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/lager.h b/include/configs/lager.h index 16d15ccdd91..815239a73bd 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -22,7 +22,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/porter.h b/include/configs/porter.h index f217141af8c..f732aeb47b5 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -23,7 +23,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/silk.h b/include/configs/silk.h index 09c23d379e9..005eed15494 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -23,7 +23,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/stout.h b/include/configs/stout.h index dd44b3e6d00..cf90e4d4645 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -27,7 +27,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE -- cgit v1.3.1 From 85b55117085fd6912f1c06eb74d864c44f515e66 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:51 -0500 Subject: global: Migrate CONFIG_SH_ETHER_PHY_MODE to CFG Perform a simple rename of CONFIG_SH_ETHER_PHY_MODE to CFG_SH_ETHER_PHY_MODE Signed-off-by: Tom Rini --- include/configs/alt.h | 2 +- include/configs/condor.h | 2 +- include/configs/gose.h | 2 +- include/configs/grpeach.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/lager.h | 2 +- include/configs/porter.h | 2 +- include/configs/silk.h | 2 +- include/configs/stout.h | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/configs/alt.h b/include/configs/alt.h index 06ab5ce669b..53c31562a5d 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -23,7 +23,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/condor.h b/include/configs/condor.h index 43b88f12721..2c9817cf02c 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -16,7 +16,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/gose.h b/include/configs/gose.h index 5184db41061..ed7dd70dd96 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -22,7 +22,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 8ba9b73672c..6a11aa61f0f 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -19,7 +19,7 @@ /* Network interface */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 2910336def6..31d0795f07f 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -22,7 +22,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/lager.h b/include/configs/lager.h index 815239a73bd..991fc9020ee 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -23,7 +23,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/porter.h b/include/configs/porter.h index f732aeb47b5..1587c5c5397 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -24,7 +24,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/silk.h b/include/configs/silk.h index 005eed15494..21100c46b1c 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -24,7 +24,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/stout.h b/include/configs/stout.h index cf90e4d4645..51f4420ed6f 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -28,7 +28,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 -- cgit v1.3.1 From 97148cb6142b2507972459b8f578c04717a52c40 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:52 -0500 Subject: global: Migrate CONFIG_SH_ETHER_USE_PORT to CFG Perform a simple rename of CONFIG_SH_ETHER_USE_PORT to CFG_SH_ETHER_USE_PORT Signed-off-by: Tom Rini --- README | 2 +- drivers/net/sh_eth.c | 6 +++--- include/configs/alt.h | 2 +- include/configs/condor.h | 2 +- include/configs/gose.h | 2 +- include/configs/grpeach.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/lager.h | 2 +- include/configs/porter.h | 2 +- include/configs/silk.h | 2 +- include/configs/stout.h | 2 +- 11 files changed, 13 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/README b/README index 217fbaf5575..a9b225e45ec 100644 --- a/README +++ b/README @@ -541,7 +541,7 @@ The following options need to be configured: CONFIG_SH_ETHER Support for Renesas on-chip Ethernet controller - CONFIG_SH_ETHER_USE_PORT + CFG_SH_ETHER_USE_PORT Define the number of ports to be used CFG_SH_ETHER_PHY_ADDR diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 3bf94cb2f7e..8f162ca58fb 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -30,8 +30,8 @@ #include "sh_eth.h" -#ifndef CONFIG_SH_ETHER_USE_PORT -# error "Please define CONFIG_SH_ETHER_USE_PORT" +#ifndef CFG_SH_ETHER_USE_PORT +# error "Please define CFG_SH_ETHER_USE_PORT" #endif #ifndef CFG_SH_ETHER_PHY_ADDR # error "Please define CFG_SH_ETHER_PHY_ADDR" @@ -693,7 +693,7 @@ static int sh_ether_probe(struct udevice *udev) priv->bus = miiphy_get_dev_by_name(udev->name); - eth->port = CONFIG_SH_ETHER_USE_PORT; + eth->port = CFG_SH_ETHER_USE_PORT; eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR; eth->port_info[eth->port].iobase = (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port); diff --git a/include/configs/alt.h b/include/configs/alt.h index 53c31562a5d..8f03762583e 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -21,7 +21,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/condor.h b/include/configs/condor.h index 2c9817cf02c..50c8d173383 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -14,7 +14,7 @@ /* Environment compatibility */ /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/gose.h b/include/configs/gose.h index ed7dd70dd96..7ae0726518d 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -20,7 +20,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024) /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 6a11aa61f0f..8de4a36e931 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -17,7 +17,7 @@ #define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) /* Network interface */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 31d0795f07f..d47d70178cc 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -20,7 +20,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/lager.h b/include/configs/lager.h index 991fc9020ee..2577c7a7da6 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -21,7 +21,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/porter.h b/include/configs/porter.h index 1587c5c5397..2cb430be8b0 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -22,7 +22,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/silk.h b/include/configs/silk.h index 21100c46b1c..7bed32d8553 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -22,7 +22,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/stout.h b/include/configs/stout.h index 51f4420ed6f..1278ba63f4f 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -26,7 +26,7 @@ #define CFG_SCIF_A /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK -- cgit v1.3.1 From 59f3a09a6c86e99f9790f9b534465b035863a5b4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:53 -0500 Subject: global: Migrate CONFIG_SLIC to CFG Perform a simple rename of CONFIG_SLIC to CFG_SLIC Signed-off-by: Tom Rini --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +- include/configs/p1_p2_rdb_pc.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index df9f6ae4732..4d7d042eaf3 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -187,7 +187,7 @@ void board_gpio_init(void) setbits_be32(&pgpio->gpdat, 0x00080000); #endif -#ifdef CONFIG_SLIC +#ifdef CFG_SLIC /* reset SLIC */ setbits_be32(&pgpio->gpdir, 0x00040000); setbits_be32(&pgpio->gpdat, 0x00040000); diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 832ad9c3ece..be768019829 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -13,7 +13,7 @@ #include #if defined(CONFIG_TARGET_P1020RDB_PC) -#define CONFIG_SLIC +#define CFG_SLIC #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0x5c #define __SW_BOOT_SPI 0x1c @@ -42,7 +42,7 @@ * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off */ #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_SLIC +#define CFG_SLIC #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0x64 #define __SW_BOOT_SPI 0x34 -- cgit v1.3.1 From 3e204427c8369d6c34c2beaac29a539a55c7be4f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:54 -0500 Subject: global: Migrate CONFIG_SMP_PEN_ADDR to CFG Perform a simple rename of CONFIG_SMP_PEN_ADDR to CFG_SMP_PEN_ADDR Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- board/samsung/arndale/arndale.c | 4 ++-- include/configs/arndale.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/ls1021aiot.h | 2 +- include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atwr.h | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index a303039ba50..9004074da2c 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -205,11 +205,11 @@ ENTRY(_nonsec_init) bx lr ENDPROC(_nonsec_init) -#ifdef CONFIG_SMP_PEN_ADDR +#ifdef CFG_SMP_PEN_ADDR /* void __weak smp_waitloop(unsigned previous_address); */ WEAK(smp_waitloop) wfi - ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address + ldr r1, =CFG_SMP_PEN_ADDR @ load start address ldr r1, [r1] #ifdef CONFIG_PEN_ADDR_BIG_ENDIAN rev r1, r1 diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index a992dc68429..3ebf600e1d7 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -112,10 +112,10 @@ int checkboard(void) } #endif -#ifdef CONFIG_SMP_PEN_ADDR +#ifdef CFG_SMP_PEN_ADDR void smp_set_core_boot_addr(unsigned long addr, int corenr) { - writel(addr, CONFIG_SMP_PEN_ADDR); + writel(addr, CFG_SMP_PEN_ADDR); /* make sure this write is really executed */ __asm__ volatile ("dsb\n"); diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 8acc525b11c..b56effcd411 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -16,7 +16,7 @@ /* Miscellaneous configurable options */ -#define CONFIG_SMP_PEN_ADDR 0x02020000 +#define CFG_SMP_PEN_ADDR 0x02020000 /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CFG_ARM_GIC_BASE_ADDRESS 0x10480000 diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 423bb773e93..15ef68a0507 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -158,7 +158,7 @@ {1, {I2C_NULL_HOP} }, \ } -#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CFG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 53d9936f4e7..83ab94ec444 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -68,7 +68,7 @@ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CFG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 78432e55811..e4e5522a238 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -242,7 +242,7 @@ * MMC */ -#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CFG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a387eeab472..eb8fb042723 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -133,7 +133,7 @@ /* GPIO */ -#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CFG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 -- cgit v1.3.1 From 6786ce1ce14feb4d02854a0c04bc0cce505be46e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:55 -0500 Subject: global: Migrate CONFIG_STACKBASE to CFG Perform a simple rename of CONFIG_STACKBASE to CFG_STACKBASE Signed-off-by: Tom Rini --- include/configs/tegra-common.h | 2 +- include/configs/tegra114-common.h | 2 +- include/configs/tegra124-common.h | 2 +- include/configs/tegra20-common.h | 2 +- include/configs/tegra30-common.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 66cf7ae5847..bde7ffce008 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -45,7 +45,7 @@ #define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ #ifndef CONFIG_ARM64 -#define CFG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE +#define CFG_SYS_INIT_RAM_ADDR CFG_STACKBASE #define CFG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN /* Defines for SPL */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 87ec1f5a99d..ab4fa5504c5 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -15,7 +15,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_STACKBASE 0x83800000 /* 56MB */ +#define CFG_STACKBASE 0x83800000 /* 56MB */ /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 0485fea6ccb..b413e251212 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -17,7 +17,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_STACKBASE 0x83800000 /* 56MB */ +#define CFG_STACKBASE 0x83800000 /* 56MB */ /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 617bfb2197c..a313ac2041a 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -16,7 +16,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_STACKBASE 0x03800000 /* 56MB */ +#define CFG_STACKBASE 0x03800000 /* 56MB */ /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 04fcf11ed82..c57d2d157e3 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -16,7 +16,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_STACKBASE 0x83800000 /* 56MB */ +#define CFG_STACKBASE 0x83800000 /* 56MB */ /* * Memory layout for where various images get loaded by boot scripts: -- cgit v1.3.1 From e02e5e5188b94a084e46fccf455026cef4c6d01a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:56 -0500 Subject: global: Migrate CONFIG_STD_DEVICES_SETTINGS to CFG Perform a simple rename of CONFIG_STD_DEVICES_SETTINGS to CFG_STD_DEVICES_SETTINGS Signed-off-by: Tom Rini --- include/configs/bayleybay.h | 2 +- include/configs/cherryhill.h | 2 +- include/configs/chromebook_coral.h | 4 ++-- include/configs/chromebook_samus.h | 4 ++-- include/configs/conga-qeval20-qa3-e3845.h | 2 +- include/configs/coreboot.h | 2 +- include/configs/cougarcanyon2.h | 2 +- include/configs/crownbay.h | 2 +- include/configs/dfi-bt700.h | 2 +- include/configs/efi-x86_app.h | 2 +- include/configs/efi-x86_payload.h | 2 +- include/configs/galileo.h | 2 +- include/configs/minnowmax.h | 2 +- include/configs/qemu-x86.h | 2 +- include/configs/slimbootloader.h | 4 ++-- include/configs/som-db5800-som-6867.h | 2 +- include/configs/theadorable-x86-common.h | 2 +- include/configs/x86-chromebook.h | 2 +- include/configs/x86-common.h | 2 +- 19 files changed, 22 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h index b347125f2fa..b0df328cd84 100644 --- a/include/configs/bayleybay.h +++ b/include/configs/bayleybay.h @@ -12,7 +12,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/cherryhill.h b/include/configs/cherryhill.h index 726c43d35ea..d6ce70a96ae 100644 --- a/include/configs/cherryhill.h +++ b/include/configs/cherryhill.h @@ -8,7 +8,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" diff --git a/include/configs/chromebook_coral.h b/include/configs/chromebook_coral.h index d14c1d445b2..43fdc394416 100644 --- a/include/configs/chromebook_coral.h +++ b/include/configs/chromebook_coral.h @@ -13,8 +13,8 @@ #include #include -#undef CONFIG_STD_DEVICES_SETTINGS -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ +#undef CFG_STD_DEVICES_SETTINGS +#define CFG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" diff --git a/include/configs/chromebook_samus.h b/include/configs/chromebook_samus.h index e29be3fda4a..03a1033c573 100644 --- a/include/configs/chromebook_samus.h +++ b/include/configs/chromebook_samus.h @@ -15,8 +15,8 @@ #include #include -#undef CONFIG_STD_DEVICES_SETTINGS -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ +#undef CFG_STD_DEVICES_SETTINGS +#define CFG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h index 6f431725269..60617e6fec2 100644 --- a/include/configs/conga-qeval20-qa3-e3845.h +++ b/include/configs/conga-qeval20-qa3-e3845.h @@ -12,7 +12,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index f73004386fd..b4f49bf5289 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -15,7 +15,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h index b64c7df1b25..31639e48da8 100644 --- a/include/configs/cougarcanyon2.h +++ b/include/configs/cougarcanyon2.h @@ -8,7 +8,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vga\0" \ "stderr=serial,vga\0" diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index ff74deb3d40..387bb8800e8 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -12,7 +12,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index d10422b6c1c..05389a435be 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -16,7 +16,7 @@ /* Use BayTrail internal HS UART which is memory-mapped */ #endif -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" diff --git a/include/configs/efi-x86_app.h b/include/configs/efi-x86_app.h index 17a78514026..843ed8b9d1d 100644 --- a/include/configs/efi-x86_app.h +++ b/include/configs/efi-x86_app.h @@ -8,7 +8,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=vidconsole\0" \ "stderr=vidconsole\0" diff --git a/include/configs/efi-x86_payload.h b/include/configs/efi-x86_payload.h index f50c2ce4dd0..c72b067c367 100644 --- a/include/configs/efi-x86_payload.h +++ b/include/configs/efi-x86_payload.h @@ -12,7 +12,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/galileo.h b/include/configs/galileo.h index 472f236b9b6..0380ac287be 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -14,7 +14,7 @@ /* ns16550 UART is memory-mapped in Quark SoC */ -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 6c15c72efda..4a12c2f72c6 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -12,7 +12,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" \ "usb_pgood_delay=40\0" diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index 5cd13887084..33263a46a40 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -22,7 +22,7 @@ #include #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/slimbootloader.h b/include/configs/slimbootloader.h index 748a423b083..20b99a1021d 100644 --- a/include/configs/slimbootloader.h +++ b/include/configs/slimbootloader.h @@ -8,7 +8,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS \ +#define CFG_STD_DEVICES_SETTINGS \ "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial\0" \ "stderr=serial\0" @@ -18,7 +18,7 @@ */ #undef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ - CONFIG_STD_DEVICES_SETTINGS \ + CFG_STD_DEVICES_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=0x4000000\0" \ diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h index f0970921367..b2e7aa1514c 100644 --- a/include/configs/som-db5800-som-6867.h +++ b/include/configs/som-db5800-som-6867.h @@ -12,7 +12,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h index 746995179f9..b23b8783076 100644 --- a/include/configs/theadorable-x86-common.h +++ b/include/configs/theadorable-x86-common.h @@ -11,7 +11,7 @@ #ifndef __THEADORABLE_X86_COMMON_H #define __THEADORABLE_X86_COMMON_H -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 9df3bfd527f..41fb499ae4f 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -12,7 +12,7 @@ #define VIDEO_IO_OFFSET 0 -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index f421ec58034..c1c5a09a35c 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -44,7 +44,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ DISTRO_BOOTENV \ - CONFIG_STD_DEVICES_SETTINGS \ + CFG_STD_DEVICES_SETTINGS \ SPLASH_SETTINGS \ "pciconfighost=1\0" \ "netdev=eth0\0" \ -- cgit v1.3.1 From d8964b3e1d7233a1b45679c57985575ec0056022 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:57 -0500 Subject: global: Migrate CONFIG_SYS_I2C_DIRECT_BUS to CFG Perform a simple rename of CONFIG_SYS_I2C_DIRECT_BUS to CFG_SYS_I2C_DIRECT_BUS Signed-off-by: Tom Rini --- README | 4 ++-- cmd/i2c.c | 4 ++-- drivers/i2c/i2c_core.c | 10 +++++----- include/i2c.h | 8 ++++---- 4 files changed, 13 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/README b/README index a9b225e45ec..fe571f7ef0a 100644 --- a/README +++ b/README @@ -843,7 +843,7 @@ The following options need to be configured: CFG_SYS_NUM_I2C_BUSES Hold the number of i2c buses you want to use. - CONFIG_SYS_I2C_DIRECT_BUS + CFG_SYS_I2C_DIRECT_BUS define this, if you don't use i2c muxes on your hardware. if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can omit this define. @@ -855,7 +855,7 @@ The following options need to be configured: CFG_SYS_I2C_BUSES hold a list of buses you want to use, only used if - CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example + CFG_SYS_I2C_DIRECT_BUS is not defined, for example a board with CFG_SYS_I2C_MAX_HOPS = 1 and CFG_SYS_NUM_I2C_BUSES = 9: diff --git a/cmd/i2c.c b/cmd/i2c.c index f204061cf09..dd803ee2271 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -1699,7 +1699,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, for (i = 0; i < CFG_SYS_NUM_I2C_BUSES; i++) { printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name); -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS int j; for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) { @@ -1735,7 +1735,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, return -1; } printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name); -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS int j; for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) { if (i2c_bus[i].next_hop[j].chip == 0) diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 7f65db23205..fe0cd75d94a 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -33,14 +33,14 @@ struct i2c_adapter *i2c_get_adapter(int index) return i2c_adap_p; } -#if !defined(CONFIG_SYS_I2C_DIRECT_BUS) +#if !defined(CFG_SYS_I2C_DIRECT_BUS) struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] = CFG_SYS_I2C_BUSES; #endif DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS /* * i2c_mux_set() * ------------- @@ -237,7 +237,7 @@ int i2c_set_bus_num(unsigned int bus) if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0)) return 0; -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS if (bus >= CFG_SYS_NUM_I2C_BUSES) return -1; #endif @@ -249,7 +249,7 @@ int i2c_set_bus_num(unsigned int bus) return -2; } -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS i2c_mux_disconnect_all(); #endif @@ -257,7 +257,7 @@ int i2c_set_bus_num(unsigned int bus) if (I2C_ADAP->init_done == 0) i2c_init_bus(bus, I2C_ADAP->speed, I2C_ADAP->slaveaddr); -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS i2c_mux_set_all(); #endif return 0; diff --git a/include/i2c.h b/include/i2c.h index 3811b26c08e..ef3820eaba7 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -635,12 +635,12 @@ void i2c_early_init_f(void); #if !defined(CFG_SYS_I2C_MAX_HOPS) /* no muxes used bus = i2c adapters */ -#define CONFIG_SYS_I2C_DIRECT_BUS 1 +#define CFG_SYS_I2C_DIRECT_BUS 1 #define CFG_SYS_I2C_MAX_HOPS 0 #define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) #else /* we use i2c muxes */ -#undef CONFIG_SYS_I2C_DIRECT_BUS +#undef CFG_SYS_I2C_DIRECT_BUS #endif /* define the I2C bus number for RTC and DTT if not already done */ @@ -691,7 +691,7 @@ struct i2c_adapter { struct i2c_adapter *i2c_get_adapter(int index); -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS struct i2c_mux { int id; char name[16]; @@ -720,7 +720,7 @@ extern struct i2c_bus_hose i2c_bus[]; #define I2C_ADAP I2C_ADAP_NR(gd->cur_i2c_bus) #define I2C_ADAP_HWNR (I2C_ADAP->hwadapnr) -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS #define I2C_MUX_PCA9540_ID 1 #define I2C_MUX_PCA9540 {I2C_MUX_PCA9540_ID, "PCA9540B"} #define I2C_MUX_PCA9542_ID 2 -- cgit v1.3.1 From e660e972c44f53c8d90dfcb2d6b3564b325bec66 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:58 -0500 Subject: global: Migrate CONFIG_TEGRA_BOARD_STRING to CFG Perform a simple rename of CONFIG_TEGRA_BOARD_STRING to CFG_TEGRA_BOARD_STRING Signed-off-by: Tom Rini --- arch/arm/mach-tegra/board2.c | 2 +- include/configs/beaver.h | 2 +- include/configs/cardhu.h | 2 +- include/configs/cei-tk1-som.h | 2 +- include/configs/dalmore.h | 2 +- include/configs/harmony.h | 2 +- include/configs/jetson-tk1.h | 2 +- include/configs/medcom-wide.h | 2 +- include/configs/nyan-big.h | 2 +- include/configs/p2371-0000.h | 2 +- include/configs/p2371-2180.h | 2 +- include/configs/p2571.h | 2 +- include/configs/p2771-0000.h | 2 +- include/configs/p3450-0000.h | 2 +- include/configs/paz00.h | 2 +- include/configs/plutux.h | 2 +- include/configs/seaboard.h | 2 +- include/configs/tec-ng.h | 2 +- include/configs/tec.h | 2 +- include/configs/trimslice.h | 2 +- include/configs/venice2.h | 2 +- include/configs/ventana.h | 2 +- 22 files changed, 22 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 54bbd8a776e..c7a45f4ff82 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -89,7 +89,7 @@ int checkboard(void) { int board_id = tegra_board_id(); - printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); + printf("Board: %s", CFG_TEGRA_BOARD_STRING); if (board_id != -1) printf(", ID: %d\n", board_id); printf("\n"); diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 7e0e4779607..e622b7127e3 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -11,7 +11,7 @@ #include "tegra30-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Beaver" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Beaver" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 64d713a1969..82729eb95cf 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -11,7 +11,7 @@ #include "tegra30-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Cardhu" #define BOARD_EXTRA_ENV_SETTINGS \ "board_name=cardhu-a04\0" \ diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index e49eb602081..fbd38b77fe5 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -16,7 +16,7 @@ #include "tegra124-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "CEI tk1-som" +#define CFG_TEGRA_BOARD_STRING "CEI tk1-som" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index c9009e39623..095554157fa 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -11,7 +11,7 @@ #include "tegra114-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Dalmore" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Dalmore" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/harmony.h b/include/configs/harmony.h index a1a66bfb64e..cae7acdb70b 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -11,7 +11,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Harmony" /* Board-specific serial config */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index aa9e1d811a5..9858f8ff2b5 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -12,7 +12,7 @@ #include "tegra124-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index efac0febdf8..8dbe741278a 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -12,7 +12,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide" +#define CFG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index e885526e625..c04d402deb0 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -12,7 +12,7 @@ #include "tegra124-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big" +#define CFG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index f426889e1c4..a29d7135d0b 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -12,7 +12,7 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" +#define CFG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" /* Board-specific serial config */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 24adf4e13f0..0b077aba659 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -12,7 +12,7 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-2180" +#define CFG_TEGRA_BOARD_STRING "NVIDIA P2371-2180" /* Board-specific serial config */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 8a1e7d9b968..5155aa7b1dd 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -12,7 +12,7 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571" +#define CFG_TEGRA_BOARD_STRING "NVIDIA P2571" /* Board-specific serial config */ diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h index 84cdd571962..e409cc3896d 100644 --- a/include/configs/p2771-0000.h +++ b/include/configs/p2771-0000.h @@ -11,7 +11,7 @@ #include "tegra186-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" +#define CFG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h index 078d35dde2c..e60f42eaa72 100644 --- a/include/configs/p3450-0000.h +++ b/include/configs/p3450-0000.h @@ -11,7 +11,7 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-0000" +#define CFG_TEGRA_BOARD_STRING "NVIDIA P3450-0000" /* Board-specific serial config */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 898167009f6..950b3217642 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -13,7 +13,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Compal Paz00" +#define CFG_TEGRA_BOARD_STRING "Compal Paz00" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 1d8ac618c0b..30bfce9f503 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -12,7 +12,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux" +#define CFG_TEGRA_BOARD_STRING "Avionic Design Plutux" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index e5d672746b1..8e98620422d 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -12,7 +12,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Seaboard" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index ae879abe3f8..5e49abb49fa 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -10,7 +10,7 @@ #include "tegra30-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" +#define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/tec.h b/include/configs/tec.h index e8a9df756d5..05dd7c96f61 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -12,7 +12,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" +#define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index b5bf9912201..7d1ff2afd14 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -11,7 +11,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice" +#define CFG_TEGRA_BOARD_STRING "Compulab Trimslice" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 970893ca17b..353b5ea67c1 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -12,7 +12,7 @@ #include "tegra124-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Venice2" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/ventana.h b/include/configs/ventana.h index e7b7b911d9b..1d9c60ca7c6 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -11,7 +11,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Ventana" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -- cgit v1.3.1 From 77cfb3d345651fa1cf78c8f30eca9d6d285f1e0b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:59 -0500 Subject: global: Migrate CONFIG_TESTPIN_MASK to CFG Perform a simple rename of CONFIG_TESTPIN_MASK to CFG_TESTPIN_MASK Signed-off-by: Tom Rini --- board/keymile/km83xx/km83xx.c | 2 +- include/configs/kmcoge5ne.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 88afc76bbbf..73e3709bbba 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -217,7 +217,7 @@ int post_hotkeys_pressed(void) struct km_bec_fpga *base = (struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE; int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG); - testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0; + testpin = (testpin_reg & CFG_TESTPIN_MASK) != 0; debug("post_hotkeys_pressed: %d\n", !testpin); return testpin; } diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index e0f94aead79..d9c2f4fc4f9 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -31,6 +31,6 @@ #define CFG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ -#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ +#define CFG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ #endif /* CONFIG */ -- cgit v1.3.1 From 39d4e7b0b060c47879d1f2727853a3e7e38191b5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:00 -0500 Subject: global: Migrate CONFIG_TESTPIN_REG to CFG Perform a simple rename of CONFIG_TESTPIN_REG to CFG_TESTPIN_REG Signed-off-by: Tom Rini --- board/keymile/km83xx/km83xx.c | 2 +- include/configs/kmcoge5ne.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 73e3709bbba..9ec1dbc6f97 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -216,7 +216,7 @@ int post_hotkeys_pressed(void) int testpin = 0; struct km_bec_fpga *base = (struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE; - int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG); + int testpin_reg = in_8(&base->CFG_TESTPIN_REG); testpin = (testpin_reg & CFG_TESTPIN_MASK) != 0; debug("post_hotkeys_pressed: %d\n", !testpin); return testpin; diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index d9c2f4fc4f9..d52f45ba911 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -30,7 +30,7 @@ #define CFG_POST (CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) #define CFG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END -#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ +#define CFG_TESTPIN_REG gprt3 /* for kmcoge5ne */ #define CFG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ #endif /* CONFIG */ -- cgit v1.3.1 From 805482d1874d1d06da89d71fcf0f9a46945f7836 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:02 -0500 Subject: global: Migrate CONFIG_USART_BASE to CFG Perform a simple rename of CONFIG_USART_BASE to CFG_USART_BASE Signed-off-by: Tom Rini --- drivers/serial/atmel_usart.c | 10 +++++----- include/configs/corvus.h | 2 +- include/configs/sam9x60_curiosity.h | 2 +- include/configs/sam9x60ek.h | 2 +- include/configs/smartweb.h | 2 +- include/configs/taurus.h | 2 +- include/configs/vinco.h | 2 +- 7 files changed, 11 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 90ccdf6b294..56655427b06 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -72,13 +72,13 @@ static void atmel_serial_activate(atmel_usart3_t *usart) static void atmel_serial_setbrg(void) { - atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE, + atmel_serial_setbrg_internal((atmel_usart3_t *)CFG_USART_BASE, CONFIG_USART_ID, gd->baudrate); } static int atmel_serial_init(void) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE; atmel_serial_init_internal(usart); serial_setbrg(); @@ -89,7 +89,7 @@ static int atmel_serial_init(void) static void atmel_serial_putc(char c) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE; if (c == '\n') serial_putc('\r'); @@ -100,7 +100,7 @@ static void atmel_serial_putc(char c) static int atmel_serial_getc(void) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE; while (!(readl(&usart->csr) & USART3_BIT(RXRDY))) schedule(); @@ -109,7 +109,7 @@ static int atmel_serial_getc(void) static int atmel_serial_tstc(void) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE; return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0; } diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 8a61086ecc1..c9eb75d9308 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -28,7 +28,7 @@ #define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* serial console */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CFG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS /* SDRAM */ diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h index f44ce909b91..204020d5ee7 100644 --- a/include/configs/sam9x60_curiosity.h +++ b/include/configs/sam9x60_curiosity.h @@ -13,7 +13,7 @@ #define CFG_SYS_AT91_SLOW_CLOCK 32768 #define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CFG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0 /* ignored in arm */ /* SDRAM */ diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 27b39ebf417..800b98ff98a 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -14,7 +14,7 @@ #define CFG_SYS_AT91_SLOW_CLOCK 32768 #define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CFG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0 /* ignored in arm */ /* diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 762f61470b1..f9a5aa9e32d 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -61,7 +61,7 @@ #define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13 /* serial console */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CFG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS /* DFU class support */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 855218a8901..88870d6fdf6 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -34,7 +34,7 @@ /* Misc CPU related */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CFG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS /* diff --git a/include/configs/vinco.h b/include/configs/vinco.h index 0698ae1d1c6..3b4032301f6 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -17,7 +17,7 @@ /* The value in the common file is too far away for the VInCo platform */ /* serial console */ -#define CONFIG_USART_BASE 0xfc00c000 +#define CFG_USART_BASE 0xfc00c000 #define CONFIG_USART_ID 30 /* Timer */ -- cgit v1.3.1 From 61693acbce16dd674de9d6193fbfaffc739f4829 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:03 -0500 Subject: global: Migrate CONFIG_USART_ID to CFG Perform a simple rename of CONFIG_USART_ID to CFG_USART_ID Signed-off-by: Tom Rini --- drivers/serial/atmel_usart.c | 2 +- include/configs/corvus.h | 2 +- include/configs/sam9x60_curiosity.h | 2 +- include/configs/sam9x60ek.h | 2 +- include/configs/smartweb.h | 2 +- include/configs/taurus.h | 2 +- include/configs/vinco.h | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 56655427b06..9d97bc86544 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -73,7 +73,7 @@ static void atmel_serial_activate(atmel_usart3_t *usart) static void atmel_serial_setbrg(void) { atmel_serial_setbrg_internal((atmel_usart3_t *)CFG_USART_BASE, - CONFIG_USART_ID, gd->baudrate); + CFG_USART_ID, gd->baudrate); } static int atmel_serial_init(void) diff --git a/include/configs/corvus.h b/include/configs/corvus.h index c9eb75d9308..f2675e0ec86 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -29,7 +29,7 @@ /* serial console */ #define CFG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS +#define CFG_USART_ID ATMEL_ID_SYS /* SDRAM */ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h index 204020d5ee7..e79f80f17f6 100644 --- a/include/configs/sam9x60_curiosity.h +++ b/include/configs/sam9x60_curiosity.h @@ -14,7 +14,7 @@ #define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ #define CFG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID 0 /* ignored in arm */ +#define CFG_USART_ID 0 /* ignored in arm */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 800b98ff98a..2c761821efb 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -15,7 +15,7 @@ #define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ #define CFG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID 0 /* ignored in arm */ +#define CFG_USART_ID 0 /* ignored in arm */ /* * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index f9a5aa9e32d..75a1670e331 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -62,7 +62,7 @@ /* serial console */ #define CFG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS +#define CFG_USART_ID ATMEL_ID_SYS /* DFU class support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 88870d6fdf6..174b848e259 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -35,7 +35,7 @@ /* Misc CPU related */ #define CFG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS +#define CFG_USART_ID ATMEL_ID_SYS /* * SDRAM: 1 bank, min 32, max 128 MB diff --git a/include/configs/vinco.h b/include/configs/vinco.h index 3b4032301f6..68c56df5435 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -18,7 +18,7 @@ /* serial console */ #define CFG_USART_BASE 0xfc00c000 -#define CONFIG_USART_ID 30 +#define CFG_USART_ID 30 /* Timer */ #define CFG_SYS_TIMER_COUNTER 0xfc06863c -- cgit v1.3.1 From 1d0eaf2f32353424063686478a34a56dfa251416 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:04 -0500 Subject: global: Migrate CONFIG_USB_ISP1301_I2C_ADDR to CFG Perform a simple rename of CONFIG_USB_ISP1301_I2C_ADDR to CFG_USB_ISP1301_I2C_ADDR Signed-off-by: Tom Rini --- drivers/usb/host/ohci-lpc32xx.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c index 3be0b311a36..a04b2961b96 100644 --- a/drivers/usb/host/ohci-lpc32xx.c +++ b/drivers/usb/host/ohci-lpc32xx.c @@ -69,7 +69,7 @@ struct otg_regs { #define OTG1_DM_PULLDOWN (1 << 3) #define OTG1_VBUS_DRV (1 << 5) -#define ISP1301_I2C_ADDR CONFIG_USB_ISP1301_I2C_ADDR +#define ISP1301_I2C_ADDR CFG_USB_ISP1301_I2C_ADDR #define ISP1301_I2C_MODE_CONTROL_1_SET 0x04 #define ISP1301_I2C_MODE_CONTROL_1_CLR 0x05 diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 9cfee381d4a..d85aeaafe51 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -53,7 +53,7 @@ /* * USB */ -#define CONFIG_USB_ISP1301_I2C_ADDR 0x2d +#define CFG_USB_ISP1301_I2C_ADDR 0x2d /* * U-Boot General Configurations -- cgit v1.3.1 From 438654c87c0ec20019c2489ecce02919005b91bc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:05 -0500 Subject: global: Migrate CONFIG_VSC7385_IMAGE et al to CFG Perform simple renames of: CONFIG_VSC7385_IMAGE to CFG_VSC7385_IMAGE CONFIG_VSC7385_IMAGE_SIZE to CFG_VSC7385_IMAGE_SIZE Signed-off-by: Tom Rini --- board/freescale/mpc837xerdb/mpc837xerdb.c | 6 +++--- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +- include/configs/MPC837XERDB.h | 4 ++-- include/configs/p1_p2_rdb_pc.h | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 8b1bfe0a9f9..97884a39796 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -206,9 +206,9 @@ int misc_init_r(void) { int rc = 0; -#ifdef CONFIG_VSC7385_IMAGE - if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, - CONFIG_VSC7385_IMAGE_SIZE)) { +#ifdef CFG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CFG_VSC7385_IMAGE, + CFG_VSC7385_IMAGE_SIZE)) { puts("Failure uploading VSC7385 microcode.\n"); rc = 1; } diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 4d7d042eaf3..602b7f0156b 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -355,7 +355,7 @@ int board_early_init_r(void) vscfw_addr = hextoul(tmp, NULL); printf("uploading VSC7385 microcode from %x\n", vscfw_addr); if (vsc7385_upload_firmware((void *)vscfw_addr, - CONFIG_VSC7385_IMAGE_SIZE)) + CFG_VSC7385_IMAGE_SIZE)) puts("Failure uploading VSC7385 microcode.\n"); } else { puts("No address specified for VSC7385 microcode.\n"); diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 07c989d9890..70b1c399241 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -42,8 +42,8 @@ #ifdef CONFIG_VSC7385_ENET /* The flash address and size of the VSC7385 firmware image */ -#define CONFIG_VSC7385_IMAGE 0xFE7FE000 -#define CONFIG_VSC7385_IMAGE_SIZE 8192 +#define CFG_VSC7385_IMAGE 0xFE7FE000 +#define CFG_VSC7385_IMAGE_SIZE 8192 #endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index be768019829..f5bd0913449 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -270,7 +270,7 @@ #endif /* The size of the VSC7385 firmware image */ -#define CONFIG_VSC7385_IMAGE_SIZE 8192 +#define CFG_VSC7385_IMAGE_SIZE 8192 #endif #ifndef __VSCFW_ADDR -- cgit v1.3.1 From bb34410509205e70ab7c9830f9c17277e8dd54ad Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:06 -0500 Subject: global: Migrate CONFIG_WATCHDOG_PRESC et al to CFG Perform simple renames of: CONFIG_WATCHDOG_PRESC to CFG_WATCHDOG_PRESC CONFIG_WATCHDOG_RC to CFG_WATCHDOG_RC Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- include/configs/kmcent2.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 0abcc01b857..e8a3e82765f 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -357,7 +357,7 @@ void init_85xx_watchdog(void) { mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) | - TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC)); + TCR_WP(CFG_WATCHDOG_PRESC) | TCR_WRC(CFG_WATCHDOG_RC)); } void diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 58dff495ac5..60fea59dee0 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -364,8 +364,8 @@ int get_scl(void); /* * Hardware Watchdog */ -#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */ -#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ +#define CFG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */ +#define CFG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ /* * For booting Linux, the board info and command line data -- cgit v1.3.1 From fa2fd534b5d80d59b9043f2d8291fcb1c6c75a5b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:07 -0500 Subject: global: Migrate CONFIG_X86_MRC_ADDR to CFG Perform a simple rename of CONFIG_X86_MRC_ADDR to CFG_X86_MRC_ADDR Signed-off-by: Tom Rini --- arch/x86/cpu/intel_common/mrc.c | 2 +- arch/x86/dts/u-boot.dtsi | 2 +- include/configs/x86-chromebook.h | 2 +- tools/binman/binman.rst | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index a4918fbad61..69405d740b4 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -200,7 +200,7 @@ static int sdram_initialise(struct udevice *dev, struct udevice *me_dev, debug("PEI data at %p:\n", pei_data); - data = (char *)CONFIG_X86_MRC_ADDR; + data = (char *)CFG_X86_MRC_ADDR; if (data) { int rv; ulong start; diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 24e692f988d..454efc17614 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -86,7 +86,7 @@ #endif #ifdef CONFIG_HAVE_MRC intel-mrc { - offset = ; + offset = ; }; #endif #ifdef CONFIG_FSP_VERSION1 diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 41fb499ae4f..059e3a0d8a2 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -6,7 +6,7 @@ #ifndef _X86_CHROMEBOOK_H #define _X86_CHROMEBOOK_H -#define CONFIG_X86_MRC_ADDR 0xfffa0000 +#define CFG_X86_MRC_ADDR 0xfffa0000 #define CONFIG_X86_REFCODE_ADDR 0xffea0000 #define CONFIG_X86_REFCODE_RUN_ADDR 0 diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst index e7b231e0712..69e4b00239c 100644 --- a/tools/binman/binman.rst +++ b/tools/binman/binman.rst @@ -298,7 +298,7 @@ C preprocessor:: #ifdef CONFIG_HAVE_MRC intel-mrc { - offset = ; + offset = ; }; #endif -- cgit v1.3.1 From d4143373f161984426f0bd1fda1cbced21e57272 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:08 -0500 Subject: global: Migrate CONFIG_X86_REFCODE_ADDR to CFG Perform a simple rename of CONFIG_X86_REFCODE_ADDR to CFG_X86_REFCODE_ADDR Signed-off-by: Tom Rini --- arch/x86/cpu/broadwell/refcode.c | 2 +- arch/x86/dts/u-boot.dtsi | 2 +- include/configs/x86-chromebook.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c index 94c2e05346a..3b7ec2b74e8 100644 --- a/arch/x86/cpu/broadwell/refcode.c +++ b/arch/x86/cpu/broadwell/refcode.c @@ -78,7 +78,7 @@ static int cpu_run_reference_code(void) int ret, dummy; int size; - hdr = (struct rmodule_header *)CONFIG_X86_REFCODE_ADDR; + hdr = (struct rmodule_header *)CFG_X86_REFCODE_ADDR; debug("Extracting code from rmodule at %p\n", hdr); if (hdr->magic != RMODULE_MAGIC) { debug("Invalid rmodule magic\n"); diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 454efc17614..e0de3318091 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -149,7 +149,7 @@ #endif #ifdef CONFIG_HAVE_REFCODE intel-refcode { - offset = ; + offset = ; }; #endif #ifdef CONFIG_TPL diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 059e3a0d8a2..8bbbe51ecb5 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -7,7 +7,7 @@ #define _X86_CHROMEBOOK_H #define CFG_X86_MRC_ADDR 0xfffa0000 -#define CONFIG_X86_REFCODE_ADDR 0xffea0000 +#define CFG_X86_REFCODE_ADDR 0xffea0000 #define CONFIG_X86_REFCODE_RUN_ADDR 0 #define VIDEO_IO_OFFSET 0 -- cgit v1.3.1 From 92a5c899987301f6b53ef37e46ea96ce9abb752e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:09 -0500 Subject: global: Migrate CONFIG_X86_REFCODE_RUN_ADDR to CFG Perform a simple rename of CONFIG_X86_REFCODE_RUN_ADDR to CFG_X86_REFCODE_RUN_ADDR Signed-off-by: Tom Rini --- arch/x86/cpu/broadwell/refcode.c | 4 ++-- include/configs/x86-chromebook.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c index 3b7ec2b74e8..df2df7972e9 100644 --- a/arch/x86/cpu/broadwell/refcode.c +++ b/arch/x86/cpu/broadwell/refcode.c @@ -99,7 +99,7 @@ static int cpu_run_reference_code(void) pei_data->saved_data = (void *)&dummy; src = (char *)hdr + hdr->payload_begin_offset; - dest = (char *)CONFIG_X86_REFCODE_RUN_ADDR; + dest = (char *)CFG_X86_REFCODE_RUN_ADDR; size = hdr->payload_end_offset - hdr->payload_begin_offset; debug("Copying refcode from %p to %p, size %x\n", src, dest, size); @@ -112,7 +112,7 @@ static int cpu_run_reference_code(void) func = (asmlinkage int (*)(void *))dest; debug("Running reference code at %p\n", func); #ifdef DEBUG - print_buffer(CONFIG_X86_REFCODE_RUN_ADDR, (void *)func, 1, 0x40, 0); + print_buffer(CFG_X86_REFCODE_RUN_ADDR, (void *)func, 1, 0x40, 0); #endif ret = func(pei_data); if (ret != 0) { diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 8bbbe51ecb5..98abb00927a 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -8,7 +8,7 @@ #define CFG_X86_MRC_ADDR 0xfffa0000 #define CFG_X86_REFCODE_ADDR 0xffea0000 -#define CONFIG_X86_REFCODE_RUN_ADDR 0 +#define CFG_X86_REFCODE_RUN_ADDR 0 #define VIDEO_IO_OFFSET 0 -- cgit v1.3.1 From e1d6c16d80cbe510f524d68a1879ed0fab26a80b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:10 -0500 Subject: librem5: Rename CONFIG_POWER_BD71837 symbols Rename the CONFIG_POWER_BD71837_I2C_* symbols to not have the CONFIG prefix and be local to the file they are used in. Signed-off-by: Tom Rini --- board/purism/librem5/spl.c | 8 +++++--- include/configs/librem5.h | 4 ---- 2 files changed, 5 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c index 1bfd948806f..1a203b45999 100644 --- a/board/purism/librem5/spl.c +++ b/board/purism/librem5/spl.c @@ -322,6 +322,8 @@ void disable_charger_bq25895(void) } #define I2C_PMIC 0 +#define POWER_BD71837_I2C_BUS 0 +#define POWER_BD71837_I2C_ADDR 0x4B int power_bd71837_init(unsigned char bus) { @@ -336,7 +338,7 @@ int power_bd71837_init(unsigned char bus) p->name = name; p->interface = I2C_PMIC; p->number_of_regs = BD718XX_MAX_REGISTER; - p->hw.i2c.addr = CONFIG_POWER_BD71837_I2C_ADDR; + p->hw.i2c.addr = POWER_BD71837_I2C_ADDR; p->hw.i2c.tx_num = 1; p->bus = bus; @@ -357,10 +359,10 @@ int power_init_board(void) /* * Init PMIC */ - rv = power_bd71837_init(CONFIG_POWER_BD71837_I2C_BUS); + rv = power_bd71837_init(POWER_BD71837_I2C_BUS); if (rv) { log_err("%s: power_bd71837_init(%d) error %d\n", __func__, - CONFIG_POWER_BD71837_I2C_BUS, rv); + POWER_BD71837_I2C_BUS, rv); goto out; } diff --git a/include/configs/librem5.h b/include/configs/librem5.h index 9e4d373e56d..e17190ce9c5 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -19,10 +19,6 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ -#define CONFIG_POWER_BD71837 -#define CONFIG_POWER_BD71837_I2C_BUS 0 -#define CONFIG_POWER_BD71837_I2C_ADDR 0x4B - #endif /* CONFIG_SPL_BUILD*/ #define CFG_SYS_FSL_USDHC_NUM 2 -- cgit v1.3.1 From f5dd0c5e19cf587c744e234e8a7e47f63642e113 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:11 -0500 Subject: configs: Remove unused or redundant CONFIG symbols A number of CONFIG symbols have crept in that are never referenced in code, so drop them here. Further, we have two symbols being enabled in headers while already enabled correctly in Kconfig, so these lines can also be removed. Signed-off-by: Tom Rini --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 - arch/arm/mach-mvebu/include/mach/config.h | 3 --- include/configs/cgtqmx8.h | 1 - include/configs/imx8mp_rsb3720.h | 9 --------- include/configs/imx8mq_cm.h | 1 - include/configs/imx8mq_evk.h | 1 - include/configs/imx8mq_phanbell.h | 1 - include/configs/imx8qm_mek.h | 1 - include/configs/imx8qxp_mek.h | 1 - include/configs/kontron_pitx_imx8m.h | 1 - include/configs/librem5.h | 6 ------ include/configs/pico-imx8mq.h | 1 - 13 files changed, 1 insertion(+), 27 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 2862257e1f2..9656c52e955 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -29,6 +29,7 @@ config ARCH_LS1028A select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_LAYERSCAPE select FSL_LSCH3 + select FSL_TZASC_400 select GICV3 select NXP_LSCH3_2 select SYS_FSL_HAS_CCI400 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 12758c8dd1c..516c9eab047 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -160,7 +160,6 @@ #elif defined(CONFIG_ARCH_LS1028A) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_FSL_TZASC_400 /* TZ Protection Controller Definitions */ #define TZPC_BASE 0x02200000 diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 96a08104ff4..61027475483 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -27,7 +27,4 @@ #define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE -/* Needed for SPI NOR booting in SPL */ -#define CONFIG_DM_SEQ_ALIAS 1 - #endif /* __MVEBU_CONFIG_H */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 91454df1972..98d4d8cf4bd 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -12,7 +12,6 @@ #include #ifdef CONFIG_SPL_BUILD -#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 495ca313db2..d4ab6a6207d 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -28,12 +28,6 @@ * GD_FLG_FULL_MALLOC_INIT \ * set \ */ - - -#if defined(CONFIG_NAND_BOOT) -#define CONFIG_SPL_NAND_MXS -#endif - #endif /* ENET Config */ @@ -158,9 +152,6 @@ #define FSL_FSPI_FLASH_NUM 1 #define FSPI0_BASE_ADDR 0x30bb0000 #define FSPI0_AMBA_BASE 0x0 -#define CONFIG_FSPI_QUAD_SUPPORT - -#define CONFIG_SYS_FSL_FSPI_AHB #endif #ifdef CONFIG_NAND_MXS diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 828bd672372..7cf482d6de1 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -11,7 +11,6 @@ #include #ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x182000 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index d2de2900c06..d2e1649400a 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -12,7 +12,6 @@ #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x182000 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index bfde15e6240..b66fc18fa5e 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -11,7 +11,6 @@ #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x182000 diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index a25efbb16bd..4d5abe2d073 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -11,7 +11,6 @@ #include #ifdef CONFIG_SPL_BUILD -#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 4f55ae49403..93999509948 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -11,7 +11,6 @@ #include #ifdef CONFIG_SPL_BUILD -#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index e3a021c987c..5cf6b5a6dd4 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -13,7 +13,6 @@ 0x40, 0xd4, 0x5c, 0xca, 0x13, 0x99) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x182000 diff --git a/include/configs/librem5.h b/include/configs/librem5.h index e17190ce9c5..ce0a340ba26 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -15,12 +15,6 @@ #include #include -#ifdef CONFIG_SPL_BUILD - -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ - -#endif /* CONFIG_SPL_BUILD*/ - #define CFG_SYS_FSL_USDHC_NUM 2 #define CONSOLE_ON_UART1 diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 4b602ea0302..be31f8a23ca 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -11,7 +11,6 @@ #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x182000 -- cgit v1.3.1 From 0478dac62a9add8c73981a900ceaa6da732ae2bb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:13 -0500 Subject: kbuild: Remove uncmd_spl logic At this point in the conversion there should be no need to have logic to disable some symbol during the SPL build as all symbols should have an SPL counterpart. The main real changes done here are that we now must make proper use of CONFIG_IS_ENABLED(DM_SERIAL) rather than many of the odd tricks we developed prior to CONFIG_IS_ENABLED() being available. Signed-off-by: Tom Rini --- board/freescale/common/i2c_common.c | 2 +- board/freescale/common/i2c_common.h | 2 +- drivers/misc/gsc.c | 2 +- drivers/serial/Makefile | 17 +---------------- drivers/serial/atmel_usart.c | 8 +++----- drivers/serial/serial-uclass.c | 6 +++--- drivers/serial/serial_mtk.c | 3 +-- drivers/serial/serial_pl01x.c | 11 +++-------- drivers/serial/serial_pl01x_internal.h | 2 +- include/config_uncmd_spl.h | 21 --------------------- include/configs/kmcent2.h | 2 +- include/configs/mv-common.h | 2 +- include/configs/sunxi-common.h | 2 +- include/configs/ti_omap4_common.h | 2 +- include/configs/x530.h | 2 +- include/ns16550.h | 10 +++++----- scripts/Makefile.autoconf | 1 - scripts/Makefile.build | 1 - scripts/Makefile.uncmd_spl | 14 -------------- 19 files changed, 25 insertions(+), 85 deletions(-) delete mode 100644 include/config_uncmd_spl.h delete mode 100644 scripts/Makefile.uncmd_spl (limited to 'include') diff --git a/board/freescale/common/i2c_common.c b/board/freescale/common/i2c_common.c index 0f09ed7d34f..119ed3c6171 100644 --- a/board/freescale/common/i2c_common.c +++ b/board/freescale/common/i2c_common.c @@ -9,7 +9,7 @@ #include #include "i2c_common.h" -#ifdef CONFIG_DM_I2C +#if CONFIG_IS_ENABLED(DM_I2C) /* If DM is in use, retrieve the chip for the specified bus number */ int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev) diff --git a/board/freescale/common/i2c_common.h b/board/freescale/common/i2c_common.h index 840ad661831..77a7b6aedd7 100644 --- a/board/freescale/common/i2c_common.h +++ b/board/freescale/common/i2c_common.h @@ -9,7 +9,7 @@ #define __NXP_I2C_COMMON_H__ /* Common functionality shared by the I2C drivers for VID and the mux. */ -#ifdef CONFIG_DM_I2C +#if CONFIG_IS_ENABLED(DM_I2C) #define DEVICE_HANDLE_T struct udevice * #define I2C_READ(dev, register, data, length) \ diff --git a/drivers/misc/gsc.c b/drivers/misc/gsc.c index ec24ca807b0..65c9c2c6ce3 100644 --- a/drivers/misc/gsc.c +++ b/drivers/misc/gsc.c @@ -77,7 +77,7 @@ enum { GSC_SC_RST_CAUSE_MAX = 10, }; -#if (IS_ENABLED(CONFIG_DM_I2C)) +#if CONFIG_IS_ENABLED(DM_I2C) struct gsc_priv { int gscver; diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 33fa5682211..37d3f82dbd8 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -3,30 +3,15 @@ # (C) Copyright 2006-2009 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifdef CONFIG_SPL_BUILD - -ifeq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)DM_SERIAL),yy) -obj-y += serial-uclass.o -else -obj-y += serial.o -endif - -else - -ifdef CONFIG_DM_SERIAL +ifeq ($(CONFIG_$(SPL_TPL_)DM_SERIAL),y) obj-y += serial-uclass.o else obj-y += serial.o endif -endif - -ifdef CONFIG_DM_SERIAL obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o -else obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o obj-$(CONFIG_$(SPL_)SYS_NS16550_SERIAL) += serial_ns16550.o -endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 9d97bc86544..9853f49c94f 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -18,7 +18,7 @@ #include #include -#ifdef CONFIG_DM_SERIAL +#if CONFIG_IS_ENABLED(DM_SERIAL) #include #endif #include @@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_DM_SERIAL +#if !CONFIG_IS_ENABLED(DM_SERIAL) static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id, int baudrate) { @@ -133,9 +133,7 @@ __weak struct serial_device *default_serial_console(void) { return &atmel_serial_drv; } -#endif - -#ifdef CONFIG_DM_SERIAL +#else enum serial_clk_type { CLK_TYPE_NORMAL = 0, CLK_TYPE_DBGU, diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index c02106747a0..7240d763d12 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -407,7 +407,7 @@ void serial_stdio_init(void) { } -#if defined(CONFIG_DM_STDIO) +#if CONFIG_IS_ENABLED(DM_STDIO) #if CONFIG_IS_ENABLED(SERIAL_PRESENT) static void serial_stub_putc(struct stdio_dev *sdev, const char ch) @@ -505,7 +505,7 @@ U_BOOT_ENV_CALLBACK(baudrate, on_baudrate); static int serial_post_probe(struct udevice *dev) { struct dm_serial_ops *ops = serial_get_ops(dev); -#ifdef CONFIG_DM_STDIO +#if CONFIG_IS_ENABLED(DM_STDIO) struct serial_dev_priv *upriv = dev_get_uclass_priv(dev); struct stdio_dev sdev; #endif @@ -540,7 +540,7 @@ static int serial_post_probe(struct udevice *dev) return ret; } -#ifdef CONFIG_DM_STDIO +#if CONFIG_IS_ENABLED(DM_STDIO) if (!(gd->flags & GD_FLG_RELOC)) return 0; memset(&sdev, '\0', sizeof(sdev)); diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index 6fb4cb65c29..ded7346a13f 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -173,8 +173,7 @@ static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input) return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1; } -#if defined(CONFIG_DM_SERIAL) && \ - (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_DM)) +#if CONFIG_IS_ENABLED(DM_SERIAL) static int mtk_serial_setbrg(struct udevice *dev, int baudrate) { struct mtk_serial_priv *priv = dev_get_priv(dev); diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 7449e9b9043..f5468353e10 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -27,8 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_DM_SERIAL - +#if !CONFIG_IS_ENABLED(DM_SERIAL) static volatile unsigned char *const port[] = CFG_PL01x_PORTS; static enum pl01x_type pl01x_type __section(".data"); static struct pl01x_regs *base_regs __section(".data"); @@ -186,7 +185,7 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, return 0; } -#ifndef CONFIG_DM_SERIAL +#if !CONFIG_IS_ENABLED(DM_SERIAL) static void pl01x_serial_init_baud(int baudrate) { int clock = 0; @@ -273,11 +272,7 @@ __weak struct serial_device *default_serial_console(void) { return &pl01x_serial_drv; } - -#endif /* nCONFIG_DM_SERIAL */ - -#ifdef CONFIG_DM_SERIAL - +#else int pl01x_serial_setbrg(struct udevice *dev, int baudrate) { struct pl01x_serial_plat *plat = dev_get_plat(dev); diff --git a/drivers/serial/serial_pl01x_internal.h b/drivers/serial/serial_pl01x_internal.h index dfd95a0b77c..71c52bb5312 100644 --- a/drivers/serial/serial_pl01x_internal.h +++ b/drivers/serial/serial_pl01x_internal.h @@ -38,7 +38,7 @@ struct pl01x_regs { u32 pl011_cr; /* 0x30 Control register */ }; -#ifdef CONFIG_DM_SERIAL +#if CONFIG_IS_ENABLED(DM_SERIAL) int pl01x_serial_of_to_plat(struct udevice *dev); int pl01x_serial_probe(struct udevice *dev); diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h deleted file mode 100644 index a59b9bbafbd..00000000000 --- a/include/config_uncmd_spl.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * Ilya Yanok, ilya.yanok@gmail.com - */ - -#ifndef __CONFIG_UNCMD_SPL_H__ -#define __CONFIG_UNCMD_SPL_H__ - -#ifdef CONFIG_SPL_BUILD -/* SPL needs only BOOTP + TFTP so undefine other stuff to save space */ - -#ifndef CONFIG_SPL_DM -#undef CONFIG_DM_SERIAL -#undef CONFIG_DM_I2C -#endif - -#undef CONFIG_DM_STDIO - -#endif /* CONFIG_SPL_BUILD */ -#endif /* __CONFIG_UNCMD_SPL_H__ */ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 60fea59dee0..e7ae18ec5f9 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -314,7 +314,7 @@ * shorted - index 1 * Retain non-DM serial port for debug purposes. */ -#if !defined(CONFIG_DM_SERIAL) +#if !CONFIG_IS_ENABLED(DM_SERIAL) #define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR + 0x11C500) #endif diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index fa275d61d18..3dfcb138b49 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -33,7 +33,7 @@ * NS16550 Configuration */ #define CFG_SYS_NS16550_CLK CFG_SYS_TCLK -#if !defined(CONFIG_DM_SERIAL) +#if !CONFIG_IS_ENABLED(DM_SERIAL) #define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index eae107fe5ec..8032abe7692 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -23,7 +23,7 @@ #else #define CFG_SYS_NS16550_CLK 24000000 #endif -#ifndef CONFIG_DM_SERIAL +#if !CONFIG_IS_ENABLED(DM_SERIAL) # define CFG_SYS_NS16550_COM1 SUNXI_UART0_BASE # define CFG_SYS_NS16550_COM2 SUNXI_UART1_BASE # define CFG_SYS_NS16550_COM3 SUNXI_UART2_BASE diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 49f4263e16b..9e312ac16d1 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -28,7 +28,7 @@ * Hardware drivers */ #define CFG_SYS_NS16550_CLK 48000000 -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) +#if !CONFIG_IS_ENABLED(DM_SERIAL) #define CFG_SYS_NS16550_COM3 UART3_BASE #endif diff --git a/include/configs/x530.h b/include/configs/x530.h index fddf00d3d13..e1678e79e49 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -14,7 +14,7 @@ * NS16550 Configuration */ #define CFG_SYS_NS16550_CLK CFG_SYS_TCLK -#if !defined(CONFIG_DM_SERIAL) +#if !CONFIG_IS_ENABLED(DM_SERIAL) #define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif diff --git a/include/ns16550.h b/include/ns16550.h index 0ee5c4d6de7..f45fc8cecc5 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_SYS_NS16550_REG_SIZE) +#if CONFIG_IS_ENABLED(DM_SERIAL) && !defined(CONFIG_SYS_NS16550_REG_SIZE) /* * For driver model we always use one byte per register, and sort out the * differences in the driver @@ -37,10 +37,10 @@ #ifdef CONFIG_NS16550_DYNAMIC #define UART_REG(x) unsigned char x #else -#if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) -#error "Please define NS16550 registers size." -#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL) +#if defined(CONFIG_SYS_NS16550_MEM32) && !CONFIG_IS_ENABLED(DM_SERIAL) #define UART_REG(x) u32 x +#elif !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) +#error "Please define NS16550 registers size." #elif (CONFIG_SYS_NS16550_REG_SIZE > 0) #define UART_REG(x) \ unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ @@ -113,7 +113,7 @@ struct ns16550 { UART_REG(scr); /* 10*/ UART_REG(ssr); /* 11*/ #endif -#ifdef CONFIG_DM_SERIAL +#if CONFIG_IS_ENABLED(DM_SERIAL) struct ns16550_plat *plat; #endif }; diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf index f5f5e4a4d54..0ade91642ae 100644 --- a/scripts/Makefile.autoconf +++ b/scripts/Makefile.autoconf @@ -113,7 +113,6 @@ vpl/include/autoconf.mk: vpl/u-boot.cfg define filechk_config_h (echo "/* Automatically generated - do not edit */"; \ echo \#define CFG_BOARDDIR board/$(if $(VENDOR),$(VENDOR)/)$(BOARD);\ - echo \#include \; \ echo \#include \; \ echo \#include \; \ echo \#include \; \ diff --git a/scripts/Makefile.build b/scripts/Makefile.build index 3b8c9d8c319..97dd4a64f6e 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -48,7 +48,6 @@ subdir-ccflags-y := # Modified for U-Boot -include include/config/auto.conf -include $(prefix)/include/autoconf.mk -include scripts/Makefile.uncmd_spl include scripts/Kbuild.include diff --git a/scripts/Makefile.uncmd_spl b/scripts/Makefile.uncmd_spl deleted file mode 100644 index 6ea097d36dd..00000000000 --- a/scripts/Makefile.uncmd_spl +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# Makefile version of include/config_uncmd_spl.h -# TODO: Invent a better way - -ifdef CONFIG_SPL_BUILD - -ifndef CONFIG_SPL_DM -CONFIG_DM_SERIAL= -CONFIG_DM_I2C= -CONFIG_DM_SPI= -CONFIG_DM_SPI_FLASH= -endif - -endif -- cgit v1.3.1 From 1e019503330585e892be057cca3ed4eb1b9c9344 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:17 -0500 Subject: post: Move CONFIG_SYS_POST to CFG_SYS_POST Migrate the rest of the CONFIG_SYS_POST macros over to CFG_SYS_POST namespace. Signed-off-by: Tom Rini --- doc/README.POST | 12 ++--- drivers/serial/serial-uclass.c | 2 +- drivers/serial/serial.c | 2 +- include/post.h | 50 ++++++++--------- include/serial.h | 4 +- post/cpu/mpc83xx/ecc.c | 8 +-- post/drivers/flash.c | 14 ++--- post/drivers/i2c.c | 20 +++---- post/drivers/rtc.c | 4 +- post/lib_powerpc/andi.c | 2 +- post/lib_powerpc/asm.S | 2 +- post/lib_powerpc/b.c | 2 +- post/lib_powerpc/cmp.c | 2 +- post/lib_powerpc/cmpi.c | 2 +- post/lib_powerpc/complex.c | 2 +- post/lib_powerpc/cpu.c | 4 +- post/lib_powerpc/cr.c | 2 +- post/lib_powerpc/fpu/20001122-1.c | 4 +- post/lib_powerpc/fpu/20010114-2.c | 4 +- post/lib_powerpc/fpu/20010226-1.c | 4 +- post/lib_powerpc/fpu/980619-1.c | 4 +- post/lib_powerpc/fpu/acc1.c | 4 +- post/lib_powerpc/fpu/compare-fp-1.c | 4 +- post/lib_powerpc/fpu/fpu.c | 4 +- post/lib_powerpc/fpu/mul-subnormal-single-1.c | 4 +- post/lib_powerpc/load.c | 2 +- post/lib_powerpc/multi.c | 2 +- post/lib_powerpc/rlwimi.c | 2 +- post/lib_powerpc/rlwinm.c | 2 +- post/lib_powerpc/rlwnm.c | 2 +- post/lib_powerpc/srawi.c | 2 +- post/lib_powerpc/store.c | 2 +- post/lib_powerpc/string.c | 2 +- post/lib_powerpc/three.c | 2 +- post/lib_powerpc/threei.c | 2 +- post/lib_powerpc/threex.c | 2 +- post/lib_powerpc/two.c | 2 +- post/lib_powerpc/twox.c | 2 +- post/post.c | 6 +-- post/tests.c | 78 +++++++++++++-------------- 40 files changed, 138 insertions(+), 138 deletions(-) (limited to 'include') diff --git a/doc/README.POST b/doc/README.POST index 5d92f3fe6e9..1366f95c662 100644 --- a/doc/README.POST +++ b/doc/README.POST @@ -649,15 +649,15 @@ not need any modifications for porting them to another board/CPU. For verifying the I2C bus, a full I2C bus scanning will be performed using the i2c_probe() routine. If a board defines -CONFIG_SYS_POST_I2C_ADDRS the I2C test will pass if all devices -listed in CONFIG_SYS_POST_I2C_ADDRS are found, and no additional -devices are detected. If CONFIG_SYS_POST_I2C_ADDRS is not defined +CFG_SYS_POST_I2C_ADDRS the I2C test will pass if all devices +listed in CFG_SYS_POST_I2C_ADDRS are found, and no additional +devices are detected. If CFG_SYS_POST_I2C_ADDRS is not defined the test will pass if any I2C device is found. -The CONFIG_SYS_POST_I2C_IGNORES define can be used to list I2C +The CFG_SYS_POST_I2C_IGNORES define can be used to list I2C devices which may or may not be present when using -CONFIG_SYS_POST_I2C_ADDRS. The I2C POST test will pass regardless -if the devices in CONFIG_SYS_POST_I2C_IGNORES are found or not. +CFG_SYS_POST_I2C_ADDRS. The I2C POST test will pass regardless +if the devices in CFG_SYS_POST_I2C_IGNORES are found or not. This is useful in cases when I2C devices are optional (eg on a daughtercard that may or may not be present) or not critical to board operation. diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 7240d763d12..77d3f373721 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -526,7 +526,7 @@ static int serial_post_probe(struct udevice *dev) ops->getconfig += gd->reloc_off; if (ops->setconfig) ops->setconfig += gd->reloc_off; -#if CFG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CFG_SYS_POST_UART if (ops->loop) ops->loop += gd->reloc_off; #endif diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 369a8e38e3e..9a380d7c5e7 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -458,7 +458,7 @@ void default_serial_puts(const char *s) dev->putc(*s++); } -#if CFG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CFG_SYS_POST_UART static const int bauds[] = CFG_SYS_BAUDRATE_TABLE; /** diff --git a/include/post.h b/include/post.h index e68d5c89020..41120695064 100644 --- a/include/post.h +++ b/include/post.h @@ -17,8 +17,8 @@ #if defined(CONFIG_POST) #ifndef CFG_POST_EXTERNAL_WORD_FUNCS -#ifdef CONFIG_SYS_POST_WORD_ADDR -#define _POST_WORD_ADDR CONFIG_SYS_POST_WORD_ADDR +#ifdef CFG_SYS_POST_WORD_ADDR +#define _POST_WORD_ADDR CFG_SYS_POST_WORD_ADDR #else #if defined(CONFIG_ARCH_MPC8360) @@ -34,7 +34,7 @@ #ifndef _POST_WORD_ADDR #error "_POST_WORD_ADDR currently not implemented for this platform!" #endif -#endif /* CONFIG_SYS_POST_WORD_ADDR */ +#endif /* CFG_SYS_POST_WORD_ADDR */ static inline ulong post_word_load (void) { @@ -140,29 +140,29 @@ extern int memory_post_test(int flags); #endif /* __GNUC__ */ #endif /* __ASSEMBLY__ */ -#define CONFIG_SYS_POST_RTC 0x00000001 -#define CONFIG_SYS_POST_WATCHDOG 0x00000002 +#define CFG_SYS_POST_RTC 0x00000001 +#define CFG_SYS_POST_WATCHDOG 0x00000002 #define CFG_SYS_POST_MEMORY 0x00000004 -#define CONFIG_SYS_POST_CPU 0x00000008 -#define CONFIG_SYS_POST_I2C 0x00000010 -#define CONFIG_SYS_POST_CACHE 0x00000020 -#define CONFIG_SYS_POST_UART 0x00000040 -#define CONFIG_SYS_POST_ETHER 0x00000080 -#define CONFIG_SYS_POST_USB 0x00000200 -#define CONFIG_SYS_POST_SPR 0x00000400 -#define CONFIG_SYS_POST_SYSMON 0x00000800 -#define CONFIG_SYS_POST_DSP 0x00001000 -#define CONFIG_SYS_POST_OCM 0x00002000 -#define CONFIG_SYS_POST_FPU 0x00004000 -#define CONFIG_SYS_POST_ECC 0x00008000 -#define CONFIG_SYS_POST_BSPEC1 0x00010000 -#define CONFIG_SYS_POST_BSPEC2 0x00020000 -#define CONFIG_SYS_POST_BSPEC3 0x00040000 -#define CONFIG_SYS_POST_BSPEC4 0x00080000 -#define CONFIG_SYS_POST_BSPEC5 0x00100000 -#define CONFIG_SYS_POST_CODEC 0x00200000 -#define CONFIG_SYS_POST_COPROC 0x00400000 -#define CONFIG_SYS_POST_FLASH 0x00800000 +#define CFG_SYS_POST_CPU 0x00000008 +#define CFG_SYS_POST_I2C 0x00000010 +#define CFG_SYS_POST_CACHE 0x00000020 +#define CFG_SYS_POST_UART 0x00000040 +#define CFG_SYS_POST_ETHER 0x00000080 +#define CFG_SYS_POST_USB 0x00000200 +#define CFG_SYS_POST_SPR 0x00000400 +#define CFG_SYS_POST_SYSMON 0x00000800 +#define CFG_SYS_POST_DSP 0x00001000 +#define CFG_SYS_POST_OCM 0x00002000 +#define CFG_SYS_POST_FPU 0x00004000 +#define CFG_SYS_POST_ECC 0x00008000 +#define CFG_SYS_POST_BSPEC1 0x00010000 +#define CFG_SYS_POST_BSPEC2 0x00020000 +#define CFG_SYS_POST_BSPEC3 0x00040000 +#define CFG_SYS_POST_BSPEC4 0x00080000 +#define CFG_SYS_POST_BSPEC5 0x00100000 +#define CFG_SYS_POST_CODEC 0x00200000 +#define CFG_SYS_POST_COPROC 0x00400000 +#define CFG_SYS_POST_FLASH 0x00800000 #define CFG_SYS_POST_MEM_REGIONS 0x01000000 #endif /* CONFIG_POST */ diff --git a/include/serial.h b/include/serial.h index f4d7dc58a9e..42bdf3759c0 100644 --- a/include/serial.h +++ b/include/serial.h @@ -14,7 +14,7 @@ struct serial_device { int (*tstc)(void); void (*putc)(const char c); void (*puts)(const char *s); -#if CFG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CFG_SYS_POST_UART void (*loop)(int); #endif struct serial_device *next; @@ -242,7 +242,7 @@ struct dm_serial_ops { * @return 0 if OK, -ve on error */ int (*clear)(struct udevice *dev); -#if CFG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CFG_SYS_POST_UART /** * loop() - Control serial device loopback mode * diff --git a/post/cpu/mpc83xx/ecc.c b/post/cpu/mpc83xx/ecc.c index 45263e6b44c..68da8ff4171 100644 --- a/post/cpu/mpc83xx/ecc.c +++ b/post/cpu/mpc83xx/ecc.c @@ -17,7 +17,7 @@ #include #include -#if CFG_POST & CONFIG_SYS_POST_ECC +#if CFG_POST & CFG_SYS_POST_ECC /* * We use the RAW I/O accessors where possible in order to * achieve performance goal, since the test's execution time @@ -51,7 +51,7 @@ int ecc_post_test(int flags) int errbit; u32 pattern[2], writeback[2], retval[2]; ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr; - volatile u64 *addr = (u64 *)CONFIG_SYS_POST_ECC_START_ADDR; + volatile u64 *addr = (u64 *)CFG_SYS_POST_ECC_START_ADDR; /* The pattern is written into memory to generate error */ pattern[0] = 0xfedcba98UL; @@ -70,8 +70,8 @@ int ecc_post_test(int flags) int_state = disable_interrupts(); icache_enable(); - for (addr = (u64*)CONFIG_SYS_POST_ECC_START_ADDR, errbit=0; - addr < (u64*)CONFIG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) { + for (addr = (u64*)CFG_SYS_POST_ECC_START_ADDR, errbit=0; + addr < (u64*)CFG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) { schedule(); diff --git a/post/drivers/flash.c b/post/drivers/flash.c index e157d369110..a1fcf1f135d 100644 --- a/post/drivers/flash.c +++ b/post/drivers/flash.c @@ -6,7 +6,7 @@ * Licensed under the GPL-2 or later. */ -#if CFG_POST & CONFIG_SYS_POST_FLASH +#if CFG_POST & CFG_SYS_POST_FLASH #include #include #include @@ -23,10 +23,10 @@ * - better seed pattern than 0x00..0xff */ -#ifndef CONFIG_SYS_POST_FLASH_NUM -# define CONFIG_SYS_POST_FLASH_NUM 0 +#ifndef CFG_SYS_POST_FLASH_NUM +# define CFG_SYS_POST_FLASH_NUM 0 #endif -#if CONFIG_SYS_POST_FLASH_START >= CONFIG_SYS_POST_FLASH_END +#if CFG_SYS_POST_FLASH_START >= CFG_SYS_POST_FLASH_END # error "invalid flash block start/end" #endif @@ -59,9 +59,9 @@ int flash_post_test(int flags) len = 0; src = NULL; - info = &flash_info[CONFIG_SYS_POST_FLASH_NUM]; - n_start = CONFIG_SYS_POST_FLASH_START; - n_end = CONFIG_SYS_POST_FLASH_END; + info = &flash_info[CFG_SYS_POST_FLASH_NUM]; + n_start = CFG_SYS_POST_FLASH_START; + n_end = CFG_SYS_POST_FLASH_END; for (n = n_start; n < n_end; ++n) { ulong s_start, s_len, s_off; diff --git a/post/drivers/i2c.c b/post/drivers/i2c.c index 057454ffd8f..557d6329a4f 100644 --- a/post/drivers/i2c.c +++ b/post/drivers/i2c.c @@ -9,14 +9,14 @@ * * For verifying the I2C bus, a full I2C bus scanning is performed. * - * #ifdef CONFIG_SYS_POST_I2C_ADDRS + * #ifdef CFG_SYS_POST_I2C_ADDRS * The test is considered as passed if all the devices and only the devices * in the list are found. - * #ifdef CONFIG_SYS_POST_I2C_IGNORES - * Ignore devices listed in CONFIG_SYS_POST_I2C_IGNORES. These devices + * #ifdef CFG_SYS_POST_I2C_IGNORES + * Ignore devices listed in CFG_SYS_POST_I2C_IGNORES. These devices * are optional or not vital to board functionality. * #endif - * #else [ ! CONFIG_SYS_POST_I2C_ADDRS ] + * #else [ ! CFG_SYS_POST_I2C_ADDRS ] * The test is considered as passed if any I2C device is found. * #endif */ @@ -26,12 +26,12 @@ #include #include -#if CFG_POST & CONFIG_SYS_POST_I2C +#if CFG_POST & CFG_SYS_POST_I2C static int i2c_ignore_device(unsigned int chip) { -#ifdef CONFIG_SYS_POST_I2C_IGNORES - const unsigned char i2c_ignore_list[] = CONFIG_SYS_POST_I2C_IGNORES; +#ifdef CFG_SYS_POST_I2C_IGNORES + const unsigned char i2c_ignore_list[] = CFG_SYS_POST_I2C_IGNORES; int i; for (i = 0; i < sizeof(i2c_ignore_list); i++) @@ -45,7 +45,7 @@ static int i2c_ignore_device(unsigned int chip) int i2c_post_test (int flags) { unsigned int i; -#ifndef CONFIG_SYS_POST_I2C_ADDRS +#ifndef CFG_SYS_POST_I2C_ADDRS /* Start at address 1, address 0 is the general call address */ for (i = 1; i < 128; i++) { if (i2c_ignore_device(i)) @@ -59,7 +59,7 @@ int i2c_post_test (int flags) #else unsigned int ret = 0; int j; - unsigned char i2c_addr_list[] = CONFIG_SYS_POST_I2C_ADDRS; + unsigned char i2c_addr_list[] = CFG_SYS_POST_I2C_ADDRS; /* Start at address 1, address 0 is the general call address */ for (i = 1; i < 128; i++) { @@ -94,4 +94,4 @@ int i2c_post_test (int flags) #endif } -#endif /* CFG_POST & CONFIG_SYS_POST_I2C */ +#endif /* CFG_POST & CFG_SYS_POST_I2C */ diff --git a/post/drivers/rtc.c b/post/drivers/rtc.c index cfed56b680c..cc7a49847cc 100644 --- a/post/drivers/rtc.c +++ b/post/drivers/rtc.c @@ -26,7 +26,7 @@ #include #include -#if CFG_POST & CONFIG_SYS_POST_RTC +#if CFG_POST & CFG_SYS_POST_RTC static int rtc_post_skip (ulong * diff) { @@ -189,4 +189,4 @@ int rtc_post_test (int flags) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_RTC */ +#endif /* CFG_POST & CFG_SYS_POST_RTC */ diff --git a/post/lib_powerpc/andi.c b/post/lib_powerpc/andi.c index d69d61396bc..4f302166880 100644 --- a/post/lib_powerpc/andi.c +++ b/post/lib_powerpc/andi.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/asm.S b/post/lib_powerpc/asm.S index 13302d79689..93c78563936 100644 --- a/post/lib_powerpc/asm.S +++ b/post/lib_powerpc/asm.S @@ -10,7 +10,7 @@ #include #include -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU /* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */ .global cpu_post_exec_02 diff --git a/post/lib_powerpc/b.c b/post/lib_powerpc/b.c index eb9371fa6b2..0ec032dcb15 100644 --- a/post/lib_powerpc/b.c +++ b/post/lib_powerpc/b.c @@ -24,7 +24,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, diff --git a/post/lib_powerpc/cmp.c b/post/lib_powerpc/cmp.c index e4d0931fc9a..57f2b9694c3 100644 --- a/post/lib_powerpc/cmp.c +++ b/post/lib_powerpc/cmp.c @@ -23,7 +23,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/cmpi.c b/post/lib_powerpc/cmpi.c index 983892d0063..6e2bd636d74 100644 --- a/post/lib_powerpc/cmpi.c +++ b/post/lib_powerpc/cmpi.c @@ -23,7 +23,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); diff --git a/post/lib_powerpc/complex.c b/post/lib_powerpc/complex.c index d2ec21b0cbe..751bce67378 100644 --- a/post/lib_powerpc/complex.c +++ b/post/lib_powerpc/complex.c @@ -18,7 +18,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); extern int cpu_post_complex_2_asm (int x, int n); diff --git a/post/lib_powerpc/cpu.c b/post/lib_powerpc/cpu.c index 77c25381729..98a8c6392c3 100644 --- a/post/lib_powerpc/cpu.c +++ b/post/lib_powerpc/cpu.c @@ -20,7 +20,7 @@ #include #include -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern int cpu_post_test_cmp (void); extern int cpu_post_test_cmpi (void); @@ -118,4 +118,4 @@ int cpu_post_test (int flags) return ret; } -#endif /* CFG_POST & CONFIG_SYS_POST_CPU */ +#endif /* CFG_POST & CFG_SYS_POST_CPU */ diff --git a/post/lib_powerpc/cr.c b/post/lib_powerpc/cr.c index 077fb0f2da3..3c7b6113846 100644 --- a/post/lib_powerpc/cr.c +++ b/post/lib_powerpc/cr.c @@ -33,7 +33,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); extern void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); diff --git a/post/lib_powerpc/fpu/20001122-1.c b/post/lib_powerpc/fpu/20001122-1.c index eddd3f915ee..9c1c886fc4f 100644 --- a/post/lib_powerpc/fpu/20001122-1.c +++ b/post/lib_powerpc/fpu/20001122-1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU int fpu_post_test_math1 (void) { @@ -40,4 +40,4 @@ int fpu_post_test_math1 (void) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/20010114-2.c b/post/lib_powerpc/fpu/20010114-2.c index 9e3e54661f9..01bac500383 100644 --- a/post/lib_powerpc/fpu/20010114-2.c +++ b/post/lib_powerpc/fpu/20010114-2.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU static float rintf (float x) { @@ -45,4 +45,4 @@ int fpu_post_test_math2 (void) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/20010226-1.c b/post/lib_powerpc/fpu/20010226-1.c index 5bb38609003..cc4aa0dca64 100644 --- a/post/lib_powerpc/fpu/20010226-1.c +++ b/post/lib_powerpc/fpu/20010226-1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU int fpu_post_test_math3 (void) { @@ -33,4 +33,4 @@ int fpu_post_test_math3 (void) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/980619-1.c b/post/lib_powerpc/fpu/980619-1.c index 415cd50c85d..111a2013fb5 100644 --- a/post/lib_powerpc/fpu/980619-1.c +++ b/post/lib_powerpc/fpu/980619-1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU int fpu_post_test_math4 (void) { @@ -39,4 +39,4 @@ int fpu_post_test_math4 (void) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/acc1.c b/post/lib_powerpc/fpu/acc1.c index 4cf3b7cef75..63cc3eeafc3 100644 --- a/post/lib_powerpc/fpu/acc1.c +++ b/post/lib_powerpc/fpu/acc1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU static double func (const double *array) { @@ -36,4 +36,4 @@ int fpu_post_test_math5 (void) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/compare-fp-1.c b/post/lib_powerpc/fpu/compare-fp-1.c index 029600fd2b7..4b4589664f1 100644 --- a/post/lib_powerpc/fpu/compare-fp-1.c +++ b/post/lib_powerpc/fpu/compare-fp-1.c @@ -15,7 +15,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU static int failed; @@ -204,4 +204,4 @@ int fpu_post_test_math6 (void) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/fpu.c b/post/lib_powerpc/fpu/fpu.c index 8993b36e801..59109f71e36 100644 --- a/post/lib_powerpc/fpu/fpu.c +++ b/post/lib_powerpc/fpu/fpu.c @@ -21,7 +21,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU #include @@ -71,4 +71,4 @@ int fpu_post_test (int flags) return ret; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/mul-subnormal-single-1.c b/post/lib_powerpc/fpu/mul-subnormal-single-1.c index 87b882c6b22..891aa95685f 100644 --- a/post/lib_powerpc/fpu/mul-subnormal-single-1.c +++ b/post/lib_powerpc/fpu/mul-subnormal-single-1.c @@ -15,7 +15,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU union uf { @@ -82,4 +82,4 @@ int fpu_post_test_math7 (void) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/load.c b/post/lib_powerpc/load.c index ece0b2756e0..e4ac6bf186f 100644 --- a/post/lib_powerpc/load.c +++ b/post/lib_powerpc/load.c @@ -28,7 +28,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); extern void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); diff --git a/post/lib_powerpc/multi.c b/post/lib_powerpc/multi.c index 0e9ee88eb5d..4df45790ab6 100644 --- a/post/lib_powerpc/multi.c +++ b/post/lib_powerpc/multi.c @@ -21,7 +21,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_02(ulong *code, ulong op1, ulong op2); diff --git a/post/lib_powerpc/rlwimi.c b/post/lib_powerpc/rlwimi.c index d24a3f665c7..da219132257 100644 --- a/post/lib_powerpc/rlwimi.c +++ b/post/lib_powerpc/rlwimi.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/rlwinm.c b/post/lib_powerpc/rlwinm.c index 9f4a3edb3ea..b0b976f98af 100644 --- a/post/lib_powerpc/rlwinm.c +++ b/post/lib_powerpc/rlwinm.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/rlwnm.c b/post/lib_powerpc/rlwnm.c index 224e6bdd45e..22cd4568fc8 100644 --- a/post/lib_powerpc/rlwnm.c +++ b/post/lib_powerpc/rlwnm.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/srawi.c b/post/lib_powerpc/srawi.c index 713d4f2276b..a103df75eb1 100644 --- a/post/lib_powerpc/srawi.c +++ b/post/lib_powerpc/srawi.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/store.c b/post/lib_powerpc/store.c index 2dbcccf098a..71a4b6aba43 100644 --- a/post/lib_powerpc/store.c +++ b/post/lib_powerpc/store.c @@ -28,7 +28,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); extern void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); diff --git a/post/lib_powerpc/string.c b/post/lib_powerpc/string.c index 9b54847632a..21e02bcb266 100644 --- a/post/lib_powerpc/string.c +++ b/post/lib_powerpc/string.c @@ -20,7 +20,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); extern void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, diff --git a/post/lib_powerpc/three.c b/post/lib_powerpc/three.c index 55f0ff8a882..68339b05ef2 100644 --- a/post/lib_powerpc/three.c +++ b/post/lib_powerpc/three.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/threei.c b/post/lib_powerpc/threei.c index ec52d238e69..885dd8cb095 100644 --- a/post/lib_powerpc/threei.c +++ b/post/lib_powerpc/threei.c @@ -21,7 +21,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/threex.c b/post/lib_powerpc/threex.c index 6f5f0b8eb76..62ac713ecff 100644 --- a/post/lib_powerpc/threex.c +++ b/post/lib_powerpc/threex.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/two.c b/post/lib_powerpc/two.c index b44dd4e2084..7985669ba6e 100644 --- a/post/lib_powerpc/two.c +++ b/post/lib_powerpc/two.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/twox.c b/post/lib_powerpc/twox.c index 320cc0a64e7..33d1a1d8d91 100644 --- a/post/lib_powerpc/twox.c +++ b/post/lib_powerpc/twox.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); extern ulong cpu_post_makecr (long v); diff --git a/post/post.c b/post/post.c index 9964b410804..4db862c0dbb 100644 --- a/post/post.c +++ b/post/post.c @@ -16,7 +16,7 @@ #include #include -#ifdef CONFIG_SYS_POST_HOTKEYS_GPIO +#ifdef CFG_SYS_POST_HOTKEYS_GPIO #include #endif @@ -55,9 +55,9 @@ int post_init_f(void) */ __weak int post_hotkeys_pressed(void) { -#ifdef CONFIG_SYS_POST_HOTKEYS_GPIO +#ifdef CFG_SYS_POST_HOTKEYS_GPIO int ret; - unsigned gpio = CONFIG_SYS_POST_HOTKEYS_GPIO; + unsigned gpio = CFG_SYS_POST_HOTKEYS_GPIO; ret = gpio_request(gpio, "hotkeys"); if (ret) { diff --git a/post/tests.c b/post/tests.c index d61ea74d512..8cea428fcdc 100644 --- a/post/tests.c +++ b/post/tests.c @@ -45,7 +45,7 @@ extern void sysmon_reloc (void); struct post_test post_list[] = { -#if CFG_POST & CONFIG_SYS_POST_OCM +#if CFG_POST & CFG_SYS_POST_OCM { "OCM test", "ocm", @@ -54,10 +54,10 @@ struct post_test post_list[] = &ocm_post_test, NULL, NULL, - CONFIG_SYS_POST_OCM + CFG_SYS_POST_OCM }, #endif -#if CFG_POST & CONFIG_SYS_POST_CACHE +#if CFG_POST & CFG_SYS_POST_CACHE { "Cache test", "cache", @@ -66,10 +66,10 @@ struct post_test post_list[] = &cache_post_test, NULL, NULL, - CONFIG_SYS_POST_CACHE + CFG_SYS_POST_CACHE }, #endif -#if CFG_POST & CONFIG_SYS_POST_WATCHDOG +#if CFG_POST & CFG_SYS_POST_WATCHDOG #if defined(CFG_POST_WATCHDOG) CFG_POST_WATCHDOG, #else @@ -81,11 +81,11 @@ struct post_test post_list[] = &watchdog_post_test, NULL, NULL, - CONFIG_SYS_POST_WATCHDOG + CFG_SYS_POST_WATCHDOG }, #endif #endif -#if CFG_POST & CONFIG_SYS_POST_I2C +#if CFG_POST & CFG_SYS_POST_I2C { "I2C test", "i2c", @@ -94,10 +94,10 @@ struct post_test post_list[] = &i2c_post_test, NULL, NULL, - CONFIG_SYS_POST_I2C + CFG_SYS_POST_I2C }, #endif -#if CFG_POST & CONFIG_SYS_POST_RTC +#if CFG_POST & CFG_SYS_POST_RTC { "RTC test", "rtc", @@ -106,7 +106,7 @@ struct post_test post_list[] = &rtc_post_test, NULL, NULL, - CONFIG_SYS_POST_RTC + CFG_SYS_POST_RTC }, #endif #if CFG_POST & CFG_SYS_POST_MEMORY @@ -121,7 +121,7 @@ struct post_test post_list[] = CFG_SYS_POST_MEMORY }, #endif -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU { "CPU test", "cpu", @@ -131,10 +131,10 @@ struct post_test post_list[] = &cpu_post_test, NULL, NULL, - CONFIG_SYS_POST_CPU + CFG_SYS_POST_CPU }, #endif -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU { "FPU test", "fpu", @@ -144,10 +144,10 @@ struct post_test post_list[] = &fpu_post_test, NULL, NULL, - CONFIG_SYS_POST_FPU + CFG_SYS_POST_FPU }, #endif -#if CFG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CFG_SYS_POST_UART #if defined(CFG_POST_UART) CFG_POST_UART, #else @@ -159,11 +159,11 @@ struct post_test post_list[] = &uart_post_test, NULL, NULL, - CONFIG_SYS_POST_UART + CFG_SYS_POST_UART }, #endif /* CFG_POST_UART */ #endif -#if CFG_POST & CONFIG_SYS_POST_ETHER +#if CFG_POST & CFG_SYS_POST_ETHER { "ETHERNET test", "ethernet", @@ -172,10 +172,10 @@ struct post_test post_list[] = ðer_post_test, NULL, NULL, - CONFIG_SYS_POST_ETHER + CFG_SYS_POST_ETHER }, #endif -#if CFG_POST & CONFIG_SYS_POST_USB +#if CFG_POST & CFG_SYS_POST_USB { "USB test", "usb", @@ -184,10 +184,10 @@ struct post_test post_list[] = &usb_post_test, NULL, NULL, - CONFIG_SYS_POST_USB + CFG_SYS_POST_USB }, #endif -#if CFG_POST & CONFIG_SYS_POST_SPR +#if CFG_POST & CFG_SYS_POST_SPR { "SPR test", "spr", @@ -196,10 +196,10 @@ struct post_test post_list[] = &spr_post_test, NULL, NULL, - CONFIG_SYS_POST_SPR + CFG_SYS_POST_SPR }, #endif -#if CFG_POST & CONFIG_SYS_POST_SYSMON +#if CFG_POST & CFG_SYS_POST_SYSMON { "SYSMON test", "sysmon", @@ -208,10 +208,10 @@ struct post_test post_list[] = &sysmon_post_test, &sysmon_init_f, &sysmon_reloc, - CONFIG_SYS_POST_SYSMON + CFG_SYS_POST_SYSMON }, #endif -#if CFG_POST & CONFIG_SYS_POST_DSP +#if CFG_POST & CFG_SYS_POST_DSP { "DSP test", "dsp", @@ -220,10 +220,10 @@ struct post_test post_list[] = &dsp_post_test, NULL, NULL, - CONFIG_SYS_POST_DSP + CFG_SYS_POST_DSP }, #endif -#if CFG_POST & CONFIG_SYS_POST_CODEC +#if CFG_POST & CFG_SYS_POST_CODEC { "CODEC test", "codec", @@ -232,10 +232,10 @@ struct post_test post_list[] = &codec_post_test, NULL, NULL, - CONFIG_SYS_POST_CODEC + CFG_SYS_POST_CODEC }, #endif -#if CFG_POST & CONFIG_SYS_POST_ECC +#if CFG_POST & CFG_SYS_POST_ECC { "ECC test", "ecc", @@ -244,25 +244,25 @@ struct post_test post_list[] = &ecc_post_test, NULL, NULL, - CONFIG_SYS_POST_ECC + CFG_SYS_POST_ECC }, #endif -#if CFG_POST & CONFIG_SYS_POST_BSPEC1 +#if CFG_POST & CFG_SYS_POST_BSPEC1 CFG_POST_BSPEC1, #endif -#if CFG_POST & CONFIG_SYS_POST_BSPEC2 +#if CFG_POST & CFG_SYS_POST_BSPEC2 CFG_POST_BSPEC2, #endif -#if CFG_POST & CONFIG_SYS_POST_BSPEC3 +#if CFG_POST & CFG_SYS_POST_BSPEC3 CFG_POST_BSPEC3, #endif -#if CFG_POST & CONFIG_SYS_POST_BSPEC4 +#if CFG_POST & CFG_SYS_POST_BSPEC4 CFG_POST_BSPEC4, #endif -#if CFG_POST & CONFIG_SYS_POST_BSPEC5 +#if CFG_POST & CFG_SYS_POST_BSPEC5 CFG_POST_BSPEC5, #endif -#if CFG_POST & CONFIG_SYS_POST_COPROC +#if CFG_POST & CFG_SYS_POST_COPROC { "Coprocessors communication test", "coproc_com", @@ -271,10 +271,10 @@ struct post_test post_list[] = &coprocessor_post_test, NULL, NULL, - CONFIG_SYS_POST_COPROC + CFG_SYS_POST_COPROC }, #endif -#if CFG_POST & CONFIG_SYS_POST_FLASH +#if CFG_POST & CFG_SYS_POST_FLASH { "Parallel NOR flash test", "flash", @@ -283,7 +283,7 @@ struct post_test post_list[] = &flash_post_test, NULL, NULL, - CONFIG_SYS_POST_FLASH + CFG_SYS_POST_FLASH }, #endif #if CFG_POST & CFG_SYS_POST_MEM_REGIONS -- cgit v1.3.1 From b5fd7b4a31e5098ff024ebc63bccfcb2b4429c82 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 12 Dec 2022 14:12:07 -0500 Subject: image: Add fallback for fit_config_verify Add a fallback for this function so it can be used without regard to whether FIT_SIGNATURE is enabled or not. Signed-off-by: Sean Anderson Reviewed-by: Tom Rini Reviewed-by: Simon Glass --- include/image.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/image.h b/include/image.h index b6a809834ad..6f9c5a486bc 100644 --- a/include/image.h +++ b/include/image.h @@ -1259,7 +1259,14 @@ int fit_image_verify_with_data(const void *fit, int image_noffset, size_t size); int fit_image_verify(const void *fit, int noffset); +#if CONFIG_IS_ENABLED(FIT_SIGNATURE) int fit_config_verify(const void *fit, int conf_noffset); +#else +static inline int fit_config_verify(const void *fit, int conf_noffset) +{ + return 0; +} +#endif int fit_all_image_verify(const void *fit); int fit_config_decrypt(const void *fit, int conf_noffset); int fit_image_check_os(const void *fit, int noffset, uint8_t os); -- cgit v1.3.1 From bcc85b96b5ffbbce19a89747138feb873d918915 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 12 Dec 2022 14:12:11 -0500 Subject: cmd: source: Support specifying config name As discussed previously [1,2], the source command is not safe to use with verified boot unless there is a key with required = "images" (which has its own problems). This is because if such a key is absent, signatures are verified but not required. It is assumed that configuration nodes will provide the signature. Because the source command does not use configurations to determine the image to source, effectively no verification takes place. To address this, allow specifying configuration nodes. We use the same syntax as the bootm command (helpfully provided for us by fit_parse_conf). By default, we first try the default config and then the default image. To force using a config, # must be present in the command (e.g. `source $loadaddr#my-conf`). For convenience, the config may be omitted, just like the address may be (e.g. `source \#`). This also works for images (`source :` behaves exactly like `source` currently does). [1] https://lore.kernel.org/u-boot/7d711133-d513-5bcb-52f2-a9dbaa9eeded@prevas.dk/ [2] https://lore.kernel.org/u-boot/042dcb34-f85f-351e-1b0e-513f89005fdd@gmail.com/ Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- .../arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c | 2 +- boot/bootmeth_script.c | 2 +- cmd/source.c | 74 ++++++++++++++++------ doc/uImage.FIT/source_file_format.txt | 3 + drivers/usb/gadget/f_sdp.c | 2 +- include/image.h | 15 ++++- test/py/tests/test_source.py | 11 +++- 7 files changed, 81 insertions(+), 28 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index 3627b4c35c9..cb13a14d829 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -154,7 +154,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, do_bootz(cmdtp, 0, 4, bootm_argv); } if (data->script) - image_source_script(data->script, NULL); + image_source_script(data->script, NULL, NULL); if (reset) { puts("Reset...\n"); diff --git a/boot/bootmeth_script.c b/boot/bootmeth_script.c index d1c3f940037..6c84721d1cd 100644 --- a/boot/bootmeth_script.c +++ b/boot/bootmeth_script.c @@ -101,7 +101,7 @@ static int script_boot(struct udevice *dev, struct bootflow *bflow) log_debug("mmc_bootdev: %s\n", env_get("mmc_bootdev")); addr = map_to_sysmem(bflow->buf); - ret = image_source_script(addr, NULL); + ret = image_source_script(addr, NULL, NULL); if (ret) return log_msg_ret("boot", ret); diff --git a/cmd/source.c b/cmd/source.c index 59738246018..94da5d8d6ad 100644 --- a/cmd/source.c +++ b/cmd/source.c @@ -42,7 +42,7 @@ static const char *get_default_image(const void *fit) } #endif -int image_source_script(ulong addr, const char *fit_uname) +int image_source_script(ulong addr, const char *fit_uname, const char *confname) { ulong len; #if defined(CONFIG_LEGACY_IMAGE_FORMAT) @@ -112,19 +112,47 @@ int image_source_script(ulong addr, const char *fit_uname) return 1; } - if (!fit_uname) - fit_uname = get_default_image(fit_hdr); - if (!fit_uname) { - puts("No FIT subimage unit name\n"); - return 1; - } + /* If confname is empty, use the default */ + if (confname && *confname) + noffset = fit_conf_get_node(fit_hdr, confname); + else + noffset = fit_conf_get_node(fit_hdr, NULL); + if (noffset < 0) { + if (!confname) + goto fallback; + printf("Could not find config %s\n", confname); + return 1; + } - /* get script component image node offset */ - noffset = fit_image_get_node (fit_hdr, fit_uname); - if (noffset < 0) { - printf ("Can't find '%s' FIT subimage\n", fit_uname); - return 1; + if (verify && fit_config_verify(fit_hdr, noffset)) + return 1; + + noffset = fit_conf_get_prop_node(fit_hdr, noffset, + FIT_SCRIPT_PROP, + IH_PHASE_NONE); + if (noffset < 0) { + if (!confname) + goto fallback; + printf("Could not find script in %s\n", confname); + return 1; + } + } else { +fallback: + if (!fit_uname || !*fit_uname) + fit_uname = get_default_image(fit_hdr); + if (!fit_uname) { + puts("No FIT subimage unit name\n"); + return 1; + } + + /* get script component image node offset */ + noffset = fit_image_get_node(fit_hdr, fit_uname); + if (noffset < 0) { + printf("Can't find '%s' FIT subimage\n", + fit_uname); + return 1; + } } if (!fit_image_check_type (fit_hdr, noffset, IH_TYPE_SCRIPT)) { @@ -164,7 +192,7 @@ static int do_source(struct cmd_tbl *cmdtp, int flag, int argc, { ulong addr; int rcode; - const char *fit_uname = NULL; + const char *fit_uname = NULL, *confname = NULL; /* Find script image */ if (argc < 2) { @@ -175,6 +203,9 @@ static int do_source(struct cmd_tbl *cmdtp, int flag, int argc, &fit_uname)) { debug("* source: subimage '%s' from FIT image at 0x%08lx\n", fit_uname, addr); + } else if (fit_parse_conf(argv[1], image_load_addr, &addr, &confname)) { + debug("* source: config '%s' from FIT image at 0x%08lx\n", + confname, addr); #endif } else { addr = hextoul(argv[1], NULL); @@ -182,21 +213,22 @@ static int do_source(struct cmd_tbl *cmdtp, int flag, int argc, } printf ("## Executing script at %08lx\n", addr); - rcode = image_source_script(addr, fit_uname); + rcode = image_source_script(addr, fit_uname, confname); return rcode; } #ifdef CONFIG_SYS_LONGHELP static char source_help_text[] = - "[addr]\n" - "\t- run script starting at addr\n" - "\t- A valid image header must be present" #if defined(CONFIG_FIT) - "\n" - "For FIT format uImage addr must include subimage\n" - "unit name in the form of addr:" + "[][:[]|#[]]\n" + "\t- Run script starting at addr\n" + "\t- A FIT config name or subimage name may be specified with : or #\n" + "\t (like bootm). If the image or config name is omitted, the\n" + "\t default is used."; +#else + "[]\n" + "\t- Run script starting at addr"; #endif - ""; #endif U_BOOT_CMD( diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt index 4640e38e3cc..269e1fa0b58 100644 --- a/doc/uImage.FIT/source_file_format.txt +++ b/doc/uImage.FIT/source_file_format.txt @@ -247,6 +247,7 @@ o config-1 |- kernel = "kernel sub-node unit name" |- fdt = "fdt sub-node unit-name" [, "fdt overlay sub-node unit-name", ...] |- loadables = "loadables sub-node unit-name" + |- script = " |- compatible = "vendor,board-style device tree compatible string" @@ -268,6 +269,8 @@ o config-1 of strings. U-Boot will load each binary at its given start-address and may optionally invoke additional post-processing steps on this binary based on its component image node type. + - script : The image to use when loading a U-Boot script (for use with the + source command). - compatible : The root compatible string of the U-Boot device tree that this configuration shall automatically match when CONFIG_FIT_BEST_MATCH is enabled. If this property is not provided, the compatible string will be diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index 1643d289477..5ae5b62741a 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -868,7 +868,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, jump_to_image_no_args(&spl_image); #else /* In U-Boot, allow jumps to scripts */ - image_source_script(sdp_func->jmp_address, NULL); + image_source_script(sdp_func->jmp_address, NULL, NULL); #endif } diff --git a/include/image.h b/include/image.h index 6f9c5a486bc..bed75ce1b38 100644 --- a/include/image.h +++ b/include/image.h @@ -711,15 +711,23 @@ int fit_image_load(struct bootm_headers *images, ulong addr, /** * image_source_script() - Execute a script + * @addr: Address of script + * @fit_uname: FIT subimage name + * @confname: FIT config name. The subimage is chosen based on FIT_SCRIPT_PROP. * * Executes a U-Boot script at a particular address in memory. The script should * have a header (FIT or legacy) with the script type (IH_TYPE_SCRIPT). * - * @addr: Address of script - * @fit_uname: FIT subimage name + * If @fit_uname is the empty string, then the default image is used. If + * @confname is the empty string, the default config is used. If @confname and + * @fit_uname are both non-%NULL, then @confname is ignored. If @confname and + * @fit_uname are both %NULL, then first the default config is tried, and then + * the default image. + * * Return: result code (enum command_ret_t) */ -int image_source_script(ulong addr, const char *fit_uname); +int image_source_script(ulong addr, const char *fit_uname, + const char *confname); /** * fit_get_node_from_config() - Look up an image a FIT by type @@ -1032,6 +1040,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, #define FIT_FPGA_PROP "fpga" #define FIT_FIRMWARE_PROP "firmware" #define FIT_STANDALONE_PROP "standalone" +#define FIT_SCRIPT_PROP "script" #define FIT_PHASE_PROP "phase" #define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE diff --git a/test/py/tests/test_source.py b/test/py/tests/test_source.py index e5ffdfe3fc4..bbc311df6d1 100644 --- a/test/py/tests/test_source.py +++ b/test/py/tests/test_source.py @@ -18,11 +18,20 @@ def test_source(u_boot_console): util.run_and_log(cons, (mkimage, '-f', its, fit)) cons.run_command(f'host load hostfs - $loadaddr {fit}') - assert '1' in cons.run_command('source') + assert '2' in cons.run_command('source') + assert '1' in cons.run_command('source :') assert '1' in cons.run_command('source :script-1') assert '2' in cons.run_command('source :script-2') assert 'Fail' in cons.run_command('source :not-a-script || echo Fail') + assert '2' in cons.run_command('source \\#') + assert '1' in cons.run_command('source \\#conf-1') + assert '2' in cons.run_command('source \\#conf-2') cons.run_command('fdt addr $loadaddr') + cons.run_command('fdt rm /configurations default') + assert '1' in cons.run_command('source') + assert 'Fail' in cons.run_command('source \\# || echo Fail') + cons.run_command('fdt rm /images default') assert 'Fail' in cons.run_command('source || echo Fail') + assert 'Fail' in cons.run_command('source \\# || echo Fail') -- cgit v1.3.1 From 872413bb0a03831ffe6f060b40cdb8bcc76f9867 Mon Sep 17 00:00:00 2001 From: Dai Okamura Date: Fri, 9 Dec 2022 20:33:48 +0900 Subject: arm: uniphier: use DM_TIMER of arm a9 global timer All uniphier v7 SoCs have cortex-a9 and use cortex-a9 global timer in a simple implementation. Now DM_TIMER of it is available on 35751c7f3f ("timer: sti: convert sti-timer to arm a9 global timer"), so let's switch to it. The old driver reads the lower 32bits of counter field and sets the prescaler as 50 with PERIPHCLK(=50MHz), so the global timer works as a 32-bit 1MHz timer. The DM_TIMER uses the whole 64bits with no prescaler, so the global timer works as a 64-bit PERIPHCLK timer. CONFIG_SYS_HZ_CLOCK is set as the default PERIPHCLK frequency, if there is no 'clocks' property in devicetree. Signed-off-by: Dai Okamura --- arch/arm/dts/uniphier-v7-u-boot.dtsi | 4 ++++ arch/arm/mach-uniphier/Kconfig | 1 + arch/arm/mach-uniphier/arm32/Makefile | 2 -- arch/arm/mach-uniphier/arm32/timer.c | 39 ----------------------------------- configs/uniphier_ld4_sld8_defconfig | 2 ++ configs/uniphier_v7_defconfig | 2 ++ include/configs/uniphier.h | 3 +-- 7 files changed, 10 insertions(+), 43 deletions(-) delete mode 100644 arch/arm/mach-uniphier/arm32/timer.c (limited to 'include') diff --git a/arch/arm/dts/uniphier-v7-u-boot.dtsi b/arch/arm/dts/uniphier-v7-u-boot.dtsi index 9459bf03775..603b33dd2b9 100644 --- a/arch/arm/dts/uniphier-v7-u-boot.dtsi +++ b/arch/arm/dts/uniphier-v7-u-boot.dtsi @@ -2,6 +2,10 @@ soc { u-boot,dm-pre-reloc; + timer@60000200 { + u-boot,dm-pre-reloc; + }; + serial@54006800 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 3a8eee7b843..c570fb3294d 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -12,6 +12,7 @@ config ARCH_UNIPHIER_V7_MULTI select ARMV7_NONSEC select CPU_V7A select CPU_V7_HAS_NONSEC + select ARM_GLOBAL_TIMER if TIMER config ARCH_UNIPHIER_V8_MULTI bool "UniPhier V8 SoCs" diff --git a/arch/arm/mach-uniphier/arm32/Makefile b/arch/arm/mach-uniphier/arm32/Makefile index 3cd00b7e5e9..b41aba7e29a 100644 --- a/arch/arm/mach-uniphier/arm32/Makefile +++ b/arch/arm/mach-uniphier/arm32/Makefile @@ -8,5 +8,3 @@ obj-y += late_lowlevel_init.o obj-y += cache-uniphier.o obj-$(CONFIG_ARMV7_PSCI) += psci.o psci_smp.o endif - -obj-y += timer.o diff --git a/arch/arm/mach-uniphier/arm32/timer.c b/arch/arm/mach-uniphier/arm32/timer.c deleted file mode 100644 index 58247c2738a..00000000000 --- a/arch/arm/mach-uniphier/arm32/timer.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012-2015 Masahiro Yamada - */ - -#include -#include -#include - -#include "arm-mpcore.h" - -#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */ -#define PRESCALER ((PERIPHCLK) / (CFG_SYS_TIMER_RATE) - 1) - -static void *get_global_timer_base(void) -{ - void *val; - - asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory"); - - return val + GLOBAL_TIMER_OFFSET; -} - -unsigned long timer_read_counter(void) -{ - /* - * ARM 64bit Global Timer is too much for our purpose. - * We use only lower 32 bit of the timer counter. - */ - return readl(get_global_timer_base() + GTIMER_CNT_L); -} - -int timer_init(void) -{ - /* enable timer */ - writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL); - - return 0; -} diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index b361e3f4034..b11dea593a9 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -13,6 +13,8 @@ CONFIG_SYS_LOAD_ADDR=0x85000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000 CONFIG_SYS_MONITOR_LEN=2097152 +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y CONFIG_TIMESTAMP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index 765d42a3e6c..d626968c76d 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -13,6 +13,8 @@ CONFIG_SYS_LOAD_ADDR=0x85000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000 CONFIG_SYS_MONITOR_LEN=2097152 +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y CONFIG_TIMESTAMP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index ecf0d2ac44a..0a14d0448c6 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -36,8 +36,7 @@ BOOT_TARGET_DEVICE_USB(func) #if !defined(CONFIG_ARM64) -/* Time clock 1MHz */ -#define CFG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_HZ_CLOCK 50000000 #endif #define CFG_SYS_NAND_REGS_BASE 0x68100000 -- cgit v1.3.1 From 28663622cf0767d0c5f31629ab50e34069bf0267 Mon Sep 17 00:00:00 2001 From: Stefan Bosch Date: Sun, 18 Dec 2022 12:26:47 +0000 Subject: arm: s5p4418: dm_serial: remove old code / add DEBUG_UART Remove init of UART-clock and UART-reset in arch_cpu_init(). Add DEBUG_UART to s5p4418_nanopi2_defconfig. Signed-off-by: Stefan Bosch --- arch/arm/cpu/armv7/s5p4418/cpu.c | 29 ----------------------------- arch/arm/mach-nexell/clock.c | 2 +- configs/s5p4418_nanopi2_defconfig | 6 +++++- include/configs/s5p4418_nanopi2.h | 8 +++----- 4 files changed, 9 insertions(+), 36 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 7ba9c0b0323..fcaafc0ff76 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -13,10 +13,8 @@ #include #include #include -#include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -45,39 +43,12 @@ static void cpu_soc_init(void) nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1); } -#ifdef CONFIG_PL011_SERIAL -static void serial_device_init(void) -{ - char dev[10]; - int id; - - sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX); - id = RESET_ID_UART0 + CONFIG_CONS_INDEX; - - struct clk *clk = clk_get((const char *)dev); - - /* reset control: Low active ___|--- */ - nx_rstcon_setrst(id, RSTCON_ASSERT); - udelay(10); - nx_rstcon_setrst(id, RSTCON_NEGATE); - udelay(10); - - /* set clock */ - clk_disable(clk); - clk_set_rate(clk, CFG_PL011_CLOCK); - clk_enable(clk); -} -#endif - int arch_cpu_init(void) { flush_dcache_all(); cpu_soc_init(); clk_init(); - if (IS_ENABLED(CONFIG_PL011_SERIAL)) - serial_device_init(); - return 0; } diff --git a/arch/arm/mach-nexell/clock.c b/arch/arm/mach-nexell/clock.c index 24fa204ccd2..59ffa26255f 100644 --- a/arch/arm/mach-nexell/clock.c +++ b/arch/arm/mach-nexell/clock.c @@ -856,7 +856,7 @@ void __init clk_init(void) } /* prevent uart clock disable for low step debug message */ - #ifndef CONFIG_DEBUG_NX_UART + #ifndef CONFIG_DEBUG_UART if (peri->dev_name) { #ifdef CONFIG_BACKLIGHT_PWM if (!strcmp(peri->dev_name, DEV_NAME_PWM)) diff --git a/configs/s5p4418_nanopi2_defconfig b/configs/s5p4418_nanopi2_defconfig index 35e7c880598..0645b09f78a 100644 --- a/configs/s5p4418_nanopi2_defconfig +++ b/configs/s5p4418_nanopi2_defconfig @@ -11,12 +11,15 @@ CONFIG_ENV_OFFSET=0x2E0200 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="s5p4418-nanopi2" CONFIG_SYS_PROMPT="nanopi2# " +CONFIG_DEBUG_UART_BASE=0xC00A1000 +CONFIG_DEBUG_UART_CLOCK=150000000 CONFIG_TARGET_NANOPI2=y CONFIG_S5P4418_ONEWIRE=y CONFIG_ROOT_DEV=1 CONFIG_BOOT_PART=1 CONFIG_ROOT_PART=2 CONFIG_SYS_LOAD_ADDR=0x71080000 +CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x71000000 CONFIG_SYS_MEMTEST_END=0xb0000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -54,7 +57,8 @@ CONFIG_MMC_DW=y CONFIG_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y -CONFIG_CONS_INDEX=0 +CONFIG_DEBUG_UART_PL011=y +CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y CONFIG_DISPLAY=y diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index 2fa44e65fc1..fec1bfd50eb 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -76,11 +76,9 @@ /*----------------------------------------------------------------------- * serial console configuration */ -#define CFG_PL011_CLOCK 50000000 -#define CFG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \ - (void *)PHY_BASEADDR_UART1, \ - (void *)PHY_BASEADDR_UART2, \ - (void *)PHY_BASEADDR_UART3} + +/* 150MHz is the clock rate set by SPL (uart0) */ +#define CFG_PL011_CLOCK 150000000 /*----------------------------------------------------------------------- * BACKLIGHT -- cgit v1.3.1 From 7b88887ba78d100bcb74d3e0baa03f87a338e707 Mon Sep 17 00:00:00 2001 From: Sergiu Moga Date: Wed, 4 Jan 2023 16:04:13 +0200 Subject: dt-bindings: reset: add sama7g5 definitions Upstream linux commit 5994f58977e0. Add reset bindings for SAMA7G5. At the moment only USB PHYs are included. The three reset USB phy's have their ID's mapped from 4 to 6. There are no USB phy's with ID's numbered from 0 to 3. Signed-off-by: Sergiu Moga --- include/dt-bindings/reset/sama7g5-reset.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 include/dt-bindings/reset/sama7g5-reset.h (limited to 'include') diff --git a/include/dt-bindings/reset/sama7g5-reset.h b/include/dt-bindings/reset/sama7g5-reset.h new file mode 100644 index 00000000000..2116f41d04e --- /dev/null +++ b/include/dt-bindings/reset/sama7g5-reset.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_RESET_SAMA7G5_H +#define __DT_BINDINGS_RESET_SAMA7G5_H + +#define SAMA7G5_RESET_USB_PHY1 4 +#define SAMA7G5_RESET_USB_PHY2 5 +#define SAMA7G5_RESET_USB_PHY3 6 + +#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */ -- cgit v1.3.1 From ee25ed5899b8a7ee125e58298bd1b71feedb79f1 Mon Sep 17 00:00:00 2001 From: Sergiu Moga Date: Wed, 4 Jan 2023 16:04:14 +0200 Subject: dt-bindings: clk: at91: Define additional UTMI related clocks Add definitions for an additional main UTMI clock as well as its respective subclocks. Signed-off-by: Sergiu Moga --- include/dt-bindings/clk/at91.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/dt-bindings/clk/at91.h b/include/dt-bindings/clk/at91.h index e30756b2804..a178b94157b 100644 --- a/include/dt-bindings/clk/at91.h +++ b/include/dt-bindings/clk/at91.h @@ -18,5 +18,10 @@ #define PMC_TYPE_PERIPHERAL 3 #define PMC_TYPE_GCK 4 #define PMC_TYPE_SLOW 5 +#define USB_UTMI 6 + +#define USB_UTMI1 0 +#define USB_UTMI2 1 +#define USB_UTMI3 2 #endif -- cgit v1.3.1 From 7363cf0581a3e70b3dbd346dec8b7ae652776f80 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 20 Dec 2022 12:22:03 +0200 Subject: mtd: rawnand: omap_elm: u-boot driver model support Support u-boot driver model. We still retain support legacy way of doing things if ELM_BASE is defined in We could completely get rid of that if all platforms defining ELM_BASE get rid of that definition and enable CONFIG_SYS_NAND_SELF_INIT and are verified to work. Signed-off-by: Roger Quadros Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Reviewed-by: Tom Rini Link: https://lore.kernel.org/all/20221220102203.52398-9-rogerq@kernel.org Link: https://lore.kernel.org/all/CABGWkvrvKiVA_yaDnHJcHEKwc+pEuLdz=i6HQEY0oJQvohCUsw@mail.gmail.com --- drivers/mtd/nand/raw/omap_elm.c | 38 +++++++++++++++++- drivers/mtd/nand/raw/omap_elm.h | 85 ++++++++++++++++++++++++++++++++++++++++ drivers/mtd/nand/raw/omap_gpmc.c | 12 +++++- include/linux/mtd/omap_elm.h | 79 ------------------------------------- 4 files changed, 133 insertions(+), 81 deletions(-) create mode 100644 drivers/mtd/nand/raw/omap_elm.h delete mode 100644 include/linux/mtd/omap_elm.h (limited to 'include') diff --git a/drivers/mtd/nand/raw/omap_elm.c b/drivers/mtd/nand/raw/omap_elm.c index 35c6dd1f1bc..56a2c39e4f6 100644 --- a/drivers/mtd/nand/raw/omap_elm.c +++ b/drivers/mtd/nand/raw/omap_elm.c @@ -15,9 +15,14 @@ #include #include #include -#include #include +#include +#include +#include + +#include "omap_elm.h" + #define DRIVER_NAME "omap-elm" #define ELM_DEFAULT_POLY (0) @@ -180,6 +185,7 @@ void elm_reset(void) ; } +#ifdef ELM_BASE /** * elm_init - Initialize ELM module * @@ -191,3 +197,33 @@ void elm_init(void) elm_cfg = (struct elm *)ELM_BASE; elm_reset(); } +#endif + +#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT) + +static int elm_probe(struct udevice *dev) +{ +#ifndef ELM_BASE + struct resource res; + + dev_read_resource(dev, 0, &res); + elm_cfg = devm_ioremap(dev, res.start, resource_size(&res)); + elm_reset(); +#endif + + return 0; +} + +static const struct udevice_id elm_ids[] = { + { .compatible = "ti,am3352-elm" }, + { .compatible = "ti,am64-elm" }, + { } +}; + +U_BOOT_DRIVER(gpmc_elm) = { + .name = DRIVER_NAME, + .id = UCLASS_MTD, + .of_match = elm_ids, + .probe = elm_probe, +}; +#endif /* CONFIG_SYS_NAND_SELF_INIT */ diff --git a/drivers/mtd/nand/raw/omap_elm.h b/drivers/mtd/nand/raw/omap_elm.h new file mode 100644 index 00000000000..a7f7bacb154 --- /dev/null +++ b/drivers/mtd/nand/raw/omap_elm.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2011 Texas Instruments, + * Mansoor Ahamed + * + * Derived from work done by Rohit Choraria for omap3 + */ +#ifndef __ASM_ARCH_ELM_H +#define __ASM_ARCH_ELM_H +/* + * ELM Module Registers + */ + +/* ELM registers bit fields */ +#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2) +#define ELM_SYSCONFIG_SOFTRESET (0x2) +#define ELM_SYSSTATUS_RESETDONE_MASK (0x1) +#define ELM_SYSSTATUS_RESETDONE (0x1) +#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3) +#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000) +#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16) +#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000) +#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100) +#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F) + +#define ELM_MAX_CHANNELS 8 +#define ELM_MAX_ERROR_COUNT 16 + +#ifndef __ASSEMBLY__ + +enum bch_level { + BCH_4_BIT = 0, + BCH_8_BIT, + BCH_16_BIT +}; + + +/* BCH syndrome registers */ +struct syndrome { + u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */ + u8 res1[36]; /* 0x41c */ +}; + +/* BCH error status & location register */ +struct location { + u32 location_status; /* 0x800 */ + u8 res1[124]; /* 0x804 */ + u32 error_location_x[ELM_MAX_ERROR_COUNT]; /* 0x880, 0x980, .. */ + u8 res2[64]; /* 0x8c0 */ +}; + +/* BCH ELM register map - do not try to allocate memmory for this structure. + * We have used plenty of reserved variables to fill the slots in the ELM + * register memory map. + * Directly initialize the struct pointer to ELM base address. + */ +struct elm { + u32 rev; /* 0x000 */ + u8 res1[12]; /* 0x004 */ + u32 sysconfig; /* 0x010 */ + u32 sysstatus; /* 0x014 */ + u32 irqstatus; /* 0x018 */ + u32 irqenable; /* 0x01c */ + u32 location_config; /* 0x020 */ + u8 res2[92]; /* 0x024 */ + u32 page_ctrl; /* 0x080 */ + u8 res3[892]; /* 0x084 */ + struct syndrome syndrome_fragments[ELM_MAX_CHANNELS]; /* 0x400,0x420 */ + u8 res4[512]; /* 0x600 */ + struct location error_location[ELM_MAX_CHANNELS]; /* 0x800,0x900 ... */ +}; + +int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, + u32 *error_locations); +int elm_config(enum bch_level level); +void elm_reset(void); +#ifdef ELM_BASE +void elm_init(void); +#else +static inline void elm_init(void) +{ +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_ELM_H */ diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 4d5f2455df3..1a5ed0de31a 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -20,7 +20,8 @@ #include #include #include -#include + +#include "omap_elm.h" #ifndef GPMC_MAX_CS #define GPMC_MAX_CS 4 @@ -1249,6 +1250,15 @@ void board_nand_init(void) struct udevice *dev; int ret; +#ifdef CONFIG_NAND_OMAP_ELM + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(gpmc_elm), &dev); + if (ret && ret != -ENODEV) { + pr_err("%s: Failed to get ELM device: %d\n", __func__, ret); + return; + } +#endif + ret = uclass_get_device_by_driver(UCLASS_MTD, DM_DRIVER_GET(gpmc_nand), &dev); if (ret && ret != -ENODEV) diff --git a/include/linux/mtd/omap_elm.h b/include/linux/mtd/omap_elm.h deleted file mode 100644 index f3db00d55de..00000000000 --- a/include/linux/mtd/omap_elm.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2011 Texas Instruments, - * Mansoor Ahamed - * - * Derived from work done by Rohit Choraria for omap3 - */ -#ifndef __ASM_ARCH_ELM_H -#define __ASM_ARCH_ELM_H -/* - * ELM Module Registers - */ - -/* ELM registers bit fields */ -#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2) -#define ELM_SYSCONFIG_SOFTRESET (0x2) -#define ELM_SYSSTATUS_RESETDONE_MASK (0x1) -#define ELM_SYSSTATUS_RESETDONE (0x1) -#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3) -#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000) -#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16) -#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000) -#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100) -#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F) - -#define ELM_MAX_CHANNELS 8 -#define ELM_MAX_ERROR_COUNT 16 - -#ifndef __ASSEMBLY__ - -enum bch_level { - BCH_4_BIT = 0, - BCH_8_BIT, - BCH_16_BIT -}; - - -/* BCH syndrome registers */ -struct syndrome { - u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */ - u8 res1[36]; /* 0x41c */ -}; - -/* BCH error status & location register */ -struct location { - u32 location_status; /* 0x800 */ - u8 res1[124]; /* 0x804 */ - u32 error_location_x[ELM_MAX_ERROR_COUNT]; /* 0x880, 0x980, .. */ - u8 res2[64]; /* 0x8c0 */ -}; - -/* BCH ELM register map - do not try to allocate memmory for this structure. - * We have used plenty of reserved variables to fill the slots in the ELM - * register memory map. - * Directly initialize the struct pointer to ELM base address. - */ -struct elm { - u32 rev; /* 0x000 */ - u8 res1[12]; /* 0x004 */ - u32 sysconfig; /* 0x010 */ - u32 sysstatus; /* 0x014 */ - u32 irqstatus; /* 0x018 */ - u32 irqenable; /* 0x01c */ - u32 location_config; /* 0x020 */ - u8 res2[92]; /* 0x024 */ - u32 page_ctrl; /* 0x080 */ - u8 res3[892]; /* 0x084 */ - struct syndrome syndrome_fragments[ELM_MAX_CHANNELS]; /* 0x400,0x420 */ - u8 res4[512]; /* 0x600 */ - struct location error_location[ELM_MAX_CHANNELS]; /* 0x800,0x900 ... */ -}; - -int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, - u32 *error_locations); -int elm_config(enum bch_level level); -void elm_reset(void); -void elm_init(void); -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARCH_ELM_H */ -- cgit v1.3.1