From e1df080b0d8b1bf9ed3e6a01a647192b2c90c72a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 17 Sep 2015 17:30:29 +0200 Subject: arm: socfpga: Fix cache configuration By not defining CONFIG_SYS_ARM_CACHE_WRITEALLOC, the WRITEBACK cache policy is selected. This leads to much better performance on the SoCFPGA. A quick network test shows this: Without this patch: => tftp 100000 big-40mb Speed: 1000, full duplex Using dwmac.ff702000 device TFTP from server 192.168.1.54; our IP address is 192.168.1.252 Filename 'big-40mb'. Load address: 0x100000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ########################## 2.5 MiB/s With this patch: => tftp 100000 big-40mb Speed: 1000, full duplex Using dwmac.ff702000 device TFTP from server 192.168.1.54; our IP address is 192.168.1.252 Filename 'big-40mb'. Load address: 0x100000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ########################## 7.6 MiB/s A performance improvement of factor ~3. Signed-off-by: Stefan Roese Cc: Dinh Nguyen Cc: Chin Liang See Cc: Pavel Machek Cc: Marek Vasut --- include/configs/socfpga_common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 38ae763653b..a2811bacd2c 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -73,7 +73,6 @@ /* * Cache */ -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS -- cgit v1.3.1 From 3cbc7b878ba6352bb0ae21213394844f3a9b3e9d Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 22 Sep 2015 17:01:32 -0500 Subject: arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA board config files. Suggested-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/Kconfig | 4 +- include/configs/socfpga_arria5.h | 97 -------------------------------- include/configs/socfpga_arria5_socdk.h | 97 ++++++++++++++++++++++++++++++++ include/configs/socfpga_cyclone5.h | 97 -------------------------------- include/configs/socfpga_cyclone5_socdk.h | 97 ++++++++++++++++++++++++++++++++ 5 files changed, 196 insertions(+), 196 deletions(-) delete mode 100644 include/configs/socfpga_arria5.h create mode 100644 include/configs/socfpga_arria5_socdk.h delete mode 100644 include/configs/socfpga_cyclone5.h create mode 100644 include/configs/socfpga_cyclone5_socdk.h (limited to 'include') diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 089280a91d3..a413ea4d1b4 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -50,8 +50,8 @@ config SYS_SOC default "socfpga" config SYS_CONFIG_NAME - default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK - default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h deleted file mode 100644 index 3193684798c..00000000000 --- a/include/configs/socfpga_arria5.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (C) 2014 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_SOCFPGA_ARRIA5_H__ -#define __CONFIG_SOCFPGA_ARRIA5_H__ - -#include - -/* U-Boot Commands */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_DOS_PARTITION -#define CONFIG_FAT_WRITE -#define CONFIG_HW_WATCHDOG - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DFU -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_GPIO -#define CONFIG_CMD_GREPENV -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB -#define CONFIG_CMD_USB_MASS_STORAGE - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ - -/* Booting Linux */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTFILE "zImage" -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_BOOTCOMMAND "run ramboot" -#else -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" -#endif -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Ethernet on SoC (EMAC) */ -#if defined(CONFIG_CMD_NET) - -/* PHY */ -#define CONFIG_PHY_MICREL -#define CONFIG_PHY_MICREL_KSZ9021 -#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" -#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 -#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" -#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 - -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif -#define CONFIG_G_DNL_MANUFACTURER "Altera" - -/* Extra Environment */ -#define CONFIG_HOSTNAME socfpga_arria5 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=zImage\0" \ - "fdt_addr=100\0" \ - "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${mmcroot} rw rootwait;" \ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:1 ${loadaddr} ${bootimage};" \ - "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */ diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h new file mode 100644 index 00000000000..3193684798c --- /dev/null +++ b/include/configs/socfpga_arria5_socdk.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_SOCFPGA_ARRIA5_H__ +#define __CONFIG_SOCFPGA_ARRIA5_H__ + +#include + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DFU +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_USB_MASS_STORAGE + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_BOOTCOMMAND "run ramboot" +#else +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#endif +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) + +/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 + +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS +#endif +#define CONFIG_G_DNL_MANUFACTURER "Altera" + +/* Extra Environment */ +#define CONFIG_HOSTNAME socfpga_arria5 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h deleted file mode 100644 index 9e733e5c487..00000000000 --- a/include/configs/socfpga_cyclone5.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (C) 2014 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ -#define __CONFIG_SOCFPGA_CYCLONE5_H__ - -#include - -/* U-Boot Commands */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_DOS_PARTITION -#define CONFIG_FAT_WRITE -#define CONFIG_HW_WATCHDOG - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DFU -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_GPIO -#define CONFIG_CMD_GREPENV -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB -#define CONFIG_CMD_USB_MASS_STORAGE - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ - -/* Booting Linux */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTFILE "zImage" -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_BOOTCOMMAND "run ramboot" -#else -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" -#endif -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Ethernet on SoC (EMAC) */ -#if defined(CONFIG_CMD_NET) - -/* PHY */ -#define CONFIG_PHY_MICREL -#define CONFIG_PHY_MICREL_KSZ9021 -#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" -#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 -#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" -#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 - -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif -#define CONFIG_G_DNL_MANUFACTURER "Altera" - -/* Extra Environment */ -#define CONFIG_HOSTNAME socfpga_cyclone5 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=zImage\0" \ - "fdt_addr=100\0" \ - "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${mmcroot} rw rootwait;" \ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:1 ${loadaddr} ${bootimage};" \ - "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */ diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h new file mode 100644 index 00000000000..9e733e5c487 --- /dev/null +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ +#define __CONFIG_SOCFPGA_CYCLONE5_H__ + +#include + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DFU +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_USB_MASS_STORAGE + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_BOOTCOMMAND "run ramboot" +#else +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#endif +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) + +/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 + +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS +#endif +#define CONFIG_G_DNL_MANUFACTURER "Altera" + +/* Extra Environment */ +#define CONFIG_HOSTNAME socfpga_cyclone5 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */ -- cgit v1.3.1 From 68a3e32b722261d07cf7325ea86275bf4e3b8917 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 23 Sep 2015 15:38:01 -0500 Subject: arm: socfpga: Enable saveenv for SD/MMC Enable the able to save the environment variables when SD/MMC is used. Signed-off-by: Dinh Nguyen --- include/configs/socfpga_arria5_socdk.h | 4 ++++ include/configs/socfpga_common.h | 1 - include/configs/socfpga_cyclone5_socdk.h | 4 ++++ include/configs/socfpga_de0_nano_soc.h | 4 ++++ include/configs/socfpga_mcvevk.h | 2 ++ include/configs/socfpga_sockit.h | 4 ++++ 6 files changed, 18 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index 3193684798c..b75b0a27fa9 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -59,6 +59,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a2811bacd2c..cece0950e29 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -281,7 +281,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE -#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE 4096 /* diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 9e733e5c487..fa67b25a792 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -59,6 +59,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index 2508d037e33..191e1f7a43f 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -55,6 +55,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index c5b4b4ca9d3..ed9b5cce6ac 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -43,6 +43,8 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_ENV_IS_NOWHERE + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 747e988ac9f..6c71ef4e23f 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -59,6 +59,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -- cgit v1.3.1 From aad604aef36e90bd42b4ce1969960f3427be4a7a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 24 Sep 2015 09:06:06 +0200 Subject: arm: socfpga: Enable env support on MCV Enable support for env in eMMC on MCV SoM. Signed-off-by: Marek Vasut --- include/configs/socfpga_mcvevk.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index ed9b5cce6ac..65816a05cfc 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -43,7 +43,11 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_ENV_IS_NOWHERE +/* Environment is in MMC */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* USB */ #ifdef CONFIG_CMD_USB -- cgit v1.3.1