From debb7354d1ea4f694154818df5e5b523f5c1cc1d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 26 Apr 2006 17:58:56 -0500 Subject: Initial support for MPC8641 HPCN board. --- include/asm-ppc/immap_86xx.h | 1362 +++++++++++++++++++++++++++++++++++++++++ include/asm-ppc/mmu.h | 15 +- include/asm-ppc/processor.h | 18 +- include/asm-ppc/u-boot.h | 2 +- include/common.h | 11 +- include/configs/MPC8641HPCN.h | 629 +++++++++++++++++++ include/ft_build.h | 4 +- include/mpc86xx.h | 119 ++++ include/pci.h | 6 + 9 files changed, 2160 insertions(+), 6 deletions(-) create mode 100644 include/asm-ppc/immap_86xx.h create mode 100644 include/configs/MPC8641HPCN.h create mode 100644 include/mpc86xx.h (limited to 'include') diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h new file mode 100644 index 00000000000..6bbe072b2df --- /dev/null +++ b/include/asm-ppc/immap_86xx.h @@ -0,0 +1,1362 @@ +/* + * MPC86xx Internal Memory Map + * + * Copyright(c) 2004 Freescale Semiconductor + * Jeff Brown (Jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + */ + +#ifndef __IMMAP_86xx__ +#define __IMMAP_86xx__ + + +/* Local-Access Registers and MCM Registers(0x0000-0x2000) */ +typedef struct ccsr_local_mcm { + uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */ + char res1[4]; + uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */ + char res2[4]; + uint altcar; /* 0x10 - Alternate Configuration Attribute Register */ + char res3[12]; + uint bptr; /* 0x20 - Boot Page Translation Register */ + char res4[3044]; + uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */ + char res5[4]; + uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */ + char res6[20]; + uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */ + char res7[4]; + uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */ + char res8[20]; + uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */ + char res9[4]; + uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */ + char res10[20]; + uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */ + char res11[4]; + uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */ + char res12[20]; + uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */ + char res13[4]; + uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */ + char res14[20]; + uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */ + char res15[4]; + uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */ + char res16[20]; + uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */ + char res17[4]; + uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */ + char res18[20]; + uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ + char res19[4]; + uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ + char res20[16]; + uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ + char res21[4]; + uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ + char res22[20]; + uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ + char res23[4]; + uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ + char res24[720]; + uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */ + char res25[4]; + uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ + char res26[4]; + uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */ + char res27[44]; + uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */ + uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */ + uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */ + uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */ + char res28[16]; + uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */ + uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */ + uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */ + char res29[3476]; + uint edr; /* 0x1e00 - MCM Error Detect Register */ + char res30[4]; + uint eer; /* 0x1e08 - MCM Error Enable Register */ + uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */ + uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */ + uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */ + char res31[488]; +} ccsr_local_mcm_t; + +/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */ + +typedef struct ccsr_ddr { + uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ + char res1[4]; + uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */ + char res2[4]; + uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */ + char res3[4]; + uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */ + char res4[4]; + uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */ + char res5[4]; + uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */ + char res6[84]; + uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */ + uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ + uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ + uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ + uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ + uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ + char res7[104]; + uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ + uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ + uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ + uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ + uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */ + uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ + uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ + uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ + uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ + uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ + uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ + char res8[4]; + uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ + char res9[12]; + uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ + uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ + uint init_addr; /* 0x2148 - DDR training initialzation address */ + uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ + char res10[2728]; + uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ + uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ + char res11[512]; + uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ + uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ + uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */ + char res12[20]; + uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */ + uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */ + uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */ + char res13[20]; + uint err_detect; /* 0x2e40 - DDR Memory Error Detect */ + uint err_disable; /* 0x2e44 - DDR Memory Error Disable */ + uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */ + uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ + uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ + uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ + uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ + char res14[164]; + uint debug_1; /* 0x2f00 */ + uint debug_2; + uint debug_3; + uint debug_4; + uint debug_5; + char res15[236]; +} ccsr_ddr_t; + + +/* Daul I2C Registers(0x3000-0x4000) */ + +typedef struct ccsr_i2c { + u_char i2cadr1; /* 0x3000 - I2C 1 Address Register */ +#define MPC86xx_I2CADR_MASK 0xFE + char res1[3]; + u_char i2cfdr1; /* 0x3004 - I2C 1 Frequency Divider Register */ +#define MPC86xx_I2CFDR_MASK 0x3F + char res2[3]; + u_char i2ccr1; /* 0x3008 - I2C 1 Control Register */ +#define MPC86xx_I2CCR_MEN 0x80 +#define MPC86xx_I2CCR_MIEN 0x40 +#define MPC86xx_I2CCR_MSTA 0x20 +#define MPC86xx_I2CCR_MTX 0x10 +#define MPC86xx_I2CCR_TXAK 0x08 +#define MPC86xx_I2CCR_RSTA 0x04 +#define MPC86xx_I2CCR_BCST 0x01 + char res3[3]; + u_char i2csr1; /* 0x300c - I2C 1 Status Register */ +#define MPC86xx_I2CSR_MCF 0x80 +#define MPC86xx_I2CSR_MAAS 0x40 +#define MPC86xx_I2CSR_MBB 0x20 +#define MPC86xx_I2CSR_MAL 0x10 +#define MPC86xx_I2CSR_BCSTM 0x08 +#define MPC86xx_I2CSR_SRW 0x04 +#define MPC86xx_I2CSR_MIF 0x02 +#define MPC86xx_I2CSR_RXAK 0x01 + char res4[3]; + u_char i2cdr1; /* 0x3010 - I2C 1 Data Register */ +#define MPC86xx_I2CDR_DATA 0xFF + char res5[3]; + u_char i2cdfsrr1; /* 0x3014 - I2C 1 Digital Filtering Sampling Rate Register */ +#define MPC86xx_I2CDFSRR 0x3F + char res6[235]; + + u_char i2cadr2; /* 0x3100 - I2C 2 Address Register */ + char res7[3]; + u_char i2cfdr2; /* 0x3104 - I2C 2 Frequency Divider Register */ + char res8[3]; + u_char i2ccr2; /* 0x3108 - I2C 2 Control Register */ + char res9[3]; + u_char i2csr2; /* 0x310c - I2C 2 Status Register */ + char res10[3]; + u_char i2cdr2; /* 0x3110 - I2C 2 Data Register */ + char res11[3]; + u_char i2cdfsrr2; /* 0x3114 - I2C 2 Digital Filtering Sampling Rate Register */ + char res12[3819]; +} ccsr_i2c_t; + +/* DUART Registers(0x4000-0x5000) */ +typedef struct ccsr_duart { + char res1[1280]; + u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */ + u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */ + u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */ + u_char ulcr1; /* 0x4503 - UART1 Line Control Register */ + u_char umcr1; /* 0x4504 - UART1 Modem Control Register */ + u_char ulsr1; /* 0x4505 - UART1 Line Status Register */ + u_char umsr1; /* 0x4506 - UART1 Modem Status Register */ + u_char uscr1; /* 0x4507 - UART1 Scratch Register */ + char res2[8]; + u_char udsr1; /* 0x4510 - UART1 DMA Status Register */ + char res3[239]; + u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */ + u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */ + u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */ + u_char ulcr2; /* 0x4603 - UART2 Line Control Register */ + u_char umcr2; /* 0x4604 - UART2 Modem Control Register */ + u_char ulsr2; /* 0x4605 - UART2 Line Status Register */ + u_char umsr2; /* 0x4606 - UART2 Modem Status Register */ + u_char uscr2; /* 0x4607 - UART2 Scratch Register */ + char res4[8]; + u_char udsr2; /* 0x4610 - UART2 DMA Status Register */ + char res5[2543]; +} ccsr_duart_t; + + +/* Local Bus Controller Registers(0x5000-0x6000) */ +typedef struct ccsr_lbc { + uint br0; /* 0x5000 - LBC Base Register 0 */ + uint or0; /* 0x5004 - LBC Options Register 0 */ + uint br1; /* 0x5008 - LBC Base Register 1 */ + uint or1; /* 0x500c - LBC Options Register 1 */ + uint br2; /* 0x5010 - LBC Base Register 2 */ + uint or2; /* 0x5014 - LBC Options Register 2 */ + uint br3; /* 0x5018 - LBC Base Register 3 */ + uint or3; /* 0x501c - LBC Options Register 3 */ + uint br4; /* 0x5020 - LBC Base Register 4 */ + uint or4; /* 0x5024 - LBC Options Register 4 */ + uint br5; /* 0x5028 - LBC Base Register 5 */ + uint or5; /* 0x502c - LBC Options Register 5 */ + uint br6; /* 0x5030 - LBC Base Register 6 */ + uint or6; /* 0x5034 - LBC Options Register 6 */ + uint br7; /* 0x5038 - LBC Base Register 7 */ + uint or7; /* 0x503c - LBC Options Register 7 */ + char res1[40]; + uint mar; /* 0x5068 - LBC UPM Address Register */ + char res2[4]; + uint mamr; /* 0x5070 - LBC UPMA Mode Register */ + uint mbmr; /* 0x5074 - LBC UPMB Mode Register */ + uint mcmr; /* 0x5078 - LBC UPMC Mode Register */ + char res3[8]; + uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */ + uint mdr; /* 0x5088 - LBC UPM Data Register */ + char res4[8]; + uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */ + char res5[8]; + uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */ + uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */ + char res6[8]; + uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */ + uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */ + uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */ + uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */ + uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */ + char res7[12]; + uint lbcr; /* 0x50d0 - LBC Configuration Register */ + uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */ + char res8[3880]; +} ccsr_lbc_t; + +/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */ +typedef struct ccsr_pex { + uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */ + uint cfg_data; /* 0x8004 - PEX Configuration Data Register */ + char res1[4]; + uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */ + char res2[16]; + uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */ + uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */ + uint pme_msg_dis; /* 0x802C - PEX PME & message disable register */ + char res3[4]; + uint pm_command; /* 0x8030 - PEX PM Command register */ + char res4[3016]; + uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */ + uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */ + uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */ + uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */ + char res5[8]; + uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */ + char res6[12]; + uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */ + uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */ + uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */ + char res7[4]; + uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */ + char res8[12]; + uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */ + uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */ + uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */ + char res9[4]; + uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */ + char res10[12]; + uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */ + uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */ + uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */ + char res11[4]; + uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */ + char res12[12]; + uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */ + uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */ + uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */ + char res13[4]; + uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */ + char res14[268]; + uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */ + char res15[4]; + uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */ + uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */ + uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */ + char res16[12]; + uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */ + char res17[4]; + uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */ + uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */ + uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */ + char res18[12]; + uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */ + char res19[4]; + uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */ + char res20[4]; + uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */ + char res21[12]; + uint pedr; /* 0x8e00 - PEX Error Detect Register */ + uint pecdr; /* 0x8e04 - PEX Error Capture Disable Register */ + uint peer; /* 0x8e08 - PEX Error Enable Register */ + uint perr_cap0; /* 0x8e0c - PEX Error Capture Register 0 */ + uint perr_cap1; /* 0x8e10 - PEX Error Capture Register 1 */ + uint perr_cap2; /* 0x8e14 - PEX Error Capture Register 2 */ + uint perr_cap3; /* 0x8e18 - PEX Error Capture Register 3 */ + char res22[100]; + uint perr_stat; /* 0x8e80 - PEX Error Status Register */ + char res23[124]; + uint pdebug; /* 0x8f00 - PEX Debug Register */ + char res24[248]; //Sri: changed this because of adding 4 bytes before 0x?8020. +} ccsr_pex_t; + +/* Hyper Transport Register Block (0xA000-0xB000) */ +typedef struct ccsr_ht { + uint hcfg_addr; /* 0xa000 - HT Configuration Address register */ + uint hcfg_data; /* 0xa004 - HT Configuration Data register */ + char res1[3064]; + uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */ + char res2[12]; + uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */ + char res3[12]; + uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */ + char res4[4]; + uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */ + char res5[4]; + uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */ + char res6[12]; + uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */ + char res7[4]; + uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */ + char res8[4]; + uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */ + char res9[12]; + uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */ + char res10[4]; + uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */ + char res11[4]; + uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */ + char res12[12]; + uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */ + char res13[4]; + uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */ + char res14[4]; + uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */ + char res15[236]; + uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */ + char res16[4]; + uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */ + char res17[4]; + uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */ + char res18[12]; + uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */ + char res19[4]; + uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */ + char res20[4]; + uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */ + char res21[12]; + uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */ + char res22[4]; + uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */ + char res23[4]; + uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */ + char res24[12]; + uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */ + char res25[4]; + uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */ + char res26[4]; + uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */ + char res27[12]; + uint hedr; /* 0xae00 - HT Error Detect register */ + char res28[4]; + uint heier; /* 0xae08 - HT Error Interrupt Enable register */ + char res29[4]; + uint hecdr; /* 0xae10 - HT Error Capture Disbale register */ + char res30[12]; + uint hecsr; /* 0xae20 - HT Error Capture Status register */ + char res31[4]; + uint hec0; /* 0xae28 - HT Error Capture 0 register */ + uint hec1; /* 0xae2c - HT Error Capture 1 register */ + uint hec2; /* 0xae30 - HT Error Capture 2 register */ + char res32[460]; +} ccsr_ht_t; + +/* DMA Registers(0x2_1000-0x2_2000) */ +typedef struct ccsr_dma { + char res1[256]; + uint mr0; /* 0x21100 - DMA 0 Mode Register */ + uint sr0; /* 0x21104 - DMA 0 Status Register */ + char res2[4]; + uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */ + uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */ + uint sar0; /* 0x21114 - DMA 0 Source Address Register */ + uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */ + uint dar0; /* 0x2111c - DMA 0 Destination Address Register */ + uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */ + char res3[4]; + uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */ + char res4[8]; + uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */ + char res5[4]; + uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */ + uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */ + uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */ + char res6[56]; + uint mr1; /* 0x21180 - DMA 1 Mode Register */ + uint sr1; /* 0x21184 - DMA 1 Status Register */ + char res7[4]; + uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */ + uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */ + uint sar1; /* 0x21194 - DMA 1 Source Address Register */ + uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */ + uint dar1; /* 0x2119c - DMA 1 Destination Address Register */ + uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */ + char res8[4]; + uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */ + char res9[8]; + uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */ + char res10[4]; + uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */ + uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */ + uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */ + char res11[56]; + uint mr2; /* 0x21200 - DMA 2 Mode Register */ + uint sr2; /* 0x21204 - DMA 2 Status Register */ + char res12[4]; + uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */ + uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */ + uint sar2; /* 0x21214 - DMA 2 Source Address Register */ + uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */ + uint dar2; /* 0x2121c - DMA 2 Destination Address Register */ + uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */ + char res13[4]; + uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */ + char res14[8]; + uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */ + char res15[4]; + uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */ + uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */ + uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */ + char res16[56]; + uint mr3; /* 0x21280 - DMA 3 Mode Register */ + uint sr3; /* 0x21284 - DMA 3 Status Register */ + char res17[4]; + uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */ + uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */ + uint sar3; /* 0x21294 - DMA 3 Source Address Register */ + uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */ + uint dar3; /* 0x2129c - DMA 3 Destination Address Register */ + uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */ + char res18[4]; + uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */ + char res19[8]; + uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */ + char res20[4]; + uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */ + uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */ + uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */ + char res21[56]; + uint dgsr; /* 0x21300 - DMA General Status Register */ + char res22[3324]; +} ccsr_dma_t; + +/* tsec1-4: 24000-28000 */ +typedef struct ccsr_tsec { + uint id; /* 0x24000 - Controller ID Register */ + char res1[12]; + uint ievent; /* 0x24010 - Interrupt Event Register */ + uint imask; /* 0x24014 - Interrupt Mask Register */ + uint edis; /* 0x24018 - Error Disabled Register */ + char res2[4]; + uint ecntrl; /* 0x24020 - Ethernet Control Register */ + char res2_1[4]; + uint ptv; /* 0x24028 - Pause Time Value Register */ + uint dmactrl; /* 0x2402c - DMA Control Register */ + uint tbipa; /* 0x24030 - TBI PHY Address Register */ + char res3[88]; + uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */ + char res4[8]; + uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */ + uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */ + char res4_1[4]; + uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */ + uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */ + char res5[84]; + uint tctrl; /* 0x24100 - Transmit Control Register */ + uint tstat; /* 0x24104 - Transmit Status Register */ + uint dfvlan; /* 0x24108 - Default VLAN control word */ + char res6[4]; + uint txic; /* 0x24110 - Transmit interrupt coalescing Register */ + uint tqueue; /* 0x24114 - Transmit Queue Control Register */ + char res7[40]; + uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */ + uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */ + char res8[52]; + uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */ + char res9[4]; + uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */ + char res10[4]; + uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */ + char res11[4]; + uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */ + char res12[4]; + uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */ + char res13[4]; + uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */ + char res14[4]; + uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */ + char res15[4]; + uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */ + char res16[4]; + uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */ + char res17[64]; + uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */ + uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */ + char res18[4]; + uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */ + char res19[4]; + uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */ + char res20[4]; + uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */ + char res21[4]; + uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */ + char res22[4]; + uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */ + char res23[4]; + uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */ + char res24[4]; + uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */ + char res25[192]; + uint rctrl; /* 0x24300 - Receive Control Register */ + uint rstat; /* 0x24304 - Receive Status Register */ + char res26[8]; + uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */ + uint rqueue; /* 0x24314 - Receive queue control register */ + char res27[24]; + uint rbifx; /* 0x24330 - Receive bit field extract control Register */ + uint rqfar; /* 0x24334 - Receive queue filing table address Register */ + uint rqfcr; /* 0x24338 - Receive queue filing table control Register */ + uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ + uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ + char res28[56]; + uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */ + char res29[4]; + uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */ + char res30[4]; + uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */ + char res31[4]; + uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */ + char res32[4]; + uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */ + char res33[4]; + uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */ + char res34[4]; + uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */ + char res35[4]; + uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */ + char res36[4]; + uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */ + char res37[64]; + uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */ + uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */ + char res38[4]; + uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */ + char res39[4]; + uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */ + char res40[4]; + uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */ + char res41[4]; + uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */ + char res42[4]; + uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */ + char res43[4]; + uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */ + char res44[4]; + uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */ + char res45[192]; + uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */ + uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */ + uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */ + uint hafdup; /* 0x2450c - Half Duplex Register */ + uint maxfrm; /* 0x24510 - Maximum Frame Length Register */ + char res46[12]; + uint miimcfg; /* 0x24520 - MII Management Configuration Register */ + uint miimcom; /* 0x24524 - MII Management Command Register */ + uint miimadd; /* 0x24528 - MII Management Address Register */ + uint miimcon; /* 0x2452c - MII Management Control Register */ + uint miimstat; /* 0x24530 - MII Management Status Register */ + uint miimind; /* 0x24534 - MII Management Indicator Register */ + uint ifctrl; /* 0x24538 - Interface Contrl Register */ + uint ifstat; /* 0x2453c - Interface Status Register */ + uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */ + uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */ + uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */ + uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */ + uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */ + uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */ + uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */ + uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */ + uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */ + uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */ + uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */ + uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */ + uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */ + uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */ + uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */ + uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */ + uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */ + uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */ + uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */ + uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */ + uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */ + uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */ + uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */ + uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */ + uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */ + uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */ + uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */ + uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */ + uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */ + uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */ + uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */ + uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */ + char res48[192]; + uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */ + uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */ + uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */ + uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */ + uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */ + uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */ + uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ + uint rbyt; /* 0x2469c - Receive Byte Counter */ + uint rpkt; /* 0x246a0 - Receive Packet Counter */ + uint rfcs; /* 0x246a4 - Receive FCS Error Counter */ + uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */ + uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */ + uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */ + uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */ + uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */ + uint raln; /* 0x246bc - Receive Alignment Error Counter */ + uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */ + uint rcde; /* 0x246c4 - Receive Code Error Counter */ + uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */ + uint rund; /* 0x246cc - Receive Undersize Packet Counter */ + uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */ + uint rfrg; /* 0x246d4 - Receive Fragments Counter */ + uint rjbr; /* 0x246d8 - Receive Jabber Counter */ + uint rdrp; /* 0x246dc - Receive Drop Counter */ + uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */ + uint tpkt; /* 0x246e4 - Transmit Packet Counter */ + uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */ + uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */ + uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */ + uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */ + uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */ + uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */ + uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */ + uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */ + uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */ + uint tncl; /* 0x2470c - Transmit Total Collision Counter */ + char res49[4]; + uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */ + uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */ + uint tfcs; /* 0x2471c - Transmit FCS Error Counter */ + uint txcf; /* 0x24720 - Transmit Control Frame Counter */ + uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */ + uint tund; /* 0x24728 - Transmit Undersize Frame Counter */ + uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */ + uint car1; /* 0x24730 - Carry Register One */ + uint car2; /* 0x24734 - Carry Register Two */ + uint cam1; /* 0x24738 - Carry Mask Register One */ + uint cam2; /* 0x2473c - Carry Mask Register Two */ + uint rrej; /* 0x24740 - Receive filer rejected packet counter */ + char res50[188]; + uint iaddr0; /* 0x24800 - Indivdual address register 0 */ + uint iaddr1; /* 0x24804 - Indivdual address register 1 */ + uint iaddr2; /* 0x24808 - Indivdual address register 2 */ + uint iaddr3; /* 0x2480c - Indivdual address register 3 */ + uint iaddr4; /* 0x24810 - Indivdual address register 4 */ + uint iaddr5; /* 0x24814 - Indivdual address register 5 */ + uint iaddr6; /* 0x24818 - Indivdual address register 6 */ + uint iaddr7; /* 0x2481c - Indivdual address register 7 */ + char res51[96]; + uint gaddr0; /* 0x24880 - Global address register 0 */ + uint gaddr1; /* 0x24884 - Global address register 1 */ + uint gaddr2; /* 0x24888 - Global address register 2 */ + uint gaddr3; /* 0x2488c - Global address register 3 */ + uint gaddr4; /* 0x24890 - Global address register 4 */ + uint gaddr5; /* 0x24894 - Global address register 5 */ + uint gaddr6; /* 0x24898 - Global address register 6 */ + uint gaddr7; /* 0x2489c - Global address register 7 */ + char res52[352]; + uint fifocfg; /* 0x24A00 - FIFO interface configuration register */ + char res53[500]; + uint attr; /* 0x24BF8 - DMA Attribute register */ + uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */ + char res54[1024]; +} ccsr_tsec_t; + +/* PIC Registers(0x4_0000-0x6_1000) */ + +typedef struct ccsr_pic { + char res1[64]; + uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ + char res2[12]; + uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ + char res3[12]; + uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */ + char res4[12]; + uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */ + char res5[12]; + uint ctpr; /* 0x40080 - Current Task Priority Register */ + char res6[12]; + uint whoami; /* 0x40090 - Who Am I Register */ + char res7[12]; + uint iack; /* 0x400a0 - Interrupt Acknowledge Register */ + char res8[12]; + uint eoi; /* 0x400b0 - End Of Interrupt Register */ + char res9[3916]; + uint frr; /* 0x41000 - Feature Reporting Register */ + char res10[28]; + uint gcr; /* 0x41020 - Global Configuration Register */ + char res11[92]; + uint vir; /* 0x41080 - Vendor Identification Register */ + char res12[12]; + uint pir; /* 0x41090 - Processor Initialization Register */ + char res13[12]; + uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */ + char res14[12]; + uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */ + char res15[12]; + uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */ + char res16[12]; + uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */ + char res17[12]; + uint svr; /* 0x410e0 - Spurious Vector Register */ + char res18[12]; + uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */ + char res19[12]; + uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */ + char res20[12]; + uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */ + char res21[12]; + uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */ + char res22[12]; + uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */ + char res23[12]; + uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */ + char res24[12]; + uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */ + char res25[12]; + uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */ + char res26[12]; + uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */ + char res27[12]; + uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */ + char res28[12]; + uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */ + char res29[12]; + uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */ + char res30[12]; + uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */ + char res31[12]; + uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */ + char res32[12]; + uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */ + char res33[12]; + uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */ + char res34[12]; + uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */ + char res35[268]; + uint tcr; /* 0x41300 - Timer Control Register */ + char res36[12]; + uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */ + char res37[12]; + uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */ + char res38[12]; + uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */ + char res39[12]; + uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */ + char res40[12]; + uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */ + char res41[12]; + uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */ + char res42[12]; + uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */ + char res43[12]; + uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */ + char res44[12]; + uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */ + char res45[12]; + uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */ + char res46[12]; + uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */ + char res47[12]; + uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */ + char res48[60]; + uint msgr0; /* 0x41400 - Message Register 0 */ + char res49[12]; + uint msgr1; /* 0x41410 - Message Register 1 */ + char res50[12]; + uint msgr2; /* 0x41420 - Message Register 2 */ + char res51[12]; + uint msgr3; /* 0x41430 - Message Register 3 */ + char res52[204]; + uint mer; /* 0x41500 - Message Enable Register */ + char res53[12]; + uint msr; /* 0x41510 - Message Status Register */ + char res54[60140]; + uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */ + char res55[12]; + uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */ + char res56[12]; + uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */ + char res57[12]; + uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */ + char res58[12]; + uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */ + char res59[12]; + uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */ + char res60[12]; + uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */ + char res61[12]; + uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */ + char res62[12]; + uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */ + char res63[12]; + uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */ + char res64[12]; + uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */ + char res65[12]; + uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */ + char res66[12]; + uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */ + char res67[12]; + uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */ + char res68[12]; + uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */ + char res69[12]; + uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */ + char res70[12]; + uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */ + char res71[12]; + uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */ + char res72[12]; + uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */ + char res73[12]; + uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */ + char res74[12]; + uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */ + char res75[12]; + uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */ + char res76[12]; + uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */ + char res77[12]; + uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */ + char res78[140]; + uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */ + char res79[12]; + uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */ + char res80[12]; + uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */ + char res81[12]; + uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */ + char res82[12]; + uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */ + char res83[12]; + uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */ + char res84[12]; + uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */ + char res85[12]; + uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */ + char res86[12]; + uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */ + char res87[12]; + uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */ + char res88[12]; + uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */ + char res89[12]; + uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */ + char res90[12]; + uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */ + char res91[12]; + uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */ + char res92[12]; + uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */ + char res93[12]; + uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */ + char res94[12]; + uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */ + char res95[12]; + uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */ + char res96[12]; + uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */ + char res97[12]; + uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */ + char res98[12]; + uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */ + char res99[12]; + uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */ + char res100[12]; + uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */ + char res101[12]; + uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */ + char res102[12]; + uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */ + char res103[12]; + uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */ + char res104[12]; + uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */ + char res105[12]; + uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */ + char res106[12]; + uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */ + char res107[12]; + uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */ + char res108[12]; + uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */ + char res109[12]; + uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */ + char res110[12]; + uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */ + char res111[12]; + uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */ + char res112[12]; + uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */ + char res113[12]; + uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */ + char res114[12]; + uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */ + char res115[12]; + uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */ + char res116[12]; + uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */ + char res117[12]; + uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */ + char res118[12]; + uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */ + char res119[12]; + uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */ + char res120[12]; + uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */ + char res121[12]; + uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */ + char res122[12]; + uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */ + char res123[12]; + uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */ + char res124[12]; + uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */ + char res125[12]; + uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */ + char res126[12]; + uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */ + char res127[12]; + uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */ + char res128[12]; + uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */ + char res129[12]; + uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */ + char res130[12]; + uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */ + char res131[12]; + uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */ + char res132[12]; + uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */ + char res133[12]; + uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */ + char res134[12]; + uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */ + char res135[12]; + uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */ + char res136[12]; + uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */ + char res137[12]; + uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */ + char res138[12]; + uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */ + char res139[12]; + uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */ + char res140[12]; + uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */ + char res141[12]; + uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */ + char res142[4108]; + uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */ + char res143[12]; + uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */ + char res144[12]; + uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */ + char res145[12]; + uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */ + char res146[12]; + uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */ + char res147[12]; + uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */ + char res148[12]; + uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */ + char res149[12]; + uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */ + char res150[59852]; + uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */ + char res151[12]; + uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */ + char res152[12]; + uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */ + char res153[12]; + uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */ + char res154[12]; + uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */ + char res155[12]; + uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */ + char res156[12]; + uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */ + char res157[12]; + uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */ + char res158[3916]; +} ccsr_pic_t; + +/* RapidIO Registers(0xc_0000-0xe_0000) */ + +typedef struct ccsr_rio { + uint didcar; /* 0xc0000 - Device Identity Capability Register */ + uint dicar; /* 0xc0004 - Device Information Capability Register */ + uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ + uint aicar; /* 0xc000c - Assembly Information Capability Register */ + uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ + uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ + uint socar; /* 0xc0018 - Source Operations Capability Register */ + uint docar; /* 0xc001c - Destination Operations Capability Register */ + char res1[32]; + uint msr; /* 0xc0040 - Mailbox Command And Status Register */ + uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ + char res2[4]; + uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ + char res3[12]; + uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ + uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ + char res4[4]; + uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ + uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ + char res5[144]; + uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ + char res6[28]; + uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ + uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ + char res7[20]; + uint pgccsr; /* 0xc013c - Port General Command and Status Register */ + uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ + uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ + uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ + char res8[12]; + uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ + uint pccsr; /* 0xc015c - Port Control Command and Status Register */ + char res9[1184]; + uint erbh; /* 0xc0600 - Error Reporting Block Header Register */ + char res10[4]; + uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */ + uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */ + char res11[4]; + uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */ + uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */ + uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */ + char res12[32]; + uint edcsr; /* 0xc0640 - Port 0 error detect status register */ + uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */ + uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */ + uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */ + uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */ + uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ + uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */ + char res13[12]; + uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */ + uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/ + char res14[63892]; + uint llcr; /* 0xd0004 - Logical Layer Configuration Register */ + char res15[12]; + uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */ + char res16[12]; + uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */ + char res17[92]; + uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */ + char res18[124]; + uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */ + char res19[28]; + uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */ + char res20[12]; + uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */ + char res21[12]; + uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */ + char res22[20]; + uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */ + char res23[4]; + uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ + char res24[2716]; + uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ + uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */ + char res25[8]; + uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ + char res26[12]; + uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ + uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */ + uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ + char res27[4]; + uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ + uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */ + uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */ + uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */ + uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ + uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */ + uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ + char res28[4]; + uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ + uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */ + uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */ + uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */ + uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ + uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */ + uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ + char res29[4]; + uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ + uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */ + uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */ + uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */ + uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ + uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */ + uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ + char res30[4]; + uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ + uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */ + uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */ + uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */ + uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ + uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */ + uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ + char res31[4]; + uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ + uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */ + uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */ + uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */ + uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ + uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */ + uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ + char res32[4]; + uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ + uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */ + uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */ + uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */ + uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ + uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */ + uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ + char res33[4]; + uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ + uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */ + uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */ + uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */ + uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ + uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */ + uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ + char res34[4]; + uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ + uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */ + uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */ + uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */ + char res35[64]; + uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ + uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ + char res36[4]; + uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ + char res37[12]; + uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ + char res38[4]; + uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ + char res39[4]; + uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ + char res40[12]; + uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ + char res41[4]; + uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ + char res42[4]; + uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ + char res43[12]; + uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ + char res44[4]; + uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ + char res45[4]; + uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ + char res46[12]; + uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ + char res47[12]; + uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ + char res48[12]; + uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ + uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ + uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ + uint pecr; /* 0xd0e0c - Port Error Control Register */ + uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ + uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ + uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ + char res49[4]; + uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ + char res50[4]; + uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ + uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ + char res51[8656]; + uint omr; /* 0xd3000 - Outbound Mode Register */ + uint osr; /* 0xd3004 - Outbound Status Register */ + uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ + uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */ + uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */ + uint osar; /* 0xd3014 - Outbound Unit Source Address Register */ + uint odpr; /* 0xd3018 - Outbound Destination Port Register */ + uint odatr; /* 0xd301c - Outbound Destination Attributes Register */ + uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */ + uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ + uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */ + uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */ + uint omgr; /* 0xd3030 - Outbound Multicast Group Register */ + uint omlr; /* 0xd3034 - Outbound Multicast List Register */ + char res52[40]; + uint imr; /* 0xd3060 - Outbound Mode Register */ + uint isr; /* 0xd3064 - Inbound Status Register */ + uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ + uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */ + uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */ + uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */ + uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */ + char res53[900]; + uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */ + uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */ + char res54[16]; + uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */ + uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */ + char res55[12]; + uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */ + char res56[48]; + uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */ + uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */ + uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */ + uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */ + uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */ + uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */ + uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ + char res57[100]; + uint pwmr; /* 0xd34e0 - Port-Write Mode Register */ + uint pwsr; /* 0xd34e4 - Port-Write Status Register */ + uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */ + uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */ + char res58[51984]; +} ccsr_rio_t; + +/* Global Utilities Register Block(0xe_0000-0xf_ffff) */ +typedef struct ccsr_gur { + uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ + uint porbmsr; /* 0xe0004 - POR boot mode status register */ +#define MPC86xx_PORBMSR_HA 0x00060000 + uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ + uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ +#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000 + uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ + char res1[12]; + uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ + char res2[12]; + uint gpiocr; /* 0xe0030 - GPIO control register */ + char res3[12]; + uint gpoutdr; /* 0xe0040 - General-purpose output data register */ + char res4[12]; + uint gpindr; /* 0xe0050 - General-purpose input data register */ + char res5[12]; + uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ + char res6[12]; + uint devdisr; /* 0xe0070 - Device disable control */ +#define MPC86xx_DEVDISR_PCIEX1 0x80000000 +#define MPC86xx_DEVDISR_PCIEX2 0x40000000 + char res7[12]; + uint powmgtcsr; /* 0xe0080 - Power management status and control register */ + char res8[12]; + uint mcpsumr; /* 0xe0090 - Machine check summary register */ + char res9[12]; + uint pvr; /* 0xe00a0 - Processor version register */ + uint svr; /* 0xe00a4 - System version register */ + char res10[3416]; + uint clkocr; /* 0xe0e00 - Clock out select register */ + char res11[12]; + uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ + char res12[12]; + uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ + int res13[57]; + uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ + int res14[6]; + uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ + char res15[61656]; +} ccsr_gur_t; + +typedef struct immap { + ccsr_local_mcm_t im_local_mcm; + ccsr_ddr_t im_ddr1; + ccsr_i2c_t im_i2c; + ccsr_duart_t im_duart; + ccsr_lbc_t im_lbc; + ccsr_ddr_t im_ddr2; + char res1[4096]; + ccsr_pex_t im_pex1; + ccsr_pex_t im_pex2; + ccsr_ht_t im_ht; + char res2[90112]; + ccsr_dma_t im_dma; + char res3[8192]; + ccsr_tsec_t im_tsec1; + ccsr_tsec_t im_tsec2; + ccsr_tsec_t im_tsec3; + ccsr_tsec_t im_tsec4; + char res4[98304]; + ccsr_pic_t im_pic; + char res5[389120]; + ccsr_rio_t im_rio; + ccsr_gur_t im_gur; +} immap_t; + +extern immap_t *immr; + +#endif /*__IMMAP_86xx__*/ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 2606b79a249..612b5df4873 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -434,19 +434,28 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_1GB 10 #define BOOKE_PAGESZ_4GB 11 +#if defined(CONFIG_MPC86xx) +#define LAWBAR_BASE_ADDR 0x00FFFFFF +#define LAWAR_TRGT_IF 0x01F00000 +#else #define LAWBAR_BASE_ADDR 0x000FFFFF -#define LAWAR_EN 0x80000000 #define LAWAR_TRGT_IF 0x00F00000 +#endif +#define LAWAR_EN 0x80000000 #define LAWAR_SIZE 0x0000003F #define LAWAR_TRGT_IF_PCI 0x00000000 #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 +#define LAWAR_TRGT_IF_HT 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 +#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 #define LAWAR_TRGT_IF_RIO 0x00c00000 #define LAWAR_TRGT_IF_DDR 0x00f00000 +#define LAWAR_TRGT_IF_DDR1 0x00f00000 +#define LAWAR_TRGT_IF_DDR2 0x01600000 #define LAWAR_SIZE_BASE 0xa #define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) @@ -469,5 +478,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) #define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) #define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) +#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) +#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) +#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) +#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) #endif /* _PPC_MMU_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 811378383df..1848aaf8cdc 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -264,6 +264,7 @@ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MBAR 0x137 /* System memory base address */ @@ -443,6 +444,11 @@ #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ #define ESR_ST 0x00800000 /* Store Operation */ +#if defined(CONFIG_MPC86xx) +#define SPRN_MSSCRO 0x3f6 +#endif + + /* Short-hand versions for a number of the above SPRNs */ #define CTR SPRN_CTR /* Counter Register */ @@ -501,10 +507,14 @@ #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ +#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ -#if defined(CONFIG_E500) +#if defined(CONFIG_MPC86xx) +#define MSSCR0 SPRN_MSSCRO +#endif +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define PIR SPRN_PIR #endif #define SVR SPRN_SVR /* System-On-Chip Version Register */ @@ -538,7 +548,7 @@ #define CSRR0 SPRN_CSRR0 #define CSRR1 SPRN_CSRR1 #define IVPR SPRN_IVPR -#define USPRG0 SPRN_USPRG0 +#define USPRG0 SPRN_USPRG #define SPRG4R SPRN_SPRG4R #define SPRG5R SPRN_SPRG5R #define SPRG6R SPRN_SPRG6R @@ -755,6 +765,8 @@ #define PVR_85xx_REV1 (PVR_85xx | 0x0010) #define PVR_85xx_REV2 (PVR_85xx | 0x0020) +#define PVR_86xx 0x80040000 +#define PVR_86xx_REV1 (PVR_86xx | 0x0010) /* * For the 8xx processors, all of them report the same PVR family for @@ -808,6 +820,8 @@ #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 +#define SVR_8641 0x8090 +#define SVR_8641D 0x8091 /* I am just adding a single entry for 8260 boards. I think we may be * able to combine mbx, fads, rpxlite, bseip, and classic into a single diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index f7aa55f3343..f335cd856aa 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -45,7 +45,7 @@ typedef struct bd_info { unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ #if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ - || defined(CONFIG_E500) + || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif #if defined(CONFIG_MPC5xxx) diff --git a/include/common.h b/include/common.h index 5d8b15628b5..83ccf7c9877 100644 --- a/include/common.h +++ b/include/common.h @@ -79,6 +79,10 @@ typedef volatile unsigned char vu_char; #endif #include #endif +#ifdef CONFIG_MPC86xx +#include +#include +#endif #ifdef CONFIG_MPC85xx #include #include @@ -366,6 +370,7 @@ void trap_init (ulong); defined (CONFIG_74xx) || \ defined (CONFIG_MPC8220) || \ defined (CONFIG_MPC85xx) || \ + defined (CONFIG_MPC86xx) || \ defined (CONFIG_MPC83XX) unsigned char in8(unsigned int); void out8(unsigned int, unsigned char); @@ -454,6 +459,10 @@ ulong get_bus_freq (ulong); typedef MPC85xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); #endif +#if defined(CONFIG_MPC86xx) +typedef MPC86xx_SYS_INFO sys_info_t; +void get_sys_info ( sys_info_t * ); +#endif #if defined(CONFIG_4xx) || defined(CONFIG_IOP480) # if defined(CONFIG_440) @@ -468,7 +477,7 @@ void get_sys_info ( sys_info_t * ); #if defined(CONFIG_8xx) || defined(CONFIG_8260) void cpu_init_f (volatile immap_t *immr); #endif -#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx) void cpu_init_f (void); #endif diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h new file mode 100644 index 00000000000..8d2e08851e4 --- /dev/null +++ b/include/configs/MPC8641HPCN.h @@ -0,0 +1,629 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8641hpc3 board configuration file + * + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_MPC86xx 1 /* MPC86xx */ +#define CONFIG_MPC8641 1 /* MPC8641 specific */ +#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ +#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ +#undef DEBUG + +//#define RUN_DIAG 1 +#ifdef RUN_DIAG +#define CFG_DIAG_ADDR 0xff800000 +#endif +#define CFG_RESET_ADDRESS 0xfff00100 + +//#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +/*#define CONFIG_DDR_ECC */ /* only for ECC DDR module */ +/*#define CONFIG_DDR_DLL */ /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + + +#define CONFIG_ALTIVEC 1 +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + */ + +#define CFG_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +#ifndef CONFIG_SYS_CLK_FREQ +//#define CONFIG_SYS_CLK_FREQ 33000000 +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +/* JB - XXX - Are these available on 86xx? */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define MPC86xx_DDR_SDRAM_CLK_CNTL + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +#else + /* + * Manually set up DDR parameters + */ + +/* DDR I */ +#if 1 + #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ + + #define CFG_DDR_CS0_BNDS 0x0000000F + #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ + #define CFG_DDR_EXT_REFRESH 0x00000000 + #define CFG_DDR_TIMING_0 0x00260802 + #define CFG_DDR_TIMING_1 0x39357322 + #define CFG_DDR_TIMING_2 0x14904cc8 + #define CFG_DDR_MODE_1 0x00480432 + #define CFG_DDR_MODE_2 0x00000000 + #define CFG_DDR_INTERVAL 0x06090100 + #define CFG_DDR_DATA_INIT 0xdeadbeef + #define CFG_DDR_CLK_CTRL 0x03800000 + #define CFG_DDR_OCD_CTRL 0x00000000 + #define CFG_DDR_OCD_STATUS 0x00000000 + #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ + #define CFG_DDR_CONTROL2 0x04400000 + + //Not used in fixed_sdram function + + #define CFG_DDR_MODE 0x00000022 + #define CFG_DDR_CS1_BNDS 0x00000000 + #define CFG_DDR_CS2_BNDS 0x00000FFF //Not done + #define CFG_DDR_CS3_BNDS 0x00000FFF //Not done + #define CFG_DDR_CS4_BNDS 0x00000FFF //Not done + #define CFG_DDR_CS5_BNDS 0x00000FFF //Not done + + + +#endif +#endif + + +/* + * SDRAM on the Local Bus + */ +//#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +//#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 + * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff + * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. + * However, when u-boot comes up, the flash_init needs hard start addresses + * to build its info table. For user convenience, we have the flash addresses + * as fe800000 and ff800000. That way, when we do flash operations, u-boot + * knows where the flash is and the user can download u-boot code from promjet to + * fef00000 <- more intuitive than fe700000. Note that, on switching the boot + * location, fef00000 becomes fff00000. +*/ +#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ +#define CFG_FLASH_BASE2 0xff800000 + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} + + +/*Sri: This looks like a good place to init all the Local Bus chip selects*/ + +#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ +#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ + +#define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ +#define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ + +#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ +#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ + +#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ +#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ + +#define PIXIS_BASE 0xf8100000 /* PIXIS registers*/ +#define PIXIS_ID 0x0 /* MPC8641HPCN Board ID at offset 0*/ +#define PIXIS_VER 0x1 /* MPC8641HPCN board version version at offset 1*/ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2*/ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register*/ +#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ + + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +//#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +/*#define CFG_HPCN_FLASH_CFI_DRIVER */ +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#if !defined(CFG_RAMBOOT) +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +#define CONFIG_L1_INIT_RAM +#undef CFG_INIT_RAM_LOCK +#ifndef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ +#else +#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ +#endif +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8641@0" +#define OF_SOC "soc8641@f8000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/* RapidIO MMU */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +//#define CFG_PCI1_MEM_BASE 0xd0000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +//#define CFG_PCI1_IO_BASE 0xe0000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +//#define CFG_PCI1_IO_BUS 0x00000000 +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +/* For RTL8139 */ +#define _IO_BASE 0x00000000 + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ + +// #define CFG_PCI1_MEM_BASE 0x80000000 +// #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +// #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +// #define CFG_PCI1_IO_BASE 0xe2000000 +// #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +// #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + + + +#if defined(CONFIG_PCI) + + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +//#define CFG_SCSI_SCAN_BUS_REVERSE + + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_RTL8139 + + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +//#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ + +#define CONFIG_MPC86XX_TSEC1 1 +#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" +#define CONFIG_MPC86XX_TSEC2 1 +#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" +#define CONFIG_MPC86XX_TSEC3 1 +#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" +#define CONFIG_MPC86XX_TSEC4 1 +#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" + + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 +#define TSEC4_PHY_ADDR 3 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#endif /* CONFIG_TSEC_ENET */ + + +/* BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +//#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (0x0 | BATU_BL_512M | BATU_VS | BATU_VP) +//#define CFG_IBAT0L CFG_DBAT0L +//#define CFG_IBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT0L (0x0| BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) +#define CFG_IBAT0U CFG_DBAT0U + +/* BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 512M PCI-Express 1 Memory + * 0xa000_0000 512M PCI-Express 2 Memory + ** SS - Changed it for operating from 0xd0000000 + */ +#define CFG_DBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT1U CFG_DBAT1U + +/* BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M RapidIO Memory + */ +#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT2U CFG_DBAT2U + +/* BAT3 4M Cache-inhibited, guarded + * 0xf800_0000 4M CCSR + */ +#define CFG_DBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U CFG_DBAT3U + +/* BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + ** SS - Note that this is at 0xe0000000 + */ +#define CFG_DBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT4U CFG_DBAT4U + +/* BAT5 128K Cacheable, non-guarded + * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_IBAT5L CFG_DBAT5L +#define CFG_IBAT5U CFG_DBAT5U + +/* BAT6 32M Cache-inhibited, guarded + * 0xfe00_0000 32M FLASH + */ +#define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT6U CFG_DBAT6U + + +#define CFG_DBAT7L 0x00000000 +#define CFG_DBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 +#define CFG_IBAT7U 0x00000000 + + + + +/* + * Environment + */ + #ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 + #else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 + #endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_IMLS \ + | CFG_CMD_FLASH \ + | CFG_CMD_LOADS)) + #else + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_IMLS \ + | CFG_CMD_FLASH \ + | CFG_CMD_LOADS)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #else + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:01 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD +#endif + +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 +#define CONFIG_HAS_ETH3 1 + +#define CONFIG_IPADDR 10.82.193.138 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage + +#define CONFIG_SERVERIP 10.82.193.104 +#define CONFIG_GATEWAYIP 10.82.193.254 +#define CONFIG_NETMASK 255.255.252.0 + +#define CONFIG_LOADADDR 1000000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0" \ + "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ + "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ + "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ + "pex=run pexstat; run pex1; run pexd\0" \ + "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ + "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ + "maxcpus=2" + + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/ft_build.h b/include/ft_build.h index 47ca575d9fe..5c5e06309bc 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -58,7 +58,9 @@ void ft_begin(struct ft_cxt *cxt, void *blob, int max_size); void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size); void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end); - +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup(void *blob, bd_t *bd); +#endif void ft_dump_blob(const void *bphp); void ft_merge_blob(struct ft_cxt *cxt, void *blob); void *ft_get_prop(void *bphp, const char *propname, int *szp); diff --git a/include/mpc86xx.h b/include/mpc86xx.h new file mode 100644 index 00000000000..61b527979ce --- /dev/null +++ b/include/mpc86xx.h @@ -0,0 +1,119 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeffrey Brown (jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + */ + +#ifndef __MPC86xx_H__ +#define __MPC86xx_H__ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ + +/*---------------------------------------------------------------- + * l2cr values. Look in config_.h for the actual setup + */ +#define l2cr 1017 + +#define L2CR_L2E 0x80000000 /* bit 0 - enable */ +#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ +#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ +#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ +#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */ +#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */ +#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ +#define L2CR_L2IP 0x00000001 /* global invalidate in progress */ + +/*---------------------------------------------------------------- + * BAT settings. Look in config_.h for the actual setup + */ + +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc +#define BATU_BL_512M 0x00003ffc +#define BATU_BL_1G 0x00007ffc +#define BATU_BL_2G 0x0000fffc +#define BATU_BL_4G 0x0001fffc + +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 +#define BATU_INVALID 0x00000000 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 +#define BATL_NO_ACCESS 0x00000000 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 + +#define BATL_PP_NO_ACCESS BATL_PP_00 +#define BATL_PP_RO BATL_PP_01 +#define BATL_PP_RW BATL_PP_10 + +#define HID0_XBSEN 0x00000100 +#define HID0_HIGH_BAT_EN 0x00800000 +#define HID0_XAEN 0x00020000 + +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long freqProcessor; + unsigned long freqSystemBus; +} MPC86xx_SYS_INFO; + +#define l1icache_enable icache_enable + +void l2cache_enable(void); +void l1dcache_enable(void); + +static __inline__ unsigned long get_hid0 (void) +{ + unsigned long hid0; + asm volatile("mfspr %0, 1008" : "=r" (hid0) :); + return hid0; +} + +static __inline__ unsigned long get_hid1 (void) +{ + unsigned long hid1; + asm volatile("mfspr %0, 1009" : "=r" (hid1) :); + return hid1; +} + +static __inline__ void set_hid0 (unsigned long hid0) +{ + asm volatile("mtspr 1008, %0" : : "r" (hid0)); +} + +static __inline__ void set_hid1 (unsigned long hid1) +{ + asm volatile("mtspr 1009, %0" : : "r" (hid1)); +} + + +static __inline__ unsigned long get_l2cr (void) +{ + unsigned long l2cr_val; + asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :); + return l2cr_val; +} + +#endif /* _ASMLANGUAGE */ +#endif /* __MPC86xx_H__ */ + + diff --git a/include/pci.h b/include/pci.h index 0fc00e42769..705d1fcd8a6 100644 --- a/include/pci.h +++ b/include/pci.h @@ -270,6 +270,12 @@ #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ #define PCI_AGP_SIZEOF 12 +/* PCI-X registers */ +#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */+#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ +#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ +#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ + /* Slot Identification */ #define PCI_SID_ESR 2 /* Expansion Slot Register */ -- cgit v1.3.1 From 5c9efb36a6b5431423f52888a0e3b4b515fe7eca Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 27 Apr 2006 10:15:16 -0500 Subject: Cleanup whitespaces and style issues. Removed //-style comments. Use 80-column lines. Remove trailing whitespace. Remove dead code and debug cruft. --- board/mpc8641hpcn/mpc8641hpcn.c | 33 ++--- board/mpc8641hpcn/oftree.dts | 2 +- cpu/mpc86xx/cpu.c | 262 +++++++++++++++++++--------------------- cpu/mpc86xx/cpu_init.c | 17 ++- cpu/mpc86xx/i2c.c | 68 +++++------ cpu/mpc86xx/interrupts.c | 23 ++-- cpu/mpc86xx/pci.c | 105 ++++++---------- cpu/mpc86xx/spd_sdram.c | 9 +- cpu/mpc86xx/speed.c | 260 +++++++++++++++++++-------------------- cpu/mpc86xx/start.S | 4 +- cpu/mpc86xx/traps.c | 2 - include/configs/MPC8641HPCN.h | 203 +++++++++++++------------------ include/mpc86xx.h | 6 +- 13 files changed, 439 insertions(+), 555 deletions(-) (limited to 'include') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index cdfce6c1fd0..ace6d47fdee 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -57,9 +57,6 @@ int checkboard (void) #ifdef CONFIG_PCI - /* Sri: Note that at this point we will only test on PCI1 - */ - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; volatile ccsr_pex_t *pex1 = &immap->im_pex1; @@ -70,13 +67,16 @@ int checkboard (void) uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); - if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ - debug ("PCI-EXPRESS 1: %s \n", - pex1_agent ? "Agent" : "Host"); + if ((io_sel==2 || io_sel==3 || io_sel==5 \ + || io_sel==6 || io_sel==7 || io_sel==0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ + debug ("PCI-EXPRESS 1: %s \n", + pex1_agent ? "Agent" : "Host"); debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); if (pex1->pme_msg_det) { pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det); + debug (" with errors. Clearing. Now 0x%08x", + pex1->pme_msg_det); } debug ("\n"); } else { @@ -120,15 +120,6 @@ initdram(int board_type) ddr_enable_ecc(dram_size); #endif - /* - * Initialize SDRAM. Currently HPCN doesn't have - * SDRAM but we'll leave this here for now - * in case someone changes their mind - */ -#if !defined(CONFIG_MPC8641HPCN) - // sdram_init(); -#endif - puts(" DDR: "); return dram_size; } @@ -163,7 +154,7 @@ local_bus_init(void) } #if defined(CFG_DRAM_TEST) -int testdram (void) +int testdram(void) { uint *pstart = (uint *) CFG_MEMTEST_START; uint *pend = (uint *) CFG_MEMTEST_END; @@ -198,10 +189,10 @@ int testdram (void) #if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -long int fixed_sdram (void) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +long int fixed_sdram(void) { #if !defined(CFG_RAMBOOT) volatile immap_t *immap = (immap_t *)CFG_IMMR; diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index 6c32ade0ca4..8e38047e729 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -1,5 +1,5 @@ /* - * MPC8641 HPCn Device Tree Source + * MPC8641 HPCN Device Tree Source * * Copyright 2006 Freescale Semiconductor Inc. * diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index b0fe8abb2c3..36da7774eaf 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -32,31 +32,30 @@ #include #endif +extern unsigned long get_board_sys_clk(ulong dummy); -// SS: For debug only, remove after use static __inline__ unsigned long get_dbat3u (void) { - unsigned long dbat3u; - asm volatile("mfspr %0, 542" : "=r" (dbat3u) :); - return dbat3u; + unsigned long dbat3u; + asm volatile("mfspr %0, 542" : "=r" (dbat3u) :); + return dbat3u; } static __inline__ unsigned long get_dbat3l (void) { - unsigned long dbat3l; - asm volatile("mfspr %0, 543" : "=r" (dbat3l) :); - return dbat3l; + unsigned long dbat3l; + asm volatile("mfspr %0, 543" : "=r" (dbat3l) :); + return dbat3l; } static __inline__ unsigned long get_msr (void) { - unsigned long msr; - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; + unsigned long msr; + asm volatile("mfmsr %0" : "=r" (msr) :); + return msr; } -extern unsigned long get_board_sys_clk(ulong dummy); int checkcpu (void) { @@ -66,7 +65,7 @@ int checkcpu (void) uint major, minor; uint lcrr; /* local bus clock ratio register */ uint clkdiv; /* clock divider portion of lcrr */ - + puts("Freescale PowerPC\n"); pvr = get_pvr(); @@ -74,10 +73,10 @@ int checkcpu (void) major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); - puts ("CPU:\n"); + puts("CPU:\n"); printf(" Core: "); - + switch (ver) { case PVR_VER(PVR_86xx): puts("E600"); @@ -94,7 +93,7 @@ int checkcpu (void) minor = SVR_MIN(svr); puts(" System: "); - switch (ver) { + switch (ver) { case SVR_8641: puts("8641"); break; @@ -113,7 +112,7 @@ int checkcpu (void) printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); - + #if defined(CFG_LBC_LCRR) lcrr = CFG_LBC_LCRR; #else @@ -134,11 +133,11 @@ int checkcpu (void) printf(" L2: "); if (get_l2cr() & 0x80000000) - printf("Enabled\n"); + printf("Enabled\n"); else - printf("Disabled\n"); - - return (0); + printf("Disabled\n"); + + return 0; } @@ -149,7 +148,7 @@ soft_restart(unsigned long addr) { #ifndef CONFIG_MPC8641HPCN - + /* SRR0 has system reset vector, SRR1 has default MSR value */ /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ @@ -215,7 +214,7 @@ int set_px_sysclk(ulong sysclk) sysclk_s = 0x06; sysclk_r = 0x1F; sysclk_v = 0x3B; - sysclk_aux = 0x06; + sysclk_aux = 0x06; break; case 166: sysclk_s = 0x06; @@ -227,14 +226,14 @@ int set_px_sysclk(ulong sysclk) printf("Unsupported SYSCLK frequency.\n"); return 0; } - + vclkh = (sysclk_s << 5) | sysclk_r ; vclkl = sysclk_v; out8(PIXIS_BASE+PIXIS_VCLKH,vclkh); out8(PIXIS_BASE+PIXIS_VCLKL,vclkl); out8(PIXIS_BASE+PIXIS_AUX,sysclk_aux); - + return 1; } @@ -262,7 +261,7 @@ int set_px_mpxpll(ulong mpxpll) tmp = in8(PIXIS_BASE+PIXIS_VSPEED1); tmp = (tmp & 0xF0) | (val & 0x0F); out8(PIXIS_BASE+PIXIS_VSPEED1,tmp); - + return 1; } @@ -270,9 +269,8 @@ int set_px_corepll(ulong corepll) { u8 tmp; u8 val; - - switch((int)corepll) - { + + switch ((int)corepll) { case 20: val = 0x08; break; @@ -295,11 +293,11 @@ int set_px_corepll(ulong corepll) printf("Unsupported COREPLL ratio.\n"); return 0; } - + tmp = in8(PIXIS_BASE+PIXIS_VSPEED0); tmp = (tmp & 0xE0) | (val & 0x1F); out8(PIXIS_BASE+PIXIS_VSPEED0,tmp); - + return 1; } @@ -311,7 +309,7 @@ void read_from_px_regs(int set) tmp = tmp | mask; else tmp = tmp & ~mask; - out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp); + out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp); } void read_from_px_regs_altbank(int set) @@ -322,7 +320,7 @@ void read_from_px_regs_altbank(int set) tmp = tmp | mask; else tmp = tmp & ~mask; - out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp); + out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp); } void set_altbank(void) @@ -342,7 +340,7 @@ void set_px_go(void) out8(PIXIS_BASE+PIXIS_VCTL,tmp); tmp = in8(PIXIS_BASE+PIXIS_VCTL); tmp = tmp | 0x01; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); + out8(PIXIS_BASE+PIXIS_VCTL,tmp); } void set_px_go_with_watchdog(void) @@ -353,7 +351,7 @@ void set_px_go_with_watchdog(void) out8(PIXIS_BASE+PIXIS_VCTL,tmp); tmp = in8(PIXIS_BASE+PIXIS_VCTL); tmp = tmp | 0x09; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); + out8(PIXIS_BASE+PIXIS_VCTL,tmp); } /* This function takes the non-integral cpu:mpx pll ratio @@ -381,11 +379,11 @@ ulong strfractoint(uchar *strptr) no_dec = 1; break; /* Break from loop once the end of string is reached */ } - + intarr[i] = strptr[i]; i++; } - + intarr_len = i; /* Assign length of integer part to intarr_len*/ intarr[i] = '\0'; /* */ @@ -404,14 +402,14 @@ ulong strfractoint(uchar *strptr) i++; j++; } - + decarr_len = j; decarr[j] = '\0'; - + mulconst=1; for(i=0; i 1) - { - cmd = argv[1][1]; - switch(cmd) - { - case 'f': /* reset with frequency changed */ - - if (argc < 5) - goto my_usage; - - read_from_px_regs(0); - - val = set_px_sysclk(simple_strtoul(argv[2],NULL,10)); - - corepll = strfractoint(argv[3]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[4],NULL,10)); - if(val == 3) - { - printf("Setting registers VCFGEN0 and VCTL\n"); - read_from_px_regs(1); - printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); - set_px_go(); - } - else - goto my_usage; - - while(1); /* Not reached */ - - case 'l': - if(argv[2][1] == 'f') - { - read_from_px_regs(0); - read_from_px_regs_altbank(0); - /* reset with frequency changed */ - val = set_px_sysclk(simple_strtoul(argv[3],NULL,10)); - - corepll = strfractoint(argv[4]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10)); - if(val == 3) - { - printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs(1); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); - set_px_go_with_watchdog(); - - } - else - goto my_usage; - - while(1); /* Not reached */ - } - else /* Reset from next bank without changing frequencies */ - { - read_from_px_regs(0); - read_from_px_regs_altbank(0); - if(argc > 2) - goto my_usage; - printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); - set_px_go_with_watchdog(); - while(1); /* Not reached */ - } - - default: - goto my_usage; - } + + if (argc > 1) { + cmd = argv[1][1]; + switch(cmd) { + case 'f': /* reset with frequency changed */ + if (argc < 5) + goto my_usage; + read_from_px_regs(0); + + val = set_px_sysclk(simple_strtoul(argv[2],NULL,10)); + + corepll = strfractoint(argv[3]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[4], + NULL, 10)); + if (val == 3) { + printf("Setting registers VCFGEN0 and VCTL\n"); + read_from_px_regs(1); + printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); + set_px_go(); + } else + goto my_usage; + + while (1); /* Not reached */ + + case 'l': + if (argv[2][1] == 'f') { + read_from_px_regs(0); + read_from_px_regs_altbank(0); + /* reset with frequency changed */ + val = set_px_sysclk(simple_strtoul(argv[3],NULL,10)); + + corepll = strfractoint(argv[4]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10)); + if (val == 3) { + printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs(1); + read_from_px_regs_altbank(1); + printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); + set_px_go_with_watchdog(); + } else + goto my_usage; + + while(1); /* Not reached */ + } else { + /* Reset from next bank without changing frequencies */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if(argc > 2) + goto my_usage; + printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); + set_px_go_with_watchdog(); + while(1); /* Not reached */ + } + + default: + goto my_usage; + } + my_usage: - printf("\nUsage: reset cf \n"); - printf(" reset altbank [cf ]\n"); - printf("For example: reset cf 40 2.5 10\n"); - printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); - return; - } - else - out8(PIXIS_BASE+PIXIS_RST,0); - + printf("\nUsage: reset cf \n"); + printf(" reset altbank [cf ]\n"); + printf("For example: reset cf 40 2.5 10\n"); + printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); + return; + } else + out8(PIXIS_BASE+PIXIS_RST,0); + #endif /* !CONFIG_MPC8641HPCN */ - + while(1); /* not reached */ } -/* ------------------------------------------------------------------------- */ - /* * Get timebase clock frequency */ @@ -566,24 +550,21 @@ unsigned long get_tbclk(void) sys_info_t sys_info; get_sys_info(&sys_info); - return ((sys_info.freqSystemBus + 3L) / 4L); - + return (sys_info.freqSystemBus + 3L) / 4L; } -/* ------------------------------------------------------------------------- */ #if defined(CONFIG_WATCHDOG) void watchdog_reset(void) { - } #endif /* CONFIG_WATCHDOG */ -/* ------------------------------------------------------------------------- */ #if defined(CONFIG_DDR_ECC) -void dma_init(void) { +void dma_init(void) +{ volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; @@ -593,7 +574,8 @@ void dma_init(void) { return; } -uint dma_check(void) { +uint dma_check(void) +{ volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; volatile uint status = dma->sr0; @@ -609,7 +591,8 @@ uint dma_check(void) { return status; } -int dma_xfer(void *dest, uint count, void *src) { +int dma_xfer(void *dest, uint count, void *src) +{ volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; @@ -622,6 +605,7 @@ int dma_xfer(void *dest, uint count, void *src) { asm("sync;isync"); return dma_check(); } + #endif /* CONFIG_DDR_ECC */ @@ -631,7 +615,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) u32 *p; ulong clock; int len; - + clock = bd->bi_busfreq; p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); if (p != NULL) @@ -649,7 +633,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len); memcpy(p, bd->bi_enetaddr, 6); #endif - + #if defined(CONFIG_MPC86XX_TSEC2) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len); memcpy(p, bd->bi_enet1addr, 6); diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 582ac6ba95f..c816c18974c 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -36,13 +36,12 @@ * initialize a bunch of registers */ -void cpu_init_f (void) +void cpu_init_f(void) { DECLARE_GLOBAL_DATA_PTR; volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_lbc_t *memctl = &immap->im_lbc; - //u8 val; - + /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); @@ -72,23 +71,21 @@ void cpu_init_f (void) memctl->br1 = CFG_BR1_PRELIM; #endif - //#if !defined(CONFIG_MPC86xx) #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) memctl->or2 = CFG_OR2_PRELIM; memctl->br2 = CFG_BR2_PRELIM; #endif - //#endif - + #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) memctl->or3 = CFG_OR3_PRELIM; memctl->br3 = CFG_BR3_PRELIM; #endif - + #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) memctl->or4 = CFG_OR4_PRELIM; memctl->br4 = CFG_BR4_PRELIM; #endif - + #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) memctl->or5 = CFG_OR5_PRELIM; memctl->br5 = CFG_BR5_PRELIM; @@ -123,9 +120,9 @@ void cpu_init_f (void) /* * initialize higher level parts of CPU like timers */ -int cpu_init_r (void) +int cpu_init_r(void) { - return (0); + return 0; } diff --git a/cpu/mpc86xx/i2c.c b/cpu/mpc86xx/i2c.c index c5d4642b9ab..f2b4b0f6daa 100644 --- a/cpu/mpc86xx/i2c.c +++ b/cpu/mpc86xx/i2c.c @@ -74,29 +74,27 @@ i2c_init(int speed, int slaveadd) } static __inline__ int -i2c_wait4bus (void) +i2c_wait4bus(void) { ulong timeval = get_timer (0); - // debug("I2C: Wait for bus\n"); while (readb(I2CCSR) & MPC86xx_I2CSR_MBB) { - if (get_timer (timeval) > TIMEOUT) { + if (get_timer(timeval) > TIMEOUT) { return -1; } } - return 0; + return 0; } static __inline__ int -i2c_wait (int write) +i2c_wait(int write) { u32 csr; ulong timeval = get_timer (0); do { csr = readb(I2CCSR); - if (!(csr & MPC86xx_I2CSR_MIF)) continue; @@ -118,7 +116,7 @@ i2c_wait (int write) } return 0; - } while (get_timer (timeval) < TIMEOUT); + } while (get_timer(timeval) < TIMEOUT); debug("i2c_wait: timed out\n"); return -1; @@ -127,14 +125,13 @@ i2c_wait (int write) static __inline__ int i2c_write_addr (u8 dev, u8 dir, int rsta) { - // debug("I2C: Write Addr\n"); - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX | - (rsta?MPC86xx_I2CCR_RSTA:0), + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX + | (rsta ? MPC86xx_I2CCR_RSTA : 0), I2CCCR); writeb((dev << 1) | dir, I2CCDR); - if (i2c_wait (I2C_WRITE) < 0) + if (i2c_wait(I2C_WRITE) < 0) return 0; return 1; @@ -144,14 +141,14 @@ static __inline__ int __i2c_write (u8 *data, int length) { int i; - // debug("I2C: __i2c_write\n"); + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX, I2CCCR); - for (i=0; i < length; i++) { + for (i = 0; i < length; i++) { writeb(data[i], I2CCDR); - if (i2c_wait (I2C_WRITE) < 0) + if (i2c_wait(I2C_WRITE) < 0) break; } @@ -163,33 +160,30 @@ __i2c_read (u8 *data, int length) { int i; - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | - ((length == 1) ? MPC86xx_I2CCR_TXAK : 0), + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA + | ((length == 1) ? MPC86xx_I2CCR_TXAK : 0), I2CCCR); /* dummy read */ readb(I2CCDR); - // debug("length = %d\n", length); - for (i=0; i < length; i++) { - if (i2c_wait (I2C_READ) < 0) + for (i = 0; i < length; i++) { + if (i2c_wait(I2C_READ) < 0) break; /* Generate ack on last next to last byte */ if (i == length - 2) - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | - MPC86xx_I2CCR_TXAK, + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA + | MPC86xx_I2CCR_TXAK, I2CCCR); /* Generate stop on last byte */ if (i == length - 1) writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_TXAK, I2CCCR); - // debug("I2CCR = 0x%08x\n", readb(I2CCCR)); data[i] = readb(I2CCDR); - // debug("data[i] = 0x%08x\n", data[i]); } - // debug("Returning i = %d\n", i); + return i; } @@ -199,19 +193,19 @@ i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) int i = 0; u8 *a = (u8*)&addr; - if (i2c_wait4bus () < 0) + if (i2c_wait4bus() < 0) goto exit; - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) goto exit; - if (__i2c_write (&a[4 - alen], alen) != alen) + if (__i2c_write(&a[4 - alen], alen) != alen) goto exit; - if (i2c_write_addr (dev, I2C_READ, 1) == 0) + if (i2c_write_addr(dev, I2C_READ, 1) == 0) goto exit; - i = __i2c_read (data, length); + i = __i2c_read(data, length); exit: writeb(MPC86xx_I2CCR_MEN, I2CCCR); @@ -225,16 +219,16 @@ i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) int i = 0; u8 *a = (u8*)&addr; - if (i2c_wait4bus () < 0) + if (i2c_wait4bus() < 0) goto exit; - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) goto exit; - if (__i2c_write (&a[4 - alen], alen) != alen) + if (__i2c_write(&a[4 - alen], alen) != alen) goto exit; - i = __i2c_write (data, length); + i = __i2c_write(data, length); exit: writeb(MPC86xx_I2CCR_MEN, I2CCCR); @@ -253,21 +247,21 @@ int i2c_probe (uchar chip) */ udelay(10000); - return i2c_read (chip, 0, 1, (char *)&tmp, 1); + return i2c_read(chip, 0, 1, (char *)&tmp, 1); } uchar i2c_reg_read (uchar i2c_addr, uchar reg) { char buf[1]; - i2c_read (i2c_addr, reg, 1, buf, 1); + i2c_read(i2c_addr, reg, 1, buf, 1); - return (buf[0]); + return buf[0]; } void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) { - i2c_write (i2c_addr, reg, 1, &val, 1); + i2c_write(i2c_addr, reg, 1, &val, 1); } #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 759a30f9f04..b5cd439e53d 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -75,7 +75,7 @@ static __inline__ void set_dec (unsigned long val) /* interrupt is not supported yet */ int interrupt_init_cpu (unsigned *decrementer_count) { - return (0); + return 0; } @@ -91,14 +91,14 @@ int interrupt_init (void) decrementer_count = get_tbclk()/CFG_HZ; debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count); - + set_dec (decrementer_count); set_msr (get_msr () | MSR_EE); debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec()); - - return (0); + + return 0; } @@ -113,7 +113,7 @@ int disable_interrupts (void) ulong msr = get_msr (); set_msr (msr & ~MSR_EE); - return ((msr & MSR_EE) != 0); + return (msr & MSR_EE) != 0; } @@ -131,7 +131,6 @@ void timer_interrupt_cpu (struct pt_regs *regs) { /* nothing to do here */ - return; } @@ -139,14 +138,14 @@ void timer_interrupt (struct pt_regs *regs) { /* call cpu specific function from $(CPU)/interrupts.c */ timer_interrupt_cpu (regs); - + timestamp++; ppcDcbf(×tamp); - + /* Restore Decrementer Count */ set_dec (decrementer_count); - + #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0) WATCHDOG_RESET (); @@ -169,8 +168,8 @@ void reset_timer (void) } ulong get_timer (ulong base) -{ - return (timestamp - base); +{ + return timestamp - base; } void set_timer (ulong t) @@ -185,13 +184,11 @@ void set_timer (ulong t) void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) { - return; } void irq_free_handler(int vec) { - return; } diff --git a/cpu/mpc86xx/pci.c b/cpu/mpc86xx/pci.c index 9cf5f7ca95d..05976bdd4b4 100644 --- a/cpu/mpc86xx/pci.c +++ b/cpu/mpc86xx/pci.c @@ -22,7 +22,7 @@ */ /* - * PEX Configuration space access support for MPC85xx PEX Bridge + * PEX Configuration space access support for PEX Bridge */ #include #include @@ -44,24 +44,25 @@ pci_mpc86xx_init(struct pci_controller *hose) ulong addr, data; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - - if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ + + if ((io_sel==2 || io_sel==3 || io_sel==5 + || io_sel==6 || io_sel==7 || io_sel==0xF ) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ printf ("PCI-EXPRESS 1: Configured as %s \n", pex1_agent ? "Agent" : "Host"); printf (" Scanning PCI bus"); debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); if (pex1->pme_msg_det) { pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det); + debug (" with errors. Clearing. Now 0x%08x", + pex1->pme_msg_det); } debug ("\n"); } - - + hose->first_busno = 0; hose->last_busno = 0x7f; @@ -88,36 +89,26 @@ pci_mpc86xx_init(struct pci_controller *hose) */ pci_register_hose(hose); - //#define MPC8548_REV1_PEX12_ERRATA -#ifdef MPC8548_REV1_PEX12_ERRATA - /* can only read/write 4 bytes */ - pci_read_config_dword (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®32); - printf("pex_mpc85xx_init: pex cr %2x %8x\n",PCI_VENDOR_ID, reg32); - - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®32); - reg32 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg32); -#else pci_read_config_word (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®16); debug("pex_mpc86xx_init: read %2x %4x\n",PCI_VENDOR_ID, reg16); pci_read_config_word (PCI_BDF(0,0,0), PCI_DEVICE_ID, ®16); debug("pex_mpc86xx_init: read %2x %4x\n",PCI_DEVICE_ID, reg16); pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY \ + | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); debug("pex_mpc86xx_init: read %2x %4x\n",PCI_COMMAND, reg16); - -#endif - /* * Clear non-reserved bits in status register. */ - // pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - // pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); + /* + * pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); + * pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); + */ pex1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; pex1->powar1 = 0x8004401c; /* 512M MEM space */ @@ -129,7 +120,6 @@ pci_mpc86xx_init(struct pci_controller *hose) pex1->potar2 = 0x00000000; pex1->potear2 = 0x00000000; - if (!pex1->piwar1) { pex1->pitar1 = 0x00000000; pex1->piwbar1 = (0x80000000 >> 12 ) & 0x000fffff; @@ -140,57 +130,34 @@ pci_mpc86xx_init(struct pci_controller *hose) pex1->pitar2 = 0x00000000; pex1->piwbar2 = (0xe2000000 >> 12 ) & 0x000fffff; pex1->piwar2 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, - - - -/* if (pex1_host) { */ -/* #ifdef MPC8548_REV1_PEX12_ERRATA */ -/* pci_write_config_dword (PCI_BDF(0,0,0), 0x18, 0x00ff0100); */ -/* #else */ - - - - *(u32 *)(0xf8008000)= 0x80000000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - - - pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F); -/* #endif */ - - - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + * Snoop R/W, 2G */ + *(u32 *)(0xf8008000)= 0x80000000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", + *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - - hose->last_busno = pci_hose_scan(hose); - hose->last_busno = 0x21; - debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno); - debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F); + *(u32 *)(0xf8008000)= 0x80200000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", + *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - printf("....PCI scan & enumeration done\n"); + *(u32 *)(0xf8008000)= 0x80200000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", + *(u32*)(0xf8008000), *(u32*)(0xf8008004)); -/* *(u32 *)(0xf8008000)= 0x80000000 | (0x12 << 11); */ -/* printf("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); */ - -/* if (hose->last_busno < 1) { */ -/* hose->last_busno=1; /\*Hack*\/ */ -/* } else { */ -/* hose->last_busno = 0; */ -/* } */ -/*}*/ -/* pci_read_config_dword (PCI_BDF(1,0,0), 0x18, ®32); */ -/* printf("pex_mpc86xx_init: pex cr %2x %8x\n",0x18, reg32); */ + *(u32 *)(0xf8008000)= 0x80200000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", + *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + hose->last_busno = pci_hose_scan(hose); + hose->last_busno = 0x21; + debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno); + debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno); + printf("....PCI scan & enumeration done\n"); } + #endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 9c07f200fbd..9ce31d7c6f3 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -179,7 +179,7 @@ spd_sdram(void) unsigned int law_size; volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; - + /* * Read SPD information. */ @@ -614,7 +614,7 @@ spd_sdram(void) ddr1->timing_cfg_2 = (0 | ((add_lat & 0x7) << 28) /* ADD_LAT */ - | ((cpo & 0x1f) << 23) /* CPO */ + | ((cpo & 0x1f) << 23) /* CPO */ | ((wr_lat & 0x7) << 19) /* WR_LAT */ | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */ | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */ @@ -806,7 +806,7 @@ spd_sdram(void) /* * Memory will be initialized via DMA, or not at all. */ - d_init = 0; + d_init = 0; #endif ddr1->sdram_cfg_2 = (0 @@ -946,8 +946,7 @@ spd_sdram(void) | (LAWAR_SIZE & law_size)); debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); debug("DDR: LARAR1=0x%08x\n", mcm->lawar1); - - + return memsize * 1024 * 1024; } diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 0f5a6388ce1..a08ae5f94b9 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -33,9 +33,7 @@ unsigned long get_board_sys_clk(ulong dummy); unsigned long get_sysclk_from_px_regs(void); -/* --------------------------------------------------------------- */ - -void get_sys_info (sys_info_t * sysInfo) +void get_sys_info (sys_info_t *sysInfo) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; @@ -43,7 +41,7 @@ void get_sys_info (sys_info_t * sysInfo) plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; - + switch(plat_ratio) { case 0x0: sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ; @@ -65,72 +63,77 @@ void get_sys_info (sys_info_t * sysInfo) break; } - // printf("assigned system bus freq = %d for plat ratio 0x%08lx\n", sysInfo->freqSystemBus, plat_ratio); +#if 0 + printf("assigned system bus freq = %d for plat ratio 0x%08lx\n", + sysInfo->freqSystemBus, plat_ratio); +#endif + e600_ratio = (gur->porpllsr) & 0x003f0000; e600_ratio >>= 16; - switch(e600_ratio) { + + switch (e600_ratio) { case 0x10: - sysInfo->freqProcessor = 2*sysInfo->freqSystemBus; + sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus; break; - case 0x19: - sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2; + case 0x19: + sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus/2; break; case 0x20: - sysInfo->freqProcessor = 3*sysInfo->freqSystemBus; + sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; break; case 0x39: - sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2; + sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus/2; break; case 0x28: - sysInfo->freqProcessor = 4*sysInfo->freqSystemBus; + sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus; break; case 0x1d: - sysInfo->freqProcessor = 9*sysInfo->freqSystemBus/2; + sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus/2; break; default: - /* JB - Emulator workaround until real cop is plugged in */ - sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; - //sysInfo->freqProcessor = 3*sysInfo->freqSystemBus; + /* JB - Emulator workaround until real cop is plugged in */ + /* sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; */ + sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; break; } - // printf("assigned processor freq = %d for e600 ratio 0x%08lx\n", sysInfo->freqProcessor, e600_ratio); - +#if 0 + printf("assigned processor freq = %d for e600 ratio 0x%08lx\n", + sysInfo->freqProcessor, e600_ratio); +#endif } -/* ------------------------------------------------------------------------- */ - /* * Measure CPU clock speed (core clock GCLK1, GCLK2) - * * (Approx. GCLK frequency in Hz) */ -int get_clocks (void) +int get_clocks(void) { DECLARE_GLOBAL_DATA_PTR; sys_info_t sys_info; - get_sys_info (&sys_info); + get_sys_info(&sys_info); gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; - - if(gd->cpu_clk != 0) return (0); - else return (1); + + if (gd->cpu_clk != 0) + return 0; + else + return 1; } -/* ------------------------------------------------------------------------- */ -/******************************************** + +/* * get_bus_freq - * return system bus freq in Hz - *********************************************/ -ulong get_bus_freq (ulong dummy) + * Return system bus freq in Hz + */ +ulong get_bus_freq(ulong dummy) { ulong val; - sys_info_t sys_info; - get_sys_info (&sys_info); + get_sys_info(&sys_info); val = sys_info.freqSystemBus; return val; @@ -138,111 +141,100 @@ ulong get_bus_freq (ulong dummy) unsigned long get_sysclk_from_px_regs() { - ulong val; - u8 vclkh,vclkl; - - vclkh = in8(PIXIS_BASE+PIXIS_VCLKH); - vclkl = in8(PIXIS_BASE+PIXIS_VCLKL); - - if((vclkh == 0x84) && (vclkl ==0x07)) - { - val = 33000000; - } - if((vclkh == 0x3F) && (vclkl ==0x20)) - { - val = 40000000; - } - if((vclkh == 0x3F) && (vclkl ==0x2A)) - { - val = 50000000; - } - if((vclkh == 0x24) && (vclkl ==0x04)) - { - val = 66000000; - } - if((vclkh == 0x3F) && (vclkl ==0x4B)) - { - val = 83000000; - } - if((vclkh == 0x3F) && (vclkl ==0x5C)) - { - val = 100000000; - } - if((vclkh == 0xDF) && (vclkl ==0x3B)) - { - val = 134000000; - } - if((vclkh == 0xDF) && (vclkl ==0x4B)) - { - val = 166000000; - } - - return val; + ulong val; + u8 vclkh, vclkl; + + vclkh = in8(PIXIS_BASE + PIXIS_VCLKH); + vclkl = in8(PIXIS_BASE + PIXIS_VCLKL); + + if ((vclkh == 0x84) && (vclkl == 0x07)) { + val = 33000000; + } + if ((vclkh == 0x3F) && (vclkl == 0x20)) { + val = 40000000; + } + if ((vclkh == 0x3F) && (vclkl == 0x2A)) { + val = 50000000; + } + if ((vclkh == 0x24) && (vclkl == 0x04)) { + val = 66000000; + } + if ((vclkh == 0x3F) && (vclkl == 0x4B)) { + val = 83000000; + } + if ((vclkh == 0x3F) && (vclkl == 0x5C)) { + val = 100000000; + } + if ((vclkh == 0xDF) && (vclkl == 0x3B)) { + val = 134000000; + } + if ((vclkh == 0xDF) && (vclkl == 0x4B)) { + val = 166000000; + } + + return val; } -/******* From MPC8641HPCN Design Workbook ************ - * + +/* * get_board_sys_clk - * reads the FPGA on board for CONFIG_SYS_CLK_FREQ - * - ********************************************************/ + * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ + */ unsigned long get_board_sys_clk(ulong dummy) { - u8 i, go_bit, rd_clks; - ulong val; - - go_bit = in8(PIXIS_BASE+PIXIS_VCTL); - go_bit &= 0x01; - - rd_clks = in8(PIXIS_BASE+PIXIS_VCFGEN0); - rd_clks &= 0x1C; - - /* Only if both go bit and the SCLK bit in VCFGEN0 are set - * should we be using the AUX register. Remember, we also set the - * GO bit to boot from the alternate bank on the on-board flash - */ - - if(go_bit) - { - if(rd_clks == 0x1c) - i = in8(PIXIS_BASE+PIXIS_AUX); - else - i = in8(PIXIS_BASE+PIXIS_SPD); - //val = get_sysclk_from_px_regs(); - } - else - i = in8(PIXIS_BASE+PIXIS_SPD); - - i &= 0x07; - - switch(i) - { - case 0: - val = 33000000; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66000000; - break; - case 4: - val = 83000000; - break; - case 5: - val = 100000000; - break; - case 6: - val = 134000000; - break; - case 7: - val = 166000000; - break; - } - - return val; + u8 i, go_bit, rd_clks; + ulong val; + + go_bit = in8(PIXIS_BASE + PIXIS_VCTL); + go_bit &= 0x01; + + rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); + rd_clks &= 0x1C; + + /* + * Only if both go bit and the SCLK bit in VCFGEN0 are set + * should we be using the AUX register. Remember, we also set the + * GO bit to boot from the alternate bank on the on-board flash + */ + + if (go_bit) { + if (rd_clks == 0x1c) + i = in8(PIXIS_BASE + PIXIS_AUX); + else + i = in8(PIXIS_BASE + PIXIS_SPD); + } else { + i = in8(PIXIS_BASE + PIXIS_SPD); + } + + i &= 0x07; + + switch (i) { + case 0: + val = 33000000; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66000000; + break; + case 4: + val = 83000000; + break; + case 5: + val = 100000000; + break; + case 6: + val = 134000000; + break; + case 7: + val = 166000000; + break; + } + + return val; } diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 531bd0c5fbd..0a447a76b75 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -783,12 +783,12 @@ ppcDcbz: dcbz r0,r3 blr -/*------------------------------------------------------------------------------- */ +/*-------------------------------------------------------------------------- */ /* Function: ppcSync */ /* Description: Processor Synchronize */ /* Input: none. */ /* Output: none. */ -/*------------------------------------------------------------------------------- */ +/*-------------------------------------------------------------------------- */ .globl ppcSync ppcSync: sync diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index fdfc95dfc57..8113dfbcc35 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -1,6 +1,4 @@ /* - * linux/arch/ppc/kernel/traps.c - * * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) * * Modified by Cort Dougan (cort@cs.nmt.edu) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 8d2e08851e4..76efd7c604d 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -1,5 +1,6 @@ -/* - * Copyright 2004 Freescale Semiconductor. +/* + * Copyright 2006 Freescale Semiconductor. + * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -22,8 +23,7 @@ */ /* - * mpc8641hpc3 board configuration file - * + * MPC8641HPCN board configuration file * * Make sure you change the MAC address and other network params first, * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. @@ -38,48 +38,38 @@ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ -#undef DEBUG +#undef DEBUG -//#define RUN_DIAG 1 #ifdef RUN_DIAG #define CFG_DIAG_ADDR 0xff800000 #endif + #define CFG_RESET_ADDRESS 0xfff00100 -//#define CONFIG_PCI +#undef CONFIG_PCI + #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -/*#define CONFIG_DDR_ECC */ /* only for ECC DDR module */ -/*#define CONFIG_DDR_DLL */ /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - +#undef CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_ALTIVEC 1 -#define CONFIG_ALTIVEC 1 -/*----------------------------------------------------------------------- +/* * L2CR setup -- make sure this is right for your board! */ - -#define CFG_L2 +#define CFG_L2 #define L2_INIT 0 #define L2_ENABLE (L2CR_L2E) #ifndef CONFIG_SYS_CLK_FREQ -//#define CONFIG_SYS_CLK_FREQ 33000000 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif -/* - * These can be toggled for performance analysis, otherwise use default. - */ -/* JB - XXX - Are these available on 86xx? */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #undef CFG_DRAM_TEST /* memory test, takes time */ @@ -130,10 +120,10 @@ #define CFG_DDR_INTERVAL 0x06090100 #define CFG_DDR_DATA_INIT 0xdeadbeef #define CFG_DDR_CLK_CTRL 0x03800000 - #define CFG_DDR_OCD_CTRL 0x00000000 - #define CFG_DDR_OCD_STATUS 0x00000000 + #define CFG_DDR_OCD_CTRL 0x00000000 + #define CFG_DDR_OCD_STATUS 0x00000000 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ - #define CFG_DDR_CONTROL2 0x04400000 + #define CFG_DDR_CONTROL2 0x04400000 //Not used in fixed_sdram function @@ -143,20 +133,12 @@ #define CFG_DDR_CS3_BNDS 0x00000FFF //Not done #define CFG_DDR_CS4_BNDS 0x00000FFF //Not done #define CFG_DDR_CS5_BNDS 0x00000FFF //Not done - - - #endif #endif /* - * SDRAM on the Local Bus - */ -//#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -//#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 + * In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. * However, when u-boot comes up, the flash_init needs hard start addresses @@ -165,15 +147,12 @@ * knows where the flash is and the user can download u-boot code from promjet to * fef00000 <- more intuitive than fe700000. Note that, on switching the boot * location, fef00000 becomes fff00000. -*/ + */ #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ -#define CFG_FLASH_BASE2 0xff800000 +#define CFG_FLASH_BASE2 0xff800000 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} - -/*Sri: This looks like a good place to init all the Local Bus chip selects*/ - #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ @@ -186,25 +165,24 @@ #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ -#define PIXIS_BASE 0xf8100000 /* PIXIS registers*/ -#define PIXIS_ID 0x0 /* MPC8641HPCN Board ID at offset 0*/ -#define PIXIS_VER 0x1 /* MPC8641HPCN board version version at offset 1*/ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2*/ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register*/ -#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define PIXIS_BASE 0xf8100000 /* PIXIS registers */ +#define PIXIS_ID 0x0 /* Board ID at offset 0 */ +#define PIXIS_VER 0x1 /* Board version at offset 1 */ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ +#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -//#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ #undef CFG_FLASH_CHECKSUM @@ -212,11 +190,9 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -/*#define CFG_HPCN_FLASH_CFI_DRIVER */ #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO - #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else @@ -230,7 +206,7 @@ #undef CONFIG_CLOCKS_IN_MHZ #define CONFIG_L1_INIT_RAM -#undef CFG_INIT_RAM_LOCK +#undef CFG_INIT_RAM_LOCK #ifndef CFG_INIT_RAM_LOCK #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ #else @@ -265,20 +241,22 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 +/* + * Pass open firmware flat tree to kernel + */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 /* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 +#define OF_FLAT_TREE_MAX_SIZE 8192 -#define OF_CPU "PowerPC,8641@0" -#define OF_SOC "soc8641@f8000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" +#define OF_CPU "PowerPC,8641@0" +#define OF_SOC "soc8641@f8000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" -#define CFG_64BIT_VSPRINTF 1 -#define CFG_64BIT_STRTOUL 1 +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ @@ -297,13 +275,10 @@ * Addresses are mapped 1-1. */ #define CFG_PCI1_MEM_BASE 0x80000000 -//#define CFG_PCI1_MEM_BASE 0xd0000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0xe2000000 -//#define CFG_PCI1_IO_BASE 0xe0000000 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -//#define CFG_PCI1_IO_BUS 0x00000000 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ /* For RTL8139 */ @@ -316,29 +291,18 @@ #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ -// #define CFG_PCI1_MEM_BASE 0x80000000 -// #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -// #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -// #define CFG_PCI1_IO_BASE 0xe2000000 -// #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -// #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - - #if defined(CONFIG_PCI) - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -//#define CFG_SCSI_SCAN_BUS_REVERSE - +#undef CFG_SCSI_SCAN_BUS_REVERSE #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_RTL8139 - #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -349,7 +313,6 @@ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -//#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ @@ -371,7 +334,6 @@ #define CONFIG_MPC86XX_TSEC4 1 #define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" - #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 @@ -389,12 +351,10 @@ /* BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR */ -//#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE) -#define CFG_DBAT0U (0x0 | BATU_BL_512M | BATU_VS | BATU_VP) -//#define CFG_IBAT0L CFG_DBAT0L -//#define CFG_IBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0L (0x0| BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) +#define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) +#define CFG_DBAT0U ( BATU_BL_512M | BATU_VS | BATU_VP ) +#define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) #define CFG_IBAT0U CFG_DBAT0U /* BAT1 1G Cache-inhibited, guarded @@ -402,7 +362,8 @@ * 0xa000_0000 512M PCI-Express 2 Memory ** SS - Changed it for operating from 0xd0000000 */ -#define CFG_DBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT1U CFG_DBAT1U @@ -410,7 +371,8 @@ /* BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ -#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT2U CFG_DBAT2U @@ -418,7 +380,8 @@ /* BAT3 4M Cache-inhibited, guarded * 0xf800_0000 4M CCSR */ -#define CFG_DBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT3U CFG_DBAT3U @@ -428,7 +391,8 @@ * 0xe300_0000 16M PCI-Express 2 I/0 ** SS - Note that this is at 0xe0000000 */ -#define CFG_DBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT4U CFG_DBAT4U @@ -444,12 +408,12 @@ /* BAT6 32M Cache-inhibited, guarded * 0xfe00_0000 32M FLASH */ -#define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) #define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CFG_IBAT6U CFG_DBAT6U - #define CFG_DBAT7L 0x00000000 #define CFG_DBAT7U 0x00000000 #define CFG_IBAT7L 0x00000000 @@ -461,17 +425,17 @@ /* * Environment */ - #ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 - #else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 - #endif +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -572,24 +536,25 @@ #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif -#define CONFIG_HAS_ETH1 1 -#define CONFIG_HAS_ETH2 1 -#define CONFIG_HAS_ETH3 1 +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 +#define CONFIG_HAS_ETH3 1 -#define CONFIG_IPADDR 10.82.193.138 +#define CONFIG_IPADDR 10.82.193.138 #define CONFIG_HOSTNAME unknown #define CONFIG_ROOTPATH /opt/nfsroot #define CONFIG_BOOTFILE uImage -#define CONFIG_SERVERIP 10.82.193.104 -#define CONFIG_GATEWAYIP 10.82.193.254 -#define CONFIG_NETMASK 255.255.252.0 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 10.82.193.104 +#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 1000000 /* default location for tftp and bootm */ +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" #define CONFIG_BAUDRATE 115200 @@ -599,7 +564,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=400000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ - "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0" \ + "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\ "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 61b527979ce..4edeae16477 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2006 Freescale Semiconductor. * Jeffrey Brown (jeffrey@freescale.com) * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) */ @@ -9,7 +9,7 @@ #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ -/*---------------------------------------------------------------- +/* * l2cr values. Look in config_.h for the actual setup */ #define l2cr 1017 @@ -23,7 +23,7 @@ #define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ #define L2CR_L2IP 0x00000001 /* global invalidate in progress */ -/*---------------------------------------------------------------- +/* * BAT settings. Look in config_.h for the actual setup */ -- cgit v1.3.1 From 18b6c8cd8af6cc7f35180cedc4adb3236cc1a1b8 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 9 May 2006 08:23:49 -0500 Subject: Get MPC8641HPCN flash images working. Enable the CFI driver. Remove bogus LAWBAR7 cruft. Use correct TEXT_BASE, Fixup load script. Enable SPD EEPROM during DDR setup. Use generic RFC 1918 IP addresses by default. --- board/mpc8641hpcn/config.mk | 3 +-- board/mpc8641hpcn/init.S | 17 ----------------- board/mpc8641hpcn/u-boot.lds | 4 ++-- include/configs/MPC8641HPCN.h | 30 ++++++++++++++---------------- 4 files changed, 17 insertions(+), 37 deletions(-) (limited to 'include') diff --git a/board/mpc8641hpcn/config.mk b/board/mpc8641hpcn/config.mk index 63b9779af05..4bdceec4dc9 100644 --- a/board/mpc8641hpcn/config.mk +++ b/board/mpc8641hpcn/config.mk @@ -25,8 +25,7 @@ # default CCSRBAR is at 0xff700000 # assume U-Boot is less than 0.5MB # -#TEXT_BASE = 0xfff01000 -TEXT_BASE = 0x00400000 +TEXT_BASE = 0xfff01000 PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S index 9d43de55395..4d555a509fa 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/mpc8641hpcn/init.S @@ -80,23 +80,6 @@ #define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -/* -#ifdef CFG_INIT_RAM_LOCK -#define LAWBAR7 ((CFG_RIO_MEM_BASE>>12) & 0xffffff) -#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#endif -*/ -/* - * Stack at 0xfc00_0000 for 32M on LBC - */ -#if !defined(CFG_INIT_RAM_LOCK) -#define LAWBAR7 ((CFG_INIT_RAM_ADDR>>12) & 0xffffff) -#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) -#endif - .section .bootpg, "ax" .globl law_entry law_entry: diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds index dbe8e4fab13..c5c40e7eb49 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/mpc8641hpcn/u-boot.lds @@ -28,7 +28,7 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/ __DYNAMIC = 0; */ SECTIONS { -/* .resetvec 0xFFF00100 : + .resetvec 0xFFF00100 : { *(.resetvec) } = 0xffff @@ -38,7 +38,7 @@ SECTIONS cpu/mpc86xx/start.o (.bootpg) board/mpc8641hpcn/init.o (.bootpg) } = 0xffff -*/ + /* Read-only sections, merged into text segment: */ . = + 1024; .interp : { *(.interp) } diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 76efd7c604d..d4a28edf9ba 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -51,6 +51,7 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #undef CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ @@ -102,11 +103,9 @@ #else /* - * Manually set up DDR parameters + * Manually set up DDR1 parameters */ -/* DDR I */ -#if 1 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ #define CFG_DDR_CS0_BNDS 0x0000000F @@ -125,15 +124,14 @@ #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ #define CFG_DDR_CONTROL2 0x04400000 - //Not used in fixed_sdram function + /* Not used in fixed_sdram function */ #define CFG_DDR_MODE 0x00000022 #define CFG_DDR_CS1_BNDS 0x00000000 - #define CFG_DDR_CS2_BNDS 0x00000FFF //Not done - #define CFG_DDR_CS3_BNDS 0x00000FFF //Not done - #define CFG_DDR_CS4_BNDS 0x00000FFF //Not done - #define CFG_DDR_CS5_BNDS 0x00000FFF //Not done -#endif + #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ #endif @@ -190,6 +188,7 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO @@ -199,14 +198,14 @@ #undef CFG_RAMBOOT #endif -#if !defined(CFG_RAMBOOT) -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT) +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #endif #undef CONFIG_CLOCKS_IN_MHZ #define CONFIG_L1_INIT_RAM -#undef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_LOCK 1 #ifndef CFG_INIT_RAM_LOCK #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ #else @@ -540,22 +539,21 @@ #define CONFIG_HAS_ETH2 1 #define CONFIG_HAS_ETH3 1 -#define CONFIG_IPADDR 10.82.193.138 +#define CONFIG_IPADDR 192.168.1.100 #define CONFIG_HOSTNAME unknown #define CONFIG_ROOTPATH /opt/nfsroot #define CONFIG_BOOTFILE uImage #define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 10.82.193.104 +#define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.255.0 /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 -- cgit v1.3.1 From 586d1d5abd3e525f1e1d9b81e5a61a4da6b2fa3c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 19 May 2006 13:22:44 -0500 Subject: Update 86xx address map and LAWBARs. --- board/mpc8641hpcn/init.S | 25 ++++++++++++++++----- include/asm-ppc/immap_86xx.h | 4 ++-- include/configs/MPC8641HPCN.h | 52 ++++++++++++++++++++++++++----------------- 3 files changed, 54 insertions(+), 27 deletions(-) (limited to 'include') diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S index 4d555a509fa..5f19fdfb6e6 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/mpc8641hpcn/init.S @@ -36,11 +36,10 @@ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xf800_0000 0xf80f_ffff CCSRBAR 1M + * 0xf810_0000 0xf81f_ffff PIXIS 1M * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M * * Notes: @@ -76,9 +75,16 @@ /*#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) */ #define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) - #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) - #define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) +#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR8 0 +#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) +#endif .section .bootpg, "ax" .globl law_entry @@ -151,5 +157,14 @@ law_entry: ori r6,r6,LAWAR7@l stwu r6, 0x20(r5) + /* LAWBAR8, LAWAR8 */ + lis r6,LAWBAR8@h + ori r6,r6,LAWBAR8@l + stwu r6, 0x20(r4) + + lis r6,LAWAR8@h + ori r6,r6,LAWAR8@l + stwu r6, 0x20(r5) + blr diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 6bbe072b2df..9e81b470716 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -52,7 +52,7 @@ typedef struct ccsr_local_mcm { uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ char res19[4]; uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ - char res20[16]; + char res20[20]; uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ char res21[4]; uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ @@ -60,7 +60,7 @@ typedef struct ccsr_local_mcm { uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ char res23[4]; uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ - char res24[720]; + char res24[716]; uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */ char res25[4]; uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index d4a28edf9ba..aaf99c150f7 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -136,15 +136,16 @@ /* - * In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 - * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff + * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. + * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. * However, when u-boot comes up, the flash_init needs hard start addresses - * to build its info table. For user convenience, we have the flash addresses - * as fe800000 and ff800000. That way, when we do flash operations, u-boot - * knows where the flash is and the user can download u-boot code from promjet to - * fef00000 <- more intuitive than fe700000. Note that, on switching the boot - * location, fef00000 becomes fff00000. + * to build its info table. For user convenience, the flash addresses is + * fe800000 and ff800000. That way, u-boot knows where the flash is + * and the user can download u-boot code from promjet to fef00000, a + * more intuitive location than fe700000. + * + * Note that, on switching the boot location, fef00000 becomes fff00000. */ #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ #define CFG_FLASH_BASE2 0xff800000 @@ -257,14 +258,18 @@ #define CFG_64BIT_VSPRINTF 1 #define CFG_64BIT_STRTOUL 1 -/* I2C */ +/* + * I2C + */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -/* RapidIO MMU */ +/* + * RapidIO MMU + */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ @@ -347,19 +352,21 @@ #endif /* CONFIG_TSEC_ENET */ -/* BAT0 2G Cacheable, non-guarded +/* + * BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR */ #define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) -#define CFG_DBAT0U ( BATU_BL_512M | BATU_VS | BATU_VP ) +#define CFG_DBAT0U ( BATU_BL_2G | BATU_VS | BATU_VP ) #define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) #define CFG_IBAT0U CFG_DBAT0U -/* BAT1 1G Cache-inhibited, guarded +/* + * BAT1 1G Cache-inhibited, guarded * 0x8000_0000 512M PCI-Express 1 Memory * 0xa000_0000 512M PCI-Express 2 Memory - ** SS - Changed it for operating from 0xd0000000 + * Changed it for operating from 0xd0000000 */ #define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) @@ -367,7 +374,8 @@ #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT1U CFG_DBAT1U -/* BAT2 512M Cache-inhibited, guarded +/* + * BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ #define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ @@ -376,7 +384,8 @@ #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT2U CFG_DBAT2U -/* BAT3 4M Cache-inhibited, guarded +/* + * BAT3 4M Cache-inhibited, guarded * 0xf800_0000 4M CCSR */ #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ @@ -385,10 +394,11 @@ #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT3U CFG_DBAT3U -/* BAT4 32M Cache-inhibited, guarded +/* + * BAT4 32M Cache-inhibited, guarded * 0xe200_0000 16M PCI-Express 1 I/O * 0xe300_0000 16M PCI-Express 2 I/0 - ** SS - Note that this is at 0xe0000000 + * Note that this is at 0xe0000000 */ #define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) @@ -396,7 +406,8 @@ #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT4U CFG_DBAT4U -/* BAT5 128K Cacheable, non-guarded +/* + * BAT5 128K Cacheable, non-guarded * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) */ #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) @@ -404,7 +415,8 @@ #define CFG_IBAT5L CFG_DBAT5L #define CFG_IBAT5U CFG_DBAT5U -/* BAT6 32M Cache-inhibited, guarded +/* + * BAT6 32M Cache-inhibited, guarded * 0xfe00_0000 32M FLASH */ #define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \ @@ -427,7 +439,7 @@ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */ -- cgit v1.3.1 From 9a655876e5995be80f49054e2509500e871e4d3a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 19 May 2006 13:26:34 -0500 Subject: Enable dual DDR controllers and interleaving. --- cpu/mpc86xx/spd_sdram.c | 615 +++++++++++++++++++++++++++++++++--------- include/configs/MPC8641HPCN.h | 12 +- 2 files changed, 505 insertions(+), 122 deletions(-) (limited to 'include') diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 9ce31d7c6f3..130c8fc3961 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -41,6 +41,15 @@ extern int dma_xfer(void *dest, uint count, void *src); #define CFG_READ_SPD i2c_read #endif +/* + * Only one of the following three should be 1; others should be 0 + * By default the cache line interleaving is selected if + * the CONFIG_DDR_INTERLEAVE flag is defined in MPC8641HPCN.h + */ +#define CFG_PAGE_INTERLEAVING 0 +#define CFG_BANK_INTERLEAVING 0 +#define CFG_SUPER_BANK_INTERLEAVING 0 + /* * Convert picoseconds into clock cycles (rounding up if needed). */ @@ -144,10 +153,11 @@ convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) long int -spd_sdram(void) +spd_init(unsigned char i2c_address, unsigned int ddr_num, + unsigned int dimm_num, unsigned int start_addr) { volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; + volatile ccsr_ddr_t *ddr; volatile ccsr_gur_t *gur = &immap->im_gur; spd_eeprom_t spd; unsigned int n_ranks; @@ -175,28 +185,41 @@ spd_sdram(void) unsigned int mode_caslat; unsigned char sdram_type; unsigned char d_init; + unsigned int law_size; + volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; - - unsigned int law_size; - volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + if (ddr_num == 1) + ddr = &immap->im_ddr1; + else + ddr = &immap->im_ddr2; /* * Read SPD information. */ - CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd)); + debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address); + memset((void *)&spd, 0, sizeof(spd)); + CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd)); /* * Check for supported memory module types. */ if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) { - printf("Unable to locate DDR I or DDR II module.\n" - " Fundamental memory type is 0x%0x\n", - spd.mem_type); + debug("Warning: Unable to locate DDR I or DDR II module for DIMM %d of DDR controller %d.\n" + " Fundamental memory type is 0x%0x\n", + dimm_num, + ddr_num, + spd.mem_type); return 0; } + debug("\nFound memory of type 0x%02lx ", spd.mem_type); + if (spd.mem_type == SPD_MEMTYPE_DDR) + debug("DDR I\n"); + else + debug("DDR II\n"); + /* * These test gloss over DDR I and II differences in interpretation * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks @@ -253,11 +276,7 @@ spd_sdram(void) */ rank_density = compute_banksize(spd.mem_type, spd.row_dens); - - /* - * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg - */ - ddr1->cs0_bnds = (rank_density >> 24) - 1; + debug("Start address for this controller is 0x%08lx\n", start_addr); /* * ODT configuration recommendation from DDR Controller Chapter. @@ -268,30 +287,133 @@ spd_sdram(void) odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */ } - ddr1->cs0_config = ( 1 << 31 - | (odt_rd_cfg << 20) - | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 - | (spd.ncol_addr - 8) ); - debug("\n"); - debug("DDR: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds); - debug("DDR: cs0_config = 0x%08x\n", ddr1->cs0_config); +#ifdef CONFIG_DDR_INTERLEAVE +#ifdef CONFIG_MPC8641HPCN + if (dimm_num != 1) { + printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num); + return 0; + } else { + /* + * Since interleaved memory only uses CS0, the + * memory sticks have to be identical in size and quantity + * of ranks. That essentially gives double the size on + * one rank, i.e on CS0 for both controllers put together. + * Confirm this??? + */ + rank_density *= 2; - if (n_ranks == 2) { /* - * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg + * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg + */ + start_addr = 0; + ddr->cs0_bnds = (start_addr >> 8) + | (((start_addr + rank_density - 1) >> 24)); + /* + * Default interleaving mode to cache-line interleaving. */ - ddr1->cs1_bnds = ( (rank_density >> 8) - | ((rank_density >> (24 - 1)) - 1) ); - ddr1->cs1_config = ( 1<<31 + ddr->cs0_config = ( 1 << 31 +#if (CFG_PAGE_INTERLEAVING == 1) + | (PAGE_INTERLEAVING) +#elif (CFG_BANK_INTERLEAVING == 1) + | (BANK_INTERLEAVING) +#elif (CFG_SUPER_BANK_INTERLEAVING == 1) + | (SUPER_BANK_INTERLEAVING) +#else + | (CACHE_LINE_INTERLEAVING) +#endif | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); - debug("DDR: cs1_bnds = 0x%08x\n", ddr1->cs1_bnds); - debug("DDR: cs1_config = 0x%08x\n", ddr1->cs1_config); + + debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds); + debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config); + + /* + * Adjustment for dual rank memory to get correct memory + * size (return value of this function). + */ + if (n_ranks == 2) { + n_ranks = 1; + rank_density /= 2; + } else { + rank_density /= 2; + } } +#endif /* CONFIG_MPC8641HPCN */ +#else /* CONFIG_DDR_INTERLEAVE */ + + if (dimm_num == 1) { + /* + * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg + */ + ddr->cs0_bnds = (start_addr >> 8) + | (((start_addr + rank_density - 1) >> 24)); + + ddr->cs0_config = ( 1 << 31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + + debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds); + debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config); + + if (n_ranks == 2) { + /* + * Eg: Bounds: 0x1000_0000 to 0x1f00_0000, + * second 256 Meg + */ + ddr->cs1_bnds = (((start_addr + rank_density) >> 8) + | (( start_addr + 2*rank_density - 1) + >> 24)); + ddr->cs1_config = ( 1<<31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds); + debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config); + } + + } else { + /* + * This is the 2nd DIMM slot for this controller + */ + /* + * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg + */ + ddr->cs2_bnds = (start_addr >> 8) + | (((start_addr + rank_density - 1) >> 24)); + + ddr->cs2_config = ( 1 << 31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + + debug("DDR: cs2_bnds = 0x%08x\n", ddr->cs2_bnds); + debug("DDR: cs2_config = 0x%08x\n", ddr->cs2_config); + + if (n_ranks == 2) { + /* + * Eg: Bounds: 0x1000_0000 to 0x1f00_0000, + * second 256 Meg + */ + ddr->cs3_bnds = (((start_addr + rank_density) >> 8) + | (( start_addr + 2*rank_density - 1) + >> 24)); + ddr->cs3_config = ( 1<<31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds); + debug("DDR: cs3_config = 0x%08x\n", ddr->cs3_config); + } + } +#endif /* CONFIG_DDR_INTERLEAVE */ /* * Find the largest CAS by locating the highest 1 bit @@ -447,15 +569,14 @@ spd_sdram(void) unsigned char act_pd_exit = 2; /* Empirical? */ unsigned char pre_pd_exit = 6; /* Empirical? */ - ddr1->timing_cfg_0 = (0 + ddr->timing_cfg_0 = (0 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */ | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */ | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */ | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */ ); - debug("DDR: timing_cfg_0 = 0x%08x\n", ddr1->timing_cfg_0); + debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); - } else { } @@ -520,10 +641,10 @@ spd_sdram(void) /* * Sneak in some Extended Refresh Recovery. */ - ddr1->ext_refrec = (trfc_high << 16); - debug("DDR: ext_refrec = 0x%08x\n", ddr1->ext_refrec); + ddr->ext_refrec = (trfc_high << 16); + debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); - ddr1->timing_cfg_1 = + ddr->timing_cfg_1 = (0 | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */ | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */ @@ -535,7 +656,7 @@ spd_sdram(void) | ((twtr_clk & 0x07) << 0) /* WRTORD */ ); - debug("DDR: timing_cfg_1 = 0x%08x\n", ddr1->timing_cfg_1); + debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); /* @@ -612,7 +733,7 @@ spd_sdram(void) } } - ddr1->timing_cfg_2 = (0 + ddr->timing_cfg_2 = (0 | ((add_lat & 0x7) << 28) /* ADD_LAT */ | ((cpo & 0x1f) << 23) /* CPO */ | ((wr_lat & 0x7) << 19) /* WR_LAT */ @@ -622,7 +743,7 @@ spd_sdram(void) | ((four_act & 0x1f) << 0) /* FOUR_ACT */ ); - debug("DDR: timing_cfg_2 = 0x%08x\n", ddr1->timing_cfg_2); + debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); /* @@ -673,7 +794,7 @@ spd_sdram(void) } /* - * Encoded Burst Lenght of 4. + * Encoded Burst Length of 4. */ burst_len = 2; /* Fiat. */ @@ -706,7 +827,7 @@ spd_sdram(void) mode_odt_enable = 0x40; /* 150 Ohm */ } - ddr1->sdram_mode_1 = + ddr->sdram_mode_1 = (0 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ @@ -715,14 +836,14 @@ spd_sdram(void) | (burst_len << 0) /* Burst length */ ); - debug("DDR: sdram_mode = 0x%08x\n", ddr1->sdram_mode_1); + debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1); /* * Clear EMRS2 and EMRS3. */ - ddr1->sdram_mode_2 = 0; - debug("DDR: sdram_mode_2 = 0x%08x\n", ddr1->sdram_mode_2); + ddr->sdram_mode_2 = 0; + debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2); /* @@ -749,12 +870,12 @@ spd_sdram(void) * Set BSTOPRE to 0x100 for page mode * If auto-charge is used, set BSTOPRE = 0 */ - ddr1->sdram_interval = + ddr->sdram_interval = (0 | (refresh_clk & 0x3fff) << 16 | 0x100 ); - debug("DDR: sdram_interval = 0x%08x\n", ddr1->sdram_interval); + debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval); } /* @@ -763,11 +884,11 @@ spd_sdram(void) */ #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) if (spd.config == 0x02) { - ddr1->err_disable = 0x0000000d; - ddr1->err_sbe = 0x00ff0000; + ddr->err_disable = 0x0000000d; + ddr->err_sbe = 0x00ff0000; } - debug("DDR: err_disable = 0x%08x\n", ddr1->err_disable); - debug("DDR: err_sbe = 0x%08x\n", ddr1->err_sbe); + debug("DDR: err_disable = 0x%08x\n", ddr->err_disable); + debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); #endif asm("sync;isync"); @@ -800,8 +921,8 @@ spd_sdram(void) * Use the DDR controller to auto initialize memory. */ d_init = 1; - ddr1->sdram_data_init = CONFIG_MEM_INIT_VALUE; - debug("DDR: ddr_data_init = 0x%08x\n", ddr1->sdram_data_init); + ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE; + debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init); #else /* * Memory will be initialized via DMA, or not at all. @@ -809,13 +930,13 @@ spd_sdram(void) d_init = 0; #endif - ddr1->sdram_cfg_2 = (0 + ddr->sdram_cfg_2 = (0 | (dqs_cfg << 26) /* Differential DQS */ | (odt_cfg << 21) /* ODT */ | (d_init << 4) /* D_INIT auto init DDR */ ); - debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr1->sdram_cfg_2); + debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2); #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL @@ -835,121 +956,373 @@ spd_sdram(void) clk_adjust = 0x7; } - ddr1->sdram_clk_cntl = (0 + ddr->sdram_clk_cntl = (0 | 0x80000000 | (clk_adjust << 23) ); - debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr1->sdram_clk_cntl); + debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl); } #endif + /* - * Figure out the settings for the sdram_cfg register. - * Build up the entire register in 'sdram_cfg' before writing - * since the write into the register will actually enable the - * memory controller; all settings must be done before enabling. - * - * sdram_cfg[0] = 1 (ddr sdram logic enable) - * sdram_cfg[1] = 1 (self-refresh-enable) - * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) - * 010 DDR 1 SDRAM - * 011 DDR 2 SDRAM + * Figure out memory size in Megabytes. */ - sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3; - sdram_cfg_1 = (0 - | (1 << 31) /* Enable */ - | (1 << 30) /* Self refresh */ - | (sdram_type << 24) /* SDRAM type */ - ); + debug("# ranks = %d, rank_density = 0x%08lx\n", n_ranks, rank_density); + memsize = n_ranks * rank_density / 0x100000; + return memsize; +} + + +unsigned int enable_ddr(unsigned int ddr_num) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + spd_eeprom_t spd1,spd2; + volatile ccsr_ddr_t *ddr; + unsigned sdram_cfg_1; + unsigned char sdram_type, mem_type, config, mod_attr; + unsigned char d_init; + unsigned int no_dimm1=0, no_dimm2=0; + + /* Set up pointer to enable the current ddr controller */ + if (ddr_num == 1) + ddr = &immap->im_ddr1; + else + ddr = &immap->im_ddr2; /* - * sdram_cfg[3] = RD_EN - registered DIMM enable - * A value of 0x26 indicates micron registered DIMMS (micron.com) + * Read both dimm slots and decide whether + * or not to enable this controller. */ - if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) { - sdram_cfg_1 |= 0x10000000; /* RD_EN */ + memset((void *)&spd1,0,sizeof(spd1)); + memset((void *)&spd2,0,sizeof(spd2)); + + if (ddr_num == 1) { + CFG_READ_SPD(SPD_EEPROM_ADDRESS1, + 0, 1, (uchar *) &spd1, sizeof(spd1)); + CFG_READ_SPD(SPD_EEPROM_ADDRESS2, + 0, 1, (uchar *) &spd2, sizeof(spd2)); + } else { + CFG_READ_SPD(SPD_EEPROM_ADDRESS3, + 0, 1, (uchar *) &spd1, sizeof(spd1)); + CFG_READ_SPD(SPD_EEPROM_ADDRESS4, + 0, 1, (uchar *) &spd2, sizeof(spd2)); } -#if defined(CONFIG_DDR_ECC) /* - * If the user wanted ECC (enabled via sdram_cfg[2]) + * Check for supported memory module types. */ - if (spd.config == 0x02) { - sdram_cfg_1 |= 0x20000000; /* ECC_EN */ + if (spd1.mem_type != SPD_MEMTYPE_DDR + && spd1.mem_type != SPD_MEMTYPE_DDR2) { + no_dimm1 = 1; + } else { + debug("\nFound memory of type 0x%02lx ",spd1.mem_type ); + if (spd1.mem_type == SPD_MEMTYPE_DDR) + debug("DDR I\n"); + else + debug("DDR II\n"); + } + + if (spd2.mem_type != SPD_MEMTYPE_DDR && + spd2.mem_type != SPD_MEMTYPE_DDR2) { + no_dimm2 = 1; + } else { + debug("\nFound memory of type 0x%02lx ",spd2.mem_type ); + if (spd2.mem_type == SPD_MEMTYPE_DDR) + debug("DDR I\n"); + else + debug("DDR II\n"); + } + +#ifdef CONFIG_DDR_INTERLEAVE + if (no_dimm1) { + printf("For interleaved operation memory modules need to be present in CS0 DIMM slots of both DDR controllers!\n"); + return 0; } #endif /* - * REV1 uses 1T timing. - * REV2 may use 1T or 2T as configured by the user. + * Memory is not present in DIMM1 and DIMM2 - so do not enable DDRn */ - { - uint pvr = get_pvr(); + if (no_dimm1 && no_dimm2) { + printf("No memory modules found for DDR controller %d!!\n", ddr_num); + return 0; + } else { + mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type; - if (pvr != PVR_85xx_REV1) { + /* + * Figure out the settings for the sdram_cfg register. + * Build up the entire register in 'sdram_cfg' before + * writing since the write into the register will + * actually enable the memory controller; all settings + * must be done before enabling. + * + * sdram_cfg[0] = 1 (ddr sdram logic enable) + * sdram_cfg[1] = 1 (self-refresh-enable) + * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) + * 010 DDR 1 SDRAM + * 011 DDR 2 SDRAM + */ + sdram_type = (mem_type == SPD_MEMTYPE_DDR) ? 2 : 3; + sdram_cfg_1 = (0 + | (1 << 31) /* Enable */ + | (1 << 30) /* Self refresh */ + | (sdram_type << 24) /* SDRAM type */ + ); + + /* + * sdram_cfg[3] = RD_EN - registered DIMM enable + * A value of 0x26 indicates micron registered + * DIMMS (micron.com) + */ + mod_attr = no_dimm2 ? spd1.mod_attr : spd2.mod_attr; + if (mem_type == SPD_MEMTYPE_DDR && mod_attr == 0x26) { + sdram_cfg_1 |= 0x10000000; /* RD_EN */ + } + +#if defined(CONFIG_DDR_ECC) + + config = no_dimm2 ? spd1.config : spd2.config; + + /* + * If the user wanted ECC (enabled via sdram_cfg[2]) + */ + if (config == 0x02) { + sdram_cfg_1 |= 0x20000000; /* ECC_EN */ + } +#endif + + /* + * REV1 uses 1T timing. + * REV2 may use 1T or 2T as configured by the user. + */ + { + uint pvr = get_pvr(); + + if (pvr != PVR_85xx_REV1) { #if defined(CONFIG_DDR_2T_TIMING) - /* - * Enable 2T timing by setting sdram_cfg[16]. - */ - sdram_cfg_1 |= 0x8000; /* 2T_EN */ + /* + * Enable 2T timing by setting sdram_cfg[16]. + */ + sdram_cfg_1 |= 0x8000; /* 2T_EN */ #endif + } } - } - /* - * 200 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - */ - udelay(200); + /* + * 200 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + */ + udelay(200); - /* - * Go! - */ - ddr1->sdram_cfg_1 = sdram_cfg_1; + /* + * Go! + */ + ddr->sdram_cfg_1 = sdram_cfg_1; - asm("sync;isync"); - udelay(500); + asm volatile("sync;isync"); + udelay(500); - debug("DDR: sdram_cfg = 0x%08x\n", ddr1->sdram_cfg_1); + debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg_1); #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - debug("DDR: memory initializing\n"); - /* - * Poll until memory is initialized. - * 512 Meg at 400 might hit this 200 times or so. - */ - while ((ddr1->sdram_cfg_2 & (d_init << 4)) != 0) { - udelay(1000); + d_init = 1; + debug("DDR: memory initializing\n"); + + /* + * Poll until memory is initialized. + * 512 Meg at 400 might hit this 200 times or so. + */ + while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { + udelay(1000); + } + debug("DDR: memory initialized\n\n"); +#endif + + debug("Enabled DDR Controller %d\n", ddr_num); + return 1; + } +} + + +long int +spd_sdram(void) +{ + int memsize_ddr1_dimm1 = 0; + int memsize_ddr1_dimm2 = 0; + int memsize_ddr2_dimm1 = 0; + int memsize_ddr2_dimm2 = 0; + int memsize_total = 0; + int memsize_ddr1 = 0; + int memsize_ddr2 = 0; + unsigned int ddr1_enabled = 0; + unsigned int ddr2_enabled = 0; + unsigned int law_size_ddr1; + unsigned int law_size_ddr2; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; + volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2; + volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + +#ifdef CONFIG_DDR_INTERLEAVE + unsigned int law_size_interleaved; + + memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, + 1, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr1_dimm1; + + memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3, + 2, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr2_dimm1; + + if (memsize_ddr1_dimm1 != memsize_ddr2_dimm1) { + if (memsize_ddr1_dimm1 < memsize_ddr2_dimm1) + memsize_total -= memsize_ddr1_dimm1; + else + memsize_total -= memsize_ddr2_dimm1; + debug("Total memory available for interleaving 0x%08lx\n", + memsize_total * 1024 * 1024); + debug("Adjusting CS0_BNDS to account for unequal DIMM sizes in interleaved memory\n"); + ddr1->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24; + ddr2->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24; + debug("DDR1: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds); + debug("DDR2: cs0_bnds = 0x%08x\n", ddr2->cs0_bnds); } - debug("DDR: memory initialized\n"); + + ddr1_enabled = enable_ddr(1); + ddr2_enabled = enable_ddr(2); + + /* + * Both controllers need to be enabled for interleaving. + */ + if (ddr1_enabled && ddr2_enabled) { + law_size_interleaved = 19 + __ilog2(memsize_total); + + /* + * Set up LAWBAR for DDR 1 space. + */ + mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + mcm->lawar1 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR_INTERLEAVED + | (LAWAR_SIZE & law_size_interleaved)); + debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); + debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); + debug("Interleaved memory size is 0x%08lx\n", memsize_total); + +#ifdef CONFIG_DDR_INTERLEAVE +#if (CFG_PAGE_INTERLEAVING == 1) + printf("Page "); +#elif (CFG_BANK_INTERLEAVING == 1) + printf("Bank "); +#elif (CFG_SUPER_BANK_INTERLEAVING == 1) + printf("Super-bank "); +#else + printf("Cache-line "); #endif +#endif + printf("Interleaved"); + return memsize_total * 1024 * 1024; + } else { + printf("Interleaved memory not enabled - check CS0 DIMM slots for both controllers.\n"); + return 0; + } + +#else + /* + * Call spd_sdram() routine to init ddr1 - pass I2c address, + * controller number, dimm number, and starting address. + */ + memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, + 1, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr1_dimm1; + memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2, + 1, 2, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr1_dimm2; /* - * Figure out memory size in Megabytes. + * Enable the DDR controller - pass ddr controller number. */ - memsize = n_ranks * rank_density / 0x100000; + ddr1_enabled = enable_ddr(1); + /* Keep track of memory to be addressed by DDR1 */ + memsize_ddr1 = memsize_ddr1_dimm1 + memsize_ddr1_dimm2; - /* + /* * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord. */ - law_size = 19 + __ilog2(memsize); + if (ddr1_enabled) { + law_size_ddr1 = 19 + __ilog2(memsize_ddr1); + + /* + * Set up LAWBAR for DDR 1 space. + */ + mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + mcm->lawar1 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR1 + | (LAWAR_SIZE & law_size_ddr1)); + debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); + debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); + } + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3, + 2, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr2_dimm1; + + memsize_ddr2_dimm2 = spd_init(SPD_EEPROM_ADDRESS4, + 2, 2, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr2_dimm2; + + ddr2_enabled = enable_ddr(2); + + /* Keep track of memory to be addressed by DDR2 */ + memsize_ddr2 = memsize_ddr2_dimm1 + memsize_ddr2_dimm2; + + if (ddr2_enabled) { + law_size_ddr2 = 19 + __ilog2(memsize_ddr2); + + /* + * Set up LAWBAR for DDR 2 space. + */ + if (ddr1_enabled) + mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12) + & 0xfffff); + else + mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + + mcm->lawar8 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR2 + | (LAWAR_SIZE & law_size_ddr2)); + debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8); + debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8); + } +#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ + + debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n", + memsize_ddr1, memsize_ddr2); /* - * Set up LAWBAR for all of DDR. + * If neither DDR controller is enabled return 0. */ - mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); - mcm->lawar1 = (LAWAR_EN - | LAWAR_TRGT_IF_DDR - | (LAWAR_SIZE & law_size)); - debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); - debug("DDR: LARAR1=0x%08x\n", mcm->lawar1); + if (!ddr1_enabled && !ddr2_enabled) + return 0; + else { + printf("Non-interleaved"); + return memsize_total * 1024 * 1024; + } - return memsize * 1024 * 1024; +#endif /* CONFIG_DDR_INTERLEAVE */ } + #endif /* CONFIG_SPD_EEPROM */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index aaf99c150f7..2a197be294d 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -57,6 +57,13 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_NUM_DDR_CONTROLLERS 2 +/* #define CONFIG_DDR_INTERLEAVE 1 */ +#define CACHE_LINE_INTERLEAVING 0x20000000 +#define PAGE_INTERLEAVING 0x21000000 +#define BANK_INTERLEAVING 0x22000000 +#define SUPER_BANK_INTERLEAVING 0x23000000 + #define CONFIG_ALTIVEC 1 @@ -99,7 +106,10 @@ /* * Determine DDR configuration from I2C interface. */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ #else /* -- cgit v1.3.1 From fa7db9c377bc2353a17bf1d381d65a6c418728f0 Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong-R64188 Date: Tue, 27 Jun 2006 18:11:54 +0800 Subject: Enable PCIE1 for MPC8641HPCN board Signed-off-by: Jason Jin --- cpu/mpc86xx/Makefile | 4 +- cpu/mpc86xx/pci.c | 192 ++++++++++++++++++---------------------- cpu/mpc86xx/pcie_indirect.c | 198 ++++++++++++++++++++++++++++++++++++++++++ include/asm-ppc/immap_86xx.h | 62 ++++++------- include/configs/MPC8641HPCN.h | 20 +++-- 5 files changed, 330 insertions(+), 146 deletions(-) create mode 100644 cpu/mpc86xx/pcie_indirect.c (limited to 'include') diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile index ab6255a7dfd..79959451694 100644 --- a/cpu/mpc86xx/Makefile +++ b/cpu/mpc86xx/Makefile @@ -28,9 +28,9 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.o #resetvec.o -ASOBJS = cache.o +ASOBJS = cache.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o i2c.o spd_sdram.o + pci.o pcie_indirect.o i2c.o spd_sdram.o OBJS = $(COBJS) all: .depend $(START) $(ASOBJS) $(LIB) diff --git a/cpu/mpc86xx/pci.c b/cpu/mpc86xx/pci.c index 05976bdd4b4..deb66aa64f4 100644 --- a/cpu/mpc86xx/pci.c +++ b/cpu/mpc86xx/pci.c @@ -1,6 +1,9 @@ /* - * Copyright 2005 Freescale Semiconductor. + * Copyright (C) Freescale Semiconductor,Inc. + * 2005, 2006. All rights reserved. + * * Ed Swarthout (ed.swarthout@freescale.com) + * Jason Jin (Jason.jin@freescale.com) * * See file CREDITS for list of people who contributed to this * project. @@ -22,142 +25,115 @@ */ /* - * PEX Configuration space access support for PEX Bridge + * PCIE Configuration space access support for PCIE Bridge */ #include #include - #if defined(CONFIG_PCI) - void pci_mpc86xx_init(struct pci_controller *hose) { volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; - volatile ccsr_pex_t *pex1 = &immap->im_pex1; + volatile ccsr_pex_t *pcie1 = &immap->im_pex1; + u16 temp16; + u32 temp32; + volatile ccsr_gur_t *gur = &immap->im_gur; uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_host = (host1_agent == 2) || (host1_agent == 3); - - u16 reg16, reg16_1, reg16_2, reg16_3; - u32 reg32, i; - - ulong addr, data; - - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - - if ((io_sel==2 || io_sel==3 || io_sel==5 - || io_sel==6 || io_sel==7 || io_sel==0xF ) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ - printf ("PCI-EXPRESS 1: Configured as %s \n", - pex1_agent ? "Agent" : "Host"); - printf (" Scanning PCI bus"); - debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); - if (pex1->pme_msg_det) { - pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x", - pex1->pme_msg_det); - } - debug ("\n"); - } - - hose->first_busno = 0; - hose->last_busno = 0x7f; - - pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - pci_set_region(hose->regions + 1, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, - PCI_REGION_IO); + uint pcie1_host = (host1_agent == 2) || (host1_agent == 3); + uint pcie1_agent = (host1_agent == 0) || (host1_agent == 1); + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + + if ((io_sel ==2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || + io_sel == 7 || io_sel == 0xf) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ + printf ("PCI-EXPRESS 1: Configured as %s \n", + pcie1_agent ? "Agent" : "Host"); + if(pcie1_agent) return; /*Don't scan bus when configured as agent*/ + printf (" Scanning PCIE bus"); + debug("0x%08x=0x%08x ", &pcie1->pme_msg_det,pcie1->pme_msg_det); + if (pcie1->pme_msg_det) { + pcie1->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x", + pcie1->pme_msg_det); + } + debug ("\n"); + } + else{ + printf("PCI-EXPRESS 1 disabled!\n"); + return; + } - hose->region_count = 2; + /*set first_bus=0 only skipped B0:D0:F0 which is + * a reserved device in M1575, but make it easy for + * most of the scan process. + */ + hose->first_busno = 0x00; + hose->last_busno = 0xfe; - pci_setup_indirect(hose, + pcie_setup_indirect(hose, (CFG_IMMR+0x8000), (CFG_IMMR+0x8004)); - /* - * Hose scan. - */ - pci_register_hose(hose); + pci_hose_read_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, &temp16); + temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, temp16); - pci_read_config_word (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®16); - debug("pex_mpc86xx_init: read %2x %4x\n",PCI_VENDOR_ID, reg16); - pci_read_config_word (PCI_BDF(0,0,0), PCI_DEVICE_ID, ®16); - debug("pex_mpc86xx_init: read %2x %4x\n",PCI_DEVICE_ID, reg16); + pci_hose_write_config_word(hose,PCI_BDF(0,0,0), PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, 0x80); - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY \ - | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); + pci_hose_read_config_dword(hose, PCI_BDF(0,0,0), PCI_PRIMARY_BUS, &temp32); + temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16); + pci_hose_write_config_dword(hose, PCI_BDF(0,0,0), PCI_PRIMARY_BUS, temp32); - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - debug("pex_mpc86xx_init: read %2x %4x\n",PCI_COMMAND, reg16); + pcie1->powar1 = 0; + pcie1->powar2 = 0; + pcie1->piwar1 = 0; + pcie1->piwar1 = 0; - /* - * Clear non-reserved bits in status register. - */ - /* - * pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - * pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); - */ + pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcie1->powar1 = 0x8004401c; /* 512M MEM space */ + pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcie1->potear1 = 0x00000000; - pex1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pex1->powar1 = 0x8004401c; /* 512M MEM space */ - pex1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pex1->potear1 = 0x00000000; - - pex1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; - pex1->powar2 = 0x80088017; /* 16M IO space */ - pex1->potar2 = 0x00000000; - pex1->potear2 = 0x00000000; - - if (!pex1->piwar1) { - pex1->pitar1 = 0x00000000; - pex1->piwbar1 = (0x80000000 >> 12 ) & 0x000fffff; - pex1->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, - * Snoop R/W, 2G */ - } + pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcie1->powar2 = 0x80088017; /* 16M IO space */ + pcie1->potar2 = 0x00000000; + pcie1->potear2 = 0x00000000; - pex1->pitar2 = 0x00000000; - pex1->piwbar2 = (0xe2000000 >> 12 ) & 0x000fffff; - pex1->piwar2 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, - * Snoop R/W, 2G */ + pcie1->pitar1 = 0x00000000; + pcie1->piwbar1 = 0x00000000; + /* Enable, Prefetch, Local Mem, * Snoop R/W, 2G */ + pcie1->piwar1 = 0xa0f5501e; - *(u32 *)(0xf8008000)= 0x80000000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", - *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F); + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", - *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", - *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + hose->region_count = 3; - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", - *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); - hose->last_busno = 0x21; - debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno); - debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno); + debug("pcie_mpc86xx_init: last_busno %x\n",hose->last_busno); + debug("pcie_mpc86xx init: current_busno %x\n ",hose->current_busno); - printf("....PCI scan & enumeration done\n"); + printf("....PCIE1 scan & enumeration done\n"); } - #endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/pcie_indirect.c b/cpu/mpc86xx/pcie_indirect.c new file mode 100644 index 00000000000..e3cb4beede9 --- /dev/null +++ b/cpu/mpc86xx/pcie_indirect.c @@ -0,0 +1,198 @@ +/* + * Support for indirect PCI bridges. + * + * Copyright (c) Freescale Semiconductor, Inc. + * 2006. All rights reserved. + * + * Jason Jin + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * partly derived from + * arch/powerpc/platforms/86xx/mpc86xx_pcie.c + */ + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include + +#define PCI_CFG_OUT out_be32 +#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff) + +static int +indirect_read_config_pcie(struct pci_controller *hose, + pci_dev_t dev, int offset, + int len,u32 *val) +{ + int bus = PCI_BUS(dev); + char devfn = ( (PCI_DEV(dev) << 4 ) | (PCI_FUNC(dev)) ) ; + + unsigned char *cfg_data; + u32 temp; + + PEX_FIX; + if( bus == 0xff) { + PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); + }else { + PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); + } + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ + cfg_data = hose->cfg_data; + PEX_FIX; + temp = in_le32(cfg_data); + switch (len) { + case 1: + *val = (temp >> (((offset & 3))*8)) & 0xff; + break; + case 2: + *val = (temp >> (((offset & 3))*8)) & 0xffff; + break; + default: + *val = temp; + break; + } + + return 0; +} + +static int +indirect_write_config_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + int len, + u32 val) +{ + int bus = PCI_BUS(dev); + char devfn = ( (PCI_DEV(dev) << 4 ) | (PCI_FUNC(dev)) ) ; + + unsigned char *cfg_data; + u32 temp; + + PEX_FIX; + if( bus == 0xff) { + PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); + }else { + PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); + } + + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ + cfg_data = hose->cfg_data; + switch (len) { + case 1: + PEX_FIX; + temp = in_le32(cfg_data); + temp = (temp & ~(0xff << ((offset & 3) * 8))) | + (val << ((offset & 3) * 8)); + PEX_FIX; + out_le32(cfg_data, temp); + break; + case 2: + PEX_FIX; + temp = in_le32(cfg_data); + temp = (temp & ~(0xffff << ((offset & 3) * 8))); + temp |= (val << ((offset & 3) * 8)) ; + PEX_FIX; + out_le32(cfg_data, temp); + break; + default: + PEX_FIX; + out_le32(cfg_data, val); + break; + } + PEX_FIX; + return 0; +} + +static int +indirect_read_config_byte_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + u8 *val) +{ + u32 val32; + indirect_read_config_pcie(hose,dev,offset,1,&val32); + *val = (u8)val32; + return 0; +} + +static int +indirect_read_config_word_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + u16 *val) +{ + u32 val32; + indirect_read_config_pcie(hose,dev,offset,2,&val32); + *val = (u16)val32; + return 0; +} + +static int +indirect_read_config_dword_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + u32 *val) +{ + return indirect_read_config_pcie(hose,dev, offset,4,val); +} + +static int +indirect_write_config_byte_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + char val) +{ + return indirect_write_config_pcie(hose,dev, offset,1,(u32)val); +} + +static int +indirect_write_config_word_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + unsigned short val) +{ + return indirect_write_config_pcie(hose,dev, offset,2,(u32)val); +} + +static int +indirect_write_config_dword_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + unsigned short val) +{ + return indirect_write_config_pcie(hose,dev, offset,4,val); +} + +void +pcie_setup_indirect(struct pci_controller* hose, + u32 cfg_addr, + u32 cfg_data) +{ + pci_set_ops(hose, + indirect_read_config_byte_pcie, + indirect_read_config_word_pcie, + indirect_read_config_dword_pcie, + indirect_write_config_byte_pcie, + indirect_write_config_word_pcie, + indirect_write_config_dword_pcie); + + hose->cfg_addr = (unsigned int *) cfg_addr; + hose->cfg_data = (unsigned char *) cfg_data; +} + +#endif /* CONFIG_PCI */ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 9e81b470716..5b1f0f4ea6c 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -284,41 +284,41 @@ typedef struct ccsr_pex { char res2[16]; uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */ uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */ - uint pme_msg_dis; /* 0x802C - PEX PME & message disable register */ - char res3[4]; - uint pm_command; /* 0x8030 - PEX PM Command register */ - char res4[3016]; - uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */ - uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */ + uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */ + uint pm_command; /* 0x802c - PEX PM Command register */ + char res3[3016]; + uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */ + uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */ uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */ uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */ - char res5[8]; + char res4[8]; uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */ - char res6[12]; + char res5[12]; uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */ uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */ uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */ - char res7[4]; + char res6[4]; uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */ - char res8[12]; + char res7[12]; uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */ uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */ uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */ - char res9[4]; + char res8[4]; uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */ - char res10[12]; + char res9[12]; uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */ uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */ uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */ - char res11[4]; + char res10[4]; uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */ - char res12[12]; + char res11[12]; uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */ uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */ uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */ - char res13[4]; + char res12[4]; uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */ - char res14[268]; + char res13[12]; + char res14[256]; uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */ char res15[4]; uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */ @@ -332,23 +332,25 @@ typedef struct ccsr_pex { uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */ char res18[12]; uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */ - char res19[4]; + char res19[4]; uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */ - char res20[4]; + uint piwbear1; uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */ - char res21[12]; + char res20[12]; uint pedr; /* 0x8e00 - PEX Error Detect Register */ - uint pecdr; /* 0x8e04 - PEX Error Capture Disable Register */ - uint peer; /* 0x8e08 - PEX Error Enable Register */ - uint perr_cap0; /* 0x8e0c - PEX Error Capture Register 0 */ - uint perr_cap1; /* 0x8e10 - PEX Error Capture Register 1 */ - uint perr_cap2; /* 0x8e14 - PEX Error Capture Register 2 */ - uint perr_cap3; /* 0x8e18 - PEX Error Capture Register 3 */ - char res22[100]; - uint perr_stat; /* 0x8e80 - PEX Error Status Register */ - char res23[124]; - uint pdebug; /* 0x8f00 - PEX Debug Register */ - char res24[248]; //Sri: changed this because of adding 4 bytes before 0x?8020. + char res21[4]; + uint peer; /* 0x8e08 - PEX Error Interrupt Enable Register */ + char res22[4]; + uint pecdr; /* 0x8e10 - PEX Error Disable Register */ + char res23[12]; + uint peer_stat; /* 0x8e20 - PEX Error Capture Status Register */ + char res24[4]; + uint perr_cap0; /* 0x8e28 - PEX Error Capture Register 0 */ + uint perr_cap1; /* 0x8e2c - PEX Error Capture Register 1 */ + uint perr_cap2; /* 0x8e30 - PEX Error Capture Register 2 */ + uint perr_cap3; /* 0x8e34 - PEX Error Capture Register 3 */ + char res25[452]; + char res26[4]; } ccsr_pex_t; /* Hyper Transport Register Block (0xA000-0xB000) */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 2a197be294d..4453171d45a 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -46,7 +46,8 @@ #define CFG_RESET_ADDRESS 0xfff00100 -#undef CONFIG_PCI +/*#undef CONFIG_PCI*/ +#define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -209,8 +210,10 @@ #undef CFG_RAMBOOT #endif -#if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT) -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#if defined(CFG_RAMBOOT) +#undef CFG_FLASH_CFI_DRIVER +#undef CONFIG_SPD_EEPROM +#define CFG_SDRAM_SIZE 256 #endif #undef CONFIG_CLOCKS_IN_MHZ @@ -295,6 +298,11 @@ #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + /* For RTL8139 */ #define _IO_BASE 0x00000000 @@ -429,10 +437,10 @@ * BAT6 32M Cache-inhibited, guarded * 0xfe00_0000 32M FLASH */ -#define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \ +#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) #define CFG_IBAT6U CFG_DBAT6U #define CFG_DBAT7L 0x00000000 -- cgit v1.3.1 From bc09cf3c2bfb8d54c659cbb332f79d0950982fd0 Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong-R64188 Date: Tue, 27 Jun 2006 18:12:10 +0800 Subject: Fix RTL8139 in big endian signed-off-by: Jason Jin signed-off-by: Wei Zhang --- drivers/rtl8139.c | 1 + include/configs/MPC8641HPCN.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index a95f84e6258..848d1d177ae 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -196,6 +196,7 @@ static void rtl_disable(struct eth_device *dev); static struct pci_device_id supported[] = { {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, + {0x1186, 0x1300}, {} }; diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 4453171d45a..b0897695a7c 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -304,6 +304,7 @@ #define CFG_PCI_MEMORY_SIZE 0x80000000 /* For RTL8139 */ +#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) #define _IO_BASE 0x00000000 #define CFG_PCI2_MEM_BASE 0xa0000000 -- cgit v1.3.1 From da012ab661fd4ab169dd7b9b32201a4df62cf34a Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong Date: Wed, 28 Jun 2006 08:43:56 -0500 Subject: Change Id to symbolic name for RTL8139 Signed-off-by: Jason Jin --- drivers/rtl8139.c | 2 +- include/pci_ids.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index 848d1d177ae..afe1a4fdaf6 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -196,7 +196,7 @@ static void rtl_disable(struct eth_device *dev); static struct pci_device_id supported[] = { {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, - {0x1186, 0x1300}, + {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139}, {} }; diff --git a/include/pci_ids.h b/include/pci_ids.h index 8cc3ec0a235..3b104524160 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1045,6 +1045,9 @@ #define PCI_DEVICE_ID_REALTEK_8139 0x8139 #define PCI_DEVICE_ID_REALTEK_8169 0x8169 +#define PCI_VENDOR_ID_DLINK 0x1186 +#define PCI_DEVICE_ID_DLINK_8139 0x1300 + #define PCI_VENDOR_ID_XILINX 0x10ee #define PCI_DEVICE_ID_TURBOPAM 0x4020 -- cgit v1.3.1 From 1b380ec225665e73959677f3893dc658c5925e05 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:42:24 -0500 Subject: * Patch to modify ft_build.c to update flat device trees in place Patch by Matthew McClintock 26-June-2006 --- common/cmd_bootm.c | 2 +- common/ft_build.c | 341 ++++++++++++++++------------------------------------- include/ft_build.h | 19 +-- 3 files changed, 115 insertions(+), 247 deletions(-) (limited to 'include') diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index a472a1d7b25..f1c0eb4d183 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -836,7 +836,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); #else - ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd, initrd_start, initrd_end); + ft_setup(of_flat_tree, kbd, initrd_start, initrd_end); /* ft_dump_blob(of_flat_tree); */ #if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) diff --git a/common/ft_build.c b/common/ft_build.c index 9e9c906fc1f..b5a997c1ba5 100644 --- a/common/ft_build.c +++ b/common/ft_build.c @@ -1,5 +1,22 @@ /* * OF flat tree builder + * Written by: Pantelis Antoniou + * Updated by: Matthew McClintock + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #include @@ -13,44 +30,39 @@ #include +#undef DEBUG + /* align addr on a size boundary - adjust address up if needed -- Cort */ #define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1))) +#ifndef CONFIG_OF_BOOT_CPU +#define CONFIG_OF_BOOT_CPU 0 +#endif +#define SIZE_OF_RSVMAP_ENTRY (2*sizeof(u64)) static void ft_put_word(struct ft_cxt *cxt, u32 v) { - if (cxt->overflow) /* do nothing */ - return; - - /* check for overflow */ - if (cxt->p + 4 > cxt->pstr) { - cxt->overflow = 1; - return; - } + memmove(cxt->p + sizeof(u32), cxt->p, cxt->p_end - cxt->p); *(u32 *) cxt->p = cpu_to_be32(v); - cxt->p += 4; + cxt->p += sizeof(u32); + cxt->p_end += sizeof(u32); } static inline void ft_put_bin(struct ft_cxt *cxt, const void *data, int sz) { - u8 *p; + int aligned_size = ((u8 *)_ALIGN((unsigned long)cxt->p + sz, + sizeof(u32))) - cxt->p; - if (cxt->overflow) /* do nothing */ - return; - - /* next pointer pos */ - p = (u8 *) _ALIGN((unsigned long)cxt->p + sz, 4); + memmove(cxt->p + aligned_size, cxt->p, cxt->p_end - cxt->p); - /* check for overflow */ - if (p > cxt->pstr) { - cxt->overflow = 1; - return; - } + /* make sure the last bytes are zeroed */ + memset(cxt->p + aligned_size - (aligned_size % sizeof(u32)), 0, + (aligned_size % sizeof(u32))); memcpy(cxt->p, data, sz); - if ((sz & 3) != 0) - memset(cxt->p + sz, 0, 4 - (sz & 3)); - cxt->p = p; + + cxt->p += aligned_size; + cxt->p_end += aligned_size; } void ft_begin_node(struct ft_cxt *cxt, const char *name) @@ -73,10 +85,10 @@ static int lookup_string(struct ft_cxt *cxt, const char *name) { u8 *p; - p = cxt->pstr; - while (p < cxt->pstr_begin) { + p = cxt->p; + while (p < cxt->p_end) { if (strcmp(p, name) == 0) - return p - cxt->p_begin; + return p - cxt->p; p += strlen(p) + 1; } @@ -85,24 +97,13 @@ static int lookup_string(struct ft_cxt *cxt, const char *name) void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz) { - int len, off; - - if (cxt->overflow) - return; - - len = strlen(name) + 1; + int off = 0; off = lookup_string(cxt, name); if (off == -1) { - /* check if we have space */ - if (cxt->p + 12 + sz + len > cxt->pstr) { - cxt->overflow = 1; - return; - } - - cxt->pstr -= len; - memcpy(cxt->pstr, name, len); - off = cxt->pstr - cxt->p_begin; + memcpy(cxt->p_end, name, strlen(name) + 1); + off = cxt->p_end - cxt->p; + cxt->p_end += strlen(name) + 2; } /* now put offset from beginning of *STRUCTURE* */ @@ -122,138 +123,63 @@ void ft_prop_int(struct ft_cxt *cxt, const char *name, int val) { u32 v = cpu_to_be32((u32) val); - ft_prop(cxt, name, &v, 4); + ft_prop(cxt, name, &v, sizeof(u32)); } -/* start construction of the flat OF tree */ -void ft_begin(struct ft_cxt *cxt, void *blob, int max_size) +/* pick up and start working on a tree in place */ +void ft_init_cxt(struct ft_cxt *cxt, void *blob) { struct boot_param_header *bph = blob; - u32 off; - /* clear the cxt */ memset(cxt, 0, sizeof(*cxt)); cxt->bph = bph; - cxt->max_size = max_size; - - /* zero everything in the header area */ - memset(bph, 0, sizeof(*bph)); - - bph->magic = cpu_to_be32(OF_DT_HEADER); - bph->version = cpu_to_be32(0x10); - bph->last_comp_version = cpu_to_be32(0x10); + bph->boot_cpuid_phys = CONFIG_OF_BOOT_CPU; - /* start pointers */ - cxt->pres_begin = (u8 *) _ALIGN((unsigned long)(bph + 1), 8); - cxt->pres = cxt->pres_begin; - - off = (unsigned long)cxt->pres_begin - (unsigned long)bph; - bph->off_mem_rsvmap = cpu_to_be32(off); - - ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */ - ((u64 *) cxt->pres)[1] = 0; + /* find beginning and end of reserve map table (zeros in last entry) */ + cxt->p_rsvmap = (u8 *)bph + bph->off_mem_rsvmap; + while ( ((uint64_t *)cxt->p_rsvmap)[0] != 0 && + ((uint64_t *)cxt->p_rsvmap)[1] != 0 ) { + cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY; + } - cxt->p_anchor = cxt->pres + 16; /* over the terminator */ + cxt->p_start = (char*)bph + bph->off_dt_struct; + cxt->p_end = (char *)bph + bph->totalsize; + cxt->p = (char *)bph + bph->off_dt_strings; } /* add a reserver physical area to the rsvmap */ -void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size) +void ft_add_rsvmap(struct ft_cxt *cxt, u64 physstart, u64 physend) { - ((u64 *) cxt->pres)[0] = cpu_to_be64(physaddr); /* phys = 0, size = 0, terminate */ - ((u64 *) cxt->pres)[1] = cpu_to_be64(size); - - cxt->pres += 16; /* advance */ - - ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */ - ((u64 *) cxt->pres)[1] = 0; - - /* keep track of size */ - cxt->res_size = cxt->pres + 16 - cxt->pres_begin; - - cxt->p_anchor = cxt->pres + 16; /* over the terminator */ + memmove(cxt->p_rsvmap + SIZE_OF_RSVMAP_ENTRY, cxt->p_rsvmap, + cxt->p_end - cxt->p_rsvmap); + + ((u64 *)cxt->p_rsvmap)[0] = cpu_to_be64(physstart); + ((u64 *)cxt->p_rsvmap)[1] = cpu_to_be64(physend); + ((u64 *)cxt->p_rsvmap)[2] = 0; + ((u64 *)cxt->p_rsvmap)[3] = 0; + + cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY; + cxt->p_start += SIZE_OF_RSVMAP_ENTRY; + cxt->p += SIZE_OF_RSVMAP_ENTRY; + cxt->p_end += SIZE_OF_RSVMAP_ENTRY; } -void ft_begin_tree(struct ft_cxt *cxt) +void ft_end_tree(struct ft_cxt *cxt) { - cxt->p_begin = cxt->p_anchor; - cxt->pstr_begin = (char *)cxt->bph + cxt->max_size; /* point at the end */ - - cxt->p = cxt->p_begin; - cxt->pstr = cxt->pstr_begin; + ft_put_word(cxt, OF_DT_END); } -int ft_end_tree(struct ft_cxt *cxt) -{ +/* update the boot param header with correct values */ +void ft_finalize_tree(struct ft_cxt *cxt) { struct boot_param_header *bph = cxt->bph; - int off, sz, sz1; - u32 tag, v; - u8 *p; - - ft_put_word(cxt, OF_DT_END); - - if (cxt->overflow) - return -ENOMEM; - - /* size of the areas */ - cxt->struct_size = cxt->p - cxt->p_begin; - cxt->strings_size = cxt->pstr_begin - cxt->pstr; - - /* the offset we must move */ - off = (cxt->pstr_begin - cxt->p_begin) - cxt->strings_size; - - /* the new strings start */ - cxt->pstr_begin = cxt->p_begin + cxt->struct_size; - - /* move the whole string area */ - memmove(cxt->pstr_begin, cxt->pstr, cxt->strings_size); - /* now perform the fixup of the strings */ - p = cxt->p_begin; - while ((tag = be32_to_cpu(*(u32 *) p)) != OF_DT_END) { - p += 4; - - if (tag == OF_DT_BEGIN_NODE) { - p = (u8 *) _ALIGN((unsigned long)p + strlen(p) + 1, 4); - continue; - } - - if (tag == OF_DT_END_NODE || tag == OF_DT_NOP) - continue; - - if (tag != OF_DT_PROP) - return -EINVAL; - - sz = be32_to_cpu(*(u32 *) p); - p += 4; - - v = be32_to_cpu(*(u32 *) p); - v -= off; - *(u32 *) p = cpu_to_be32(v); /* move down */ - p += 4; - - p = (u8 *) _ALIGN((unsigned long)p + sz, 4); - } - - /* fix sizes */ - p = (char *)cxt->bph; - sz = (cxt->pstr_begin + cxt->strings_size) - p; - sz1 = _ALIGN(sz, 16); /* align at 16 bytes */ - if (sz != sz1) - memset(p + sz, 0, sz1 - sz); - bph->totalsize = cpu_to_be32(sz1); - bph->off_dt_struct = cpu_to_be32(cxt->p_begin - p); - bph->off_dt_strings = cpu_to_be32(cxt->pstr_begin - p); - - /* the new strings start */ - cxt->pstr_begin = cxt->p_begin + cxt->struct_size; - cxt->pstr = cxt->pstr_begin + cxt->strings_size; - - return 0; + bph->totalsize = cxt->p_end - (u8 *)bph; + bph->off_dt_struct = cxt->p_start - (u8 *)bph; + bph->off_dt_strings = cxt->p - (u8 *)bph; + bph->dt_strings_size = cxt->p_end - cxt->p; } -/**********************************************************************/ - static inline int isprint(int c) { return c >= 0x20 && c <= 0x7e; @@ -299,16 +225,16 @@ static void print_data(const void *data, int len) switch (len) { case 1: /* byte */ - printf(" = <0x%02x>", (*(u8 *) data) & 0xff); + printf(" = <%02x>", (*(u8 *) data) & 0xff); break; case 2: /* half-word */ - printf(" = <0x%04x>", be16_to_cpu(*(u16 *) data) & 0xffff); + printf(" = <%04x>", be16_to_cpu(*(u16 *) data) & 0xffff); break; case 4: /* word */ - printf(" = <0x%08x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU); + printf(" = <%x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU); break; case 8: /* double-word */ - printf(" = <0x%16llx>", be64_to_cpu(*(uint64_t *) data)); + printf(" = <%qx>", be64_to_cpu(*(uint64_t *) data)); break; default: /* anything else... hexdump */ printf(" = ["); @@ -350,7 +276,7 @@ void ft_dump_blob(const void *bphp) if (addr == 0 && size == 0) break; - printf("/memreserve/ 0x%llx 0x%llx;\n", addr, size); + printf("/memreserve/ %qx %qx;\n", addr, size); } p = p_struct; @@ -381,8 +307,8 @@ void ft_dump_blob(const void *bphp) } if (tag != OF_DT_PROP) { - fprintf(stderr, "%*s ** Unknown tag 0x%08x\n", - depth * shift, "", tag); + fprintf(stderr, "%*s ** Unknown tag 0x%08x at 0x%x\n", + depth * shift, "", tag, --p); break; } sz = be32_to_cpu(*p++); @@ -397,64 +323,15 @@ void ft_dump_blob(const void *bphp) void ft_backtrack_node(struct ft_cxt *cxt) { - if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE) - return; /* XXX only for node */ - - cxt->p -= 4; -} - -/* note that the root node of the blob is "peeled" off */ -void ft_merge_blob(struct ft_cxt *cxt, void *blob) -{ - struct boot_param_header *bph = (struct boot_param_header *)blob; - u32 *p_struct = (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_struct)); - u32 *p_strings = - (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_strings)); - u32 tag, *p; - char *s, *t; - int depth, sz; - - if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE) - return; /* XXX only for node */ - - cxt->p -= 4; - - depth = 0; - p = p_struct; - while ((tag = be32_to_cpu(*p++)) != OF_DT_END) { - - /* printf("tag: 0x%08x (%d) - %d\n", tag, p - p_struct, depth); */ - - if (tag == OF_DT_BEGIN_NODE) { - s = (char *)p; - p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4); - - if (depth++ > 0) - ft_begin_node(cxt, s); - - continue; - } - - if (tag == OF_DT_END_NODE) { - ft_end_node(cxt); - if (--depth == 0) - break; - continue; - } - - if (tag == OF_DT_NOP) - continue; + int i = 4; - if (tag != OF_DT_PROP) - break; + while (be32_to_cpu(*(u32 *) (cxt->p - i)) != OF_DT_END_NODE) + i += 4; - sz = be32_to_cpu(*p++); - s = (char *)p_strings + be32_to_cpu(*p++); - t = (char *)p; - p = (u32 *) _ALIGN((unsigned long)p + sz, 4); + memmove (cxt->p - i, cxt->p, cxt->p_end - cxt->p); - ft_prop(cxt, s, t, sz); - } + cxt->p_end -= i; + cxt->p -= i; } void *ft_get_prop(void *bphp, const char *propname, int *szp) @@ -521,9 +398,6 @@ void *ft_get_prop(void *bphp, const char *propname, int *szp) /********************************************************************/ -extern unsigned char oftree_dtb[]; -extern unsigned int oftree_dtb_len; - /* Function that returns a character from the environment */ extern uchar(*env_get_char) (int); @@ -577,7 +451,7 @@ static const struct { }; #endif -void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end) +void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end) { u32 *p; int len; @@ -600,20 +474,16 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_ return; } - ft_begin(&cxt, blob, size); +#ifdef DEBUG + printf ("recieved oftree\n"); + ft_dump_blob(blob); +#endif + + ft_init_cxt(&cxt, blob); if (initrd_start && initrd_end) ft_add_rsvmap(&cxt, initrd_start, initrd_end - initrd_start + 1); - ft_begin_tree(&cxt); - - ft_begin_node(&cxt, ""); - - ft_end_node(&cxt); - - /* copy RO tree */ - ft_merge_blob(&cxt, oftree_dtb); - /* back into root */ ft_backtrack_node(&cxt); @@ -642,8 +512,8 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_ #endif ft_begin_node(&cxt, "chosen"); - ft_prop_str(&cxt, "name", "chosen"); + ft_prop_str(&cxt, "bootargs", getenv("bootargs")); ft_prop_int(&cxt, "linux,platform", 0x600); /* what is this? */ if (initrd_start && initrd_end) { @@ -659,11 +529,7 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_ ft_end_node(&cxt); /* end root */ ft_end_tree(&cxt); - - /* - printf("merged OF-tree\n"); - ft_dump_blob(blob); - */ + ft_finalize_tree(&cxt); #ifdef CONFIG_OF_HAS_BD_T /* paste the bd_t at the end of the flat tree */ @@ -712,11 +578,12 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_ ft_board_setup(blob, bd); #endif - /* - printf("final OF-tree\n"); - ft_dump_blob(blob); - */ + /* in case the size changed in the platform code */ + ft_finalize_tree(&cxt); +#ifdef DEBUG + printf("final OF-tree\n"); + ft_dump_blob(blob); +#endif } - #endif diff --git a/include/ft_build.h b/include/ft_build.h index 47ca575d9fe..f5156879de3 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -36,19 +36,18 @@ struct boot_param_header { struct ft_cxt { struct boot_param_header *bph; - int max_size; /* maximum size of tree */ - int overflow; /* set when this happens */ - u8 *p, *pstr, *pres; /* running pointers */ - u8 *p_begin, *pstr_begin, *pres_begin; /* starting pointers */ - u8 *p_anchor; /* start of constructed area */ - int struct_size, strings_size, res_size; + u8 *p_rsvmap; + u8 *p_start; /* pointer to beginning of dt_struct */ + u8 *p_end; /* pointer to end of dt_strings */ + u8 *p; /* pointer to end of dt_struct and beginning of dt_strings */ }; void ft_begin_node(struct ft_cxt *cxt, const char *name); +void ft_init_cxt(struct ft_cxt *cxt, void *blob); void ft_end_node(struct ft_cxt *cxt); -void ft_begin_tree(struct ft_cxt *cxt); -int ft_end_tree(struct ft_cxt *cxt); +void ft_end_tree(struct ft_cxt *cxt); +void ft_finalize_tree(struct ft_cxt *cxt); void ft_nop(struct ft_cxt *cxt); void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz); @@ -57,12 +56,14 @@ void ft_prop_int(struct ft_cxt *cxt, const char *name, int val); void ft_begin(struct ft_cxt *cxt, void *blob, int max_size); void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size); -void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end); +void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end); void ft_dump_blob(const void *bphp); void ft_merge_blob(struct ft_cxt *cxt, void *blob); void *ft_get_prop(void *bphp, const char *propname, int *szp); +#ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup(void *blob, bd_t *bd); +#endif #endif -- cgit v1.3.1 From 40d5fa35d02df22580593bf0039ab173367e8ef0 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:43:36 -0500 Subject: * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards Patch by Jon Loeliger 17-Jan-2006 Signed-off-by: Jon Loeliger --- board/cds/common/ft_board.c | 46 +++++++++++++++++++++++++++++++++++++++ board/cds/mpc8541cds/Makefile | 3 ++- board/cds/mpc8548cds/Makefile | 3 ++- board/cds/mpc8555cds/Makefile | 3 ++- board/mpc8540ads/mpc8540ads.c | 24 +++++++++++++++++++++ board/mpc8560ads/mpc8560ads.c | 9 ++++++++ cpu/mpc85xx/cpu.c | 50 ++++++++++++++++++++++++++++++++++++++++++- cpu/mpc85xx/cpu_init.c | 1 + include/configs/MPC8540ADS.h | 15 +++++++++++++ include/configs/MPC8541CDS.h | 12 +++++++++++ include/configs/MPC8548CDS.h | 12 +++++++++++ include/configs/MPC8555CDS.h | 12 +++++++++++ include/configs/MPC8560ADS.h | 12 +++++++++++ 13 files changed, 198 insertions(+), 4 deletions(-) create mode 100644 board/cds/common/ft_board.c (limited to 'include') diff --git a/board/cds/common/ft_board.c b/board/cds/common/ft_board.c new file mode 100644 index 00000000000..73eca5e6944 --- /dev/null +++ b/board/cds/common/ft_board.c @@ -0,0 +1,46 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_OF_FLAT_TREE) +#include +extern void ft_cpu_setup(void *blob, bd_t *bd); +#endif + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff --git a/board/cds/mpc8541cds/Makefile b/board/cds/mpc8541cds/Makefile index 0d4abbd71d8..aea61360a5f 100644 --- a/board/cds/mpc8541cds/Makefile +++ b/board/cds/mpc8541cds/Makefile @@ -28,7 +28,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ - ../common/eeprom.o + ../common/eeprom.o \ + ../common/ft_board.o SOBJS := init.o diff --git a/board/cds/mpc8548cds/Makefile b/board/cds/mpc8548cds/Makefile index 0d4abbd71d8..aea61360a5f 100644 --- a/board/cds/mpc8548cds/Makefile +++ b/board/cds/mpc8548cds/Makefile @@ -28,7 +28,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ - ../common/eeprom.o + ../common/eeprom.o \ + ../common/ft_board.o SOBJS := init.o diff --git a/board/cds/mpc8555cds/Makefile b/board/cds/mpc8555cds/Makefile index 0d4abbd71d8..aea61360a5f 100644 --- a/board/cds/mpc8555cds/Makefile +++ b/board/cds/mpc8555cds/Makefile @@ -28,7 +28,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ - ../common/eeprom.o + ../common/eeprom.o \ + ../common/ft_board.o SOBJS := init.o diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c index d0eb6904ada..855888d2761 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/mpc8540ads/mpc8540ads.c @@ -31,6 +31,12 @@ #include #include +#if defined(CONFIG_OF_FLAT_TREE) +#include +extern void ft_cpu_setup(void *blob, bd_t *bd); +#endif + + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -342,3 +348,21 @@ pci_init_board(void) pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index 25f69a0bf5d..f9d75e80510 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -544,3 +544,12 @@ pci_init_board(void) pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index f7fe22e3e1e..0507c47e6e7 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -30,7 +30,10 @@ #include #include -/* ------------------------------------------------------------------------- */ +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif + int checkcpu (void) { @@ -227,3 +230,48 @@ int dma_xfer(void *dest, uint count, void *src) { return dma_check(); } #endif + + +#ifdef CONFIG_OF_FLAT_TREE +void +ft_cpu_setup(void *blob, bd_t *bd) +{ + u32 *p; + ulong clock; + int len; + + clock = bd->bi_busfreq; + p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + +#if defined(CONFIG_MPC85XX_TSEC1) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); + memcpy(p, bd->bi_enetaddr, 6); +#endif + +#if defined(CONFIG_HAS_ETH1) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); + memcpy(p, bd->bi_enet1addr, 6); +#endif + +#if defined(CONFIG_HAS_ETH2) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); + memcpy(p, bd->bi_enet2addr, 6); +#endif + +#if defined(CONFIG_HAS_ETH3) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); + memcpy(p, bd->bi_enet3addr, 6); +#endif + +} +#endif diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c12b47b589d..9f4d36c1ab4 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_CPM2 static void config_8560_ioports (volatile immap_t * immr) { diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 131c8322426..d31a18b7948 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -293,6 +293,21 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8540@0" +#define OF_SOC "soc8540@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index c96b98b54d3..86bcfe324c8 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -308,6 +308,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8541@0" +#define OF_SOC "soc8541@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4ca8bc35db1..b1f8a192dff 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -314,6 +314,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8548@0" +#define OF_SOC "soc8548@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index a44e3ec8453..b725dac52b6 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -308,6 +308,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8555@0" +#define OF_SOC "soc8555@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 2d5031b77d3..1c684f2fd10 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -290,6 +290,18 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8560@0" +#define OF_SOC "soc8560@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -- cgit v1.3.1 From b636aaeb6fd516a442fb611bbeeddf3077a687fb Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:44:49 -0500 Subject: * Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming --- include/pci.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/pci.h b/include/pci.h index 0fc00e42769..e0e8783a7aa 100644 --- a/include/pci.h +++ b/include/pci.h @@ -270,6 +270,15 @@ #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ #define PCI_AGP_SIZEOF 12 +/* PCI-X registers */ + +#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ +#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ +#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ +#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ + + /* Slot Identification */ #define PCI_SID_ESR 2 /* Expansion Slot Register */ -- cgit v1.3.1 From 087454609e47295443af793a282cddcd91a5f49c Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:45:17 -0500 Subject: * Added support for initializing second PCI bus on 85xx Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- cpu/mpc85xx/pci.c | 182 ++++++++++++++++++++++++++++++++++--------- include/asm-ppc/immap_85xx.h | 25 +++++- 2 files changed, 170 insertions(+), 37 deletions(-) (limited to 'include') diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index a94493e0802..ca11bce22ea 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -32,66 +32,90 @@ #if defined(CONFIG_PCI) +static struct pci_controller *pci_hose; + void -pci_mpc85xx_init(struct pci_controller *hose) +pci_mpc85xx_init(struct pci_controller *board_hose) { + u16 reg16; + u32 dev; + volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; volatile ccsr_pcix_t *pcix = &immap->im_pcix; + volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2; + volatile ccsr_gur_t *gur = &immap->im_gur; + struct pci_controller * hose; - u16 reg16; + pci_hose = board_hose; + + hose = &pci_hose[0]; hose->first_busno = 0; hose->last_busno = 0xff; - pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - pci_set_region(hose->regions + 1, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 2; - pci_setup_indirect(hose, (CFG_IMMR+0x8000), (CFG_IMMR+0x8004)); + /* + * Hose scan. + */ + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + + if (!(gur->pordevsr & PORDEVSR_PCI)) { + /* PCI-X init */ + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16); + } + pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; pcix->potear1 = 0x00000000; - pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff; pcix->powbear1 = 0x00000000; - pcix->powar1 = 0x8004401c; /* 512M MEM space */ + pcix->powar1 = (POWAR_EN | POWAR_MEM_READ | + POWAR_MEM_WRITE | POWAR_MEM_512M); - pcix->potar2 = 0x00000000; + pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; pcix->potear2 = 0x00000000; - pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff; pcix->powbear2 = 0x00000000; - pcix->powar2 = 0x80088017; /* 16M IO space */ + pcix->powar2 = (POWAR_EN | POWAR_IO_READ | + POWAR_IO_WRITE | POWAR_IO_1M); pcix->pitar1 = 0x00000000; pcix->piwbar1 = 0x00000000; - pcix->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, - * Snoop R/W, 2G */ + pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G); - /* - * Hose scan. - */ - pci_register_hose(hose); + pcix->powar3 = 0; + pcix->powar4 = 0; + pcix->piwar2 = 0; + pcix->piwar3 = 0; - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); - /* - * Clear non-reserved bits in status register. - */ - pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); + pci_set_region(hose->regions + 1, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 2; + + pci_register_hose(hose); #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS) /* @@ -117,6 +141,94 @@ pci_mpc85xx_init(struct pci_controller *hose) #endif hose->last_busno = pci_hose_scan(hose); + +#ifdef CONFIG_MPC85XX_PCI2 + hose = &pci_hose[1]; + + hose->first_busno = pci_hose[0].last_busno + 1; + hose->last_busno = 0xff; + + pci_setup_indirect(hose, + (CFG_IMMR+0x9000), + (CFG_IMMR+0x9004)); + + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + + pcix2->potar1 = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff; + pcix2->potear1 = 0x00000000; + pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff; + pcix2->powbear1 = 0x00000000; + pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ | + POWAR_MEM_WRITE | POWAR_MEM_512M); + + pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff; + pcix2->potear2 = 0x00000000; + pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff; + pcix2->powbear2 = 0x00000000; + pcix2->powar2 = (POWAR_EN | POWAR_IO_READ | + POWAR_IO_WRITE | POWAR_IO_1M); + + pcix2->pitar1 = 0x00000000; + pcix2->piwbar1 = 0x00000000; + pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G); + + pcix2->powar3 = 0; + pcix2->powar4 = 0; + pcix2->piwar2 = 0; + pcix2->piwar3 = 0; + + pci_set_region(hose->regions + 0, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, + PCI_REGION_MEM); + + pci_set_region(hose->regions + 1, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, + CFG_PCI2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 2; + + /* + * Hose scan. + */ + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); +#endif } +#ifdef CONFIG_OF_FLAT_TREE +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[0].first_busno; + p[1] = pci_hose[0].last_busno; + } + +#ifdef CONFIG_MPC85XX_PCI2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[1].first_busno; + p[1] = pci_hose[1].last_busno; + } +#endif +} +#endif /* CONFIG_OF_FLAT_TREE */ #endif /* CONFIG_PCI */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 2f10e9591d2..7a4345a7408 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -246,7 +246,6 @@ typedef struct ccsr_lbc { /* * PCI Registers(0x8000-0x9000) - * Omitting Reserved(0x9000-0x2_0000) */ typedef struct ccsr_pcix { uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */ @@ -309,9 +308,27 @@ typedef struct ccsr_pcix { uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */ uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */ uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */ - char res11[94688]; + uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */ + char res11[476]; } ccsr_pcix_t; +#define PCIX_COMMAND 0x62 +#define POWAR_EN 0x80000000 +#define POWAR_IO_READ 0x00080000 +#define POWAR_MEM_READ 0x00040000 +#define POWAR_IO_WRITE 0x00008000 +#define POWAR_MEM_WRITE 0x00004000 +#define POWAR_MEM_512M 0x0000001c +#define POWAR_IO_1M 0x00000013 + +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_LOCAL 0x00f00000 +#define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE_SNOOP 0x00005000 +#define PIWAR_MEM_2G 0x0000001e + + /* * L2 Cache Registers(0x2_0000-0x2_1000) */ @@ -1572,6 +1589,8 @@ typedef struct ccsr_gur { char res15[61651]; } ccsr_gur_t; +#define PORDEVSR_PCI (0x00800000) /* PCI Mode */ + typedef struct immap { ccsr_local_ecm_t im_local_ecm; ccsr_ddr_t im_ddr; @@ -1579,6 +1598,8 @@ typedef struct immap { ccsr_duart_t im_duart; ccsr_lbc_t im_lbc; ccsr_pcix_t im_pcix; + ccsr_pcix_t im_pcix2; + char reserved[90112]; ccsr_l2cache_t im_l2cache; ccsr_dma_t im_dma; ccsr_tsec_t im_tsec1; -- cgit v1.3.1 From 52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:45:41 -0500 Subject: * Fixed PCI memory definitions Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- board/mpc8540ads/mpc8540ads.c | 21 ++++----------------- include/configs/MPC8540ADS.h | 9 +++++---- 2 files changed, 9 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c index 855888d2761..fbcb397290a 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/mpc8540ads/mpc8540ads.c @@ -317,24 +317,8 @@ long int fixed_sdram (void) * Initialize PCI Devices, report devices found. */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxads_config_table, -#endif -}; +static struct pci_controller hose; #endif /* CONFIG_PCI */ @@ -357,6 +341,9 @@ ft_board_setup(void *blob, bd_t *bd) u32 *p; int len; +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif ft_cpu_setup(blob, bd); p = ft_get_prop(blob, "/memory/reg", &len); diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index d31a18b7948..81ee945d499 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -71,7 +71,7 @@ */ #ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33000000 +#define CONFIG_SYS_CLK_FREQ 66000000 #endif @@ -327,9 +327,10 @@ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#define CFG_PCI1_IO_BASE 0x0 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) -- cgit v1.3.1 From cbfc7ce756b88eb26e5537bc7b625c445c6dcfac Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:46:13 -0500 Subject: * Added VIA configuration table * Added support for PCI2 on CDS Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- board/cds/common/ft_board.c | 3 ++ board/cds/common/via.c | 99 +++++++++++++++++++++++++++++++++++++++ board/cds/common/via.h | 18 +++++++ board/cds/mpc8541cds/Makefile | 3 +- board/cds/mpc8541cds/init.S | 12 ++--- board/cds/mpc8541cds/mpc8541cds.c | 32 ++++++------- board/cds/mpc8548cds/Makefile | 3 +- board/cds/mpc8548cds/init.S | 12 ++--- board/cds/mpc8548cds/mpc8548cds.c | 32 ++++++------- board/cds/mpc8555cds/Makefile | 3 +- board/cds/mpc8555cds/init.S | 12 ++--- board/cds/mpc8555cds/mpc8555cds.c | 39 ++++++++------- include/configs/MPC8541CDS.h | 21 ++++----- include/configs/MPC8548CDS.h | 23 ++++----- include/configs/MPC8555CDS.h | 23 ++++----- 15 files changed, 223 insertions(+), 112 deletions(-) create mode 100644 board/cds/common/via.c create mode 100644 board/cds/common/via.h (limited to 'include') diff --git a/board/cds/common/ft_board.c b/board/cds/common/ft_board.c index 73eca5e6944..77d1d851d90 100644 --- a/board/cds/common/ft_board.c +++ b/board/cds/common/ft_board.c @@ -35,6 +35,9 @@ ft_board_setup(void *blob, bd_t *bd) u32 *p; int len; +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif ft_cpu_setup(blob, bd); p = ft_get_prop(blob, "/memory/reg", &len); diff --git a/board/cds/common/via.c b/board/cds/common/via.c new file mode 100644 index 00000000000..68c8d212f41 --- /dev/null +++ b/board/cds/common/via.c @@ -0,0 +1,99 @@ +/* + * Copyright 2006 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* Config the VIA chip */ +void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pci_dev_t bridge; + + /* Enable USB and IDE functions */ + pci_hose_write_config_byte(hose, dev, 0x48, 0x08); + + pciauto_config_device(hose, dev); + + /* + * Force the backplane P2P bridge to have a window + * open from 0x00000000-0x00001fff in PCI I/O space. + * This allows legacy I/O (i8259, etc) on the VIA + * southbridge to be accessed. + */ + bridge = PCI_BDF(0,17,0); + pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); + pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); + pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); + pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0); +} + +/* Function 1, IDE */ +void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + /* + * Since the P2P window was forced to cover the fixed + * legacy I/O addresses, it is necessary to manually + * place the base addresses for the IDE and USB functions + * within this window. + */ + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0); +} + +/* Function 2, USB ports 0-1 */ +void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0); +} + +/* Function 3, USB ports 2-3 */ +void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80); +} + +/* Function 5, Power Management */ +void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8); +} + +/* Function 6, AC97 Interface */ +void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00); +} + diff --git a/board/cds/common/via.h b/board/cds/common/via.h new file mode 100644 index 00000000000..77cfacc5261 --- /dev/null +++ b/board/cds/common/via.h @@ -0,0 +1,18 @@ +#ifndef _MPC85xx_VIA_H +void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 1, IDE */ +void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 2, USB ports 0-1 */ +void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 3, USB ports 2-3 */ +void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 5, Power Management */ +void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 6, AC97 Interface */ +void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); +#endif /* _MPC85xx_VIA_H */ diff --git a/board/cds/mpc8541cds/Makefile b/board/cds/mpc8541cds/Makefile index aea61360a5f..d202281d454 100644 --- a/board/cds/mpc8541cds/Makefile +++ b/board/cds/mpc8541cds/Makefile @@ -29,7 +29,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ ../common/eeprom.o \ - ../common/ft_board.o + ../common/ft_board.o \ + ../common/via.o SOBJS := init.o diff --git a/board/cds/mpc8541cds/init.S b/board/cds/mpc8541cds/init.S index 53dcd0d7624..978bda5e4dc 100644 --- a/board/cds/mpc8541cds/init.S +++ b/board/cds/mpc8541cds/init.S @@ -210,8 +210,8 @@ tlb1_entry: * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -234,11 +234,11 @@ tlb1_entry: #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index 6b8aa68f541..c2b3009fd2b 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -31,6 +31,7 @@ #include "../common/cadmus.h" #include "../common/eeprom.h" +#include "../common/via.h" #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -468,26 +469,25 @@ testdram(void) #endif #if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it. */ +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } -#ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}}, + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}} }; -#endif -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxcds_config_table, +static struct pci_controller hose[] = { + { config_table: pci_mpc85xxcds_config_table,}, +#ifdef CONFIG_MPC85XX_PCI2 + {}, #endif }; @@ -497,7 +497,7 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); + extern void pci_mpc85xx_init(struct pci_controller **hose); pci_mpc85xx_init(&hose); #endif diff --git a/board/cds/mpc8548cds/Makefile b/board/cds/mpc8548cds/Makefile index aea61360a5f..d202281d454 100644 --- a/board/cds/mpc8548cds/Makefile +++ b/board/cds/mpc8548cds/Makefile @@ -29,7 +29,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ ../common/eeprom.o \ - ../common/ft_board.o + ../common/ft_board.o \ + ../common/via.o SOBJS := init.o diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S index 53dcd0d7624..978bda5e4dc 100644 --- a/board/cds/mpc8548cds/init.S +++ b/board/cds/mpc8548cds/init.S @@ -210,8 +210,8 @@ tlb1_entry: * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -234,11 +234,11 @@ tlb1_entry: #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 5bc08900a47..6eedb4a2095 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -30,6 +30,7 @@ #include "../common/cadmus.h" #include "../common/eeprom.h" +#include "../common/via.h" #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -293,26 +294,25 @@ testdram(void) #endif #if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it. */ +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } -#ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}}, + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}} }; -#endif -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxcds_config_table, +static struct pci_controller hose[] = { + { config_table: pci_mpc85xxcds_config_table,}, +#ifdef CONFIG_MPC85XX_PCI2 + {}, #endif }; @@ -322,7 +322,7 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); + extern void pci_mpc85xx_init(struct pci_controller **hose); pci_mpc85xx_init(&hose); #endif diff --git a/board/cds/mpc8555cds/Makefile b/board/cds/mpc8555cds/Makefile index aea61360a5f..d202281d454 100644 --- a/board/cds/mpc8555cds/Makefile +++ b/board/cds/mpc8555cds/Makefile @@ -29,7 +29,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ ../common/eeprom.o \ - ../common/ft_board.o + ../common/ft_board.o \ + ../common/via.o SOBJS := init.o diff --git a/board/cds/mpc8555cds/init.S b/board/cds/mpc8555cds/init.S index 53dcd0d7624..978bda5e4dc 100644 --- a/board/cds/mpc8555cds/init.S +++ b/board/cds/mpc8555cds/init.S @@ -210,8 +210,8 @@ tlb1_entry: * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -234,11 +234,11 @@ tlb1_entry: #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index 18adf5b9e6f..e15bf8f2ca3 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -29,6 +29,7 @@ #include "../common/cadmus.h" #include "../common/eeprom.h" +#include "../common/via.h" #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -464,38 +465,40 @@ testdram(void) } #endif -#if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. +#ifdef CONFIG_PCI +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it */ +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } -#ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}}, + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}} }; -#endif -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP + +static struct pci_controller hose[] = { + { config_table: pci_mpc85xxcds_config_table, + }, +#ifdef CONFIG_MPC85XX_PCI2 + { } #endif }; -#endif /* CONFIG_PCI */ +#endif void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); + extern void pci_mpc85xx_init(struct pci_controller **hose); - pci_mpc85xx_init(&hose); + pci_mpc85xx_init(*pci_hose); #endif } diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 86bcfe324c8..f73caf0319c 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8541@0" #define OF_SOC "soc8541@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -335,32 +335,27 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) +#define CONFIG_MPC85XX_PCI2 #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b1f8a192dff..37b518cca50 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -324,7 +324,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8548@0" #define OF_SOC "soc8548@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -341,32 +341,27 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_85XX_PCI2 #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ @@ -386,7 +381,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#define CONFIG_MPC85XX_TSEC4 1 +#undef CONFIG_MPC85XX_TSEC4 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index b725dac52b6..b94e38ae347 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8555@0" #define OF_SOC "soc8555@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -335,33 +335,28 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_MPC85XX_PCI2 #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ -- cgit v1.3.1 From 38433ccc5850ee70549af0b2bc5b920355ef5388 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:47:03 -0500 Subject: * Switched default PCI speed for 8540 ADS back to 33MHz * Added comments and a printf to warn that PCI-X won't work at 33MHz Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- cpu/mpc85xx/pci.c | 3 +++ doc/README.mpc85xxads | 3 +++ include/configs/MPC8540ADS.h | 6 +++++- 3 files changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index ca11bce22ea..cfb7dcdc895 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -72,6 +72,9 @@ pci_mpc85xx_init(struct pci_controller *board_hose) if (!(gur->pordevsr & PORDEVSR_PCI)) { /* PCI-X init */ + if (CONFIG_SYS_CLK_FREQ < 66000000) + printf("PCI-X will only work at 66 MHz\n"); + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16); diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index f0cf782a8fc..ae8202bdd17 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -100,6 +100,9 @@ Updated 13-July-2004 Jon Loeliger SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock + In order to use PCI-X (only in the first PCI slot. The one with + the RIO connector), you need to set SW1[4] (config) to 1 (off). + Also, configure the board to run PCI at 66 MHz. 2. MEMORY MAP TO WORK WITH LINUX KERNEL diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 81ee945d499..8e4d2c95a44 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -68,10 +68,14 @@ * The board, however, can run at 66MHz. In any event, this value * must match the settings of some switches. Details can be found * in the README.mpc85xxads. + * + * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to + * 33MHz to accommodate, based on a PCI pin. + * Note that PCI-X won't work at 33MHz. */ #ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_SYS_CLK_FREQ 33000000 #endif -- cgit v1.3.1 From fcb28e763415e0e4e66b0f45842d1557ae198e5e Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong Date: Thu, 13 Jul 2006 10:35:10 -0500 Subject: Fixed initrd issue by define big RAM Signed-off-by:Jason Jin --- common/cmd_bootm.c | 1 - include/configs/MPC8641HPCN.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index a78a16df9cb..e5d70fa202a 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -538,7 +538,6 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, initrd_copy_to_ram = 0; } else { /* not set, no restrictions to load high */ initrd_high = ~0; - initrd_copy_to_ram = 0; } #ifdef CONFIG_LOGBUFFER diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index b0897695a7c..aca2ecc2341 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -100,6 +100,7 @@ */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM #define MPC86xx_DDR_SDRAM_CLK_CNTL -- cgit v1.3.1 From bea3f28d285942bf3f7ab339ce85178ded544225 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 12 Jul 2006 10:48:05 -0400 Subject: Add support for reading and writing mac addresses to or from ID EEPROM. Added code for reading and writing Mac addresses to/from ID EEPROM(0x57). With attached patch, we can use command "mac/mac read/mac save/" to read and write EEPROM under u-boot prompt. U-boot will calculate the checksum of EEPROM while bootup, if it is right, then u-boot will check whether the mac address of eTSEC0/1/2/3 is availalbe (non-zero). If there is mac address availabe in EEPROM, u-boot will use it, otherewise, u-boot will use the mac address defined in MPC8641HPCN.h. This matches the requirement to set unique mac address for each TSEC port. Signed-off-by: Haiying Wang Signed-off-by: York Sun --- board/mpc8641hpcn/Makefile | 2 +- board/mpc8641hpcn/sys_eeprom.c | 244 +++++++++++++++++++++++++++++++++++++++++ common/Makefile | 2 +- common/cmd_mac.c | 66 +++++++++++ include/common.h | 3 + include/configs/MPC8641HPCN.h | 2 + lib_ppc/board.c | 4 + 7 files changed, 321 insertions(+), 2 deletions(-) create mode 100644 board/mpc8641hpcn/sys_eeprom.c create mode 100644 common/cmd_mac.c (limited to 'include') diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index 060db84efd2..0ebed87bce8 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := $(BOARD).o pixis.o oftree.o +OBJS := $(BOARD).o pixis.o sys_eeprom.o oftree.o SOBJS := init.o $(LIB): $(OBJS) $(SOBJS) diff --git a/board/mpc8641hpcn/sys_eeprom.c b/board/mpc8641hpcn/sys_eeprom.c new file mode 100644 index 00000000000..733a57f93f7 --- /dev/null +++ b/board/mpc8641hpcn/sys_eeprom.c @@ -0,0 +1,244 @@ +/* + * Copyright 2006 Freescale Semiconductor + * York Sun (yorksun@freescale.com) + * Haiying Wang (haiying.wang@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef CFG_ID_EEPROM +typedef struct { + unsigned char id[4]; /* 0x0000 - 0x0003 */ + unsigned char sn[12]; /* 0x0004 - 0x000F */ + unsigned char errata[5];/* 0x0010 - 0x0014 */ + unsigned char date[7]; /* 0x0015 - 0x001a */ + unsigned char res_1[37];/* 0x001b - 0x003f */ + unsigned char tab_size; /* 0x0040 */ + unsigned char tab_flag; /* 0x0041 */ + unsigned char mac[8][6];/* 0x0042 - 0x0071 */ + unsigned char res_2[126];/* 0x0072 - 0x00ef */ + unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */ +} EEPROM_data; + +static EEPROM_data mac_data; + +int mac_show(void) +{ + int i; + unsigned char ethaddr[8][18]; + + printf("ID %c%c%c%c\n", mac_data.id[0],\ + mac_data.id[1],\ + mac_data.id[2],\ + mac_data.id[3]); + printf("Errata %c%c%c%c%c\n", mac_data.errata[0],\ + mac_data.errata[1],\ + mac_data.errata[2],\ + mac_data.errata[3],\ + mac_data.errata[4]); + printf("Date %c%c%c%c%c%c%c\n", mac_data.date[0],\ + mac_data.date[1],\ + mac_data.date[2],\ + mac_data.date[3],\ + mac_data.date[4],\ + mac_data.date[5],\ + mac_data.date[6]); + for (i = 0; i < 8; i++) { + sprintf(ethaddr[i],"%02x:%02x:%02x:%02x:%02x:%02x",\ + mac_data.mac[i][0],\ + mac_data.mac[i][1],\ + mac_data.mac[i][2],\ + mac_data.mac[i][3],\ + mac_data.mac[i][4],\ + mac_data.mac[i][5]); + printf("MAC %d %s\n", i, ethaddr[i]); + } + + setenv("ethaddr", ethaddr[0]); + setenv("eth1addr", ethaddr[1]); + setenv("eth2addr", ethaddr[2]); + setenv("eth3addr", ethaddr[3]); + + return 0; +} + +int mac_read(void) +{ + int ret,length; + unsigned int crc = 0; + unsigned char dev = ID_EEPROM_ADDR, *data; + + length = sizeof(EEPROM_data); + ret = i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length); + if (ret) { + printf("Read failed.\n"); + return -1; + } + + data = (unsigned char *)(&mac_data); + printf("Check CRC on reading ..."); + crc = crc32(crc, data, length-4); + if (crc != mac_data.crc) { + printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n",mac_data.crc,crc); + return -1; + } + else { + printf("CRC OK\n"); + mac_show(); + } + return 0; +} + +int mac_prog(void) +{ + int ret, i, length; + unsigned int crc = 0; + unsigned char dev = ID_EEPROM_ADDR,*ptr; + unsigned char * eeprom_data = (unsigned char *)(&mac_data); + + for (i = 0; i < sizeof(mac_data.res_1); i++) + mac_data.res_1[i] = 0; + for (i = 0;i < sizeof(mac_data.res_2); i++) + mac_data.res_2[i] = 0; + length = sizeof(EEPROM_data); + crc = crc32 (crc, eeprom_data, length-4); + mac_data.crc = crc; + for (i = 0, ptr = eeprom_data; i < length; i += 8, ptr += 8) { + ret = i2c_write(dev, i, 1, ptr, (length-i) <8 ? (length-i) : 8); + udelay(5000); /* 5ms write cycle timing */ + if (ret) + break; + } + if (ret) { + printf("Programming failed.\n"); + return -1; + } + else { + printf("Programming %d bytes. Reading back ...\n",length); + mac_read(); + } + return 0; +} + +int do_mac (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + char cmd = 's'; + unsigned long long mac_val; + + if(i2c_probe(ID_EEPROM_ADDR) != 0) + return -1; + + if(argc>1) { + cmd = argv[1][0]; + switch (cmd) { + case 'r': /* display */ + mac_read(); + break; + case 's': /* save */ + mac_prog(); + break; + case 'i': /* id */ + for (i=0; i<4; i++) { + mac_data.id[i] = argv[2][i]; + } + break; + case 'n': /* serial number */ + for (i=0; i<12; i++) { + mac_data.sn[i] = argv[2][i]; + } + break; + case 'e': /* errata */ + for (i=0; i<5; i++) { + mac_data.errata[i] = argv[2][i]; + } + break; + case 'd': /* date */ + for (i=0; i<7; i++) { + mac_data.date[i] = argv[2][i]; + } + break; + case 'p': /* number of ports */ + mac_data.tab_size = (unsigned char)simple_strtoul(argv[2],NULL,16); + break; + case '0': /* mac 0 */ + case '1': /* mac 1 */ + case '2': /* mac 2 */ + case '3': /* mac 3 */ + case '4': /* mac 4 */ + case '5': /* mac 5 */ + case '6': /* mac 6 */ + case '7': /* mac 7 */ + mac_val = simple_strtoull(argv[2],NULL,16); + for (i=0; i<6; i++) { + mac_data.mac[cmd-'0'][i] = *((unsigned char *)(((unsigned int)(&mac_val))+i+2)); + } + break; + case 'h': /* help */ + default: + printf ("Usage:\n%s\n", cmdtp->usage); + break; + } + } + else { + mac_show(); + } + return 0; +} + +int mac_read_from_eeprom(void) +{ + int length,i; + unsigned char dev = ID_EEPROM_ADDR, *data, ethaddr[4][18], enetvar[32]; + unsigned int crc = 0; + + length = sizeof(EEPROM_data); + if(i2c_read (dev, 0, 1, (unsigned char *)(&mac_data), length)) { + printf("Read failed.\n"); + return -1; + } + + data = (unsigned char *)(&mac_data); + crc = crc32(crc, data, length-4); + if (crc != mac_data.crc) { + return -1; + } + else { + for(i=0; i<4; i++) { + if(memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) { + sprintf(ethaddr[i], "%02x:%02x:%02x:%02x:%02x:%02x", \ + mac_data.mac[i][0], \ + mac_data.mac[i][1], \ + mac_data.mac[i][2], \ + mac_data.mac[i][3], \ + mac_data.mac[i][4], \ + mac_data.mac[i][5]); + sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); + setenv(enetvar, ethaddr[i]); + } + } + } + return 0; +} +#endif /* CFG_ID_EEPROM */ diff --git a/common/Makefile b/common/Makefile index eb0b5dadfec..a62bc16e85d 100644 --- a/common/Makefile +++ b/common/Makefile @@ -51,7 +51,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \ memsize.o miiphybb.o miiphyutil.o \ s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \ usb.o usb_kbd.o usb_storage.o \ - virtex2.o xilinx.o crc16.o xyzModem.o + virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o OBJS = $(AOBJS) $(COBJS) diff --git a/common/cmd_mac.c b/common/cmd_mac.c new file mode 100644 index 00000000000..0add43285f3 --- /dev/null +++ b/common/cmd_mac.c @@ -0,0 +1,66 @@ +/* + * Copyright 2006 Freescale Semiconductor + * York Sun (yorksun@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CFG_ID_EEPROM + +extern int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +U_BOOT_CMD( + mac, 3, 1, do_mac, + "mac - display and program the system ID and MAC addresses in EEPROM\n", + "[read|save|id|num|errata|date|ports|0|1|2|3|4|5|6|7]\n" + "read\n" + " - show content of mac\n" + "mac save\n" + " - save to the EEPROM\n" + "mac id\n" + " - program system id\n" + "mac num\n" + " - program system serial number\n" + "mac errata\n" + " - program errata data\n" + "mac date\n" + " - program data date\n" + "mac ports\n" + " - program the number of ports\n" + "mac 0\n" + " - program the MAC address for port 0\n" + "mac 1\n" + " - program the MAC address for port 1\n" + "mac 2\n" + " - program the MAC address for port 2\n" + "mac 3\n" + " - program the MAC address for port 3\n" + "mac 4\n" + " - program the MAC address for port 4\n" + "mac 5\n" + " - program the MAC address for port 5\n" + "mac 6\n" + " - program the MAC address for port 6\n" + "mac 7\n" + " - program the MAC address for port 7\n" +); +#endif /* CFG_ID_EEPROM */ diff --git a/include/common.h b/include/common.h index 83ccf7c9877..7e54da93bfd 100644 --- a/include/common.h +++ b/include/common.h @@ -197,6 +197,9 @@ int checkdram (void); char * strmhz(char *buf, long hz); int last_stage_init(void); extern ulong monitor_flash_len; +#ifdef CFG_ID_EEPROM +int mac_read_from_eeprom(void); +#endif /* common/flash.c */ void flash_perror (int); diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index aca2ecc2341..7e91e644b1d 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -146,6 +146,8 @@ #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ #endif +#define CFG_ID_EEPROM 1 +#define ID_EEPROM_ADDR 0x57 /* * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. diff --git a/lib_ppc/board.c b/lib_ppc/board.c index c367b3ef9f2..2c29f467ec5 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -862,6 +862,10 @@ void board_init_r (gd_t *id, ulong dest_addr) } #endif +#ifdef CFG_ID_EEPROM + mac_read_from_eeprom(); +#endif + #if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \ defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) load_sernum_ethaddr (); -- cgit v1.3.1 From 515ab8a62e8574e2babc6e8dcc43544ad221c5b2 Mon Sep 17 00:00:00 2001 From: John Traill Date: Fri, 28 Jul 2006 08:16:06 +0100 Subject: Fix 8641HPCN timebase --- include/configs/MPC8641HPCN.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 7e91e644b1d..15e987139ad 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -268,7 +268,7 @@ #define OF_CPU "PowerPC,8641@0" #define OF_SOC "soc8641@f8000000" -#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" #define CFG_64BIT_VSPRINTF 1 -- cgit v1.3.1 From 4f92ed5fc083631ac7aef6c027cdf1177befd204 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 7 Aug 2006 14:33:32 +0200 Subject: Add commandline history support to all AMCC eval boards Patch by Stefan Roese, 07 Aug 2006 --- CHANGELOG | 3 +++ include/configs/bamboo.h | 14 ++++++-------- include/configs/bubinga.h | 3 ++- include/configs/ebony.h | 12 ++++++++++-- include/configs/luan.h | 14 ++++++++++++++ include/configs/ocotea.h | 19 +++++++++++++------ include/configs/walnut.h | 21 +++++++++++++++------ include/configs/yellowstone.h | 7 +++++++ include/configs/yosemite.h | 7 +++++++ include/configs/yucca.h | 9 +++++++++ 10 files changed, 86 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 21dd6574013..5ef76d22062 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add commandline history support to all AMCC eval boards + Patch by Stefan Roese, 07 Aug 2006 + * Add Macronix MXLV320T flash support for AMCC Bamboo Patch by Stefan Roese, 07 Aug 2006 diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 2c1c31927c1..cd4339b5822 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -310,11 +310,11 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ - CFG_CMD_EEPROM | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -358,13 +358,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_CMDLINE_EDITING - -#ifdef CONFIG_CMDLINE_EDITING -#undef CONFIG_AUTO_COMPLETE -#else -#define CONFIG_AUTO_COMPLETE -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 4a79835d6ac..a66cdc39567 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -200,8 +200,9 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index a26af6952ef..d8882ea31c5 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -143,7 +143,13 @@ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ @@ -205,6 +211,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -243,8 +250,9 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ diff --git a/include/configs/luan.h b/include/configs/luan.h index 0335a009858..0350e91f0fb 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -145,6 +145,13 @@ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" @@ -215,6 +222,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -253,6 +261,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index a13d6a870ab..89e9164e036 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -158,7 +158,13 @@ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ @@ -219,6 +225,9 @@ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_RESET_DELAY 1000 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ @@ -226,6 +235,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -264,15 +274,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/walnut.h b/include/configs/walnut.h index 1171ee5ae51..28abd6e1533 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -90,6 +90,11 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* needed for NetConsole */ + #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ @@ -97,6 +102,7 @@ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ @@ -156,16 +162,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* needed for NetConsole */ - /*----------------------------------------------------------------------- * I2C stuff *----------------------------------------------------------------------- @@ -175,6 +177,13 @@ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h index 7d555665ec8..cf42b666b00 100644 --- a/include/configs/yellowstone.h +++ b/include/configs/yellowstone.h @@ -229,6 +229,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -265,6 +266,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index a81cf34f11d..86a85b8a6d3 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -231,6 +231,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -272,6 +273,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 0e58e7e1024..f027d72d65e 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -220,6 +220,9 @@ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* needed for NetConsole */ + #undef CONFIG_WATCHDOG /* watchdog disabled */ /* @@ -245,6 +248,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -- cgit v1.3.1 From 5498d90312aad9f6bdbf047986027c35b03cd163 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:42:24 -0500 Subject: * Patch to modify ft_build.c to update flat device trees in place Patch by Matthew McClintock 26-June-2006 --- common/cmd_bootm.c | 2 +- common/ft_build.c | 341 ++++++++++++++++------------------------------------- include/ft_build.h | 19 +-- 3 files changed, 115 insertions(+), 247 deletions(-) (limited to 'include') diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index a472a1d7b25..f1c0eb4d183 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -836,7 +836,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); #else - ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd, initrd_start, initrd_end); + ft_setup(of_flat_tree, kbd, initrd_start, initrd_end); /* ft_dump_blob(of_flat_tree); */ #if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) diff --git a/common/ft_build.c b/common/ft_build.c index 9e9c906fc1f..b5a997c1ba5 100644 --- a/common/ft_build.c +++ b/common/ft_build.c @@ -1,5 +1,22 @@ /* * OF flat tree builder + * Written by: Pantelis Antoniou + * Updated by: Matthew McClintock + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #include @@ -13,44 +30,39 @@ #include +#undef DEBUG + /* align addr on a size boundary - adjust address up if needed -- Cort */ #define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1))) +#ifndef CONFIG_OF_BOOT_CPU +#define CONFIG_OF_BOOT_CPU 0 +#endif +#define SIZE_OF_RSVMAP_ENTRY (2*sizeof(u64)) static void ft_put_word(struct ft_cxt *cxt, u32 v) { - if (cxt->overflow) /* do nothing */ - return; - - /* check for overflow */ - if (cxt->p + 4 > cxt->pstr) { - cxt->overflow = 1; - return; - } + memmove(cxt->p + sizeof(u32), cxt->p, cxt->p_end - cxt->p); *(u32 *) cxt->p = cpu_to_be32(v); - cxt->p += 4; + cxt->p += sizeof(u32); + cxt->p_end += sizeof(u32); } static inline void ft_put_bin(struct ft_cxt *cxt, const void *data, int sz) { - u8 *p; + int aligned_size = ((u8 *)_ALIGN((unsigned long)cxt->p + sz, + sizeof(u32))) - cxt->p; - if (cxt->overflow) /* do nothing */ - return; - - /* next pointer pos */ - p = (u8 *) _ALIGN((unsigned long)cxt->p + sz, 4); + memmove(cxt->p + aligned_size, cxt->p, cxt->p_end - cxt->p); - /* check for overflow */ - if (p > cxt->pstr) { - cxt->overflow = 1; - return; - } + /* make sure the last bytes are zeroed */ + memset(cxt->p + aligned_size - (aligned_size % sizeof(u32)), 0, + (aligned_size % sizeof(u32))); memcpy(cxt->p, data, sz); - if ((sz & 3) != 0) - memset(cxt->p + sz, 0, 4 - (sz & 3)); - cxt->p = p; + + cxt->p += aligned_size; + cxt->p_end += aligned_size; } void ft_begin_node(struct ft_cxt *cxt, const char *name) @@ -73,10 +85,10 @@ static int lookup_string(struct ft_cxt *cxt, const char *name) { u8 *p; - p = cxt->pstr; - while (p < cxt->pstr_begin) { + p = cxt->p; + while (p < cxt->p_end) { if (strcmp(p, name) == 0) - return p - cxt->p_begin; + return p - cxt->p; p += strlen(p) + 1; } @@ -85,24 +97,13 @@ static int lookup_string(struct ft_cxt *cxt, const char *name) void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz) { - int len, off; - - if (cxt->overflow) - return; - - len = strlen(name) + 1; + int off = 0; off = lookup_string(cxt, name); if (off == -1) { - /* check if we have space */ - if (cxt->p + 12 + sz + len > cxt->pstr) { - cxt->overflow = 1; - return; - } - - cxt->pstr -= len; - memcpy(cxt->pstr, name, len); - off = cxt->pstr - cxt->p_begin; + memcpy(cxt->p_end, name, strlen(name) + 1); + off = cxt->p_end - cxt->p; + cxt->p_end += strlen(name) + 2; } /* now put offset from beginning of *STRUCTURE* */ @@ -122,138 +123,63 @@ void ft_prop_int(struct ft_cxt *cxt, const char *name, int val) { u32 v = cpu_to_be32((u32) val); - ft_prop(cxt, name, &v, 4); + ft_prop(cxt, name, &v, sizeof(u32)); } -/* start construction of the flat OF tree */ -void ft_begin(struct ft_cxt *cxt, void *blob, int max_size) +/* pick up and start working on a tree in place */ +void ft_init_cxt(struct ft_cxt *cxt, void *blob) { struct boot_param_header *bph = blob; - u32 off; - /* clear the cxt */ memset(cxt, 0, sizeof(*cxt)); cxt->bph = bph; - cxt->max_size = max_size; - - /* zero everything in the header area */ - memset(bph, 0, sizeof(*bph)); - - bph->magic = cpu_to_be32(OF_DT_HEADER); - bph->version = cpu_to_be32(0x10); - bph->last_comp_version = cpu_to_be32(0x10); + bph->boot_cpuid_phys = CONFIG_OF_BOOT_CPU; - /* start pointers */ - cxt->pres_begin = (u8 *) _ALIGN((unsigned long)(bph + 1), 8); - cxt->pres = cxt->pres_begin; - - off = (unsigned long)cxt->pres_begin - (unsigned long)bph; - bph->off_mem_rsvmap = cpu_to_be32(off); - - ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */ - ((u64 *) cxt->pres)[1] = 0; + /* find beginning and end of reserve map table (zeros in last entry) */ + cxt->p_rsvmap = (u8 *)bph + bph->off_mem_rsvmap; + while ( ((uint64_t *)cxt->p_rsvmap)[0] != 0 && + ((uint64_t *)cxt->p_rsvmap)[1] != 0 ) { + cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY; + } - cxt->p_anchor = cxt->pres + 16; /* over the terminator */ + cxt->p_start = (char*)bph + bph->off_dt_struct; + cxt->p_end = (char *)bph + bph->totalsize; + cxt->p = (char *)bph + bph->off_dt_strings; } /* add a reserver physical area to the rsvmap */ -void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size) +void ft_add_rsvmap(struct ft_cxt *cxt, u64 physstart, u64 physend) { - ((u64 *) cxt->pres)[0] = cpu_to_be64(physaddr); /* phys = 0, size = 0, terminate */ - ((u64 *) cxt->pres)[1] = cpu_to_be64(size); - - cxt->pres += 16; /* advance */ - - ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */ - ((u64 *) cxt->pres)[1] = 0; - - /* keep track of size */ - cxt->res_size = cxt->pres + 16 - cxt->pres_begin; - - cxt->p_anchor = cxt->pres + 16; /* over the terminator */ + memmove(cxt->p_rsvmap + SIZE_OF_RSVMAP_ENTRY, cxt->p_rsvmap, + cxt->p_end - cxt->p_rsvmap); + + ((u64 *)cxt->p_rsvmap)[0] = cpu_to_be64(physstart); + ((u64 *)cxt->p_rsvmap)[1] = cpu_to_be64(physend); + ((u64 *)cxt->p_rsvmap)[2] = 0; + ((u64 *)cxt->p_rsvmap)[3] = 0; + + cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY; + cxt->p_start += SIZE_OF_RSVMAP_ENTRY; + cxt->p += SIZE_OF_RSVMAP_ENTRY; + cxt->p_end += SIZE_OF_RSVMAP_ENTRY; } -void ft_begin_tree(struct ft_cxt *cxt) +void ft_end_tree(struct ft_cxt *cxt) { - cxt->p_begin = cxt->p_anchor; - cxt->pstr_begin = (char *)cxt->bph + cxt->max_size; /* point at the end */ - - cxt->p = cxt->p_begin; - cxt->pstr = cxt->pstr_begin; + ft_put_word(cxt, OF_DT_END); } -int ft_end_tree(struct ft_cxt *cxt) -{ +/* update the boot param header with correct values */ +void ft_finalize_tree(struct ft_cxt *cxt) { struct boot_param_header *bph = cxt->bph; - int off, sz, sz1; - u32 tag, v; - u8 *p; - - ft_put_word(cxt, OF_DT_END); - - if (cxt->overflow) - return -ENOMEM; - - /* size of the areas */ - cxt->struct_size = cxt->p - cxt->p_begin; - cxt->strings_size = cxt->pstr_begin - cxt->pstr; - - /* the offset we must move */ - off = (cxt->pstr_begin - cxt->p_begin) - cxt->strings_size; - - /* the new strings start */ - cxt->pstr_begin = cxt->p_begin + cxt->struct_size; - - /* move the whole string area */ - memmove(cxt->pstr_begin, cxt->pstr, cxt->strings_size); - /* now perform the fixup of the strings */ - p = cxt->p_begin; - while ((tag = be32_to_cpu(*(u32 *) p)) != OF_DT_END) { - p += 4; - - if (tag == OF_DT_BEGIN_NODE) { - p = (u8 *) _ALIGN((unsigned long)p + strlen(p) + 1, 4); - continue; - } - - if (tag == OF_DT_END_NODE || tag == OF_DT_NOP) - continue; - - if (tag != OF_DT_PROP) - return -EINVAL; - - sz = be32_to_cpu(*(u32 *) p); - p += 4; - - v = be32_to_cpu(*(u32 *) p); - v -= off; - *(u32 *) p = cpu_to_be32(v); /* move down */ - p += 4; - - p = (u8 *) _ALIGN((unsigned long)p + sz, 4); - } - - /* fix sizes */ - p = (char *)cxt->bph; - sz = (cxt->pstr_begin + cxt->strings_size) - p; - sz1 = _ALIGN(sz, 16); /* align at 16 bytes */ - if (sz != sz1) - memset(p + sz, 0, sz1 - sz); - bph->totalsize = cpu_to_be32(sz1); - bph->off_dt_struct = cpu_to_be32(cxt->p_begin - p); - bph->off_dt_strings = cpu_to_be32(cxt->pstr_begin - p); - - /* the new strings start */ - cxt->pstr_begin = cxt->p_begin + cxt->struct_size; - cxt->pstr = cxt->pstr_begin + cxt->strings_size; - - return 0; + bph->totalsize = cxt->p_end - (u8 *)bph; + bph->off_dt_struct = cxt->p_start - (u8 *)bph; + bph->off_dt_strings = cxt->p - (u8 *)bph; + bph->dt_strings_size = cxt->p_end - cxt->p; } -/**********************************************************************/ - static inline int isprint(int c) { return c >= 0x20 && c <= 0x7e; @@ -299,16 +225,16 @@ static void print_data(const void *data, int len) switch (len) { case 1: /* byte */ - printf(" = <0x%02x>", (*(u8 *) data) & 0xff); + printf(" = <%02x>", (*(u8 *) data) & 0xff); break; case 2: /* half-word */ - printf(" = <0x%04x>", be16_to_cpu(*(u16 *) data) & 0xffff); + printf(" = <%04x>", be16_to_cpu(*(u16 *) data) & 0xffff); break; case 4: /* word */ - printf(" = <0x%08x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU); + printf(" = <%x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU); break; case 8: /* double-word */ - printf(" = <0x%16llx>", be64_to_cpu(*(uint64_t *) data)); + printf(" = <%qx>", be64_to_cpu(*(uint64_t *) data)); break; default: /* anything else... hexdump */ printf(" = ["); @@ -350,7 +276,7 @@ void ft_dump_blob(const void *bphp) if (addr == 0 && size == 0) break; - printf("/memreserve/ 0x%llx 0x%llx;\n", addr, size); + printf("/memreserve/ %qx %qx;\n", addr, size); } p = p_struct; @@ -381,8 +307,8 @@ void ft_dump_blob(const void *bphp) } if (tag != OF_DT_PROP) { - fprintf(stderr, "%*s ** Unknown tag 0x%08x\n", - depth * shift, "", tag); + fprintf(stderr, "%*s ** Unknown tag 0x%08x at 0x%x\n", + depth * shift, "", tag, --p); break; } sz = be32_to_cpu(*p++); @@ -397,64 +323,15 @@ void ft_dump_blob(const void *bphp) void ft_backtrack_node(struct ft_cxt *cxt) { - if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE) - return; /* XXX only for node */ - - cxt->p -= 4; -} - -/* note that the root node of the blob is "peeled" off */ -void ft_merge_blob(struct ft_cxt *cxt, void *blob) -{ - struct boot_param_header *bph = (struct boot_param_header *)blob; - u32 *p_struct = (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_struct)); - u32 *p_strings = - (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_strings)); - u32 tag, *p; - char *s, *t; - int depth, sz; - - if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE) - return; /* XXX only for node */ - - cxt->p -= 4; - - depth = 0; - p = p_struct; - while ((tag = be32_to_cpu(*p++)) != OF_DT_END) { - - /* printf("tag: 0x%08x (%d) - %d\n", tag, p - p_struct, depth); */ - - if (tag == OF_DT_BEGIN_NODE) { - s = (char *)p; - p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4); - - if (depth++ > 0) - ft_begin_node(cxt, s); - - continue; - } - - if (tag == OF_DT_END_NODE) { - ft_end_node(cxt); - if (--depth == 0) - break; - continue; - } - - if (tag == OF_DT_NOP) - continue; + int i = 4; - if (tag != OF_DT_PROP) - break; + while (be32_to_cpu(*(u32 *) (cxt->p - i)) != OF_DT_END_NODE) + i += 4; - sz = be32_to_cpu(*p++); - s = (char *)p_strings + be32_to_cpu(*p++); - t = (char *)p; - p = (u32 *) _ALIGN((unsigned long)p + sz, 4); + memmove (cxt->p - i, cxt->p, cxt->p_end - cxt->p); - ft_prop(cxt, s, t, sz); - } + cxt->p_end -= i; + cxt->p -= i; } void *ft_get_prop(void *bphp, const char *propname, int *szp) @@ -521,9 +398,6 @@ void *ft_get_prop(void *bphp, const char *propname, int *szp) /********************************************************************/ -extern unsigned char oftree_dtb[]; -extern unsigned int oftree_dtb_len; - /* Function that returns a character from the environment */ extern uchar(*env_get_char) (int); @@ -577,7 +451,7 @@ static const struct { }; #endif -void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end) +void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end) { u32 *p; int len; @@ -600,20 +474,16 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_ return; } - ft_begin(&cxt, blob, size); +#ifdef DEBUG + printf ("recieved oftree\n"); + ft_dump_blob(blob); +#endif + + ft_init_cxt(&cxt, blob); if (initrd_start && initrd_end) ft_add_rsvmap(&cxt, initrd_start, initrd_end - initrd_start + 1); - ft_begin_tree(&cxt); - - ft_begin_node(&cxt, ""); - - ft_end_node(&cxt); - - /* copy RO tree */ - ft_merge_blob(&cxt, oftree_dtb); - /* back into root */ ft_backtrack_node(&cxt); @@ -642,8 +512,8 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_ #endif ft_begin_node(&cxt, "chosen"); - ft_prop_str(&cxt, "name", "chosen"); + ft_prop_str(&cxt, "bootargs", getenv("bootargs")); ft_prop_int(&cxt, "linux,platform", 0x600); /* what is this? */ if (initrd_start && initrd_end) { @@ -659,11 +529,7 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_ ft_end_node(&cxt); /* end root */ ft_end_tree(&cxt); - - /* - printf("merged OF-tree\n"); - ft_dump_blob(blob); - */ + ft_finalize_tree(&cxt); #ifdef CONFIG_OF_HAS_BD_T /* paste the bd_t at the end of the flat tree */ @@ -712,11 +578,12 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_ ft_board_setup(blob, bd); #endif - /* - printf("final OF-tree\n"); - ft_dump_blob(blob); - */ + /* in case the size changed in the platform code */ + ft_finalize_tree(&cxt); +#ifdef DEBUG + printf("final OF-tree\n"); + ft_dump_blob(blob); +#endif } - #endif diff --git a/include/ft_build.h b/include/ft_build.h index 47ca575d9fe..f5156879de3 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -36,19 +36,18 @@ struct boot_param_header { struct ft_cxt { struct boot_param_header *bph; - int max_size; /* maximum size of tree */ - int overflow; /* set when this happens */ - u8 *p, *pstr, *pres; /* running pointers */ - u8 *p_begin, *pstr_begin, *pres_begin; /* starting pointers */ - u8 *p_anchor; /* start of constructed area */ - int struct_size, strings_size, res_size; + u8 *p_rsvmap; + u8 *p_start; /* pointer to beginning of dt_struct */ + u8 *p_end; /* pointer to end of dt_strings */ + u8 *p; /* pointer to end of dt_struct and beginning of dt_strings */ }; void ft_begin_node(struct ft_cxt *cxt, const char *name); +void ft_init_cxt(struct ft_cxt *cxt, void *blob); void ft_end_node(struct ft_cxt *cxt); -void ft_begin_tree(struct ft_cxt *cxt); -int ft_end_tree(struct ft_cxt *cxt); +void ft_end_tree(struct ft_cxt *cxt); +void ft_finalize_tree(struct ft_cxt *cxt); void ft_nop(struct ft_cxt *cxt); void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz); @@ -57,12 +56,14 @@ void ft_prop_int(struct ft_cxt *cxt, const char *name, int val); void ft_begin(struct ft_cxt *cxt, void *blob, int max_size); void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size); -void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end); +void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end); void ft_dump_blob(const void *bphp); void ft_merge_blob(struct ft_cxt *cxt, void *blob); void *ft_get_prop(void *bphp, const char *propname, int *szp); +#ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup(void *blob, bd_t *bd); +#endif #endif -- cgit v1.3.1 From 0e16387db1d4aacd5bf35cb6d7c1942765c0347b Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:43:36 -0500 Subject: * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards Patch by Jon Loeliger 17-Jan-2006 Signed-off-by: Jon Loeliger --- board/cds/common/ft_board.c | 46 +++++++++++++++++++++++++++++++++++++++ board/cds/mpc8541cds/Makefile | 3 ++- board/cds/mpc8548cds/Makefile | 3 ++- board/cds/mpc8555cds/Makefile | 3 ++- board/mpc8540ads/mpc8540ads.c | 24 +++++++++++++++++++++ board/mpc8560ads/mpc8560ads.c | 9 ++++++++ cpu/mpc85xx/cpu.c | 50 ++++++++++++++++++++++++++++++++++++++++++- cpu/mpc85xx/cpu_init.c | 1 + include/configs/MPC8540ADS.h | 15 +++++++++++++ include/configs/MPC8541CDS.h | 12 +++++++++++ include/configs/MPC8548CDS.h | 12 +++++++++++ include/configs/MPC8555CDS.h | 12 +++++++++++ include/configs/MPC8560ADS.h | 12 +++++++++++ 13 files changed, 198 insertions(+), 4 deletions(-) create mode 100644 board/cds/common/ft_board.c (limited to 'include') diff --git a/board/cds/common/ft_board.c b/board/cds/common/ft_board.c new file mode 100644 index 00000000000..73eca5e6944 --- /dev/null +++ b/board/cds/common/ft_board.c @@ -0,0 +1,46 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_OF_FLAT_TREE) +#include +extern void ft_cpu_setup(void *blob, bd_t *bd); +#endif + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff --git a/board/cds/mpc8541cds/Makefile b/board/cds/mpc8541cds/Makefile index 0d4abbd71d8..aea61360a5f 100644 --- a/board/cds/mpc8541cds/Makefile +++ b/board/cds/mpc8541cds/Makefile @@ -28,7 +28,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ - ../common/eeprom.o + ../common/eeprom.o \ + ../common/ft_board.o SOBJS := init.o diff --git a/board/cds/mpc8548cds/Makefile b/board/cds/mpc8548cds/Makefile index 0d4abbd71d8..aea61360a5f 100644 --- a/board/cds/mpc8548cds/Makefile +++ b/board/cds/mpc8548cds/Makefile @@ -28,7 +28,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ - ../common/eeprom.o + ../common/eeprom.o \ + ../common/ft_board.o SOBJS := init.o diff --git a/board/cds/mpc8555cds/Makefile b/board/cds/mpc8555cds/Makefile index 0d4abbd71d8..aea61360a5f 100644 --- a/board/cds/mpc8555cds/Makefile +++ b/board/cds/mpc8555cds/Makefile @@ -28,7 +28,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ - ../common/eeprom.o + ../common/eeprom.o \ + ../common/ft_board.o SOBJS := init.o diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c index d0eb6904ada..855888d2761 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/mpc8540ads/mpc8540ads.c @@ -31,6 +31,12 @@ #include #include +#if defined(CONFIG_OF_FLAT_TREE) +#include +extern void ft_cpu_setup(void *blob, bd_t *bd); +#endif + + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -342,3 +348,21 @@ pci_init_board(void) pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index 25f69a0bf5d..f9d75e80510 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -544,3 +544,12 @@ pci_init_board(void) pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index f7fe22e3e1e..0507c47e6e7 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -30,7 +30,10 @@ #include #include -/* ------------------------------------------------------------------------- */ +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif + int checkcpu (void) { @@ -227,3 +230,48 @@ int dma_xfer(void *dest, uint count, void *src) { return dma_check(); } #endif + + +#ifdef CONFIG_OF_FLAT_TREE +void +ft_cpu_setup(void *blob, bd_t *bd) +{ + u32 *p; + ulong clock; + int len; + + clock = bd->bi_busfreq; + p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + +#if defined(CONFIG_MPC85XX_TSEC1) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); + memcpy(p, bd->bi_enetaddr, 6); +#endif + +#if defined(CONFIG_HAS_ETH1) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); + memcpy(p, bd->bi_enet1addr, 6); +#endif + +#if defined(CONFIG_HAS_ETH2) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); + memcpy(p, bd->bi_enet2addr, 6); +#endif + +#if defined(CONFIG_HAS_ETH3) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); + memcpy(p, bd->bi_enet3addr, 6); +#endif + +} +#endif diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c12b47b589d..9f4d36c1ab4 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_CPM2 static void config_8560_ioports (volatile immap_t * immr) { diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 131c8322426..d31a18b7948 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -293,6 +293,21 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8540@0" +#define OF_SOC "soc8540@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index c96b98b54d3..86bcfe324c8 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -308,6 +308,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8541@0" +#define OF_SOC "soc8541@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4ca8bc35db1..b1f8a192dff 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -314,6 +314,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8548@0" +#define OF_SOC "soc8548@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index a44e3ec8453..b725dac52b6 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -308,6 +308,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8555@0" +#define OF_SOC "soc8555@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 2d5031b77d3..1c684f2fd10 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -290,6 +290,18 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8560@0" +#define OF_SOC "soc8560@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -- cgit v1.3.1 From f0e6f57f71b3c4fdd13028eb03c3f3e91926dda2 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:44:49 -0500 Subject: * Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming --- include/pci.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/pci.h b/include/pci.h index 0fc00e42769..e0e8783a7aa 100644 --- a/include/pci.h +++ b/include/pci.h @@ -270,6 +270,15 @@ #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ #define PCI_AGP_SIZEOF 12 +/* PCI-X registers */ + +#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ +#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ +#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ +#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ + + /* Slot Identification */ #define PCI_SID_ESR 2 /* Expansion Slot Register */ -- cgit v1.3.1 From 97074ed9655309b64231bc2cee69fe85399f8055 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:45:17 -0500 Subject: * Added support for initializing second PCI bus on 85xx Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- cpu/mpc85xx/pci.c | 182 ++++++++++++++++++++++++++++++++++--------- include/asm-ppc/immap_85xx.h | 25 +++++- 2 files changed, 170 insertions(+), 37 deletions(-) (limited to 'include') diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index a94493e0802..ca11bce22ea 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -32,66 +32,90 @@ #if defined(CONFIG_PCI) +static struct pci_controller *pci_hose; + void -pci_mpc85xx_init(struct pci_controller *hose) +pci_mpc85xx_init(struct pci_controller *board_hose) { + u16 reg16; + u32 dev; + volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; volatile ccsr_pcix_t *pcix = &immap->im_pcix; + volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2; + volatile ccsr_gur_t *gur = &immap->im_gur; + struct pci_controller * hose; - u16 reg16; + pci_hose = board_hose; + + hose = &pci_hose[0]; hose->first_busno = 0; hose->last_busno = 0xff; - pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - pci_set_region(hose->regions + 1, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 2; - pci_setup_indirect(hose, (CFG_IMMR+0x8000), (CFG_IMMR+0x8004)); + /* + * Hose scan. + */ + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + + if (!(gur->pordevsr & PORDEVSR_PCI)) { + /* PCI-X init */ + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16); + } + pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; pcix->potear1 = 0x00000000; - pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff; pcix->powbear1 = 0x00000000; - pcix->powar1 = 0x8004401c; /* 512M MEM space */ + pcix->powar1 = (POWAR_EN | POWAR_MEM_READ | + POWAR_MEM_WRITE | POWAR_MEM_512M); - pcix->potar2 = 0x00000000; + pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; pcix->potear2 = 0x00000000; - pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff; pcix->powbear2 = 0x00000000; - pcix->powar2 = 0x80088017; /* 16M IO space */ + pcix->powar2 = (POWAR_EN | POWAR_IO_READ | + POWAR_IO_WRITE | POWAR_IO_1M); pcix->pitar1 = 0x00000000; pcix->piwbar1 = 0x00000000; - pcix->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, - * Snoop R/W, 2G */ + pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G); - /* - * Hose scan. - */ - pci_register_hose(hose); + pcix->powar3 = 0; + pcix->powar4 = 0; + pcix->piwar2 = 0; + pcix->piwar3 = 0; - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); - /* - * Clear non-reserved bits in status register. - */ - pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); + pci_set_region(hose->regions + 1, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 2; + + pci_register_hose(hose); #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS) /* @@ -117,6 +141,94 @@ pci_mpc85xx_init(struct pci_controller *hose) #endif hose->last_busno = pci_hose_scan(hose); + +#ifdef CONFIG_MPC85XX_PCI2 + hose = &pci_hose[1]; + + hose->first_busno = pci_hose[0].last_busno + 1; + hose->last_busno = 0xff; + + pci_setup_indirect(hose, + (CFG_IMMR+0x9000), + (CFG_IMMR+0x9004)); + + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + + pcix2->potar1 = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff; + pcix2->potear1 = 0x00000000; + pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff; + pcix2->powbear1 = 0x00000000; + pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ | + POWAR_MEM_WRITE | POWAR_MEM_512M); + + pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff; + pcix2->potear2 = 0x00000000; + pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff; + pcix2->powbear2 = 0x00000000; + pcix2->powar2 = (POWAR_EN | POWAR_IO_READ | + POWAR_IO_WRITE | POWAR_IO_1M); + + pcix2->pitar1 = 0x00000000; + pcix2->piwbar1 = 0x00000000; + pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G); + + pcix2->powar3 = 0; + pcix2->powar4 = 0; + pcix2->piwar2 = 0; + pcix2->piwar3 = 0; + + pci_set_region(hose->regions + 0, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, + PCI_REGION_MEM); + + pci_set_region(hose->regions + 1, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, + CFG_PCI2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 2; + + /* + * Hose scan. + */ + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); +#endif } +#ifdef CONFIG_OF_FLAT_TREE +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[0].first_busno; + p[1] = pci_hose[0].last_busno; + } + +#ifdef CONFIG_MPC85XX_PCI2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[1].first_busno; + p[1] = pci_hose[1].last_busno; + } +#endif +} +#endif /* CONFIG_OF_FLAT_TREE */ #endif /* CONFIG_PCI */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 2f10e9591d2..7a4345a7408 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -246,7 +246,6 @@ typedef struct ccsr_lbc { /* * PCI Registers(0x8000-0x9000) - * Omitting Reserved(0x9000-0x2_0000) */ typedef struct ccsr_pcix { uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */ @@ -309,9 +308,27 @@ typedef struct ccsr_pcix { uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */ uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */ uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */ - char res11[94688]; + uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */ + char res11[476]; } ccsr_pcix_t; +#define PCIX_COMMAND 0x62 +#define POWAR_EN 0x80000000 +#define POWAR_IO_READ 0x00080000 +#define POWAR_MEM_READ 0x00040000 +#define POWAR_IO_WRITE 0x00008000 +#define POWAR_MEM_WRITE 0x00004000 +#define POWAR_MEM_512M 0x0000001c +#define POWAR_IO_1M 0x00000013 + +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_LOCAL 0x00f00000 +#define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE_SNOOP 0x00005000 +#define PIWAR_MEM_2G 0x0000001e + + /* * L2 Cache Registers(0x2_0000-0x2_1000) */ @@ -1572,6 +1589,8 @@ typedef struct ccsr_gur { char res15[61651]; } ccsr_gur_t; +#define PORDEVSR_PCI (0x00800000) /* PCI Mode */ + typedef struct immap { ccsr_local_ecm_t im_local_ecm; ccsr_ddr_t im_ddr; @@ -1579,6 +1598,8 @@ typedef struct immap { ccsr_duart_t im_duart; ccsr_lbc_t im_lbc; ccsr_pcix_t im_pcix; + ccsr_pcix_t im_pcix2; + char reserved[90112]; ccsr_l2cache_t im_l2cache; ccsr_dma_t im_dma; ccsr_tsec_t im_tsec1; -- cgit v1.3.1 From c88f9fe66b64247e5b6a38410ba315ca25596d16 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:45:41 -0500 Subject: * Fixed PCI memory definitions Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- board/mpc8540ads/mpc8540ads.c | 21 ++++----------------- include/configs/MPC8540ADS.h | 9 +++++---- 2 files changed, 9 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c index 855888d2761..fbcb397290a 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/mpc8540ads/mpc8540ads.c @@ -317,24 +317,8 @@ long int fixed_sdram (void) * Initialize PCI Devices, report devices found. */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxads_config_table, -#endif -}; +static struct pci_controller hose; #endif /* CONFIG_PCI */ @@ -357,6 +341,9 @@ ft_board_setup(void *blob, bd_t *bd) u32 *p; int len; +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif ft_cpu_setup(blob, bd); p = ft_get_prop(blob, "/memory/reg", &len); diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index d31a18b7948..81ee945d499 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -71,7 +71,7 @@ */ #ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33000000 +#define CONFIG_SYS_CLK_FREQ 66000000 #endif @@ -327,9 +327,10 @@ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#define CFG_PCI1_IO_BASE 0x0 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) -- cgit v1.3.1 From bf1dfffd8c26f8ecdd630a0ae4c834e751e4e452 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:46:13 -0500 Subject: * Added VIA configuration table * Added support for PCI2 on CDS Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- board/cds/common/ft_board.c | 3 ++ board/cds/common/via.c | 99 +++++++++++++++++++++++++++++++++++++++ board/cds/common/via.h | 18 +++++++ board/cds/mpc8541cds/Makefile | 3 +- board/cds/mpc8541cds/init.S | 12 ++--- board/cds/mpc8541cds/mpc8541cds.c | 32 ++++++------- board/cds/mpc8548cds/Makefile | 3 +- board/cds/mpc8548cds/init.S | 12 ++--- board/cds/mpc8548cds/mpc8548cds.c | 32 ++++++------- board/cds/mpc8555cds/Makefile | 3 +- board/cds/mpc8555cds/init.S | 12 ++--- board/cds/mpc8555cds/mpc8555cds.c | 39 ++++++++------- include/configs/MPC8541CDS.h | 21 ++++----- include/configs/MPC8548CDS.h | 23 ++++----- include/configs/MPC8555CDS.h | 23 ++++----- 15 files changed, 223 insertions(+), 112 deletions(-) create mode 100644 board/cds/common/via.c create mode 100644 board/cds/common/via.h (limited to 'include') diff --git a/board/cds/common/ft_board.c b/board/cds/common/ft_board.c index 73eca5e6944..77d1d851d90 100644 --- a/board/cds/common/ft_board.c +++ b/board/cds/common/ft_board.c @@ -35,6 +35,9 @@ ft_board_setup(void *blob, bd_t *bd) u32 *p; int len; +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif ft_cpu_setup(blob, bd); p = ft_get_prop(blob, "/memory/reg", &len); diff --git a/board/cds/common/via.c b/board/cds/common/via.c new file mode 100644 index 00000000000..68c8d212f41 --- /dev/null +++ b/board/cds/common/via.c @@ -0,0 +1,99 @@ +/* + * Copyright 2006 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* Config the VIA chip */ +void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pci_dev_t bridge; + + /* Enable USB and IDE functions */ + pci_hose_write_config_byte(hose, dev, 0x48, 0x08); + + pciauto_config_device(hose, dev); + + /* + * Force the backplane P2P bridge to have a window + * open from 0x00000000-0x00001fff in PCI I/O space. + * This allows legacy I/O (i8259, etc) on the VIA + * southbridge to be accessed. + */ + bridge = PCI_BDF(0,17,0); + pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); + pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); + pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); + pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0); +} + +/* Function 1, IDE */ +void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + /* + * Since the P2P window was forced to cover the fixed + * legacy I/O addresses, it is necessary to manually + * place the base addresses for the IDE and USB functions + * within this window. + */ + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0); +} + +/* Function 2, USB ports 0-1 */ +void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0); +} + +/* Function 3, USB ports 2-3 */ +void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80); +} + +/* Function 5, Power Management */ +void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8); +} + +/* Function 6, AC97 Interface */ +void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00); +} + diff --git a/board/cds/common/via.h b/board/cds/common/via.h new file mode 100644 index 00000000000..77cfacc5261 --- /dev/null +++ b/board/cds/common/via.h @@ -0,0 +1,18 @@ +#ifndef _MPC85xx_VIA_H +void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 1, IDE */ +void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 2, USB ports 0-1 */ +void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 3, USB ports 2-3 */ +void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 5, Power Management */ +void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 6, AC97 Interface */ +void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); +#endif /* _MPC85xx_VIA_H */ diff --git a/board/cds/mpc8541cds/Makefile b/board/cds/mpc8541cds/Makefile index aea61360a5f..d202281d454 100644 --- a/board/cds/mpc8541cds/Makefile +++ b/board/cds/mpc8541cds/Makefile @@ -29,7 +29,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ ../common/eeprom.o \ - ../common/ft_board.o + ../common/ft_board.o \ + ../common/via.o SOBJS := init.o diff --git a/board/cds/mpc8541cds/init.S b/board/cds/mpc8541cds/init.S index 53dcd0d7624..978bda5e4dc 100644 --- a/board/cds/mpc8541cds/init.S +++ b/board/cds/mpc8541cds/init.S @@ -210,8 +210,8 @@ tlb1_entry: * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -234,11 +234,11 @@ tlb1_entry: #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index 6b8aa68f541..c2b3009fd2b 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -31,6 +31,7 @@ #include "../common/cadmus.h" #include "../common/eeprom.h" +#include "../common/via.h" #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -468,26 +469,25 @@ testdram(void) #endif #if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it. */ +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } -#ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}}, + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}} }; -#endif -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxcds_config_table, +static struct pci_controller hose[] = { + { config_table: pci_mpc85xxcds_config_table,}, +#ifdef CONFIG_MPC85XX_PCI2 + {}, #endif }; @@ -497,7 +497,7 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); + extern void pci_mpc85xx_init(struct pci_controller **hose); pci_mpc85xx_init(&hose); #endif diff --git a/board/cds/mpc8548cds/Makefile b/board/cds/mpc8548cds/Makefile index aea61360a5f..d202281d454 100644 --- a/board/cds/mpc8548cds/Makefile +++ b/board/cds/mpc8548cds/Makefile @@ -29,7 +29,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ ../common/eeprom.o \ - ../common/ft_board.o + ../common/ft_board.o \ + ../common/via.o SOBJS := init.o diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S index 53dcd0d7624..978bda5e4dc 100644 --- a/board/cds/mpc8548cds/init.S +++ b/board/cds/mpc8548cds/init.S @@ -210,8 +210,8 @@ tlb1_entry: * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -234,11 +234,11 @@ tlb1_entry: #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 5bc08900a47..6eedb4a2095 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -30,6 +30,7 @@ #include "../common/cadmus.h" #include "../common/eeprom.h" +#include "../common/via.h" #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -293,26 +294,25 @@ testdram(void) #endif #if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it. */ +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } -#ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}}, + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}} }; -#endif -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxcds_config_table, +static struct pci_controller hose[] = { + { config_table: pci_mpc85xxcds_config_table,}, +#ifdef CONFIG_MPC85XX_PCI2 + {}, #endif }; @@ -322,7 +322,7 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); + extern void pci_mpc85xx_init(struct pci_controller **hose); pci_mpc85xx_init(&hose); #endif diff --git a/board/cds/mpc8555cds/Makefile b/board/cds/mpc8555cds/Makefile index aea61360a5f..d202281d454 100644 --- a/board/cds/mpc8555cds/Makefile +++ b/board/cds/mpc8555cds/Makefile @@ -29,7 +29,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ ../common/eeprom.o \ - ../common/ft_board.o + ../common/ft_board.o \ + ../common/via.o SOBJS := init.o diff --git a/board/cds/mpc8555cds/init.S b/board/cds/mpc8555cds/init.S index 53dcd0d7624..978bda5e4dc 100644 --- a/board/cds/mpc8555cds/init.S +++ b/board/cds/mpc8555cds/init.S @@ -210,8 +210,8 @@ tlb1_entry: * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -234,11 +234,11 @@ tlb1_entry: #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index 18adf5b9e6f..e15bf8f2ca3 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -29,6 +29,7 @@ #include "../common/cadmus.h" #include "../common/eeprom.h" +#include "../common/via.h" #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -464,38 +465,40 @@ testdram(void) } #endif -#if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. +#ifdef CONFIG_PCI +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it */ +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } -#ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}}, + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}} }; -#endif -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP + +static struct pci_controller hose[] = { + { config_table: pci_mpc85xxcds_config_table, + }, +#ifdef CONFIG_MPC85XX_PCI2 + { } #endif }; -#endif /* CONFIG_PCI */ +#endif void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); + extern void pci_mpc85xx_init(struct pci_controller **hose); - pci_mpc85xx_init(&hose); + pci_mpc85xx_init(*pci_hose); #endif } diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 86bcfe324c8..f73caf0319c 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8541@0" #define OF_SOC "soc8541@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -335,32 +335,27 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) +#define CONFIG_MPC85XX_PCI2 #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b1f8a192dff..37b518cca50 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -324,7 +324,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8548@0" #define OF_SOC "soc8548@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -341,32 +341,27 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_85XX_PCI2 #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ @@ -386,7 +381,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#define CONFIG_MPC85XX_TSEC4 1 +#undef CONFIG_MPC85XX_TSEC4 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index b725dac52b6..b94e38ae347 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8555@0" #define OF_SOC "soc8555@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -335,33 +335,28 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_MPC85XX_PCI2 #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ -- cgit v1.3.1 From 34c3c0e01dbf1f8cc2bd08de92f2b89ba84921eb Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:47:03 -0500 Subject: * Switched default PCI speed for 8540 ADS back to 33MHz * Added comments and a printf to warn that PCI-X won't work at 33MHz Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- cpu/mpc85xx/pci.c | 3 +++ doc/README.mpc85xxads | 3 +++ include/configs/MPC8540ADS.h | 6 +++++- 3 files changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index ca11bce22ea..cfb7dcdc895 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -72,6 +72,9 @@ pci_mpc85xx_init(struct pci_controller *board_hose) if (!(gur->pordevsr & PORDEVSR_PCI)) { /* PCI-X init */ + if (CONFIG_SYS_CLK_FREQ < 66000000) + printf("PCI-X will only work at 66 MHz\n"); + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16); diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index f0cf782a8fc..ae8202bdd17 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -100,6 +100,9 @@ Updated 13-July-2004 Jon Loeliger SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock + In order to use PCI-X (only in the first PCI slot. The one with + the RIO connector), you need to set SW1[4] (config) to 1 (off). + Also, configure the board to run PCI at 66 MHz. 2. MEMORY MAP TO WORK WITH LINUX KERNEL diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 81ee945d499..8e4d2c95a44 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -68,10 +68,14 @@ * The board, however, can run at 66MHz. In any event, this value * must match the settings of some switches. Details can be found * in the README.mpc85xxads. + * + * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to + * 33MHz to accommodate, based on a PCI pin. + * Note that PCI-X won't work at 33MHz. */ #ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_SYS_CLK_FREQ 33000000 #endif -- cgit v1.3.1 From 692519b1edfd5803cd2a841921492889f46f0ce3 Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Thu, 10 Aug 2006 12:43:17 +0200 Subject: Add support for PCI-Express on PPC440SPe (Yucca board). --- CHANGELOG | 2 + board/amcc/yucca/init.S | 62 ++++- board/amcc/yucca/yucca.c | 130 ++++++++++- cpu/ppc4xx/405gp_pci.c | 5 +- cpu/ppc4xx/440spe_pcie.c | 593 +++++++++++++++++++++++++++++++++++++++++++++++ cpu/ppc4xx/440spe_pcie.h | 162 +++++++++++++ cpu/ppc4xx/Makefile | 3 +- cpu/ppc4xx/cpu.c | 11 + cpu/ppc4xx/start.S | 16 ++ include/common.h | 4 + include/configs/yucca.h | 32 ++- 11 files changed, 1000 insertions(+), 20 deletions(-) create mode 100644 cpu/ppc4xx/440spe_pcie.c create mode 100644 cpu/ppc4xx/440spe_pcie.h (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index de02125bd63..0c70d3cfcdb 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add initial support for PCI-Express on PPC440SPe (Yucca board). + * Fix timer problems on AMCC yucca board. Set Timer Clock Select to use CPU clock as a timer input source. diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S index 8cf2636228b..a950eac44f9 100644 --- a/board/amcc/yucca/init.S +++ b/board/amcc/yucca/init.S @@ -82,9 +82,12 @@ *************************************************************************/ .section .bootpg,"ax" - .globl tlbtab -tlbtab: +/************************************************************************** + * TLB table for revA + *************************************************************************/ + .globl tlbtabA +tlbtabA: tlbtab_start tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G) @@ -94,12 +97,63 @@ tlbtab: tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) - tlbentry(CFG_FPGA_BASE,SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I) + tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I) - tlbentry(CFG_OPER_FLASH,SZ_16M,0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_XCFGBASE, SZ_4K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_XCFGBASE, SZ_4K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_XCFGBASE, SZ_4K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCIE1_REGBASE, SZ_1K, 0x60000400, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE3_REGBASE, SZ_1K, 0x60001400, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE5_REGBASE, SZ_1K, 0x60002400, 0xD, AC_R|AC_W|SA_G|SA_I) tlbtab_end +/************************************************************************** + * TLB table for revB + * + * Notice: revB of the 440SPe chip is very strict about PLB real addressess + * and ranges to be mapped for config space: it seems to only work with + * d_nnnn_nnnn range (hangs the core upon config transaction attempts when + * set otherwise) while revA uses c_nnnn_nnnn. + *************************************************************************/ + .globl tlbtabB +tlbtabB: + tlbtab_start + tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G) + + tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + + tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) + tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I) + + tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCIE1_REGBASE, SZ_1K, 0x60000400, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE3_REGBASE, SZ_1K, 0x60001400, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE5_REGBASE, SZ_1K, 0x60002400, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbtab_end diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 1ae3a549b9b..a6589ec262a 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -21,12 +21,16 @@ * MA 02111-1307 USA * * Port to AMCC-440SPE Evaluation Board SOP - April 2005 + * + * PCIe supporting routines derived from Linux 440SPe PCIe driver. */ #include #include #include #include +#include + #include "yucca.h" void fpga_init (void); @@ -39,6 +43,9 @@ int get_console_port(void); unsigned long ppcMfcpr(unsigned long cpr_reg); unsigned long ppcMfsdr(unsigned long sdr_reg); +int ppc440spe_init_pcie_rootport(int port); +void ppc440spe_setup_pcie(struct pci_controller *hose, int port); + #define DEBUG_ENV #ifdef DEBUG_ENV #define DEBUGF(fmt,args...) printf(fmt ,##args) @@ -908,6 +915,7 @@ void pci_target_init(struct pci_controller * hose ) } #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#if defined(CONFIG_PCI) /************************************************************************* * is_pci_host * @@ -923,12 +931,131 @@ void pci_target_init(struct pci_controller * hose ) * * ************************************************************************/ -#if defined(CONFIG_PCI) int is_pci_host(struct pci_controller *hose) { /* The yucca board is always configured as host. */ return 1; } + + +int yucca_pcie_card_present(int port) +{ + u16 reg; + + reg = in_be16((u16 *)FPGA_REG1C); + switch(port) { + case 0: + return !(reg & FPGA_REG1C_PE0_PRSNT); + case 1: + return !(reg & FPGA_REG1C_PE1_PRSNT); + case 2: + return !(reg & FPGA_REG1C_PE2_PRSNT); + default: + return 0; + } +} + +/* + * For the given slot, set rootpoint mode, send power to the slot, + * turn on the green LED and turn off the yellow LED, enable the clock + * and turn off reset. + */ +void yucca_setup_pcie_fpga_rootpoint(int port) +{ + u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint; + + switch(port) { + case 0: + rootpoint = FPGA_REG1C_PE0_ROOTPOINT; + endpoint = 0; + power = FPGA_REG1A_PE0_PWRON; + green_led = FPGA_REG1A_PE0_GLED; + clock = FPGA_REG1A_PE0_REFCLK_ENABLE; + yellow_led = FPGA_REG1A_PE0_YLED; + reset_off = FPGA_REG1C_PE0_PERST; + break; + case 1: + rootpoint = 0; + endpoint = FPGA_REG1C_PE1_ENDPOINT; + power = FPGA_REG1A_PE1_PWRON; + green_led = FPGA_REG1A_PE1_GLED; + clock = FPGA_REG1A_PE1_REFCLK_ENABLE; + yellow_led = FPGA_REG1A_PE1_YLED; + reset_off = FPGA_REG1C_PE1_PERST; + break; + case 2: + rootpoint = 0; + endpoint = FPGA_REG1C_PE2_ENDPOINT; + power = FPGA_REG1A_PE2_PWRON; + green_led = FPGA_REG1A_PE2_GLED; + clock = FPGA_REG1A_PE2_REFCLK_ENABLE; + yellow_led = FPGA_REG1A_PE2_YLED; + reset_off = FPGA_REG1C_PE2_PERST; + break; + + default: + return; + } + + out_be16((u16 *)FPGA_REG1A, + ~(power | clock | green_led) & + (yellow_led | in_be16((u16 *)FPGA_REG1A))); + + out_be16((u16 *)FPGA_REG1C, + ~(endpoint | reset_off) & + (rootpoint | in_be16((u16 *)FPGA_REG1C))); + /* + * Leave device in reset for a while after powering on the + * slot to give it a chance to initialize. + */ + udelay(250 * 1000); + + out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C)); +} + + +static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; + +void pcie_setup_hoses(void) +{ + struct pci_controller *hose; + int i, bus; + + /* + * assume we're called after the PCIX hose is initialized, which takes + * bus ID 0 and therefore start numbering PCIe's from 1. + */ + bus = 1; + for (i = 0; i <= 2; i++) { + /* Check for yucca card presence */ + if (!yucca_pcie_card_present(i)) + continue; + + yucca_setup_pcie_fpga_rootpoint(i); + if (ppc440spe_init_pcie_rootport(i)) { + printf("PCIE%d: initialization failed\n", i); + continue; + } + + hose = &pcie_hose[i]; + hose->first_busno = bus; + hose->last_busno = bus; + bus++; + + /* setup mem resource */ + pci_set_region(hose->regions + 0, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMSIZE, + PCI_REGION_MEM + ); + hose->region_count = 1; + pci_register_hose(hose); + + ppc440spe_setup_pcie(hose, i); + hose->last_busno = pci_hose_scan(hose); + } +} #endif /* defined(CONFIG_PCI) */ int misc_init_f (void) @@ -1094,4 +1221,3 @@ unsigned long ppcMfsdr(unsigned long sdr_reg) return (sdr_value); } - diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index cf5eccb01fd..0b0686bcf71 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -315,7 +315,6 @@ void pci_405gp_init(struct pci_controller *hose) #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif - hose->last_busno = pci_hose_scan(hose); } #endif /* CONFIG_PCI_PNP */ @@ -563,10 +562,12 @@ void pci_440_init (struct pci_controller *hose) } } - void pci_init_board(void) { pci_440_init (&ppc440_hose); +#if defined(CONFIG_440SPE) + pcie_setup_hoses(); +#endif } #endif /* CONFIG_440 & CONFIG_PCI */ diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c new file mode 100644 index 00000000000..cbc93dd0228 --- /dev/null +++ b/cpu/ppc4xx/440spe_pcie.c @@ -0,0 +1,593 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * Roland Dreier + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +#include "440spe_pcie.h" + +#if defined(CONFIG_440SPE) +#if defined(CONFIG_PCI) + +enum { + PTYPE_ENDPOINT = 0x0, + PTYPE_LEGACY_ENDPOINT = 0x1, + PTYPE_ROOT_PORT = 0x4, + + LNKW_X1 = 0x1, + LNKW_X4 = 0x4, + LNKW_X8 = 0x8 +}; + +static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, + int offset, int len, u32 *val) { + + *val = 0; + /* + * 440SPE implements only one function per port + */ + if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1))) + return 0; + + devfn = PCI_BDF(0,0,0); + offset += devfn << 4; + + switch (len) { + case 1: + *val = in_8(hose->cfg_data + offset); + break; + case 2: + *val = in_le16((u16 *)(hose->cfg_data + offset)); + break; + default: + *val = in_le32((u32 *)(hose->cfg_data + offset)); + break; + } + return 0; +} + +static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, + int offset, int len, u32 val) { + + /* + * 440SPE implements only one function per port + */ + if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1))) + return 0; + + devfn = PCI_BDF(0,0,0); + offset += devfn << 4; + + switch (len) { + case 1: + out_8(hose->cfg_data + offset, val); + break; + case 2: + out_le16((u16 *)(hose->cfg_data + offset), val); + break; + default: + out_le32((u32 *)(hose->cfg_data + offset), val); + break; + } + return 0; +} + +int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 1, &v); + *val = (u8)v; + return rv; +} + +int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 2, &v); + *val = (u16)v; + return rv; +} + +int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 3, &v); + *val = (u32)v; + return rv; +} + +int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val) +{ + return pcie_write_config(hose,(u32)dev,offset,1,val); +} + +int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val) +{ + return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val); +} + +int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val) +{ + return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val); +} + +static void ppc440spe_setup_utl(u32 port) { + + volatile void *utl_base = NULL; + + /* + * Map UTL registers + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000d); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x60000400); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xFFFFFC01); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); + utl_base = (unsigned int *)(CFG_PCIE1_REGBASE); + break; + + case 1: + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000d); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x60001400); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xFFFFFC01); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); + utl_base = (unsigned int *)(CFG_PCIE3_REGBASE); + break; + + case 2: + mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000d); + mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x60002400); + mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0xFFFFFC01); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); + utl_base = (unsigned int *)(CFG_PCIE5_REGBASE); + break; + } + + /* + * Set buffer allocations and then assert VRB and TXE. + */ + out_be32(utl_base + PEUTL_OUTTR, 0x08000000); + out_be32(utl_base + PEUTL_INTR, 0x02000000); + out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000); + out_be32(utl_base + PEUTL_PBBSZ, 0x53000000); + out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); + out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); + out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); + out_be32(utl_base + PEUTL_PCTL, 0x8080007d); +} + +static int check_error(void) +{ + u32 valPE0, valPE1, valPE2; + int err = 0; + + /* SDR0_PEGPLLLCT1 reset */ + if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) { + printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0); + } + + valPE0 = SDR_READ(PESDR0_RCSSET); + valPE1 = SDR_READ(PESDR1_RCSSET); + valPE2 = SDR_READ(PESDR2_RCSSET); + + /* SDR0_PExRCSSET rstgu */ + if (!(valPE0 & 0x01000000) || + !(valPE1 & 0x01000000) || + !(valPE2 & 0x01000000)) { + printf("PCIE: SDR0_PExRCSSET rstgu error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstdl */ + if (!(valPE0 & 0x00010000) || + !(valPE1 & 0x00010000) || + !(valPE2 & 0x00010000)) { + printf("PCIE: SDR0_PExRCSSET rstdl error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstpyn */ + if ((valPE0 & 0x00001000) || + (valPE1 & 0x00001000) || + (valPE2 & 0x00001000)) { + printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); + err = -1; + } + + /* SDR0_PExRCSSET hldplb */ + if ((valPE0 & 0x10000000) || + (valPE1 & 0x10000000) || + (valPE2 & 0x10000000)) { + printf("PCIE: SDR0_PExRCSSET hldplb error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rdy */ + if ((valPE0 & 0x00100000) || + (valPE1 & 0x00100000) || + (valPE2 & 0x00100000)) { + printf("PCIE: SDR0_PExRCSSET rdy error\n"); + err = -1; + } + + /* SDR0_PExRCSSET shutdown */ + if ((valPE0 & 0x00000100) || + (valPE1 & 0x00000100) || + (valPE2 & 0x00000100)) { + printf("PCIE: SDR0_PExRCSSET shutdown error\n"); + err = -1; + } + return err; +} + +/* + * Initialize PCI Express core + */ +int ppc440spe_init_pcie(void) +{ + int time_out = 20; + + /* Set PLL clock receiver to LVPECL */ + SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); + + if (check_error()) + return -1; + + if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) + { + printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n", + SDR_READ(PESDR0_PLLLCT2)); + return -1; + } + /* De-assert reset of PCIe PLL, wait for lock */ + SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); + udelay(3); + + while(time_out) { + if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { + time_out--; + udelay(1); + } else + break; + } + if (!time_out) { + printf("PCIE: VCO output not locked\n"); + return -1; + } + return 0; +} + +int ppc440spe_init_pcie_rootport(int port) +{ + static int core_init; + volatile u32 val = 0; + int attempts; + + if (!core_init) { + ++core_init; + if (ppc440spe_init_pcie()) + return -1; + } + + /* + * Initialize various parts of the PCI Express core for our port: + * + * - Set as a root port and enable max width + * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). + * - Set up UTL configuration. + * - Increase SERDES drive strength to levels suggested by AMCC. + * - De-assert RSTPYN, RSTDL and RSTGU. + * + * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with + * default setting 0x11310000. The register has new fields, + * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core + * hang. + */ + switch (port) { + case 0: + SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12); + + SDR_WRITE(PESDR0_UTLSET1, 0x21222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR0_UTLSET2, 0x11000000); + SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); + SDR_WRITE(PESDR0_RCSSET, + (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + + case 1: + SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); + SDR_WRITE(PESDR1_UTLSET1, 0x21222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR1_UTLSET2, 0x11000000); + SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR1_RCSSET, + (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + + case 2: + SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); + SDR_WRITE(PESDR2_UTLSET1, 0x21222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR2_UTLSET2, 0x11000000); + SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR2_RCSSET, + (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + } + /* + * Notice: the following delay has critical impact on device + * initialization - if too short (<50ms) the link doesn't get up. + */ + mdelay(100); + + switch (port) { + case 0: val = SDR_READ(PESDR0_RCSSTS); break; + case 1: val = SDR_READ(PESDR1_RCSSTS); break; + case 2: val = SDR_READ(PESDR2_RCSSTS); break; + } + + if (val & (1 << 20)) { + printf("PCIE%d: PGRST failed %08x\n", port, val); + return -1; + } + + /* + * Verify link is up + */ + val = 0; + switch (port) + { + case 0: + val = SDR_READ(PESDR0_LOOP); + break; + case 1: + val = SDR_READ(PESDR1_LOOP); + break; + case 2: + val = SDR_READ(PESDR2_LOOP); + break; + } + if (!(val & 0x00001000)) { + printf("PCIE%d: link is not up.\n", port); + return -1; + } + + /* + * Setup UTL registers - but only on revA! + * We use default settings for revB chip. + */ + if (!ppc440spe_revB()) + ppc440spe_setup_utl(port); + + /* + * We map PCI Express configuration access into the 512MB regions + * + * NOTICE: revB is very strict about PLB real addressess and ranges to + * be mapped for config space; it seems to only work with d_nnnn_nnnn + * range (hangs the core upon config transaction attempts when set + * otherwise) while revA uses c_nnnn_nnnn. + * + * For revA: + * PCIE0: 0xc_4000_0000 + * PCIE1: 0xc_8000_0000 + * PCIE2: 0xc_c000_0000 + * + * For revB: + * PCIE0: 0xd_0000_0000 + * PCIE1: 0xd_2000_0000 + * PCIE2: 0xd_4000_0000 + */ + switch (port) { + case 0: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000); + } else { + /* revA */ + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ + break; + + case 1: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000); + } else { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ + break; + + case 2: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000); + } else { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ + break; + } + + /* + * Check for VC0 active and assert RDY. + */ + attempts = 10; + switch (port) { + case 0: + while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE0: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); + break; + case 1: + while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE1: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + + SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); + break; + case 2: + while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE2: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + + SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); + break; + } + mdelay(100); + + return 0; +} + +void ppc440spe_setup_pcie(struct pci_controller *hose, int port) +{ + volatile void *mbase = NULL; + + pci_set_ops(hose, + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); + + switch(port) { + case 0: + mbase = (u32 *)CFG_PCIE0_XCFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; + break; + case 1: + mbase = (u32 *)CFG_PCIE1_XCFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; + break; + case 2: + mbase = (u32 *)CFG_PCIE2_XCFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; + break; + } + + /* + * Set bus numbers on our root port + */ + if (ppc440spe_revB()) { + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); + out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); + } else { + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0); + } + + /* + * Set up outbound translation to hose->mem_space from PLB + * addresses at an offset of 0xd_0000_0000. We set the low + * bits of the mask to 11 to turn off splitting into 8 + * subregions and to enable the outbound translation. + */ + out_le32(mbase + PECFG_POM0LAH, 0x00000000); + out_le32(mbase + PECFG_POM0LAL, (CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE)); + + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + case 1: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + case 2: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + } + + /* Set up 16GB inbound memory window at 0 */ + out_le32(mbase + PCI_BASE_ADDRESS_0, 0); + out_le32(mbase + PCI_BASE_ADDRESS_1, 0); + out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); + out_le32(mbase + PECFG_BAR0LMPA, 0); + out_le32(mbase + PECFG_PIM0LAL, 0); + out_le32(mbase + PECFG_PIM0LAH, 0); + out_le32(mbase + PECFG_PIMEN, 0x1); + + /* Enable I/O, Mem, and Busmaster cycles */ + out_le16((u16 *)(mbase + PCI_COMMAND), + in_le16((u16 *)(mbase + PCI_COMMAND)) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); +} +#endif /* CONFIG_PCI */ +#endif /* CONFIG_440SPE */ diff --git a/cpu/ppc4xx/440spe_pcie.h b/cpu/ppc4xx/440spe_pcie.h new file mode 100644 index 00000000000..47df7620a6d --- /dev/null +++ b/cpu/ppc4xx/440spe_pcie.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * Roland Dreier + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#ifndef __440SPE_PCIE_H +#define __440SPE_PCIE_H + +#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);}) + +#define DCRN_SDR0_CFGADDR 0x00e +#define DCRN_SDR0_CFGDATA 0x00f + +#define DCRN_PCIE0_BASE 0x100 +#define DCRN_PCIE1_BASE 0x120 +#define DCRN_PCIE2_BASE 0x140 +#define PCIE0 DCRN_PCIE0_BASE +#define PCIE1 DCRN_PCIE1_BASE +#define PCIE2 DCRN_PCIE2_BASE + +#define DCRN_PEGPL_CFGBAH(base) (base + 0x00) +#define DCRN_PEGPL_CFGBAL(base) (base + 0x01) +#define DCRN_PEGPL_CFGMSK(base) (base + 0x02) +#define DCRN_PEGPL_MSGBAH(base) (base + 0x03) +#define DCRN_PEGPL_MSGBAL(base) (base + 0x04) +#define DCRN_PEGPL_MSGMSK(base) (base + 0x05) +#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06) +#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07) +#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08) +#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09) +#define DCRN_PEGPL_REGBAH(base) (base + 0x12) +#define DCRN_PEGPL_REGBAL(base) (base + 0x13) +#define DCRN_PEGPL_REGMSK(base) (base + 0x14) +#define DCRN_PEGPL_SPECIAL(base) (base + 0x15) + +/* + * System DCRs (SDRs) + */ +#define PESDR0_PLLLCT1 0x03a0 +#define PESDR0_PLLLCT2 0x03a1 +#define PESDR0_PLLLCT3 0x03a2 + +#define PESDR0_UTLSET1 0x0300 +#define PESDR0_UTLSET2 0x0301 +#define PESDR0_DLPSET 0x0302 +#define PESDR0_LOOP 0x0303 +#define PESDR0_RCSSET 0x0304 +#define PESDR0_RCSSTS 0x0305 +#define PESDR0_HSSL0SET1 0x0306 +#define PESDR0_HSSL0SET2 0x0307 +#define PESDR0_HSSL0STS 0x0308 +#define PESDR0_HSSL1SET1 0x0309 +#define PESDR0_HSSL1SET2 0x030a +#define PESDR0_HSSL1STS 0x030b +#define PESDR0_HSSL2SET1 0x030c +#define PESDR0_HSSL2SET2 0x030d +#define PESDR0_HSSL2STS 0x030e +#define PESDR0_HSSL3SET1 0x030f +#define PESDR0_HSSL3SET2 0x0310 +#define PESDR0_HSSL3STS 0x0311 +#define PESDR0_HSSL4SET1 0x0312 +#define PESDR0_HSSL4SET2 0x0313 +#define PESDR0_HSSL4STS 0x0314 +#define PESDR0_HSSL5SET1 0x0315 +#define PESDR0_HSSL5SET2 0x0316 +#define PESDR0_HSSL5STS 0x0317 +#define PESDR0_HSSL6SET1 0x0318 +#define PESDR0_HSSL6SET2 0x0319 +#define PESDR0_HSSL6STS 0x031a +#define PESDR0_HSSL7SET1 0x031b +#define PESDR0_HSSL7SET2 0x031c +#define PESDR0_HSSL7STS 0x031d +#define PESDR0_HSSCTLSET 0x031e +#define PESDR0_LANE_ABCD 0x031f +#define PESDR0_LANE_EFGH 0x0320 + +#define PESDR1_UTLSET1 0x0340 +#define PESDR1_UTLSET2 0x0341 +#define PESDR1_DLPSET 0x0342 +#define PESDR1_LOOP 0x0343 +#define PESDR1_RCSSET 0x0344 +#define PESDR1_RCSSTS 0x0345 +#define PESDR1_HSSL0SET1 0x0346 +#define PESDR1_HSSL0SET2 0x0347 +#define PESDR1_HSSL0STS 0x0348 +#define PESDR1_HSSL1SET1 0x0349 +#define PESDR1_HSSL1SET2 0x034a +#define PESDR1_HSSL1STS 0x034b +#define PESDR1_HSSL2SET1 0x034c +#define PESDR1_HSSL2SET2 0x034d +#define PESDR1_HSSL2STS 0x034e +#define PESDR1_HSSL3SET1 0x034f +#define PESDR1_HSSL3SET2 0x0350 +#define PESDR1_HSSL3STS 0x0351 +#define PESDR1_HSSCTLSET 0x0352 +#define PESDR1_LANE_ABCD 0x0353 + +#define PESDR2_UTLSET1 0x0370 +#define PESDR2_UTLSET2 0x0371 +#define PESDR2_DLPSET 0x0372 +#define PESDR2_LOOP 0x0373 +#define PESDR2_RCSSET 0x0374 +#define PESDR2_RCSSTS 0x0375 +#define PESDR2_HSSL0SET1 0x0376 +#define PESDR2_HSSL0SET2 0x0377 +#define PESDR2_HSSL0STS 0x0378 +#define PESDR2_HSSL1SET1 0x0379 +#define PESDR2_HSSL1SET2 0x037a +#define PESDR2_HSSL1STS 0x037b +#define PESDR2_HSSL2SET1 0x037c +#define PESDR2_HSSL2SET2 0x037d +#define PESDR2_HSSL2STS 0x037e +#define PESDR2_HSSL3SET1 0x037f +#define PESDR2_HSSL3SET2 0x0380 +#define PESDR2_HSSL3STS 0x0381 +#define PESDR2_HSSCTLSET 0x0382 +#define PESDR2_LANE_ABCD 0x0383 + +/* + * UTL register offsets + */ +#define PEUTL_PBBSZ 0x20 +#define PEUTL_OPDBSZ 0x68 +#define PEUTL_IPHBSZ 0x70 +#define PEUTL_IPDBSZ 0x78 +#define PEUTL_OUTTR 0x90 +#define PEUTL_INTR 0x98 +#define PEUTL_PCTL 0xa0 +#define PEUTL_RCIRQEN 0xb8 + +/* + * Config space register offsets + */ +#define PECFG_BAR0LMPA 0x210 +#define PECFG_BAR0HMPA 0x214 +#define PECFG_PIMEN 0x33c +#define PECFG_PIM0LAL 0x340 +#define PECFG_PIM0LAH 0x344 +#define PECFG_POM0LAL 0x380 +#define PECFG_POM0LAH 0x384 + +#define SDR_READ(offset) ({\ + mtdcr(DCRN_SDR0_CFGADDR, offset); \ + mfdcr(DCRN_SDR0_CFGDATA);}) + +#define SDR_WRITE(offset, data) ({\ + mtdcr(DCRN_SDR0_CFGADDR, offset); \ + mtdcr(DCRN_SDR0_CFGDATA,data);}) + +int ppc440spe_init_pcie(void); +int ppc440spe_init_pcie_rootport(int port); +void yucca_setup_pcie_fpga_rootpoint(int port); +void ppc440spe_setup_pcie(struct pci_controller *hose, int port); +int yucca_pcie_card_present(int port); +int pcie_hose_scan(struct pci_controller *hose, int bus); +#endif /* __440SPE_PCIE_H */ diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index c5634570054..7d6990f9a87 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -31,7 +31,8 @@ COBJS = 405gp_pci.o 4xx_enet.o \ bedbug_405.o commproc.o \ cpu.o cpu_init.o i2c.o interrupts.o \ miiphy.o sdram.o serial.o \ - spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o + spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o \ + 440spe_pcie.o OBJS = $(AOBJS) $(COBJS) diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 71303bcc49f..bc51fbfdbed 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -315,6 +315,17 @@ int checkcpu (void) return 0; } +#if defined (CONFIG_440SPE) +int ppc440spe_revB() { + unsigned int pvr; + + pvr = get_pvr(); + if (pvr == PVR_440SPe_RB) + return 1; + else + return 0; +} +#endif /* ------------------------------------------------------------------------- */ diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 0a6f81de449..6d6d75fd30f 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -315,7 +315,23 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ /*----------------------------------------------------------------*/ /* TLB entry setup -- step thru tlbtab */ /*----------------------------------------------------------------*/ +#if defined(CONFIG_440SPE) + /*----------------------------------------------------------------*/ + /* We have different TLB tables for revA and rev B of 440SPe */ + /*----------------------------------------------------------------*/ + mfspr r1, PVR + lis r0,0x5342 + ori r0,r0,0x1891 + cmpw r7,r1,r0 + bne r7,..revA + bl tlbtabB + b ..goon +..revA: + bl tlbtabA +..goon: +#else bl tlbtab /* Get tlbtab pointer */ +#endif mr r5,r0 li r1,0x003f /* 64 TLB entries max */ mtctr r1 diff --git a/include/common.h b/include/common.h index 6d7c41ad2b6..5f00f91f3fb 100644 --- a/include/common.h +++ b/include/common.h @@ -244,6 +244,9 @@ void pciinfo (int, int); void pci_master_init (struct pci_controller *); # endif int is_pci_host (struct pci_controller *); +#if defined(CONFIG_440SPE) + void pcie_setup_hoses(void); +#endif #endif int misc_init_f (void); @@ -461,6 +464,7 @@ void get_sys_info ( sys_info_t * ); # if defined(CONFIG_440SPE) unsigned long determine_sysper(void); unsigned long determine_pci_clock_per(void); + int ppc440spe_revB(void); # endif # else typedef PPC405_SYS_INFO sys_info_t; diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 0e58e7e1024..9dd9e5eae48 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -63,17 +63,26 @@ #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PCI_MEMBASE1 0x90000000 /* mapped pci memory */ -#define CFG_PCI_MEMBASE2 0xa0000000 /* mapped pci memory */ -#define CFG_PCI_MEMBASE3 0xb0000000 /* mapped pci memory */ - +#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ -#define CFG_PCI_TARGBASE 0x80000000 /*PCIaddr mapped to CFG_PCI_MEMBASE*/ +#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE + +#define CFG_PCIE_MEMBASE 0xB0000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x01000000 -/* #define CFG_PCI_BASE_IO 0xB8000000 */ /* internal PCI I-O */ -/* #define CFG_PCI_BASE_REGS 0xBEC00000 */ /* internal PCI regs */ -/* #define CFG_PCI_BASE_CYCLE 0xBED00000 */ /* internal PCI regs */ +#define CFG_PCIE0_CFGBASE 0xc0000000 +#define CFG_PCIE0_XCFGBASE 0xc0000400 +#define CFG_PCIE1_CFGBASE 0xc0001000 +#define CFG_PCIE1_XCFGBASE 0xc0001400 +#define CFG_PCIE2_CFGBASE 0xc0002000 +#define CFG_PCIE2_XCFGBASE 0xc0002400 + +#define CFG_PCIE0_REGBASE 0xc0003000 +#define CFG_PCIE1_REGBASE 0xc0003400 +#define CFG_PCIE2_REGBASE 0xc0004000 +#define CFG_PCIE3_REGBASE 0xc0004400 +#define CFG_PCIE4_REGBASE 0xc0005000 +#define CFG_PCIE5_REGBASE 0xc0005400 /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE @@ -292,6 +301,7 @@ */ /* Support for Intel 82557/82559/82559ER chips. */ #define CONFIG_EEPRO100 + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -506,8 +516,8 @@ #define FPGA_REG1C_PE1_WAKE 0x0040 #define FPGA_REG1C_PE2_WAKE 0x0020 #define FPGA_REG1C_PE0_PERST 0x0010 -#define FPGA_REG1C_PE1_PERST 0x0080 -#define FPGA_REG1C_PE2_PERST 0x0040 +#define FPGA_REG1C_PE1_PERST 0x0008 +#define FPGA_REG1C_PE2_PERST 0x0004 /*----------------------------------------------------------------------------+ | Defines -- cgit v1.3.1 From 36b904a7fdc170a69eb94975b0e506dc2a73fa82 Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Fri, 11 Aug 2006 12:35:52 +0200 Subject: Fix PCI-Express on PPC440SPe rev. A. --- CHANGELOG | 2 ++ board/amcc/yucca/init.S | 23 ++++++++--------------- board/amcc/yucca/yucca.c | 1 + cpu/ppc4xx/440spe_pcie.c | 27 +++++++++++++-------------- include/configs/yucca.h | 10 ++-------- 5 files changed, 26 insertions(+), 37 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 0c70d3cfcdb..88c7a103955 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix PCI-Express on PPC440SPe rev. A. + * Add initial support for PCI-Express on PPC440SPe (Yucca board). * Fix timer problems on AMCC yucca board. diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S index a950eac44f9..48e2ec277ca 100644 --- a/board/amcc/yucca/init.S +++ b/board/amcc/yucca/init.S @@ -105,17 +105,14 @@ tlbtabA: tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - - tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_XCFGBASE, SZ_4K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_XCFGBASE, SZ_4K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_XCFGBASE, SZ_4K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) - - tlbentry(CFG_PCIE1_REGBASE, SZ_1K, 0x60000400, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE3_REGBASE, SZ_1K, 0x60001400, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE5_REGBASE, SZ_1K, 0x60002400, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbtab_end /************************************************************************** @@ -152,8 +149,4 @@ tlbtabB: tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) - - tlbentry(CFG_PCIE1_REGBASE, SZ_1K, 0x60000400, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE3_REGBASE, SZ_1K, 0x60001400, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE5_REGBASE, SZ_1K, 0x60002400, 0xD, AC_R|AC_W|SA_G|SA_I) tlbtab_end diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index a6589ec262a..af12839c2c3 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -1032,6 +1032,7 @@ void pcie_setup_hoses(void) continue; yucca_setup_pcie_fpga_rootpoint(i); + if (ppc440spe_init_pcie_rootport(i)) { printf("PCIE%d: initialization failed\n", i); continue; diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c index cbc93dd0228..2e920aadf01 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/440spe_pcie.c @@ -148,30 +148,28 @@ static void ppc440spe_setup_utl(u32 port) { */ switch (port) { case 0: - mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000d); - mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x60000400); - mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xFFFFFC01); + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); - utl_base = (unsigned int *)(CFG_PCIE1_REGBASE); break; case 1: - mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x60001400); - mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xFFFFFC01); + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); - utl_base = (unsigned int *)(CFG_PCIE3_REGBASE); break; case 2: - mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x60002400); - mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0xFFFFFC01); + mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001); mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); - utl_base = (unsigned int *)(CFG_PCIE5_REGBASE); break; } - + utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port); + /* * Set buffer allocations and then assert VRB and TXE. */ @@ -182,7 +180,7 @@ static void ppc440spe_setup_utl(u32 port) { out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); - out_be32(utl_base + PEUTL_PCTL, 0x8080007d); + out_be32(utl_base + PEUTL_PCTL, 0x80800066); } static int check_error(void) @@ -420,6 +418,7 @@ int ppc440spe_init_pcie_rootport(int port) * PCIE1: 0xd_2000_0000 * PCIE2: 0xd_4000_0000 */ + switch (port) { case 0: if (ppc440spe_revB()) { diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 9dd9e5eae48..26a330eea71 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -67,8 +67,9 @@ #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE -#define CFG_PCIE_MEMBASE 0xB0000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ #define CFG_PCIE_MEMSIZE 0x01000000 +#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 #define CFG_PCIE0_XCFGBASE 0xc0000400 @@ -77,13 +78,6 @@ #define CFG_PCIE2_CFGBASE 0xc0002000 #define CFG_PCIE2_XCFGBASE 0xc0002400 -#define CFG_PCIE0_REGBASE 0xc0003000 -#define CFG_PCIE1_REGBASE 0xc0003400 -#define CFG_PCIE2_REGBASE 0xc0004000 -#define CFG_PCIE3_REGBASE 0xc0004400 -#define CFG_PCIE4_REGBASE 0xc0005000 -#define CFG_PCIE5_REGBASE 0xc0005400 - /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE -- cgit v1.3.1 From 015c200b1f9ae9b986b8c02130fb8572d6d3970c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 11 Aug 2006 17:29:38 +0200 Subject: Adapt TQM85xx ramdisk address to Linux kernel memory map --- CHANGELOG | 2 ++ include/configs/TQM85xx.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index a586c7736e4..2a8519135e7 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Adapt TQM85xx ramdisk address to Linux kernel memory map + * Add initial support for PCI-Express on PPC440SPe (Yucca board). * Fix compiler warning for TRAB board. diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 780f27433e6..2e64e11cdb8 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -449,7 +449,7 @@ "run nfsargs addip addcons;bootm\0" \ "rootpath=/opt/eldk/ppc_85xx\0" \ "kernel_addr=FE000000\0" \ - "ramdisk_addr=FE100000\0" \ + "ramdisk_addr=FE180000\0" \ "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ -- cgit v1.3.1 From d8519dc7187a5a1d33f39a5381747430267e12be Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 11 Aug 2006 17:33:42 +0200 Subject: Fix preboot message on TQM85xx after switching to hush parser. --- CHANGELOG | 2 ++ include/configs/TQM85xx.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 2a8519135e7..596e89405e4 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix preboot message on TQM85xx after switching to hush parser. + * Adapt TQM85xx ramdisk address to Linux kernel memory map * Add initial support for PCI-Express on PPC440SPe (Yucca board). diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 2e64e11cdb8..bc3b9aa1d0a 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -424,7 +424,7 @@ #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -- cgit v1.3.1 From 80f0c0f58f6a39f893101d14a79169504e3c93fd Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 14 Aug 2006 22:05:26 +0200 Subject: Fix fatload command on FAT32 formatted partitions. Patch by Joachim Jaeger, 18 Nov 2005 --- CHANGELOG | 3 +++ include/fat.h | 8 ++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 2247a24af44..6c8043ff7c1 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix fatload command on FAT32 formatted partitions. + Patch by Joachim Jaeger, 18 Nov 2005 + * Fix drivers/dm9000.c when configured in 32 bit mode. Patch by Eric Benard, 17 Nov 2005 diff --git a/include/fat.h b/include/fat.h index 0645458f17b..92638d535e4 100644 --- a/include/fat.h +++ b/include/fat.h @@ -175,15 +175,19 @@ typedef struct dir_slot { __u8 name11_12[4]; /* Last 2 characters in name */ } dir_slot; -/* Private filesystem parameters */ +/* Private filesystem parameters + * + * Note: FAT buffer has to be 32 bit aligned + * (see FAT32 accesses) + */ typedef struct { + __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */ int fatsize; /* Size of FAT in bits */ __u16 fatlength; /* Length of FAT in sectors */ __u16 fat_sect; /* Starting sector of the FAT */ __u16 rootdir_sect; /* Start sector of root directory */ __u16 clust_size; /* Size of clusters in sectors */ short data_begin; /* The sector of the first cluster, can be negative */ - __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */ int fatbufnum; /* Used by get_fatent, init to -1 */ } fsdata; -- cgit v1.3.1 From 2f6fa46d4149f62f0e8686d5005da2beeba9e243 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 14 Aug 2006 23:17:47 +0200 Subject: Fixed common.h spelling error. Patch by Cory Tusar, 30 Nov 2005 --- CHANGELOG | 3 +++ include/common.h | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 2ddc67d71a2..206c441096e 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fixed common.h spelling error. + Patch by Cory Tusar, 30 Nov 2005 + * Fix typo. Patch by Andreas Engel, 28 Nov 2005 diff --git a/include/common.h b/include/common.h index bd41ae179ae..9a19001c18d 100644 --- a/include/common.h +++ b/include/common.h @@ -603,7 +603,7 @@ void show_boot_progress (int status); #endif #ifdef CONFIG_INIT_CRITICAL -#error CONFIG_INIT_CRITICAL is depracted! +#error CONFIG_INIT_CRITICAL is deprecated! #error Read section CONFIG_SKIP_LOWLEVEL_INIT in README. #endif -- cgit v1.3.1 From fecf1c7e4de1b2779edc18742b91c22bdc32b68b Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 14 Aug 2006 15:33:38 -0500 Subject: Fix BAT0 to actually be cacheable, non-guarded as documented. Signed-off-by: Jon Loeliger --- include/configs/MPC8641HPCN.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 15e987139ad..200a38f3e89 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -378,10 +378,9 @@ * BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR */ -#define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) -#define CFG_DBAT0U ( BATU_BL_2G | BATU_VS | BATU_VP ) -#define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) +#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) #define CFG_IBAT0U CFG_DBAT0U /* -- cgit v1.3.1 From 25c751e9adc86e22fe3b5b47cf2806379b575db7 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 16 Aug 2006 10:54:09 -0500 Subject: * Support for FDT in uImage format, error when using FDT from flash Signed-off-by: Matthew McClintock --- common/cmd_bootm.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++---- include/image.h | 1 + tools/mkimage.c | 1 + 3 files changed, 67 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index f1c0eb4d183..6eb258ec2bf 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -528,7 +528,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, void (*kernel)(bd_t *, ulong, ulong, ulong, ulong); image_header_t *hdr = &header; #ifdef CONFIG_OF_FLAT_TREE - char *of_flat_tree; + char *of_flat_tree = NULL; #endif if ((s = getenv ("initrd_high")) != NULL) { @@ -737,14 +737,73 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, } #ifdef CONFIG_OF_FLAT_TREE - if (argc >= 3) - { + if(argc >= 3) { of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16); - printf ("Booting using flat device tree at 0x%x\n", + hdr = (image_header_t *)of_flat_tree; + + if (*(ulong *)of_flat_tree == OF_DT_HEADER) { +#ifndef CFG_NO_FLASH + if (addr2info((ulong)of_flat_tree) != NULL) { + printf ("Cannot modify flat device tree stored in flash\n" \ + "Copy to memory before using the bootm command\n"); + return; + } +#endif + } else if (ntohl(hdr->ih_magic) == IH_MAGIC) { + printf("## Flat Device Tree Image at %08lX\n", hdr); + print_image_hdr(hdr); + + if ((ntohl(hdr->ih_load) < ((unsigned long)hdr + ntohl(hdr->ih_size) + sizeof(hdr))) && + ((ntohl(hdr->ih_load) + ntohl(hdr->ih_size)) > (unsigned long)hdr)) { + printf ("ERROR: Load address overwrites Flat Device Tree uImage\n"); + return; + } + + printf(" Verifying Checksum ... "); + memmove (&header, (char *)hdr, sizeof(image_header_t)); + checksum = ntohl(header.ih_hcrc); + header.ih_hcrc = 0; + + if(checksum != crc32(0, (uchar *)&header, sizeof(image_header_t))) { + printf("ERROR: Flat Device Tree header checksum is invalid\n"); + return; + } + + checksum = ntohl(hdr->ih_dcrc); + addr = (ulong)((uchar *)(hdr) + sizeof(image_header_t)); + len = ntohl(hdr->ih_size); + + if(checksum != crc32(0, (uchar *)addr, len)) { + printf("ERROR: Flat Device Tree checksum is invalid\n"); + return; + } + printf("OK\n"); + + if (ntohl(hdr->ih_type) != IH_TYPE_FLATDT) { + printf ("ERROR: uImage not Flat Device Tree type\n"); + return; + } + if (ntohl(hdr->ih_comp) != IH_COMP_NONE) { + printf("ERROR: uImage is not uncompressed\n"); + return; + } + if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) { + printf ("ERROR: uImage data is not a flat device tree\n"); + return; + } + + memmove((void *)ntohl(hdr->ih_load), + (void *)(of_flat_tree + sizeof(image_header_t)), + ntohl(hdr->ih_size)); + of_flat_tree = (char *)ntohl(hdr->ih_load); + } else { + printf ("Did not find a flat flat device tree at address %08lX\n", of_flat_tree); + return; + } + printf (" Booting using flat device tree at 0x%x\n", of_flat_tree); } #endif - if (!data) { debug ("No initrd\n"); } @@ -1272,6 +1331,7 @@ print_type (image_header_t *hdr) case IH_TYPE_MULTI: type = "Multi-File Image"; break; case IH_TYPE_FIRMWARE: type = "Firmware"; break; case IH_TYPE_SCRIPT: type = "Script"; break; + case IH_TYPE_FLATDT: type = "Flat Device Tree"; break; default: type = "Unknown Image"; break; } diff --git a/include/image.h b/include/image.h index 139df0b2d1e..ea7e9531dc7 100644 --- a/include/image.h +++ b/include/image.h @@ -124,6 +124,7 @@ #define IH_TYPE_FIRMWARE 5 /* Firmware Image */ #define IH_TYPE_SCRIPT 6 /* Script file */ #define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ +#define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ /* * Compression Types diff --git a/tools/mkimage.c b/tools/mkimage.c index fea3e5bc6b3..d6000e04bf5 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -130,6 +130,7 @@ table_entry_t type_name[] = { { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, { IH_TYPE_SCRIPT, "script", "Script", }, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, + { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, { -1, "", "", }, }; -- cgit v1.3.1 From 463764c893a657124eb2818e3103a04171bcbda1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 17 Aug 2006 00:36:51 +0200 Subject: Add debug console on COM12 for MCC200 board --- CHANGELOG | 2 ++ Makefile | 5 +++++ include/configs/mcc200.h | 9 +++++++-- 3 files changed, 14 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 24499c5621a..727d7ec7aed 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add debug console on COM12 for MCC200 board + * Fix control-c handing in CONFIG_CMDLINE_EDITING Properly pass break code back from readline. Patch by Roger Blofeld, 31 Jul 2006 diff --git a/Makefile b/Makefile index 128ae59a066..4d579d9bd35 100644 --- a/Makefile +++ b/Makefile @@ -325,6 +325,7 @@ lite5200b_LOWBOOT_config: unconfig mcc200_config \ mcc200_SDRAM \ mcc200_highboot \ +mcc200_COM12 \ mcc200_highboot_SDRAM: unconfig @ >include/config.h @[ -n "$(findstring highboot,$@)" ] || \ @@ -341,6 +342,10 @@ mcc200_highboot_SDRAM: unconfig { echo "#define CONFIG_MCC200_SDRAM" >>include/config.h ; \ echo "... with SDRAM" ; \ } + @[ -z "$(findstring COM12,$@)" ] || \ + { echo "#define CONFIG_CONSOLE_COM12" >>include/config.h ; \ + echo "... with console on COM12" ; \ + } @./mkconfig -a mcc200 ppc mpc5xxx mcc200 o2dnt_config: diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index ce33b85c96d..563f7978d5f 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -51,15 +51,20 @@ * To select console on the one of 8 external UARTs, * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART, * or as 5, 6, 7, or 8 for the second Quad UART. + * COM11, COM12, COM13, COM14 are located on the second Quad UART. * * CONFIG_PSC_CONSOLE must be undefined in this case. */ -/* #define CONFIG_QUART_CONSOLE 1 */ /* console is on UART1 of QUART1 */ +#ifdef CONFIG_CONSOLE_COM12 +#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */ +#else +#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */ +#endif /* * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1 * and undefine CONFIG_QUART_CONSOLE. */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +/*#define CONFIG_PSC_CONSOLE 1 */ /* console is on PSC1 */ #if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) #error "Select only one console device!" #endif -- cgit v1.3.1 From 0a0f3a46fb5cfa7105402bee9c52dd379325d156 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 17 Aug 2006 10:48:36 +0200 Subject: Cleanup debug code for yucca board. --- CHANGELOG | 2 ++ include/configs/yucca.h | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index a3b4b239f92..961e073e4c2 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Cleanup debug code for yucca board. + * MCC200: restrict addressable flash space to 32 MB * Add debug console on COM12 for MCC200 board diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 884f85c31e9..a6532b5e853 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -31,9 +31,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define DEBUG -#undef DEBUG - /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -- cgit v1.3.1 From 6fe16a8769a3c8923dea24a7ed9ff7f1f89c3bef Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Fri, 18 Aug 2006 10:39:11 +0200 Subject: Fix TQM834x hang. --- CHANGELOG | 2 ++ include/configs/TQM834x.h | 19 ++++++++++++++----- 2 files changed, 16 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 961e073e4c2..05d33b4e2d8 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix TQM834x hang. + * Cleanup debug code for yucca board. * MCC200: restrict addressable flash space to 32 MB diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index cec7e3ece44..92c7016e6bc 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -422,9 +422,9 @@ extern int tqm834x_num_flash_banks; #define CFG_SICRL SICRL_LDP_A /* i-cache and d-cache disabled */ -#define CFG_HID0_INIT 0x000000000 -#define CFG_HID0_FINAL CFG_HID0_INIT -#define CFG_HID2 0x000000000 +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT +#define CFG_HID2 HID2_HBE /* DDR 0 - 512M */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) @@ -437,12 +437,21 @@ extern int tqm834x_num_flash_banks; #define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) /* PCI */ -#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#ifdef CONFIG_PCI +#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT3L (0) +#define CFG_IBAT3U (0) +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) +#define CFG_IBAT5L (0) +#define CFG_IBAT5U (0) +#endif /* IMMRBAR */ #define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -- cgit v1.3.1 From 6d3bc9b8cfd5d60708f95ded007cda7bc29ac089 Mon Sep 17 00:00:00 2001 From: Marian Balakowicz Date: Fri, 18 Aug 2006 19:14:46 +0200 Subject: Add support for WTK FO300 board (TQM5200 based). --- CHANGELOG | 2 ++ MAKEALL | 2 +- Makefile | 7 ++++- board/tqm5200/cmd_stk52xx.c | 27 +++++++++++++++++-- board/tqm5200/tqm5200.c | 64 ++++++++++++++++++++++++++++++++++++++++++++- include/configs/TQM5200.h | 55 ++++++++++++++++++++++++++++++++------ include/mpc5xxx.h | 10 +++++++ 7 files changed, 154 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index e40de367466..82be4e3d779 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add support for WTK FO300 board (TQM5200 based). + * Fix TQM834x hang. * Update for SC520 board. diff --git a/MAKEALL b/MAKEALL index 467a9bee0a7..48eeaaacf66 100755 --- a/MAKEALL +++ b/MAKEALL @@ -29,7 +29,7 @@ LIST_5xxx=" \ icecube_5200 lite5200b mcc200 o2dnt \ pf5200 PM520 TB5200 Total5100 \ Total5200 Total5200_Rev2 TQM5200 TQM5200_B \ - TQM5200S \ + TQM5200S fo300 \ " ######################################################################### diff --git a/Makefile b/Makefile index 4d579d9bd35..4cc7a48ba32 100644 --- a/Makefile +++ b/Makefile @@ -424,8 +424,13 @@ TQM5200S_config \ TQM5200S_HIGHBOOT_config \ TQM5200_STK100_config \ cam5200_config \ -MiniFAP_config: unconfig +MiniFAP_config \ +fo300_config: unconfig @ >include/config.h + @[ -z "$(findstring fo300,$@)" ] || \ + { echo "#define CONFIG_FO300" >>include/config.h ; \ + echo "... TQM5200 on FO300" ; \ + } @[ -z "$(findstring MiniFAP,$@)" ] || \ { echo "#define CONFIG_MINIFAP" >>include/config.h ; \ echo "... TQM5200_AC on MiniFAP" ; \ diff --git a/board/tqm5200/cmd_stk52xx.c b/board/tqm5200/cmd_stk52xx.c index c37d4c662ef..7af69f21a23 100755 --- a/board/tqm5200/cmd_stk52xx.c +++ b/board/tqm5200/cmd_stk52xx.c @@ -30,8 +30,8 @@ #include #if (CONFIG_COMMANDS & CFG_CMD_BSP) -#if defined (CONFIG_STK52XX) +#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) #define DEFAULT_VOL 45 #define DEFAULT_FREQ 500 #define DEFAULT_DURATION 200 @@ -537,7 +537,9 @@ static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return rcode; } +#endif +#if defined(CONFIG_STK52XX) void led_init(void) { struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; @@ -736,7 +738,9 @@ int do_led(char *argv[]) return 0; } +#endif +#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) /* * return 1 on CAN initialization failure * return 0 if no failure @@ -1106,6 +1110,7 @@ int do_rs232(char *argv[]) return error_status; } +#ifndef CONFIG_FO300 static void sm501_backlight (unsigned int state) { if (state == BL_ON) { @@ -1115,6 +1120,7 @@ static void sm501_backlight (unsigned int state) *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= ~((1 << 26) | (1 << 27)); } +#endif int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -1124,7 +1130,9 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf ("Revision 100 of STK52XX not supported!\n"); return 1; #endif +#if defined(CONFIG_STK52XX) led_init(); +#endif can_init(); switch (argc) { @@ -1152,6 +1160,7 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else printf ("Error\n"); return rcode; +#ifndef CONFIG_FO300 } else if (strncmp (argv[1], "backlight", 4) == 0) { if (strncmp (argv[2], "on", 2) == 0) { sm501_backlight (BL_ON); @@ -1161,14 +1170,17 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) sm501_backlight (BL_OFF); return 0; } +#endif } break; +#if defined(CONFIG_STK52XX) case 4: if (strcmp (argv[1], "led") == 0) { return (do_led (argv)); } break; +#endif default: break; @@ -1204,7 +1216,9 @@ U_BOOT_CMD( "[channel]\n" " - play short beep on \"l\"eft or \"r\"ight channel\n" ); +#endif /* CONFIG_STK52XX || CONFIG_FO300 */ +#if defined(CONFIG_STK52XX) U_BOOT_CMD( fkt , 4, 1, cmd_fkt, "fkt - Function test routines\n", @@ -1217,5 +1231,14 @@ U_BOOT_CMD( "fkt backlight on/off\n" " - switch backlight on or off\n" ); -#endif /* CONFIG_STK52XX */ +#elif defined(CONFIG_FO300) +U_BOOT_CMD( + fkt , 3, 1, cmd_fkt, + "fkt - Function test routines\n", + "fkt can\n" + " - loopback plug for X16/X29 required\n" + "fkt rs232 number\n" + " - loopback plug(s) for X21/X22 required\n" +); +#endif #endif /* CFG_CMD_BSP */ diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index d6f7737d5bd..0026e086cbb 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -290,6 +290,8 @@ int checkboard (void) # define CARRIER_NAME "TB5200" #elif defined(CONFIG_CAM5200) # define CARRIER_NAME "Cam5200" +#elif defined(CONFIG_FO300) +# define CARRIER_NAME "FO300" #else # error "Unknown carrier board" #endif @@ -541,7 +543,11 @@ int last_stage_init (void) #ifdef CONFIG_VIDEO_SM501 +#ifdef CONFIG_FO300 +#define DISPLAY_WIDTH 800 +#else #define DISPLAY_WIDTH 640 +#endif #define DISPLAY_HEIGHT 480 #ifdef CONFIG_VIDEO_SM501_8BPP @@ -571,6 +577,28 @@ static const SMI_REGS init_regs [] = {0x80218, 0x000201e9}, {0x80200, 0x00013306}, #else /* panel + CRT */ +#ifdef CONFIG_FO300 + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x301a0a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x091a0a01}, + {0x00054, 0x0}, + {0x80000, 0x0f013106}, + {0x80004, 0xc428bb17}, + {0x8000C, 0x00000000}, + {0x80010, 0x0C800C80}, + {0x80014, 0x03200000}, + {0x80018, 0x01e00000}, + {0x8001C, 0x00000000}, + {0x80020, 0x01e00320}, + {0x80024, 0x042a031f}, + {0x80028, 0x0086034a}, + {0x8002C, 0x020c01df}, + {0x80030, 0x000201ea}, + {0x80200, 0x00010000}, +#else {0x00004, 0x0}, {0x00048, 0x00021807}, {0x0004C, 0x091a0a01}, @@ -591,6 +619,7 @@ static const SMI_REGS init_regs [] = {0x8002C, 0x020c01df}, {0x80030, 0x000201e9}, {0x80200, 0x00010000}, +#endif /* #ifdef CONFIG_FO300 */ #endif {0, 0} }; @@ -604,7 +633,7 @@ void video_get_info_str (int line_number, char *info) { if (line_number == 1) { strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); -#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) +#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300) } else if (line_number == 2) { #if defined (CONFIG_STK52XX) strcpy (info, " on a STK52xx carrier board"); @@ -612,6 +641,9 @@ void video_get_info_str (int line_number, char *info) #if defined (CONFIG_TB5200) strcpy (info, " on a TB5200 carrier board"); #endif +#if defined (CONFIG_FO300) + strcpy (info, " on a FO300 carrier board"); +#endif #endif } else { @@ -697,3 +729,33 @@ int board_get_height (void) } #endif /* CONFIG_VIDEO_SM501 */ + + +#ifdef CONFIG_BOARD_EARLY_INIT_F +#ifdef CONFIG_FO300 +int board_early_init_f (void) +{ + vu_long timer3_status; + DECLARE_GLOBAL_DATA_PTR; + + /* Configure GPT3 as GPIO input */ + *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004; + + /* Read in TIMER_3 pin status */ + timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS; + +#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED + /* Force silent console mode if S1 switch + * is in closed position (TIMER_3 pin status is LOW). */ + if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0) +#else + /* Force silent console mode if S1 switch + * is in open position (TIMER_3 pin status is HIGH). */ + if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1) +#endif + gd->flags |= GD_FLG_SILENT; + + return 0; +} +#endif +#endif diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index be83b676720..f157d42fce3 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -37,7 +37,8 @@ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -#ifndef CONFIG_CAM5200 /* On a Cameron board or ... */ +/* On a Cameron board or on a FO300 board or ... */ +#if !defined(CONFIG_CAM5200) && !defined(CONFIG_FO300) #define CONFIG_STK52XX 1 /* ... on a STK52XX board */ #endif @@ -58,6 +59,20 @@ #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#ifdef CONFIG_FO300 +#define CFG_DEVICE_NULLDEV 1 /* enable null device */ +#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */ + +#if 0 +#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */ + /* switch is closed */ +#endif + +#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */ + /* switch is open */ +#endif + #ifdef CONFIG_STK52XX #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ @@ -105,12 +120,18 @@ #define CONFIG_VIDEO_SM501_32BPP #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE + +#ifndef CONFIG_FO300 #define CONFIG_CONSOLE_EXTRA_INFO +#else +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_SPLASH_SCREEN #define CFG_CONSOLE_IS_IN_ENV -#endif +#endif /* #ifndef CONFIG_TQM5200S */ #ifdef CONFIG_VIDEO #define ADD_BMP_CMD CFG_CMD_BMP @@ -124,7 +145,7 @@ #define CONFIG_ISO_PARTITION /* USB */ -#ifdef CONFIG_STK52XX +#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) #define CONFIG_USB_OHCI #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE @@ -148,7 +169,7 @@ #endif /* IDE */ -#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) +#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) || defined(CONFIG_FO300) #define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) #else #define ADD_IDE_CMD 0 @@ -224,6 +245,12 @@ "erase FC000000 FC03FFFF;" \ "cp.b 200000 FC000000 ${filesize};" \ "protect on FC000000 FC03FFFF\0" +#elif defined (CONFIG_FO300) +# define ENV_UPDT \ + "update=protect off FC000000 FC05FFFF;" \ + "erase FC000000 FC05FFFF;" \ + "cp.b 200000 FC000000 ${filesize};" \ + "protect on FC000000 FC05FFFF\0" #else # error "Unknown Carrier Board" #endif /* CONFIG_STK52XX */ @@ -378,6 +405,13 @@ "2m(initrd)," \ "8m(misc)," \ "16m(big-fs)" +#elif defined (CONFIG_FO300) +# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ + "1408k(kernel)," \ + "2m(initrd)," \ + "4m(small-fs)," \ + "8m(misc)," \ + "16m(big-fs)" #else # error "Unknown Carrier Board" #endif /* CONFIG_STK52XX */ @@ -450,15 +484,18 @@ * use ALT CAN position: Bits 2-3 (mask: 0x30000000): * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) + * Use for REV200 STK52XX boards and FO300 boards. Do not use + * with REV100 modules (because, there I2C1 is used as I2C bus) * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) * 000 -> All PSC2 pins are GIOPs * 001 -> CAN1/2 on PSC2 pins * Use for REV100 STK52xx boards + * 01x -> Use AC97 + * use PSC3: Bits 20-23 (mask: 0x00000f00) + * 1100 -> UART/SPI (on FO300 board) * use PSC6: - * on STK52xx: + * on STK52xx and FO300: * use as UART. Pins PSC6_0 to PSC6_3 are used. * Bits 9:11 (mask: 0x00700000): * 101 -> PSC6 : Extended POST test is not available @@ -480,6 +517,8 @@ # define CFG_GPS_PORT_CONFIG 0x91500004 # endif # endif +#elif defined (CONFIG_FO300) +# define CFG_GPS_PORT_CONFIG 0x91502c24 #else /* TMQ5200 Inbetriebnahme-Board */ # define CFG_GPS_PORT_CONFIG 0x81000004 #endif diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index 50a6ac1e98d..daa4d5f6d4c 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -235,20 +235,30 @@ /* General Purpose Timers registers */ #define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0) #define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4) +#define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C) #define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10) #define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14) +#define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C) #define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20) #define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24) +#define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C) #define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30) #define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34) +#define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C) #define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40) #define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44) +#define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C) #define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50) +#define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C) #define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54) #define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60) #define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64) +#define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C) #define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70) #define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74) +#define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C) + +#define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8) #define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78) -- cgit v1.3.1 From 5196a7a03bc436435787e1ad7044af94d93a5448 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 18 Aug 2006 23:27:33 +0200 Subject: Minor cleanup --- MAKEALL | 10 +++++----- Makefile | 26 +++++++++++++------------- board/tqm5200/tqm5200.c | 2 +- include/configs/TQM5200.h | 4 ++-- 4 files changed, 21 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/MAKEALL b/MAKEALL index 48eeaaacf66..720ab03bd37 100755 --- a/MAKEALL +++ b/MAKEALL @@ -25,11 +25,11 @@ LIST_5xx=" \ ######################################################################### LIST_5xxx=" \ - BC3450 cpci5200 EVAL5200 icecube_5100 \ - icecube_5200 lite5200b mcc200 o2dnt \ - pf5200 PM520 TB5200 Total5100 \ - Total5200 Total5200_Rev2 TQM5200 TQM5200_B \ - TQM5200S fo300 \ + BC3450 cpci5200 EVAL5200 fo300 \ + icecube_5100 icecube_5200 lite5200b mcc200 \ + o2dnt pf5200 PM520 TB5200 \ + Total5100 Total5200 Total5200_Rev2 TQM5200 \ + TQM5200_B TQM5200S \ " ######################################################################### diff --git a/Makefile b/Makefile index 4cc7a48ba32..a78f35b6219 100644 --- a/Makefile +++ b/Makefile @@ -417,16 +417,22 @@ Total5200_Rev2_lowboot_config: unconfig } @./mkconfig -a Total5200 ppc mpc5xxx total5200 -TQM5200_config \ -TQM5200_B_config \ -TQM5200_B_HIGHBOOT_config \ -TQM5200S_config \ -TQM5200S_HIGHBOOT_config \ -TQM5200_STK100_config \ cam5200_config \ +fo300_config \ MiniFAP_config \ -fo300_config: unconfig +TQM5200S_config \ +TQM5200S_HIGHBOOT_config \ +TQM5200_B_config \ +TQM5200_B_HIGHBOOT_config \ +TQM5200_config \ +TQM5200_STK100_config: unconfig @ >include/config.h + @[ -z "$(findstring cam5200,$@)" ] || \ + { echo "#define CONFIG_CAM5200" >>include/config.h ; \ + echo "#define CONFIG_TQM5200S" >>include/config.h ; \ + echo "#define CONFIG_TQM5200_B" >>include/config.h ; \ + echo "... TQM5200S on Cam5200" ; \ + } @[ -z "$(findstring fo300,$@)" ] || \ { echo "#define CONFIG_FO300" >>include/config.h ; \ echo "... TQM5200 on FO300" ; \ @@ -435,12 +441,6 @@ fo300_config: unconfig { echo "#define CONFIG_MINIFAP" >>include/config.h ; \ echo "... TQM5200_AC on MiniFAP" ; \ } - @[ -z "$(findstring cam5200,$@)" ] || \ - { echo "#define CONFIG_CAM5200" >>include/config.h ; \ - echo "#define CONFIG_TQM5200S" >>include/config.h ; \ - echo "#define CONFIG_TQM5200_B" >>include/config.h ; \ - echo "... TQM5200S on Cam5200" ; \ - } @[ -z "$(findstring STK100,$@)" ] || \ { echo "#define CONFIG_STK52XX_REV100" >>include/config.h ; \ echo "... on a STK52XX.100 base board" ; \ diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 0026e086cbb..c8350ab3b5d 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -293,7 +293,7 @@ int checkboard (void) #elif defined(CONFIG_FO300) # define CARRIER_NAME "FO300" #else -# error "Unknown carrier board" +# error "UNKNOWN" #endif puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n" diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index f157d42fce3..31e3eed68c7 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -37,7 +37,7 @@ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -/* On a Cameron board or on a FO300 board or ... */ +/* On a Cameron or on a FO300 board or ... */ #if !defined(CONFIG_CAM5200) && !defined(CONFIG_FO300) #define CONFIG_STK52XX 1 /* ... on a STK52XX board */ #endif @@ -71,7 +71,7 @@ #undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */ /* switch is open */ -#endif +#endif /* CONFIG_FO300 */ #ifdef CONFIG_STK52XX #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -- cgit v1.3.1 From ddde6b7cf8341a15ad46551dc611488e9a3f36e6 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Tue, 22 Aug 2006 10:38:18 +0200 Subject: Add a fix for a buggy USB device on the FO300 board. --- CHANGELOG | 2 ++ common/usb_storage.c | 25 +++++++++++++++++++++++++ include/configs/TQM5200.h | 2 +- 3 files changed, 28 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 82be4e3d779..3c752d15996 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add a fix for a buggy USB device on the FO300 board. + * Add support for WTK FO300 board (TQM5200 based). * Fix TQM834x hang. diff --git a/common/usb_storage.c b/common/usb_storage.c index e64470cb91f..69ecf187842 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -916,6 +916,28 @@ static int usb_read_10(ccb *srb,struct us_data *ss, unsigned long start, unsigne } +#ifdef CONFIG_USB_BIN_FIXUP +/* + * Some USB storage devices queried for SCSI identification data respond with + * binary strings, which if output to the console freeze the terminal. The + * workaround is to modify the vendor and product strings read from such + * device with proper values (as reported by 'usb info'). + * + * Vendor and product length limits are taken from the definition of + * block_dev_desc_t in include/part.h. + */ +static void usb_bin_fixup(struct usb_device_descriptor descriptor, + unsigned char vendor[], + unsigned char product[]) { + const unsigned char max_vendor_len = 40; + const unsigned char max_product_len = 20; + if (descriptor.idVendor == 0x0424 && descriptor.idProduct == 0x223a) { + strncpy(vendor, "SMSC", max_vendor_len); + strncpy(product, "Flash Media Cntrller", max_product_len); + } +} +#endif /* CONFIG_USB_BIN_FIXUP */ + #define USB_MAX_READ_BLK 20 unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, unsigned long *buffer) @@ -1171,6 +1193,9 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t dev_desc->vendor[8] = 0; dev_desc->product[16] = 0; dev_desc->revision[4] = 0; +#ifdef CONFIG_USB_BIN_FIXUP + usb_bin_fixup(dev->descriptor, dev_desc->vendor, dev_desc->product); +#endif /* CONFIG_USB_BIN_FIXUP */ USB_STOR_PRINTF("ISO Vers %X, Response Data %X\n",usb_stor_buf[2],usb_stor_buf[3]); if(usb_test_unit_ready(pccb,ss)) { printf("Device NOT ready\n Request Sense returned %02X %02X %02X\n",pccb->sense_buf[2],pccb->sense_buf[12],pccb->sense_buf[13]); diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index f157d42fce3..89ec1bf7a9b 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -63,7 +63,7 @@ #define CFG_DEVICE_NULLDEV 1 /* enable null device */ #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */ - +#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */ #if 0 #define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */ /* switch is closed */ -- cgit v1.3.1 From 87a449c8ac396420cb24260f717ea9e6faa82047 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Tue, 22 Aug 2006 09:23:55 -0500 Subject: Support for FDT in uImage format, error when using FDT from flash Signed-off-by: Matthew McClintock --- common/cmd_bootm.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++---- include/image.h | 1 + tools/mkimage.c | 1 + 3 files changed, 67 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index f1c0eb4d183..f980659f7bd 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -528,7 +528,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, void (*kernel)(bd_t *, ulong, ulong, ulong, ulong); image_header_t *hdr = &header; #ifdef CONFIG_OF_FLAT_TREE - char *of_flat_tree; + char *of_flat_tree = NULL; #endif if ((s = getenv ("initrd_high")) != NULL) { @@ -737,14 +737,73 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, } #ifdef CONFIG_OF_FLAT_TREE - if (argc >= 3) - { + if(argc >= 3) { of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16); - printf ("Booting using flat device tree at 0x%x\n", + hdr = (image_header_t *)of_flat_tree; + + if (*(ulong *)of_flat_tree == OF_DT_HEADER) { +#ifndef CFG_NO_FLASH + if (addr2info((ulong)of_flat_tree) != NULL) { + printf ("Cannot modify flat device tree stored in flash\n" \ + "Copy to memory before using the bootm command\n"); + return; + } +#endif + } else if (ntohl(hdr->ih_magic) == IH_MAGIC) { + printf("## Flat Device Tree Image at %08lX\n", hdr); + print_image_hdr(hdr); + + if ((ntohl(hdr->ih_load) < ((unsigned long)hdr + ntohl(hdr->ih_size) + sizeof(hdr))) && + ((ntohl(hdr->ih_load) + ntohl(hdr->ih_size)) > (unsigned long)hdr)) { + printf ("ERROR: Load address overwrites Flat Device Tree uImage\n"); + return; + } + + printf(" Verifying Checksum ... "); + memmove (&header, (char *)hdr, sizeof(image_header_t)); + checksum = ntohl(header.ih_hcrc); + header.ih_hcrc = 0; + + if(checksum != crc32(0, (uchar *)&header, sizeof(image_header_t))) { + printf("ERROR: Flat Device Tree header checksum is invalid\n"); + return; + } + + checksum = ntohl(hdr->ih_dcrc); + addr = (ulong)((uchar *)(hdr) + sizeof(image_header_t)); + len = ntohl(hdr->ih_size); + + if(checksum != crc32(0, (uchar *)addr, len)) { + printf("ERROR: Flat Device Tree checksum is invalid\n"); + return; + } + printf("OK\n"); + + if (ntohl(hdr->ih_type) != IH_TYPE_FLATDT) { + printf ("ERROR: uImage not Flat Device Tree type\n"); + return; + } + if (ntohl(hdr->ih_comp) != IH_COMP_NONE) { + printf("ERROR: uImage is not uncompressed\n"); + return; + } + if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) { + printf ("ERROR: uImage data is not a flat device tree\n"); + return; + } + + memmove((void *)ntohl(hdr->ih_load), + (void *)(of_flat_tree + sizeof(image_header_t)), + ntohl(hdr->ih_size)); + of_flat_tree = (char *)ntohl(hdr->ih_load); + } else { + printf ("Did not find a flat flat device tree at address %08lX\n", of_flat_tree); + return; + } + printf (" Booting using flat device tree at 0x%x\n", of_flat_tree); } #endif - if (!data) { debug ("No initrd\n"); } @@ -1272,6 +1331,7 @@ print_type (image_header_t *hdr) case IH_TYPE_MULTI: type = "Multi-File Image"; break; case IH_TYPE_FIRMWARE: type = "Firmware"; break; case IH_TYPE_SCRIPT: type = "Script"; break; + case IH_TYPE_FLATDT: type = "Flat Device Tree"; break; default: type = "Unknown Image"; break; } diff --git a/include/image.h b/include/image.h index 139df0b2d1e..ea7e9531dc7 100644 --- a/include/image.h +++ b/include/image.h @@ -124,6 +124,7 @@ #define IH_TYPE_FIRMWARE 5 /* Firmware Image */ #define IH_TYPE_SCRIPT 6 /* Script file */ #define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ +#define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ /* * Compression Types diff --git a/tools/mkimage.c b/tools/mkimage.c index fea3e5bc6b3..d6000e04bf5 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -130,6 +130,7 @@ table_entry_t type_name[] = { { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, { IH_TYPE_SCRIPT, "script", "Script", }, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, + { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, { -1, "", "", }, }; -- cgit v1.3.1 From 2c33e8a1c535b3ae91cf0b284480600bf3f57c57 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 17:54:05 -0500 Subject: Cleanup poorly introduced whitespace. --- include/asm-ppc/mmu.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 612b5df4873..4f49789f633 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -435,8 +435,8 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_4GB 11 #if defined(CONFIG_MPC86xx) -#define LAWBAR_BASE_ADDR 0x00FFFFFF -#define LAWAR_TRGT_IF 0x01F00000 +#define LAWBAR_BASE_ADDR 0x00FFFFFF +#define LAWAR_TRGT_IF 0x01F00000 #else #define LAWBAR_BASE_ADDR 0x000FFFFF #define LAWAR_TRGT_IF 0x00F00000 @@ -448,14 +448,14 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 -#define LAWAR_TRGT_IF_HT 0x00200000 +#define LAWAR_TRGT_IF_HT 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 #define LAWAR_TRGT_IF_RIO 0x00c00000 #define LAWAR_TRGT_IF_DDR 0x00f00000 -#define LAWAR_TRGT_IF_DDR1 0x00f00000 -#define LAWAR_TRGT_IF_DDR2 0x01600000 +#define LAWAR_TRGT_IF_DDR1 0x00f00000 +#define LAWAR_TRGT_IF_DDR2 0x01600000 #define LAWAR_SIZE_BASE 0xa #define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) @@ -478,9 +478,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) #define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) #define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) -#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) -#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) -#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) -#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) +#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) +#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) +#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) +#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) #endif /* _PPC_MMU_H_ */ -- cgit v1.3.1 From ae6241685cbcf0c79a3636530d2ceab1fb291a94 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 18:07:00 -0500 Subject: Cleanup more poorly introduced whitespace. --- include/asm-ppc/processor.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 1848aaf8cdc..0060cd030b0 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -264,7 +264,7 @@ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ -#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ +#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MBAR 0x137 /* System memory base address */ @@ -445,7 +445,7 @@ #define ESR_ST 0x00800000 /* Store Operation */ #if defined(CONFIG_MPC86xx) -#define SPRN_MSSCRO 0x3f6 +#define SPRN_MSSCRO 0x3f6 #endif @@ -507,12 +507,12 @@ #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ -#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ +#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_MPC86xx) -#define MSSCR0 SPRN_MSSCRO +#define MSSCR0 SPRN_MSSCRO #endif #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define PIR SPRN_PIR @@ -548,7 +548,7 @@ #define CSRR0 SPRN_CSRR0 #define CSRR1 SPRN_CSRR1 #define IVPR SPRN_IVPR -#define USPRG0 SPRN_USPRG +#define USPRG0 SPRN_USPRG #define SPRG4R SPRN_SPRG4R #define SPRG5R SPRN_SPRG5R #define SPRG6R SPRN_SPRG6R -- cgit v1.3.1 From b93775c2036b99baa390ea425c4771895bbc63c4 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 18:26:08 -0500 Subject: Cleanup even more poorly introduced whitespace. --- include/mpc86xx.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 4edeae16477..bc8ba3f2da2 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -1,6 +1,6 @@ /* * Copyright 2006 Freescale Semiconductor. - * Jeffrey Brown (jeffrey@freescale.com) + * Jeffrey Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) */ @@ -70,10 +70,9 @@ #ifndef __ASSEMBLY__ -typedef struct -{ - unsigned long freqProcessor; - unsigned long freqSystemBus; +typedef struct { + unsigned long freqProcessor; + unsigned long freqSystemBus; } MPC86xx_SYS_INFO; #define l1icache_enable icache_enable @@ -115,5 +114,3 @@ static __inline__ unsigned long get_l2cr (void) #endif /* _ASMLANGUAGE */ #endif /* __MPC86xx_H__ */ - - -- cgit v1.3.1 From d8ea2acf5f137cae99417df4f573d036ee384668 Mon Sep 17 00:00:00 2001 From: Zhang Wei Date: Wed, 23 Aug 2006 17:54:32 +0800 Subject: Add dtb boot-up parameter to default boot commands. Signed-off-by: Zhang Wei --- include/configs/MPC8641HPCN.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 200a38f3e89..1f5e2dfd949 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -595,6 +595,8 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=400000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ + "dtbaddr=2000000\0" \ + "dtbfile=mpc8641_hpcn.dtb\0" \ "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\ "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ @@ -611,14 +613,16 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr $ramdiskaddr $dtbaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND -- cgit v1.3.1 From 4782ac80b02f0d01afd309e2200dd3c7037f2ba4 Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong Date: Wed, 23 Aug 2006 19:10:44 +0800 Subject: Add AHCI support to u-boot Add AHCI support in u-boot, enable the sata disk controllers which following the AHCI protocol. Signed-off-by:Jason Jin --- common/cmd_scsi.c | 7 +- drivers/Makefile | 2 +- drivers/ahci.c | 706 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/ahci.h | 190 +++++++++++++++ 4 files changed, 903 insertions(+), 2 deletions(-) create mode 100644 drivers/ahci.c create mode 100644 include/ahci.h (limited to 'include') diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index e8048611f93..cc08743d5dc 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -43,8 +43,13 @@ #else #define SCSI_DEV_ID CONFIG_SCSI_DEV_ID #endif +#elif defined CONFIG_SATA_ULI5288 + +#define SCSI_VEND_ID 0x10b9 +#define SCSI_DEV_ID 0x5288 + #else -#error CONFIG_SCSI_SYM53C8XX must be defined +#error no scsi device defined #endif diff --git a/drivers/Makefile b/drivers/Makefile index e6176ed86ae..98c4ef95f8f 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -44,7 +44,7 @@ OBJS = 3c589.o 5701rls.o ali512x.o \ serial.o serial_max3100.o \ serial_pl010.o serial_pl011.o serial_xuartlite.o \ sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ - status_led.o sym53c8xx.o \ + status_led.o sym53c8xx.o ahci.o \ ti_pci1410a.o tigon3.o tsec.o \ usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \ videomodes.o w83c553f.o \ diff --git a/drivers/ahci.c b/drivers/ahci.c new file mode 100644 index 00000000000..828498ddce7 --- /dev/null +++ b/drivers/ahci.c @@ -0,0 +1,706 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * Author: Jason Jin + * Zhang Wei + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference on libata and ahci drvier in kernel + * + */ +#include + +#ifdef CONFIG_SCSI_AHCI + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct ahci_probe_ent *probe_ent = NULL; +hd_driveid_t *ataid[AHCI_MAX_PORTS]; + +#define writel_with_flush(a,b) do{writel(a,b);readl(b);}while(0) + +static inline u32 ahci_port_base(u32 base, u32 port) +{ + return base + 0x100 + (port * 0x80); +} + + +static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, + unsigned int port_idx) +{ + base = ahci_port_base(base, port_idx); + + port->cmd_addr = base; + port->scr_addr = base + PORT_SCR; +} + + +#define msleep(a) udelay(a * 1000) +#define ssleep(a) msleep(a * 1000) +static int waiting_for_cmd_completed(volatile u8 *offset, int timeout_msec, u32 sign) +{ + int i; + u32 status; + for(i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) + msleep(1); + + return (i < timeout_msec)? 0 : -1; +} + + +static int ahci_host_init(struct ahci_probe_ent *probe_ent) +{ + pci_dev_t pdev = probe_ent->dev; + volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + u32 tmp, cap_save; + u16 tmp16; + int i, j; + volatile u8* port_mmio; + unsigned short vendor; + + cap_save = readl(mmio + HOST_CAP); + cap_save &= ( (1<<28) | (1<<17) ); + cap_save |= (1 << 27); + + /* global controller reset */ + tmp = readl(mmio + HOST_CTL); + if ((tmp & HOST_RESET) == 0) + writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); + + /* reset must complete within 1 second, or + * the hardware should be considered fried. + */ + ssleep(1); + + tmp = readl(mmio + HOST_CTL); + if (tmp & HOST_RESET) { + debug("controller reset failed (0x%x)\n", tmp); + return -1; + } + + writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); + writel(cap_save, mmio + HOST_CAP); + writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); + + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); + + if (vendor == PCI_VENDOR_ID_INTEL) { + u16 tmp16; + pci_read_config_word(pdev, 0x92, &tmp16); + tmp16 |= 0xf; + pci_write_config_word(pdev, 0x92, tmp16); + } + + probe_ent->cap = readl(mmio + HOST_CAP); + probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); + probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; + + debug("cap 0x%x port_map 0x%x n_ports %d\n", + probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); + + for (i = 0; i < probe_ent->n_ports; i++) { + probe_ent->port[i].port_mmio = ahci_port_base((u32)mmio, i); + port_mmio = (u8 *)probe_ent->port[i].port_mmio; + ahci_setup_port(&probe_ent->port[i], + (unsigned long) mmio, i); + + /* make sure port is not active */ + tmp = readl(port_mmio + PORT_CMD); + if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | + PORT_CMD_FIS_RX | PORT_CMD_START)) { + tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | + PORT_CMD_FIS_RX | PORT_CMD_START); + writel_with_flush(tmp, port_mmio + PORT_CMD); + + /* spec says 500 msecs for each bit, so + * this is slightly incorrect. + */ + msleep(500); + } + + writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); + + j = 0; + while (j < 100) { + msleep(10); + tmp = readl(port_mmio + PORT_SCR_STAT); + if ((tmp & 0xf) == 0x3) + break; + j++; + } + + tmp = readl(port_mmio + PORT_SCR_ERR); + debug("PORT_SCR_ERR 0x%x\n", tmp); + writel(tmp, port_mmio + PORT_SCR_ERR); + + /* ack any pending irq events for this port */ + tmp = readl(port_mmio + PORT_IRQ_STAT); + debug("PORT_IRQ_STAT 0x%x\n", tmp); + if (tmp) + writel(tmp, port_mmio + PORT_IRQ_STAT); + + writel(1 << i, mmio + HOST_IRQ_STAT); + + /* set irq mask (enables interrupts) */ + writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); + + /*register linkup ports*/ + tmp = readl(port_mmio + PORT_SCR_STAT); + debug("Port %d status: 0x%x\n",i,tmp); + if((tmp & 0xf) == 0x03) + probe_ent->link_port_map |= (0x01<< i); + } + + tmp = readl(mmio + HOST_CTL); + debug("HOST_CTL 0x%x\n", tmp); + writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); + tmp = readl(mmio + HOST_CTL); + debug("HOST_CTL 0x%x\n", tmp); + + pci_read_config_word(pdev, PCI_COMMAND, &tmp16); + tmp |= PCI_COMMAND_MASTER; + pci_write_config_word(pdev, PCI_COMMAND, tmp16); + + return 0; +} + + +static void ahci_print_info(struct ahci_probe_ent *probe_ent) +{ + pci_dev_t pdev = probe_ent->dev; + volatile u8* mmio = (volatile u8 *)probe_ent->mmio_base; + u32 vers, cap, impl, speed; + const char *speed_s; + u16 cc; + const char *scc_s; + + vers = readl(mmio + HOST_VERSION); + cap = probe_ent->cap; + impl = probe_ent->port_map; + + speed = (cap >> 20) & 0xf; + if (speed == 1) + speed_s = "1.5"; + else if (speed == 2) + speed_s = "3"; + else + speed_s = "?"; + + pci_read_config_word(pdev, 0x0a, &cc); + if (cc == 0x0101) + scc_s = "IDE"; + else if (cc == 0x0106) + scc_s = "SATA"; + else if (cc == 0x0104) + scc_s = "RAID"; + else + scc_s = "unknown"; + + printf( "AHCI %02x%02x.%02x%02x " + "%u slots %u ports %s Gbps 0x%x impl %s mode\n" + , + + (vers >> 24) & 0xff, + (vers >> 16) & 0xff, + (vers >> 8) & 0xff, + vers & 0xff, + + ((cap >> 8) & 0x1f) + 1, + (cap & 0x1f) + 1, + speed_s, + impl, + scc_s); + + printf("flags: " + "%s%s%s%s%s%s" + "%s%s%s%s%s%s%s\n" + , + + cap & (1 << 31) ? "64bit " : "", + cap & (1 << 30) ? "ncq " : "", + cap & (1 << 28) ? "ilck " : "", + cap & (1 << 27) ? "stag " : "", + cap & (1 << 26) ? "pm " : "", + cap & (1 << 25) ? "led " : "", + + cap & (1 << 24) ? "clo " : "", + cap & (1 << 19) ? "nz " : "", + cap & (1 << 18) ? "only " : "", + cap & (1 << 17) ? "pmp " : "", + cap & (1 << 15) ? "pio " : "", + cap & (1 << 14) ? "slum " : "", + cap & (1 << 13) ? "part " : "" + ); +} + + +static int ahci_init_one (pci_dev_t pdev) +{ + u32 iobase, vendor; + int rc; + + memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); + + probe_ent = malloc(sizeof(probe_ent)); + memset(probe_ent, 0, sizeof(probe_ent)); + probe_ent->dev = pdev; + + pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); + iobase &= ~0xf; + + probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY + | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA + | ATA_FLAG_NO_ATAPI; + probe_ent->pio_mask = 0x1f; + probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6*/ + + probe_ent->mmio_base = iobase; + + /* Take from kernel: + * JMicron-specific fixup: + * make sure we're in AHCI mode + */ + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); + if(vendor == 0x197b) + pci_write_config_byte(pdev, 0x41, 0xa1); + + /* initialize adapter */ + rc = ahci_host_init(probe_ent); + if (rc) + goto err_out; + + ahci_print_info(probe_ent); + + return 0; + +err_out: + return rc; +} + + +#define MAX_DATA_BYTE_COUNT (4*1024*1024) +static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; + u32 sg_count; + int i; + + sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; + if(sg_count > AHCI_MAX_SG){ + printf("Error:Too much sg!\n"); + return -1; + } + + for(i = 0;i < sg_count; i++) + { + ahci_sg->addr = cpu_to_le32((u32)buf + i * MAX_DATA_BYTE_COUNT); + ahci_sg->addr_hi = 0; + ahci_sg->flags_size = cpu_to_le32( 0x3fffff & + (buf_len < MAX_DATA_BYTE_COUNT + ? (buf_len - 1) + : (MAX_DATA_BYTE_COUNT - 1))); + ahci_sg++; + buf_len -= MAX_DATA_BYTE_COUNT; + } + + return sg_count; +} + + +static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) +{ + pp->cmd_slot->opts = cpu_to_le32(opts); + pp->cmd_slot->status = 0; + pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); + pp->cmd_slot->tbl_addr_hi = 0; +} + + +static void ahci_set_feature(u8 port) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; + u32 cmd_fis_len = 5; /* five dwords */ + u8 fis[20]; + + /*set feature*/ + memset(fis,0,20); + fis[0] = 0x27; + fis[1] = 1 << 7; + fis[2] = ATA_CMD_SETF; + fis[3] = SETFEATURES_XFER; + fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; + + memcpy((unsigned char *)pp->cmd_tbl,fis,20); + ahci_fill_cmd_slot(pp, cmd_fis_len); + writel(1, port_mmio + PORT_CMD_ISSUE); + readl(port_mmio + PORT_CMD_ISSUE); + + if(waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + printf("set feature error!\n"); + } +} + + +static int ahci_port_start(u8 port) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; + u32 port_status; + u32 mem; + + debug("Enter start port: %d\n",port); + port_status = readl(port_mmio + PORT_SCR_STAT); + debug("Port %d status: %x\n",port,port_status); + if((port_status & 0xf) != 0x03){ + printf("No Link on this port!\n"); + return -1; + } + + mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); + if (!mem) { + free(pp); + printf("No mem for table!\n"); + return -ENOMEM; + } + + mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ + + memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); + /* + * First item in chunk of DMA memory: 32-slot command table, + * 32 bytes each in size + */ + pp->cmd_slot = (struct ahci_cmd_hdr *)mem; + debug("cmd_slot = 0x%x\n",pp->cmd_slot); + + mem += (AHCI_CMD_SLOT_SZ + 224); + /* + * Second item: Received-FIS area + */ + pp->rx_fis = mem; + + mem += AHCI_RX_FIS_SZ; + /* + * Third item: data area for storing a single command + * and its scatter-gather table + */ + pp->cmd_tbl = mem; + debug("cmd_tbl_dma = 0x%x\n",pp->cmd_tbl); + + mem += AHCI_CMD_TBL_HDR; + pp->cmd_tbl_sg = (struct ahci_sg *)mem; + + writel_with_flush((u32)pp->cmd_slot, port_mmio + PORT_LST_ADDR); + + writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); + + writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | + PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | + PORT_CMD_START, port_mmio + PORT_CMD); + + debug("Exit start port %d\n",port); + + return 0; +} + + +static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, int buf_len) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; + u32 opts; + u32 port_status; + int sg_count; + + debug("Enter get_ahci_device_data: for port %d\n",port); + + if(port > probe_ent->n_ports){ + printf("Invaild port number %d\n", port); + return -1; + } + + port_status = readl(port_mmio + PORT_SCR_STAT); + if((port_status & 0xf) != 0x03){ + debug("No Link on port %d!\n",port); + return -1; + } + + memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); + + sg_count = ahci_fill_sg(port,buf,buf_len); + opts = (fis_len >> 2) | (sg_count << 16) ; + ahci_fill_cmd_slot(pp, opts); + + writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); + + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + printf("timeout exit!\n"); + return -1; + } + debug("get_ahci_device_data: %d byte transferred.\n", + pp->cmd_slot->status); + + return 0; +} + + +static char *ata_id_strcpy(u16 *target, u16 *src, int len) +{ + int i; + for(i = 0; i < len / 2; i++) + target[i] = le16_to_cpu(src[i]); + return (char *)target; +} + + +static void dump_ataid(hd_driveid_t *ataid) +{ + debug("(49)ataid->capability = 0x%x\n", ataid->capability); + debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); + debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); + debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); + debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); + debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); + debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); + debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); + debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); + debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); + debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); + debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); + debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); + debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); + debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); +} + +/* + * SCSI INQUIRY command operation. + */ +static int ata_scsiop_inquiry(ccb *pccb) +{ + u8 hdr[] = { + 0, + 0, + 0x5, /* claim SPC-3 version compatibility */ + 2, + 95 - 4, + }; + u8 fis[20]; + u8 *tmpid; + u8 port; + + /* Clean ccb data buffer */ + memset(pccb->pdata, 0, pccb->datalen); + + memcpy(pccb->pdata, hdr, sizeof(hdr)); + + if(pccb->datalen <= 35) + return 0; + + memset(fis, 0, 20); + /* Construct the FIS */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_IDENT; /* Command byte. */ + + /* Read id from sata */ + port = pccb->target; + if(!(tmpid = malloc(sizeof(hd_driveid_t)))) + return -ENOMEM; + + if(get_ahci_device_data(port, (u8 *)&fis, 20, + tmpid, sizeof(hd_driveid_t))){ + debug("scsi_ahci: SCSI inquiry command failure.\n"); + return -EIO; + } + + if(ataid[port]) + free(ataid[port]); + ataid[port] = (hd_driveid_t *)tmpid; + + memcpy(&pccb->pdata[8], "ATA ", 8); + ata_id_strcpy((u16 *)&pccb->pdata[16], (u16 *)ataid[port]->model, 16); + ata_id_strcpy((u16 *)&pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); + + dump_ataid(ataid[port]); + return 0; +} + + +/* + * SCSI READ10 command operation. + */ +static int ata_scsiop_read10(ccb *pccb) +{ + u64 lba = 0; + u32 len = 0; + u8 fis[20]; + + lba = (((u64)pccb->cmd[2]) << 24) | (((u64)pccb->cmd[3]) << 16) + | (((u64)pccb->cmd[4]) << 8) | ((u64)pccb->cmd[5]); + len = (((u32)pccb->cmd[7]) << 8) | ((u32)pccb->cmd[8]); + + /* For 10-byte and 16-byte SCSI R/W commands, transfer + * length 0 means transfer 0 block of data. + * However, for ATA R/W commands, sector count 0 means + * 256 or 65536 sectors, not 0 sectors as in SCSI. + * + * WARNING: one or two older ATA drives treat 0 as 0... + */ + if(!len) return 0; + memset(fis, 0, 20); + + /* Construct the FIS */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ + + /* LBA address, only support LBA28 in this driver*/ + fis[4] = pccb->cmd[5]; + fis[5] = pccb->cmd[4]; + fis[6] = pccb->cmd[3]; + fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0; + + /* Sector Count */ + fis[12] = pccb->cmd[8]; + fis[13] = pccb->cmd[7]; + + /* Read from ahci */ + if(get_ahci_device_data(pccb->target, (u8*)&fis, 20, + pccb->pdata, pccb->datalen)){ + debug("scsi_ahci: SCSI READ10 command failure.\n"); + return -EIO; + } + + return 0; +} + + +/* + * SCSI READ CAPACITY10 command operation. + */ +static int ata_scsiop_read_capacity10(ccb *pccb) +{ + u8 buf[8]; + + if(!ataid[pccb->target]) { + printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " + "\tNo ATA info!\n" + "\tPlease run SCSI commmand INQUIRY firstly!\n"); + return -EPERM; + } + + memset(buf, 0, 8); + + *(u32 *)buf = le32_to_cpu(ataid[pccb->target]->lba_capacity); + + buf[6] = 512 >> 8; + buf[7] = 512 & 0xff; + + memcpy(pccb->pdata, buf, 8); + + return 0; +} + + +/* + * SCSI TEST UNIT READY command operation. + */ +static int ata_scsiop_test_unit_ready(ccb *pccb) +{ + return (ataid[pccb->target]) ? 0 : -EPERM; +} + +int scsi_exec(ccb *pccb) +{ + int ret; + + switch(pccb->cmd[0]) { + case SCSI_READ10: + ret = ata_scsiop_read10(pccb); + break; + case SCSI_RD_CAPAC: + ret = ata_scsiop_read_capacity10(pccb); + break; + case SCSI_TST_U_RDY: + ret = ata_scsiop_test_unit_ready(pccb); + break; + case SCSI_INQUIRY: + ret = ata_scsiop_inquiry(pccb); + break; + default: + printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); + return FALSE; + } + + if(ret) { + debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0],ret); + return FALSE; + } + return TRUE; + +} + + +void scsi_low_level_init(int busdevfunc) +{ + int i; + u32 linkmap; + + ahci_init_one(busdevfunc); + + linkmap = probe_ent->link_port_map; + + for(i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++){ + if( ((linkmap >> i) & 0x01) ){ + if(ahci_port_start((u8)i)){ + printf("Can not start port %d\n",i); + continue; + } + ahci_set_feature((u8)i); + } + } +} + + +void scsi_bus_reset(void) +{ +/*Not implement*/ +} + + +void scsi_print_error(ccb *pccb) +{ +/*The ahci error info can be read in the ahci driver*/ +} +#endif diff --git a/include/ahci.h b/include/ahci.h new file mode 100644 index 00000000000..80701e298cf --- /dev/null +++ b/include/ahci.h @@ -0,0 +1,190 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * Author: Jason Jin + * Zhang Wei + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef _AHCI_H_ +#define _AHCI_H_ + +#define AHCI_PCI_BAR 0x24 +#define AHCI_MAX_SG 56 /* hardware max is 64K */ +#define AHCI_CMD_SLOT_SZ 32 +#define AHCI_RX_FIS_SZ 256 +#define AHCI_CMD_TBL_HDR 0x80 +#define AHCI_CMD_TBL_CDB 0x40 +#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) +#define AHCI_PORT_PRIV_DMA_SZ AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ \ + + AHCI_RX_FIS_SZ +#define AHCI_CMD_ATAPI (1 << 5) +#define AHCI_CMD_WRITE (1 << 6) +#define AHCI_CMD_PREFETCH (1 << 7) +#define AHCI_CMD_RESET (1 << 8) +#define AHCI_CMD_CLR_BUSY (1 << 10) + +#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ + +/* Global controller registers */ +#define HOST_CAP 0x00 /* host capabilities */ +#define HOST_CTL 0x04 /* global host control */ +#define HOST_IRQ_STAT 0x08 /* interrupt status */ +#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ +#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ + +/* HOST_CTL bits */ +#define HOST_RESET (1 << 0) /* reset controller; self-clear */ +#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ +#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */ + +/* Registers for each SATA port */ +#define PORT_LST_ADDR 0x00 /* command list DMA addr */ +#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */ +#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */ +#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */ +#define PORT_IRQ_STAT 0x10 /* interrupt status */ +#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */ +#define PORT_CMD 0x18 /* port command */ +#define PORT_TFDATA 0x20 /* taskfile data */ +#define PORT_SIG 0x24 /* device TF signature */ +#define PORT_CMD_ISSUE 0x38 /* command issue */ +#define PORT_SCR 0x28 /* SATA phy register block */ +#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */ +#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */ +#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ +#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */ + +/* PORT_IRQ_{STAT,MASK} bits */ +#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ +#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ +#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ +#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ +#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ +#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ +#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ +#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ + +#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ +#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ +#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ +#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ +#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ +#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ +#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ +#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ +#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ + +#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \ + | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR + +#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \ + | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \ + | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \ + | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \ + | PORT_IRQ_D2H_REG_FIS + +/* PORT_CMD bits */ +#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ +#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ +#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ +#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ +#define PORT_CMD_CLO (1 << 3) /* Command list override */ +#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ +#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ +#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ + +#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ +#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ +#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ + +#define AHCI_MAX_PORTS 32 + +/* SETFEATURES stuff */ +#define SETFEATURES_XFER 0x03 +#define XFER_UDMA_7 0x47 +#define XFER_UDMA_6 0x46 +#define XFER_UDMA_5 0x45 +#define XFER_UDMA_4 0x44 +#define XFER_UDMA_3 0x43 +#define XFER_UDMA_2 0x42 +#define XFER_UDMA_1 0x41 +#define XFER_UDMA_0 0x40 +#define XFER_MW_DMA_2 0x22 +#define XFER_MW_DMA_1 0x21 +#define XFER_MW_DMA_0 0x20 +#define XFER_SW_DMA_2 0x12 +#define XFER_SW_DMA_1 0x11 +#define XFER_SW_DMA_0 0x10 +#define XFER_PIO_4 0x0C +#define XFER_PIO_3 0x0B +#define XFER_PIO_2 0x0A +#define XFER_PIO_1 0x09 +#define XFER_PIO_0 0x08 +#define XFER_PIO_SLOW 0x00 + +#define ATA_FLAG_SATA (1 << 3) +#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */ +#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */ +#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */ +#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */ +#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */ + +struct ahci_cmd_hdr { + u32 opts; + u32 status; + u32 tbl_addr; + u32 tbl_addr_hi; + u32 reserved[4]; +}; + +struct ahci_sg { + u32 addr; + u32 addr_hi; + u32 reserved; + u32 flags_size; +}; + +struct ahci_ioports { + u32 cmd_addr; + u32 scr_addr; + u32 port_mmio; + struct ahci_cmd_hdr *cmd_slot; + struct ahci_sg *cmd_tbl_sg; + u32 cmd_tbl; + u32 rx_fis; +}; + +struct ahci_probe_ent { + pci_dev_t dev; + struct ahci_ioports port[AHCI_MAX_PORTS]; + u32 n_ports; + u32 hard_port_no; + u32 host_flags; + u32 host_set_flags; + u32 mmio_base; + u32 pio_mask; + u32 udma_mask; + u32 flags; + u32 cap; /* cache of HOST_CAP register */ + u32 port_map; /* cache of HOST_PORTS_IMPL reg */ + u32 link_port_map; /*linkup port map*/ +}; + +#endif -- cgit v1.3.1 From dabf9ef8c10b4dead5ef2106ef742b1c06b542de Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong Date: Wed, 23 Aug 2006 19:15:12 +0800 Subject: Add AHCI define and sata support for MPC8641HPCN board. Signed-off-by:Jason Jin --- include/configs/MPC8641HPCN.h | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 1f5e2dfd949..7097b3eee4e 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -340,6 +340,17 @@ #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#define CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CFG_SCSI_MAX_SCSI_ID 4 +#define CFG_SCSI_MAX_LUN 1 +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE +#endif + #endif /* CONFIG_PCI */ @@ -477,7 +488,9 @@ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | CFG_CMD_PING \ | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CFG_CMD_EXT2) \ & \ ~(CFG_CMD_ENV \ | CFG_CMD_IMLS \ @@ -486,7 +499,9 @@ #else #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | CFG_CMD_PING \ - | CFG_CMD_I2C) \ + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CGF_CMD_EXT2) \ & \ ~(CFG_CMD_ENV \ | CFG_CMD_IMLS \ @@ -498,7 +513,9 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_PCI \ | CFG_CMD_PING \ - | CFG_CMD_I2C) + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CFG_CMD_EXT2) #else #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_PING \ -- cgit v1.3.1 From ed1cf8456f2a5a4efdb4bb3d04b503d78f410e9c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 24 Aug 2006 00:26:42 +0200 Subject: Updates for MCC200 / PRS200 boards: - support for configurations with SDRAM or DDR memory, - support for highboot and lowboot - adjusting environment definitions --- CHANGELOG | 5 +++++ Makefile | 31 +++++++++++++++++++++----- board/mcc200/config.mk | 2 +- board/mcc200/mcc200.c | 4 ++++ include/configs/mcc200.h | 57 +++++++++++++++++++++++++++++++++--------------- 5 files changed, 75 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 82be4e3d779..7975cf38a0d 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,11 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Updates for MCC200 / PRS200 boards: + - support for configurations with SDRAM or DDR memory, + - support for highboot and lowboot + - adjusting environment definitions + * Add support for WTK FO300 board (TQM5200 based). * Fix TQM834x hang. diff --git a/Makefile b/Makefile index a78f35b6219..7542ab4dcc9 100644 --- a/Makefile +++ b/Makefile @@ -323,10 +323,15 @@ lite5200b_LOWBOOT_config: unconfig @./mkconfig -a IceCube ppc mpc5xxx icecube mcc200_config \ -mcc200_SDRAM \ -mcc200_highboot \ -mcc200_COM12 \ -mcc200_highboot_SDRAM: unconfig +mcc200_SDRAM_config \ +mcc200_highboot_config \ +mcc200_COM12_config \ +mcc200_COM12_SDRAM_config \ +mcc200_highboot_SDRAM_config \ +prs200_config \ +prs200_DDR_config \ +prs200_highboot_config \ +prs200_highboot_DDR_config: unconfig @ >include/config.h @[ -n "$(findstring highboot,$@)" ] || \ { echo "... with lowboot configuration" ; \ @@ -336,7 +341,18 @@ mcc200_highboot_SDRAM: unconfig echo "... with highboot configuration" ; \ } @[ -n "$(findstring _SDRAM,$@)" ] || \ - { echo "... with DDR" ; \ + { if [ -n "$(findstring mcc200,$@)" ]; \ + then \ + echo "... with DDR" ; \ + else \ + if [ -n "$(findstring _DDR,$@)" ];\ + then \ + echo "... with DDR" ; \ + else \ + echo "#define CONFIG_MCC200_SDRAM" >>include/config.h ;\ + echo "... with SDRAM" ; \ + fi; \ + fi; \ } @[ -z "$(findstring _SDRAM,$@)" ] || \ { echo "#define CONFIG_MCC200_SDRAM" >>include/config.h ; \ @@ -346,7 +362,10 @@ mcc200_highboot_SDRAM: unconfig { echo "#define CONFIG_CONSOLE_COM12" >>include/config.h ; \ echo "... with console on COM12" ; \ } - @./mkconfig -a mcc200 ppc mpc5xxx mcc200 + @[ -z "$(findstring prs200,$@)" ] || \ + { echo "#define CONFIG_PRS200" >>include/config.h ;\ + } + @./mkconfig -n $@ -a mcc200 ppc mpc5xxx mcc200 o2dnt_config: @./mkconfig o2dnt ppc mpc5xxx o2dnt diff --git a/board/mcc200/config.mk b/board/mcc200/config.mk index a8225598cc1..192272334a9 100644 --- a/board/mcc200/config.mk +++ b/board/mcc200/config.mk @@ -22,7 +22,7 @@ # # -# MCC200 board: +# MCC200, PRS200 boards: # # Valid values for TEXT_BASE are: # diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index 775030c17cb..9c5780998ea 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -197,7 +197,11 @@ long int initdram (int board_type) int checkboard (void) { +#if defined(CONFIG_PRS200) + puts ("Board: PRS200\n"); +#else puts ("Board: MCC200\n"); +#endif return 0; } diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index 563f7978d5f..aead49a926b 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -55,16 +55,28 @@ * * CONFIG_PSC_CONSOLE must be undefined in this case. */ +#if !defined(CONFIG_PRS200) +/* MCC200 configuration: */ #ifdef CONFIG_CONSOLE_COM12 #define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */ #else #define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */ #endif +#else +/* PRS200 configuration: */ +#undef CONFIG_QUART_CONSOLE +#endif /* CONFIG_PRS200 */ /* * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1 * and undefine CONFIG_QUART_CONSOLE. */ -/*#define CONFIG_PSC_CONSOLE 1 */ /* console is on PSC1 */ +#if !defined(CONFIG_PRS200) +/* MCC200 configuration: */ +#undef CONFIG_PSC_CONSOLE +#else +/* PRS200 configuration: */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#endif #if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) #error "Select only one console device!" #endif @@ -103,33 +115,44 @@ #undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#ifdef CONFIG_PRS200 +# define CFG__BOARDNAME "prs200" +#else +# define CFG__BOARDNAME "mcc200" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ - "hostname=mcc200\0" \ + "hostname=" CFG__BOARDNAME "\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ + "addcons=etenv bootargs ${bootargs} " \ + "console=${console},${baudrate}\0" \ + "flash_nfs=run nfsargs addip addcons;" \ "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ + "flash_self=run ramargs addip addcons;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addcons;bootm\0" \ + "console=ttyS0\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/mcc200/uImage\0" \ - "baudrate=115200\0" \ - "load=tftp 200000 /tftpboot/mcc200/u-boot.bin\0" \ - "update=protect off FFF00000 +${filesize};" \ - "era FFF00000 +${filesize};" \ - "cp.b 200000 FFF00000 ${filesize}\0" \ - "serverip=192.168.1.1\0" \ - "ipaddr=192.168.133.144\0" \ - "netmask=255.255.0.0\0" \ + "bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \ + "load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \ + "text_base=" MK_STR(TEXT_BASE) "\0" \ + "update=protect off ${text_base} +${filesize};" \ + "era ${text_base} +${filesize};" \ + "cp.b 200000 ${text_base} ${filesize}\0" \ "unlock=yes\0" \ - "ethaddr=00:02:44:7D:73:3B\0" \ "" +#undef MK_STR +#undef XMK_STR #define CONFIG_BOOTCOMMAND "run flash_self" @@ -314,7 +337,7 @@ * One of four SC16C554 UARTs is selected with * A3-A4 (DA5-DA6) lines. */ -#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) +#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200) #define CFG_NS16550_COM1 (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) #define CFG_NS16550_COM1 (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) -- cgit v1.3.1 From 113f64e09ac4905ddc330181c8761a4b29e82394 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 25 Aug 2006 01:38:04 +0200 Subject: Update for MCC200 / PRS200 boards: - auto-adjust console device for Linux. - fix typos. --- CHANGELOG | 4 ++++ Makefile | 2 ++ include/configs/mcc200.h | 6 ++++-- 3 files changed, 10 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index b6dc06784c7..af180eed169 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,10 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Update for MCC200 / PRS200 boards: + - auto-adjust console device for Linux. + - fix typos. + * Add a fix for a buggy USB device on the FO300 board. * Updates for MCC200 / PRS200 boards: diff --git a/Makefile b/Makefile index 7542ab4dcc9..9bf7c49fb9c 100644 --- a/Makefile +++ b/Makefile @@ -327,6 +327,8 @@ mcc200_SDRAM_config \ mcc200_highboot_config \ mcc200_COM12_config \ mcc200_COM12_SDRAM_config \ +mcc200_COM12_highboot_config \ +mcc200_COM12_highboot_SDRAM_config \ mcc200_highboot_SDRAM_config \ prs200_config \ prs200_DDR_config \ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index aead49a926b..df3d68e9f77 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -120,8 +120,10 @@ #ifdef CONFIG_PRS200 # define CFG__BOARDNAME "prs200" +# define LINUX_CONSOLE "ttyS0" #else # define CFG__BOARDNAME "mcc200" +# define LINUX_CONSOLE "ttyEU7" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -133,7 +135,7 @@ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=etenv bootargs ${bootargs} " \ + "addcons=setenv bootargs ${bootargs} " \ "console=${console},${baudrate}\0" \ "flash_nfs=run nfsargs addip addcons;" \ "bootm ${kernel_addr}\0" \ @@ -141,7 +143,7 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};" \ "run nfsargs addip addcons;bootm\0" \ - "console=ttyS0\0" \ + "console=" MK_STR(LINUX_CONSOLE) "\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ "bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \ "load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \ -- cgit v1.3.1 From 3b0ff842bf70baf1f370c8e76e8f33a0f9904c1b Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 25 Aug 2006 11:47:06 +0200 Subject: Fix typo in MCC200/PRS200 configuration --- include/configs/mcc200.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index df3d68e9f77..14a5bae36c7 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -115,15 +115,15 @@ #undef CONFIG_BOOTARGS -#define XMK_STR(x) #x -#define MK_STR(x) XMK_STR(x) +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) #ifdef CONFIG_PRS200 -# define CFG__BOARDNAME "prs200" -# define LINUX_CONSOLE "ttyS0" +# define CFG__BOARDNAME "prs200" +# define CFG__LINUX_CONSOLE "ttyS0" #else -# define CFG__BOARDNAME "mcc200" -# define LINUX_CONSOLE "ttyEU7" +# define CFG__BOARDNAME "mcc200" +# define CFG__LINUX_CONSOLE "ttyEU7" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -143,7 +143,7 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};" \ "run nfsargs addip addcons;bootm\0" \ - "console=" MK_STR(LINUX_CONSOLE) "\0" \ + "console=" LINUX_CONSOLE "\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ "bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \ "load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \ -- cgit v1.3.1 From 5567806b67d0ae83493aa8823ad3b6c914f581d7 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 25 Aug 2006 14:38:34 -0400 Subject: Change ramdiskaddr and dtbaddr Remove PEX fluff commands. Signed-off-by: Haiying Wang Signed-off-by: Jon Loeliger --- include/configs/MPC8641HPCN.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 7097b3eee4e..c704d4659ab 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -610,15 +610,10 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ + "ramdiskaddr=2000000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ - "dtbaddr=2000000\0" \ + "dtbaddr=400000\0" \ "dtbfile=mpc8641_hpcn.dtb\0" \ - "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\ - "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ - "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ - "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ - "pex=run pexstat; run pex1; run pexd\0" \ "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ "maxcpus=2" -- cgit v1.3.1 From 16850919ff8666f20d047cb83b4ee77581336515 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 27 Aug 2006 18:10:01 +0200 Subject: Code cleanup --- CHANGELOG | 2 ++ board/amcc/common/flash.c | 60 +++++++++++++++++++++++------------------------ board/cpu87/cpu87.c | 8 +++---- board/mcc200/mcc200.c | 4 ++-- board/tqm5200/tqm5200.c | 6 ++--- cpu/i386/sc520.c | 2 +- cpu/i386/sc520_asm.S | 12 +++++----- cpu/ppc4xx/440spe_pcie.c | 2 +- include/configs/CPU87.h | 2 +- 9 files changed, 50 insertions(+), 48 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index af180eed169..e326782373e 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Code cleanup + * Update for MCC200 / PRS200 boards: - auto-adjust console device for Linux. - fix typos. diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c index a0acbba70c3..e6429ecd136 100644 --- a/board/amcc/common/flash.c +++ b/board/amcc/common/flash.c @@ -35,7 +35,7 @@ #include #include -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -76,7 +76,7 @@ void flash_print_info(flash_info_t * info) case FLASH_MAN_SST: printf("SST "); break; - case FLASH_MAN_MX: + case FLASH_MAN_MX: printf ("MACRONIX "); break; default: @@ -223,75 +223,75 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) return (0); /* no or unknown flash */ } - value = addr2[1]; /* device ID */ + value = addr2[1]; /* device ID */ DEBUGF("\nFLASH DEVICEID: %x\n", value); switch (value) { case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B: info->flash_id += FLASH_AM040; info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ + info->size = 0x0080000; /* => 512 KiB */ break; case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B: info->flash_id += FLASH_AM040; info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ + info->size = 0x0080000; /* => 512 KiB */ break; case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B: info->flash_id += FLASH_AM040; info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ + info->size = 0x0080000; /* => 512 KiB */ break; case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D: info->flash_id += FLASH_AMD016; info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ + info->size = 0x00200000; /* => 2 MiB */ + break; case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C: info->flash_id += FLASH_AMDLV033C; info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ + info->size = 0x00400000; /* => 4 MiB */ + break; case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T: info->flash_id += FLASH_AM400T; info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ + info->size = 0x00080000; /* => 512 KiB */ + break; case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B: info->flash_id += FLASH_AM400B; info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ + info->size = 0x00080000; /* => 512 KiB */ + break; case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T: info->flash_id += FLASH_AM800T; info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ + info->size = 0x00100000; /* => 1 MiB */ + break; case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B: info->flash_id += FLASH_AM800B; info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ + info->size = 0x00100000; /* => 1 MiB */ + break; case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T: info->flash_id += FLASH_AM160T; info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ + info->size = 0x00200000; /* => 2 MiB */ + break; case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B: info->flash_id += FLASH_AM160B; info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ + info->size = 0x00200000; /* => 2 MiB */ + break; default: info->flash_id = FLASH_UNKNOWN; @@ -306,7 +306,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) info->start[i] = base + (i * 0x00010000); } else { if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ + /* set sector offsets for bottom boot block type */ info->start[0] = base + 0x00000000; info->start[1] = base + 0x00004000; info->start[2] = base + 0x00006000; @@ -316,7 +316,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) base + (i * 0x00010000) - 0x00030000; } } else { - /* set sector offsets for top boot block type */ + /* set sector offsets for top boot block type */ i = info->sector_count - 1; info->start[i--] = base + info->size - 0x00004000; info->start[i--] = base + info->size - 0x00006000; @@ -666,7 +666,7 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) return (0); /* no or unknown flash */ } - value = addr2[1]; /* device ID */ + value = addr2[1]; /* device ID */ DEBUGF("\nFLASH DEVICEID: %x\n", value); @@ -675,17 +675,17 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: info->flash_id += FLASH_AM320T; info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ + info->size = 0x00400000; break; /* => 4 MiB */ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: info->flash_id += FLASH_AM320B; info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ + info->size = 0x00400000; break; /* => 4 MiB */ case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: info->flash_id += FLASH_STMW320DT; info->sector_count = 67; - info->size = 0x00400000; break; /* => 4 MB */ + info->size = 0x00400000; break; /* => 4 MiB */ case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T: info->flash_id += FLASH_MXLV320T; @@ -743,7 +743,7 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) info->start[i] = base + i * 0x00010000; } else { if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ + /* set sector offsets for bottom boot block type */ info->start[0] = base + 0x00000000; info->start[1] = base + 0x00004000; info->start[2] = base + 0x00006000; @@ -753,7 +753,7 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) base + (i * 0x00010000) - 0x00030000; } } else { - /* set sector offsets for top boot block type */ + /* set sector offsets for top boot block type */ i = info->sector_count - 1; info->start[i--] = base + info->size - 0x00004000; info->start[i--] = base + info->size - 0x00006000; diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c index e8c2614eb47..9fecdd0dfef 100644 --- a/board/cpu87/cpu87.c +++ b/board/cpu87/cpu87.c @@ -294,15 +294,15 @@ long int initdram (int board_type) */ size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, (uchar *) CFG_SDRAM_BASE); - + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, (uchar *) CFG_SDRAM_BASE); - + size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL, (uchar *) CFG_SDRAM_BASE); - + psize = max(size8,max(size9,size10)); - + if (psize == size8) { psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, (uchar *) CFG_SDRAM_BASE); diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index 9c5780998ea..71a691b5dbf 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -265,8 +265,8 @@ int misc_init_r (void) *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6); printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n"); flash_info[0].size = 32 << 20; - for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20); - flash_info[0].start[snum] < flash_sup_end; + for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20); + flash_info[0].start[snum] < flash_sup_end; snum++); flash_info[0].sector_count = snum; } diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index c8350ab3b5d..2a0d542ef8b 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -743,7 +743,7 @@ int board_early_init_f (void) /* Read in TIMER_3 pin status */ timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS; - + #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* Force silent console mode if S1 switch * is in closed position (TIMER_3 pin status is LOW). */ @@ -757,5 +757,5 @@ int board_early_init_f (void) return 0; } -#endif -#endif +#endif /* CONFIG_FO300 */ +#endif /* CONFIG_BOARD_EARLY_INIT_F */ diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c index 1c4370b0819..d0a73418827 100644 --- a/cpu/i386/sc520.c +++ b/cpu/i386/sc520.c @@ -149,7 +149,7 @@ unsigned long init_sc520_dram(void) /* these memory control registers are set up in the assember part, * in sc520_asm.S, during 'mem_init'. If we muck with them here, * after we are running a stack in RAM, we have troubles. Besides, - * these refresh and delay values are better ? simply specified + * these refresh and delay values are better ? simply specified * outright in the include/configs/{cfg} file since the HW designer * simply dictates it. */ diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S index e1fa37a4a61..8fc713d93bb 100644 --- a/cpu/i386/sc520_asm.S +++ b/cpu/i386/sc520_asm.S @@ -462,7 +462,7 @@ emptybank: #if defined CFG_SDRAM_DRCTMCTL /* just have your hardware desinger _GIVE_ you what you need here! */ - movl $DRCTMCTL, %edi + movl $DRCTMCTL, %edi movb $CFG_SDRAM_DRCTMCTL,%al movb (%edi), %al #else @@ -477,7 +477,7 @@ emptybank: #ifdef CFG_SDRAM_CAS_LATENCY_3T orb $0x10, %al #endif - movb %al, (%edi) + movb %al, (%edi) #endif #endif movl $DRCCTL, %edi /* DRAM Control register */ @@ -537,7 +537,7 @@ bank0: movl (%edi), %eax movl %eax, %ebx -done: +done: movl %ebx, %eax #if CFG_SDRAM_ECC_ENABLE @@ -547,7 +547,7 @@ done: movl $0x1, %edi memtest0: movb $0xa5, (%edi) - cmpb $0xa5, (%edi) + cmpb $0xa5, (%edi) jne out shrl $1, %ecx andl %ecx,%ecx @@ -571,11 +571,11 @@ set_ecc: /* enable NMI mapping for ECC */ movl $ECCINT, %edi mov $0x10, %al - movb %al, (%edi) + movb %al, (%edi) /* Turn on ECC */ movl $ECCCTL, %edi mov $0x05, %al - movb %al, (%edi) + movb %al, (%edi) #endif out: movl %ebx, %eax diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c index 2e920aadf01..b2621c2ec5b 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/440spe_pcie.c @@ -169,7 +169,7 @@ static void ppc440spe_setup_utl(u32 port) { break; } utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port); - + /* * Set buffer allocations and then assert VRB and TXE. */ diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h index 7a1dada2db5..ce969ecdd18 100644 --- a/include/configs/CPU87.h +++ b/include/configs/CPU87.h @@ -527,7 +527,7 @@ PSDMR_LDOTOPRE_1C |\ PSDMR_WRC_1C |\ PSDMR_CL_2) - + /* * Init Memory Controller: * -- cgit v1.3.1 From 21a9cc028d00c50f542e25d58201e3debecd5166 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Aug 2006 10:49:11 +0200 Subject: Fix typo. --- CHANGELOG | 2 ++ include/configs/mcc200.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index e326782373e..46e77e7c462 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix typo. + * Code cleanup * Update for MCC200 / PRS200 boards: diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index 14a5bae36c7..fc5781e438f 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -143,7 +143,7 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};" \ "run nfsargs addip addcons;bootm\0" \ - "console=" LINUX_CONSOLE "\0" \ + "console=" CFG__LINUX_CONSOLE "\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ "bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \ "load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \ -- cgit v1.3.1 From 0fd30252c840ee54d2a80475d6504766d43b8add Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 30 Aug 2006 23:02:10 +0200 Subject: Make the serial driver framework work with CONFIG_SERIAL_MULTI enabled --- CHANGELOG | 3 ++ common/serial.c | 28 +++++++++++- drivers/ns9750_serial.c | 4 ++ drivers/serial.c | 111 +++++++++++++++++++++++++++++++++++++++++++++++ include/configs/mcc200.h | 7 ++- include/serial.h | 7 +++ 6 files changed, 157 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 02ccd30a3e7..87341755e27 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Make the serial driver framework work with CONFIG_SERIAL_MULTI + enabled + * PCIe endpoint support for AMCC Yucca 440SPe board Patch by Tirumala R Marri, 26 Aug 2006 diff --git a/common/serial.c b/common/serial.c index 38057d21f6c..605d4e34be0 100644 --- a/common/serial.c +++ b/common/serial.c @@ -42,7 +42,19 @@ struct serial_device *default_serial_console (void) return &serial_scc_device; #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx) -#if defined(CONFIG_UART1_CONSOLE) +#if defined(CONFIG_CONS_INDEX) && defined(CFG_NS16550_SERIAL) +#if (CONFIG_CONS_INDEX==1) + return &eserial1_device; +#elif (CONFIG_CONS_INDEX==2) + return &eserial2_device; +#elif (CONFIG_CONS_INDEX==3) + return &eserial3_device; +#elif (CONFIG_CONS_INDEX==4) + return &eserial4_device; +#else +#error "Bad CONFIG_CONS_INDEX." +#endif +#elif defined(CONFIG_UART1_CONSOLE) return &serial1_device; #else return &serial0_device; @@ -84,6 +96,20 @@ void serial_initialize (void) serial_register(&serial1_device); #endif +#if defined(CFG_NS16550_SERIAL) +#if defined(CFG_NS16550_COM1) + serial_register(&eserial1_device); +#endif +#if defined(CFG_NS16550_COM2) + serial_register(&eserial2_device); +#endif +#if defined(CFG_NS16550_COM3) + serial_register(&eserial3_device); +#endif +#if defined(CFG_NS16550_COM4) + serial_register(&eserial4_device); +#endif +#endif /* CFG_NS16550_SERIAL */ serial_assign (default_serial_console ()->name); } diff --git a/drivers/ns9750_serial.c b/drivers/ns9750_serial.c index 8dff3677450..02c0d395209 100644 --- a/drivers/ns9750_serial.c +++ b/drivers/ns9750_serial.c @@ -35,6 +35,10 @@ DECLARE_GLOBAL_DATA_PTR; +#if !defined(CONFIG_CONS_INDEX) +#error "No console index specified." +#endif + #define CONSOLE CONFIG_CONS_INDEX static unsigned int calcBitrateRegister( void ); diff --git a/drivers/serial.c b/drivers/serial.c index 228781b46a6..8d1ae96bf85 100644 --- a/drivers/serial.c +++ b/drivers/serial.c @@ -30,10 +30,20 @@ #include #endif +#if defined (CONFIG_SERIAL_MULTI) +#include +#endif + DECLARE_GLOBAL_DATA_PTR; #if !defined(CONFIG_CONS_INDEX) +#if defined (CONFIG_SERIAL_MULTI) +/* with CONFIG_SERIAL_MULTI we might have no console + * on these devices + */ +#else #error "No console index specified." +#endif /* CONFIG_SERIAL_MULTI */ #elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4) #error "Invalid console index value." #endif @@ -75,7 +85,42 @@ static NS16550_t serial_ports[4] = { }; #define PORT serial_ports[port-1] +#if defined(CONFIG_CONS_INDEX) #define CONSOLE (serial_ports[CONFIG_CONS_INDEX-1]) +#endif + +#if defined(CONFIG_SERIAL_MULTI) + +/* Multi serial device functions */ +#define DECLARE_ESERIAL_FUNCTIONS(port) \ + int eserial##port##_init (void) {\ + int clock_divisor; \ + clock_divisor = calc_divisor(serial_ports[port-1]); \ + NS16550_init(serial_ports[port-1], clock_divisor); \ + return(0);}\ + void eserial##port##_setbrg (void) {\ + serial_setbrg_dev(port);}\ + int eserial##port##_getc (void) {\ + return serial_getc_dev(port);}\ + int eserial##port##_tstc (void) {\ + return serial_tstc_dev(port);}\ + void eserial##port##_putc (const char c) {\ + serial_putc_dev(port, c);}\ + void eserial##port##_puts (const char *s) {\ + serial_puts_dev(port, s);} + +/* Serial device descriptor */ +#define INIT_ESERIAL_STRUCTURE(port,name,bus) {\ + name,\ + bus,\ + eserial##port##_init,\ + eserial##port##_setbrg,\ + eserial##port##_getc,\ + eserial##port##_tstc,\ + eserial##port##_putc,\ + eserial##port##_puts, } + +#endif /* CONFIG_SERIAL_MULTI */ static int calc_divisor (NS16550_t port) { @@ -103,6 +148,7 @@ static int calc_divisor (NS16550_t port) } +#if !defined(CONFIG_SERIAL_MULTI) int serial_init (void) { int clock_divisor; @@ -130,6 +176,7 @@ int serial_init (void) return (0); } +#endif void _serial_putc(const char c,const int port) @@ -176,40 +223,104 @@ _serial_setbrg (const int port) NS16550_reinit(PORT, clock_divisor); } +#if defined(CONFIG_SERIAL_MULTI) +static inline void +serial_putc_dev(unsigned int dev_index,const char c) +{ + _serial_putc(c,dev_index); +} +#else void serial_putc(const char c) { _serial_putc(c,CONFIG_CONS_INDEX); } +#endif +#if defined(CONFIG_SERIAL_MULTI) +static inline void +serial_putc_raw_dev(unsigned int dev_index,const char c) +{ + _serial_putc_raw(c,dev_index); +} +#else void serial_putc_raw(const char c) { _serial_putc_raw(c,CONFIG_CONS_INDEX); } +#endif +#if defined(CONFIG_SERIAL_MULTI) +static inline void +serial_puts_dev(unsigned int dev_index,const char *s) +{ + _serial_puts(s,dev_index); +} +#else void serial_puts(const char *s) { _serial_puts(s,CONFIG_CONS_INDEX); } +#endif +#if defined(CONFIG_SERIAL_MULTI) +static inline int +serial_getc_dev(unsigned int dev_index) +{ + return _serial_getc(dev_index); +} +#else int serial_getc(void) { return _serial_getc(CONFIG_CONS_INDEX); } +#endif +#if defined(CONFIG_SERIAL_MULTI) +static inline int +serial_tstc_dev(unsigned int dev_index) +{ + return _serial_tstc(dev_index); +} +#else int serial_tstc(void) { return _serial_tstc(CONFIG_CONS_INDEX); } +#endif +#if defined(CONFIG_SERIAL_MULTI) +static inline void +serial_setbrg_dev(unsigned int dev_index) +{ + _serial_setbrg(dev_index); +} +#else void serial_setbrg(void) { _serial_setbrg(CONFIG_CONS_INDEX); } +#endif + +#if defined(CONFIG_SERIAL_MULTI) + +DECLARE_ESERIAL_FUNCTIONS(1); +struct serial_device eserial1_device = + INIT_ESERIAL_STRUCTURE(1,"eserial0","EUART1"); +DECLARE_ESERIAL_FUNCTIONS(2); +struct serial_device eserial2_device = + INIT_ESERIAL_STRUCTURE(2,"eserial1","EUART2"); +DECLARE_ESERIAL_FUNCTIONS(3); +struct serial_device eserial3_device = + INIT_ESERIAL_STRUCTURE(3,"eserial2","EUART3"); +DECLARE_ESERIAL_FUNCTIONS(4); +struct serial_device eserial4_device = + INIT_ESERIAL_STRUCTURE(4,"eserial3","EUART4"); +#endif /* CONFIG_SERIAL_MULTI */ #endif diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index fc5781e438f..61014ecd1f2 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -72,12 +72,15 @@ */ #if !defined(CONFIG_PRS200) /* MCC200 configuration: */ -#undef CONFIG_PSC_CONSOLE +#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */ +#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */ #else /* PRS200 configuration: */ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ #endif -#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) +#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \ + !defined(CONFIG_SERIAL_MULTI) #error "Select only one console device!" #endif #define CONFIG_BAUDRATE 115200 diff --git a/include/serial.h b/include/serial.h index 8c7b1c26c13..48800595d78 100644 --- a/include/serial.h +++ b/include/serial.h @@ -26,6 +26,13 @@ extern struct serial_device * default_serial_console (void); || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx) extern struct serial_device serial0_device; extern struct serial_device serial1_device; +#if defined(CFG_NS16550_SERIAL) +extern struct serial_device eserial1_device; +extern struct serial_device eserial2_device; +extern struct serial_device eserial3_device; +extern struct serial_device eserial4_device; +#endif /* CFG_NS16550_SERIAL */ + #endif -- cgit v1.3.1 From e8143e72e1cbe2f771258533e26ee2105a8768a7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 30 Aug 2006 23:09:00 +0200 Subject: Add splashscreen support for MCC200 board. --- CHANGELOG | 2 + board/mcc200/Makefile | 2 +- board/mcc200/lcd.c | 190 +++++++++++++++++++++++++++++++++++++++++++++++ common/lcd.c | 28 ++++++- cpu/mpc5xxx/serial.c | 56 ++++++++++++++ include/configs/mcc200.h | 15 ++++ include/lcd.h | 9 ++- 7 files changed, 297 insertions(+), 5 deletions(-) create mode 100644 board/mcc200/lcd.c (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 87341755e27..7df923c047d 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add splashscreen support for MCC200 board. + * Make the serial driver framework work with CONFIG_SERIAL_MULTI enabled diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile index 7fdc088e9c1..bd75859f615 100644 --- a/board/mcc200/Makefile +++ b/board/mcc200/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := $(BOARD).o +OBJS := $(BOARD).o lcd.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c new file mode 100644 index 00000000000..b2625160a5e --- /dev/null +++ b/board/mcc200/lcd.c @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_LCD + +#define SWAPPED_LCD +/* + * The name of the device used for communication + * with the PSoC. + */ +#define PSOC_PSC MPC5XXX_PSC2 +#define PSOC_BAUD 500000UL + +#define RTS_ASSERT 1 +#define RTS_NEGATE 0 +#define CTS_ASSERT 1 +#define CTS_NEGATE 0 + +/* + * Dimensions in pixels + */ +#define LCD_WIDTH 160 +#define LCD_HEIGHT 100 + +/* + * Dimensions in bytes + */ +#define LCD_BUF_SIZE ((LCD_WIDTH*LCD_HEIGHT)>>3) + +#if LCD_BPP != LCD_MONOCHROME +#error "MCC200 support only monochrome displays (1 bpp)!" +#endif + +#define PSOC_RETRIES 10 /* each of PSOC_WAIT_TIME */ +#define PSOC_WAIT_TIME 10 /* usec */ + +DECLARE_GLOBAL_DATA_PTR; + +/* + * LCD information + */ +vidinfo_t panel_info = { + LCD_WIDTH, LCD_HEIGHT, LCD_BPP +}; + +int lcd_line_length; + +int lcd_color_fg; +int lcd_color_bg; + +/* + * Frame buffer memory information + */ +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +short console_col = 0; +short console_row = 0; + +/* + * The device we use to communicate with PSoC + */ +int serial_inited = 0; + +/* + * Exported functions + */ +void lcd_initcolregs (void); +void lcd_ctrl_init (void *lcdbase); +void lcd_enable (void); + +/* + * Imported functions to support the PSoC protocol + */ +extern int serial_init_dev (unsigned long dev_base); +extern void serial_setrts_dev (unsigned long dev_base, int s); +extern int serial_getcts_dev (unsigned long dev_base); +extern void serial_putc_raw_dev(unsigned long dev_base, const char c); + +/* + * Just stubs for our driver, needed for compiling compabilty with + * the common LCD driver code. + */ +void lcd_initcolregs (void) +{ +} + +void lcd_ctrl_init (void *lcdbase) +{ +} + +/* + * Function sends the contents of the frame-buffer to the LCD + */ +void lcd_enable (void) +{ + int i, retries, fb_size; + + if (!serial_inited) { + unsigned long baud; + + baud = gd->baudrate; + gd->baudrate = PSOC_BAUD; + serial_init_dev(PSOC_PSC); + gd->baudrate = baud; + serial_setrts_dev (PSOC_PSC, RTS_ASSERT); + serial_inited = 1; + } + + /* + * Implement PSoC communication protocol: + * 1. Assert RTS, wait CTS assertion + * 2. Transmit data + * 3. Negate RTS, wait CTS negation + */ + + /* 1 */ + serial_setrts_dev (PSOC_PSC, RTS_ASSERT); + for (retries = PSOC_RETRIES; retries; retries--) { + if (serial_getcts_dev(PSOC_PSC) == CTS_ASSERT) + break; + udelay (PSOC_WAIT_TIME); + } + if (!retries) { + printf ("%s Error: PSoC doesn't respond on " + "RTS ASSERT\n", __FUNCTION__); + } + + /* 2 */ + fb_size = panel_info.vl_row * (panel_info.vl_col >> 3); + +#if !defined(SWAPPED_LCD) + for (i=0; i> 3); + for (y=0; y>4 & 0x0F)); + serial_putc_raw_dev (PSOC_PSC, (p[i+x+3]<<4 & 0xF0) | (p[i+x+4]>>4 & 0x0F)); + serial_putc_raw_dev (PSOC_PSC, (p[i+x+4]<<4 & 0xF0) | (p[i+x]>>4 & 0x0F)); + serial_putc_raw_dev (PSOC_PSC, (p[i+x]<<4 & 0xF0) | (p[i+x+1]>>4 & 0x0F)); + serial_putc_raw_dev (PSOC_PSC, (p[i+x+1]<<4 & 0xF0) | (p[i+x+2]>>4 & 0x0F)); + } + } + } +#endif + + /* 3 */ + serial_setrts_dev (PSOC_PSC, RTS_NEGATE); + for (retries = PSOC_RETRIES; retries; retries--) { + if (serial_getcts_dev(PSOC_PSC) == CTS_NEGATE) + break; + udelay (PSOC_WAIT_TIME); + } + if (!retries) { + printf ("%s Error: PSoC doesn't respond on " + "RTS NEGATE\n", __FUNCTION__); + } + + return; +} +#endif /* CONFIG_LCD */ diff --git a/common/lcd.c b/common/lcd.c index 0be1912a359..d79350f2347 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -585,6 +585,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) uchar *bmap; ushort padded_line; unsigned long width, height; + unsigned long pwidth = panel_info.vl_col; unsigned colors,bpix; unsigned long compression; #if defined(CONFIG_PXA250) @@ -628,6 +629,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) cmap = (ushort *)fbi->palette; #elif defined(CONFIG_MPC823) cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]); +#elif defined(CONFIG_MCC200) + /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */ #else # error "Don't know location of color map" #endif @@ -652,9 +655,28 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) } } + /* + * BMP format for Monochrome assumes that the state of a + * pixel is described on a per Bit basis, not per Byte. + * So, in case of Monochrome BMP we should align widths + * on a byte boundary and convert them from Bit to Byte + * units. + * Probably, PXA250 and MPC823 process 1bpp BMP images in + * their own ways, so make the converting to be MCC200 + * specific. + */ +#if defined(CONFIG_MCC200) + if (bpix==1) + { + width = ((width + 7) & ~7) >> 3; + x = ((x + 7) & ~7) >> 3; + pwidth= ((pwidth + 7) & ~7) >> 3; + } +#endif + padded_line = (width&0x3) ? ((width&~0x3)+4) : (width); - if ((x + width)>panel_info.vl_col) - width = panel_info.vl_col - x; + if ((x + width)>pwidth) + width = pwidth - x; if ((y + height)>panel_info.vl_row) height = panel_info.vl_row - y; @@ -666,7 +688,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) for (j = 0; j < width ; j++) #if defined(CONFIG_PXA250) *(fb++)=*(bmap++); -#elif defined(CONFIG_MPC823) +#elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200) *(fb++)=255-*(bmap++); #endif bmap += (width - padded_line); diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c index 6cb523d3c7b..430d63f7464 100644 --- a/cpu/mpc5xxx/serial.c +++ b/cpu/mpc5xxx/serial.c @@ -165,6 +165,25 @@ void serial_putc(const char c) psc->psc_buffer_8 = c; } +#if defined(CONFIG_SERIAL_MULTI) +void serial_putc_raw_dev(unsigned long dev_base, const char c) +#else +void serial_putc_raw(const char c) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + /* Wait for last character to go. */ + while (!(psc->psc_status & PSC_SR_TXEMP)) + ; + + psc->psc_buffer_8 = c; +} + + #if defined(CONFIG_SERIAL_MULTI) void serial_puts_dev (unsigned long dev_base, const char *s) #else @@ -239,6 +258,43 @@ void serial_setbrg(void) psc->ctlr = div & 0xff; } +#if defined(CONFIG_SERIAL_MULTI) +void serial_setrts_dev (unsigned long dev_base, int s) +#else +void serial_setrts(int s) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + + if (s) { + /* Assert RTS (become LOW) */ + psc->op1 = 0x1; + } + else { + /* Negate RTS (become HIGH) */ + psc->op0 = 0x1; + } +} + +#if defined(CONFIG_SERIAL_MULTI) +int serial_getcts_dev (unsigned long dev_base) +#else +int serial_getcts(void) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + + return (psc->ip & 0x1) ? 0 : 1; +} + #if defined(CONFIG_SERIAL_MULTI) int serial0_init(void) { diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index 61014ecd1f2..e95d68bfb88 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -258,12 +258,27 @@ /* #define CONFIG_FEC_10MBIT 1 */ #define CONFIG_PHY_ADDR 1 +/* + * LCD Splash Screen + */ +#define CONFIG_LCD 1 +#if defined(CONFIG_LCD) +#define CONFIG_SPLASH_SCREEN 1 +#define CFG_CONSOLE_IS_IN_ENV 1 +#define LCD_BPP LCD_MONOCHROME +#endif + /* * GPIO configuration */ /* 0x10000004 = 32MB SDRAM */ /* 0x90000004 = 64MB SDRAM */ +#if defined(CONFIG_LCD) +/* set PSC2 in UART mode */ +#define CFG_GPS_PORT_CONFIG 0x00000044 +#else #define CFG_GPS_PORT_CONFIG 0x00000004 +#endif /* * Miscellaneous configurable options diff --git a/include/lcd.h b/include/lcd.h index 7e23736bca9..b688583828b 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -148,7 +148,14 @@ typedef struct vidinfo { extern vidinfo_t panel_info; -#endif /* CONFIG_MPC823 or CONFIG_PXA250 */ +#elif defined(CONFIG_MCC200) +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 160) */ + ushort vl_row; /* Number of rows (i.e. 100) */ + + u_char vl_bpix; /* Bits per pixel, 0 = 1 */ +} vidinfo_t; +#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 */ /* Video functions */ -- cgit v1.3.1 From 43835aac4803d459dd73fabce09b27a826a381d7 Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Fri, 1 Sep 2006 11:59:23 +0200 Subject: Added interrupt handling capabilities for mpc5xxx processors. Also added Linux like BUG() macros. --- cpu/mpc5xxx/interrupts.c | 292 ++++++++++++++++++++++++++++++++++++++++++++--- include/common.h | 6 + include/mpc5xxx.h | 59 ++++++++++ 3 files changed, 342 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/cpu/mpc5xxx/interrupts.c b/cpu/mpc5xxx/interrupts.c index 7bacecd595b..7b5cb8be4e2 100644 --- a/cpu/mpc5xxx/interrupts.c +++ b/cpu/mpc5xxx/interrupts.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2006 + * Detlev Zundel, DENX Software Engineering, dzu@denx.de + * * (C) Copyright -2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -24,18 +27,212 @@ * MA 02111-1307 USA */ -/* - * interrupts.c - just enough support for the decrementer/timer +/* this section was ripped out of arch/ppc/syslib/mpc52xx_pic.c in the + * Linux 2.6 source with the following copyright. + * + * Based on (well, mostly copied from) the code from the 2.4 kernel by + * Dale Farnsworth and Kent Borg. + * + * Copyright (C) 2004 Sylvain Munaut + * Copyright (C) 2003 Montavista Software, Inc */ #include #include +#include #include -int interrupt_init_cpu (ulong *decrementer_count) +struct irq_action { + interrupt_handler_t *handler; + void *arg; + ulong count; +}; + +static struct irq_action irq_handlers[NR_IRQS]; + +static struct mpc5xxx_intr *intr; +static struct mpc5xxx_sdma *sdma; + +static void mpc5xxx_ic_disable(unsigned int irq) +{ + u32 val; + + if (irq == MPC5XXX_IRQ0) { + val = in_be32(&intr->ctrl); + val &= ~(1 << 11); + out_be32(&intr->ctrl, val); + } else if (irq < MPC5XXX_IRQ1) { + BUG(); + } else if (irq <= MPC5XXX_IRQ3) { + val = in_be32(&intr->ctrl); + val &= ~(1 << (10 - (irq - MPC5XXX_IRQ1))); + out_be32(&intr->ctrl, val); + } else if (irq < MPC5XXX_SDMA_IRQ_BASE) { + val = in_be32(&intr->main_mask); + val |= 1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE)); + out_be32(&intr->main_mask, val); + } else if (irq < MPC5XXX_PERP_IRQ_BASE) { + val = in_be32(&sdma->IntMask); + val |= 1 << (irq - MPC5XXX_SDMA_IRQ_BASE); + out_be32(&sdma->IntMask, val); + } else { + val = in_be32(&intr->per_mask); + val |= 1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE)); + out_be32(&intr->per_mask, val); + } +} + +static void mpc5xxx_ic_enable(unsigned int irq) +{ + u32 val; + + if (irq == MPC5XXX_IRQ0) { + val = in_be32(&intr->ctrl); + val |= 1 << 11; + out_be32(&intr->ctrl, val); + } else if (irq < MPC5XXX_IRQ1) { + BUG(); + } else if (irq <= MPC5XXX_IRQ3) { + val = in_be32(&intr->ctrl); + val |= 1 << (10 - (irq - MPC5XXX_IRQ1)); + out_be32(&intr->ctrl, val); + } else if (irq < MPC5XXX_SDMA_IRQ_BASE) { + val = in_be32(&intr->main_mask); + val &= ~(1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE))); + out_be32(&intr->main_mask, val); + } else if (irq < MPC5XXX_PERP_IRQ_BASE) { + val = in_be32(&sdma->IntMask); + val &= ~(1 << (irq - MPC5XXX_SDMA_IRQ_BASE)); + out_be32(&sdma->IntMask, val); + } else { + val = in_be32(&intr->per_mask); + val &= ~(1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE))); + out_be32(&intr->per_mask, val); + } +} + +static void mpc5xxx_ic_ack(unsigned int irq) +{ + u32 val; + + /* + * Only some irqs are reset here, others in interrupting hardware. + */ + + switch (irq) { + case MPC5XXX_IRQ0: + val = in_be32(&intr->ctrl); + val |= 0x08000000; + out_be32(&intr->ctrl, val); + break; + case MPC5XXX_CCS_IRQ: + val = in_be32(&intr->enc_status); + val |= 0x00000400; + out_be32(&intr->enc_status, val); + break; + case MPC5XXX_IRQ1: + val = in_be32(&intr->ctrl); + val |= 0x04000000; + out_be32(&intr->ctrl, val); + break; + case MPC5XXX_IRQ2: + val = in_be32(&intr->ctrl); + val |= 0x02000000; + out_be32(&intr->ctrl, val); + break; + case MPC5XXX_IRQ3: + val = in_be32(&intr->ctrl); + val |= 0x01000000; + out_be32(&intr->ctrl, val); + break; + default: + if (irq >= MPC5XXX_SDMA_IRQ_BASE + && irq < (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)) { + out_be32(&sdma->IntPend, + 1 << (irq - MPC5XXX_SDMA_IRQ_BASE)); + } + break; + } +} + +static void mpc5xxx_ic_disable_and_ack(unsigned int irq) +{ + mpc5xxx_ic_disable(irq); + mpc5xxx_ic_ack(irq); +} + +static void mpc5xxx_ic_end(unsigned int irq) +{ + mpc5xxx_ic_enable(irq); +} + +void mpc5xxx_init_irq(void) +{ + u32 intr_ctrl; + + /* Remap the necessary zones */ + intr = (struct mpc5xxx_intr *)(MPC5XXX_ICTL); + sdma = (struct mpc5xxx_sdma *)(MPC5XXX_SDMA); + + /* Disable all interrupt sources. */ + out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */ + out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */ + out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */ + out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */ + intr_ctrl = in_be32(&intr->ctrl); + intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */ + 0x00ff0000 | /* IRQ 0-3 level sensitive low active */ + 0x00001000 | /* MEE master external enable */ + 0x00000000 | /* 0 means disable IRQ 0-3 */ + 0x00000001; /* CEb route critical normally */ + out_be32(&intr->ctrl, intr_ctrl); + + /* Zero a bunch of the priority settings. */ + out_be32(&intr->per_pri1, 0); + out_be32(&intr->per_pri2, 0); + out_be32(&intr->per_pri3, 0); + out_be32(&intr->main_pri1, 0); + out_be32(&intr->main_pri2, 0); +} + +int mpc5xxx_get_irq(struct pt_regs *regs) +{ + u32 status; + int irq = -1; + + status = in_be32(&intr->enc_status); + + if (status & 0x00000400) { /* critical */ + irq = (status >> 8) & 0x3; + if (irq == 2) /* high priority peripheral */ + goto peripheral; + irq += MPC5XXX_CRIT_IRQ_BASE; + } else if (status & 0x00200000) { /* main */ + irq = (status >> 16) & 0x1f; + if (irq == 4) /* low priority peripheral */ + goto peripheral; + irq += MPC5XXX_MAIN_IRQ_BASE; + } else if (status & 0x20000000) { /* peripheral */ + peripheral: + irq = (status >> 24) & 0x1f; + if (irq == 0) { /* bestcomm */ + status = in_be32(&sdma->IntPend); + irq = ffs(status) + MPC5XXX_SDMA_IRQ_BASE - 1; + } else + irq += MPC5XXX_PERP_IRQ_BASE; + } + + return irq; +} + +/****************************************************************************/ + +int interrupt_init_cpu(ulong * decrementer_count) { *decrementer_count = get_tbclk() / CFG_HZ; + mpc5xxx_init_irq(); + return (0); } @@ -44,14 +241,32 @@ int interrupt_init_cpu (ulong *decrementer_count) /* * Handle external interrupts */ -void -external_interrupt(struct pt_regs *regs) +void external_interrupt(struct pt_regs *regs) { - puts("external_interrupt (oops!)\n"); + int irq, unmask = 1; + + irq = mpc5xxx_get_irq(regs); + + mpc5xxx_ic_disable_and_ack(irq); + + enable_interrupts(); + + if (irq_handlers[irq].handler != NULL) + (*irq_handlers[irq].handler) (irq_handlers[irq].arg); + else { + printf("\nBogus External Interrupt IRQ %d\n", irq); + /* + * turn off the bogus interrupt, otherwise it + * might repeat forever + */ + unmask = 0; + } + + if (unmask) + mpc5xxx_ic_end(irq); } -void -timer_interrupt_cpu (struct pt_regs *regs) +void timer_interrupt_cpu(struct pt_regs *regs) { /* nothing to do here */ return; @@ -63,22 +278,69 @@ timer_interrupt_cpu (struct pt_regs *regs) * Install and free a interrupt handler. */ -void -irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) +void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg) { + if (irq < 0 || irq >= NR_IRQS) { + printf("irq_install_handler: bad irq number %d\n", irq); + return; + } + if (irq_handlers[irq].handler != NULL) + printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n", + (ulong) handler, (ulong) irq_handlers[irq].handler); + + irq_handlers[irq].handler = handler; + irq_handlers[irq].arg = arg; + + mpc5xxx_ic_enable(irq); } -void -irq_free_handler(int vec) +void irq_free_handler(int irq) { + if (irq < 0 || irq >= NR_IRQS) { + printf("irq_free_handler: bad irq number %d\n", irq); + return; + } + + mpc5xxx_ic_disable(irq); + irq_handlers[irq].handler = NULL; + irq_handlers[irq].arg = NULL; } /****************************************************************************/ -void -do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) { - puts("IRQ related functions are unimplemented currently.\n"); + int irq, re_enable; + u32 intr_ctrl; + char *irq_config[] = { "level sensitive, active high", + "edge sensitive, rising active edge", + "edge sensitive, falling active edge", + "level sensitive, active low" + }; + + re_enable = disable_interrupts(); + + intr_ctrl = in_be32(&intr->ctrl); + printf("Interrupt configuration:\n"); + + for (irq = 0; irq <= 3; irq++) { + printf("IRQ%d: %s\n", irq, + irq_config[(intr_ctrl >> (22 - 2 * irq)) & 0x3]); + } + + puts("\nInterrupt-Information:\n" "Nr Routine Arg Count\n"); + + for (irq = 0; irq < NR_IRQS; irq++) + if (irq_handlers[irq].handler != NULL) + printf("%02d %08lx %08lx %ld\n", irq, + (ulong) irq_handlers[irq].handler, + (ulong) irq_handlers[irq].arg, + irq_handlers[irq].count); + + if (re_enable) + enable_interrupts(); } +#endif diff --git a/include/common.h b/include/common.h index 9a19001c18d..bee2fb70224 100644 --- a/include/common.h +++ b/include/common.h @@ -109,6 +109,12 @@ typedef volatile unsigned char vu_char; #define debugX(level,fmt,args...) #endif /* DEBUG */ +#define BUG() do { \ + printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ + panic("BUG!"); \ +} while (0) +#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0) + typedef void (interrupt_handler_t)(void *); #include /* boot information for Linux kernel */ diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index daa4d5f6d4c..1d20d1dcf55 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -232,6 +232,65 @@ #define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030) #define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038) +#define NR_IRQS 64 + +/* IRQ mapping - these are our logical IRQ numbers */ +#define MPC5XXX_CRIT_IRQ_NUM 4 +#define MPC5XXX_MAIN_IRQ_NUM 17 +#define MPC5XXX_SDMA_IRQ_NUM 17 +#define MPC5XXX_PERP_IRQ_NUM 23 + +#define MPC5XXX_CRIT_IRQ_BASE 1 +#define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM) +#define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM) +#define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM) + +#define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0) +#define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1) +#define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2) +#define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3) + +#define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1) +#define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2) +#define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3) +#define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5) +#define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6) +#define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7) +#define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8) +#define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9) +#define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10) +#define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11) +#define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12) +#define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13) +#define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14) +#define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15) +#define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16) + +#define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0) +#define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1) +#define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2) +#define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3) +#define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4) +#define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4) +#define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5) +#define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6) +#define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7) +#define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8) +#define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9) +#define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10) +#define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11) +#define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12) +#define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13) +#define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14) +#define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15) +#define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16) +#define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17) +#define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18) +#define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19) +#define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20) +#define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21) +#define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22) + /* General Purpose Timers registers */ #define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0) #define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4) -- cgit v1.3.1 From d7c2a02dea550e8701d1151010a823df48ad5c98 Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Fri, 1 Sep 2006 15:00:02 +0200 Subject: Added simple_strtoul(), getenv() and setenv() to the exported functions. Also bumped up ABI version to reflect this change. --- common/exports.c | 7 +++++-- include/_exports.h | 3 +++ include/exports.h | 5 ++++- 3 files changed, 12 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/common/exports.c b/common/exports.c index ef253381697..0cb4396ea4a 100644 --- a/common/exports.c +++ b/common/exports.c @@ -23,8 +23,11 @@ void jumptable_init (void) gd->jt[XF_get_version] = (void *) get_version; gd->jt[XF_malloc] = (void *) malloc; gd->jt[XF_free] = (void *) free; - gd->jt[XF_get_timer] = (void *)get_timer; - gd->jt[XF_udelay] = (void *)udelay; + gd->jt[XF_getenv] = (void *) getenv; + gd->jt[XF_setenv] = (void *) setenv; + gd->jt[XF_get_timer] = (void *) get_timer; + gd->jt[XF_simple_strtoul] = (void *) simple_strtoul; + gd->jt[XF_udelay] = (void *) udelay; #if defined(CONFIG_I386) || defined(CONFIG_PPC) gd->jt[XF_install_hdlr] = (void *) irq_install_handler; gd->jt[XF_free_hdlr] = (void *) irq_free_handler; diff --git a/include/_exports.h b/include/_exports.h index 61dcaaf331c..2b8ec3d3f91 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -12,6 +12,9 @@ EXPORT_FUNC(udelay) EXPORT_FUNC(get_timer) EXPORT_FUNC(vprintf) EXPORT_FUNC(do_reset) +EXPORT_FUNC(getenv) +EXPORT_FUNC(setenv) +EXPORT_FUNC(simple_strtoul) #if (CONFIG_COMMANDS & CFG_CMD_I2C) EXPORT_FUNC(i2c_write) EXPORT_FUNC(i2c_read) diff --git a/include/exports.h b/include/exports.h index 0eaf66e1838..8f7f61703c6 100644 --- a/include/exports.h +++ b/include/exports.h @@ -20,6 +20,9 @@ void udelay(unsigned long); unsigned long get_timer(unsigned long); void vprintf(const char *, va_list); void do_reset (void); +unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base); +char *getenv (char *name); +void setenv (char *varname, char *varvalue); #if (CONFIG_COMMANDS & CFG_CMD_I2C) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); @@ -37,7 +40,7 @@ enum { XF_MAX }; -#define XF_VERSION 2 +#define XF_VERSION 3 #if defined(CONFIG_I386) extern gd_t *global_data; -- cgit v1.3.1 From 360b4103677b27ad4018174a1d186218969d83a1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 3 Sep 2006 18:17:46 +0200 Subject: Fixed problems on PRS200 board caused by adding splash screen on MCC200 --- CHANGELOG | 2 ++ include/configs/mcc200.h | 41 ++++++++++++++++++++++------------------- 2 files changed, 24 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 5e6e1f36847..5743bbc3927 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fixed problems on PRS200 board caused by adding splash screen on MCC200 + * Extended README entry on coding style * Added another example showing simple interrupt interception. diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index e95d68bfb88..0c935bfcea9 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -37,12 +37,12 @@ #define CONFIG_MISC_INIT_R -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /* @@ -92,7 +92,7 @@ /* USB */ #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE /* @@ -167,7 +167,7 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ /* * I2C configuration @@ -183,9 +183,9 @@ * TEXT base always at 0xFFF00000 * ENV_ADDR always at 0xFFF40000 * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!) - * 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB + * 0xFE000000 for 32 MB + * 0xFF000000 for 16 MB + * 0xFF800000 for 8 MB */ #define CFG_FLASH_BASE 0xfc000000 #define CFG_FLASH_SIZE 0x04000000 @@ -207,9 +207,9 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ @@ -239,7 +239,7 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_BASE TEXT_BASE #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) # define CFG_RAMBOOT 1 #endif @@ -261,11 +261,14 @@ /* * LCD Splash Screen */ +#if !defined(CONFIG_PRS200) #define CONFIG_LCD 1 +#endif + #if defined(CONFIG_LCD) #define CONFIG_SPLASH_SCREEN 1 #define CFG_CONSOLE_IS_IN_ENV 1 -#define LCD_BPP LCD_MONOCHROME +#define LCD_BPP LCD_MONOCHROME #endif /* @@ -283,18 +286,18 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ #define CFG_LOAD_ADDR 0x100000 /* default load address */ -- cgit v1.3.1 From f60ba0d35e13e9dcf839d4563f9436d07468b1ef Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 4 Sep 2006 02:01:27 +0200 Subject: Fix build problems on sorcery board. --- CHANGELOG | 2 ++ board/sorcery/sorcery.c | 2 +- cpu/mpc8220/pci.c | 2 +- include/configs/sorcery.h | 1 + 4 files changed, 5 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index be18ac206c1..a288465b3b9 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix build problems on sorcery board. + * Fix coldfire build problems. Patch by Marian Balakowicz, 01 Sep 2006 diff --git a/board/sorcery/sorcery.c b/board/sorcery/sorcery.c index 35d6a06084b..165e9e2999f 100644 --- a/board/sorcery/sorcery.c +++ b/board/sorcery/sorcery.c @@ -33,7 +33,7 @@ long int initdram (int board_type) size = dramSetup (); - return get_ram_size((ulong *)CFG_SDRAM_BASE, size); + return get_ram_size(CFG_SDRAM_BASE, size); } int checkboard (void) diff --git a/cpu/mpc8220/pci.c b/cpu/mpc8220/pci.c index ca4a04d21e1..4ef214e5402 100644 --- a/cpu/mpc8220/pci.c +++ b/cpu/mpc8220/pci.c @@ -170,7 +170,7 @@ pci_mpc8220_init(struct pci_controller *hose) hose->region_count = 3; hose->cfg_addr = &(xcpci->cfg_adr); - hose->cfg_data = CONFIG_PCI_CFG_BUS; + hose->cfg_data = (volatile unsigned char *)CONFIG_PCI_CFG_BUS; pci_set_ops(hose, mpc8220_pci_read_config_byte, diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h index 3d907f888c2..4937638820b 100644 --- a/include/configs/sorcery.h +++ b/include/configs/sorcery.h @@ -261,6 +261,7 @@ #define CONFIG_MPC8220_FEC 1 #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ #define CONFIG_PHY_ADDR 0x1F +#define CONFIG_MII 1 /* * Miscellaneous configurable options -- cgit v1.3.1 From 887e2ec9ecf49366a60a49b32b73825804909865 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 7 Sep 2006 11:51:23 +0200 Subject: Add support for AMCC Sequoia PPC440EPx eval board - Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006 --- CHANGELOG | 10 + MAINTAINERS | 1 + MAKEALL | 9 +- Makefile | 39 ++- board/amcc/sequoia/Makefile | 52 +++ board/amcc/sequoia/config.mk | 41 +++ board/amcc/sequoia/init.S | 157 +++++++++ board/amcc/sequoia/sdram.c | 83 +++++ board/amcc/sequoia/sequoia.c | 552 ++++++++++++++++++++++++++++++ board/amcc/sequoia/sequoia.h | 67 ++++ board/amcc/sequoia/u-boot-nand.lds | 131 +++++++ board/amcc/sequoia/u-boot.lds | 145 ++++++++ common/cmd_bdinfo.c | 6 +- config.mk | 4 + cpu/ppc4xx/405gp_pci.c | 3 +- cpu/ppc4xx/4xx_enet.c | 184 ++++++++-- cpu/ppc4xx/Makefile | 2 +- cpu/ppc4xx/cpu.c | 109 +++++- cpu/ppc4xx/interrupts.c | 57 ++- cpu/ppc4xx/miiphy.c | 14 +- cpu/ppc4xx/ndfc.c | 173 ++++++++++ cpu/ppc4xx/serial.c | 263 +++++--------- cpu/ppc4xx/speed.c | 3 +- cpu/ppc4xx/start.S | 128 ++++++- cpu/ppc4xx/usb_ohci.c | 8 +- cpu/ppc4xx/usbdev.c | 20 +- cpu/ppc4xx/vecnum.h | 89 ++++- doc/README.nand-boot-ppc440 | 36 ++ dtt/lm75.c | 5 + include/405_mal.h | 2 +- include/440_i2c.h | 3 +- include/asm-ppc/processor.h | 4 + include/asm-ppc/u-boot.h | 3 +- include/configs/bamboo.h | 1 + include/configs/pcs440ep.h | 1 + include/configs/sequoia.h | 431 +++++++++++++++++++++++ include/configs/yellowstone.h | 1 + include/configs/yosemite.h | 1 + include/linux/mtd/compat.h | 2 + include/linux/mtd/ndfc.h | 67 ++++ include/ppc440.h | 609 +++++++++++++++++++++++++++++++-- include/ppc4xx_enet.h | 22 +- include/ppc_asm.tmpl | 2 +- lib_ppc/board.c | 12 +- nand_spl/board/amcc/sequoia/Makefile | 83 +++++ nand_spl/board/amcc/sequoia/config.mk | 49 +++ nand_spl/board/amcc/sequoia/u-boot.lds | 65 ++++ nand_spl/nand_boot.c | 178 ++++++++++ 48 files changed, 3606 insertions(+), 321 deletions(-) create mode 100644 board/amcc/sequoia/Makefile create mode 100644 board/amcc/sequoia/config.mk create mode 100644 board/amcc/sequoia/init.S create mode 100644 board/amcc/sequoia/sdram.c create mode 100644 board/amcc/sequoia/sequoia.c create mode 100644 board/amcc/sequoia/sequoia.h create mode 100644 board/amcc/sequoia/u-boot-nand.lds create mode 100644 board/amcc/sequoia/u-boot.lds create mode 100644 cpu/ppc4xx/ndfc.c create mode 100644 doc/README.nand-boot-ppc440 create mode 100644 include/configs/sequoia.h create mode 100644 include/linux/mtd/ndfc.h create mode 100644 nand_spl/board/amcc/sequoia/Makefile create mode 100644 nand_spl/board/amcc/sequoia/config.mk create mode 100644 nand_spl/board/amcc/sequoia/u-boot.lds create mode 100644 nand_spl/nand_boot.c (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 3c42d93fe84..576cd7fb861 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,16 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add support for AMCC Sequoia PPC440EPx eval board + - Add support for PPC440EPx & PPC440GRx + - Add support for PPC440EP(x)/GR(x) NAND controller + in cpu/ppc4xx directory + - Add NAND boot functionality for Sequoia board, + please see doc/README.nand-boot-ppc440 for details + - This Sequoia NAND image doesn't support environment + in NAND for now. This will be added in a short while. + Patch by Stefan Roese, 07 Sep 2006 + * Fix mkimage -l bug with multifile images on 64bit platforms Patch by David Updegraff, 06 Sep 2006 diff --git a/MAINTAINERS b/MAINTAINERS index 0c4cfb43cf4..42627196f86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -285,6 +285,7 @@ Stefan Roese ocotea PPC440GX p3p440 PPC440GP pcs440ep PPC440EP + sequoia PPC440EPx sycamore PPC405GPr walnut PPC405GP yellowstone PPC440GR diff --git a/MAKEALL b/MAKEALL index d2f86d3ac8a..8039f3d7082 100755 --- a/MAKEALL +++ b/MAKEALL @@ -13,7 +13,7 @@ if [ "${MAKEALL_LOGDIR}" ] ; then else LOG_DIR="LOG" fi - + if [ ! "${BUILD_DIR}" ] ; then BUILD_DIR="." fi @@ -85,9 +85,10 @@ LIST_4xx=" \ ML2 ml300 ocotea OCRTC \ ORSG p3p440 PCI405 pcs440ep \ PIP405 PLU405 PMC405 PPChameleonEVB \ - sbc405 VOH405 VOM405 W7OLMC \ - W7OLMG walnut WUH405 XPEDITE1K \ - yellowstone yosemite yucca bamboo \ + sbc405 sequoia sequoia_nand VOH405 \ + VOM405 W7OLMC W7OLMG walnut \ + WUH405 XPEDITE1K yellowstone yosemite \ + yucca bamboo \ " ######################################################################### diff --git a/Makefile b/Makefile index fc7b117e3fe..a63aaef15bc 100644 --- a/Makefile +++ b/Makefile @@ -48,7 +48,7 @@ VENDOR= # # U-boot build supports producing a object files to the separate external # directory. Two use cases are supported: -# +# # 1) Add O= to the make command line # 'make O=/tmp/build all' # @@ -59,12 +59,12 @@ VENDOR= # The second approach can also be used with a MAKEALL script # 'export BUILD_DIR=/tmp/build' # './MAKEALL' -# +# # Command line 'O=' setting overrides BUILD_DIR environent variable. -# +# # When none of the above methods is used the local build is performed and # the object files are placed in the source directory. -# +# ifdef O ifeq ("$(origin O)", "command line") @@ -101,7 +101,7 @@ src := $(SRCTREE)/ else obj := src := -endif +endif export obj src ######################################################################### @@ -214,13 +214,18 @@ SUBDIRS = tools \ post/cpu .PHONY : $(SUBDIRS) +ifeq ($(CONFIG_NAND_U_BOOT),y) +NAND_SPL = nand_spl +U_BOOT_NAND = $(obj)u-boot-nand.bin +endif + __OBJS := $(subst $(obj),,$(OBJS)) __LIBS := $(subst $(obj),,$(LIBS)) ######################################################################### ######################################################################### -ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map +ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) all: $(ALL) @@ -258,6 +263,12 @@ $(LIBS): $(SUBDIRS): $(MAKE) -C $@ all +$(NAND_SPL): version + $(MAKE) -C nand_spl all + +$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin + cat nand_spl/u-boot-spl-4k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin + version: @echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \ echo -n "$(U_BOOT_VERSION)" >> $(VERSION_FILE); \ @@ -309,7 +320,8 @@ endif ######################################################################### unconfig: - @rm -f $(obj)include/config.h $(obj)include/config.mk $(obj)board/*/config.tmp + @rm -f $(obj)include/config.h $(obj)include/config.mk \ + $(obj)board/*/config.tmp $(obj)board/*/*/config.tmp #======================================================================== # PowerPC @@ -1128,6 +1140,17 @@ PPChameleonEVB_HI_33_config: unconfig sbc405_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405 +sequoia_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx sequoia amcc + +sequoia_nand_config: unconfig + @ln -s board/amcc/sequoia/Makefile nand_spl/Makefile + @echo "#define CONFIG_NAND_U_BOOT" >include/config.h + @echo "Compile NAND boot image for sequoia" + @$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc + @echo "TEXT_BASE = 0x01000000" >board/amcc/sequoia/config.tmp + @echo "CONFIG_NAND_U_BOOT = y" >> include/config.mk + sycamore_config: unconfig @echo "Configuring for sycamore board as subset of walnut..." @$(MKCONFIG) -a walnut ppc ppc4xx walnut amcc @@ -2195,6 +2218,8 @@ clean: rm -f $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom rm -f $(obj)board/integratorap/u-boot.lds $(obj)board/integratorcp/u-boot.lds rm -f $(obj)include/bmp_logo.h + find nand_spl -lname "*" -print | xargs rm -f + rm -f nand_spl/u-boot-spl nand_spl/u-boot-spl.map clobber: clean find $(OBJTREE) -type f \( -name .depend \ diff --git a/board/amcc/sequoia/Makefile b/board/amcc/sequoia/Makefile new file mode 100644 index 00000000000..b29c04a0d9e --- /dev/null +++ b/board/amcc/sequoia/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2002-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +include $(TOPDIR)/include/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o sdram.o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk new file mode 100644 index 00000000000..7713a72be85 --- /dev/null +++ b/board/amcc/sequoia/config.mk @@ -0,0 +1,41 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# AMCC 440EPx Reference Platform (Sequoia) board +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0xFFFA0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S new file mode 100644 index 00000000000..3d4ac8543d5 --- /dev/null +++ b/board/amcc/sequoia/init.S @@ -0,0 +1,157 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 +#define _256M 0x10000000 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_8M 0x00000060 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ +#ifndef CONFIG_NAND_SPL + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) +#else + tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) +#endif + + /* TLB-entry for DDR SDRAM (Up to 2GB) */ + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + +#ifdef CFG_INIT_RAM_DCACHE + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) +#endif + + /* TLB-entry for PCI Memory */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) + + /* TLB-entry for EBC */ + tlbentry( CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB-entry for NAND */ + tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB-entry for Internal Registers & OCM */ + tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) + + /*TLB-entry PCI registers*/ + tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB-entry for peripherals */ + tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + + tlbtab_end + +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) + /* + * For NAND booting the first TLB has to be reconfigured to full size + * and with caching disabled after running from RAM! + */ +#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M) +#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1) +#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) + + .globl reconfig_tlb0 +reconfig_tlb0: + sync + isync + addi r4,r0,0x0000 /* TLB entry #0 */ + lis r5,TLB00@h + ori r5,r5,TLB00@l + tlbwe r5,r4,0x0000 /* Save it out */ + lis r5,TLB01@h + ori r5,r5,TLB01@l + tlbwe r5,r4,0x0001 /* Save it out */ + lis r5,TLB02@h + ori r5,r5,TLB02@l + tlbwe r5,r4,0x0002 /* Save it out */ + sync + isync + blr +#endif diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c new file mode 100644 index 00000000000..a62648bb5f4 --- /dev/null +++ b/board/amcc/sequoia/sdram.c @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/************************************************************************* + * + * initdram -- 440EPx's DDR controller is a DENALI Core + * + ************************************************************************/ +long int initdram (int board_type) +{ +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + volatile ulong val; + + mtsdram(DDR0_02, 0x00000000); + + /* + * Soft-reset SDRAM controller + */ + mtsdr(sdr_srst, SDR0_SRST0_DMC); + mtsdr(sdr_srst, 0x00000000); + + mtsdram(DDR0_00, 0x0000190A); + mtsdram(DDR0_01, 0x01000000); + mtsdram(DDR0_03, 0x02030602); + mtsdram(DDR0_04, 0x13030300); + mtsdram(DDR0_05, 0x0202050E); + mtsdram(DDR0_06, 0x0104C823); + mtsdram(DDR0_07, 0x000D0100); + mtsdram(DDR0_08, 0x02360001); + mtsdram(DDR0_09, 0x00011D5F); + mtsdram(DDR0_10, 0x00000300); + mtsdram(DDR0_11, 0x0027C800); + mtsdram(DDR0_12, 0x00000003); + mtsdram(DDR0_14, 0x00000000); + mtsdram(DDR0_17, 0x19000000); + mtsdram(DDR0_18, 0x19191919); + mtsdram(DDR0_19, 0x19191919); + mtsdram(DDR0_20, 0x0B0B0B0B); + mtsdram(DDR0_21, 0x0B0B0B0B); + mtsdram(DDR0_22, 0x00267F0B); + mtsdram(DDR0_23, 0x00000000); + mtsdram(DDR0_24, 0x01010002); + mtsdram(DDR0_26, 0x5B260181); + mtsdram(DDR0_27, 0x0000682B); + mtsdram(DDR0_28, 0x00000000); + mtsdram(DDR0_31, 0x00000000); + mtsdram(DDR0_42, 0x01000006); + mtsdram(DDR0_43, 0x050A0200); + mtsdram(DDR0_44, 0x00000005); + mtsdram(DDR0_02, 0x00000001); + + /* + * Wait for DCC master delay line to finish calibration + */ + mfsdram(DDR0_17, val); + while (((val >> 8) & 0x000007f) == 0) { + mfsdram(DDR0_17, val); + } +#endif /* #ifndef CONFIG_NAND_U_BOOT */ + + return (CFG_MBYTES_SDRAM << 20); +} diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c new file mode 100644 index 00000000000..95734b9c57c --- /dev/null +++ b/board/amcc/sequoia/sequoia.c @@ -0,0 +1,552 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "sequoia.h" + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +int board_early_init_f(void) +{ + unsigned long sdr0_cust0; + unsigned long sdr0_pfc1, sdr0_pfc2; + register uint reg; + + mtdcr(ebccfga, xbcfg); + mtdcr(ebccfgd, 0xb8400000); + + /*-------------------------------------------------------------------- + * Setup the GPIO pins + *-------------------------------------------------------------------*/ + /* test-only: take GPIO init from pcs440ep ???? in config file */ + out32(GPIO0_OR, 0x00000000); + out32(GPIO0_TCR, 0x0000000f); + out32(GPIO0_OSRL, 0x50015400); + out32(GPIO0_OSRH, 0x550050aa); + out32(GPIO0_TSRL, 0x50015400); + out32(GPIO0_TSRH, 0x55005000); + out32(GPIO0_ISR1L, 0x50000000); + out32(GPIO0_ISR1H, 0x00000000); + out32(GPIO0_ISR2L, 0x00000000); + out32(GPIO0_ISR2H, 0x00000100); + out32(GPIO0_ISR3L, 0x00000000); + out32(GPIO0_ISR3H, 0x00000000); + + out32(GPIO1_OR, 0x00000000); + out32(GPIO1_TCR, 0xc2000000); + out32(GPIO1_OSRL, 0x5c280000); + out32(GPIO1_OSRH, 0x00000000); + out32(GPIO1_TSRL, 0x0c000000); + out32(GPIO1_TSRH, 0x00000000); + out32(GPIO1_ISR1L, 0x00005550); + out32(GPIO1_ISR1H, 0x00000000); + out32(GPIO1_ISR2L, 0x00050000); + out32(GPIO1_ISR2H, 0x00000000); + out32(GPIO1_ISR3L, 0x01400000); + out32(GPIO1_ISR3H, 0x00000000); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ + mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(uic2er, 0x00000000); /* disable all */ + mtdcr(uic2cr, 0x00000000); /* all non-critical */ + mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic2sr, 0xffffffff); /* clear all */ + + /* 50MHz tmrclk */ + *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; + + /* clear write protects */ + *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; + + /* enable Ethernet */ + *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00; + + /* enable USB device */ + *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20; + + /* select Ethernet pins */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4; + mfsdr(SDR0_PFC2, sdr0_pfc2); + sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4; + mtsdr(SDR0_PFC2, sdr0_pfc2); + mtsdr(SDR0_PFC1, sdr0_pfc1); + + /* PCI arbiter enabled */ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); + + /* setup NAND FLASH */ + mfsdr(SDR0_CUST0, sdr0_cust0); + sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | + SDR0_CUST0_NDFC_ENABLE | + SDR0_CUST0_NDFC_BW_8_BIT | + SDR0_CUST0_NDFC_ARE_MASK | + (0x80000000 >> (28 + CFG_NAND_CS)); + mtsdr(SDR0_CUST0, sdr0_cust0); + + return 0; +} + +/*---------------------------------------------------------------------------+ + | misc_init_r. + +---------------------------------------------------------------------------*/ +int misc_init_r(void) +{ + uint pbcr; + int size_val = 0; + unsigned long usb2d0cr = 0; + unsigned long usb2phy0cr, usb2h0cr = 0; + unsigned long sdr0_pfc1; + char *act = getenv("usbact"); + + /* + * FLASH stuff... + */ + + /* Re-do sizing to get full correct info */ +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + mtdcr(ebccfga, pb3cr); +#else + mtdcr(ebccfga, pb0cr); +#endif + pbcr = mfdcr(ebccfgd); + switch (gd->bd->bi_flashsize) { + case 1 << 20: + size_val = 0; + break; + case 2 << 20: + size_val = 1; + break; + case 4 << 20: + size_val = 2; + break; + case 8 << 20: + size_val = 3; + break; + case 16 << 20: + size_val = 4; + break; + case 32 << 20: + size_val = 5; + break; + case 64 << 20: + size_val = 6; + break; + case 128 << 20: + size_val = 7; + break; + } + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + mtdcr(ebccfga, pb3cr); +#else + mtdcr(ebccfga, pb0cr); +#endif + mtdcr(ebccfgd, pbcr); + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + +#ifdef CFG_ENV_IS_IN_FLASH + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + /* Env protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + /* + * USB suff... + */ + if (act == NULL || strcmp(act, "hostdev") == 0) { + /* SDR Setting */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + mfsdr(SDR0_USB0, usb2d0cr); + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2H0CR, usb2h0cr); + + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + + /* An 8-bit/60MHz interface is the only possible alternative + when connecting the Device to the PHY */ + usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ + + /* To enable the USB 2.0 Device function through the UTMI interface */ + usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; + usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ + + sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ + + mtsdr(SDR0_PFC1, sdr0_pfc1); + mtsdr(SDR0_USB0, usb2d0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB2H0CR, usb2h0cr); + + /*clear resets*/ + udelay (1000); + mtsdr(SDR0_SRST1, 0x00000000); + udelay (1000); + mtsdr(SDR0_SRST0, 0x00000000); + + printf("USB: Host(int phy) Device(ext phy)\n"); + + } else if (strcmp(act, "dev") == 0) { + /*-------------------PATCH-------------------------------*/ + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + + udelay (1000); + mtsdr(SDR0_SRST1, 0x672c6000); + + udelay (1000); + mtsdr(SDR0_SRST0, 0x00000080); + + udelay (1000); + mtsdr(SDR0_SRST1, 0x60206000); + + *(unsigned int *)(0xe0000350) = 0x00000001; + + udelay (1000); + mtsdr(SDR0_SRST1, 0x60306000); + /*-------------------PATCH-------------------------------*/ + + /* SDR Setting */ + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2H0CR, usb2h0cr); + mfsdr(SDR0_USB0, usb2d0cr); + mfsdr(SDR0_PFC1, sdr0_pfc1); + + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/ + + usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/ + + usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; + usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/ + + sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/ + + mtsdr(SDR0_USB2H0CR, usb2h0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB0, usb2d0cr); + mtsdr(SDR0_PFC1, sdr0_pfc1); + + /*clear resets*/ + udelay (1000); + mtsdr(SDR0_SRST1, 0x00000000); + udelay (1000); + mtsdr(SDR0_SRST0, 0x00000000); + + printf("USB: Device(int phy)\n"); + } + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_MBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + return 0; +} +#endif + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; +#if 0 + /*--------------------------------------------------------------------------+ + * Cactus is always configured as the host & requires the + * PCI arbiter to be enabled ??? + *--------------------------------------------------------------------------*/ + unsigned long strap; + mfsdr(sdr_sdstp1, strap); + if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) { + printf("PCI: SDR0_STRP1[PAE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return 0; + } +#endif + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB3 devices to 0. + | Set PLB3 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB4 devices to 0. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /*-------------------------------------------------------------------------+ + | Set Nebula PLB4 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /*--------------------------------------------------------------------------+ + * Set up Direct MMIO registers + *--------------------------------------------------------------------------*/ + /*--------------------------------------------------------------------------+ + | PowerPC440EPX PCI Master configuration. + | Map one 1Gig range of PLB/processor addresses to PCI memory space. + | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers + *--------------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*--------------------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* Cactus is always configured as host. */ + return (1); +} +#endif /* defined(CONFIG_PCI) */ diff --git a/board/amcc/sequoia/sequoia.h b/board/amcc/sequoia/sequoia.h new file mode 100644 index 00000000000..1d44b164649 --- /dev/null +++ b/board/amcc/sequoia/sequoia.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +/*----------------------------------------------------------------------------+ + | EBC Configuration Register - EBC0_CFG + +----------------------------------------------------------------------------*/ +/* External Bus Three-State Control */ +#define EBC0_CFG_EBTC_DRIVEN 0x80000000 +/* Device-Paced Time-out Disable */ +#define EBC0_CFG_PTD_ENABLED 0x00000000 +/* Ready Timeout Count */ +#define EBC0_CFG_RTC_MASK 0x38000000 +#define EBC0_CFG_RTC_16PERCLK 0x00000000 +#define EBC0_CFG_RTC_32PERCLK 0x08000000 +#define EBC0_CFG_RTC_64PERCLK 0x10000000 +#define EBC0_CFG_RTC_128PERCLK 0x18000000 +#define EBC0_CFG_RTC_256PERCLK 0x20000000 +#define EBC0_CFG_RTC_512PERCLK 0x28000000 +#define EBC0_CFG_RTC_1024PERCLK 0x30000000 +#define EBC0_CFG_RTC_2048PERCLK 0x38000000 +/* External Master Priority Low */ +#define EBC0_CFG_EMPL_LOW 0x00000000 +#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000 +#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000 +#define EBC0_CFG_EMPL_HIGH 0x06000000 +/* External Master Priority High */ +#define EBC0_CFG_EMPH_LOW 0x00000000 +#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000 +#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000 +#define EBC0_CFG_EMPH_HIGH 0x01800000 +/* Chip Select Three-State Control */ +#define EBC0_CFG_CSTC_DRIVEN 0x00400000 +/* Burst Prefetch */ +#define EBC0_CFG_BPF_ONEDW 0x00000000 +#define EBC0_CFG_BPF_TWODW 0x00100000 +#define EBC0_CFG_BPF_FOURDW 0x00200000 +/* External Master Size */ +#define EBC0_CFG_EMS_8BIT 0x00000000 +/* Power Management Enable */ +#define EBC0_CFG_PME_DISABLED 0x00000000 +#define EBC0_CFG_PME_ENABLED 0x00020000 +/* Power Management Timer */ +#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) + +#define SDR0_USB0 0x0320 /* USB Control Register */ diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds new file mode 100644 index 00000000000..c3d3d968fed --- /dev/null +++ b/board/amcc/sequoia/u-boot-nand.lds @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/sequoia/u-boot.lds b/board/amcc/sequoia/u-boot.lds new file mode 100644 index 00000000000..a423f982858 --- /dev/null +++ b/board/amcc/sequoia/u-boot.lds @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 256e4bc7968..70de795deed 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -62,11 +62,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440SP) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) print_str ("procfreq", strmhz(buf, bd->bi_procfreq)); print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq)); #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) + defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq)); #endif #else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */ diff --git a/config.mk b/config.mk index 3ed7107fb80..0f5d0f43d94 100644 --- a/config.mk +++ b/config.mk @@ -132,8 +132,12 @@ DBGFLAGS= -g # -DDEBUG OPTFLAGS= -Os #-fomit-frame-pointer ifndef LDSCRIPT #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug +ifeq ($(CONFIG_NAND_U_BOOT),y) +LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds +else LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds endif +endif OBJCFLAGS += --gap-fill=0xff gccincdir := $(shell $(CC) -print-file-name=include) diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index 0b0686bcf71..03128d3f6d1 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -555,7 +555,8 @@ void pci_440_init (struct pci_controller *hose) #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif -#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) +#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ + !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER); #endif hose->last_busno = pci_hose_scan(hose); diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index fab65aff78a..5b1c17c351a 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -130,7 +130,17 @@ #define BI_PHYMODE_NONE 0 #define BI_PHYMODE_ZMII 1 #define BI_PHYMODE_RGMII 2 +#define BI_PHYMODE_GMII 3 +#define BI_PHYMODE_RTBI 4 +#define BI_PHYMODE_TBI 5 +#if defined (CONFIG_440EPX) +#define BI_PHYMODE_SMII 6 +#define BI_PHYMODE_MII 7 +#endif +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) +#endif /*-----------------------------------------------------------------------------+ * Global variables. TX and RX descriptors and buffers. @@ -181,7 +191,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) { EMAC_4XX_HW_PST hw_p = dev->priv; uint32_t failsafe = 10000; -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) unsigned long mfr; #endif @@ -205,19 +215,19 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) } /* EMAC RESET */ -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* provide clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); - mfr |= 0x08000000; + mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); mtsdr(sdr_mfr, mfr); #endif out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* remove clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); - mfr &= ~0x08000000; + mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); mtsdr(sdr_mfr, mfr); #endif @@ -317,10 +327,50 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) out32 (RGMII_FER, rmiifer); return ((int)pfc1); - } #endif /* CONFIG_440_GX */ +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) +{ + unsigned long zmiifer=0x0; + + /* + * Right now only 2*RGMII is supported. Please extend when needed. + * sr - 2006-08-29 + */ + switch (1) { + case 0: + /* 1 x GMII port */ + out32 (ZMII_FER, 0x00); + out32 (RGMII_FER, 0x00000037); + bis->bi_phymode[0] = BI_PHYMODE_GMII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + break; + case 1: + /* 2 x RGMII ports */ + out32 (ZMII_FER, 0x00); + out32 (RGMII_FER, 0x00000055); + bis->bi_phymode[0] = BI_PHYMODE_RGMII; + bis->bi_phymode[1] = BI_PHYMODE_RGMII; + break; + case 2: + /* 2 x SMII ports */ + + break; + default: + break; + } + + /* Ensure we setup mdio for this devnum and ONLY this devnum */ + zmiifer = in32 (ZMII_FER); + zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); + out32 (ZMII_FER, zmiifer); + + return ((int)0x0); +} +#endif /* CONFIG_440EPX */ + static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) { int i, j; @@ -332,13 +382,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) unsigned mode_reg; unsigned short devnum; unsigned short reg_short; -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) sys_info_t sysinfo; -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) int ethgroup = -1; #endif #endif -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE) unsigned long mfr; #endif @@ -352,7 +405,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) return -1; } -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* Need to get the OPB frequency so we can access the PHY */ get_sys_info (&sysinfo); #endif @@ -407,7 +462,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); -#elif defined(CONFIG_440GX) +#elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); #elif defined(CONFIG_440GP) /* set RMII mode */ @@ -429,10 +484,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) __asm__ volatile ("eieio"); /* reset emac so we have access to the phy */ -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* provide clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); - mfr |= 0x08000000; + mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum); mtsdr(sdr_mfr, mfr); #endif @@ -444,15 +499,19 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) udelay (1000); failsafe--; } + if (failsafe <= 0) + printf("\nProblem resetting EMAC!\n"); -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* remove clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); - mfr &= ~0x08000000; + mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum); mtsdr(sdr_mfr, mfr); #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* Whack the M1 register */ mode_reg = 0x0; mode_reg &= ~0x00000038; @@ -502,15 +561,39 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) * otherwise, just check the speeds & feeds */ if (hw_p->first_init == 0) { +#if defined(CONFIG_88E1111_CLK_DELAY) + /* + * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs + * the "RGMII transmit timing control" and "RGMII receive + * timing control" bits set, so that Gbit communication works + * without problems. + * Also set the "Transmitter disable" to 1 to enable the + * transmitter. + * After setting these bits a soft-reset must occur for this + * change to become active. + */ + miiphy_read (dev->name, reg, 0x14, ®_short); + reg_short |= (1 << 7) | (1 << 1) | (1 << 0); + miiphy_write (dev->name, reg, 0x14, reg_short); +#endif +#if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */ + miiphy_write (dev->name, reg, 0x14, 0x0ce3); + miiphy_write (dev->name, reg, 0x18, 0x4101); + miiphy_write (dev->name, reg, 0x09, 0x0e00); + miiphy_write (dev->name, reg, 0x04, 0x01e1); +#endif miiphy_reset (dev->name, reg); -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) + #if defined(CONFIG_CIS8201_PHY) /* * Cicada 8201 PHY needs to have an extended register whacked * for RGMII mode. */ - if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) { + if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) { #if defined(CONFIG_CIS8201_SHORT_ETCH) miiphy_write (dev->name, reg, 23, 0x1300); #else @@ -580,7 +663,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) (int) speed, (duplex == HALF) ? "HALF" : "FULL"); } -#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) +#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ + !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) mfsdr(sdr_mfr, reg); if (speed == 100) { @@ -603,15 +687,34 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); else if (speed == 100) reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); - else + else if (speed == 10) reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); - + else { + printf("Error in RGMII Speed\n"); + return -1; + } out32 (RGMII_SSR, reg); } #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + if (speed == 1000) + reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); + else if (speed == 100) + reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); + else if (speed == 10) + reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); + else { + printf("Error in RGMII Speed\n"); + return -1; + } + out32 (RGMII_SSR, reg); +#endif + /* set the Mal configuration reg */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); #else @@ -795,8 +898,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* set speed */ if (speed == _1000BASET) { -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) unsigned long pfc1; + mfsdr (sdr_pfc1, pfc1); pfc1 |= SDR0_PFC1_EM_1000; mtsdr (sdr_pfc1, pfc1); @@ -942,6 +1047,14 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, #define UIC0SR uic0sr #endif +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define UICMSR_ETHX uic0msr +#define UICSR_ETHX uic0sr +#else +#define UICMSR_ETHX uic1msr +#define UICSR_ETHX uic1sr +#endif + int enetInt (struct eth_device *dev) { int serviced; @@ -950,6 +1063,7 @@ int enetInt (struct eth_device *dev) unsigned long emac_isr = 0; unsigned long mal_rx_eob; unsigned long my_uic0msr, my_uic1msr; + unsigned long my_uicmsr_ethx; #if defined(CONFIG_440GX) unsigned long my_uic2msr; @@ -977,8 +1091,11 @@ int enetInt (struct eth_device *dev) #if defined(CONFIG_440GX) my_uic2msr = mfdcr (uic2msr); #endif + my_uicmsr_ethx = mfdcr (UICMSR_ETHX); + if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) - && !(my_uic1msr & (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE))) { + && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) + && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) { /* not for us */ return (rc); } @@ -997,8 +1114,7 @@ int enetInt (struct eth_device *dev) mal_isr = mfdcr (malesr); /* look for mal error */ if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) { - mal_err (dev, mal_isr, my_uic0msr, - MAL_UIC_DEF, MAL_UIC_ERR); + mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR); serviced = 1; rc = 0; } @@ -1006,7 +1122,7 @@ int enetInt (struct eth_device *dev) /* port by port dispatch of emac interrupts */ if (hw_p->devnum == 0) { - if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */ + if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */ emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); @@ -1017,14 +1133,15 @@ int enetInt (struct eth_device *dev) if ((hw_p->emac_ier & emac_isr) || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */ return (rc); /* we had errors so get out */ } } #if !defined(CONFIG_440SP) if (hw_p->devnum == 1) { - if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */ + if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */ emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); @@ -1035,7 +1152,8 @@ int enetInt (struct eth_device *dev) if ((hw_p->emac_ier & emac_isr) || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */ return (rc); /* we had errors so get out */ } } @@ -1102,10 +1220,10 @@ int enetInt (struct eth_device *dev) mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ switch (hw_p->devnum) { case 0: - mtdcr (uic1sr, UIC_ETH0); + mtdcr (UICSR_ETHX, UIC_ETH0); break; case 1: - mtdcr (uic1sr, UIC_ETH1); + mtdcr (UICSR_ETHX, UIC_ETH1); break; #if defined (CONFIG_440GX) case 2: @@ -1512,7 +1630,7 @@ int ppc_4xx_eth_initialize (bd_t * bis) if (0 == virgin) { /* set the MAL IER ??? names may change with new spec ??? */ -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) mal_ier = MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ; diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 93416b57bf7..16dc8d62c05 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -30,7 +30,7 @@ SOBJS = dcr.o COBJS = 405gp_pci.o 4xx_enet.o \ bedbug_405.o commproc.o \ cpu.o cpu_init.o i2c.o interrupts.o \ - miiphy.o sdram.o serial.o \ + miiphy.o ndfc.o sdram.o serial.o \ spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o \ 440spe_pcie.o diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index bc51fbfdbed..94478dbb109 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -41,14 +41,15 @@ DECLARE_GLOBAL_DATA_PTR; #endif - #if defined(CONFIG_440) #define FREQ_EBC (sys_info.freqEPB) #else #define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv) #endif -#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_405GP) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define PCI_ASYNC @@ -58,7 +59,8 @@ int pci_async_enabled(void) return (mfdcr(strap) & PSR_PCI_ASYNC_EN); #endif -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) unsigned long val; mfsdr(sdr_sdstp1, val); @@ -82,9 +84,10 @@ int pci_arbiter_enabled(void) return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK); #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ - defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ - defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long val; mfsdr(sdr_sdstp1, val); @@ -93,8 +96,10 @@ int pci_arbiter_enabled(void) } #endif -#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define I2C_BOOTROM @@ -102,17 +107,75 @@ int i2c_bootrom_enabled(void) { #if defined(CONFIG_405EP) return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP); -#endif - -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ - defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ - defined(CONFIG_440SPE) +#else unsigned long val; mfsdr(sdr_sdcs, val); return (val & SDR0_SDCS_SDD); #endif } + +#if defined(CONFIG_440GX) +#define SDR0_PINSTP_SHIFT 29 +static char *bootstrap_str[] = { + "EBC (16 bits)", + "EBC (8 bits)", + "EBC (32 bits)", + "EBC (8 bits)", + "PCI", + "I2C (Addr 0x54)", + "Reserved", + "I2C (Addr 0x50)", +}; +#endif + +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#define SDR0_PINSTP_SHIFT 30 +static char *bootstrap_str[] = { + "EBC (8 bits)", + "PCI", + "I2C (Addr 0x54)", + "I2C (Addr 0x50)", +}; +#endif + +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define SDR0_PINSTP_SHIFT 29 +static char *bootstrap_str[] = { + "EBC (8 bits)", + "PCI", + "NAND (8 bits)", + "EBC (16 bits)", + "EBC (16 bits)", + "I2C (Addr 0x54)", + "PCI", + "I2C (Addr 0x52)", +}; +#endif + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define SDR0_PINSTP_SHIFT 29 +static char *bootstrap_str[] = { + "EBC (8 bits)", + "EBC (16 bits)", + "EBC (16 bits)", + "NAND (8 bits)", + "PCI", + "I2C (Addr 0x54)", + "PCI", + "I2C (Addr 0x52)", +}; +#endif + +#if defined(SDR0_PINSTP_SHIFT) +static int bootstrap_option(void) +{ + unsigned long val; + + mfsdr(sdr_pinstp, val); + return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT); +} +#endif /* SDR0_PINSTP_SHIFT */ #endif @@ -244,6 +307,22 @@ int checkcpu (void) #endif /* CONFIG_440GR */ #endif /* CONFIG_440 */ + case PVR_440EPX1_RA: + puts("EPx Rev. A - Security/Kasumi support"); + break; + + case PVR_440EPX2_RA: + puts("EPx Rev. A - No Security/Kasumi support"); + break; + + case PVR_440GRX1_RA: + puts("GRx Rev. A - Security/Kasumi support"); + break; + + case PVR_440GRX2_RA: + puts("GRx Rev. A - No Security/Kasumi support"); + break; + case PVR_440SP_RA: puts("SP Rev. A"); break; @@ -272,6 +351,10 @@ int checkcpu (void) #if defined(I2C_BOOTROM) printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); +#if defined(SDR0_PINSTP_SHIFT) + printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A'); + printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); +#endif #endif #if defined(CONFIG_PCI) diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 886f4051562..c5a9f02566a 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -57,12 +57,13 @@ static struct irq_action irq_vecs1[32]; /* For UIC1 */ void uic1_interrupt( void * parms); /* UIC1 handler */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) static struct irq_action irq_vecs2[32]; /* For UIC2 */ void uic2_interrupt( void * parms); /* UIC2 handler */ #endif /* CONFIG_440GX CONFIG_440SPE */ -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) static struct irq_action irq_vecs3[32]; /* For UIC3 */ void uic3_interrupt( void * parms); /* UIC3 handler */ #endif /* CONFIG_440SPE */ @@ -119,12 +120,13 @@ int interrupt_init_cpu (unsigned *decrementer_count) irq_vecs1[vec].handler = NULL; irq_vecs1[vec].arg = NULL; irq_vecs1[vec].count = 0; -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) irq_vecs2[vec].handler = NULL; irq_vecs2[vec].arg = NULL; irq_vecs2[vec].count = 0; #endif /* CONFIG_440GX */ -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) irq_vecs3[vec].handler = NULL; irq_vecs3[vec].arg = NULL; irq_vecs3[vec].count = 0; @@ -230,6 +232,32 @@ void external_interrupt(struct pt_regs *regs) } /* external_interrupt CONFIG_440GX */ +#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +void external_interrupt(struct pt_regs *regs) +{ + ulong uic_msr; + + /* + * Read masked interrupt status register to determine interrupt source + */ + /* 440 SPe uses base uic register */ + uic_msr = mfdcr(uic0msr); + + if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) ) + uic1_interrupt(0); + + if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) ) + uic2_interrupt(0); + + if (uic_msr & ~(UICB0_ALL)) + uic0_interrupt(0); + + mtdcr(uic0sr, uic_msr); + + return; + +} /* external_interrupt CONFIG_440EPX & CONFIG_440GRX */ + #elif defined(CONFIG_440SPE) void external_interrupt(struct pt_regs *regs) { @@ -303,7 +331,8 @@ void external_interrupt(struct pt_regs *regs) } #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* Handler for UIC0 interrupt */ void uic0_interrupt( void * parms) { @@ -394,7 +423,8 @@ void uic1_interrupt( void * parms) } #endif /* defined(CONFIG_440) */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* Handler for UIC2 interrupt */ void uic2_interrupt( void * parms) { @@ -496,7 +526,8 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) int i = vec; #if defined(CONFIG_440) -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) if ((vec > 31) && (vec < 64)) { i = vec - 32; irqa = irq_vecs1; @@ -523,7 +554,8 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) irqa[i].arg = arg; #if defined(CONFIG_440) -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) if ((vec > 31) && (vec < 64)) mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i)); else if (vec > 63) @@ -546,7 +578,8 @@ void irq_free_handler (int vec) int i = vec; #if defined(CONFIG_440) -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) if ((vec > 31) && (vec < 64)) { irqa = irq_vecs1; i = vec - 32; @@ -567,7 +600,8 @@ void irq_free_handler (int vec) #endif #if defined(CONFIG_440) -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) if ((vec > 31) && (vec < 64)) mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i)); else if (vec > 63) @@ -635,7 +669,8 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf("\n"); #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) printf ("\nUIC 2\n"); printf ("Nr Routine Arg Count\n"); diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index aa580ed48f9..6b98025308f 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -173,7 +173,8 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, } sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ; #else @@ -183,7 +184,9 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; #endif -#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE) +#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \ + !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ + !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; #endif sta_reg = sta_reg | (addr << 5); /* Phy address */ @@ -244,7 +247,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, sta_reg = 0; sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE; #else @@ -254,7 +258,9 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; #endif -#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE) +#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \ + !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ + !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ #endif sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */ diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c new file mode 100644 index 00000000000..e4ab326bbfc --- /dev/null +++ b/cpu/ppc4xx/ndfc.c @@ -0,0 +1,173 @@ +/* + * Overview: + * Platform independend driver for NDFC (NanD Flash Controller) + * integrated into EP440 cores + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Based on original work by + * Thomas Gleixner + * Copyright 2006 IBM + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include +#include +#include +#include + +static u8 hwctl = 0; + +static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + switch (cmd) { + case NAND_CTL_SETCLE: + hwctl |= 0x1; + break; + + case NAND_CTL_CLRCLE: + hwctl &= ~0x1; + break; + + case NAND_CTL_SETALE: + hwctl |= 0x2; + break; + + case NAND_CTL_CLRALE: + hwctl &= ~0x2; + break; + } +} + +static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; + + if (hwctl & 0x1) + out8(base + NDFC_CMD, byte); + else if (hwctl & 0x2) + out8(base + NDFC_ALE, byte); + else + out8(base + NDFC_DATA, byte); +} + +static u_char ndfc_read_byte(struct mtd_info *mtdinfo) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; + + return (in8(base + NDFC_DATA)); +} + +static int ndfc_dev_ready(struct mtd_info *mtdinfo) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; + + while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY)) + ; + + return 1; +} + +#ifndef CONFIG_NAND_SPL +/* + * Don't use these speedup functions in NAND boot image, since the image + * has to fit into 4kByte. + */ + +/* + * Speedups for buffer read/write/verify + * + * NDFC allows 32bit read/write of data. So we can speed up the buffer + * functions. No further checking, as nand_base will always read/write + * page aligned. + */ +static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; + uint32_t *p = (uint32_t *) buf; + + for(;len > 0; len -= 4) + *p++ = in32(base + NDFC_DATA); +} + +static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; + uint32_t *p = (uint32_t *) buf; + + for(; len > 0; len -= 4) + out32(base + NDFC_DATA, *p++); +} + +static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; + uint32_t *p = (uint32_t *) buf; + + for(; len > 0; len -= 4) + if (*p++ != in32(base + NDFC_DATA)) + return -1; + + return 0; +} +#endif /* #ifndef CONFIG_NAND_SPL */ + +void board_nand_init(struct nand_chip *nand) +{ + nand->eccmode = NAND_ECC_SOFT; + + nand->hwcontrol = ndfc_hwcontrol; + nand->read_byte = ndfc_read_byte; + nand->write_byte = ndfc_write_byte; + nand->dev_ready = ndfc_dev_ready; + +#ifndef CONFIG_NAND_SPL + nand->write_buf = ndfc_write_buf; + nand->read_buf = ndfc_read_buf; + nand->verify_buf = ndfc_verify_buf; +#else + /* + * Setup EBC (CS0 only right now) + */ + mtdcr(ebccfga, xbcfg); + mtdcr(ebccfgd, 0xb8400000); + + mtebc(pb0cr, CFG_EBC_PB0CR); + mtebc(pb0ap, CFG_EBC_PB0AP); +#endif + + /* Set NandFlash Core Configuration Register */ + /* Chip select 3, 1col x 2 rows */ + out32(CFG_NAND_BASE + NDFC_CCR, 0x00000000 | (CFG_NAND_CS << 24)); + out32(CFG_NAND_BASE + NDFC_BCFG0 + (CFG_NAND_CS << 2), 0x80002222); +} + +#endif diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index ad3ca6e819e..fab0d950063 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -264,10 +264,12 @@ int serial_tstc () #endif /* CONFIG_IOP480 */ /*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \ + defined(CONFIG_440) #if defined(CONFIG_440) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400 #else @@ -279,15 +281,34 @@ int serial_tstc () #define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600 #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define CR0_MASK 0xdfffffff -#define CR0_EXTCLK_ENA 0x00800000 -#define CR0_UDIV_POS 0 -#else +#if defined(CONFIG_440GP) #define CR0_MASK 0x3fff0000 #define CR0_EXTCLK_ENA 0x00600000 #define CR0_UDIV_POS 16 -#endif /* CONFIG_440GX */ +#define UDIV_SUBTRACT 1 +#define UART0_SDR cntrl0 +#define MFREG(a, d) d = mfdcr(a) +#define MTREG(a, d) mtdcr(a, d) +#else /* #if defined(CONFIG_440GP) */ +/* all other 440 PPC's access clock divider via sdr register */ +#define CR0_MASK 0xdfffffff +#define CR0_EXTCLK_ENA 0x00800000 +#define CR0_UDIV_POS 0 +#define UDIV_SUBTRACT 0 +#define UART0_SDR sdr_uart0 +#define UART1_SDR sdr_uart1 +#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPe) +#define UART2_SDR sdr_uart2 +#endif +#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRx) +#define UART3_SDR sdr_uart3 +#endif +#define MFREG(a, d) mfsdr(a, d) +#define MTREG(a, d) mtsdr(a, d) +#endif /* #if defined(CONFIG_440GP) */ #elif defined(CONFIG_405EP) #define UART0_BASE 0xef600300 #define UART1_BASE 0xef600400 @@ -309,21 +330,15 @@ int serial_tstc () #if defined(CONFIG_UART1_CONSOLE) #define ACTING_UART0_BASE UART1_BASE #define ACTING_UART1_BASE UART0_BASE -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ - defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ - defined(CONFIG_440SPE) -#define UART0_SDR sdr_uart1 -#define UART1_SDR sdr_uart0 -#endif /* CONFIG_440GX */ #else #define ACTING_UART0_BASE UART0_BASE #define ACTING_UART1_BASE UART1_BASE -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ - defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ - defined(CONFIG_440SPE) -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 -#endif /* CONFIG_440GX */ +#endif + +#if defined(CONFIG_SERIAL_MULTI) +#define UART_BASE dev_base +#else +#define UART_BASE ACTING_UART0_BASE #endif #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK) @@ -419,7 +434,7 @@ static void serial_divs (int baudrate, unsigned long *pudiv, *pbdiv = div/udiv; } -#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */ +#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */ /* * Minimal serial functions needed to use one of the SMC ports @@ -441,23 +456,9 @@ int serial_init(void) unsigned long tmp; #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \ - defined(CONFIG_440SPE) -#if defined(CONFIG_SERIAL_MULTI) - if (UART0_BASE == dev_base) { - mfsdr(UART0_SDR,reg); - reg &= ~CR0_MASK; - } else { - mfsdr(UART1_SDR,reg); - reg &= ~CR0_MASK; - } -#else - mfsdr(UART0_SDR,reg); + MFREG(UART0_SDR, reg); reg &= ~CR0_MASK; -#endif -#else - reg = mfdcr(cntrl0) & ~CR0_MASK; -#endif /* CONFIG_440GX */ + #ifdef CFG_EXT_SERIAL_CLOCK reg |= CR0_EXTCLK_ENA; udiv = 1; @@ -471,47 +472,34 @@ int serial_init(void) serial_divs (gd->baudrate, &udiv, &bdiv); #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ - defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ - defined(CONFIG_440SPE) - reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */ -#if defined(CONFIG_SERIAL_MULTI) - if (UART0_BASE == dev_base) { - mtsdr (UART0_SDR,reg); - } else { - mtsdr (UART1_SDR,reg); - } -#else - mtsdr (UART0_SDR,reg); + reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ + + /* + * Configure input clock to baudrate generator for all + * available serial ports here + */ + MTREG(UART0_SDR, reg); +#if defined(UART1_SDR) + MTREG(UART1_SDR, reg); #endif -#else - reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ - mtdcr (cntrl0, reg); +#if defined(UART2_SDR) + MTREG(UART2_SDR, reg); #endif - -#if defined(CONFIG_SERIAL_MULTI) - out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ - out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */ - out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (dev_base + UART_LSR); /* clear line status */ - val = in8 (dev_base + UART_RBR); /* read receive buffer */ - out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */ - out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */ -#else - out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */ - val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */ - out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ +#if defined(UART3_SDR) + MTREG(UART3_SDR, reg); #endif + + out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ + out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8(UART_BASE + UART_LSR); /* clear line status */ + val = in8(UART_BASE + UART_RBR); /* read receive buffer */ + out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */ + return (0); } @@ -564,29 +552,17 @@ int serial_init (void) tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; -#if defined(CONFIG_SERIAL_MULTI) - out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ - out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */ - out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (dev_base + UART_LSR); /* clear line status */ - val = in8 (dev_base + UART_RBR); /* read receive buffer */ - out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */ - out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */ -#else - out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */ - val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */ - out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ -#endif + out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ + out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8(UART_BASE + UART_LSR); /* clear line status */ + val = in8(UART_BASE + UART_RBR); /* read receive buffer */ + out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */ + return (0); } @@ -598,55 +574,10 @@ void serial_setbrg_dev (unsigned long dev_base) void serial_setbrg (void) #endif { - unsigned long tmp; - unsigned long clk; - unsigned long udiv; - unsigned short bdiv; - -#ifdef CFG_EXT_SERIAL_CLOCK - clk = CFG_EXT_SERIAL_CLOCK; -#else - clk = gd->cpu_clk; -#endif - -#ifdef CONFIG_405EP - udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS); -#else - udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1; -#endif /* CONFIG_405EP */ - -#if !defined(CFG_EXT_SERIAL_CLOCK) && \ - ( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ - defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ - defined(CONFIG_440SPE) ) - serial_divs (gd->baudrate, &udiv, &bdiv); - tmp = udiv << CR0_UDIV_POS; /* set the UART divisor */ -#if defined(CONFIG_SERIAL_MULTI) - if (UART0_BASE == dev_base) { - mtsdr (UART0_SDR, tmp); - } else { - mtsdr (UART1_SDR, tmp); - } -#else - mtsdr (UART0_SDR, tmp); -#endif - -#else - - tmp = gd->baudrate * udiv * 16; - bdiv = (clk + tmp / 2) / tmp; -#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */ - #if defined(CONFIG_SERIAL_MULTI) - out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ - out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + serial_init_dev(dev_base); #else - out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + serial_init(); #endif } @@ -667,19 +598,11 @@ void serial_putc (const char c) /* check THRE bit, wait for transmiter available */ for (i = 1; i < 3500; i++) { -#if defined(CONFIG_SERIAL_MULTI) - if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20) -#else - if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20) -#endif + if ((in8 (UART_BASE + UART_LSR) & 0x20) == 0x20) break; udelay (100); } -#if defined(CONFIG_SERIAL_MULTI) - out8 (dev_base + UART_THR, c); /* put character out */ -#else - out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */ -#endif + out8 (UART_BASE + UART_THR, c); /* put character out */ } #if defined(CONFIG_SERIAL_MULTI) @@ -709,11 +632,7 @@ int serial_getc (void) #if defined(CONFIG_HW_WATCHDOG) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ #endif /* CONFIG_HW_WATCHDOG */ -#if defined(CONFIG_SERIAL_MULTI) - status = in8 (dev_base + UART_LSR); -#else - status = in8 (ACTING_UART0_BASE + UART_LSR); -#endif + status = in8 (UART_BASE + UART_LSR); if ((status & asyncLSRDataReady1) != 0x0) { break; } @@ -721,22 +640,14 @@ int serial_getc (void) asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1 )) != 0) { -#if defined(CONFIG_SERIAL_MULTI) - out8 (dev_base + UART_LSR, -#else - out8 (ACTING_UART0_BASE + UART_LSR, -#endif + out8 (UART_BASE + UART_LSR, asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1); } } -#if defined(CONFIG_SERIAL_MULTI) - return (0x000000ff & (int) in8 (dev_base)); -#else - return (0x000000ff & (int) in8 (ACTING_UART0_BASE)); -#endif + return (0x000000ff & (int) in8 (UART_BASE)); } #if defined(CONFIG_SERIAL_MULTI) @@ -747,11 +658,7 @@ int serial_tstc (void) { unsigned char status; -#if defined(CONFIG_SERIAL_MULTI) - status = in8 (dev_base + UART_LSR); -#else - status = in8 (ACTING_UART0_BASE + UART_LSR); -#endif + status = in8 (UART_BASE + UART_LSR); if ((status & asyncLSRDataReady1) != 0x0) { return (1); } @@ -759,11 +666,7 @@ int serial_tstc (void) asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1 )) != 0) { -#if defined(CONFIG_SERIAL_MULTI) - out8 (dev_base + UART_LSR, -#else - out8 (ACTING_UART0_BASE + UART_LSR, -#endif + out8 (UART_BASE + UART_LSR, asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index e552c034733..2d16a83420a 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -199,7 +199,8 @@ ulong get_PCI_freq (void) #elif defined(CONFIG_440) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) void get_sys_info (sys_info_t *sysInfo) { unsigned long temp; diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 60ed2d54536..5a1ab386b18 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -117,12 +117,16 @@ .extern ext_bus_cntlr_init .extern sdram_init +#ifdef CONFIG_NAND_U_BOOT + .extern reconfig_tlb0 +#endif /* * Set up GOT: Global Offset Table * * Use r14 to access the GOT */ +#if !defined(CONFIG_NAND_SPL) START_GOT GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(_FIXUP_TABLE_) @@ -136,6 +140,18 @@ GOT_ENTRY(_end) GOT_ENTRY(__bss_start) END_GOT +#endif /* CONFIG_NAND_SPL */ + +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) + /* + * NAND U-Boot image is started from offset 0 + */ + .text + bl reconfig_tlb0 + GET_GOT + bl cpu_init_f /* run low-level CPU init code (from Flash) */ + bl board_init_f +#endif /* * 440 Startup -- on reset only the top 4k of the effective @@ -150,11 +166,21 @@ */ #if defined(CONFIG_440) +#if !defined(CONFIG_NAND_SPL) .section .bootpg,"ax" +#endif .globl _start_440 /**************************************************************************/ _start_440: + /*--------------------------------------------------------------------+ + | 440EPX BUP Change - Hardware team request + +--------------------------------------------------------------------*/ +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + sync + nop + nop +#endif /*----------------------------------------------------------------+ | Core bug fix. Clear the esr +-----------------------------------------------------------------*/ @@ -171,15 +197,19 @@ _start_440: mtspr srr1,r0 mtspr csrr0,r0 mtspr csrr1,r0 -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* NOTE: 440GX adds machine check status regs */ + /* NOTE: 440GX adds machine check status regs */ +#if defined(CONFIG_440) && !defined(CONFIG_440GP) mtspr mcsrr0,r0 mtspr mcsrr1,r0 - mfspr r1, mcsr + mfspr r1,mcsr mtspr mcsr,r1 #endif /*----------------------------------------------------------------*/ /* Initialize debug */ /*----------------------------------------------------------------*/ + mfspr r1,dbcr0 + andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ + bne skip_debug_init /* if set, don't clear debug register */ mtspr dbcr0,r0 mtspr dbcr1,r0 mtspr dbcr2,r0 @@ -193,6 +223,7 @@ _start_440: mfspr r1,dbsr mtspr dbsr,r1 /* Clear all valid bits */ +skip_debug_init: /*----------------------------------------------------------------*/ /* CCR0 init */ @@ -352,7 +383,53 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ /*----------------------------------------------------------------*/ /* Continue from 'normal' start */ /*----------------------------------------------------------------*/ -2: bl 3f +2: + +#if defined(CONFIG_NAND_SPL) + /* + * Enable internal SRAM + */ + lis r2,0x7fff + ori r2,r2,0xffff + mfdcr r1,isram0_dpc + and r1,r1,r2 /* Disable parity check */ + mtdcr isram0_dpc,r1 + mfdcr r1,isram0_pmeg + and r1,r1,r2 /* Disable pwr mgmt */ + mtdcr isram0_pmeg,r1 + + /* + * Copy SPL from cache into internal SRAM + */ + li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1 + mtctr r4 + lis r2,CFG_NAND_BOOT_SPL_SRC@h + ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l + lis r3,CFG_NAND_BOOT_SPL_DST@h + ori r3,r3,CFG_NAND_BOOT_SPL_DST@l +spl_loop: + lwzu r4,4(r2) + stwu r4,4(r3) + bdnz spl_loop + + /* + * Jump to code in RAM + */ + bl 00f +00: mflr r10 + lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h + ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l + sub r10,r10,r3 + addi r10,r10,28 + mtlr r10 + blr + +start_ram: + sync + isync +#endif + + bl 3f b _start 3: li r0,0 @@ -366,6 +443,7 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ * r3 - 1st arg to board_init(): IMMP pointer * r4 - 2nd arg to board_init(): boot flag */ +#ifndef CONFIG_NAND_SPL .text .long 0x27051956 /* U-Boot Magic Number */ .globl version_string @@ -379,6 +457,7 @@ version_string: * location (0x100) is where the CriticalInput Execption should be. */ . = EXC_OFF_SYS_RESET +#endif .globl _start _start: @@ -417,7 +496,8 @@ _start: /* Setup the internal SRAM */ /*----------------------------------------------------------------*/ li r0,0 -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) + +#ifdef CFG_INIT_RAM_DCACHE /* Clear Dcache to use as RAM */ addis r3,r0,CFG_INIT_RAM_ADDR@h ori r3,r3,CFG_INIT_RAM_ADDR@l @@ -433,19 +513,22 @@ _start: dcbz r0,r3 addi r3,r3,32 bdnz ..d_ag -#else -#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#endif /* CFG_INIT_RAM_DCACHE */ + + /* 440EP & 440GR are only 440er PPC's without internal SRAM */ +#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) + /* not all PPC's have internal SRAM usable as L2-cache */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */ #endif - mtdcr isram0_sb1cr,r0 /* Disable bank 1 */ - li r2,0x7fff + lis r2,0x7fff ori r2,r2,0xffff mfdcr r1,isram0_dpc and r1,r1,r2 /* Disable parity check */ mtdcr isram0_dpc,r1 mfdcr r1,isram0_pmeg - andis. r1,r1,r2 /* Disable pwr mgmt */ + and r1,r1,r2 /* Disable pwr mgmt */ mtdcr isram0_pmeg,r1 lis r1,0x8000 /* BAS = 8000_0000 */ @@ -474,11 +557,12 @@ _start: lis r1, 0x0003 ori r1,r1, 0x0984 /* fourth 64k */ mtdcr isram0_sb3cr,r1 -#else +#elif defined(CONFIG_440GP) ori r1,r1,0x0380 /* 8k rw */ mtdcr isram0_sb0cr,r1 + mtdcr isram0_sb1cr,r0 /* Disable bank 1 */ #endif -#endif +#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */ /*----------------------------------------------------------------*/ /* Setup the stack in internal SRAM */ @@ -495,10 +579,14 @@ _start: stwu r1,-8(r1) /* Save back chain and move SP */ stw r0,+12(r1) /* Save return addr (underflow vect) */ +#ifdef CONFIG_NAND_SPL + bl nand_boot /* will not return */ +#else GET_GOT bl cpu_init_f /* run low-level CPU init code (from Flash) */ bl board_init_f +#endif #endif /* CONFIG_440 */ @@ -808,6 +896,7 @@ _start: /*----------------------------------------------------------------------- */ +#ifndef CONFIG_NAND_SPL /*****************************************************************************/ .globl _start_of_vectors _start_of_vectors: @@ -1013,6 +1102,7 @@ crit_return: lwz r1,GPR1(r1) SYNC rfci +#endif /* CONFIG_NAND_SPL */ /* Cache functions. */ @@ -1254,6 +1344,7 @@ ppcSync: /*------------------------------------------------------------------------------*/ +#ifndef CONFIG_NAND_SPL /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -1267,7 +1358,9 @@ ppcSync: */ .globl relocate_code relocate_code: -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SPE) /* * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) * to speed up the boot process. Now this cache needs to be disabled. @@ -1482,22 +1575,22 @@ trap_init: cmplw 0, r7, r8 blt 4b -#if !defined(CONFIG_440GX) && !defined(CONFIG_440SPE) +#if !defined(CONFIG_440) addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ mtmsr r7 /* change MSR */ #else - bl __440gx_msr_set - b __440gx_msr_continue + bl __440_msr_set + b __440_msr_continue -__440gx_msr_set: +__440_msr_set: addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ mtspr srr1,r7 mflr r7 mtspr srr0,r7 rfi -__440gx_msr_continue: +__440_msr_continue: #endif mtlr r4 /* restore link register */ @@ -1516,6 +1609,7 @@ trap_reloc: stw r0, 4(r7) blr +#endif /* CONFIG_NAND_SPL */ /**************************************************************************/ diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c index bb5765891f8..ab852c525cf 100644 --- a/cpu/ppc4xx/usb_ohci.c +++ b/cpu/ppc4xx/usb_ohci.c @@ -76,7 +76,7 @@ #define m16_swap(x) swap_16(x) #define m32_swap(x) swap_32(x) -#ifdef CONFIG_440EP +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) #define ohci_cpu_to_le16(x) (x) #define ohci_cpu_to_le32(x) (x) #else @@ -1599,7 +1599,11 @@ int usb_lowlevel_init(void) gohci.disabled = 1; gohci.sleeping = 0; gohci.irq = -1; - gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000); +#if defined(CONFIG_440EP) + gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000); +#elif defined(CONFIG_440EPX) + gohci.regs = (struct ohci_regs *)(CFG_USB_HOST); +#endif gohci.flags = 0; gohci.slot_name = "ppc440"; diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c index 8262c54bef1..6140d2a9089 100644 --- a/cpu/ppc4xx/usbdev.c +++ b/cpu/ppc4xx/usbdev.c @@ -3,7 +3,7 @@ #include #include -#ifdef CONFIG_440EP +#if (defined(CONFIG_440EP) || defined(CONFIG_440EPX)) && (CONFIG_COMMANDS & CFG_CMD_USB) #include #include "usbdev.h" @@ -186,6 +186,21 @@ int usbInt(void) return 0; } +#if defined(CONFIG_440EPX) +void usb_dev_init() +{ + printf("USB 2.0 Device init\n"); + + /*usb dev init */ + *(unsigned char *)USB2D0_POWER_8 = 0xa1; /* 2.0 */ + + /*enable interrupts */ + *(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f; + + irq_install_handler(VECNUM_HSB2D, (interrupt_handler_t *) usbInt, + NULL); +} +#else void usb_dev_init() { #ifdef USB_2_0_DEVICE @@ -210,5 +225,6 @@ void usb_dev_init() irq_install_handler(VECNUM_USBDEV, (interrupt_handler_t *) usbInt, NULL); } +#endif -#endif /*CONFIG_440EP */ +#endif /* CONFIG_440EP || CONFIG_440EPX */ diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h index 93cef026a3f..70e436aab23 100644 --- a/cpu/ppc4xx/vecnum.h +++ b/cpu/ppc4xx/vecnum.h @@ -31,7 +31,94 @@ #ifndef _VECNUMS_H_ #define _VECNUMS_H_ -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440EPX) || defined(CONFIG_440_GRX) + +/* UIC 0 */ +#define VECNUM_U0 0 /* UART 0 */ +#define VECNUM_U1 1 /* UART 1 */ +#define VECNUM_IIC0 2 /* IIC */ +#define VECNUM_KRD 3 /* Kasumi Ready for data */ +#define VECNUM_KDA 4 /* Kasumi Data Available */ +#define VECNUM_PCRW 5 /* PCI command register write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_IIC1 7 /* IIC */ +#define VECNUM_SPI 8 /* SPI */ +#define VECNUM_EPCISER 9 /* External PCI SERR */ +#define VECNUM_MTE 10 /* MAL TXEOB */ +#define VECNUM_MRE 11 /* MAL RXEOB */ +#define VECNUM_D0 12 /* DMA channel 0 */ +#define VECNUM_D1 13 /* DMA channel 1 */ +#define VECNUM_D2 14 /* DMA channel 2 */ +#define VECNUM_D3 15 /* DMA channel 3 */ +#define VECNUM_UD0 16 /* UDMA irq 0 */ +#define VECNUM_UD1 17 /* UDMA irq 1 */ +#define VECNUM_UD2 18 /* UDMA irq 2 */ +#define VECNUM_UD3 19 /* UDMA irq 3 */ +#define VECNUM_HSB2D 20 /* USB2.0 Device */ +#define VECNUM_USBDEV 20 /* USB 1.1/USB 2.0 Device */ +#define VECNUM_OHCI1 21 /* USB2.0 Host OHCI irq 1 */ +#define VECNUM_OHCI2 22 /* USB2.0 Host OHCI irq 2 */ +#define VECNUM_EIP94 23 /* Security EIP94 */ +#define VECNUM_ETH0 24 /* Emac 0 */ +#define VECNUM_ETH1 25 /* Emac 1 */ +#define VECNUM_EHCI 26 /* USB2.0 Host EHCI */ +#define VECNUM_EIR4 27 /* External interrupt 4 */ +#define VECNUM_UIC2NC 28 /* UIC2 non-critical interrupt */ +#define VECNUM_UIC2C 29 /* UIC2 critical interrupt */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_MS (32 + 0) /* MAL SERR */ +#define VECNUM_MTDE (32 + 1) /* MAL TXDE */ +#define VECNUM_MRDE (32 + 2) /* MAL RXDE */ +#define VECNUM_U2 (32 + 3) /* UART 2 */ +#define VECNUM_U3 (32 + 4) /* UART 3 */ +#define VECNUM_EBCO (32 + 5) /* EBCO interrupt status */ +#define VECNUM_NDFC (32 + 6) /* NDFC */ +#define VECNUM_KSLE (32 + 7) /* KASUMI slave error */ +#define VECNUM_CT5 (32 + 8) /* GPT compare timer 5 */ +#define VECNUM_CT6 (32 + 9) /* GPT compare timer 6 */ +#define VECNUM_PLB34I0 (32 + 10) /* PLB3X4X MIRQ0 */ +#define VECNUM_PLB34I1 (32 + 11) /* PLB3X4X MIRQ1 */ +#define VECNUM_PLB34I2 (32 + 12) /* PLB3X4X MIRQ2 */ +#define VECNUM_PLB34I3 (32 + 13) /* PLB3X4X MIRQ3 */ +#define VECNUM_PLB34I4 (32 + 14) /* PLB3X4X MIRQ4 */ +#define VECNUM_PLB34I5 (32 + 15) /* PLB3X4X MIRQ5 */ +#define VECNUM_CT0 (32 + 16) /* GPT compare timer 0 */ +#define VECNUM_CT1 (32 + 17) /* GPT compare timer 1 */ +#define VECNUM_EIR7 (32 + 18) /* External interrupt 7 */ +#define VECNUM_EIR8 (32 + 19) /* External interrupt 8 */ +#define VECNUM_EIR9 (32 + 20) /* External interrupt 9 */ +#define VECNUM_CT2 (32 + 21) /* GPT compare timer 2 */ +#define VECNUM_CT3 (32 + 22) /* GPT compare timer 3 */ +#define VECNUM_CT4 (32 + 23) /* GPT compare timer 4 */ +#define VECNUM_SRE (32 + 24) /* Serial ROM error */ +#define VECNUM_GPTDC (32 + 25) /* GPT decrementer pulse */ +#define VECNUM_RSVD0 (32 + 26) /* Reserved */ +#define VECNUM_EPCIPER (32 + 27) /* External PCI PERR */ +#define VECNUM_EIR0 (32 + 28) /* External interrupt 0 */ +#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ +#define VECNUM_EIR1 (32 + 30) /* External interrupt 1 */ +#define VECNUM_EWU1 (32 + 31) /* Ethernet 1 wakeup */ + +#define VECNUM_TXDE VECNUM_MTDE +#define VECNUM_RXDE VECNUM_MRDE + +/* UIC 2 */ +#define VECNUM_EIR5 (62 + 0) /* External interrupt 5 */ +#define VECNUM_EIR6 (62 + 1) /* External interrupt 6 */ +#define VECNUM_OPB (62 + 2) /* OPB to PLB bridge int stat */ +#define VECNUM_EIR2 (62 + 3) /* External interrupt 2 */ +#define VECNUM_EIR3 (62 + 4) /* External interrupt 3 */ +#define VECNUM_DDR2 (62 + 5) /* DDR2 sdram */ +#define VECNUM_MCTX0 (62 + 6) /* MAl intp coalescence TX0 */ +#define VECNUM_MCTX1 (62 + 7) /* MAl intp coalescence TX1 */ +#define VECNUM_MCTR0 (62 + 8) /* MAl intp coalescence TR0 */ +#define VECNUM_MCTR1 (62 + 9) /* MAl intp coalescence TR1 */ + +#elif defined(CONFIG_440SPE) + /* UIC 0 */ #define VECNUM_U0 0 /* UART0 */ #define VECNUM_U1 1 /* UART1 */ diff --git a/doc/README.nand-boot-ppc440 b/doc/README.nand-boot-ppc440 new file mode 100644 index 00000000000..a82a10ee6a5 --- /dev/null +++ b/doc/README.nand-boot-ppc440 @@ -0,0 +1,36 @@ +----------------------------- +NAND boot on PPC440 platforms +----------------------------- + +This document describes the U-Boot NAND boot feature as it +is implemented for the AMCC Sequoia (PPC440EPx) board. + +The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH, +completely without NOR FLASH. This can be done by using the NAND +boot feature of the 440 NAND flash controller (NDFC). + +Here a short desciption of the different boot stages: + +a) IPL (Initial Program Loader, integrated inside CPU) +------------------------------------------------------ +Will load first 4k from NAND (SPL) into cache and execute it from there. + +b) SPL (Secondary Program Loader) +--------------------------------- +Will load special U-Boot version (NUB) from NAND and execute it. This SPL +has to fit into 4kByte. It sets up the CPU and configures the SDRAM +controller and the NAND controller so that the special U-Boot image can be +loaded from NAND to SDRAM. +This special image is build in the directory "nand_spl". + +c) NUB (NAND U-Boot) +-------------------- +This NAND U-Boot (NUB) is a special U-Boot version which can be started +from RAM. Therefore it mustn't (re-)configure the SDRAM controller. + +On 440EPx the SPL is copied to internal SRAM before the NAND controller +is set up. While still running from cache, I experienced problems accessing +the NAND controller. + + +September 07 2006, Stefan Roese diff --git a/dtt/lm75.c b/dtt/lm75.c index 59daa453976..63f3b7551e9 100644 --- a/dtt/lm75.c +++ b/dtt/lm75.c @@ -146,8 +146,13 @@ static int _dtt_init(int sensor) /* * Setup configuraton register */ +#ifdef CONFIG_DTT_AD7414 + /* config = alert active low and disabled */ + val = 0x60; +#else /* config = 6 sample integration, int mode, active low, and enable */ val = 0x18; +#endif if (dtt_write(sensor, DTT_CONFIG, val) != 0) return 1; diff --git a/include/405_mal.h b/include/405_mal.h index 05985869534..2a421848b4b 100644 --- a/include/405_mal.h +++ b/include/405_mal.h @@ -92,7 +92,7 @@ #define MAL_ESR_PBEI 0x00000001 /* ^^ ^^ */ /* Mal IER */ -#ifdef CONFIG_440SPE +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define MAL_IER_PT 0x00000080 #define MAL_IER_PRE 0x00000040 #define MAL_IER_PWE 0x00000020 diff --git a/include/440_i2c.h b/include/440_i2c.h index 9c90a9e3c48..0c2bf362730 100644 --- a/include/440_i2c.h +++ b/include/440_i2c.h @@ -1,7 +1,8 @@ #ifndef _440_i2c_h_ #define _440_i2c_h_ -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700) #else #define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 44b23f1eb4c..bbd3497c50e 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -728,6 +728,10 @@ #define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ #define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ #define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ +#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ +#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ +#define PVR_440GRX1_RA 0x216218D8 /* 440GRX rev A with Security / Kasumi */ +#define PVR_440GRX2_RA 0x216218DC /* 440GRX rev A without Security / Kasumi */ #define PVR_440GX_RA 0x51B21850 #define PVR_440GX_RB 0x51B21851 #define PVR_440GX_RC 0x51B21892 diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index f7aa55f3343..794a6d49747 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -108,7 +108,8 @@ typedef struct bd_info { #endif #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) unsigned int bi_opbfreq; /* OPB clock in Hz */ int bi_iic_fast[2]; /* Use fast i2c mode */ #endif diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index cd4339b5822..4961011b5cd 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -73,6 +73,7 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 50c1c4fd4cb..23bdfc8dfb9 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -63,6 +63,7 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (8 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h new file mode 100644 index 00000000000..d3fcc032aa5 --- /dev/null +++ b/include/configs/sequoia.h @@ -0,0 +1,431 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * sequoia.h - configuration for Sequoia board (PowerPC440EPx) + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_SEQUOIA 1 /* Board is Sequoia */ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +#define CFG_BOOT_BASE_ADDR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ +#define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + +/* Don't change either of these */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ + +#define CFG_USB2D0_BASE 0xe0000100 +#define CFG_USB_DEVICE 0xe0000000 +#define CFG_USB_HOST 0xe0000400 +#define CFG_BCSR_BASE 0xc0000000 + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +#if 0 +/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ +#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ +#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ +#else +#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ +#endif + +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +/* define this if you want console on UART1 */ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +/* + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#if 1 /* test-only */ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#endif +#if 0 +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#endif + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE CFG_NAND_ADDR + +/* + * IPL (Initial Program Loader, integrated inside CPU) + * Will load first 4k from NAND (SPL) into cache and execute it from there. + * + * SPL (Secondary Program Loader) + * Will load special U-Boot version (NUB) from NAND and execute it. This SPL + * has to fit into 4kByte. It sets up the CPU and configures the SDRAM + * controller and the NAND controller so that the special U-Boot image can be + * loaded from NAND to SDRAM. + * + * NUB (NAND U-Boot) + * This NAND U-Boot (NUB) is a special U-Boot version which can be started + * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. + * + * On 440EPx the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from cache, I experienced problems accessing + * the NAND controller. sr - 2006-08-25 + */ +#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ +#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ +#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */ +#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ +#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) + +/* + * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) + */ +#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ + +/* + * Now the NAND chip has to be defined (no autodetection used!) + */ +#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */ +#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ + +#ifdef CFG_ENV_IS_IN_NAND +#define CFG_ENV_SIZE 0x4000 +#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_NAND_U_BOOT_SIZE) +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (256) /* 256MB */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x0 +#endif /* CFG_ENV_IS_IN_EEPROM */ + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=sequoia\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/sequoia/uImage\0" \ + "kernel_addr=FE000000\0" \ + "ramdisk_addr=FE180000\0" \ + "load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \ + "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ + "cp.b 100000 FFFA0000 60000\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_M88E1111_PHY 1 +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 1 + +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/* Comment this out to enable USB 1.1 device */ +#define USB_2_0_DEVICE + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DTT | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NAND | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_USB ) + +#define CONFIG_SUPPORT_VFAT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE +#define CFG_NAND 0xD0000000 +#define CFG_CPLD 0xC0000000 + +/* + * On Sequoia CS0 and CS3 are switched when configuring for NAND booting + */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CFG_NAND_CS 3 /* NAND chip connected to CSx */ +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x03017300 +#define CFG_EBC_PB0CR (CFG_FLASH | 0xba000) + +/* Memory Bank 3 (NAND-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x018003c0 +#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) +#else +#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ +/* Memory Bank 3 (NOR-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x03017300 +#define CFG_EBC_PB3CR (CFG_FLASH | 0xba000) + +/* Memory Bank 0 (NAND-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x018003c0 +#define CFG_EBC_PB0CR (CFG_NAND | 0x1c000) +#endif + +/* Memory Bank 2 (CPLD) initialization */ +#define CFG_EBC_PB2AP 0x24814580 +#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h index cf42b666b00..bcafd8ba8b3 100644 --- a/include/configs/yellowstone.h +++ b/include/configs/yellowstone.h @@ -65,6 +65,7 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (8 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 86a85b8a6d3..3d7b4a2f4bc 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -65,6 +65,7 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (8 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ diff --git a/include/linux/mtd/compat.h b/include/linux/mtd/compat.h index 460cd45c808..fe55087ea93 100644 --- a/include/linux/mtd/compat.h +++ b/include/linux/mtd/compat.h @@ -31,11 +31,13 @@ #define max_t(type,x,y) \ ({ type __x = (x); type __y = (y); __x > __y ? __x: __y; }) +#ifndef BUG #define BUG() do { \ printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \ } while (0) #define BUG_ON(condition) do { if (condition) BUG(); } while(0) +#endif /* BUG */ #define likely(x) __builtin_expect(!!(x), 1) #define unlikely(x) __builtin_expect(!!(x), 0) diff --git a/include/linux/mtd/ndfc.h b/include/linux/mtd/ndfc.h new file mode 100644 index 00000000000..d0558a98262 --- /dev/null +++ b/include/linux/mtd/ndfc.h @@ -0,0 +1,67 @@ +/* + * linux/include/linux/mtd/ndfc.h + * + * Copyright (c) 2006 Thomas Gleixner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Info: + * Contains defines, datastructures for ndfc nand controller + * + */ +#ifndef __LINUX_MTD_NDFC_H +#define __LINUX_MTD_NDFC_H + +/* NDFC Register definitions */ +#define NDFC_CMD 0x00 +#define NDFC_ALE 0x04 +#define NDFC_DATA 0x08 +#define NDFC_ECC 0x10 +#define NDFC_BCFG0 0x30 +#define NDFC_BCFG1 0x34 +#define NDFC_BCFG2 0x38 +#define NDFC_BCFG3 0x3c +#define NDFC_CCR 0x40 +#define NDFC_STAT 0x44 +#define NDFC_HWCTL 0x48 +#define NDFC_REVID 0x50 + +#define NDFC_STAT_IS_READY 0x01000000 + +#define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */ +#define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */ +#define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */ +#define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */ +#define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */ +#define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */ +#define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */ +#define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */ +#define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */ +#define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */ +#define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */ +#define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */ +#define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */ +#define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */ +#define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */ +#define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */ + +#define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */ +#define NDFC_BxCFG_CED 0x40000000 /* nCE Style */ +#define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */ +#define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */ +#define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */ + +#define NDFC_MAX_BANKS 4 + +struct ndfc_controller_settings { + uint32_t ccr_settings; + uint64_t ndfc_erpn; +}; + +struct ndfc_chip_settings { + uint32_t bank_settings; +}; + +#endif diff --git a/include/ppc440.h b/include/ppc440.h index d5a9f66a419..c4a3ed54835 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -82,7 +82,10 @@ #define ivor13 0x19d /* interrupt vector offset register 13 */ #define ivor14 0x19e /* interrupt vector offset register 14 */ #define ivor15 0x19f /* interrupt vector offset register 15 */ -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define mcsrr0 0x23a /* machine check save/restore register 0 */ #define mcsrr1 0x23b /* mahcine check save/restore register 1 */ #define mcsr 0x23c /* machine check status register */ @@ -151,7 +154,18 @@ #define sdr_ecid1 0x0081 #define sdr_ecid2 0x0082 #define sdr_jtag 0x00c0 +#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) #define sdr_ddrdl 0x00e0 +#else +#define sdr_cfg 0x00e0 +#define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/ +#define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */ +#define SDR_CFG_32BITS 0x00000000 /* 32 bits */ +#define SDR_CFG_64BITS 0x01000000 /* 64 bits */ +#define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */ +#define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */ +#define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */ +#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */ #define sdr_ebc 0x0100 #define sdr_uart0 0x0120 /* UART0 Config */ #define sdr_uart1 0x0121 /* UART1 Config */ @@ -180,6 +194,54 @@ #define sdr_plbtr 0x4200 #define sdr_mfr 0x4300 /* SDR0_MFR reg */ +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* test-only!!!! */ +#define DDR0_00 0x00 +#define DDR0_01 0x01 +#define DDR0_02 0x02 +#define DDR0_03 0x03 +#define DDR0_04 0x04 +#define DDR0_05 0x05 +#define DDR0_06 0x06 +#define DDR0_07 0x07 +#define DDR0_08 0x08 +#define DDR0_09 0x09 +#define DDR0_10 0x0A +#define DDR0_11 0x0B +#define DDR0_12 0x0C +#define DDR0_13 0x0D +#define DDR0_14 0x0E +#define DDR0_15 0x0F +#define DDR0_16 0x10 +#define DDR0_17 0x11 +#define DDR0_18 0x12 +#define DDR0_19 0x13 +#define DDR0_20 0x14 +#define DDR0_21 0x15 +#define DDR0_22 0x16 +#define DDR0_23 0x17 +#define DDR0_24 0x18 +#define DDR0_25 0x19 +#define DDR0_26 0x1A +#define DDR0_27 0x1B +#define DDR0_28 0x1C +#define DDR0_29 0x1D +#define DDR0_30 0x1E +#define DDR0_31 0x1F +#define DDR0_32 0x20 +#define DDR0_33 0x21 +#define DDR0_34 0x22 +#define DDR0_35 0x23 +#define DDR0_36 0x24 +#define DDR0_37 0x25 +#define DDR0_38 0x26 +#define DDR0_39 0x27 +#define DDR0_40 0x28 +#define DDR0_41 0x29 +#define DDR0_42 0x2A +#define DDR0_43 0x2B +#define DDR0_44 0x2C +#endif /*CONFIG_440EPX*/ + /*----------------------------------------------------------------------------- | SDRAM Controller +----------------------------------------------------------------------------*/ @@ -787,7 +849,8 @@ #define xbcfg 0x23 /* external bus configuration reg */ #define xbcid 0x24 /* external bus core id reg */ -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* PLB4 to PLB3 Bridge OUT */ #define P4P3_DCR_BASE 0x020 @@ -877,6 +940,7 @@ #define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) #define plb1_bearh (PLB_ARBITER_BASE+ 0x0D) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) /* Pin Function Control Register 1 */ #define SDR0_PFC1 0x4101 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ @@ -918,6 +982,178 @@ #define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ #define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ +/* Miscealleneaous Function Reg. */ +#define SDR0_MFR 0x4300 +#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ +#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 +#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ +#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 +#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ +#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ +#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ +#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ +#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ +#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ +#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ +#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) + +#define SDR0_MFR_ERRATA3_EN0 0x00800000 +#define SDR0_MFR_ERRATA3_EN1 0x00400000 +#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ +#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */ +#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ +#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ +#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ + +#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define SDR_USB2D0CR 0x0320 +#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */ +#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */ +#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */ + +#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */ +#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ +#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ + +#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */ +#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ +#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ + +/* USB2 Host Control Register */ +#define SDR0_USB2H0CR 0x0340 +#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */ +#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */ +#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */ +#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */ + +/* Pin Function Control Register 1 */ +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ +#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ +#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ + +#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */ +#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */ +#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ +#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */ +#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */ +#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */ +#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */ +#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */ + +#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ +#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ +#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ +#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ +#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ +#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ +#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ +#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ +#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ +#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ +#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ +#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ +#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ +#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ +#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ +#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ +#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ +#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ +#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ +#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ +#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ + +#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ +#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ +#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ +#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ + +/* Ethernet PLL Configuration Register */ +#define SDR0_PFC2 0x4102 +#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */ +#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */ +#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */ +#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */ + +#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */ +#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */ + +/* USB2PHY0 Control Register */ +#define SDR0_USB2PHY0CR 0x4103 +#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */ +#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */ +#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */ + +#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */ +#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */ +#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */ + +#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */ +#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */ +#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */ + +#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */ +#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */ +#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */ + +#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */ +#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */ +#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */ + +#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */ +#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */ +#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */ + +#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */ +#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */ +#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */ + +#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */ +#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */ +#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */ + +#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */ +#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */ +#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */ + +#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */ +#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/ +#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/ +#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/ + +/* Miscealleneaous Function Reg. */ +#define SDR0_MFR 0x4300 +#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ +#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 +#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ +#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 +#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ +#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ +#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ +#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ +#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ +#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) + +#define SDR0_MFR_ERRATA3_EN0 0x00800000 +#define SDR0_MFR_ERRATA3_EN1 0x00400000 +#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ +#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */ +#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ +#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ +#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ + +#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ + /* CUST0 Customer Configuration Register0 */ #define SDR0_CUST0 0x4000 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ @@ -1007,27 +1243,18 @@ #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ -/* Miscealleneaous Function Reg. */ -#define SDR0_MFR 0x4300 -#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */ -#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */ -#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ -#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ -#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ -#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ -#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ -#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ -#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ -#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) - -#define SDR0_MFR_ERRATA3_EN0 0x00800000 -#define SDR0_MFR_ERRATA3_EN1 0x00400000 -#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ -#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */ -#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ -#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ -#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ +/*----------------------------------------------------------------------------- + | Internal SRAM + +----------------------------------------------------------------------------*/ +#define ISRAM0_DCR_BASE 0x380 +#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ +#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ +#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ +#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ +#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ +#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ +#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ +#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ #else @@ -1121,7 +1348,7 @@ #define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ #define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define UIC2_DCR_BASE 0xe0 #define uic2sr (UIC0_DCR_BASE+0x0) /* UIC2 status-Read Clear */ #define uic2srs (UIC0_DCR_BASE+0x1) /* UIC2 status-Read Set */ @@ -1423,6 +1650,46 @@ #define UIC_EIR6 0x00000004 /* External interrupt 6 */ #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ + +#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + +#define UIC_U0 0x80000000 /* UART 0 */ +#define UIC_U1 0x40000000 /* UART 1 */ +#define UIC_IIC0 0x20000000 /* IIC */ +#define UIC_KRD 0x10000000 /* Kasumi Ready for data */ +#define UIC_KDA 0x08000000 /* Kasumi Data Available */ +#define UIC_PCRW 0x04000000 /* PCI command register write */ +#define UIC_PPM 0x02000000 /* PCI power management */ +#define UIC_IIC1 0x01000000 /* IIC */ +#define UIC_SPI 0x00800000 /* SPI */ +#define UIC_EPCISER 0x00400000 /* External PCI SERR */ +#define UIC_MTE 0x00200000 /* MAL TXEOB */ +#define UIC_MRE 0x00100000 /* MAL RXEOB */ +#define UIC_D0 0x00080000 /* DMA channel 0 */ +#define UIC_D1 0x00040000 /* DMA channel 1 */ +#define UIC_D2 0x00020000 /* DMA channel 2 */ +#define UIC_D3 0x00010000 /* DMA channel 3 */ +#define UIC_UD0 0x00008000 /* UDMA irq 0 */ +#define UIC_UD1 0x00004000 /* UDMA irq 1 */ +#define UIC_UD2 0x00002000 /* UDMA irq 2 */ +#define UIC_UD3 0x00001000 /* UDMA irq 3 */ +#define UIC_HSB2D 0x00000800 /* USB2.0 Device */ +#define UIC_OHCI1 0x00000400 /* USB2.0 Host OHCI irq 1 */ +#define UIC_OHCI2 0x00000200 /* USB2.0 Host OHCI irq 2 */ +#define UIC_EIP94 0x00000100 /* Security EIP94 */ +#define UIC_ETH0 0x00000080 /* Emac 0 */ +#define UIC_ETH1 0x00000040 /* Emac 1 */ +#define UIC_EHCI 0x00000020 /* USB2.0 Host EHCI */ +#define UIC_EIR4 0x00000010 /* External interrupt 4 */ +#define UIC_UIC2NC 0x00000008 /* UIC2 non-critical interrupt */ +#define UIC_UIC2C 0x00000004 /* UIC2 critical interrupt */ +#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ +#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ + +/* For compatibility with 405 code */ +#define UIC_MAL_TXEOB UIC_MTE +#define UIC_MAL_RXEOB UIC_MRE + #elif !defined(CONFIG_440SPE) #define UIC_U0 0x80000000 /* UART 0 */ #define UIC_U1 0x40000000 /* UART 1 */ @@ -1531,6 +1798,48 @@ #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ #define UIC_ETH1 0x00000002 /* Ethernet 1 */ #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ + +#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + +#define UIC_MS 0x80000000 /* MAL SERR */ +#define UIC_MTDE 0x40000000 /* MAL TXDE */ +#define UIC_MRDE 0x20000000 /* MAL RXDE */ +#define UIC_U2 0x10000000 /* UART 2 */ +#define UIC_U3 0x08000000 /* UART 3 */ +#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ +#define UIC_NDFC 0x02000000 /* NDFC */ +#define UIC_KSLE 0x01000000 /* KASUMI slave error */ +#define UIC_CT5 0x00800000 /* GPT compare timer 5 */ +#define UIC_CT6 0x00400000 /* GPT compare timer 6 */ +#define UIC_PLB34I0 0x00200000 /* PLB3X4X MIRQ0 */ +#define UIC_PLB34I1 0x00100000 /* PLB3X4X MIRQ1 */ +#define UIC_PLB34I2 0x00080000 /* PLB3X4X MIRQ2 */ +#define UIC_PLB34I3 0x00040000 /* PLB3X4X MIRQ3 */ +#define UIC_PLB34I4 0x00020000 /* PLB3X4X MIRQ4 */ +#define UIC_PLB34I5 0x00010000 /* PLB3X4X MIRQ5 */ +#define UIC_CT0 0x00008000 /* GPT compare timer 0 */ +#define UIC_CT1 0x00004000 /* GPT compare timer 1 */ +#define UIC_EIR7 0x00002000 /* External interrupt 7 */ +#define UIC_EIR8 0x00001000 /* External interrupt 8 */ +#define UIC_EIR9 0x00000800 /* External interrupt 9 */ +#define UIC_CT2 0x00000400 /* GPT compare timer 2 */ +#define UIC_CT3 0x00000200 /* GPT compare timer 3 */ +#define UIC_CT4 0x00000100 /* GPT compare timer 4 */ +#define UIC_SRE 0x00000080 /* Serial ROM error */ +#define UIC_GPTDC 0x00000040 /* GPT decrementer pulse */ +#define UIC_RSVD0 0x00000020 /* Reserved */ +#define UIC_EPCIPER 0x00000010 /* External PCI PERR */ +#define UIC_EIR0 0x00000008 /* External interrupt 0 */ +#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ +#define UIC_EIR1 0x00000002 /* External interrupt 1 */ +#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ + +/* For compatibility with 405 code */ +#define UIC_MAL_SERR UIC_MS +#define UIC_MAL_TXDE UIC_MTDE +#define UIC_MAL_RXDE UIC_MRDE +#define UIC_ENET UIC_ETH0 + #elif !defined(CONFIG_440SPE) #define UIC_MS 0x80000000 /* MAL SERR */ #define UIC_MTDE 0x40000000 /* MAL TXDE */ @@ -1608,6 +1917,20 @@ #define UIC_RSVD29 0x00000004 /* Reserved */ #define UIC_RSVD30 0x00000002 /* Reserved */ #define UIC_RSVD31 0x00000001 /* Reserved */ + +#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */ + +#define UIC_EIR5 0x80000000 /* External interrupt 5 */ +#define UIC_EIR6 0x40000000 /* External interrupt 6 */ +#define UIC_OPB 0x20000000 /* OPB to PLB bridge interrupt stat */ +#define UIC_EIR2 0x10000000 /* External interrupt 2 */ +#define UIC_EIR3 0x08000000 /* External interrupt 3 */ +#define UIC_DDR2 0x04000000 /* DDR2 sdram */ +#define UIC_MCTX0 0x02000000 /* MAl intp coalescence TX0 */ +#define UIC_MCTX1 0x01000000 /* MAl intp coalescence TX1 */ +#define UIC_MCTR0 0x00800000 /* MAl intp coalescence TR0 */ +#define UIC_MCTR1 0x00400000 /* MAl intp coalescence TR1 */ + #endif /* CONFIG_440GX */ /*---------------------------------------------------------------------------+ @@ -1623,6 +1946,17 @@ #define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \ UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI) + +#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + +#define UICB0_UIC1CI 0x00000000 /* UIC1 Critical Interrupt */ +#define UICB0_UIC1NCI 0x00000000 /* UIC1 Noncritical Interrupt */ +#define UICB0_UIC2CI 0x00000000 /* UIC2 Critical Interrupt */ +#define UICB0_UIC2NCI 0x00000000 /* UIC2 Noncritical Interrupt */ + +#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \ + UICB0_UIC1CI | UICB0_UIC2NCI) + #endif /* CONFIG_440GX */ /*---------------------------------------------------------------------------+ | Universal interrupt controller interrupts @@ -2262,7 +2596,8 @@ #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13) #define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15) #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21) #define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27) #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ @@ -2390,11 +2725,81 @@ #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ #define SDR0_MFR_ERRATA3_EN0 0x00800000 #define SDR0_MFR_ERRATA3_EN1 0x00400000 +#if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */ #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */ #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ +#endif + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22) +#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07) +#define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29) +#define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07) +#endif + +#define SDR0_MFR_ECS_MASK 0x10000000 +#define SDR0_MFR_ECS_INTERNAL 0x10000000 + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define SDR0_SRST0 0x200 +#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ +#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ +#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ +#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ +#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */ +#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */ +#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ +#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */ +#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */ +#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ +#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ +#define SDR0_SRST0_PCI 0x00100000 /* PCI */ +#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */ +#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */ +#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ +#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */ +#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */ +#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */ +#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */ +#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */ +#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */ +#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */ +#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */ +#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ +#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */ +#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ +#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */ +#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */ +#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */ +#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */ +#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */ + +#define SDR0_SRST1 0x201 +#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */ +#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */ +#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */ +#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0 +#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */ +#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */ +#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */ +#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */ +#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */ +#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */ +#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */ +#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */ +#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */ +#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */ +#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */ +#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */ +#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */ +#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */ +#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */ +#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */ + +#else #define SDR0_SRST_BGO 0x80000000 #define SDR0_SRST_PLB 0x40000000 @@ -2427,10 +2832,15 @@ #define SDR0_SRST_EMAC3 0x00000008 #define SDR0_SRST_RGMII 0x00000001 +#endif + /*-----------------------------------------------------------------------------+ | Clocking +-----------------------------------------------------------------------------*/ -#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) +#if !defined (CONFIG_440GX) && \ + !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ + !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ + !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */ #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */ #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */ @@ -2498,6 +2908,120 @@ #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ #endif /* CONFIG_440GX */ +#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX) +/*--------------------------------------*/ +#define CPR0_PLLC 0x40 +#define CPR0_PLLC_RST_MASK 0x80000000 +#define CPR0_PLLC_RST_PLLLOCKED 0x00000000 +#define CPR0_PLLC_RST_PLLRESET 0x80000000 +#define CPR0_PLLC_ENG_MASK 0x40000000 +#define CPR0_PLLC_ENG_DISABLE 0x00000000 +#define CPR0_PLLC_ENG_ENABLE 0x40000000 +#define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) +#define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01) +#define CPR0_PLLC_SRC_MASK 0x20000000 +#define CPR0_PLLC_SRC_PLLOUTA 0x00000000 +#define CPR0_PLLC_SRC_PLLOUTB 0x20000000 +#define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) +#define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01) +#define CPR0_PLLC_SEL_MASK 0x07000000 +#define CPR0_PLLC_SEL_PLL 0x00000000 +#define CPR0_PLLC_SEL_CPU 0x01000000 +#define CPR0_PLLC_SEL_PER 0x05000000 +#define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) +#define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07) +#define CPR0_PLLC_TUNE_MASK 0x000003FF +#define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) +#define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) +/*--------------------------------------*/ +#define CPR0_PLLD 0x60 +#define CPR0_PLLD_FBDV_MASK 0x1F000000 +#define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1) +#define CPR0_PLLD_FWDVA_MASK 0x000F0000 +#define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16) +#define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1) +#define CPR0_PLLD_FWDVB_MASK 0x00000700 +#define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8) +#define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1) +#define CPR0_PLLD_LFBDV_MASK 0x0000003F +#define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) +#define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) +/*--------------------------------------*/ +#define CPR0_PRIMAD 0x80 +#define CPR0_PRIMAD_PRADV0_MASK 0x07000000 +#define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) +#define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) +/*--------------------------------------*/ +#define CPR0_PRIMBD 0xA0 +#define CPR0_PRIMBD_PRBDV0_MASK 0x07000000 +#define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) +#define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) +/*--------------------------------------*/ +#if 0 +#define CPR0_CPM0_ER 0xB0 /* CPM Enable Register */ +#define CPR0_CPM0_FR 0xB1 /* CPM Force Register */ +#define CPR0_CPM0_SR 0xB2 /* CPM Status Register */ +#define CPR0_CPM0_IIC0 0x80000000 /* Inter-Intergrated Circuit0 */ +#define CPR0_CPM0_IIC1 0x40000000 /* Inter-Intergrated Circuit1 */ +#define CPR0_CPM0_PCI 0x20000000 /* Peripheral Component Interconnect */ +#define CPR0_CPM0_USB1H 0x08000000 /* USB1.1 Host */ +#define CPR0_CPM0_FPU 0x04000000 /* PPC440 FPU */ +#define CPR0_CPM0_CPU 0x02000000 /* PPC440x5 Processor Core */ +#define CPR0_CPM0_DMA 0x01000000 /* Direct Memory Access Controller */ +#define CPR0_CPM0_BGO 0x00800000 /* PLB to OPB Bridge */ +#define CPR0_CPM0_BGI 0x00400000 /* OPB to PLB Bridge */ +#define CPR0_CPM0_EBC 0x00200000 /* External Bus Controller */ +#define CPR0_CPM0_NDFC 0x00100000 /* Nand Flash Controller */ +#define CPR0_CPM0_MADMAL 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */ +#define CPR0_CPM0_DMC 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */ +#define CPR0_CPM0_PLB4 0x00040000 /* PLB4 Arbiter */ +#define CPR0_CPM0_PLB4x3x 0x00020000 /* PLB4 to PLB3 */ +#define CPR0_CPM0_PLB3x4x 0x00010000 /* PLB3 to PLB4 */ +#define CPR0_CPM0_PLB3 0x00008000 /* PLB3 Arbiter */ +#define CPR0_CPM0_PPM 0x00002000 /* PLB Performance Monitor */ +#define CPR0_CPM0_UIC1 0x00001000 /* Universal Interrupt Controller 1 */ +#define CPR0_CPM0_GPIO 0x00000800 /* General Purpose IO */ +#define CPR0_CPM0_GPT 0x00000400 /* General Purpose Timer */ +#define CPR0_CPM0_UART0 0x00000200 /* Universal Asynchronous Rcver/Xmitter 0 */ +#define CPR0_CPM0_UART1 0x00000100 /* Universal Asynchronous Rcver/Xmitter 1 */ +#define CPR0_CPM0_UIC0 0x00000080 /* Universal Interrupt Controller 0 */ +#define CPR0_CPM0_TMRCLK 0x00000040 /* CPU Timer */ +#define CPR0_CPM0_EMC0 0x00000020 /* Ethernet 0 */ +#define CPR0_CPM0_EMC1 0x00000010 /* Ethernet 1 */ +#define CPR0_CPM0_UART2 0x00000008 /* Universal Asynchronous Rcver/Xmitter 2 */ +#define CPR0_CPM0_UART3 0x00000004 /* Universal Asynchronous Rcver/Xmitter 3 */ +#define CPR0_CPM0_USB2D 0x00000002 /* USB2.0 Device */ +#define CPR0_CPM0_USB2H 0x00000001 /* USB2.0 Host */ +#endif +/*--------------------------------------*/ +#define CPR0_OPBD 0xC0 +#define CPR0_OPBD_OPBDV0_MASK 0x03000000 +#define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) +#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) +/*--------------------------------------*/ +#define CPR0_PERD 0xE0 +#define CPR0_PERD_PERDV0_MASK 0x07000000 +#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) +#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) +/*--------------------------------------*/ +#define CPR0_MALD 0x100 +#define CPR0_MALD_MALDV0_MASK 0x03000000 +#define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) +#define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) +/*--------------------------------------*/ +#define CPR0_SPCID 0x120 +#define CPR0_SPCID_SPCIDV0_MASK 0x03000000 +#define CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) +#define CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) +/*--------------------------------------*/ +#define CPR0_ICFG 0x140 +#define CPR0_ICFG_RLI_MASK 0x80000000 +#define CPR0_ICFG_RLI_RESETCPR 0x00000000 +#define CPR0_ICFG_RLI_PRESERVECPR 0x80000000 +#define CPR0_ICFG_ICS_MASK 0x00000007 +#endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */ + /*----------------------------------------------------------------------------- | IIC Register Offsets '----------------------------------------------------------------------------*/ @@ -2539,7 +3063,8 @@ #define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000) #define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* PCI Local Configuration Registers --------------------------------- */ @@ -2625,6 +3150,33 @@ #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */ +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + +/* USB2.0 Device */ +#define USB2D0_BASE CFG_USB2D0_BASE + +#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) + +#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */ +#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */ +#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */ +#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */ +#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */ +#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */ +#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */ +#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */ +#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */ +#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */ +#define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */ +#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */ +#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */ +#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */ +#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */ +#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */ +#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */ +#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */ +#endif + /****************************************************************************** * GPIO macro register defines ******************************************************************************/ @@ -2640,7 +3192,8 @@ #define GPIO0_IR (GPIO0_BASE+0x1C) #endif /* CONFIG_440GP */ -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00) #define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00) diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index ec2e3629bb8..43c5ca451e0 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -145,12 +145,14 @@ typedef struct emac_4xx_hw_st { #define EMAC_STACR_OC_MASK (0x00000000) #endif -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define SDR0_PFC1_EM_1000 (0x00200000) #endif /*ZMII Bridge Register addresses */ -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) #else #define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780) @@ -163,6 +165,7 @@ typedef struct emac_4xx_hw_st { #define ZMII_MDI0 0x80000000 /* ZMII FER Register Bit Definitions */ +#define ZMII_FER_DIS (0x0) #define ZMII_FER_MDI (0x8) #define ZMII_FER_SMII (0x4) #define ZMII_FER_RMII (0x2) @@ -197,7 +200,11 @@ typedef struct emac_4xx_hw_st { #define ZMII_SMIISR_V(__x) ((3 - __x) * 8) /* RGMII Register Addresses */ +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000) +#else #define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790) +#endif #define RGMII_FER (RGMII_BASE + 0x00) #define RGMII_SSR (RGMII_BASE + 0x04) @@ -216,7 +223,11 @@ typedef struct emac_4xx_hw_st { #define RGMII_SSR_SP_100MBPS (0x02) #define RGMII_SSR_SP_1000MBPS (0x04) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define RGMII_SSR_V(__x) ((__x) * 8) +#else #define RGMII_SSR_V(__x) ((__x -2) * 8) +#endif /*---------------------------------------------------------------------------+ @@ -286,7 +297,8 @@ typedef struct emac_4xx_hw_st { /* Ethernet MAC Regsiter Addresses */ #if defined(CONFIG_440) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00) #else #define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) @@ -332,7 +344,9 @@ typedef struct emac_4xx_hw_st { #define EMAC_M0_WKE (0x04000000) /* on 440GX EMAC_MR1 has a different layout! */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* MODE Reg 1 */ #define EMAC_M1_FDE (0x80000000) #define EMAC_M1_ILE (0x40000000) diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 72d690ef0f8..3e47e82abad 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -312,7 +312,7 @@ label: \ lwz r3,GOT(transfer_to_handler); \ mtlr r3; \ addi r3,r1,STACK_FRAME_OVERHEAD; \ - li r20,MSR_KERNEL; \ + li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \ rlwimi r20,r23,0,25,25; \ blrl ; \ .L_ ## label : \ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index db80f775603..cf0e3fdf4b6 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -763,6 +763,12 @@ void board_init_r (gd_t *id, ulong dest_addr) spi_init_r (); #endif +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + WATCHDOG_RESET (); + puts ("NAND: "); + nand_init(); /* go init the NAND */ +#endif + /* relocate environment function pointers etc. */ env_relocate (); @@ -959,12 +965,6 @@ void board_init_r (gd_t *id, ulong dest_addr) doc_init (); #endif -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - WATCHDOG_RESET (); - puts ("NAND: "); - nand_init(); /* go init the NAND */ -#endif - #if (CONFIG_COMMANDS & CFG_CMD_NET) #if defined(CONFIG_NET_MULTI) WATCHDOG_RESET (); diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile new file mode 100644 index 00000000000..6c07e3dd8df --- /dev/null +++ b/nand_spl/board/amcc/sequoia/Makefile @@ -0,0 +1,83 @@ +# +# (C) Copyright 2006 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +include board/$(BOARDDIR)/config.mk + +LDSCRIPT= board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o init.o resetvec.o +COBJS = nand_boot.o ndfc.o sdram.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +ALL = u-boot-spl u-boot-spl.bin u-boot-spl-4k.bin + +all: $(obj).depend $(ALL) + +u-boot-spl-4k.bin: u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +u-boot-spl.bin: u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +u-boot-spl: $(OBJS) + $(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \ + -Map u-boot-spl.map -o u-boot-spl + +# create symbolic links for common files + +# from cpu directory +ndfc.c: + @rm -f ndfc.c + ln -s ../cpu/ppc4xx/ndfc.c ndfc.c + +resetvec.S: + @rm -f resetvec.S + ln -s ../cpu/ppc4xx/resetvec.S resetvec.S + +start.S: + @rm -f start.S + ln -s ../cpu/ppc4xx/start.S start.S + +# from board directory +init.S: + @rm -f init.S + ln -s ../board/amcc/sequoia/init.S init.S + +sdram.c: + @rm -f sdram.c + ln -s ../board/amcc/sequoia/sdram.c sdram.c + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/amcc/sequoia/config.mk b/nand_spl/board/amcc/sequoia/config.mk new file mode 100644 index 00000000000..a29ba5fd0dc --- /dev/null +++ b/nand_spl/board/amcc/sequoia/config.mk @@ -0,0 +1,49 @@ +# +# (C) Copyright 2006 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# AMCC 440EPx Reference Platform (Sequoia) board +# + +# +# TEXT_BASE for SPL: +# +# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff, +# in the last 4kBytes of memory space in cache. +# We will copy this SPL into internal SRAM in start.S. So we set +# TEXT_BASE to starting address in internal SRAM here. +# +TEXT_BASE = 0xE0013000 + +# PAD_TO used to generate a 16kByte binary needed for the combined image +# -> PAD_TO = TEXT_BASE + 0x4000 +PAD_TO = 0xE0017000 + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/nand_spl/board/amcc/sequoia/u-boot.lds b/nand_spl/board/amcc/sequoia/u-boot.lds new file mode 100644 index 00000000000..156368911a2 --- /dev/null +++ b/nand_spl/board/amcc/sequoia/u-boot.lds @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc:common) +SECTIONS +{ + .resetvec 0xE0013FFC : + { + *(.resetvec) + } = 0xffff + + .text : + { + start.o (.text) + init.o (.text) + nand_boot.o (.text) + sdram.o (.text) + ndfc.o (.text) + + *(.text) + *(.fixup) + } + _etext = .; + + .data : + { + *(.rodata*) + *(.data*) + *(.sdata*) + __got2_start = .; + *(.got2) + __got2_end = .; + } + + _edata = .; + + __bss_start = .; + .bss : + { + *(.sbss) + *(.bss) + } + + _end = . ; +} diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c new file mode 100644 index 00000000000..6e3af13939f --- /dev/null +++ b/nand_spl/nand_boot.c @@ -0,0 +1,178 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define CFG_NAND_READ_DELAY \ + { volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; } + +extern void board_nand_init(struct nand_chip *nand); +extern void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd); +extern void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte); +extern u_char ndfc_read_byte(struct mtd_info *mtdinfo); +extern int ndfc_dev_ready(struct mtd_info *mtdinfo); +extern int jump_to_ram(ulong delta); +extern int jump_to_uboot(ulong addr); + +static int nand_is_bad_block(struct mtd_info *mtd, int block) +{ + struct nand_chip *this = mtd->priv; + int page_addr = block * CFG_NAND_PAGE_COUNT; + + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_READOOB); + /* Set ALE and clear CLE to start address cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + this->hwcontrol(mtd, NAND_CTL_SETALE); + /* Column address */ + this->write_byte(mtd, CFG_NAND_BAD_BLOCK_POS); /* A[7:0] */ + this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */ + this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */ +#ifdef CFG_NAND_4_ADDR_CYCLE + /* One more address cycle for devices > 32MiB */ + this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:25] */ +#endif + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + + /* + * Wait a while for the data to be ready + */ + if (this->dev_ready) + this->dev_ready(mtd); + else + CFG_NAND_READ_DELAY; + + /* + * Read on byte + */ + if (this->read_byte(mtd) != 0xff) + return 1; + + return 0; +} + +static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst) +{ + struct nand_chip *this = mtd->priv; + int page_addr = page + block * CFG_NAND_PAGE_COUNT; + int i; + + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_READ0); + /* Set ALE and clear CLE to start address cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + this->hwcontrol(mtd, NAND_CTL_SETALE); + /* Column address */ + this->write_byte(mtd, 0); /* A[7:0] */ + this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */ + this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */ +#ifdef CFG_NAND_4_ADDR_CYCLE + /* One more address cycle for devices > 32MiB */ + this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:25] */ +#endif + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + + /* + * Wait a while for the data to be ready + */ + if (this->dev_ready) + this->dev_ready(mtd); + else + CFG_NAND_READ_DELAY; + + /* + * Read page into buffer + */ + for (i=0; iread_byte(mtd); + + return 0; +} + +static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst) +{ + int block; + int blockcopy_count; + int page; + + /* + * offs has to be aligned to a block address! + */ + block = offs / CFG_NAND_BLOCK_SIZE; + blockcopy_count = 0; + + while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) { + if (!nand_is_bad_block(mtd, block)) { + /* + * Skip bad blocks + */ + for (page = 0; page < CFG_NAND_PAGE_COUNT; page++) { + nand_read_page(mtd, block, page, dst); + dst += CFG_NAND_PAGE_SIZE; + } + + blockcopy_count++; + } + + block++; + } + + return 0; +} + +void nand_boot(void) +{ + ulong mem_size; + struct nand_chip nand_chip; + nand_info_t nand_info; + int ret; + void (*uboot)(void); + + /* + * Init sdram, so we have access to memory + */ + mem_size = initdram(0); + + /* + * Init board specific nand support + */ + nand_info.priv = &nand_chip; + nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CFG_NAND_BASE; + nand_chip.dev_ready = NULL; /* preset to NULL */ + board_nand_init(&nand_chip); + + /* + * Load U-Boot image from NAND into RAM + */ + ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, + CFG_NAND_U_BOOT_SIZE, + (uchar *)CFG_NAND_U_BOOT_DST); + + /* + * Jump to U-Boot image + */ + uboot = (void (*)(void))CFG_NAND_U_BOOT_START; + (*uboot)(); +} -- cgit v1.3.1 From 8cacfb85a89f9136d685697eb2c97dae5bddfe8d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 7 Sep 2006 12:23:02 +0200 Subject: Change Yellowstone to use CFI write buffer Patch by Stefan Roese, 07 Aug 2006 --- CHANGELOG | 3 +++ include/configs/yellowstone.h | 2 ++ 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 576cd7fb861..f71c864228a 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Change Yellowstone to use CFI write buffer + Patch by Stefan Roese, 07 Aug 2006 + * Add support for AMCC Sequoia PPC440EPx eval board - Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h index bcafd8ba8b3..ba27f37f6eb 100644 --- a/include/configs/yellowstone.h +++ b/include/configs/yellowstone.h @@ -110,6 +110,8 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ + #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #ifdef CFG_ENV_IS_IN_FLASH -- cgit v1.3.1 From efa20585b3ccfdde431c19c6a9d9d8dae46fe5bb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 7 Sep 2006 12:48:49 +0200 Subject: Fix build problem with CPCI440 Patch by Stefan Roese, 07 Sep 2006 --- CHANGELOG | 5 ++++- include/configs/CPCI440.h | 3 ++- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index f71c864228a..27d9226fde9 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,8 +2,11 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix build problem with CPCI440 + Patch by Stefan Roese, 07 Sep 2006 + * Change Yellowstone to use CFI write buffer - Patch by Stefan Roese, 07 Aug 2006 + Patch by Stefan Roese, 07 Sep 2006 * Add support for AMCC Sequoia PPC440EPx eval board - Add support for PPC440EPx & PPC440GRx diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h index a5bc773e177..90d3a8d8fa3 100644 --- a/include/configs/CPCI440.h +++ b/include/configs/CPCI440.h @@ -31,7 +31,8 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_EBONY 1 /* Board is ebony */ +#define CONFIG_CPCI440 1 /* Board is ebony */ +#define CONFIG_440GP 1 /* Specifc GP support */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #undef CFG_DRAM_TEST /* Disable-takes long time! */ -- cgit v1.3.1 From d12ae80889568365ecb9e6698322f9771ae76dde Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 12 Sep 2006 20:19:10 +0200 Subject: Add NAND environment support for PPC440EPx Sequoia NAND boot config Patch by Stefan Roese, 12 Sep 2006 --- CHANGELOG | 3 +++ board/amcc/sequoia/u-boot-nand.lds | 8 +++++- common/env_nand.c | 50 +++++++++++++++++++++++++++++++++++++- common/environment.c | 3 ++- include/configs/sequoia.h | 27 ++++++-------------- include/environment.h | 4 +++ nand_spl/nand_boot.c | 3 +-- 7 files changed, 73 insertions(+), 25 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index a6dc7623483..9840863bf7e 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add NAND environment support for PPC440EPx Sequoia NAND boot config + Patch by Stefan Roese, 12 Sep 2006 + * Update NAND boot documentation Patch by Stefan Roese, 12 Sep 2006 diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds index c3d3d968fed..cf2e2b55812 100644 --- a/board/amcc/sequoia/u-boot-nand.lds +++ b/board/amcc/sequoia/u-boot-nand.lds @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -56,6 +56,12 @@ SECTIONS cpu/ppc4xx/start.o (.text) + /* Align to next NAND block */ + . = ALIGN(0x4000); + common/environment.o (.ppcenv) + /* Keep some space here for redundant env and potential bad env blocks */ + . = ALIGN(0x10000); + *(.text) *(.fixup) *(.got1) diff --git a/common/env_nand.c b/common/env_nand.c index 0a05b09a7a8..67c4a4e0117 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -2,7 +2,7 @@ * (C) Copyright 2004 * Jian Zhang, Texas Instruments, jzhang@ti.com. - * (C) Copyright 2000-2004 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH @@ -76,7 +76,9 @@ env_t *env_ptr = 0; /* local functions */ +#if !defined(ENV_IS_EMBEDDED) static void use_default(void); +#endif DECLARE_GLOBAL_DATA_PTR; @@ -91,11 +93,55 @@ uchar env_get_char_spec (int index) * Mark it OK for now. env_relocate() in env_common.c * will call our relocate function which will does * the real validation. + * + * When using a NAND boot image (like sequoia_nand), the environment + * can be embedded or attached to the U-Boot image in NAND flash. This way + * the SPL loads not only the U-Boot image from NAND but also the + * environment. */ int env_init(void) { +#if defined(ENV_IS_EMBEDDED) + ulong total; + int crc1_ok = 0, crc2_ok = 0; + env_t *tmp_env1, *tmp_env2; + + total = CFG_ENV_SIZE; + + tmp_env1 = env_ptr; + tmp_env2 = (env_t *)((ulong)env_ptr + CFG_ENV_SIZE); + + crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc); + crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc); + + if (!crc1_ok && !crc2_ok) + gd->env_valid = 0; + else if(crc1_ok && !crc2_ok) + gd->env_valid = 1; + else if(!crc1_ok && crc2_ok) + gd->env_valid = 2; + else { + /* both ok - check serial */ + if(tmp_env1->flags == 255 && tmp_env2->flags == 0) + gd->env_valid = 2; + else if(tmp_env2->flags == 255 && tmp_env1->flags == 0) + gd->env_valid = 1; + else if(tmp_env1->flags > tmp_env2->flags) + gd->env_valid = 1; + else if(tmp_env2->flags > tmp_env1->flags) + gd->env_valid = 2; + else /* flags are equal - almost impossible */ + gd->env_valid = 1; + } + + if (gd->env_valid == 1) + env_ptr = tmp_env1; + else if (gd->env_valid == 2) + env_ptr = tmp_env2; +#else /* ENV_IS_EMBEDDED */ gd->env_addr = (ulong)&default_environment[0]; gd->env_valid = 1; +#endif /* ENV_IS_EMBEDDED */ return (0); } @@ -236,6 +282,7 @@ void env_relocate_spec (void) } #endif /* CFG_ENV_OFFSET_REDUND */ +#if !defined(ENV_IS_EMBEDDED) static void use_default() { puts ("*** Warning - bad CRC or NAND, using default environment\n\n"); @@ -253,5 +300,6 @@ static void use_default() gd->env_valid = 1; } +#endif #endif /* CFG_ENV_IS_IN_NAND */ diff --git a/common/environment.c b/common/environment.c index 81471ce71cd..19bdeb0f62a 100644 --- a/common/environment.c +++ b/common/environment.c @@ -60,7 +60,8 @@ defined(CONFIG_RRVISION) || \ defined(CONFIG_TRAB) || \ defined(CONFIG_PPCHAMELEONEVB) || \ - defined(CONFIG_M5271EVB)) && \ + defined(CONFIG_M5271EVB) || \ + defined(CONFIG_NAND_U_BOOT)) && \ defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */ /* XXX - This only works with GNU C */ # define __PPCENV__ __attribute__ ((section(".ppcenv"))) diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index d3fcc032aa5..639765d5990 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -69,14 +69,9 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer *----------------------------------------------------------------------*/ -#if 0 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ -#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ -#else #define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ -#endif #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ @@ -98,18 +93,11 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -/* - * Define here the location of the environment variables (FLASH or EEPROM). - * Note: DENX encourages to use redundant environment in FLASH. - */ -#if 1 /* test-only */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #else #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ #endif -#if 0 -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#endif /*----------------------------------------------------------------------- * FLASH related @@ -189,8 +177,12 @@ #undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ #ifdef CFG_ENV_IS_IN_NAND -#define CFG_ENV_SIZE 0x4000 -#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_NAND_U_BOOT_SIZE) +/* + * For NAND booting the environment is embedded in the U-Boot image. Please take + * look at the file board/amcc/sequoia/u-boot-nand.lds for details. + */ +#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE +#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) #endif @@ -214,11 +206,6 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 3 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ -#define CFG_ENV_OFFSET 0x0 -#endif /* CFG_ENV_IS_IN_EEPROM */ - /* I2C SYSMON (LM75, AD7414 is almost compatible) */ #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ #define CONFIG_DTT_AD7414 1 /* use AD7414 */ diff --git a/include/environment.h b/include/environment.h index 422f800897f..26b07120da1 100644 --- a/include/environment.h +++ b/include/environment.h @@ -79,6 +79,10 @@ # ifdef CFG_ENV_OFFSET_REDUND # define CFG_REDUNDAND_ENVIRONMENT # endif +# if defined(CONFIG_NAND_U_BOOT) +/* Use embedded environment in NAND boot versions */ +# define ENV_IS_EMBEDDED 1 +# endif #endif /* CFG_ENV_IS_IN_NAND */ diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c index 6e3af13939f..21abb09e39b 100644 --- a/nand_spl/nand_boot.c +++ b/nand_spl/nand_boot.c @@ -166,8 +166,7 @@ void nand_boot(void) /* * Load U-Boot image from NAND into RAM */ - ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, - CFG_NAND_U_BOOT_SIZE, + ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE, (uchar *)CFG_NAND_U_BOOT_DST); /* -- cgit v1.3.1 From 854bc8da75709f13dab4cfa6e9094c0cb49b5c5a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 13 Sep 2006 13:51:58 +0200 Subject: Add support for AMCC Rainier PPX440GRx eval board Patch by Stefan Roese, 13 Sep 2006 --- CHANGELOG | 3 +++ Makefile | 15 +++++++++++++++ board/amcc/sequoia/sequoia.c | 8 ++++++++ cpu/ppc4xx/4xx_enet.c | 2 +- cpu/ppc4xx/vecnum.h | 2 +- include/configs/sequoia.h | 13 ++++++++++++- 6 files changed, 40 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index a896e253a96..0f4b4d561e9 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -7,6 +7,9 @@ Changes since U-Boot 1.1.4: * Cleanup examples binaries +* Add support for AMCC Rainier PPX440GRx eval board + Patch by Stefan Roese, 13 Sep 2006 + * Add NAND environment support for PPC440EPx Sequoia NAND boot config Patch by Stefan Roese, 12 Sep 2006 diff --git a/Makefile b/Makefile index ccf7f9f88fc..f48ca6cebb5 100644 --- a/Makefile +++ b/Makefile @@ -1142,6 +1142,21 @@ PPChameleonEVB_HI_33_config: unconfig } @$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave +rainier_config: unconfig + @echo "#define CONFIG_RAINIER" > include/config.h + @echo "Configuring for rainier board as subset of sequoia..." + @$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc + +rainier_nand_config: unconfig + @echo "#define CONFIG_RAINIER" > include/config.h + @echo "Configuring for rainier board as subset of sequoia..." + @ln -s board/amcc/sequoia/Makefile nand_spl/Makefile + @echo "#define CONFIG_NAND_U_BOOT" >> include/config.h + @echo "Compile NAND boot image for sequoia" + @$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc + @echo "TEXT_BASE = 0x01000000" >board/amcc/sequoia/config.tmp + @echo "CONFIG_NAND_U_BOOT = y" >> include/config.mk + sbc405_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405 diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 95734b9c57c..a8ba2c08319 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -140,10 +140,12 @@ int misc_init_r(void) { uint pbcr; int size_val = 0; +#ifdef CONFIG_440EPX unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; char *act = getenv("usbact"); +#endif /* * FLASH stuff... @@ -211,6 +213,7 @@ int misc_init_r(void) /* * USB suff... */ +#ifdef CONFIG_440EPX if (act == NULL || strcmp(act, "hostdev") == 0) { /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); @@ -322,6 +325,7 @@ int misc_init_r(void) printf("USB: Device(int phy)\n"); } +#endif /* CONFIG_440EPX */ return 0; } @@ -330,7 +334,11 @@ int checkboard(void) { char *s = getenv("serial#"); +#ifdef CONFIG_440EPX printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); +#else + printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); +#endif if (s != NULL) { puts(", serial# "); puts(s); diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 5b1c17c351a..81d49ffdfeb 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -133,7 +133,7 @@ #define BI_PHYMODE_GMII 3 #define BI_PHYMODE_RTBI 4 #define BI_PHYMODE_TBI 5 -#if defined (CONFIG_440EPX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define BI_PHYMODE_SMII 6 #define BI_PHYMODE_MII 7 #endif diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h index 70e436aab23..685d48bcf64 100644 --- a/cpu/ppc4xx/vecnum.h +++ b/cpu/ppc4xx/vecnum.h @@ -31,7 +31,7 @@ #ifndef _VECNUMS_H_ #define _VECNUMS_H_ -#if defined(CONFIG_440EPX) || defined(CONFIG_440_GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC 0 */ #define VECNUM_U0 0 /* UART 0 */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 639765d5990..f67fd9163d0 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -31,8 +31,13 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ +/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ +#ifndef CONFIG_RAINIER #define CONFIG_SEQUOIA 1 /* Board is Sequoia */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#else +#define CONFIG_440GRX 1 /* Specific PPC440GRx */ +#endif #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ @@ -272,12 +277,18 @@ #define CONFIG_PHY1_ADDR 1 /* USB */ +#ifdef CONFIG_440EPX #define CONFIG_USB_OHCI #define CONFIG_USB_STORAGE /* Comment this out to enable USB 1.1 device */ #define USB_2_0_DEVICE +#define CMD_USB CFG_CMD_USB +#else +#define CMD_USB 0 /* no USB on 440GRx */ +#endif /* CONFIG_440EPX */ + /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -301,7 +312,7 @@ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ CFG_CMD_SDRAM | \ - CFG_CMD_USB ) + CMD_USB) #define CONFIG_SUPPORT_VFAT -- cgit v1.3.1 From d14ba6a798beb753e7a864500414fcc2d198b8bc Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 14 Sep 2006 08:40:36 -0500 Subject: Handle 86xx SVR values according to the new Reference Manual. Both 8641 and 8641D have SVR == 0x8090, and are distinguished by the byte in bits 16-23 instead. Thanks to Jason Jin for noticing. Signed-off-by: Jon Loeliger --- cpu/mpc86xx/cpu.c | 9 +++++---- include/asm-ppc/processor.h | 5 +++-- 2 files changed, 8 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index ddd0ad3b39c..551b243076f 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -76,11 +76,12 @@ checkcpu(void) puts(" System: "); switch (ver) { case SVR_8641: - puts("8641"); - break; - case SVR_8641D: + if (SVR_SUBVER(svr) == 1) { puts("8641D"); - break; + } else { + puts("8641"); + } + break; default: puts("Unknown"); break; diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 0060cd030b0..553ef3d9459 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -802,6 +802,8 @@ #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ +#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ + #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ @@ -819,9 +821,8 @@ #define SVR_8541 0x807A #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 - #define SVR_8641 0x8090 -#define SVR_8641D 0x8091 + /* I am just adding a single entry for 8260 boards. I think we may be * able to combine mbx, fads, rpxlite, bseip, and classic into a single -- cgit v1.3.1 From 09f3e09e9ebcfa7919ca8931a4b5504fadd1f1d3 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 13 Sep 2006 10:34:18 -0500 Subject: Add support for eTSEC 3 & 4 on 8548 CDS * Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS. This will only work on rev 1.3 boards (but doesn't break older boards) * Cleaned up some comments to reflect the expanded role of tsec in other systems --- board/cds/mpc8548cds/mpc8548cds.c | 32 ++++++++++++++++++ drivers/tsec.c | 69 +++++++++++++++++++++++++++++++++------ drivers/tsec.h | 17 ++++++++++ include/configs/MPC8548CDS.h | 4 ++- 4 files changed, 111 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 6eedb4a2095..66219e395b1 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "../common/cadmus.h" #include "../common/eeprom.h" @@ -327,3 +328,34 @@ pci_init_board(void) pci_mpc85xx_init(&hose); #endif } + +int last_stage_init(void) +{ + unsigned int temp; + + /* Change the resistors for the PHY */ + /* This is needed to get the RGMII working for the 1.3+ + * CDS cards */ + if (get_board_version() == 0x13) { + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 29, 18); + + miiphy_read(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, &temp); + + temp = (temp & 0xf03f); + temp |= 2 << 9; /* 36 ohm */ + temp |= 2 << 6; /* 39 ohm */ + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, temp); + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 29, 3); + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, 0x8000); + } + + return 0; +} diff --git a/drivers/tsec.c b/drivers/tsec.c index 7ec565ca67b..bfc49c46297 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -44,9 +44,7 @@ struct tsec_info_struct { /* The tsec_info structure contains 3 values which the * driver uses to determine how to operate a given ethernet - * device. For now, the structure is initialized with the - * knowledge that all current implementations have 2 TSEC - * devices, and one FEC. The information needed is: + * device. The information needed is: * phyaddr - The address of the PHY which is attached to * the given device. * @@ -56,18 +54,16 @@ struct tsec_info_struct { * * phyregidx - This variable specifies which ethernet device * controls the MII Management registers which are connected - * to the PHY. For 8540/8560, only TSEC1 (index 0) has + * to the PHY. For now, only TSEC1 (index 0) has * access to the PHYs, so all of the entries have "0". * * The values specified in the table are taken from the board's * config file in include/configs/. When implementing a new * board with ethernet capability, it is necessary to define: - * TSEC1_PHY_ADDR - * TSEC1_PHYIDX - * TSEC2_PHY_ADDR - * TSEC2_PHYIDX + * TSECn_PHY_ADDR + * TSECn_PHYIDX * - * and for 8560: + * for n = 1,2,3, etc. And for FEC: * FEC_PHY_ADDR * FEC_PHYIDX */ @@ -91,7 +87,7 @@ static struct tsec_info_struct tsec_info[] = { { 0, 0, 0}, # endif # if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) - {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX}, + {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, # else { 0, 0, 0}, # endif @@ -805,6 +801,58 @@ struct phy_info phy_info_M88E1111S = { }, }; +static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) +{ + unsigned int temp; + uint mii_data = read_phy_reg(priv, mii_reg); + + + /* Setting MIIM_88E1145_PHY_EXT_CR */ + if (priv->flags & TSEC_REDUCED) + return mii_data | + MIIM_M88E1145_RGMII_RX_DELAY | + MIIM_M88E1145_RGMII_TX_DELAY; + else + return mii_data; +} + +static struct phy_info phy_info_M88E1145 = { + 0x01410cd, + "Marvell 88E1145", + 4, + (struct phy_cmd[]) { /* config */ + /* Errata E0, E1 */ + {29, 0x001b, NULL}, + {30, 0x418f, NULL}, + {29, 0x0016, NULL}, + {30, 0xa2da, NULL}, + + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL}, + {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL}, + /* Read the Status */ + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + + struct phy_info phy_info_cis8204 = { 0x3f11, "Cicada Cis8204", @@ -999,6 +1047,7 @@ struct phy_info *phy_info[] = { &phy_info_cis8204, &phy_info_M88E1011S, &phy_info_M88E1111S, + &phy_info_M88E1145, &phy_info_dm9161, &phy_info_lxt971, &phy_info_dp83865, diff --git a/drivers/tsec.h b/drivers/tsec.h index b55b2992b22..0bfca3a3df9 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -142,6 +142,23 @@ #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 #define MIIM_88E1011_PHYSTAT_LINK 0x0400 +#define MIIM_88E1011_PHY_SCR 0x10 +#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 + +/* 88E1111 PHY LED Control Register */ +#define MIIM_88E1111_PHY_LED_CONTROL 24 +#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 +#define MIIM_88E1111_PHY_LED_COMBINE 0x411C + +/* 88E1145 Extended PHY Specific Control Register */ +#define MIIM_88E1145_PHY_EXT_CR 20 +#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 +#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 + +#define MIIM_88E1145_PHY_PAGE 29 +#define MIIM_88E1145_PHY_CAL_OV 30 + + /* DM9161 Control register values */ #define MIIM_DM9161_CR_STOP 0x0400 #define MIIM_DM9161_CR_RSTAN 0x1200 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 37b518cca50..767ab337b38 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -381,7 +381,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#undef CONFIG_MPC85XX_TSEC4 +#define CONFIG_MPC85XX_TSEC4 1 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC @@ -483,6 +483,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.1.253 -- cgit v1.3.1 From 8272dc2f58f2473d8995fcc9b916440cfba080f0 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 13 Sep 2006 10:33:35 -0500 Subject: Updated config headers to add default FDT-based booting --- include/configs/MPC8540ADS.h | 10 +++++++--- include/configs/MPC8541CDS.h | 9 ++++++--- include/configs/MPC8548CDS.h | 13 ++++++++----- include/configs/MPC8555CDS.h | 9 ++++++--- 4 files changed, 27 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 8e4d2c95a44..31ffbaf15b4 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -517,8 +517,10 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -526,13 +528,15 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index f73caf0319c..2b87f1bd6a9 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -489,8 +489,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -498,7 +500,8 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 767ab337b38..03ab976d118 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -389,13 +389,11 @@ extern unsigned long get_clock_freq(void); #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 #define TSEC4_PHY_ADDR 3 -#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 -#define FEC_PHYIDX 0 /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" @@ -507,8 +505,11 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" + #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -516,7 +517,9 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index b94e38ae347..771a9d3b950 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -489,8 +489,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -498,7 +500,8 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ -- cgit v1.3.1 From ac611700e5bcdd5a762dcc4d28db256fcc5a4bf2 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 20 Sep 2006 23:47:49 +0200 Subject: Fix comments in include/ppc440.h Patch by Martin Hicks, 16 Jun 2006 --- CHANGELOG | 3 +++ include/ppc440.h | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index a896e253a96..2059b66038b 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix comments in include/ppc440.h + Patch by Martin Hicks, 16 Jun 2006 + * Disable autoboot abort for FO300 when silent mode is enabled (according to S1 switch setting). diff --git a/include/ppc440.h b/include/ppc440.h index c4a3ed54835..e407320a9ef 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1570,8 +1570,8 @@ #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ #if defined(CONFIG_440GX) -#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */ -#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */ +#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */ +#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */ #endif /* CONFIG_440GX */ #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ -- cgit v1.3.1 From 7299712c869ce1f409a854ca0d2b268783038ab2 Mon Sep 17 00:00:00 2001 From: Marian Balakowicz Date: Tue, 3 Oct 2006 20:28:38 +0200 Subject: Update for CAM5200 board: - Map in a additional chip selects CS4 and CS5. - Modify the port configration, configure six UARTs and no PCI, ATA and USB. - Add custom flash driver to handle specific byte swapping --- CHANGELOG | 6 + board/tqm5200/Makefile | 5 +- board/tqm5200/cam5200_flash.c | 786 ++++++++++++++++++++++++++++++++++++++++++ include/configs/TQM5200.h | 101 ++++-- include/flash.h | 4 + 5 files changed, 868 insertions(+), 34 deletions(-) create mode 100644 board/tqm5200/cam5200_flash.c (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index a896e253a96..42768a365fc 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,12 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Update for CAM5200 board: + - Map in a additional chip selects CS4 and CS5. + - Modify the port configration, configure six UARTs and no PCI, + ATA and USB. + - Add custom flash driver to handle specific byte swapping + * Disable autoboot abort for FO300 when silent mode is enabled (according to S1 switch setting). diff --git a/board/tqm5200/Makefile b/board/tqm5200/Makefile index d0dde2657c7..383b0386082 100644 --- a/board/tqm5200/Makefile +++ b/board/tqm5200/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o cmd_stk52xx.o cmd_tb5200.o +COBJS := $(BOARD).o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) @@ -40,6 +40,9 @@ clean: distclean: clean rm -f $(LIB) core *.bak .depend +cam5200_flash.o: cam5200_flash.c + $(CC) $(CFLAGS) -fno-strict-aliasing -c -o $@ $< + ######################################################################### # defines $(obj).depend target diff --git a/board/tqm5200/cam5200_flash.c b/board/tqm5200/cam5200_flash.c new file mode 100644 index 00000000000..85d310b77df --- /dev/null +++ b/board/tqm5200/cam5200_flash.c @@ -0,0 +1,786 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_CAM5200 + +#if 0 +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif + +#define swap16(x) __swab16(x) + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * CAM5200 is a TQM5200B based board. Additionally it also features + * a NIOS cpu. The NIOS CPU peripherals are accessible through MPC5xxx + * Local Bus on CS5. This includes 32 bit wide RAM and SRAM as well as + * 16 bit wide flash device. Big Endian order on a 32 bit CS5 makes + * access to flash chip slightly more complicated as additional byte + * swapping is necessary within each 16 bit wide flash 'word'. + * + * This driver's task is to handle both flash devices: 32 bit TQM5200B + * flash chip and 16 bit NIOS cpu flash chip. In the below + * flash_addr_table table we use least significant address bit to mark + * 16 bit flash bank and two sets of routines *_32 and *_16 to handle + * specifics of both flashes. + */ +static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { + {CFG_BOOTCS_START, CFG_CS5_START | 1} +}; + +/*----------------------------------------------------------------------- + * Functions + */ +static int write_word(flash_info_t * info, ulong dest, ulong data); +#ifdef CFG_FLASH_2ND_16BIT_DEV +static int write_word_32(flash_info_t * info, ulong dest, ulong data); +static int write_word_16(flash_info_t * info, ulong dest, ulong data); +static int flash_erase_32(flash_info_t * info, int s_first, int s_last); +static int flash_erase_16(flash_info_t * info, int s_first, int s_last); +static ulong flash_get_size_32(vu_long * addr, flash_info_t * info); +static ulong flash_get_size_16(vu_long * addr, flash_info_t * info); +#endif + +void flash_print_info(flash_info_t * info) +{ + int i, k; + int size, erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_S29GL128N: + printf ("S29GL128N (256 Mbit, uniform sector size)\n"); + break; + case FLASH_AM320B: + printf ("29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf ("29LV320T (32 Mbit, top boot sect)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf("\n "); + + printf(" %08lX%s%s", info->start[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); + } + printf("\n"); + return; +} + + +/* + * The following code cannot be run from FLASH! + */ +#ifdef CFG_FLASH_2ND_16BIT_DEV +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +{ + + DEBUGF("get_size: FLASH ADDR %08lx\n", addr); + + /* bit 0 used for big flash marking */ + if ((ulong)addr & 0x1) + return flash_get_size_16((vu_long *)((ulong)addr & 0xfffffffe), info); + else + return flash_get_size_32(addr, info); +} + +static ulong flash_get_size_32(vu_long * addr, flash_info_t * info) +#else +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +#endif +{ + short i; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr); + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + udelay(1000); + + value = addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case AMD_ID_MIRROR: + DEBUGF("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", + addr[14], addr[15]); + switch(addr[14]) { + case AMD_ID_GL128N_2: + if (addr[15] != AMD_ID_GL128N_3) { + DEBUGF("Chip: S29GL128N -> unknown\n"); + info->flash_id = FLASH_UNKNOWN; + } else { + DEBUGF("Chip: S29GL128N\n"); + info->flash_id += FLASH_S29GL128N; + info->sector_count = 128; + info->size = 0x02000000; + } + break; + default: + info->flash_id = FLASH_UNKNOWN; + return(0); + } + break; + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00040000); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + info->protect[i] = addr2[2] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + + return (info->size); +} + +static int wait_for_DQ7_32(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (CFG_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +#ifdef CFG_FLASH_2ND_16BIT_DEV +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) { + return flash_erase_16(info, s_first, s_last); + } else { + return flash_erase_32(info, s_first, s_last); + } +} + +static int flash_erase_32(flash_info_t * info, int s_first, int s_last) +#else +int flash_erase(flash_info_t * info, int s_first, int s_last) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!", prot); + + printf("\n"); + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_32(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + + for (; cnt == 0 && i < 4; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + if ((rc = write_word(info, wp, data)) != 0) + return (rc); + + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) + data = (data << 8) | *src++; + + if ((rc = write_word(info, wp, data)) != 0) + return (rc); + + wp += 4; + cnt -= 4; + } + + if (cnt == 0) + return (0); + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +#ifdef CFG_FLASH_2ND_16BIT_DEV +static int write_word(flash_info_t * info, ulong dest, ulong data) +{ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) { + return write_word_16(info, dest, data); + } else { + return write_word_32(info, dest, data); + } +} + +static int write_word_32(flash_info_t * info, ulong dest, ulong data) +#else +static int write_word(flash_info_t * info, ulong dest, ulong data) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i, flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) + return (2); + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + return (1); + } + } + + return (0); +} + +#ifdef CFG_FLASH_2ND_16BIT_DEV + +#undef CFG_FLASH_WORD_SIZE +#define CFG_FLASH_WORD_SIZE unsigned short + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size_16(vu_long * addr, flash_info_t * info) +{ + short i; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr); + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000; + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90009000; + udelay(1000); + + value = swap16(addr2[0]); + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = swap16(addr2[1]); /* device ID */ + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00002000; + info->start[2] = base + 0x00004000; + info->start[3] = base + 0x00006000; + info->start[4] = base + 0x00008000; + info->start[5] = base + 0x0000a000; + info->start[6] = base + 0x0000c000; + info->start[7] = base + 0x0000e000; + + for (i = 8; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000) - 0x00070000; + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00002000; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000a000; + info->start[i--] = base + info->size - 0x0000c000; + info->start[i--] = base + info->size - 0x0000e000; + + for (; i >= 0; i--) + info->start[i] = base + i * 0x00010000; + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + info->protect[i] = addr2[2] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000; + + return (info->size); +} + +static int wait_for_DQ7_16(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x80008000) != + (CFG_FLASH_WORD_SIZE) 0x80008000) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +static int flash_erase_16(flash_info_t * info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!", prot); + + printf("\n"); + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80008000; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30003000; /* sector erase */ + + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_16(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000; /* reset bank */ + + printf(" done\n"); + return 0; +} + +static int write_word_16(flash_info_t * info, ulong dest, ulong data) +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + if ((dest2[i] & swap16(data2[i])) != swap16(data2[i])) + return (2); + } + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA000A000; + + dest2[i] = swap16(data2[i]); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80008000) != + (swap16(data2[i]) & (CFG_FLASH_WORD_SIZE) 0x80008000)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} +#endif /* CFG_FLASH_2ND_16BIT_DEV */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_word(flash_info_t * info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned short index = 0; + int i; + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) + continue; + + /* call flash_get_size() to initialize sector address */ + size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], + &flash_info[i]); + + flash_info[i].size = size_b[i]; + + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i] << 20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[i]); +#if defined(CFG_ENV_IS_IN_FLASH) + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#if defined(CFG_ENV_ADDR_REDUND) + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#endif +#endif + total_b += flash_info[i].size; + } + + return total_b; +} +#endif /* ifdef CONFIG_CAM5200 */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index e0de5c1b367..897d1b262b2 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -285,7 +285,7 @@ */ #define CFG_IPBSPEED_133 /* define for 133MHz speed */ -#if defined(CFG_IPBSPEED_133) +#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200) /* * PCI Bus clocking configuration * @@ -349,13 +349,29 @@ */ #define CFG_FLASH_BASE 0xFC000000 +#ifndef CONFIG_CAM5200 /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#else /* CONFIG_CAM5200 */ +#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks + (= chip selects) */ +#define CFG_FLASH_WORD_SIZE unsigned int /* main flash device with */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_ADDR0 0x555 +#define CFG_FLASH_ADDR1 0x2AA +#define CFG_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */ +#define CFG_MAX_FLASH_SECT 128 +#endif /* ifndef CONFIG_CAM5200 */ + #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ #define CFG_FLASH_USE_BUFFER_WRITE 1 #if defined (CONFIG_CAM5200) @@ -366,9 +382,6 @@ # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) #endif -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ - /* Dynamic MTD partition support */ #define CONFIG_JFFS2_CMDLINE #define MTDIDS_DEFAULT "nor0=TQM5200-0" @@ -401,10 +414,8 @@ #elif defined (CONFIG_CAM5200) # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \ "1792k(kernel)," \ - "3584k(small-fs)," \ - "2m(initrd)," \ - "8m(misc)," \ - "16m(big-fs)" + "5632k(rootfs)," \ + "24m(home)" #elif defined (CONFIG_FO300) # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ "1408k(kernel)," \ @@ -479,31 +490,43 @@ /* * GPIO configuration * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 + * use CS1: Bit 0 (mask: 0x80000000): + * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1). * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards and FO300 boards. Do not use - * with REV100 modules (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * 01x -> Use AC97 - * use PSC3: Bits 20-23 (mask: 0x00000f00) - * 1100 -> UART/SPI (on FO300 board) - * use PSC6: - * on STK52xx and FO300: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. + * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. + * SPI on PSC3 according to PSC3 setting. Use for CAM5200. + * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. + * Use for REV200 STK52XX boards and FO300 boards. Do not use + * with REV100 modules (because, there I2C1 is used as I2C bus). + * use ATA: Bits 6-7 (mask 0x03000000): + * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects. + * Use for CAM5200 board. + * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards. + * use PSC6: Bits 9-11 (mask 0x00700000): + * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as + * UART, CODEC or IrDA. + * GPIO on PSC6_3 is used in post_hotkeys_pressed() to + * enable extended POST tests. + * Use for MINI-FAP and TQM5200_IB boards. + * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used. + * Extended POST test is not available. + * Use for STK52xx, FO300 and CAM5200 boards. + * use PCI_DIS: Bit 16 (mask 0x00008000): + * 1 -> disable PCI controller (on CAM5200 board). + * use USB: Bits 18-19 (mask 0x00003000): + * 10 -> two UARTs (on FO300 and CAM5200). + * use PSC3: Bits 20-23 (mask: 0x00000f00): + * 0000 -> All PSC3 pins are GPIOs. + * 1100 -> UART/SPI (on FO300 board). + * 0100 -> UART (on CAM5200 board). + * use PSC2: Bits 25:27 (mask: 0x00000030): + * 000 -> All PSC2 pins are GPIOs. + * 100 -> UART (on CAM5200 board). + * 001 -> CAN1/2 on PSC2 pins. + * Use for REV100 STK52xx boards + * 01x -> Use AC97 (on FO300 board). + * use PSC1: Bits 29-31 (mask: 0x00000007): + * 100 -> UART (on all boards). */ #if defined (CONFIG_MINIFAP) # define CFG_GPS_PORT_CONFIG 0x91000004 @@ -519,6 +542,8 @@ # endif #elif defined (CONFIG_FO300) # define CFG_GPS_PORT_CONFIG 0x91502c24 +#elif defined (CONFIG_CAM5200) +# define CFG_GPS_PORT_CONFIG 0x8050A444 #else /* TMQ5200 Inbetriebnahme-Board */ # define CFG_GPS_PORT_CONFIG 0x81000004 #endif @@ -613,6 +638,16 @@ #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ +#if defined(CONFIG_CAM5200) +#define CFG_CS4_START 0xB0000000 +#define CFG_CS4_SIZE 0x00010000 +#define CFG_CS4_CFG 0x01019C10 + +#define CFG_CS5_START 0xD0000000 +#define CFG_CS5_SIZE 0x01208000 +#define CFG_CS5_CFG 0x1414BF10 +#endif + #define CFG_RESET_ADDRESS 0xff000000 /*----------------------------------------------------------------------- diff --git a/include/flash.h b/include/flash.h index 84b48a9f2e7..d91589a6c02 100644 --- a/include/flash.h +++ b/include/flash.h @@ -209,6 +209,9 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */ #define AMD_ID_GL064MT_2 0x22102210 /* 2nd ID word for S29GL064M-R3 (top boot sector) */ #define AMD_ID_GL064MT_3 0x22012201 /* 3rd ID word for S29GL064M-R3 (top boot sector) */ +#define AMD_ID_GL128N_2 0x22212221 /* 2nd ID word for S29GL128N */ +#define AMD_ID_GL128N_3 0x22012201 /* 3rd ID word for S29GL128N */ + #define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */ #define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */ @@ -417,6 +420,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */ #define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */ #define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */ +#define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */ #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ -- cgit v1.3.1 From 511d0c72b82aab9b807efde50fc9e390365f5ca1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 9 Oct 2006 00:42:01 +0200 Subject: Coding style cleanup --- CHANGELOG | 2 ++ board/Marvell/db64360/Makefile | 2 +- board/Marvell/db64460/Makefile | 2 +- board/amcc/sequoia/sequoia.c | 72 +++++++++++++++++++++--------------------- board/amcc/yucca/yucca.c | 3 -- board/dave/B2/Makefile | 2 +- board/esd/cpci750/Makefile | 2 +- board/evb64260/Makefile | 2 +- board/ispan/Makefile | 2 +- board/jse/Makefile | 2 +- board/netstar/Makefile | 2 +- board/sc520_spunk/Makefile | 2 +- board/tqm5200/cam5200_flash.c | 2 +- board/tqm834x/Makefile | 2 +- common/lcd.c | 4 +-- config.mk | 2 +- cpu/i386/Makefile | 2 +- cpu/mpc5xxx/interrupts.c | 2 +- cpu/mpc83xx/Makefile | 2 +- cpu/ppc4xx/ndfc.c | 24 +++++++------- cpu/ppc4xx/start.S | 6 ++-- drivers/serial.c | 6 ++-- drivers/sk98lin/Makefile | 1 - include/common.h | 2 +- lib_generic/Makefile | 2 +- nand_spl/nand_boot.c | 4 +-- tools/Makefile | 2 +- tools/gdb/Makefile | 2 +- 28 files changed, 79 insertions(+), 81 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index e12d767276e..6e797d6c9aa 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Coding style cleanup + * Add support for EP82xxM boards Patch by Aaron Sells, 20 Jun 2006 diff --git a/board/Marvell/db64360/Makefile b/board/Marvell/db64360/Makefile index a084c894ae3..f983cd96b4b 100644 --- a/board/Marvell/db64360/Makefile +++ b/board/Marvell/db64360/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# +# # (C) Copyright 2001 # Josh Huber , Mission Critical Linux, Inc. # diff --git a/board/Marvell/db64460/Makefile b/board/Marvell/db64460/Makefile index a084c894ae3..f983cd96b4b 100644 --- a/board/Marvell/db64460/Makefile +++ b/board/Marvell/db64460/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# +# # (C) Copyright 2001 # Josh Huber , Mission Critical Linux, Inc. # diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index a8ba2c08319..ccf6f0c8039 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -4,7 +4,7 @@ * * (C) Copyright 2006 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -123,12 +123,12 @@ int board_early_init_f(void) /* setup NAND FLASH */ mfsdr(SDR0_CUST0, sdr0_cust0); - sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | + sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | (0x80000000 >> (28 + CFG_NAND_CS)); - mtsdr(SDR0_CUST0, sdr0_cust0); + mtsdr(SDR0_CUST0, sdr0_cust0); return 0; } @@ -216,38 +216,38 @@ int misc_init_r(void) #ifdef CONFIG_440EPX if (act == NULL || strcmp(act, "hostdev") == 0) { /* SDR Setting */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_USB0, usb2d0cr); - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); + mfsdr(SDR0_PFC1, sdr0_pfc1); + mfsdr(SDR0_USB0, usb2d0cr); + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2H0CR, usb2h0cr); usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ /* An 8-bit/60MHz interface is the only possible alternative when connecting the Device to the PHY */ - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ - /* To enable the USB 2.0 Device function through the UTMI interface */ - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ + /* To enable the USB 2.0 Device function through the UTMI interface */ + usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; + usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ + sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ - mtsdr(SDR0_PFC1, sdr0_pfc1); - mtsdr(SDR0_USB0, usb2d0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2H0CR, usb2h0cr); + mtsdr(SDR0_PFC1, sdr0_pfc1); + mtsdr(SDR0_USB0, usb2d0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB2H0CR, usb2h0cr); /*clear resets*/ udelay (1000); @@ -264,11 +264,11 @@ int misc_init_r(void) usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); udelay (1000); @@ -287,33 +287,33 @@ int misc_init_r(void) /*-------------------PATCH-------------------------------*/ /* SDR Setting */ - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); mfsdr(SDR0_USB2H0CR, usb2h0cr); mfsdr(SDR0_USB0, usb2d0cr); mfsdr(SDR0_PFC1, sdr0_pfc1); usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/ + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/ + usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/ + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/ - mtsdr(SDR0_USB2H0CR, usb2h0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB2H0CR, usb2h0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB0, usb2d0cr); mtsdr(SDR0_PFC1, sdr0_pfc1); diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index cd175265f0d..e9b34dd249a 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -958,7 +958,6 @@ int is_pci_host(struct pci_controller *hose) return 1; } - int yucca_pcie_card_present(int port) { u16 reg; @@ -1084,8 +1083,6 @@ void yucca_setup_pcie_fpga_endpoint(int port) (endpoint | in_be16((u16 *)FPGA_REG1C))); } - - static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; void pcie_setup_hoses(void) diff --git a/board/dave/B2/Makefile b/board/dave/B2/Makefile index 106025da1eb..1762f6f084c 100644 --- a/board/dave/B2/Makefile +++ b/board/dave/B2/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# +# # (C) Copyright 2002 # Sysgo Real-Time Solutions, GmbH # Marius Groeger diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile index 0dfec601ea8..2f61d94e88d 100644 --- a/board/esd/cpci750/Makefile +++ b/board/esd/cpci750/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# +# # (C) Copyright 2001 # Josh Huber , Mission Critical Linux, Inc. # diff --git a/board/evb64260/Makefile b/board/evb64260/Makefile index b28372d818c..925844ccc4e 100644 --- a/board/evb64260/Makefile +++ b/board/evb64260/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# +# # (C) Copyright 2001 # Josh Huber , Mission Critical Linux, Inc. # diff --git a/board/ispan/Makefile b/board/ispan/Makefile index 0c1cb0253ab..d0223b51ffc 100644 --- a/board/ispan/Makefile +++ b/board/ispan/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# +# # Copyright (C) 2004 Arabella Software Ltd. # Yuli Barcohen # diff --git a/board/jse/Makefile b/board/jse/Makefile index be6bd315cdf..edbfc3f776d 100644 --- a/board/jse/Makefile +++ b/board/jse/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# +# # Copyright 2004 Picture Elements, Inc. # Stephen Williams # diff --git a/board/netstar/Makefile b/board/netstar/Makefile index b7c092d24f0..27d96d2baab 100644 --- a/board/netstar/Makefile +++ b/board/netstar/Makefile @@ -1,4 +1,4 @@ -# +# # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # diff --git a/board/sc520_spunk/Makefile b/board/sc520_spunk/Makefile index 9958e802686..5e8c15d1eb7 100644 --- a/board/sc520_spunk/Makefile +++ b/board/sc520_spunk/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# +# # (C) Copyright 2002 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se. # diff --git a/board/tqm5200/cam5200_flash.c b/board/tqm5200/cam5200_flash.c index 85d310b77df..1a40633e569 100644 --- a/board/tqm5200/cam5200_flash.c +++ b/board/tqm5200/cam5200_flash.c @@ -46,7 +46,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ * swapping is necessary within each 16 bit wide flash 'word'. * * This driver's task is to handle both flash devices: 32 bit TQM5200B - * flash chip and 16 bit NIOS cpu flash chip. In the below + * flash chip and 16 bit NIOS cpu flash chip. In the below * flash_addr_table table we use least significant address bit to mark * 16 bit flash bank and two sets of routines *_32 and *_16 to handle * specifics of both flashes. diff --git a/board/tqm834x/Makefile b/board/tqm834x/Makefile index 6991cfbf28a..24bd93f92b9 100644 --- a/board/tqm834x/Makefile +++ b/board/tqm834x/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# +# # Copyright 2004 Freescale Semiconductor, Inc. # # See file CREDITS for list of people who contributed to this diff --git a/common/lcd.c b/common/lcd.c index d79350f2347..df31ca9b8c2 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -661,8 +661,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) * So, in case of Monochrome BMP we should align widths * on a byte boundary and convert them from Bit to Byte * units. - * Probably, PXA250 and MPC823 process 1bpp BMP images in - * their own ways, so make the converting to be MCC200 + * Probably, PXA250 and MPC823 process 1bpp BMP images in + * their own ways, so make the converting to be MCC200 * specific. */ #if defined(CONFIG_MCC200) diff --git a/config.mk b/config.mk index 0f5d0f43d94..500fbcfe117 100644 --- a/config.mk +++ b/config.mk @@ -25,7 +25,7 @@ ifneq ($(OBJTREE),$(SRCTREE)) ifeq ($(CURDIR),$(SRCTREE)) -dir := +dir := else dir := $(subst $(SRCTREE)/,,$(CURDIR)) endif diff --git a/cpu/i386/Makefile b/cpu/i386/Makefile index cd46dea2c74..1245cf01081 100644 --- a/cpu/i386/Makefile +++ b/cpu/i386/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# +# # (C) Copyright 2002 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se. # diff --git a/cpu/mpc5xxx/interrupts.c b/cpu/mpc5xxx/interrupts.c index 7b5cb8be4e2..beeb222636e 100644 --- a/cpu/mpc5xxx/interrupts.c +++ b/cpu/mpc5xxx/interrupts.c @@ -32,7 +32,7 @@ * * Based on (well, mostly copied from) the code from the 2.4 kernel by * Dale Farnsworth and Kent Borg. - * + * * Copyright (C) 2004 Sylvain Munaut * Copyright (C) 2003 Montavista Software, Inc */ diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index f3fa6fd93ab..85e32e16302 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# +# # Copyright 2004 Freescale Semiconductor, Inc. # # See file CREDITS for list of people who contributed to this diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index c255f93e6bb..183ab5ef168 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -65,8 +65,8 @@ static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd) static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte) { - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; if (hwctl & 0x1) out8(base + NDFC_CMD, byte); @@ -78,16 +78,16 @@ static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte) static u_char ndfc_read_byte(struct mtd_info *mtdinfo) { - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; return (in8(base + NDFC_DATA)); } static int ndfc_dev_ready(struct mtd_info *mtdinfo) { - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY)) ; @@ -110,8 +110,8 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo) */ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) { - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; uint32_t *p = (uint32_t *) buf; for(;len > 0; len -= 4) @@ -120,8 +120,8 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; uint32_t *p = (uint32_t *) buf; for(; len > 0; len -= 4) @@ -130,8 +130,8 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; uint32_t *p = (uint32_t *) buf; for(; len > 0; len -= 4) diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 5a1ab386b18..3f2931411f3 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -173,9 +173,9 @@ /**************************************************************************/ _start_440: - /*--------------------------------------------------------------------+ - | 440EPX BUP Change - Hardware team request - +--------------------------------------------------------------------*/ + /*--------------------------------------------------------------------+ + | 440EPX BUP Change - Hardware team request + +--------------------------------------------------------------------*/ #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) sync nop diff --git a/drivers/serial.c b/drivers/serial.c index 8d1ae96bf85..76425d87901 100644 --- a/drivers/serial.c +++ b/drivers/serial.c @@ -39,7 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; #if !defined(CONFIG_CONS_INDEX) #if defined (CONFIG_SERIAL_MULTI) /* with CONFIG_SERIAL_MULTI we might have no console - * on these devices + * on these devices */ #else #error "No console index specified." @@ -238,7 +238,7 @@ serial_putc(const char c) #endif #if defined(CONFIG_SERIAL_MULTI) -static inline void +static inline void serial_putc_raw_dev(unsigned int dev_index,const char c) { _serial_putc_raw(c,dev_index); @@ -310,7 +310,7 @@ serial_setbrg(void) #if defined(CONFIG_SERIAL_MULTI) DECLARE_ESERIAL_FUNCTIONS(1); -struct serial_device eserial1_device = +struct serial_device eserial1_device = INIT_ESERIAL_STRUCTURE(1,"eserial0","EUART1"); DECLARE_ESERIAL_FUNCTIONS(2); struct serial_device eserial2_device = diff --git a/drivers/sk98lin/Makefile b/drivers/sk98lin/Makefile index ac21e02133f..76c750cdb86 100644 --- a/drivers/sk98lin/Makefile +++ b/drivers/sk98lin/Makefile @@ -104,4 +104,3 @@ include $(SRCTREE)/rules.mk sinclude $(obj).depend ######################################################################### - diff --git a/include/common.h b/include/common.h index bee2fb70224..a873fa99b7a 100644 --- a/include/common.h +++ b/include/common.h @@ -110,7 +110,7 @@ typedef volatile unsigned char vu_char; #endif /* DEBUG */ #define BUG() do { \ - printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ + printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ panic("BUG!"); \ } while (0) #define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0) diff --git a/lib_generic/Makefile b/lib_generic/Makefile index fcd43c676f7..a05b3552de3 100644 --- a/lib_generic/Makefile +++ b/lib_generic/Makefile @@ -29,7 +29,7 @@ COBJS = bzlib.o bzlib_crctable.o bzlib_decompress.o \ bzlib_randtable.o bzlib_huffman.o \ crc32.o ctype.o display_options.o ldiv.o \ string.o vsprintf.o zlib.o - + SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c index 21abb09e39b..a136fb70745 100644 --- a/nand_spl/nand_boot.c +++ b/nand_spl/nand_boot.c @@ -34,7 +34,7 @@ extern int jump_to_uboot(ulong addr); static int nand_is_bad_block(struct mtd_info *mtd, int block) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd->priv; int page_addr = block * CFG_NAND_PAGE_COUNT; /* Begin command latch cycle */ @@ -73,7 +73,7 @@ static int nand_is_bad_block(struct mtd_info *mtd, int block) static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd->priv; int page_addr = page + block * CFG_NAND_PAGE_COUNT; int i; diff --git a/tools/Makefile b/tools/Makefile index 606f0240376..6177f902716 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -108,7 +108,7 @@ endif include $(TOPDIR)/config.mk # now $(obj) is defined -SRCS := $(addprefix $(obj),$(OBJ_LINKS:.o=.c)) $(OBJ_FILES:.o=.c) +SRCS := $(addprefix $(obj),$(OBJ_LINKS:.o=.c)) $(OBJ_FILES:.o=.c) BINS := $(addprefix $(obj),$(BIN_FILES)) # diff --git a/tools/gdb/Makefile b/tools/gdb/Makefile index dbcb91f5ed7..632103d4538 100644 --- a/tools/gdb/Makefile +++ b/tools/gdb/Makefile @@ -31,7 +31,7 @@ BINS = gdbsend gdbcont COBJS = gdbsend.o gdbcont.o error.o remote.o serial.o OBJS := $(addprefix $(obj),$(COBJS)) -SRCS := $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) BINS := $(addprefix $(obj),$(BINS)) # -- cgit v1.3.1 From 7ce343e49993341f2cdd559e0c44ad7507f71eb7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 9 Oct 2006 00:48:57 +0200 Subject: Add missing files for EP82xxM boards Patch by Aaron Sells, 20 Jun 2006 --- board/ep82xxm/Makefile | 49 ++++++ board/ep82xxm/config.mk | 26 +++ board/ep82xxm/ep82xxm.c | 291 ++++++++++++++++++++++++++++++++++ board/ep82xxm/u-boot.lds | 125 +++++++++++++++ include/configs/ep82xxm.h | 395 ++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 886 insertions(+) create mode 100644 board/ep82xxm/Makefile create mode 100644 board/ep82xxm/config.mk create mode 100644 board/ep82xxm/ep82xxm.c create mode 100644 board/ep82xxm/u-boot.lds create mode 100644 include/configs/ep82xxm.h (limited to 'include') diff --git a/board/ep82xxm/Makefile b/board/ep82xxm/Makefile new file mode 100644 index 00000000000..3d5490aa58b --- /dev/null +++ b/board/ep82xxm/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ep82xxm/config.mk b/board/ep82xxm/config.mk new file mode 100644 index 00000000000..da039e21b3e --- /dev/null +++ b/board/ep82xxm/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# EP82xxM series boards by Embedded Planet + +TEXT_BASE = 0xFFF00000 diff --git a/board/ep82xxm/ep82xxm.c b/board/ep82xxm/ep82xxm.c new file mode 100644 index 00000000000..35e644df8c3 --- /dev/null +++ b/board/ep82xxm/ep82xxm.c @@ -0,0 +1,291 @@ +/* + * Copyright (C) 2006 Embedded Planet, LLC. + * + * Support for Embedded Planet EP82xxM boards. + * Tested on EP82xxM (MPC8270). + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#ifdef CONFIG_PCI +#include +#endif +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +#define CFG_FCC2 1 +#define CFG_FCC3 1 + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 0, 0, 0, 0, 1 }, /* PA31 */ + /* PA30 */ { 0, 0, 0, 0, 0, 1 }, /* PA30 */ + /* PA29 */ { 0, 0, 0, 0, 0, 1 }, /* PA29 */ + /* PA28 */ { 0, 0, 0, 0, 0, 1 }, /* PA28 */ + /* PA27 */ { 0, 0, 0, 0, 0, 1 }, /* PA27 */ + /* PA26 */ { 0, 0, 0, 0, 0, 1 }, /* PA26 */ + /* PA25 */ { 0, 0, 0, 0, 0, 1 }, /* PA25 */ + /* PA24 */ { 0, 0, 0, 0, 0, 1 }, /* PA24 */ + /* PA23 */ { 0, 0, 0, 0, 0, 1 }, /* PA23 */ + /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ + /* PA21 */ { 0, 0, 0, 0, 0, 1 }, /* PA21 */ + /* PA20 */ { 0, 0, 0, 0, 0, 1 }, /* PA20 */ + /* PA19 */ { 0, 0, 0, 0, 0, 1 }, /* PA19 */ + /* PA18 */ { 0, 0, 0, 0, 0, 1 }, /* PA18 */ + /* PA17 */ { 0, 0, 0, 0, 0, 1 }, /* PA17 */ + /* PA16 */ { 0, 0, 0, 0, 0, 1 }, /* PA16 */ + /* PA15 */ { 0, 0, 0, 0, 0, 1 }, /* PA15 */ + /* PA14 */ { 0, 0, 0, 0, 0, 1 }, /* PA14 */ + /* PA13 */ { 0, 0, 0, 0, 0, 1 }, /* PA13 */ + /* PA12 */ { 0, 0, 0, 0, 0, 1 }, /* PA12 */ + /* PA11 */ { 0, 0, 0, 0, 0, 1 }, /* PA11 */ + /* PA10 */ { 0, 0, 0, 0, 0, 1 }, /* PA10 */ + /* PA9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC2 TxD */ + /* PA8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC2 RxD */ + /* PA7 */ { 0, 0, 0, 0, 0, 1 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 0, 0, 1 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 0, 0, 1 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 0, 0, 1 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 0, 0, 1 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 0, 0, 1 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 1 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 0, 0, 1 } /* PA0 */ + }, + + /* Port B */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 CTS# */ + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ + /* PC27 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3: TXD[0] */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ + /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ + /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ + /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* RxClk (CLK13) */ + /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* TxClk (CLK14) */ + /* PC17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* RxClk (CLK15) */ + /* PC16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* TxClk (CLK16) */ + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 CD# */ + /* PC13 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CTS# */ + /* PC12 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CD# */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ + /* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 CD# */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */ + /* PC8 */ { 1, 1, 1, 0, 0, 0 }, /* SCC3 CTS# */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ + /* PD30 */ { 1, 1, 1, 1, 0, 1 }, /* SCC1 TXD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS# */ + /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ + /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ + /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS# */ + /* PD25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */ + /* PD24 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 TXD */ + /* PD23 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 RTS# */ + /* PD22 */ { 0, 0, 0, 0, 0, 1 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 0, 0, 1 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 0, 0, 1 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 0, 0, 1 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 1 }, /* PD18 */ + /* PD17 */ { 0, 0, 0, 0, 0, 1 }, /* PD17 */ + /* PD16 */ { 0, 0, 0, 0, 0, 1 }, /* PD16 */ + /* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SCL */ + /* PD13 */ { 0, 0, 0, 0, 0, 1 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 1 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 1 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 1 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC1 TxD */ + /* PD8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 RxD */ + /* PD7 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 SMSYN */ + /* PD6 */ { 0, 0, 0, 0, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 0, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + } +}; + +#ifdef CONFIG_PCI +typedef struct pci_ic_s { + unsigned long pci_int_stat; + unsigned long pci_int_mask; +}pci_ic_t; +#endif + +int board_early_init_f (void) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + + bcsr[4] |= 0x30; /* Turn the LEDs off */ + +#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC) + bcsr[6] |= 0x10; +#endif +#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC) + bcsr[7] |= 0x10; +#endif + +#if CFG_FCC3 + bcsr[8] |= 0xC0; +#endif /* CFG_FCC3 */ +#if CFG_FCC2 + bcsr[8] |= 0x30; +#endif /* CFG_FCC2 */ + + return 0; +} + +long int initdram(int board_type) +{ + /* Size in MB of SDRAM populated on board*/ + long int msize = 256; + +#ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE; + uchar c = 0xFF; + uint psdmr = CFG_PSDMR; + int i; + + unsigned char ramtmp; + unsigned char *ramptr1 = (unsigned char *)0x00000110; + + memctl->memc_mptpr = CFG_MPTPR; + +udelay(400); + + /* Initialise 60x bus SDRAM */ + memctl->memc_psrt = CFG_PSRT; + memctl->memc_or1 = CFG_SDRAM_OR; + memctl->memc_br1 = CFG_SDRAM_BR; + memctl->memc_psdmr = psdmr; + +udelay(400); + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ + ramtmp = *ramptr1; + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ + for (i = 0; i < 8; i++) { + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ + } + ramtmp = *ramptr1; + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ + *ramptr1 = 0xFF; + memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ +#endif /* !CFG_RAMBOOT */ + + /* Return total 60x bus SDRAM size */ + return msize * 1024 * 1024; +} + +int checkboard(void) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + + puts("Board: "); + switch (bcsr[0]) { + case 0x0A: + printf("EP82xxM 1.0 CPLD revision %d\n", bcsr[1]); + break; + default: + printf("unknown: ID=%02X\n", bcsr[0]); + } + + return 0; +} + +#ifdef CONFIG_PCI +struct pci_controller hose; + +extern void pci_mpc8250_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc8250_init(&hose); +} +#endif diff --git a/board/ep82xxm/u-boot.lds b/board/ep82xxm/u-boot.lds new file mode 100644 index 00000000000..18c4b46f47b --- /dev/null +++ b/board/ep82xxm/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h new file mode 100644 index 00000000000..5d7bed611a0 --- /dev/null +++ b/include/configs/ep82xxm.h @@ -0,0 +1,395 @@ +/* + * Copyright (C) 2006 Embedded Planet, LLC. + * + * U-Boot configuration for Embedded Planet EP82xxM boards. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MPC8260 +#define CPU_ID_STR "MPC8270" + +#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board /* + /* 256MB SDRAM / 64MB FLASH */ + +#undef DEBUG + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/* + * Select serial console configuration + * + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + */ +#define CONFIG_CONS_ON_SMC /* Console is on SMC */ +#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ +#undef CONFIG_CONS_NONE /* It's not on external UART */ +#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ + +#define CFG_BCSR 0xFA000000 + +/* + * Select ethernet configuration + * + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, + * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for + * SCC, 1-3 for FCC) + * + * If CONFIG_ETHER_NONE is defined, then either the ethernet routines + * must be defined elsewhere (as for the console), or CFG_CMD_NET must + * be removed from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ +#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ +#undef CONFIG_ETHER_NONE /* No external Ethernet */ + +#define CONFIG_NET_MULTI + +#define CONFIG_ETHER_ON_FCC2 +#define CONFIG_ETHER_ON_FCC3 + +#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) +#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16) +#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) + +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ + +/* + * GPIO pins used for bit-banged MII communications + */ +#define MDIO_PORT 0 /* Not used - implemented in BCSR */ +#define MDIO_ACTIVE (*(vu_char *)(CFG_BCSR + 8) &= 0xFB) +#define MDIO_TRISTATE (*(vu_char *)(CFG_BCSR + 8) |= 0x04) +#define MDIO_READ (*(vu_char *)(CFG_BCSR + 8) & 1) + +#define MDIO(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \ + else *(vu_char *)(CFG_BCSR + 8) &= 0xFE + +#define MDC(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \ + else *(vu_char *)(CFG_BCSR + 8) &= 0xFD + +#define MIIDELAY udelay(1) + + +#ifndef CONFIG_8260_CLKIN +#define CONFIG_8260_CLKIN 66000000 /* in Hz */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_ECHO \ + | CFG_CMD_I2C \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + | CFG_CMD_DATE \ + | CFG_CMD_DTT \ + | CFG_CMD_EEPROM \ + | CFG_CMD_PCI \ + | CFG_CMD_DIAG \ + ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_ETHADDR 00:10:EC:00:88:65 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:10:EC:80:88:65 +#define CONFIG_IPADDR 10.0.0.245 +#define CONFIG_HOSTNAME EP82xxM +#define CONFIG_SERVERIP 10.0.0.26 +#define CONFIG_GATEWAYIP 10.0.0.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CFG_ENV_IN_OWN_SECT 1 +#define CFG_AUTO_COMPLETE +#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3 ETHERNET" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#endif + +#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "ep82xxm=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +/* + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#endif + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_BASE 0xFC000000 +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +/* EEPROM Configuration */ +#define CFG_EEPROM_SIZE 0x1000 +#define CFG_I2C_EEPROM_ADDR 0x54 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x0 +#endif /* CFG_ENV_IS_IN_EEPROM */ + +/* RTC Configuration */ +#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */ +#define CFG_I2C_RTC_ADDR 0x68 +#define CONFIG_M41T11_BASE_YEAR 1900 + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM75 1 +#define CONFIG_DTT_SENSORS {0} +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +/*----------------------------------------------------------------------- + * NVRAM Configuration + *----------------------------------------------------------------------- + */ +#define CFG_NVRAM_BASE_ADDR 0xFA080000 +#define CFG_NVRAM_SIZE (128*1024)-16 + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_BOOTDELAY 0 + +/* PCI Memory map (if different from default map */ +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ +#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ +#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ + PICMR_PREFETCH_EN) + +/* + * These are the windows that allow the CPU to access PCI address space. + * All three PCI master windows, which allow the CPU to access PCI + * prefetch, non prefetch, and IO space (see below), must all fit within + * these windows. + */ + +/* + * Master window that allows the CPU to access PCI Memory (prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ +#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ +#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL +#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) + +/* + * Master window that allows the CPU to access PCI Memory (non-prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ +#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ +#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL +#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) + +/* + * Master window that allows the CPU to access PCI IO space. + * This window will be setup with the first set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ +#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ +#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL +#define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ +#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) + + +/* PCIBR0 - for PCI IO*/ +#define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */ +#define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ +/* PCIBR1 - prefetch and non-prefetch regions joined together */ +#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL +#define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U) + + +#define CFG_DIRECT_FLASH_TFTP + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS +#define CFG_JFFS2_FIRST_SECTOR 0 +#define CFG_JFFS2_LAST_SECTOR 62 +#define CFG_JFFS2_SORT_FRAGMENTS +#define CFG_JFFS_CUSTOM_PART +#endif /* CFG_CMD_JFFS2 */ + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#define CFG_I2C_SPEED 100000 /* I2C speed */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ +#endif /* CFG_CMD_I2C */ + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 256KB for Monitor */ + +#define CFG_DEFAULT_IMMR 0x00010000 +#define CFG_IMMR 0xF0000000 + +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* Hard reset configuration word */ +#define CFG_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */ +/* No slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 + +#define CFG_HID2 0 + +#define CFG_SIUMCR 0x02610000 +#define CFG_SYPCR 0xFFFF0689 +#define CFG_BCR 0x8080E000 +#define CFG_SCCR 0x00000001 + +#define CFG_RMR 0 +#define CFG_TMCNTSC 0x000000C3 +#define CFG_PISCR 0x00000083 +#define CFG_RCCR 0 + +#define CFG_MPTPR 0x0A00 +#define CFG_PSDMR 0xC432246E +#define CFG_PSRT 0x32 + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00000041) +#define CFG_SDRAM_OR 0xF0002900 + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801) +#define CFG_OR0_PRELIM 0xFC000882 +#define CFG_BR4_PRELIM (CFG_BCSR | 0x00001001) +#define CFG_OR4_PRELIM 0xFFF00050 + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 1a1b7374b89a04737c76948b00207b56a1bb37b6 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 9 Oct 2006 12:55:38 +0200 Subject: Define IH_CPU_AVR32 Make it possible to generate AVR32 uImage files with mkimage and make cmd_bootm recognize them. Patch by Haavard Skinnemoen, 22 Sep 2006 --- CHANGELOG | 5 +++++ common/cmd_bootm.c | 3 +++ include/image.h | 1 + tools/mkimage.c | 1 + 4 files changed, 10 insertions(+) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index b6ba66d09ce..e3ab62138dd 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,11 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Define IH_CPU_AVR32 + Make it possible to generate AVR32 uImage files with mkimage and + make cmd_bootm recognize them. + Patch by Haavard Skinnemoen, 22 Sep 2006 + * Make bootp implementation RFC3046 compliant Patch by Joakim Larsson, 27 Jun 2006 diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index fdf7180a19a..2168e6737a0 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -260,6 +260,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (hdr->ih_arch != IH_CPU_NIOS2) #elif defined(__blackfin__) if (hdr->ih_arch != IH_CPU_BLACKFIN) +#elif defined(__avr32__) + if (hdr->ih_arch != IH_CPU_AVR32) #else # error Unknown CPU type #endif @@ -1236,6 +1238,7 @@ print_type (image_header_t *hdr) case IH_CPU_INVALID: arch = "Invalid CPU"; break; case IH_CPU_ALPHA: arch = "Alpha"; break; case IH_CPU_ARM: arch = "ARM"; break; + case IH_CPU_AVR32: arch = "AVR32"; break; case IH_CPU_I386: arch = "Intel x86"; break; case IH_CPU_IA64: arch = "IA64"; break; case IH_CPU_MIPS: arch = "MIPS"; break; diff --git a/include/image.h b/include/image.h index 139df0b2d1e..d9f2d461a5f 100644 --- a/include/image.h +++ b/include/image.h @@ -76,6 +76,7 @@ #define IH_CPU_MICROBLAZE 14 /* MicroBlaze */ #define IH_CPU_NIOS2 15 /* Nios-II */ #define IH_CPU_BLACKFIN 16 /* Blackfin */ +#define IH_CPU_AVR32 17 /* AVR32 */ /* * Image Types diff --git a/tools/mkimage.c b/tools/mkimage.c index 60aac79f234..5f3634de426 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -94,6 +94,7 @@ table_entry_t arch_name[] = { { IH_CPU_SPARC, "sparc", "SPARC", }, { IH_CPU_SPARC64, "sparc64", "SPARC 64 Bit", }, { IH_CPU_BLACKFIN, "blackfin", "Blackfin", }, + { IH_CPU_AVR32, "avr32", "AVR32", }, { -1, "", "", }, }; -- cgit v1.3.1 From 2255b2d2044d434463eb2661e18018e50f1643d9 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 10 Oct 2006 12:36:02 +0200 Subject: * Several improvements to the new NAND subsystem: - JFFS2 related commands implemented in mtd-utils style - Support for bad blocks - Bad block testing commands - NAND lock commands Please take a look at doc/README.nand for more details Patch by Guido Classen, 10 Oct 2006 --- CHANGELOG | 8 + common/cmd_nand.c | 226 ++++++++++-- doc/README.nand | 44 +++ drivers/nand/Makefile | 2 +- drivers/nand/nand_util.c | 869 +++++++++++++++++++++++++++++++++++++++++++++++ include/nand.h | 57 ++++ lib_generic/crc32.c | 4 +- 7 files changed, 1183 insertions(+), 27 deletions(-) create mode 100644 drivers/nand/nand_util.c (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index a2ea35d68e3..9ed65bdbfe4 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,14 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Several improvements to the new NAND subsystem: + - JFFS2 related commands implemented in mtd-utils style + - Support for bad blocks + - Bad block testing commands + - NAND lock commands + Please take a look at doc/README.nand for more details + Patch by Guido Classen, 10 Oct 2006 + * Define IH_CPU_AVR32 Make it possible to generate AVR32 uImage files with mkimage and make cmd_bootm recognize them. diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 21adb1b4786..274ef0b9938 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -135,11 +135,16 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ulong addr, off, size; char *cmd, *s; nand_info_t *nand; + int quiet = 0; + const char *quiet_str = getenv("quiet"); /* at least two arguments please */ if (argc < 2) goto usage; + if (quiet_str) + quiet = simple_strtoul(quiet_str, NULL, 0) != 0; + cmd = argv[1]; if (strcmp(cmd, "info") == 0) { @@ -178,7 +183,10 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 && strncmp(cmd, "dump", 4) != 0 && - strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0) + strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 && + strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 && + strcmp(cmd, "biterr") != 0 && + strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 ) goto usage; /* the following commands operate on the current device */ @@ -197,14 +205,64 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; } - if (strcmp(cmd, "erase") == 0) { - arg_off_size(argc - 2, argv + 2, &off, &size, nand->size); - if (off == 0 && size == 0) - return 1; + if (strcmp(cmd, "erase") == 0 || strcmp(cmd, "scrub") == 0) { + nand_erase_options_t opts; + int clean = argc >= 3 && !strcmp("clean", argv[2]); + int rest_argc = argc - 2; + char **rest_argv = argv + 2; + int scrub = !strcmp(cmd, "scrub"); + + if (clean) { + rest_argc--; + rest_argv++; + } + + if (rest_argc == 0) { - printf("\nNAND erase: device %d offset 0x%x, size 0x%x ", - nand_curr_device, off, size); - ret = nand_erase(nand, off, size); + printf("\nNAND %s: device %d whole chip\n", + cmd, + nand_curr_device); + + off = size = 0; + } else { + arg_off_size(rest_argc, rest_argv, &off, &size, + nand->size); + + if (off == 0 && size == 0) + return 1; + + printf("\nNAND %s: device %d offset 0x%x, size 0x%x\n", + cmd, nand_curr_device, off, size); + } + + memset(&opts, 0, sizeof(opts)); + opts.offset = off; + opts.length = size; + opts.jffs2 = clean; + opts.quiet = quiet; + + if (scrub) { + printf("Warning: " + "scrub option will erase all factory set " + "bad blocks!\n" + " " + "There is no reliable way to recover them.\n" + " " + "Use this command only for testing purposes " + "if you\n" + " " + "are shure of what you are doing!\n" + "\nReally scrub this NAND flash? \n" + ); + + if (getc() == 'y' && getc() == '\r') { + opts.scrub = 1; + } else { + printf("scrub aborted\n"); + return -1; + } + } + ret = nand_erase_opts(nand, &opts); printf("%s\n", ret ? "ERROR" : "OK"); return ret == 0 ? 0 : 1; @@ -228,37 +286,153 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* read write */ if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) { + int read; + if (argc < 4) goto usage; -/* - s = strchr(cmd, '.'); - clean = CLEAN_NONE; - if (s != NULL) { - if (strcmp(s, ".jffs2") == 0 || strcmp(s, ".e") == 0 - || strcmp(s, ".i")) - clean = CLEAN_JFFS2; - } -*/ + addr = (ulong)simple_strtoul(argv[2], NULL, 16); arg_off_size(argc - 3, argv + 3, &off, &size, nand->size); if (off == 0 && size == 0) return 1; - i = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */ + read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */ printf("\nNAND %s: device %d offset %u, size %u ... ", - i ? "read" : "write", nand_curr_device, off, size); + read ? "read" : "write", nand_curr_device, off, size); - if (i) + s = strchr(cmd, '.'); + if (s != NULL && + (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i"))) { + if (read) { + /* read */ + nand_read_options_t opts; + memset(&opts, 0, sizeof(opts)); + opts.buffer = (u_char*) addr; + opts.length = size; + opts.offset = off; + opts.quiet = quiet; + ret = nand_read_opts(nand, &opts); + } else { + /* write */ + nand_write_options_t opts; + memset(&opts, 0, sizeof(opts)); + opts.buffer = (u_char*) addr; + opts.length = size; + opts.offset = off; + /* opts.forcejffs2 = 1; */ + opts.pad = 1; + opts.blockalign = 1; + opts.quiet = quiet; + ret = nand_write_opts(nand, &opts); + } + printf("%s\n", ret ? "ERROR" : "OK"); + return ret == 0 ? 0 : 1; + } + + if (read) ret = nand_read(nand, off, &size, (u_char *)addr); else ret = nand_write(nand, off, &size, (u_char *)addr); printf(" %d bytes %s: %s\n", size, - i ? "read" : "written", ret ? "ERROR" : "OK"); + read ? "read" : "written", ret ? "ERROR" : "OK"); return ret == 0 ? 0 : 1; } + + /* 2006-09-28 gc: implement missing commands */ + if (strcmp(cmd, "markbad") == 0) { + addr = (ulong)simple_strtoul(argv[2], NULL, 16); + + int ret = nand->block_markbad(nand, addr); + if (ret == 0) { + printf("block 0x%08lx successfully marked as bad\n", + (ulong) addr); + return 0; + } else { + printf("block 0x%08lx NOT marked as bad! ERROR %d\n", + (ulong) addr, ret); + } + return 1; + } + if (strcmp(cmd, "biterr") == 0) { + /* todo */ + return 1; + } + + if (strcmp(cmd, "lock") == 0) { + int tight = 0; + int status = 0; + if (argc == 3) { + if (!strcmp("tight", argv[2])) + tight = 1; + if (!strcmp("status", argv[2])) + status = 1; + } + + if (status) { + ulong block_start = 0; + ulong off; + int last_status = -1; + + struct nand_chip *nand_chip = nand->priv; + /* check the WP bit */ + nand_chip->cmdfunc (nand, NAND_CMD_STATUS, -1, -1); + printf("device is %swrite protected\n", + (nand_chip->read_byte(nand) & 0x80 ? + "NOT " : "" ) ); + + for (off = 0; off < nand->size; off += nand->oobblock) { + int s = nand_get_lock_status(nand, off); + + /* print message only if status has changed + * or at end of chip + */ + if (off == nand->size - nand->oobblock + || (s != last_status && off != 0)) { + + printf("%08x - %08x: %8d pages %s%s%s\n", + block_start, + off-1, + (off-block_start)/nand->oobblock, + ((last_status & NAND_LOCK_STATUS_TIGHT) ? "TIGHT " : ""), + ((last_status & NAND_LOCK_STATUS_LOCK) ? "LOCK " : ""), + ((last_status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : "")); + } + + last_status = s; + } + } else { + if (!nand_lock(nand, tight)) { + printf ("NAND flash successfully locked\n"); + } else { + printf ("Error locking NAND flash. \n"); + return 1; + } + } + return 0; + } + + if (strcmp(cmd, "unlock") == 0) { + if (argc == 2) { + off = 0; + size = nand->size; + } else { + arg_off_size(argc - 2, argv + 2, &off, &size, + nand->size); + } + + if (!nand_unlock(nand, off, size)) { + printf("NAND flash successfully unlocked\n"); + } else { + printf("Error unlocking NAND flash. " + "Write and erase will probably fail\n"); + return 1; + } + return 0; + } + usage: printf("Usage:\n%s\n", cmdtp->usage); return 1; @@ -277,7 +451,9 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "nand dump[.oob] off - dump page\n" "nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n" "nand markbad off - mark bad block at offset (UNSAFE)\n" - "nand biterr off - make a bit error at offset (UNSAFE)\n"); + "nand biterr off - make a bit error at offset (UNSAFE)\n" + "nand lock [tight] [status] - bring nand to lock state or display locked pages\n" + "nand unlock [offset] [size] - unlock section\n"); int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { @@ -596,7 +772,7 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } - printf ("\nNAND %s: device %d offset %ld, size %ld ... ", + printf ("\nNAND %s: device %d offset %ld, size %ld ...\n", (cmd & NANDRW_READ) ? "read" : "write", curr_device, off, size); @@ -615,7 +791,7 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong size = simple_strtoul(argv[3 + clean], NULL, 16); int ret; - printf ("\nNAND erase: device %d offset %ld, size %ld ... ", + printf ("\nNAND erase: device %d offset %ld, size %ld ...\n", curr_device, off, size); ret = nand_legacy_erase (nand_dev_desc + curr_device, @@ -635,7 +811,7 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( nand, 5, 1, do_nand, - "nand - NAND sub-system\n", + "nand - legacy NAND sub-system\n", "info - show available NAND devices\n" "nand device [dev] - show or set current device\n" "nand read[.jffs2[s]] addr off size\n" diff --git a/doc/README.nand b/doc/README.nand index f2d6a5b1e65..2b9a52966c5 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -207,3 +207,47 @@ As mentioned above, the legacy code is still used by the DoC subsystem. The consequence of this is that the legacy NAND can't be removed from the tree until the DoC is ported to use the new NAND support (or boards with DoC will break). + + + +Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006 + +JFFS2 related commands: + + implement "nand erase clean" and old "nand erase" + using both the new code which is able to skip bad blocks + "nand erase clean" additionally writes JFFS2-cleanmarkers in the oob. + + "nand write.jffs2" + like "nand write" but skip found bad eraseblocks + + "nand read.jffs2" + like "nand read" but skip found bad eraseblocks + +Miscellaneous and testing commands: + "markbad [offset]" + create an artificial bad block (for testing bad block handling) + + "scrub [offset length]" + like "erase" but don't skip bad block. Instead erase them. + DANGEROUS!!! Factory set bad blocks will be lost. Use only + to remove artificial bad blocks created with the "markbad" command. + + +NAND locking command (for chips with active LOCKPRE pin) + + "nand lock" + set NAND chip to lock state (all pages locked) + + "nand lock tight" + set NAND chip to lock tight state (software can't change locking anymore) + + "nand lock status" + displays current locking status of all pages + + "nand unlock [offset] [size]" + unlock consecutive area (can be called multiple times for different areas) + + +I have tested the code with board containing 128MiB NAND large page chips +and 32MiB small page chips. diff --git a/drivers/nand/Makefile b/drivers/nand/Makefile index b03604dc4e9..fb0185b991b 100644 --- a/drivers/nand/Makefile +++ b/drivers/nand/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libnand.a -COBJS := nand.o nand_base.o nand_ids.o nand_ecc.o nand_bbt.o +COBJS := nand.o nand_base.o nand_ids.o nand_ecc.o nand_bbt.o nand_util.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c new file mode 100644 index 00000000000..5a8e58a741c --- /dev/null +++ b/drivers/nand/nand_util.c @@ -0,0 +1,869 @@ +/* + * drivers/nand/nand_util.c + * + * Copyright (C) 2006 by Weiss-Electronic GmbH. + * All rights reserved. + * + * @author: Guido Classen + * @descr: NAND Flash support + * @references: borrowed heavily from Linux mtd-utils code: + * flash_eraseall.c by Arcom Control System Ltd + * nandwrite.c by Steven J. Hill (sjhill@realitydiluted.com) + * and Thomas Gleixner (tglx@linutronix.de) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include +#include +#include + +#include +#include + +typedef struct erase_info erase_info_t; +typedef struct mtd_info mtd_info_t; + +/* support only for native endian JFFS2 */ +#define cpu_to_je16(x) (x) +#define cpu_to_je32(x) (x) + +/*****************************************************************************/ +static int nand_block_bad_scrub(struct mtd_info *mtd, loff_t ofs, int getchip) +{ + return 0; +} + +/** + * nand_erase_opts: - erase NAND flash with support for various options + * (jffs2 formating) + * + * @param meminfo NAND device to erase + * @param opts options, @see struct nand_erase_options + * @return 0 in case of success + * + * This code is ported from flash_eraseall.c from Linux mtd utils by + * Arcom Control System Ltd. + */ +int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) +{ + struct jffs2_unknown_node cleanmarker; + int clmpos = 0; + int clmlen = 8; + erase_info_t erase; + ulong erase_length; + int isNAND; + int bbtest = 1; + int result; + int percent_complete = -1; + int (*nand_block_bad_old)(struct mtd_info *, loff_t, int) = NULL; + const char *mtd_device = meminfo->name; + + memset(&erase, 0, sizeof(erase)); + + erase.mtd = meminfo; + erase.len = meminfo->erasesize; + if (opts->offset == 0 && opts->length == 0) { + /* erase complete chip */ + erase.addr = 0; + erase_length = meminfo->size; + } else { + /* erase specified region */ + erase.addr = opts->offset; + erase_length = opts->length; + } + + isNAND = meminfo->type == MTD_NANDFLASH ? 1 : 0; + + if (opts->jffs2) { + cleanmarker.magic = cpu_to_je16 (JFFS2_MAGIC_BITMASK); + cleanmarker.nodetype = cpu_to_je16 (JFFS2_NODETYPE_CLEANMARKER); + if (isNAND) { + struct nand_oobinfo *oobinfo = &meminfo->oobinfo; + + /* check for autoplacement */ + if (oobinfo->useecc == MTD_NANDECC_AUTOPLACE) { + /* get the position of the free bytes */ + if (!oobinfo->oobfree[0][1]) { + printf(" Eeep. Autoplacement selected " + "and no empty space in oob\n"); + return -1; + } + clmpos = oobinfo->oobfree[0][0]; + clmlen = oobinfo->oobfree[0][1]; + if (clmlen > 8) + clmlen = 8; + } else { + /* legacy mode */ + switch (meminfo->oobsize) { + case 8: + clmpos = 6; + clmlen = 2; + break; + case 16: + clmpos = 8; + clmlen = 8; + break; + case 64: + clmpos = 16; + clmlen = 8; + break; + } + } + + cleanmarker.totlen = cpu_to_je32(8); + } else { + cleanmarker.totlen = + cpu_to_je32(sizeof(struct jffs2_unknown_node)); + } + cleanmarker.hdr_crc = cpu_to_je32( + crc32_no_comp(0, (unsigned char *) &cleanmarker, + sizeof(struct jffs2_unknown_node) - 4)); + } + + /* scrub option allows to erase badblock. To prevent internal + * check from erase() method, set block check method to dummy + * and disable bad block table while erasing. + */ + if (opts->scrub) { + struct nand_chip *priv_nand = meminfo->priv; + + nand_block_bad_old = priv_nand->block_bad; + priv_nand->block_bad = nand_block_bad_scrub; + /* we don't need the bad block table anymore... + * after scrub, there are no bad blocks left! + */ + if (priv_nand->bbt) { + kfree(priv_nand->bbt); + } + priv_nand->bbt = NULL; + } + + for (; + erase.addr < opts->offset + erase_length; + erase.addr += meminfo->erasesize) { + + WATCHDOG_RESET (); + + if (!opts->scrub && bbtest) { + int ret = meminfo->block_isbad(meminfo, erase.addr); + if (ret > 0) { + if (!opts->quiet) + printf("\rSkipping bad block at " + "0x%08x " + " \n", + erase.addr); + continue; + + } else if (ret < 0) { + printf("\n%s: MTD get bad block failed: %d\n", + mtd_device, + ret); + return -1; + } + } + + result = meminfo->erase(meminfo, &erase); + if (result != 0) { + printf("\n%s: MTD Erase failure: %d\n", + mtd_device, result); + continue; + } + + /* format for JFFS2 ? */ + if (opts->jffs2) { + + /* write cleanmarker */ + if (isNAND) { + size_t written; + result = meminfo->write_oob(meminfo, + erase.addr + clmpos, + clmlen, + &written, + (unsigned char *) + &cleanmarker); + if (result != 0) { + printf("\n%s: MTD writeoob failure: %d\n", + mtd_device, result); + continue; + } + } else { + printf("\n%s: this erase routine only supports" + " NAND devices!\n", + mtd_device); + } + } + + if (!opts->quiet) { + int percent = (int) + ((unsigned long long) + (erase.addr+meminfo->erasesize-opts->offset) + * 100 / erase_length); + + /* output progress message only at whole percent + * steps to reduce the number of messages printed + * on (slow) serial consoles + */ + if (percent != percent_complete) { + percent_complete = percent; + + printf("\rErasing at 0x%x -- %3d%% complete.", + erase.addr, percent); + + if (opts->jffs2 && result == 0) + printf(" Cleanmarker written at 0x%x.", + erase.addr); + } + } + } + if (!opts->quiet) + printf("\n"); + + if (nand_block_bad_old) { + struct nand_chip *priv_nand = meminfo->priv; + + priv_nand->block_bad = nand_block_bad_old; + priv_nand->scan_bbt(meminfo); + } + + return 0; +} + +#define MAX_PAGE_SIZE 2048 +#define MAX_OOB_SIZE 64 + +/* + * buffer array used for writing data + */ +static unsigned char data_buf[MAX_PAGE_SIZE]; +static unsigned char oob_buf[MAX_OOB_SIZE]; + +/* OOB layouts to pass into the kernel as default */ +static struct nand_oobinfo none_oobinfo = { + .useecc = MTD_NANDECC_OFF, +}; + +static struct nand_oobinfo jffs2_oobinfo = { + .useecc = MTD_NANDECC_PLACE, + .eccbytes = 6, + .eccpos = { 0, 1, 2, 3, 6, 7 } +}; + +static struct nand_oobinfo yaffs_oobinfo = { + .useecc = MTD_NANDECC_PLACE, + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15} +}; + +static struct nand_oobinfo autoplace_oobinfo = { + .useecc = MTD_NANDECC_AUTOPLACE +}; + +/** + * nand_write_opts: - write image to NAND flash with support for various options + * + * @param meminfo NAND device to erase + * @param opts write options (@see nand_write_options) + * @return 0 in case of success + * + * This code is ported from nandwrite.c from Linux mtd utils by + * Steven J. Hill and Thomas Gleixner. + */ +int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts) +{ + int imglen = 0; + int pagelen; + int baderaseblock; + int blockstart = -1; + loff_t offs; + int readlen; + int oobinfochanged = 0; + int percent_complete = -1; + struct nand_oobinfo old_oobinfo; + ulong mtdoffset = opts->offset; + ulong erasesize_blockalign; + u_char *buffer = opts->buffer; + size_t written; + int result; + + if (opts->pad && opts->writeoob) { + printf("Can't pad when oob data is present.\n"); + return -1; + } + + /* set erasesize to specified number of blocks - to match + * jffs2 (virtual) block size */ + if (opts->blockalign == 0) { + erasesize_blockalign = meminfo->erasesize; + } else { + erasesize_blockalign = meminfo->erasesize * opts->blockalign; + } + + /* make sure device page sizes are valid */ + if (!(meminfo->oobsize == 16 && meminfo->oobblock == 512) + && !(meminfo->oobsize == 8 && meminfo->oobblock == 256) + && !(meminfo->oobsize == 64 && meminfo->oobblock == 2048)) { + printf("Unknown flash (not normal NAND)\n"); + return -1; + } + + /* read the current oob info */ + memcpy(&old_oobinfo, &meminfo->oobinfo, sizeof(old_oobinfo)); + + /* write without ecc? */ + if (opts->noecc) { + memcpy(&meminfo->oobinfo, &none_oobinfo, + sizeof(meminfo->oobinfo)); + oobinfochanged = 1; + } + + /* autoplace ECC? */ + if (opts->autoplace && (old_oobinfo.useecc != MTD_NANDECC_AUTOPLACE)) { + + memcpy(&meminfo->oobinfo, &autoplace_oobinfo, + sizeof(meminfo->oobinfo)); + oobinfochanged = 1; + } + + /* force OOB layout for jffs2 or yaffs? */ + if (opts->forcejffs2 || opts->forceyaffs) { + struct nand_oobinfo *oobsel = + opts->forcejffs2 ? &jffs2_oobinfo : &yaffs_oobinfo; + + if (meminfo->oobsize == 8) { + if (opts->forceyaffs) { + printf("YAFSS cannot operate on " + "256 Byte page size\n"); + goto restoreoob; + } + /* Adjust number of ecc bytes */ + jffs2_oobinfo.eccbytes = 3; + } + + memcpy(&meminfo->oobinfo, oobsel, sizeof(meminfo->oobinfo)); + } + + /* get image length */ + imglen = opts->length; + pagelen = meminfo->oobblock + + ((opts->writeoob != 0) ? meminfo->oobsize : 0); + + /* check, if file is pagealigned */ + if ((!opts->pad) && ((imglen % pagelen) != 0)) { + printf("Input block length is not page aligned\n"); + goto restoreoob; + } + + /* check, if length fits into device */ + if (((imglen / pagelen) * meminfo->oobblock) + > (meminfo->size - opts->offset)) { + printf("Image %d bytes, NAND page %d bytes, " + "OOB area %u bytes, device size %u bytes\n", + imglen, pagelen, meminfo->oobblock, meminfo->size); + printf("Input block does not fit into device\n"); + goto restoreoob; + } + + if (!opts->quiet) + printf("\n"); + + /* get data from input and write to the device */ + while (imglen && (mtdoffset < meminfo->size)) { + + WATCHDOG_RESET (); + + /* + * new eraseblock, check for bad block(s). Stay in the + * loop to be sure if the offset changes because of + * a bad block, that the next block that will be + * written to is also checked. Thus avoiding errors if + * the block(s) after the skipped block(s) is also bad + * (number of blocks depending on the blockalign + */ + while (blockstart != (mtdoffset & (~erasesize_blockalign+1))) { + blockstart = mtdoffset & (~erasesize_blockalign+1); + offs = blockstart; + baderaseblock = 0; + + /* check all the blocks in an erase block for + * bad blocks */ + do { + int ret = meminfo->block_isbad(meminfo, offs); + + if (ret < 0) { + printf("Bad block check failed\n"); + goto restoreoob; + } + if (ret == 1) { + baderaseblock = 1; + if (!opts->quiet) + printf("\rBad block at 0x%lx " + "in erase block from " + "0x%x will be skipped\n", + (long) offs, + blockstart); + } + + if (baderaseblock) { + mtdoffset = blockstart + + erasesize_blockalign; + } + offs += erasesize_blockalign + / opts->blockalign; + } while (offs < blockstart + erasesize_blockalign); + } + + readlen = meminfo->oobblock; + if (opts->pad && (imglen < readlen)) { + readlen = imglen; + memset(data_buf + readlen, 0xff, + meminfo->oobblock - readlen); + } + + /* read page data from input memory buffer */ + memcpy(data_buf, buffer, readlen); + buffer += readlen; + + if (opts->writeoob) { + /* read OOB data from input memory block, exit + * on failure */ + memcpy(oob_buf, buffer, meminfo->oobsize); + buffer += meminfo->oobsize; + + /* write OOB data first, as ecc will be placed + * in there*/ + result = meminfo->write_oob(meminfo, + mtdoffset, + meminfo->oobsize, + &written, + (unsigned char *) + &oob_buf); + + if (result != 0) { + printf("\nMTD writeoob failure: %d\n", + result); + goto restoreoob; + } + imglen -= meminfo->oobsize; + } + + /* write out the page data */ + result = meminfo->write(meminfo, + mtdoffset, + meminfo->oobblock, + &written, + (unsigned char *) &data_buf); + + if (result != 0) { + printf("writing NAND page at offset 0x%lx failed\n", + mtdoffset); + goto restoreoob; + } + imglen -= readlen; + + if (!opts->quiet) { + int percent = (int) + ((unsigned long long) + (opts->length-imglen) * 100 + / opts->length); + /* output progress message only at whole percent + * steps to reduce the number of messages printed + * on (slow) serial consoles + */ + if (percent != percent_complete) { + printf("\rWriting data at 0x%x " + "-- %3d%% complete.", + mtdoffset, percent); + percent_complete = percent; + } + } + + mtdoffset += meminfo->oobblock; + } + + if (!opts->quiet) + printf("\n"); + +restoreoob: + if (oobinfochanged) { + memcpy(&meminfo->oobinfo, &old_oobinfo, + sizeof(meminfo->oobinfo)); + } + + if (imglen > 0) { + printf("Data did not fit into device, due to bad blocks\n"); + return -1; + } + + /* return happy */ + return 0; +} + +/** + * nand_read_opts: - read image from NAND flash with support for various options + * + * @param meminfo NAND device to erase + * @param opts read options (@see struct nand_read_options) + * @return 0 in case of success + * + */ +int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts) +{ + int imglen = opts->length; + int pagelen; + int baderaseblock; + int blockstart = -1; + int percent_complete = -1; + loff_t offs; + size_t readlen; + ulong mtdoffset = opts->offset; + u_char *buffer = opts->buffer; + int result; + + /* make sure device page sizes are valid */ + if (!(meminfo->oobsize == 16 && meminfo->oobblock == 512) + && !(meminfo->oobsize == 8 && meminfo->oobblock == 256) + && !(meminfo->oobsize == 64 && meminfo->oobblock == 2048)) { + printf("Unknown flash (not normal NAND)\n"); + return -1; + } + + pagelen = meminfo->oobblock + + ((opts->readoob != 0) ? meminfo->oobsize : 0); + + /* check, if length is not larger than device */ + if (((imglen / pagelen) * meminfo->oobblock) + > (meminfo->size - opts->offset)) { + printf("Image %d bytes, NAND page %d bytes, " + "OOB area %u bytes, device size %u bytes\n", + imglen, pagelen, meminfo->oobblock, meminfo->size); + printf("Input block is larger than device\n"); + return -1; + } + + if (!opts->quiet) + printf("\n"); + + /* get data from input and write to the device */ + while (imglen && (mtdoffset < meminfo->size)) { + + WATCHDOG_RESET (); + + /* + * new eraseblock, check for bad block(s). Stay in the + * loop to be sure if the offset changes because of + * a bad block, that the next block that will be + * written to is also checked. Thus avoiding errors if + * the block(s) after the skipped block(s) is also bad + * (number of blocks depending on the blockalign + */ + while (blockstart != (mtdoffset & (~meminfo->erasesize+1))) { + blockstart = mtdoffset & (~meminfo->erasesize+1); + offs = blockstart; + baderaseblock = 0; + + /* check all the blocks in an erase block for + * bad blocks */ + do { + int ret = meminfo->block_isbad(meminfo, offs); + + if (ret < 0) { + printf("Bad block check failed\n"); + return -1; + } + if (ret == 1) { + baderaseblock = 1; + if (!opts->quiet) + printf("\rBad block at 0x%lx " + "in erase block from " + "0x%x will be skipped\n", + (long) offs, + blockstart); + } + + if (baderaseblock) { + mtdoffset = blockstart + + meminfo->erasesize; + } + offs += meminfo->erasesize; + + } while (offs < blockstart + meminfo->erasesize); + } + + + /* read page data to memory buffer */ + result = meminfo->read(meminfo, + mtdoffset, + meminfo->oobblock, + &readlen, + (unsigned char *) &data_buf); + + if (result != 0) { + printf("reading NAND page at offset 0x%lx failed\n", + mtdoffset); + return -1; + } + + if (imglen < readlen) { + readlen = imglen; + } + + memcpy(buffer, data_buf, readlen); + buffer += readlen; + imglen -= readlen; + + if (opts->readoob) { + result = meminfo->read_oob(meminfo, + mtdoffset, + meminfo->oobsize, + &readlen, + (unsigned char *) + &oob_buf); + + if (result != 0) { + printf("\nMTD readoob failure: %d\n", + result); + return -1; + } + + + if (imglen < readlen) { + readlen = imglen; + } + + memcpy(buffer, oob_buf, readlen); + + buffer += readlen; + imglen -= readlen; + } + + if (!opts->quiet) { + int percent = (int) + ((unsigned long long) + (opts->length-imglen) * 100 + / opts->length); + /* output progress message only at whole percent + * steps to reduce the number of messages printed + * on (slow) serial consoles + */ + if (percent != percent_complete) { + if (!opts->quiet) + printf("\rReading data from 0x%x " + "-- %3d%% complete.", + mtdoffset, percent); + percent_complete = percent; + } + } + + mtdoffset += meminfo->oobblock; + } + + if (!opts->quiet) + printf("\n"); + + if (imglen > 0) { + printf("Could not read entire image due to bad blocks\n"); + return -1; + } + + /* return happy */ + return 0; +} + +/****************************************************************************** + * Support for locking / unlocking operations of some NAND devices + *****************************************************************************/ + +#define NAND_CMD_LOCK 0x2a +#define NAND_CMD_LOCK_TIGHT 0x2c +#define NAND_CMD_UNLOCK1 0x23 +#define NAND_CMD_UNLOCK2 0x24 +#define NAND_CMD_LOCK_STATUS 0x7a + +/** + * nand_lock: Set all pages of NAND flash chip to the LOCK or LOCK-TIGHT + * state + * + * @param meminfo nand mtd instance + * @param tight bring device in lock tight mode + * + * @return 0 on success, -1 in case of error + * + * The lock / lock-tight command only applies to the whole chip. To get some + * parts of the chip lock and others unlocked use the following sequence: + * + * - Lock all pages of the chip using nand_lock(mtd, 0) (or the lockpre pin) + * - Call nand_unlock() once for each consecutive area to be unlocked + * - If desired: Bring the chip to the lock-tight state using nand_lock(mtd, 1) + * + * If the device is in lock-tight state software can't change the + * current active lock/unlock state of all pages. nand_lock() / nand_unlock() + * calls will fail. It is only posible to leave lock-tight state by + * an hardware signal (low pulse on _WP pin) or by power down. + */ +int nand_lock(nand_info_t *meminfo, int tight) +{ + int ret = 0; + int status; + struct nand_chip *this = meminfo->priv; + + /* select the NAND device */ + this->select_chip(meminfo, 0); + + this->cmdfunc(meminfo, + (tight ? NAND_CMD_LOCK_TIGHT : NAND_CMD_LOCK), + -1, -1); + + /* call wait ready function */ + status = this->waitfunc(meminfo, this, FL_WRITING); + + /* see if device thinks it succeeded */ + if (status & 0x01) { + ret = -1; + } + + /* de-select the NAND device */ + this->select_chip(meminfo, -1); + return ret; +} + +/** + * nand_get_lock_status: - query current lock state from one page of NAND + * flash + * + * @param meminfo nand mtd instance + * @param offset page address to query (muss be page aligned!) + * + * @return -1 in case of error + * >0 lock status: + * bitfield with the following combinations: + * NAND_LOCK_STATUS_TIGHT: page in tight state + * NAND_LOCK_STATUS_LOCK: page locked + * NAND_LOCK_STATUS_UNLOCK: page unlocked + * + */ +int nand_get_lock_status(nand_info_t *meminfo, ulong offset) +{ + int ret = 0; + int chipnr; + int page; + struct nand_chip *this = meminfo->priv; + + /* select the NAND device */ + chipnr = (int)(offset >> this->chip_shift); + this->select_chip(meminfo, chipnr); + + + if ((offset & (meminfo->oobblock - 1)) != 0) { + printf ("nand_get_lock_status: " + "Start address must be beginning of " + "nand page!\n"); + ret = -1; + goto out; + } + + /* check the Lock Status */ + page = (int)(offset >> this->page_shift); + this->cmdfunc(meminfo, NAND_CMD_LOCK_STATUS, -1, page & this->pagemask); + + ret = this->read_byte(meminfo) & (NAND_LOCK_STATUS_TIGHT + | NAND_LOCK_STATUS_LOCK + | NAND_LOCK_STATUS_UNLOCK); + + out: + /* de-select the NAND device */ + this->select_chip(meminfo, -1); + return ret; +} + +/** + * nand_unlock: - Unlock area of NAND pages + * only one consecutive area can be unlocked at one time! + * + * @param meminfo nand mtd instance + * @param start start byte address + * @param length number of bytes to unlock (must be a multiple of + * page size nand->oobblock) + * + * @return 0 on success, -1 in case of error + */ +int nand_unlock(nand_info_t *meminfo, ulong start, ulong length) +{ + int ret = 0; + int chipnr; + int status; + int page; + struct nand_chip *this = meminfo->priv; + printf ("nand_unlock: start: %08x, length: %d!\n", + (int)start, (int)length); + + /* select the NAND device */ + chipnr = (int)(start >> this->chip_shift); + this->select_chip(meminfo, chipnr); + + /* check the WP bit */ + this->cmdfunc(meminfo, NAND_CMD_STATUS, -1, -1); + if ((this->read_byte(meminfo) & 0x80) == 0) { + printf ("nand_unlock: Device is write protected!\n"); + ret = -1; + goto out; + } + + if ((start & (meminfo->oobblock - 1)) != 0) { + printf ("nand_unlock: Start address must be beginning of " + "nand page!\n"); + ret = -1; + goto out; + } + + if (length == 0 || (length & (meminfo->oobblock - 1)) != 0) { + printf ("nand_unlock: Length must be a multiple of nand page " + "size!\n"); + ret = -1; + goto out; + } + + /* submit address of first page to unlock */ + page = (int)(start >> this->page_shift); + this->cmdfunc(meminfo, NAND_CMD_UNLOCK1, -1, page & this->pagemask); + + /* submit ADDRESS of LAST page to unlock */ + page += (int)(length >> this->page_shift) - 1; + this->cmdfunc(meminfo, NAND_CMD_UNLOCK2, -1, page & this->pagemask); + + /* call wait ready function */ + status = this->waitfunc(meminfo, this, FL_WRITING); + /* see if device thinks it succeeded */ + if (status & 0x01) { + /* there was an error */ + ret = -1; + goto out; + } + + out: + /* de-select the NAND device */ + this->select_chip(meminfo, -1); + return ret; +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) */ diff --git a/include/nand.h b/include/nand.h index 905115b3dac..5c7311fd505 100644 --- a/include/nand.h +++ b/include/nand.h @@ -60,4 +60,61 @@ static inline int nand_erase(nand_info_t *info, ulong off, ulong size) return info->erase(info, &instr); } + +/***************************************************************************** + * declarations from nand_util.c + ****************************************************************************/ + +struct nand_write_options { + u_char *buffer; /* memory block containing image to write */ + ulong length; /* number of bytes to write */ + ulong offset; /* start address in NAND */ + int quiet; /* don't display progress messages */ + int autoplace; /* if true use auto oob layout */ + int forcejffs2; /* force jffs2 oob layout */ + int forceyaffs; /* force yaffs oob layout */ + int noecc; /* write without ecc */ + int writeoob; /* image contains oob data */ + int pad; /* pad to page size */ + int blockalign; /* 1|2|4 set multiple of eraseblocks + * to align to */ +}; + +typedef struct nand_write_options nand_write_options_t; + +struct nand_read_options { + u_char *buffer; /* memory block in which read image is written*/ + ulong length; /* number of bytes to read */ + ulong offset; /* start address in NAND */ + int quiet; /* don't display progress messages */ + int readoob; /* put oob data in image */ +}; + +typedef struct nand_read_options nand_read_options_t; + +struct nand_erase_options { + ulong length; /* number of bytes to erase */ + ulong offset; /* first address in NAND to erase */ + int quiet; /* don't display progress messages */ + int jffs2; /* if true: format for jffs2 usage + * (write appropriate cleanmarker blocks) */ + int scrub; /* if true, really clean NAND by erasing + * bad blocks (UNSAFE) */ +}; + +typedef struct nand_erase_options nand_erase_options_t; + +int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts); + +int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts); +int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); + +#define NAND_LOCK_STATUS_TIGHT 0x01 +#define NAND_LOCK_STATUS_LOCK 0x02 +#define NAND_LOCK_STATUS_UNLOCK 0x04 + +int nand_lock( nand_info_t *meminfo, int tight ); +int nand_unlock( nand_info_t *meminfo, ulong start, ulong length ); +int nand_get_lock_status(nand_info_t *meminfo, ulong offset); + #endif diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c index 50ca4ffd380..82834135022 100644 --- a/lib_generic/crc32.c +++ b/lib_generic/crc32.c @@ -171,7 +171,9 @@ uLong ZEXPORT crc32(crc, buf, len) return crc ^ 0xffffffffL; } -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) \ + || (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + /* No ones complement version. JFFS2 (and other things ?) * don't use ones compliment in their CRC calculations. -- cgit v1.3.1 From 8b283dbb3a08d1b8d406bc15f119e081b3e2606a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Oct 2006 17:16:04 -0500 Subject: Fix whitespace issues. --- include/asm-ppc/immap_86xx.h | 466 +++++++++++++++++++++--------------------- include/configs/MPC8641HPCN.h | 9 - 2 files changed, 233 insertions(+), 242 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 5b1f0f4ea6c..685fcafdf2f 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -59,29 +59,29 @@ typedef struct ccsr_local_mcm { char res22[20]; uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ char res23[4]; - uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ + uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ char res24[716]; uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */ char res25[4]; - uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ - char res26[4]; - uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */ - char res27[44]; - uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */ - uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */ - uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */ - uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */ - char res28[16]; - uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */ - uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */ - uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */ - char res29[3476]; + uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ + char res26[4]; + uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */ + char res27[44]; + uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */ + uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */ + uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */ + uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */ + char res28[16]; + uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */ + uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */ + uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */ + char res29[3476]; uint edr; /* 0x1e00 - MCM Error Detect Register */ char res30[4]; uint eer; /* 0x1e08 - MCM Error Enable Register */ uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */ uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */ - uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */ + uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */ char res31[488]; } ccsr_local_mcm_t; @@ -106,28 +106,28 @@ typedef struct ccsr_ddr { uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ - char res7[104]; - uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ + char res7[104]; + uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */ - uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ + uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ - uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ - uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ + uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ + uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ - uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ + uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ char res8[4]; uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ - char res9[12]; - uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ - uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ - uint init_addr; /* 0x2148 - DDR training initialzation address */ - uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ - char res10[2728]; - uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ - uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ + char res9[12]; + uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ + uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ + uint init_addr; /* 0x2148 - DDR training initialzation address */ + uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ + char res10[2728]; + uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ + uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ char res11[512]; uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ @@ -142,7 +142,7 @@ typedef struct ccsr_ddr { uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */ uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ - uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ + uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ char res14[164]; uint debug_1; /* 0x2f00 */ @@ -279,7 +279,7 @@ typedef struct ccsr_lbc { typedef struct ccsr_pex { uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */ uint cfg_data; /* 0x8004 - PEX Configuration Data Register */ - char res1[4]; + char res1[4]; uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */ char res2[16]; uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */ @@ -326,7 +326,7 @@ typedef struct ccsr_pex { uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */ char res16[12]; uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */ - char res17[4]; + char res17[4]; uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */ uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */ uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */ @@ -355,73 +355,73 @@ typedef struct ccsr_pex { /* Hyper Transport Register Block (0xA000-0xB000) */ typedef struct ccsr_ht { - uint hcfg_addr; /* 0xa000 - HT Configuration Address register */ - uint hcfg_data; /* 0xa004 - HT Configuration Data register */ + uint hcfg_addr; /* 0xa000 - HT Configuration Address register */ + uint hcfg_data; /* 0xa004 - HT Configuration Data register */ char res1[3064]; - uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */ + uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */ char res2[12]; - uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */ - char res3[12]; - uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */ - char res4[4]; - uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */ - char res5[4]; - uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */ - char res6[12]; - uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */ - char res7[4]; - uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */ - char res8[4]; - uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */ - char res9[12]; - uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */ - char res10[4]; - uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */ - char res11[4]; - uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */ - char res12[12]; - uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */ - char res13[4]; - uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */ - char res14[4]; - uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */ - char res15[236]; - uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */ - char res16[4]; - uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */ - char res17[4]; - uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */ - char res18[12]; - uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */ - char res19[4]; - uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */ - char res20[4]; - uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */ - char res21[12]; - uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */ - char res22[4]; - uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */ - char res23[4]; - uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */ - char res24[12]; - uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */ - char res25[4]; - uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */ - char res26[4]; - uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */ - char res27[12]; - uint hedr; /* 0xae00 - HT Error Detect register */ - char res28[4]; - uint heier; /* 0xae08 - HT Error Interrupt Enable register */ - char res29[4]; - uint hecdr; /* 0xae10 - HT Error Capture Disbale register */ - char res30[12]; - uint hecsr; /* 0xae20 - HT Error Capture Status register */ - char res31[4]; - uint hec0; /* 0xae28 - HT Error Capture 0 register */ - uint hec1; /* 0xae2c - HT Error Capture 1 register */ - uint hec2; /* 0xae30 - HT Error Capture 2 register */ - char res32[460]; + uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */ + char res3[12]; + uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */ + char res4[4]; + uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */ + char res5[4]; + uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */ + char res6[12]; + uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */ + char res7[4]; + uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */ + char res8[4]; + uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */ + char res9[12]; + uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */ + char res10[4]; + uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */ + char res11[4]; + uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */ + char res12[12]; + uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */ + char res13[4]; + uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */ + char res14[4]; + uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */ + char res15[236]; + uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */ + char res16[4]; + uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */ + char res17[4]; + uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */ + char res18[12]; + uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */ + char res19[4]; + uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */ + char res20[4]; + uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */ + char res21[12]; + uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */ + char res22[4]; + uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */ + char res23[4]; + uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */ + char res24[12]; + uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */ + char res25[4]; + uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */ + char res26[4]; + uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */ + char res27[12]; + uint hedr; /* 0xae00 - HT Error Detect register */ + char res28[4]; + uint heier; /* 0xae08 - HT Error Interrupt Enable register */ + char res29[4]; + uint hecdr; /* 0xae10 - HT Error Capture Disbale register */ + char res30[12]; + uint hecsr; /* 0xae20 - HT Error Capture Status register */ + char res31[4]; + uint hec0; /* 0xae28 - HT Error Capture 0 register */ + uint hec1; /* 0xae2c - HT Error Capture 1 register */ + uint hec2; /* 0xae30 - HT Error Capture 2 register */ + char res32[460]; } ccsr_ht_t; /* DMA Registers(0x2_1000-0x2_2000) */ @@ -505,14 +505,14 @@ typedef struct ccsr_dma { /* tsec1-4: 24000-28000 */ typedef struct ccsr_tsec { - uint id; /* 0x24000 - Controller ID Register */ + uint id; /* 0x24000 - Controller ID Register */ char res1[12]; uint ievent; /* 0x24010 - Interrupt Event Register */ uint imask; /* 0x24014 - Interrupt Mask Register */ uint edis; /* 0x24018 - Error Disabled Register */ char res2[4]; uint ecntrl; /* 0x24020 - Ethernet Control Register */ - char res2_1[4]; + char res2_1[4]; uint ptv; /* 0x24028 - Pause Time Value Register */ uint dmactrl; /* 0x2402c - DMA Control Register */ uint tbipa; /* 0x24030 - TBI PHY Address Register */ @@ -521,102 +521,102 @@ typedef struct ccsr_tsec { char res4[8]; uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */ uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */ - char res4_1[4]; - uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */ - uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */ + char res4_1[4]; + uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */ + uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */ char res5[84]; uint tctrl; /* 0x24100 - Transmit Control Register */ uint tstat; /* 0x24104 - Transmit Status Register */ - uint dfvlan; /* 0x24108 - Default VLAN control word */ - char res6[4]; - uint txic; /* 0x24110 - Transmit interrupt coalescing Register */ - uint tqueue; /* 0x24114 - Transmit Queue Control Register */ + uint dfvlan; /* 0x24108 - Default VLAN control word */ + char res6[4]; + uint txic; /* 0x24110 - Transmit interrupt coalescing Register */ + uint tqueue; /* 0x24114 - Transmit Queue Control Register */ char res7[40]; - uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */ - uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */ - char res8[52]; - uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */ - char res9[4]; - uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */ - char res10[4]; - uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */ - char res11[4]; - uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */ - char res12[4]; - uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */ - char res13[4]; - uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */ - char res14[4]; - uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */ - char res15[4]; - uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */ - char res16[4]; - uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */ - char res17[64]; + uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */ + uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */ + char res8[52]; + uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */ + char res9[4]; + uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */ + char res10[4]; + uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */ + char res11[4]; + uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */ + char res12[4]; + uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */ + char res13[4]; + uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */ + char res14[4]; + uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */ + char res15[4]; + uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */ + char res16[4]; + uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */ + char res17[64]; uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */ uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */ - char res18[4]; - uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */ - char res19[4]; - uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */ - char res20[4]; - uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */ - char res21[4]; - uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */ - char res22[4]; - uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */ - char res23[4]; - uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */ - char res24[4]; - uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */ - char res25[192]; + char res18[4]; + uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */ + char res19[4]; + uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */ + char res20[4]; + uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */ + char res21[4]; + uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */ + char res22[4]; + uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */ + char res23[4]; + uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */ + char res24[4]; + uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */ + char res25[192]; uint rctrl; /* 0x24300 - Receive Control Register */ uint rstat; /* 0x24304 - Receive Status Register */ char res26[8]; - uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */ - uint rqueue; /* 0x24314 - Receive queue control register */ + uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */ + uint rqueue; /* 0x24314 - Receive queue control register */ char res27[24]; - uint rbifx; /* 0x24330 - Receive bit field extract control Register */ - uint rqfar; /* 0x24334 - Receive queue filing table address Register */ - uint rqfcr; /* 0x24338 - Receive queue filing table control Register */ - uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ + uint rbifx; /* 0x24330 - Receive bit field extract control Register */ + uint rqfar; /* 0x24334 - Receive queue filing table address Register */ + uint rqfcr; /* 0x24338 - Receive queue filing table control Register */ + uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ char res28[56]; - uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */ - char res29[4]; - uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */ - char res30[4]; - uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */ - char res31[4]; - uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */ - char res32[4]; - uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */ - char res33[4]; - uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */ - char res34[4]; - uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */ - char res35[4]; - uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */ - char res36[4]; - uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */ - char res37[64]; + uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */ + char res29[4]; + uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */ + char res30[4]; + uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */ + char res31[4]; + uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */ + char res32[4]; + uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */ + char res33[4]; + uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */ + char res34[4]; + uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */ + char res35[4]; + uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */ + char res36[4]; + uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */ + char res37[64]; uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */ uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */ - char res38[4]; + char res38[4]; uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */ - char res39[4]; + char res39[4]; uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */ - char res40[4]; + char res40[4]; uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */ - char res41[4]; + char res41[4]; uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */ - char res42[4]; + char res42[4]; uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */ - char res43[4]; + char res43[4]; uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */ - char res44[4]; + char res44[4]; uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */ - char res45[192]; + char res45[192]; uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */ uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */ uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */ @@ -629,40 +629,40 @@ typedef struct ccsr_tsec { uint miimcon; /* 0x2452c - MII Management Control Register */ uint miimstat; /* 0x24530 - MII Management Status Register */ uint miimind; /* 0x24534 - MII Management Indicator Register */ - uint ifctrl; /* 0x24538 - Interface Contrl Register */ + uint ifctrl; /* 0x24538 - Interface Contrl Register */ uint ifstat; /* 0x2453c - Interface Status Register */ uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */ uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */ - uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */ - uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */ - uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */ - uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */ - uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */ - uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */ - uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */ - uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */ - uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */ - uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */ - uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */ - uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */ - uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */ - uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */ - uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */ - uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */ - uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */ - uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */ - uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */ - uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */ - uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */ - uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */ - uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */ - uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */ - uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */ - uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */ - uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */ - uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */ - uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */ - uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */ + uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */ + uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */ + uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */ + uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */ + uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */ + uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */ + uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */ + uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */ + uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */ + uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */ + uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */ + uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */ + uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */ + uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */ + uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */ + uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */ + uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */ + uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */ + uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */ + uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */ + uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */ + uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */ + uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */ + uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */ + uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */ + uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */ + uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */ + uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */ + uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */ + uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */ char res48[192]; uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */ uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */ @@ -712,7 +712,7 @@ typedef struct ccsr_tsec { uint car2; /* 0x24734 - Carry Register Two */ uint cam1; /* 0x24738 - Carry Mask Register One */ uint cam2; /* 0x2473c - Carry Mask Register Two */ - uint rrej; /* 0x24740 - Receive filer rejected packet counter */ + uint rrej; /* 0x24740 - Receive filer rejected packet counter */ char res50[188]; uint iaddr0; /* 0x24800 - Indivdual address register 0 */ uint iaddr1; /* 0x24804 - Indivdual address register 1 */ @@ -732,11 +732,11 @@ typedef struct ccsr_tsec { uint gaddr6; /* 0x24898 - Global address register 6 */ uint gaddr7; /* 0x2489c - Global address register 7 */ char res52[352]; - uint fifocfg; /* 0x24A00 - FIFO interface configuration register */ - char res53[500]; - uint attr; /* 0x24BF8 - DMA Attribute register */ - uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */ - char res54[1024]; + uint fifocfg; /* 0x24A00 - FIFO interface configuration register */ + char res53[500]; + uint attr; /* 0x24BF8 - DMA Attribute register */ + uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */ + char res54[1024]; } ccsr_tsec_t; /* PIC Registers(0x4_0000-0x6_1000) */ @@ -833,7 +833,7 @@ typedef struct ccsr_pic { char res45[12]; uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */ char res46[12]; - uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */ + uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */ char res47[12]; uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */ char res48[60]; @@ -1024,7 +1024,7 @@ typedef struct ccsr_pic { uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */ char res141[12]; uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */ - char res142[4108]; + char res142[4108]; uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */ char res143[12]; uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */ @@ -1109,7 +1109,7 @@ typedef struct ccsr_rio { uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */ uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */ uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */ - uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ + uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */ char res13[12]; uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */ @@ -1133,7 +1133,7 @@ typedef struct ccsr_rio { char res22[20]; uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */ char res23[4]; - uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ + uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ char res24[2716]; uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */ @@ -1282,13 +1282,13 @@ typedef struct ccsr_rio { uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */ uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */ uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */ - uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ + uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ char res57[100]; uint pwmr; /* 0xd34e0 - Port-Write Mode Register */ uint pwsr; /* 0xd34e4 - Port-Write Status Register */ uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */ uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */ - char res58[51984]; + char res58[51984]; } ccsr_rio_t; /* Global Utilities Register Block(0xe_0000-0xf_ffff) */ @@ -1313,7 +1313,7 @@ typedef struct ccsr_gur { char res6[12]; uint devdisr; /* 0xe0070 - Device disable control */ #define MPC86xx_DEVDISR_PCIEX1 0x80000000 -#define MPC86xx_DEVDISR_PCIEX2 0x40000000 +#define MPC86xx_DEVDISR_PCIEX2 0x40000000 char res7[12]; uint powmgtcsr; /* 0xe0080 - Power management status and control register */ char res8[12]; @@ -1327,11 +1327,11 @@ typedef struct ccsr_gur { uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ char res12[12]; uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ - int res13[57]; - uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ - int res14[6]; - uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ - char res15[61656]; + int res13[57]; + uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ + int res14[6]; + uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ + char res15[61656]; } ccsr_gur_t; typedef struct immap { @@ -1340,21 +1340,21 @@ typedef struct immap { ccsr_i2c_t im_i2c; ccsr_duart_t im_duart; ccsr_lbc_t im_lbc; - ccsr_ddr_t im_ddr2; - char res1[4096]; + ccsr_ddr_t im_ddr2; + char res1[4096]; ccsr_pex_t im_pex1; - ccsr_pex_t im_pex2; - ccsr_ht_t im_ht; - char res2[90112]; + ccsr_pex_t im_pex2; + ccsr_ht_t im_ht; + char res2[90112]; ccsr_dma_t im_dma; - char res3[8192]; + char res3[8192]; ccsr_tsec_t im_tsec1; ccsr_tsec_t im_tsec2; - ccsr_tsec_t im_tsec3; - ccsr_tsec_t im_tsec4; - char res4[98304]; + ccsr_tsec_t im_tsec3; + ccsr_tsec_t im_tsec4; + char res4[98304]; ccsr_pic_t im_pic; - char res5[389120]; + char res5[389120]; ccsr_rio_t im_rio; ccsr_gur_t im_gur; } immap_t; diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index c704d4659ab..6e883f73f80 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -85,7 +85,6 @@ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 - /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) @@ -94,7 +93,6 @@ #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - /* * DDR Setup */ @@ -317,7 +315,6 @@ #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ - #if defined(CONFIG_PCI) #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -353,7 +350,6 @@ #endif /* CONFIG_PCI */ - #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI @@ -384,7 +380,6 @@ #endif /* CONFIG_TSEC_ENET */ - /* * BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR @@ -462,9 +457,6 @@ #define CFG_IBAT7L 0x00000000 #define CFG_IBAT7U 0x00000000 - - - /* * Environment */ @@ -572,7 +564,6 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif - /* * Environment Configuration */ -- cgit v1.3.1 From 7376eb87aaa601f728f9b8e5e9cd2711a67f529e Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 11 Oct 2006 15:13:01 -0500 Subject: * Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock --- board/cds/mpc8541cds/mpc8541cds.c | 4 +--- board/cds/mpc8548cds/mpc8548cds.c | 2 -- board/cds/mpc8555cds/mpc8555cds.c | 2 -- board/mpc8540ads/mpc8540ads.c | 3 --- board/mpc8560ads/mpc8560ads.c | 2 -- board/pm854/pm854.c | 2 -- board/pm856/pm856.c | 2 -- board/stxgp3/stxgp3.c | 2 -- board/tqm85xx/tqm85xx.c | 2 -- common/cmd_bootm.c | 2 +- common/ft_build.c | 10 +++++----- cpu/mpc85xx/pci.c | 5 +++++ include/ft_build.h | 2 ++ include/pci.h | 3 +++ 14 files changed, 17 insertions(+), 26 deletions(-) (limited to 'include') diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index c2b3009fd2b..a42904cf735 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -497,8 +497,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller **hose); - - pci_mpc85xx_init(&hose); + pci_mpc85xx_init(hose); #endif } diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 6eedb4a2095..ab5835dbe31 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -322,8 +322,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller **hose); - pci_mpc85xx_init(&hose); #endif } diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index 012181c31d3..d980ea63102 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -497,8 +497,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(hose); #endif } diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c index fbcb397290a..914e51a7607 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/mpc8540ads/mpc8540ads.c @@ -33,7 +33,6 @@ #if defined(CONFIG_OF_FLAT_TREE) #include -extern void ft_cpu_setup(void *blob, bd_t *bd); #endif @@ -327,8 +326,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index f9d75e80510..c1572a35d3f 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -539,8 +539,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 94c492f7821..6ead1d06309 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -289,8 +289,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index 50447083708..a10075451e0 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -442,8 +442,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c index 2b3949cd7b3..a58c043b629 100644 --- a/board/stxgp3/stxgp3.c +++ b/board/stxgp3/stxgp3.c @@ -375,8 +375,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c index befe8b76c8b..9f03ec50f73 100644 --- a/board/tqm85xx/tqm85xx.c +++ b/board/tqm85xx/tqm85xx.c @@ -408,8 +408,6 @@ static struct pci_controller hose = { void pci_init_board (void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init (struct pci_controller *hose); - pci_mpc85xx_init (&hose); #endif /* CONFIG_PCI */ } diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 04bce762c86..b785b9ea4f6 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -623,7 +623,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, /* Look for a '-' which indicates to ignore the ramdisk argument */ if (argc >= 3 && strcmp(argv[2], "-") == 0) { debug ("Skipping initrd\n"); - data = 0; + len = data = 0; } else #endif diff --git a/common/ft_build.c b/common/ft_build.c index b5937e35f7a..c6a018de240 100644 --- a/common/ft_build.c +++ b/common/ft_build.c @@ -87,9 +87,9 @@ static int lookup_string(struct ft_cxt *cxt, const char *name) p = cxt->p; while (p < cxt->p_end) { - if (strcmp(p, name) == 0) + if (strcmp((char *)p, name) == 0) return p - cxt->p; - p += strlen(p) + 1; + p += strlen((char *)p) + 1; } return -1; @@ -143,9 +143,9 @@ void ft_init_cxt(struct ft_cxt *cxt, void *blob) cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY; } - cxt->p_start = (char*)bph + bph->off_dt_struct; - cxt->p_end = (char *)bph + bph->totalsize; - cxt->p = (char *)bph + bph->off_dt_strings; + cxt->p_start = (u8 *)bph + bph->off_dt_struct; + cxt->p_end = (u8 *)bph + bph->totalsize; + cxt->p = (u8 *)bph + bph->off_dt_strings; } /* add a reserver physical area to the rsvmap */ diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index cfb7dcdc895..84f839ae1e4 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -29,6 +29,9 @@ #include #include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif #if defined(CONFIG_PCI) @@ -42,7 +45,9 @@ pci_mpc85xx_init(struct pci_controller *board_hose) volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; volatile ccsr_pcix_t *pcix = &immap->im_pcix; +#ifdef CONFIG_MPC85XX_PCI2 volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2; +#endif volatile ccsr_gur_t *gur = &immap->im_gur; struct pci_controller * hose; diff --git a/include/ft_build.h b/include/ft_build.h index f5156879de3..89c689c0847 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -64,6 +64,8 @@ void *ft_get_prop(void *bphp, const char *propname, int *szp); #ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup(void *blob, bd_t *bd); +void ft_cpu_setup(void *blob, bd_t *bd); +void ft_pci_setup(void *blob, bd_t *bd); #endif #endif diff --git a/include/pci.h b/include/pci.h index e0e8783a7aa..cc216e17d4d 100644 --- a/include/pci.h +++ b/include/pci.h @@ -501,4 +501,7 @@ extern int pci_hose_config_device(struct pci_controller *hose, extern void pci_mpc824x_init (struct pci_controller *hose); #endif +#ifdef CONFIG_MPC85xx +extern void pci_mpc85xx_init (struct pci_controller *hose); +#endif #endif /* _PCI_H */ -- cgit v1.3.1 From 4707fb50cc9f815996be5f2e5a8660de852b2c37 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Fri, 13 Oct 2006 21:09:09 +0200 Subject: Preliminary patch adding support for the MarelV38B board. --- MAKEALL | 2 +- Makefile | 3 + board/v38b/Makefile | 50 +++++++ board/v38b/config.mk | 32 +++++ board/v38b/ethaddr.c | 254 ++++++++++++++++++++++++++++++++++ board/v38b/u-boot.lds | 122 ++++++++++++++++ board/v38b/v38b.c | 253 ++++++++++++++++++++++++++++++++++ cpu/mpc5xxx/fec.c | 2 +- include/common.h | 3 +- include/configs/V38B.h | 368 +++++++++++++++++++++++++++++++++++++++++++++++++ include/status_led.h | 9 ++ lib_ppc/board.c | 7 +- 12 files changed, 1100 insertions(+), 5 deletions(-) create mode 100644 board/v38b/Makefile create mode 100644 board/v38b/config.mk create mode 100644 board/v38b/ethaddr.c create mode 100644 board/v38b/u-boot.lds create mode 100644 board/v38b/v38b.c create mode 100644 include/configs/V38B.h (limited to 'include') diff --git a/MAKEALL b/MAKEALL index 2a334ffbf93..f761467ae6e 100755 --- a/MAKEALL +++ b/MAKEALL @@ -39,7 +39,7 @@ LIST_5xxx=" \ icecube_5100 icecube_5200 lite5200b mcc200 \ o2dnt pf5200 PM520 TB5200 \ Total5100 Total5200 Total5200_Rev2 TQM5200 \ - TQM5200_B TQM5200S \ + TQM5200_B TQM5200S v38b \ " ######################################################################### diff --git a/Makefile b/Makefile index ccf7f9f88fc..3924f6559a7 100644 --- a/Makefile +++ b/Makefile @@ -400,6 +400,9 @@ icecube_5100_config: unconfig } @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube +v38b_config: unconfig + @./mkconfig -a V38B ppc mpc5xxx v38b + inka4x0_config: unconfig @$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0 diff --git a/board/v38b/Makefile b/board/v38b/Makefile new file mode 100644 index 00000000000..304deaa4f21 --- /dev/null +++ b/board/v38b/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o ethaddr.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/v38b/config.mk b/board/v38b/config.mk new file mode 100644 index 00000000000..75577fcbec7 --- /dev/null +++ b/board/v38b/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MarelV38B board +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +TEXT_BASE = 0xFF000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c new file mode 100644 index 00000000000..105608051c7 --- /dev/null +++ b/board/v38b/ethaddr.c @@ -0,0 +1,254 @@ +/* + * + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define GPIO_ENABLE (MPC5XXX_WU_GPIO) + +/* Open Drain Emulation Register */ +#define GPIO_ODR (MPC5XXX_WU_GPIO + 0x04) + +/* Data Direction Register */ +#define GPIO_DDR (MPC5XXX_WU_GPIO + 0x08) + +/* Data Value Out Register */ +#define GPIO_DVOR (MPC5XXX_WU_GPIO + 0x0C) + +/* Interrupt Enable Register */ +#define GPIO_IER (MPC5XXX_WU_GPIO + 0x10) + +/* Individual Interrupt Enable Register */ +#define GPIO_IIER (MPC5XXX_WU_GPIO + 0x14) + +/* Interrupt Type Register */ +#define GPIO_ITR (MPC5XXX_WU_GPIO + 0x18) + +/* Master Enable Register */ +#define GPIO_MER (MPC5XXX_WU_GPIO + 0x1C) + +/* Data Input Value Register */ +#define GPIO_DIVR (MPC5XXX_WU_GPIO + 0x20) + +/* Status Register */ +#define GPIO_SR (MPC5XXX_WU_GPIO + 0x24) + +#define PSC6_0 0x10000000 +#define WKUP_7 0x80000000 + +/* For NS4 A/B board define WKUP_7, for V38B board PSC_6 */ +#define GPIO_PIN PSC6_0 + +#define NO_ERROR 0 +#define ERR_NO_NUMBER 1 +#define ERR_BAD_NUMBER 2 + +typedef volatile unsigned long GPIO_REG; +typedef GPIO_REG *GPIO_REG_PTR; + +static int is_high(void); +static int check_device(void); +static void io_out(int value); +static void io_input(void); +static void io_output(void); +static void init_gpio(void); +static void read_byte(unsigned char *data); +static void write_byte(unsigned char command); + +void read_2501_memory(unsigned char *psernum, unsigned char *perr); +void board_get_enetaddr(uchar *enetaddr); + +static int is_high() +{ + return (* ((vu_long *) GPIO_DIVR) & GPIO_PIN); +} + +static void io_out(int value) +{ + if (value) + *((vu_long *) GPIO_DVOR) |= GPIO_PIN; + else + *((vu_long *) GPIO_DVOR) &= ~GPIO_PIN; +} + +static void io_input() +{ + *((vu_long *) GPIO_DDR) &= ~GPIO_PIN; + udelay(3); /* allow input to settle */ +} + +static void io_output() +{ + *((vu_long *) GPIO_DDR) |= GPIO_PIN; +} + +static void init_gpio() +{ + *((vu_long *) GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */ +} + +void read_2501_memory(unsigned char *psernum, unsigned char *perr) +{ +#define NBYTES 28 + unsigned char crcval, i; + unsigned char buf[NBYTES]; + + *perr = 0; + crcval = 0; + + for (i=0; i> 1; + } +} + +static void read_byte(unsigned char *data) +{ + unsigned char i, rdat = 0; + + for (i=0; i<8; i++) { + /* read one bit from one-wire device */ + + /* 1 - 15 us low starts bit slot */ + io_out(0); + io_output(); + udelay(0); + + /* allow line to be pulled high */ + io_input(); + + /* delay 10 us */ + udelay(10); + + /* now sample input status */ + if (is_high()) + rdat = (rdat >> 1) | 0x80; + else + rdat = rdat >> 1; + + udelay(60); /* at least 60 us */ + } + /* copy the return value */ + *data = rdat; +} + +void board_get_enetaddr(uchar *enetaddr) +{ + unsigned char sn[6], err=NO_ERROR; + + init_gpio(); + + read_2501_memory(sn, &err); + + if (err == NO_ERROR) { + sprintf(enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x", + sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]); + printf("MAC address: %s\n", enetaddr); + setenv("ethaddr", enetaddr); + } + else { + sprintf(enetaddr, "00:01:02:03:04:05"); + printf("Error reading MAC address.\n"); + printf("Setting default to %s\n", enetaddr); + setenv("ethaddr", enetaddr); + } +} diff --git a/board/v38b/u-boot.lds b/board/v38b/u-boot.lds new file mode 100644 index 00000000000..6ec525691a1 --- /dev/null +++ b/board/v38b/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c new file mode 100644 index 00000000000..c56c6c84d27 --- /dev/null +++ b/board/v38b/v38b.c @@ -0,0 +1,253 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifndef CFG_RAMBOOT +static void sdram_start(int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif /* SDRAM_DDR */ + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif /* !CFG_RAMBOOT */ + + +long int initdram(int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; + uint svr, pvr; + +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif /* SDRAM_DDR */ + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else + dramsize = test2; + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) + dramsize = 0; + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + else + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + + /* find RAM size using SDRAM CS1 only */ + if (!dramsize) + sdram_start(0); + test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + if (!dramsize) { + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + } + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else + dramsize2 = test2; + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) + dramsize2 = 0; + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + else + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) + dramsize = (1 << (dramsize - 0x13)) << 20; + else + dramsize = 0; + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + else + dramsize2 = 0; + +#endif /* CFG_RAMBOOT */ + + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + + return dramsize + dramsize2; +} + + +int checkboard (void) +{ + puts("Board: MarelV38B\n"); + return 0; +} + + +int board_early_init_r(void) +{ + /* + * Now, when we are in RAM, enable flash write access for detection process. + * Note that CS_BOOT cannot be cleared when executing in flash. + */ + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ + return 0; +} + + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +#define GPIO_PSC1_4 0x01000000UL + +void init_ide_reset(void) +{ + debug("init_ide_reset\n"); + + /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; + /* Deassert reset */ + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; +} + + +void ide_set_reset(int idereset) +{ + debug("ide_reset(%d)\n", idereset); + + if (idereset) { + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + /* Make a delay. MPC5200 spec says 25 usec min */ + udelay(500000); + } else + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + + +void led_d4_on(void) +{ + /* TIMER7 as GPIO output low */ + *(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x24; +} + + +void led_d4_off(void) +{ + /* TIMER7 as GPIO output high */ + *(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x34; +} + + +void hw_watchdog_reset(void) +{ +/* TODO fill this in */ +} + diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c index 19737ce868d..37fe3e7153f 100644 --- a/cpu/mpc5xxx/fec.c +++ b/cpu/mpc5xxx/fec.c @@ -882,7 +882,7 @@ int mpc5xxx_fec_initialize(bd_t * bis) defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \ defined(CONFIG_MCC200) || defined(CONFIG_O2DNT) || \ defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \ - defined(CONFIG_TQM5200) + defined(CONFIG_TQM5200) || defined(CONFIG_V38B) # ifndef CONFIG_FEC_10MBIT fec->xcv_type = MII100; # else diff --git a/include/common.h b/include/common.h index bee2fb70224..e296e684a0d 100644 --- a/include/common.h +++ b/include/common.h @@ -313,7 +313,8 @@ void board_ether_init (void); #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || \ defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K) || \ - defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) + defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) || \ + defined(CONFIG_V38B) void board_get_enetaddr (uchar *addr); #endif diff --git a/include/configs/V38B.h b/include/configs/V38B.h new file mode 100644 index 00000000000..9b8fc699a90 --- /dev/null +++ b/include/configs/V38B.h @@ -0,0 +1,368 @@ +/* + * (C) Copyright 2003-2004 Wolfgang Denk, DENX Software Engineering, + * wd@denx.de. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if 0 +#define DEBUG 0xFFF +#endif + +#if 0 +#define DEBUG 0x01 +#endif + +/* + * High Level Configuration Options + * (easy to change) +*/ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ +#define CONFIG_V38B 1 /* ... on V38B board */ +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ +#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ +#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ + +#define CONFIG_NETCONSOLE 1 + +#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ + +#define CFG_XLB_PIPELINING 1 /* gives better performance */ + + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + + +/* + * DDR + */ +#define SDRAM_DDR 1 /* is DDR */ +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x704f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + + +/* + * PCI - no suport + */ +#undef CONFIG_PCI + +/* + * Partitions + */ +#define CONFIG_MAC_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 + +/* + * USB + */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_SDRAMi | \ + CFG_CMD_DATE | \ + CFG_CMD_USB | \ + CFG_CMD_FAT) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Boot low with 16 MB Flash + */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT16 1 + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "devno=5\0" \ + "hostname=V38B_$(devno)\0" \ + "ipaddr=10.100.99.$(devno)\0" \ + "netmask=255.255.0.0\0" \ + "serverip=10.100.10.90\0" \ + "gatewayip=10.100.254.254\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=mpc5200/uImage\0" \ + "bootcmd=run net_nfs\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off panic=1\0" \ + "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip;bootm $(kernel_addr) " \ + "$(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs " \ + "addip;bootm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#if defined(CONFIG_MPC5200) +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#endif +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 + +/* + * RTC configuration + */ +#define CFG_I2C_RTC_ADDR 0x51 + +/* + * Flash configuration - use CFI driver + */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII 1 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x90000404 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00047801 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +/* Status LED */ + +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ + +#define CFG_LED_BASE (0xf0000600 + 0x70) /* Timer 7 GPIO */ + +#ifndef __ASSEMBLY__ +/* LEDs */ +typedef unsigned int led_id_t; + +#define __led_toggle(_msk) \ + do { \ + *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \ + } while(0) + +#define __led_set(_msk, _st) \ + do { \ + if ((_st)) \ + *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \ + else \ + *((volatile long *) (CFG_LED_BASE)) |= (_msk); \ + } while(0) + +#define __led_init(_msk, st) \ + { \ + *((volatile long *) (CFG_LED_BASE)) |= 0x34; \ + } + +#endif + +#endif /* __CONFIG_H */ diff --git a/include/status_led.h b/include/status_led.h index a56883b9a5e..db4c60fe3f3 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -346,6 +346,15 @@ void status_led_set (int led, int state); #elif defined(CONFIG_NIOS2) /* XXX empty just to avoid the error */ /************************************************************************/ +#elif defined(CONFIG_V38B) + +# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */ +# define STATUS_LED_PERIOD (CFG_HZ / 2) +# define STATUS_LED_STATE STATUS_LED_BLINKING + +# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + #else # error Status LED configuration missing #endif diff --git a/lib_ppc/board.c b/lib_ppc/board.c index cf0e3fdf4b6..3e401bead02 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2004 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -805,7 +805,10 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif /* CFG_EXTBDINFO */ s = getenv ("ethaddr"); -#if defined (CONFIG_MBX) || defined (CONFIG_RPXCLASSIC) || defined(CONFIG_IAD210) +#if defined (CONFIG_MBX) || \ + defined (CONFIG_RPXCLASSIC) || \ + defined(CONFIG_IAD210) || \ + defined(CONFIG_V38B) if (s == NULL) board_get_enetaddr (bd->bi_enetaddr); else -- cgit v1.3.1 From 5f3249a0a168e446a4cc9669b2bce0bc456f0a09 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 13 Oct 2006 16:47:53 -0500 Subject: Fixed leading whitespace issues. Removed spurious LAWAR thing. Signed-off-by: Jon Loeliger --- include/asm-ppc/mmu.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 5c38ce1e786..914f28b4617 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -117,8 +117,8 @@ typedef struct _P601_BAT { */ typedef struct _pte { - unsigned long page_num:20; - unsigned long flags:12; /* Page flags (some unused bits) */ + unsigned long page_num:20; + unsigned long flags:12; /* Page flags (some unused bits) */ } pte; #define PD_SHIFT (10+12) /* Page directory */ @@ -448,7 +448,6 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 -#define LAWAR_TRGT_IF_HT 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 -- cgit v1.3.1 From fcfed4f2f234836a0b308fd0a782f4625cd40bad Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 18 Oct 2006 22:44:38 +0200 Subject: Coding Style cleanup. --- board/v38b/ethaddr.c | 4 +- board/v38b/v38b.c | 1 - doc/README.nand | 3 -- include/configs/V38B.h | 112 ++++++++++++++++++++++++------------------------- 4 files changed, 58 insertions(+), 62 deletions(-) (limited to 'include') diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c index 105608051c7..aaa629ef611 100644 --- a/board/v38b/ethaddr.c +++ b/board/v38b/ethaddr.c @@ -118,7 +118,7 @@ void read_2501_memory(unsigned char *psernum, unsigned char *perr) crcval = 0; for (i=0; i> 1) | 0x80; else rdat = rdat >> 1; - + udelay(60); /* at least 60 us */ } /* copy the return value */ diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c index c56c6c84d27..99fe7dbc3c4 100644 --- a/board/v38b/v38b.c +++ b/board/v38b/v38b.c @@ -250,4 +250,3 @@ void hw_watchdog_reset(void) { /* TODO fill this in */ } - diff --git a/doc/README.nand b/doc/README.nand index 2b9a52966c5..5279a4f2bc5 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -1,9 +1,7 @@ NAND FLASH commands and notes - See NOTE below!!! - # (C) Copyright 2003 # Dave Ellis, SIXNET, dge@sixnetio.com # @@ -209,7 +207,6 @@ the tree until the DoC is ported to use the new NAND support (or boards with DoC will break). - Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006 JFFS2 related commands: diff --git a/include/configs/V38B.h b/include/configs/V38B.h index 9b8fc699a90..8eea504742a 100644 --- a/include/configs/V38B.h +++ b/include/configs/V38B.h @@ -11,7 +11,7 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. * * You should have received a copy of the GNU General Public License along @@ -35,35 +35,35 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_V38B 1 /* ... on V38B board */ -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ +#define CONFIG_V38B 1 /* ... on V38B board */ +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ -#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ -#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ -#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ +#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ +#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ +#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ #define CONFIG_NETCONSOLE 1 -#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ -#define CFG_XLB_PIPELINING 1 /* gives better performance */ +#define CFG_XLB_PIPELINING 1 /* gives better performance */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /* * Serial console configuration */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } @@ -97,12 +97,12 @@ #define CONFIG_USB_OHCI #define CONFIG_USB_STORAGE -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ /* * Supported commands */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_FAT | \ CFG_CMD_I2C | \ CFG_CMD_IDE | \ @@ -112,7 +112,7 @@ CFG_CMD_IRQ | \ CFG_CMD_JFFS2 | \ CFG_CMD_MII | \ - CFG_CMD_SDRAMi | \ + CFG_CMD_SDRAMi | \ CFG_CMD_DATE | \ CFG_CMD_USB | \ CFG_CMD_FAT) @@ -123,7 +123,7 @@ /* * Boot low with 16 MB Flash */ -# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT 1 # define CFG_LOWBOOT16 1 /* @@ -131,35 +131,35 @@ */ #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -#define CONFIG_PREBOOT "echo;" \ +#define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "devno=5\0" \ - "hostname=V38B_$(devno)\0" \ - "ipaddr=10.100.99.$(devno)\0" \ - "netmask=255.255.0.0\0" \ - "serverip=10.100.10.90\0" \ - "gatewayip=10.100.254.254\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=mpc5200/uImage\0" \ - "bootcmd=run net_nfs\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;bootm $(kernel_addr) " \ - "$(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs " \ - "addip;bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "devno=5\0" \ + "hostname=V38B_$(devno)\0" \ + "ipaddr=10.100.99.$(devno)\0" \ + "netmask=255.255.0.0\0" \ + "serverip=10.100.10.90\0" \ + "gatewayip=10.100.254.254\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=mpc5200/uImage\0" \ + "bootcmd=run net_nfs\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off panic=1\0" \ + "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip;bootm $(kernel_addr) " \ + "$(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs " \ + "addip;bootm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "" #define CONFIG_BOOTCOMMAND "run net_nfs" @@ -196,13 +196,13 @@ */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 +#define CFG_FLASH_CFI_AMD_RESET 1 #define CFG_FLASH_BASE 0xFF000000 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ /* * Environment settings @@ -243,7 +243,7 @@ */ #define CONFIG_MPC5xxx_FEC 1 #define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 +#define CONFIG_MII 1 /* * GPIO configuration @@ -307,12 +307,12 @@ *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ -#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_RESET /* reset for ide supported */ #define CONFIG_IDE_PREINIT #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ @@ -331,13 +331,13 @@ /* Offset for alternate registers */ #define CFG_ATA_ALT_OFFSET (0x005C) -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 -/* Status LED */ +/* Status LED */ -#define CONFIG_STATUS_LED /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ #define CFG_LED_BASE (0xf0000600 + 0x70) /* Timer 7 GPIO */ -- cgit v1.3.1 From 13a7fcdf37f6ea9429ae04c9df67f893364cfe4b Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 19 Oct 2006 11:33:52 -0500 Subject: * Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock --- board/cds/mpc8541cds/mpc8541cds.c | 4 +--- board/cds/mpc8548cds/mpc8548cds.c | 2 -- board/cds/mpc8555cds/mpc8555cds.c | 2 -- board/mpc8540ads/mpc8540ads.c | 3 --- board/mpc8560ads/mpc8560ads.c | 2 -- board/pm854/pm854.c | 2 -- board/pm856/pm856.c | 2 -- board/stxgp3/stxgp3.c | 2 -- board/tqm85xx/tqm85xx.c | 2 -- common/ft_build.c | 10 +++++----- cpu/mpc85xx/pci.c | 5 +++++ include/ft_build.h | 2 ++ include/pci.h | 3 +++ 13 files changed, 16 insertions(+), 25 deletions(-) (limited to 'include') diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index c2b3009fd2b..a42904cf735 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -497,8 +497,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller **hose); - - pci_mpc85xx_init(&hose); + pci_mpc85xx_init(hose); #endif } diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 66219e395b1..41bcf885181 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -323,8 +323,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller **hose); - pci_mpc85xx_init(&hose); #endif } diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index 012181c31d3..d980ea63102 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -497,8 +497,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(hose); #endif } diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c index fbcb397290a..914e51a7607 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/mpc8540ads/mpc8540ads.c @@ -33,7 +33,6 @@ #if defined(CONFIG_OF_FLAT_TREE) #include -extern void ft_cpu_setup(void *blob, bd_t *bd); #endif @@ -327,8 +326,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index f9d75e80510..c1572a35d3f 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -539,8 +539,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 94c492f7821..6ead1d06309 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -289,8 +289,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index 50447083708..a10075451e0 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -442,8 +442,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c index 2b3949cd7b3..a58c043b629 100644 --- a/board/stxgp3/stxgp3.c +++ b/board/stxgp3/stxgp3.c @@ -375,8 +375,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c index b4ef5afe70f..256c076c7dd 100644 --- a/board/tqm85xx/tqm85xx.c +++ b/board/tqm85xx/tqm85xx.c @@ -408,8 +408,6 @@ static struct pci_controller hose = { void pci_init_board (void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init (struct pci_controller *hose); - pci_mpc85xx_init (&hose); #endif /* CONFIG_PCI */ } diff --git a/common/ft_build.c b/common/ft_build.c index 87883cc7d22..980e40f55d5 100644 --- a/common/ft_build.c +++ b/common/ft_build.c @@ -87,9 +87,9 @@ static int lookup_string(struct ft_cxt *cxt, const char *name) p = cxt->p; while (p < cxt->p_end) { - if (strcmp(p, name) == 0) + if (strcmp((char *)p, name) == 0) return p - cxt->p; - p += strlen(p) + 1; + p += strlen((char *)p) + 1; } return -1; @@ -143,9 +143,9 @@ void ft_init_cxt(struct ft_cxt *cxt, void *blob) cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY; } - cxt->p_start = (char*)bph + bph->off_dt_struct; - cxt->p_end = (char *)bph + bph->totalsize; - cxt->p = (char *)bph + bph->off_dt_strings; + cxt->p_start = (u8 *)bph + bph->off_dt_struct; + cxt->p_end = (u8 *)bph + bph->totalsize; + cxt->p = (u8 *)bph + bph->off_dt_strings; } /* add a reserver physical area to the rsvmap */ diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index cfb7dcdc895..84f839ae1e4 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -29,6 +29,9 @@ #include #include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif #if defined(CONFIG_PCI) @@ -42,7 +45,9 @@ pci_mpc85xx_init(struct pci_controller *board_hose) volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; volatile ccsr_pcix_t *pcix = &immap->im_pcix; +#ifdef CONFIG_MPC85XX_PCI2 volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2; +#endif volatile ccsr_gur_t *gur = &immap->im_gur; struct pci_controller * hose; diff --git a/include/ft_build.h b/include/ft_build.h index f5156879de3..89c689c0847 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -64,6 +64,8 @@ void *ft_get_prop(void *bphp, const char *propname, int *szp); #ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup(void *blob, bd_t *bd); +void ft_cpu_setup(void *blob, bd_t *bd); +void ft_pci_setup(void *blob, bd_t *bd); #endif #endif diff --git a/include/pci.h b/include/pci.h index e0e8783a7aa..7c9a0e34410 100644 --- a/include/pci.h +++ b/include/pci.h @@ -501,4 +501,7 @@ extern int pci_hose_config_device(struct pci_controller *hose, extern void pci_mpc824x_init (struct pci_controller *hose); #endif +#ifdef CONFIG_MPC85xx +extern void pci_mpc85xx_init (struct pci_controller *hose); +#endif #endif /* _PCI_H */ -- cgit v1.3.1 From 7237c033b02fe295880435f1eb80819a0c987532 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 19 Oct 2006 11:02:16 -0500 Subject: Moved i2c driver out of cpu/mpc86xx/i2c.c into drivers/fsl_i2c.c in an effort to begin to unify the umpteen FSL I2C drivers that are all otherwise very similar. Signed-off-by: Jon Loeliger --- cpu/mpc86xx/Makefile | 2 +- cpu/mpc86xx/i2c.c | 269 ------------------------------------------ drivers/Makefile | 3 +- drivers/fsl_i2c.c | 247 ++++++++++++++++++++++++++++++++++++++ include/asm-ppc/fsl_i2c.h | 90 ++++++++++++++ include/configs/MPC8641HPCN.h | 1 + 6 files changed, 341 insertions(+), 271 deletions(-) delete mode 100644 cpu/mpc86xx/i2c.c create mode 100644 drivers/fsl_i2c.c create mode 100644 include/asm-ppc/fsl_i2c.h (limited to 'include') diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile index ad5b36deffc..de5561e9238 100644 --- a/cpu/mpc86xx/Makefile +++ b/cpu/mpc86xx/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(CPU).a START = start.o #resetvec.o SOBJS = cache.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o pcie_indirect.o i2c.o spd_sdram.o + pci.o pcie_indirect.o spd_sdram.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc86xx/i2c.c b/cpu/mpc86xx/i2c.c deleted file mode 100644 index d99ecb92d49..00000000000 --- a/cpu/mpc86xx/i2c.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao - * Adapted for Motorola 85xx chip. - * - * (C) Copyright 2003 - * Gleb Natapov - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk - * - * Modified for MPC86xx by Jeff Brown - * - * Hardware I2C driver for MPC107 PCI bridge. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_HARD_I2C -#include - -#define TIMEOUT (CFG_HZ/4) - -#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3100)) - -#define I2CADR &I2C_Addr[0] -#define I2CFDR &I2C_Addr[4] -#define I2CCCR &I2C_Addr[8] -#define I2CCSR &I2C_Addr[12] -#define I2CCDR &I2C_Addr[16] -#define I2CDFSRR &I2C_Addr[20] - -#define I2C_READ 1 -#define I2C_WRITE 0 - -void -i2c_init(int speed, int slaveadd) -{ - /* stop I2C controller */ - writeb(0x0, I2CCCR); - - /* set clock */ - writeb(0x3f, I2CFDR); - - /* set default filter */ - writeb(0x10, I2CDFSRR); - - /* write slave address */ - writeb(slaveadd, I2CADR); - - /* clear status register */ - writeb(0x0, I2CCSR); - - /* start I2C controller */ - writeb(MPC86xx_I2CCR_MEN, I2CCCR); -} - -static __inline__ int -i2c_wait4bus(void) -{ - ulong timeval = get_timer(0); - - while (readb(I2CCSR) & MPC86xx_I2CSR_MBB) { - if (get_timer(timeval) > TIMEOUT) { - return -1; - } - } - - return 0; -} - -static __inline__ int -i2c_wait(int write) -{ - u32 csr; - ulong timeval = get_timer(0); - - do { - csr = readb(I2CCSR); - if (!(csr & MPC86xx_I2CSR_MIF)) - continue; - - writeb(0x0, I2CCSR); - - if (csr & MPC86xx_I2CSR_MAL) { - debug("i2c_wait: MAL\n"); - return -1; - } - - if (!(csr & MPC86xx_I2CSR_MCF)) { - debug("i2c_wait: unfinished\n"); - return -1; - } - - if (write == I2C_WRITE && (csr & MPC86xx_I2CSR_RXAK)) { - debug("i2c_wait: No RXACK\n"); - return -1; - } - - return 0; - } while (get_timer(timeval) < TIMEOUT); - - debug("i2c_wait: timed out\n"); - return -1; -} - -static __inline__ int -i2c_write_addr(u8 dev, u8 dir, int rsta) -{ - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX - | (rsta ? MPC86xx_I2CCR_RSTA : 0), - I2CCCR); - - writeb((dev << 1) | dir, I2CCDR); - - if (i2c_wait(I2C_WRITE) < 0) - return 0; - - return 1; -} - -static __inline__ int -__i2c_write(u8 *data, int length) -{ - int i; - - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX, - I2CCCR); - - for (i = 0; i < length; i++) { - writeb(data[i], I2CCDR); - - if (i2c_wait(I2C_WRITE) < 0) - break; - } - - return i; -} - -static __inline__ int -__i2c_read(u8 *data, int length) -{ - int i; - - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA - | ((length == 1) ? MPC86xx_I2CCR_TXAK : 0), - I2CCCR); - - /* dummy read */ - readb(I2CCDR); - - for (i = 0; i < length; i++) { - if (i2c_wait(I2C_READ) < 0) - break; - - /* Generate ack on last next to last byte */ - if (i == length - 2) - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA - | MPC86xx_I2CCR_TXAK, I2CCCR); - - /* Generate stop on last byte */ - if (i == length - 1) - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_TXAK, I2CCCR); - - data[i] = readb(I2CCDR); - } - - return i; -} - -int -i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) -{ - int i = 0; - u8 *a = (u8 *) &addr; - - if (i2c_wait4bus() < 0) - goto exit; - - if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write(&a[4 - alen], alen) != alen) - goto exit; - - if (i2c_write_addr(dev, I2C_READ, 1) == 0) - goto exit; - - i = __i2c_read(data, length); - -exit: - writeb(MPC86xx_I2CCR_MEN, I2CCCR); - - return !(i == length); -} - -int -i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) -{ - int i = 0; - u8 *a = (u8 *) &addr; - - if (i2c_wait4bus() < 0) - goto exit; - - if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write(&a[4 - alen], alen) != alen) - goto exit; - - i = __i2c_write(data, length); - -exit: - writeb(MPC86xx_I2CCR_MEN, I2CCCR); - - return !(i == length); -} - -int -i2c_probe(uchar chip) -{ - int tmp; - - /* - * Try to read the first location of the chip. The underlying - * driver doesn't appear to support sending just the chip address - * and looking for an back. - */ - udelay(10000); - - return i2c_read(chip, 0, 1, (char *)&tmp, 1); -} - -uchar -i2c_reg_read(uchar i2c_addr, uchar reg) -{ - char buf[1]; - - i2c_read(i2c_addr, reg, 1, buf, 1); - - return buf[0]; -} - -void -i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write(i2c_addr, reg, 1, &val, 1); -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/drivers/Makefile b/drivers/Makefile index 0f84969a99a..b191018c729 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -50,7 +50,8 @@ COBJS = 3c589.o 5701rls.o ali512x.o \ videomodes.o w83c553f.o \ ks8695eth.o \ pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ - rpx_pcmcia.o + rpx_pcmcia.o \ + fsl_i2c.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c new file mode 100644 index 00000000000..72b2556b286 --- /dev/null +++ b/drivers/fsl_i2c.c @@ -0,0 +1,247 @@ +/* + * Copyright 2006 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +#ifdef CONFIG_HARD_I2C + +#include +#include + +#define I2C_TIMEOUT (CFG_HZ / 4) + +#define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET)) + + +void +i2c_init(int speed, int slaveadd) +{ + /* stop I2C controller */ + writeb(0x0 , &I2C->cr); + + /* set clock */ + writeb(0x3f, &I2C->fdr); + + /* set default filter */ + writeb(0x10, &I2C->dfsrr); + + /* write slave address */ + writeb(slaveadd, &I2C->adr); + + /* clear status register */ + writeb(0x0, &I2C->sr); + + /* start I2C controller */ + writeb(I2C_CR_MEN, &I2C->cr); +} + +static __inline__ int +i2c_wait4bus(void) +{ + ulong timeval = get_timer (0); + + while (readb(&I2C->sr) & I2C_SR_MBB) { + if (get_timer(timeval) > I2C_TIMEOUT) { + return -1; + } + } + + return 0; +} + +static __inline__ int +i2c_wait(int write) +{ + u32 csr; + ulong timeval = get_timer(0); + + do { + csr = readb(&I2C->sr); + if (!(csr & I2C_SR_MIF)) + continue; + + writeb(0x0, &I2C->sr); + + if (csr & I2C_SR_MAL) { + debug("i2c_wait: MAL\n"); + return -1; + } + + if (!(csr & I2C_SR_MCF)) { + debug("i2c_wait: unfinished\n"); + return -1; + } + + if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { + debug("i2c_wait: No RXACK\n"); + return -1; + } + + return 0; + } while (get_timer (timeval) < I2C_TIMEOUT); + + debug("i2c_wait: timed out\n"); + return -1; +} + +static __inline__ int +i2c_write_addr (u8 dev, u8 dir, int rsta) +{ + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX + | (rsta ? I2C_CR_RSTA : 0), + &I2C->cr); + + writeb((dev << 1) | dir, &I2C->dr); + + if (i2c_wait(I2C_WRITE) < 0) + return 0; + + return 1; +} + +static __inline__ int +__i2c_write(u8 *data, int length) +{ + int i; + + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, + &I2C->cr); + + for (i = 0; i < length; i++) { + writeb(data[i], &I2C->dr); + + if (i2c_wait(I2C_WRITE) < 0) + break; + } + + return i; +} + +static __inline__ int +__i2c_read(u8 *data, int length) +{ + int i; + + writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), + &I2C->cr); + + /* dummy read */ + readb(&I2C->dr); + + for (i = 0; i < length; i++) { + if (i2c_wait(I2C_READ) < 0) + break; + + /* Generate ack on last next to last byte */ + if (i == length - 2) + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, + &I2C->cr); + + /* Generate stop on last byte */ + if (i == length - 1) + writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr); + + data[i] = readb(&I2C->dr); + } + + return i; +} + +int +i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8*)&addr; + + if (i2c_wait4bus () < 0) + goto exit; + + if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write(&a[4 - alen], alen) != alen) + goto exit; + + if (i2c_write_addr(dev, I2C_READ, 1) == 0) + goto exit; + + i = __i2c_read(data, length); + + exit: + writeb(I2C_CR_MEN, &I2C->cr); + + return !(i == length); +} + +int +i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8*)&addr; + + if (i2c_wait4bus() < 0) + goto exit; + + if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write(&a[4 - alen], alen) != alen) + goto exit; + + i = __i2c_write(data, length); + + exit: + writeb(I2C_CR_MEN, &I2C->cr); + + return !(i == length); +} + +int +i2c_probe(uchar chip) +{ + int tmp; + + /* + * Try to read the first location of the chip. The underlying + * driver doesn't appear to support sending just the chip address + * and looking for an back. + */ + udelay(10000); + + return i2c_read(chip, 0, 1, (uchar *)&tmp, 1); +} + +uchar +i2c_reg_read(uchar i2c_addr, uchar reg) +{ + uchar buf[1]; + + i2c_read(i2c_addr, reg, 1, buf, 1); + + return buf[0]; +} + +void +i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write(i2c_addr, reg, 1, &val, 1); +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/include/asm-ppc/fsl_i2c.h b/include/asm-ppc/fsl_i2c.h new file mode 100644 index 00000000000..76b1c4309b8 --- /dev/null +++ b/include/asm-ppc/fsl_i2c.h @@ -0,0 +1,90 @@ +/* + * Freescale I2C Controller + * + * Copyright 2006 Freescale Semiconductor, Inc. + * + * Based on earlier versions by Gleb Natapov , + * Xianghua Xiao , Eran Liberty (liberty@freescale.com), + * and Jeff Brown. + * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_FSL_I2C_H_ +#define _ASM_FSL_I2C_H_ + +#include + +typedef struct fsl_i2c { + + u8 adr; /* I2C slave address */ + u8 res0[3]; +#define I2C_ADR 0xFE +#define I2C_ADR_SHIFT 1 +#define I2C_ADR_RES ~(I2C_ADR) + + u8 fdr; /* I2C frequency divider register */ + u8 res1[3]; +#define IC2_FDR 0x3F +#define IC2_FDR_SHIFT 0 +#define IC2_FDR_RES ~(IC2_FDR) + + u8 cr; /* I2C control redister */ + u8 res2[3]; +#define I2C_CR_MEN 0x80 +#define I2C_CR_MIEN 0x40 +#define I2C_CR_MSTA 0x20 +#define I2C_CR_MTX 0x10 +#define I2C_CR_TXAK 0x08 +#define I2C_CR_RSTA 0x04 +#define I2C_CR_BCST 0x01 + + u8 sr; /* I2C status register */ + u8 res3[3]; +#define I2C_SR_MCF 0x80 +#define I2C_SR_MAAS 0x40 +#define I2C_SR_MBB 0x20 +#define I2C_SR_MAL 0x10 +#define I2C_SR_BCSTM 0x08 +#define I2C_SR_SRW 0x04 +#define I2C_SR_MIF 0x02 +#define I2C_SR_RXAK 0x01 + + u8 dr; /* I2C data register */ + u8 res4[3]; +#define I2C_DR 0xFF +#define I2C_DR_SHIFT 0 +#define I2C_DR_RES ~(I2C_DR) + + u8 dfsrr; /* I2C digital filter sampling rate register */ + u8 res5[3]; +#define I2C_DFSRR 0x3F +#define I2C_DFSRR_SHIFT 0 +#define I2C_DFSRR_RES ~(I2C_DR) + + /* Fill out the reserved block */ + u8 res6[0xE8]; +} fsl_i2c_t; + + +#define I2C_READ 1 +#define I2C_WRITE 0 + +#endif /* _ASM_I2C_H_ */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 6e883f73f80..81bb7cf134d 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -279,6 +279,7 @@ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x3100 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* -- cgit v1.3.1 From 43a2b0e76a56995f17e1b7628c192ebafe6051ee Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 20 Oct 2006 14:28:52 +0200 Subject: Add board/cpu specific NAND chip select function to 440 NDFC Based on idea and implementation from Jeff Mann Patch by Stefan Roese, 20 Oct 2006 --- CHANGELOG | 4 ++++ common/cmd_nand.c | 8 ++++++++ cpu/ppc4xx/ndfc.c | 39 ++++++++++++++++++++++++++------------- drivers/nand/nand.c | 9 ++++++++- include/configs/sequoia.h | 15 ++++++++------- include/nand.h | 4 ++++ 6 files changed, 58 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 71096e875fc..6ff1f9b37e8 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -7,6 +7,10 @@ Changes since U-Boot 1.1.4: * Add (preliminary) support for V38B board +* Add board/cpu specific NAND chip select function to 440 NDFC + Based on idea and implementation from Jeff Mann + Patch by Stefan Roese, 20 Oct 2006 + * PPC405EP: Add support for board configuration of CPC0_PCI register This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE* Patch by Tolunay Orkun, 07 Apr 2006 diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 7042a9c2266..4fb3b65960d 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -178,6 +178,14 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf("Device %d: %s", dev, nand_info[dev].name); puts("... is now current device\n"); nand_curr_device = dev; + +#ifdef CFG_NAND_SELECT_DEVICE + /* + * Select the chip in the board/cpu specific driver + */ + board_nand_select_device(nand_info[dev].priv, dev); +#endif + return 0; } diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index 183ab5ef168..2c44111da6b 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -66,7 +66,7 @@ static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd) static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; if (hwctl & 0x1) out8(base + NDFC_CMD, byte); @@ -79,7 +79,7 @@ static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte) static u_char ndfc_read_byte(struct mtd_info *mtdinfo) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; return (in8(base + NDFC_DATA)); } @@ -87,7 +87,7 @@ static u_char ndfc_read_byte(struct mtd_info *mtdinfo) static int ndfc_dev_ready(struct mtd_info *mtdinfo) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY)) ; @@ -111,30 +111,30 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo) static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; uint32_t *p = (uint32_t *) buf; - for(;len > 0; len -= 4) + for (;len > 0; len -= 4) *p++ = in32(base + NDFC_DATA); } static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; uint32_t *p = (uint32_t *) buf; - for(; len > 0; len -= 4) + for (; len > 0; len -= 4) out32(base + NDFC_DATA, *p++); } static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; uint32_t *p = (uint32_t *) buf; - for(; len > 0; len -= 4) + for (; len > 0; len -= 4) if (*p++ != in32(base + NDFC_DATA)) return -1; @@ -142,8 +142,20 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len } #endif /* #ifndef CONFIG_NAND_SPL */ +void board_nand_select_device(struct nand_chip *nand, int chip) +{ + ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc; + + /* Set NandFlash Core Configuration Register */ + /* 1col x 2 rows */ + out32(base + NDFC_CCR, 0x00000000 | (chip << 24)); +} + void board_nand_init(struct nand_chip *nand) { + int chip = (ulong)nand->IO_ADDR_W & 0x00000003; + ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc; + nand->eccmode = NAND_ECC_SOFT; nand->hwcontrol = ndfc_hwcontrol; @@ -166,10 +178,11 @@ void board_nand_init(struct nand_chip *nand) mtebc(pb0ap, CFG_EBC_PB0AP); #endif - /* Set NandFlash Core Configuration Register */ - /* Chip select 3, 1col x 2 rows */ - out32(CFG_NAND_BASE + NDFC_CCR, 0x00000000 | (CFG_NAND_CS << 24)); - out32(CFG_NAND_BASE + NDFC_BCFG0 + (CFG_NAND_CS << 2), 0x80002222); + /* + * Select required NAND chip in NDFC + */ + board_nand_select_device(nand, chip); + out32(base + NDFC_BCFG0 + (chip << 2), 0x80002222); } #endif diff --git a/drivers/nand/nand.c b/drivers/nand/nand.c index e1781fcbbf8..3899045a72c 100644 --- a/drivers/nand/nand.c +++ b/drivers/nand/nand.c @@ -66,8 +66,15 @@ void nand_init(void) size += nand_info[i].size; if (nand_curr_device == -1) nand_curr_device = i; -} + } printf("%lu MiB\n", size / (1024 * 1024)); + +#ifdef CFG_NAND_SELECT_DEVICE + /* + * Select the chip in the board/cpu specific driver + */ + board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device); +#endif } #endif diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index f67fd9163d0..3a76315b444 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -134,13 +134,6 @@ #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #endif -/*----------------------------------------------------------------------- - * NAND FLASH - *----------------------------------------------------------------------*/ -#define CFG_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CFG_NAND_BASE CFG_NAND_ADDR - /* * IPL (Initial Program Loader, integrated inside CPU) * Will load first 4k from NAND (SPL) into cache and execute it from there. @@ -405,6 +398,14 @@ #define CFG_EBC_PB2AP 0x24814580 #define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ + /*----------------------------------------------------------------------- * Cache Configuration *----------------------------------------------------------------------*/ diff --git a/include/nand.h b/include/nand.h index 5c7311fd505..23493f7e984 100644 --- a/include/nand.h +++ b/include/nand.h @@ -117,4 +117,8 @@ int nand_lock( nand_info_t *meminfo, int tight ); int nand_unlock( nand_info_t *meminfo, ulong start, ulong length ); int nand_get_lock_status(nand_info_t *meminfo, ulong offset); +#ifdef CFG_NAND_SELECT_DEVICE +void board_nand_select_device(struct nand_chip *nand, int chip); +#endif + #endif -- cgit v1.3.1 From f836e4146088a46d9cd18bbd2f36447ea63e039c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 20 Oct 2006 16:12:14 +0200 Subject: Fix compile problem in include/configs/ep82xxm.h (must have never been tested before!) --- CHANGELOG | 3 +++ include/configs/ep82xxm.h | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 7f0b6121aee..6983b689314 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix compile problem in include/configs/ep82xxm.h + (must have never been tested before!) + * MCC200: Fix uninitialized variable problem in LCD driver * Add board/cpu specific NAND chip select function to 440 NDFC diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index 5d7bed611a0..372b10c623e 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h @@ -28,7 +28,7 @@ #define CONFIG_MPC8260 #define CPU_ID_STR "MPC8270" -#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board /* +#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */ /* 256MB SDRAM / 64MB FLASH */ #undef DEBUG -- cgit v1.3.1 From 2047672684cf85cb6f96a1fbc993180aaaf19a99 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 20 Oct 2006 15:50:15 -0500 Subject: Converted all 85xx boards to use a common FSL I2C driver. Introduced COFIG_FSL_I2C to select the common FSL I2C driver. And removed hard i2c path from a few u-boot.lds scipts too. Minor whitespace cleanups along the way. Signed-off-by: Jon Loeliger --- board/mpc8560ads/u-boot.lds | 1 - board/sbc8560/u-boot.lds | 1 - board/stxgp3/u-boot.lds | 1 - cpu/mpc85xx/Makefile | 2 +- cpu/mpc85xx/i2c.c | 265 ------------------------------------------ drivers/fsl_i2c.c | 10 +- include/configs/MPC8540ADS.h | 8 +- include/configs/MPC8540EVAL.h | 8 +- include/configs/MPC8541CDS.h | 8 +- include/configs/MPC8548CDS.h | 8 +- include/configs/MPC8555CDS.h | 8 +- include/configs/MPC8560ADS.h | 8 +- include/configs/MPC8641HPCN.h | 5 +- include/configs/PM854.h | 8 +- include/configs/PM856.h | 8 +- include/configs/SBC8540.h | 8 +- include/configs/TQM85xx.h | 7 +- include/configs/sbc8560.h | 8 +- include/configs/stxgp3.h | 8 +- 19 files changed, 83 insertions(+), 297 deletions(-) delete mode 100644 cpu/mpc85xx/i2c.c (limited to 'include') diff --git a/board/mpc8560ads/u-boot.lds b/board/mpc8560ads/u-boot.lds index 8dcee1f1015..726a153f98f 100644 --- a/board/mpc8560ads/u-boot.lds +++ b/board/mpc8560ads/u-boot.lds @@ -74,7 +74,6 @@ SECTIONS cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/i2c.o (.text) cpu/mpc85xx/spd_sdram.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) diff --git a/board/sbc8560/u-boot.lds b/board/sbc8560/u-boot.lds index 48e19fe2a22..048ac26b4b7 100644 --- a/board/sbc8560/u-boot.lds +++ b/board/sbc8560/u-boot.lds @@ -77,7 +77,6 @@ SECTIONS cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/i2c.o (.text) cpu/mpc85xx/spd_sdram.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) diff --git a/board/stxgp3/u-boot.lds b/board/stxgp3/u-boot.lds index 3bc615021dc..1bbf20ae29f 100644 --- a/board/stxgp3/u-boot.lds +++ b/board/stxgp3/u-boot.lds @@ -79,7 +79,6 @@ SECTIONS cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/i2c.o (.text) cpu/mpc85xx/spd_sdram.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 7b32305dc4c..ff67dcdd353 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(CPU).a START = start.o resetvec.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o serial_scc.o commproc.o ether_fcc.o i2c.o spd_sdram.o + pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc85xx/i2c.c b/cpu/mpc85xx/i2c.c deleted file mode 100644 index 32dcf5d47e5..00000000000 --- a/cpu/mpc85xx/i2c.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao - * Adapted for Motorola 85xx chip. - * - * (C) Copyright 2003 - * Gleb Natapov - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk - * - * Hardware I2C driver for MPC107 PCI bridge. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_HARD_I2C -#include - -#define TIMEOUT (CFG_HZ/4) - -#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3000)) - -#define I2CADR &I2C_Addr[0] -#define I2CFDR &I2C_Addr[4] -#define I2CCCR &I2C_Addr[8] -#define I2CCSR &I2C_Addr[12] -#define I2CCDR &I2C_Addr[16] -#define I2CDFSRR &I2C_Addr[20] - -#define I2C_READ 1 -#define I2C_WRITE 0 - -void -i2c_init(int speed, int slaveadd) -{ - /* stop I2C controller */ - writeb(0x0, I2CCCR); - - /* set clock */ - writeb(0x3f, I2CFDR); - - /* set default filter */ - writeb(0x10,I2CDFSRR); - - /* write slave address */ - writeb(slaveadd, I2CADR); - - /* clear status register */ - writeb(0x0, I2CCSR); - - /* start I2C controller */ - writeb(MPC85xx_I2CCR_MEN, I2CCCR); -} - -static __inline__ int -i2c_wait4bus (void) -{ - ulong timeval = get_timer (0); - - while (readb(I2CCSR) & MPC85xx_I2CSR_MBB) { - if (get_timer (timeval) > TIMEOUT) { - return -1; - } - } - - return 0; -} - -static __inline__ int -i2c_wait (int write) -{ - u32 csr; - ulong timeval = get_timer (0); - - do { - csr = readb(I2CCSR); - - if (!(csr & MPC85xx_I2CSR_MIF)) - continue; - - writeb(0x0, I2CCSR); - - if (csr & MPC85xx_I2CSR_MAL) { - debug("i2c_wait: MAL\n"); - return -1; - } - - if (!(csr & MPC85xx_I2CSR_MCF)) { - debug("i2c_wait: unfinished\n"); - return -1; - } - - if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK)) { - debug("i2c_wait: No RXACK\n"); - return -1; - } - - return 0; - } while (get_timer (timeval) < TIMEOUT); - - debug("i2c_wait: timed out\n"); - return -1; -} - -static __inline__ int -i2c_write_addr (u8 dev, u8 dir, int rsta) -{ - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX | - (rsta?MPC85xx_I2CCR_RSTA:0), - I2CCCR); - - writeb((dev << 1) | dir, I2CCDR); - - if (i2c_wait (I2C_WRITE) < 0) - return 0; - - return 1; -} - -static __inline__ int -__i2c_write (u8 *data, int length) -{ - int i; - - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX, - I2CCCR); - - for (i=0; i < length; i++) { - writeb(data[i], I2CCDR); - - if (i2c_wait (I2C_WRITE) < 0) - break; - } - - return i; -} - -static __inline__ int -__i2c_read (u8 *data, int length) -{ - int i; - - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | - ((length == 1) ? MPC85xx_I2CCR_TXAK : 0), - I2CCCR); - - /* dummy read */ - readb(I2CCDR); - - for (i=0; i < length; i++) { - if (i2c_wait (I2C_READ) < 0) - break; - - /* Generate ack on last next to last byte */ - if (i == length - 2) - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | - MPC85xx_I2CCR_TXAK, - I2CCCR); - - /* Generate stop on last byte */ - if (i == length - 1) - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR); - - data[i] = readb(I2CCDR); - } - - return i; -} - -int -i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) -{ - int i = 0; - u8 *a = (u8*)&addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - if (i2c_write_addr (dev, I2C_READ, 1) == 0) - goto exit; - - i = __i2c_read (data, length); - - exit: - writeb(MPC85xx_I2CCR_MEN, I2CCCR); - - return !(i == length); -} - -int -i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) -{ - int i = 0; - u8 *a = (u8*)&addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - i = __i2c_write (data, length); - - exit: - writeb(MPC85xx_I2CCR_MEN, I2CCCR); - - return !(i == length); -} - -int i2c_probe (uchar chip) -{ - int tmp; - - /* - * Try to read the first location of the chip. The underlying - * driver doesn't appear to support sending just the chip address - * and looking for an back. - */ - udelay(10000); - return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); -} - -uchar i2c_reg_read (uchar i2c_addr, uchar reg) -{ - uchar buf[1]; - - i2c_read (i2c_addr, reg, 1, buf, 1); - - return (buf[0]); -} - -void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write (i2c_addr, reg, 1, &val, 1); -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c index af191915e37..65c27439e36 100644 --- a/drivers/fsl_i2c.c +++ b/drivers/fsl_i2c.c @@ -18,11 +18,14 @@ #include +#ifdef CONFIG_FSL_I2C #ifdef CONFIG_HARD_I2C #include +#include /* Functional interface */ + #include -#include +#include /* HW definitions */ #define I2C_TIMEOUT (CFG_HZ / 4) #define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET)) @@ -32,7 +35,7 @@ void i2c_init(int speed, int slaveadd) { /* stop I2C controller */ - writeb(0x0 , &I2C->cr); + writeb(0x0, &I2C->cr); /* set clock */ writeb(0x3f, &I2C->fdr); @@ -53,7 +56,7 @@ i2c_init(int speed, int slaveadd) static __inline__ int i2c_wait4bus(void) { - ulong timeval = get_timer (0); + ulong timeval = get_timer(0); while (readb(&I2C->sr) & I2C_SR_MBB) { if (get_timer(timeval) > I2C_TIMEOUT) { @@ -235,3 +238,4 @@ i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) } #endif /* CONFIG_HARD_I2C */ +#endif /* CONFIG_FSL_I2C */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 31ffbaf15b4..74a84f4e86a 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -312,12 +312,16 @@ #define CFG_64BIT_VSPRINTF 1 #define CFG_64BIT_STRTOUL 1 -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* RapidIO MMU */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 1af923103ff..418a3a38e68 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -179,12 +179,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* General PCI */ #define CFG_PCI_MEM_BASE 0x80000000 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 2b87f1bd6a9..db389cfe676 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -320,13 +320,17 @@ extern unsigned long get_clock_freq(void); #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * General PCI diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 03ab976d118..be8f93ffb8d 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -326,13 +326,17 @@ extern unsigned long get_clock_freq(void); #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * General PCI diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 771a9d3b950..4c8b4e73f3b 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -320,13 +320,17 @@ extern unsigned long get_clock_freq(void); #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600" -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * General PCI diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 1c684f2fd10..835bf5cb64e 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -302,12 +302,16 @@ #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500" -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* RapidIO MMU */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 81bb7cf134d..246ac7f316f 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -275,12 +275,13 @@ /* * I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_OFFSET 0x3100 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3100 /* * RapidIO MMU diff --git a/include/configs/PM854.h b/include/configs/PM854.h index da011867717..4fb54402b1b 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -193,12 +193,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * EEPROM configuration diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 4d834878ee0..87ab9348735 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -190,12 +190,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * EEPROM configuration diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 0451b208197..f8e3397a3f0 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -214,12 +214,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 #define CFG_PCI_MEM_BASE 0xC0000000 #define CFG_PCI_MEM_PHYS 0xC0000000 diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index bc3b9aa1d0a..cce46249048 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -192,12 +192,17 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* I2C RTC */ #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 5a434dc767b..6e4fdb2498e 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -197,12 +197,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 #define CFG_PCI_MEM_BASE 0xC0000000 #define CFG_PCI_MEM_PHYS 0xC0000000 diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index e218597db01..625cf20144f 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -172,8 +172,11 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F @@ -183,6 +186,7 @@ /* I did the 'if 0' so we could keep the syntax above if ever needed. */ #undef CFG_I2C_NOPROBES #endif +#define CFG_I2C_OFFSET 0x3000 /* RapdIO Map configuration, mapped 1:1. */ -- cgit v1.3.1 From 3dfa9cfdcee78b30da3432318b32821ffabe974b Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 20 Oct 2006 17:16:35 -0500 Subject: Use generic I2C register block on 85xx and 86xx. Replace private IMMAP I2C structures with generic reg block and allow 86xx to have multiple I2C device busses. Signed-off-by: Jon Loeliger --- include/asm-ppc/immap_85xx.h | 36 +++++--------------------------- include/asm-ppc/immap_86xx.h | 49 ++++---------------------------------------- 2 files changed, 9 insertions(+), 76 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 7a4345a7408..5377c2eb5be 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -9,6 +9,9 @@ #ifndef __IMMAP_85xx__ #define __IMMAP_85xx__ +#include +#include + /* * Local-Access Registers and ECM Registers(0x0000-0x2000) */ @@ -129,37 +132,8 @@ typedef struct ccsr_ddr { * I2C Registers(0x3000-0x4000) */ typedef struct ccsr_i2c { - u_char i2cadr; /* 0x3000 - I2C Address Register */ -#define MPC85xx_I2CADR_MASK 0xFE - char res1[3]; - u_char i2cfdr; /* 0x3004 - I2C Frequency Divider Register */ -#define MPC85xx_I2CFDR_MASK 0x3F - char res2[3]; - u_char i2ccr; /* 0x3008 - I2C Control Register */ -#define MPC85xx_I2CCR_MEN 0x80 -#define MPC85xx_I2CCR_MIEN 0x40 -#define MPC85xx_I2CCR_MSTA 0x20 -#define MPC85xx_I2CCR_MTX 0x10 -#define MPC85xx_I2CCR_TXAK 0x08 -#define MPC85xx_I2CCR_RSTA 0x04 -#define MPC85xx_I2CCR_BCST 0x01 - char res3[3]; - u_char i2csr; /* 0x300c - I2C Status Register */ -#define MPC85xx_I2CSR_MCF 0x80 -#define MPC85xx_I2CSR_MAAS 0x40 -#define MPC85xx_I2CSR_MBB 0x20 -#define MPC85xx_I2CSR_MAL 0x10 -#define MPC85xx_I2CSR_BCSTM 0x08 -#define MPC85xx_I2CSR_SRW 0x04 -#define MPC85xx_I2CSR_MIF 0x02 -#define MPC85xx_I2CSR_RXAK 0x01 - char res4[3]; - u_char i2cdr; /* 0x3010 - I2C Data Register */ -#define MPC85xx_I2CDR_DATA 0xFF - char res5[3]; - u_char i2cdfsrr; /* 0x3014 - I2C Digital Filtering Sampling Rate Register */ -#define MPC85xx_I2CDFSRR 0x3F - char res6[4075]; + struct fsl_i2c i2c[1]; + u8 res[4096 - 1 * sizeof(struct fsl_i2c)]; } ccsr_i2c_t; #if defined(CONFIG_MPC8540) \ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 685fcafdf2f..a5552c48ee9 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -10,6 +10,8 @@ #ifndef __IMMAP_86xx__ #define __IMMAP_86xx__ +#include +#include /* Local-Access Registers and MCM Registers(0x0000-0x2000) */ typedef struct ccsr_local_mcm { @@ -155,52 +157,9 @@ typedef struct ccsr_ddr { /* Daul I2C Registers(0x3000-0x4000) */ - typedef struct ccsr_i2c { - u_char i2cadr1; /* 0x3000 - I2C 1 Address Register */ -#define MPC86xx_I2CADR_MASK 0xFE - char res1[3]; - u_char i2cfdr1; /* 0x3004 - I2C 1 Frequency Divider Register */ -#define MPC86xx_I2CFDR_MASK 0x3F - char res2[3]; - u_char i2ccr1; /* 0x3008 - I2C 1 Control Register */ -#define MPC86xx_I2CCR_MEN 0x80 -#define MPC86xx_I2CCR_MIEN 0x40 -#define MPC86xx_I2CCR_MSTA 0x20 -#define MPC86xx_I2CCR_MTX 0x10 -#define MPC86xx_I2CCR_TXAK 0x08 -#define MPC86xx_I2CCR_RSTA 0x04 -#define MPC86xx_I2CCR_BCST 0x01 - char res3[3]; - u_char i2csr1; /* 0x300c - I2C 1 Status Register */ -#define MPC86xx_I2CSR_MCF 0x80 -#define MPC86xx_I2CSR_MAAS 0x40 -#define MPC86xx_I2CSR_MBB 0x20 -#define MPC86xx_I2CSR_MAL 0x10 -#define MPC86xx_I2CSR_BCSTM 0x08 -#define MPC86xx_I2CSR_SRW 0x04 -#define MPC86xx_I2CSR_MIF 0x02 -#define MPC86xx_I2CSR_RXAK 0x01 - char res4[3]; - u_char i2cdr1; /* 0x3010 - I2C 1 Data Register */ -#define MPC86xx_I2CDR_DATA 0xFF - char res5[3]; - u_char i2cdfsrr1; /* 0x3014 - I2C 1 Digital Filtering Sampling Rate Register */ -#define MPC86xx_I2CDFSRR 0x3F - char res6[235]; - - u_char i2cadr2; /* 0x3100 - I2C 2 Address Register */ - char res7[3]; - u_char i2cfdr2; /* 0x3104 - I2C 2 Frequency Divider Register */ - char res8[3]; - u_char i2ccr2; /* 0x3108 - I2C 2 Control Register */ - char res9[3]; - u_char i2csr2; /* 0x310c - I2C 2 Status Register */ - char res10[3]; - u_char i2cdr2; /* 0x3110 - I2C 2 Data Register */ - char res11[3]; - u_char i2cdfsrr2; /* 0x3114 - I2C 2 Digital Filtering Sampling Rate Register */ - char res12[3819]; + struct fsl_i2c i2c[2]; + u8 res[4096 - 2 * sizeof(struct fsl_i2c)]; } ccsr_i2c_t; /* DUART Registers(0x4000-0x5000) */ -- cgit v1.3.1 From 7b64fef33c66be648826c0ff9758298ef13d0604 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 24 Oct 2006 14:21:16 +0200 Subject: Add AVR32 architecture support Patch by Haavard Skinnemoen, 6 Sep 2006 16:23:02 +0200 This patch adds common infrastructure code for the Atmel AVR32 architecture. See doc/README.AVR32 for details. Signed-off-by: Haavard Skinnemoen --- MAINTAINERS | 7 + Makefile | 7 + README | 5 +- avr32_config.mk | 25 ++++ doc/README.AVR32 | 33 +++++ examples/Makefile | 4 + examples/stubs.c | 13 ++ include/asm-avr32/addrspace.h | 46 ++++++ include/asm-avr32/bitops.h | 25 ++++ include/asm-avr32/byteorder.h | 37 +++++ include/asm-avr32/cacheflush.h | 83 +++++++++++ include/asm-avr32/div64.h | 39 +++++ include/asm-avr32/dma-mapping.h | 64 ++++++++ include/asm-avr32/errno.h | 132 +++++++++++++++++ include/asm-avr32/global_data.h | 59 ++++++++ include/asm-avr32/initcalls.h | 33 +++++ include/asm-avr32/io.h | 92 ++++++++++++ include/asm-avr32/posix_types.h | 144 ++++++++++++++++++ include/asm-avr32/processor.h | 97 +++++++++++++ include/asm-avr32/ptrace.h | 148 +++++++++++++++++++ include/asm-avr32/sdram.h | 33 +++++ include/asm-avr32/sections.h | 39 +++++ include/asm-avr32/setup.h | 142 ++++++++++++++++++ include/asm-avr32/string.h | 28 ++++ include/asm-avr32/sysreg.h | 279 +++++++++++++++++++++++++++++++++++ include/asm-avr32/types.h | 84 +++++++++++ include/asm-avr32/u-boot.h | 56 +++++++ lib_avr32/Makefile | 47 ++++++ lib_avr32/avr32_linux.c | 315 ++++++++++++++++++++++++++++++++++++++++ lib_avr32/board.c | 175 ++++++++++++++++++++++ lib_avr32/div64.c | 54 +++++++ lib_avr32/interrupts.c | 39 +++++ lib_avr32/memset.S | 81 +++++++++++ 33 files changed, 2463 insertions(+), 2 deletions(-) create mode 100644 avr32_config.mk create mode 100644 doc/README.AVR32 create mode 100644 include/asm-avr32/addrspace.h create mode 100644 include/asm-avr32/bitops.h create mode 100644 include/asm-avr32/byteorder.h create mode 100644 include/asm-avr32/cacheflush.h create mode 100644 include/asm-avr32/div64.h create mode 100644 include/asm-avr32/dma-mapping.h create mode 100644 include/asm-avr32/errno.h create mode 100644 include/asm-avr32/global_data.h create mode 100644 include/asm-avr32/initcalls.h create mode 100644 include/asm-avr32/io.h create mode 100644 include/asm-avr32/posix_types.h create mode 100644 include/asm-avr32/processor.h create mode 100644 include/asm-avr32/ptrace.h create mode 100644 include/asm-avr32/sdram.h create mode 100644 include/asm-avr32/sections.h create mode 100644 include/asm-avr32/setup.h create mode 100644 include/asm-avr32/string.h create mode 100644 include/asm-avr32/sysreg.h create mode 100644 include/asm-avr32/types.h create mode 100644 include/asm-avr32/u-boot.h create mode 100644 lib_avr32/Makefile create mode 100644 lib_avr32/avr32_linux.c create mode 100644 lib_avr32/board.c create mode 100644 lib_avr32/div64.c create mode 100644 lib_avr32/interrupts.c create mode 100644 lib_avr32/memset.S (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 42627196f86..d7ef203e551 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -554,6 +554,13 @@ Zachary P. Landau r5200 mcf52x2 +######################################################################### +# AVR32 Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + ######################################################################### # End of MAINTAINERS list # ######################################################################### diff --git a/Makefile b/Makefile index 92034947962..5260a612ff3 100644 --- a/Makefile +++ b/Makefile @@ -152,6 +152,9 @@ endif ifeq ($(ARCH),blackfin) CROSS_COMPILE = bfin-elf- endif +ifeq ($(ARCH),avr32) +CROSS_COMPILE = avr32- +endif endif endif @@ -2099,6 +2102,10 @@ pb1000_config : unconfig @echo "#define CONFIG_PB1000 1" >>$(obj)include/config.h @$(MKCONFIG) -a pb1x00 mips mips pb1x00 +#======================================================================== +# AVR32 +#======================================================================== + ######################################################################### ## MIPS64 5Kc ######################################################################### diff --git a/README b/README index a0949f0d9b1..8405a9b0cd1 100644 --- a/README +++ b/README @@ -156,6 +156,7 @@ Directory Hierarchy: - examples Example code for standalone applications, etc. - include Header Files - lib_arm Files generic to ARM architecture +- lib_avr32 Files generic to AVR32 architecture - lib_generic Files generic to all architectures - lib_i386 Files generic to i386 architecture - lib_m68k Files generic to m68k architecture @@ -2722,9 +2723,9 @@ defines the following image properties: 4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks, LynxOS, pSOS, QNX, RTEMS, ARTOS; Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS, LynxOS). -* Target CPU Architecture (Provisions for Alpha, ARM, Intel x86, +* Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86, IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit; - Currently supported: ARM, Intel x86, MIPS, NIOS, PowerPC). + Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC). * Compression Type (uncompressed, gzip, bzip2) * Load Address * Entry Point diff --git a/avr32_config.mk b/avr32_config.mk new file mode 100644 index 00000000000..0b92053e1af --- /dev/null +++ b/avr32_config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-r5 -mno-pic -mrelax +PLATFORM_LDFLAGS += --relax diff --git a/doc/README.AVR32 b/doc/README.AVR32 new file mode 100644 index 00000000000..abec872c57a --- /dev/null +++ b/doc/README.AVR32 @@ -0,0 +1,33 @@ +From: Haavard Skinnemoen +Date: Wed, 30 Aug 2006 17:01:46 +0200 +Subject: [PATCH] AVR32 architecture support + +This patch adds common infrastructure code for the Atmel AVR32 +architecture. + +AVR32 is a new high-performance 32-bit RISC microprocessor core, +designed for cost-sensitive embedded applications, with particular +emphasis on low power consumption and high code density. The AVR32 +architecture is not binary compatible with earlier 8-bit AVR +architectures. + +The AVR32 architecture, including the instruction set, is described +by the AVR32 Architecture Manual, available from + +http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf + +A GNU toolchain with support for AVR32 is included with the ATSTK1000 +BSP, which can be downloaded as an ISO image from + +http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918 + +Alternatively, you can build it yourself by following the +Getting Started guide at avr32linux.org, which also provides links +to the necessary sources and patches you need to download: + +http://avr32linux.org/twiki/bin/view/Main/GettingStarted + +The AVR32 ports of u-boot, the Linux kernel, the GNU toolchain and +other associated software are actively supported by Atmel Corporation. + +Signed-off-by: Haavard Skinnemoen diff --git a/examples/Makefile b/examples/Makefile index 680fe75d921..423a79b2dd5 100644 --- a/examples/Makefile +++ b/examples/Makefile @@ -57,6 +57,10 @@ ifeq ($(ARCH),blackfin) LOAD_ADDR = 0x1000 endif +ifeq ($(ARCH),avr32) +LOAD_ADDR = 0x00000000 +endif + include $(TOPDIR)/config.mk ELF = hello_world diff --git a/examples/stubs.c b/examples/stubs.c index 1caa5757479..ffd314e6b35 100644 --- a/examples/stubs.c +++ b/examples/stubs.c @@ -138,6 +138,19 @@ gd_t *global_data; " P0 = [P0 + %1]\n" \ " JUMP (P0)\n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "P0"); +#elif defined(CONFIG_AVR32) +/* + * r6 holds the pointer to the global_data. r8 is call clobbered. + */ +#define EXPORT_FUNC(x) \ + asm volatile( \ + " .globl\t" #x "\n" \ + #x ":\n" \ + " ld.w r8, r6[%0]\n" \ + " ld.w pc, r8[%1]\n" \ + : \ + : "i"(offsetof(gd_t, jt)), "i"(XF_ ##x) \ + : "r8"); #else #error stubs definition missing for this architecture #endif diff --git a/include/asm-avr32/addrspace.h b/include/asm-avr32/addrspace.h new file mode 100644 index 00000000000..b2ba1ee2fef --- /dev/null +++ b/include/asm-avr32/addrspace.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ADDRSPACE_H +#define __ASM_AVR32_ADDRSPACE_H + +/* Memory segments when segmentation is enabled */ +#define P0SEG 0x00000000 +#define P1SEG 0x80000000 +#define P2SEG 0xa0000000 +#define P3SEG 0xc0000000 +#define P4SEG 0xe0000000 + +/* Returns the privileged segment base of a given address */ +#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) + +/* Returns the physical address of a PnSEG (n=1,2) address */ +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) + +/* + * Map an address to a certain privileged segment + */ +#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) +#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) +#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) +#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) + +#endif /* __ASM_AVR32_ADDRSPACE_H */ diff --git a/include/asm-avr32/bitops.h b/include/asm-avr32/bitops.h new file mode 100644 index 00000000000..f15fd4647e2 --- /dev/null +++ b/include/asm-avr32/bitops.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_BITOPS_H +#define __ASM_AVR32_BITOPS_H + +#endif /* __ASM_AVR32_BITOPS_H */ diff --git a/include/asm-avr32/byteorder.h b/include/asm-avr32/byteorder.h new file mode 100644 index 00000000000..2fe867e9786 --- /dev/null +++ b/include/asm-avr32/byteorder.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_BYTEORDER_H +#define __ASM_AVR32_BYTEORDER_H + +#include + +#define __arch__swab32(x) __builtin_bswap_32(x) +#define __arch__swab16(x) __builtin_bswap_16(x) + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#include + +#endif /* __ASM_AVR32_BYTEORDER_H */ diff --git a/include/asm-avr32/cacheflush.h b/include/asm-avr32/cacheflush.h new file mode 100644 index 00000000000..929f68e1a0a --- /dev/null +++ b/include/asm-avr32/cacheflush.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_CACHEFLUSH_H +#define __ASM_AVR32_CACHEFLUSH_H + +/* + * Invalidate any cacheline containing virtual address vaddr without + * writing anything back to memory. + * + * Note that this function may corrupt unrelated data structures when + * applied on buffers that are not cacheline aligned in both ends. + */ +static inline void dcache_invalidate_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory"); +} + +/* + * Make sure any cacheline containing virtual address vaddr is written + * to memory. + */ +static inline void dcache_clean_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory"); +} + +/* + * Make sure any cacheline containing virtual address vaddr is written + * to memory and then invalidate it. + */ +static inline void dcache_flush_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory"); +} + +/* + * Invalidate any instruction cacheline containing virtual address + * vaddr. + */ +static inline void icache_invalidate_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory"); +} + +/* + * Applies the above functions on all lines that are touched by the + * specified virtual address range. + */ +void dcache_invalidate_range(volatile void *start, size_t len); +void dcache_clean_range(volatile void *start, size_t len); +void dcache_flush_range(volatile void *start, size_t len); +void icache_invalidate_range(volatile void *start, size_t len); + +static inline void dcache_flush_unlocked(void) +{ + asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory"); +} + +/* + * Make sure any pending writes are completed before continuing. + */ +#define sync_write_buffer() asm volatile("sync 0" : : : "memory") + +#endif /* __ASM_AVR32_CACHEFLUSH_H */ diff --git a/include/asm-avr32/div64.h b/include/asm-avr32/div64.h new file mode 100644 index 00000000000..2e0ba8389e1 --- /dev/null +++ b/include/asm-avr32/div64.h @@ -0,0 +1,39 @@ +#ifndef _ASM_GENERIC_DIV64_H +#define _ASM_GENERIC_DIV64_H +/* + * Copyright (C) 2003 Bernardo Innocenti + * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h + * + * The semantics of do_div() are: + * + * uint32_t do_div(uint64_t *n, uint32_t base) + * { + * uint32_t remainder = *n % base; + * *n = *n / base; + * return remainder; + * } + * + * NOTE: macro parameter n is evaluated multiple times, + * beware of side effects! + */ + +#include + +extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor); + +/* The unnecessary pointer compare is there + * to check for type safety (n must be 64bit) + */ +# define do_div(n,base) ({ \ + uint32_t __base = (base); \ + uint32_t __rem; \ + (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \ + if (((n) >> 32) == 0) { \ + __rem = (uint32_t)(n) % __base; \ + (n) = (uint32_t)(n) / __base; \ + } else \ + __rem = __div64_32(&(n), __base); \ + __rem; \ + }) + +#endif /* _ASM_GENERIC_DIV64_H */ diff --git a/include/asm-avr32/dma-mapping.h b/include/asm-avr32/dma-mapping.h new file mode 100644 index 00000000000..3b46fa3e62b --- /dev/null +++ b/include/asm-avr32/dma-mapping.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_DMA_MAPPING_H +#define __ASM_AVR32_DMA_MAPPING_H + +#include +#include + +enum dma_data_direction { + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, +}; +extern void *dma_alloc_coherent(size_t len, unsigned long *handle); + +static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, + enum dma_data_direction dir) +{ + extern void __bad_dma_data_direction(void); + + switch (dir) { + case DMA_BIDIRECTIONAL: + dcache_flush_range(vaddr, len); + break; + case DMA_TO_DEVICE: + dcache_clean_range(vaddr, len); + break; + case DMA_FROM_DEVICE: + dcache_invalidate_range(vaddr, len); + break; + default: + /* This will cause a linker error */ + __bad_dma_data_direction(); + } + + return virt_to_phys(vaddr); +} + +static inline void dma_unmap_single(volatile void *vaddr, size_t len, + unsigned long paddr) +{ + +} + +#endif /* __ASM_AVR32_DMA_MAPPING_H */ diff --git a/include/asm-avr32/errno.h b/include/asm-avr32/errno.h new file mode 100644 index 00000000000..ea3506ff380 --- /dev/null +++ b/include/asm-avr32/errno.h @@ -0,0 +1,132 @@ +#ifndef _ASM_AVR32_ERRNO_H +#define _ASM_AVR32_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +#endif /* _ASM_AVR32_ERRNO_H */ diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h new file mode 100644 index 00000000000..01d836c6395 --- /dev/null +++ b/include/asm-avr32/global_data.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_GLOBAL_DATA_H__ +#define __ASM_GLOBAL_DATA_H__ + +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + const struct device *console_uart; + const struct device *sm; + unsigned long baudrate; + unsigned long sdram_size; + unsigned long have_console; /* serial_init() was called */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of env struct */ + unsigned long env_valid; /* Checksum of env valid? */ + unsigned long cpu_hz; /* cpu core clock frequency */ + void **jt; /* jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5") + +#endif /* __ASM_GLOBAL_DATA_H__ */ diff --git a/include/asm-avr32/initcalls.h b/include/asm-avr32/initcalls.h new file mode 100644 index 00000000000..7ba25cde53e --- /dev/null +++ b/include/asm-avr32/initcalls.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2005, 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_INITCALLS_H__ +#define __ASM_AVR32_INITCALLS_H__ + +#include + +extern int cpu_init(void); +extern int timer_init(void); +extern void board_init_memories(void); +extern void board_init_pio(void); +extern void board_init_info(void); + +#endif /* __ASM_AVR32_INITCALLS_H__ */ diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h new file mode 100644 index 00000000000..e86c456ae1e --- /dev/null +++ b/include/asm-avr32/io.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_IO_H +#define __ASM_AVR32_IO_H + +#ifdef __KERNEL__ + +/* + * Generic IO read/write. These perform native-endian accesses. Note + * that some architectures will want to re-define __raw_{read,write}w. + */ +extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); +extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); +extern void __raw_writesl(unsigned int addr, const void *data, int longlen); + +extern void __raw_readsb(unsigned int addr, void *data, int bytelen); +extern void __raw_readsw(unsigned int addr, void *data, int wordlen); +extern void __raw_readsl(unsigned int addr, void *data, int longlen); + +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + +/* As long as I/O is only performed in P4 (or possibly P3), we're safe */ +#define writeb(v,a) __raw_writeb(v,a) +#define writew(v,a) __raw_writew(v,a) +#define writel(v,a) __raw_writel(v,a) + +#define readb(a) __raw_readb(a) +#define readw(a) __raw_readw(a) +#define readl(a) __raw_readl(a) + +/* + * Bad read/write accesses... + */ +extern void __readwrite_bug(const char *fn); + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * All I/O is memory mapped, so these macros doesn't make very much sense + */ +#define outb(v,p) __raw_writeb(v, p) +#define outw(v,p) __raw_writew(cpu_to_le16(v),p) +#define outl(v,p) __raw_writel(cpu_to_le32(v),p) + +#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; }) +#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; }) +#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; }) + +#include + +/* virt_to_phys will only work when address is in P1 or P2 */ +static __inline__ unsigned long virt_to_phys(volatile void *address) +{ + return PHYSADDR(address); +} + +static __inline__ void * phys_to_virt(unsigned long address) +{ + return (void *)P1SEGADDR(address); +} + +#define cached(addr) ((void *)P1SEGADDR(addr)) +#define uncached(addr) ((void *)P2SEGADDR(addr)) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_AVR32_IO_H */ diff --git a/include/asm-avr32/posix_types.h b/include/asm-avr32/posix_types.h new file mode 100644 index 00000000000..edf1bc14d25 --- /dev/null +++ b/include/asm-avr32/posix_types.h @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_POSIX_TYPES_H +#define __ASM_AVR32_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned long __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned int __kernel_uid_t; +typedef unsigned int __kernel_gid_t; +typedef unsigned long __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_timer_t; +typedef int __kernel_clockid_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; +typedef unsigned short __kernel_old_dev_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) + +#undef __FD_SET +static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); +} + +#undef __FD_CLR +static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); +} + + +#undef __FD_ISSET +static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; +} + +/* + * This will unroll the loop for the normal constant case (8 ints, + * for a 256-bit fd_set) + */ +#undef __FD_ZERO +static __inline__ void __FD_ZERO(__kernel_fd_set *__p) +{ + unsigned long *__tmp = __p->fds_bits; + int __i; + + if (__builtin_constant_p(__FDSET_LONGS)) { + switch (__FDSET_LONGS) { + case 16: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + __tmp[ 8] = 0; __tmp[ 9] = 0; + __tmp[10] = 0; __tmp[11] = 0; + __tmp[12] = 0; __tmp[13] = 0; + __tmp[14] = 0; __tmp[15] = 0; + return; + + case 8: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + return; + + case 4: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + return; + } + } + __i = __FDSET_LONGS; + while (__i) { + __i--; + *__tmp = 0; + __tmp++; + } +} + +#endif /* defined(__KERNEL__) */ + +#endif /* __ASM_AVR32_POSIX_TYPES_H */ diff --git a/include/asm-avr32/processor.h b/include/asm-avr32/processor.h new file mode 100644 index 00000000000..cc59dfad56b --- /dev/null +++ b/include/asm-avr32/processor.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PROCESSOR_H +#define __ASM_AVR32_PROCESSOR_H + +#ifndef __ASSEMBLY__ + +#define current_text_addr() ({ void *pc; __asm__("mov %0,pc" : "=r"(pc)); pc; }) + +struct avr32_cpuinfo { + unsigned long loops_per_jiffy; +}; + +extern struct avr32_cpuinfo boot_cpu_data; + +#ifdef CONFIG_SMP +extern struct avr32_cpuinfo cpu_data[]; +#define current_cpu_data cpu_data[smp_processor_id()] +#else +#define cpu_data (&boot_cpu_data) +#define current_cpu_data boot_cpu_data +#endif + +/* TODO: Make configurable (2GB will serve as a reasonable default) */ +#define TASK_SIZE 0x80000000 + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) + +#define cpu_relax() barrier() +#define cpu_sync_pipeline() asm volatile("sub pc, -2" : : : "memory") + +/* This struct contains the CPU context as stored by switch_to() */ +struct thread_struct { + unsigned long pc; + unsigned long ksp; /* Kernel stack pointer */ + unsigned long r7; + unsigned long r6; + unsigned long r5; + unsigned long r4; + unsigned long r3; + unsigned long r2; + unsigned long r1; + unsigned long r0; +}; + +#define INIT_THREAD { \ + .ksp = sizeof(init_stack) + (long)&init_stack, \ +} + +/* + * Do necessary setup to start up a newly executed thread. + */ +#define start_thread(regs, new_pc, new_sp) \ + set_fs(USER_DS); \ + regs->sr = 0; /* User mode. */ \ + regs->gr[REG_PC] = new_pc; \ + regs->gr[REG_SP] = new_sp + +struct task_struct; + +/* Free all resources held by a thread */ +extern void release_thread(struct task_struct *); + +/* Create a kernel thread without removing it from tasklists */ +extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); + +/* Prepare to copy thread state - unlazy all lazy status */ +#define prepare_to_copy(tsk) do { } while(0) + +/* Return saved PC of a blocked thread */ +#define thread_saved_pc(tsk) (tsk->thread.pc) + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_AVR32_PROCESSOR_H */ diff --git a/include/asm-avr32/ptrace.h b/include/asm-avr32/ptrace.h new file mode 100644 index 00000000000..c770ba02c30 --- /dev/null +++ b/include/asm-avr32/ptrace.h @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PTRACE_H +#define __ASM_AVR32_PTRACE_H + +/* + * Status Register bits + */ +#define SR_H 0x40000000 +#define SR_R 0x20000000 +#define SR_J 0x10000000 +#define SR_DM 0x08000000 +#define SR_D 0x04000000 +#define MODE_NMI 0x01c00000 +#define MODE_EXCEPTION 0x01800000 +#define MODE_INT3 0x01400000 +#define MODE_INT2 0x01000000 +#define MODE_INT1 0x00c00000 +#define MODE_INT0 0x00800000 +#define MODE_SUPERVISOR 0x00400000 +#define MODE_USER 0x00000000 +#define MODE_MASK 0x01c00000 +#define SR_EM 0x00200000 +#define SR_I3M 0x00100000 +#define SR_I2M 0x00080000 +#define SR_I1M 0x00040000 +#define SR_I0M 0x00020000 +#define SR_GM 0x00010000 + +#define MODE_SHIFT 22 +#define SR_EM_BIT 21 +#define SR_I3M_BIT 20 +#define SR_I2M_BIT 19 +#define SR_I1M_BIT 18 +#define SR_I0M_BIT 17 +#define SR_GM_BIT 16 + +/* The user-visible part */ +#define SR_Q 0x00000010 +#define SR_V 0x00000008 +#define SR_N 0x00000004 +#define SR_Z 0x00000002 +#define SR_C 0x00000001 + +/* + * The order is defined by the stdsp instruction. r0 is stored first, so it + * gets the highest address. + * + * Registers 0-12 are general-purpose registers (r12 is normally used for + * the function return value). + * Register 13 is the stack pointer + * Register 14 is the link register + * Register 15 is the program counter + */ +#define FRAME_SIZE_FULL 72 +#define REG_R12_ORIG 68 +#define REG_R0 64 +#define REG_R1 60 +#define REG_R2 56 +#define REG_R3 52 +#define REG_R4 48 +#define REG_R5 44 +#define REG_R6 40 +#define REG_R7 36 +#define REG_R8 32 +#define REG_R9 28 +#define REG_R10 34 +#define REG_R11 20 +#define REG_R12 16 +#define REG_SP 12 +#define REG_LR 8 + +#define FRAME_SIZE_MIN 8 +#define REG_PC 4 +#define REG_SR 0 + +#ifndef __ASSEMBLY__ +struct pt_regs { + /* These are always saved */ + unsigned long sr; + unsigned long pc; + + /* These are sometimes saved */ + unsigned long lr; + unsigned long sp; + unsigned long r12; + unsigned long r11; + unsigned long r10; + unsigned long r9; + unsigned long r8; + unsigned long r7; + unsigned long r6; + unsigned long r5; + unsigned long r4; + unsigned long r3; + unsigned long r2; + unsigned long r1; + unsigned long r0; + + /* Only saved on system call */ + unsigned long r12_orig; +}; + +#ifdef __KERNEL__ +# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER) +# define instruction_pointer(regs) ((regs)->pc) +extern void show_regs (struct pt_regs *); + +static __inline__ int valid_user_regs(struct pt_regs *regs) +{ + /* + * Some of the Java bits might be acceptable if/when we + * implement some support for that stuff... + */ + if ((regs->sr & 0xffff0000) == 0) + return 1; + + /* + * Force status register flags to be sane and report this + * illegal behaviour... + */ + regs->sr &= 0x0000ffff; + return 0; +} +#endif + +#endif /* ! __ASSEMBLY__ */ + +#endif /* __ASM_AVR32_PTRACE_H */ diff --git a/include/asm-avr32/sdram.h b/include/asm-avr32/sdram.h new file mode 100644 index 00000000000..5057eefa8ad --- /dev/null +++ b/include/asm-avr32/sdram.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_SDRAM_H +#define __ASM_AVR32_SDRAM_H + +struct sdram_info { + unsigned long phys_addr; + unsigned int row_bits, col_bits, bank_bits; + unsigned int cas, twr, trc, trp, trcd, tras, txsr; +}; + +extern unsigned long sdram_init(const struct sdram_info *info); + +#endif /* __ASM_AVR32_SDRAM_H */ diff --git a/include/asm-avr32/sections.h b/include/asm-avr32/sections.h new file mode 100644 index 00000000000..75373abde73 --- /dev/null +++ b/include/asm-avr32/sections.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_SECTIONS_H +#define __ASM_AVR32_SECTIONS_H + +/* References to section boundaries */ + +extern char _text[], _etext[]; +extern char __flashprog_start[], __flashprog_end[]; +extern char _data[], __data_lma[], _edata[], __edata_lma[]; +extern char __got_start[], __got_lma[], __got_end[]; +extern char _end[]; + +/* + * Everything in .flashprog will be locked in the icache so it doesn't + * get disturbed when executing flash commands. + */ +#define __flashprog __attribute__((section(".flashprog"), __noinline__)) + +#endif /* __ASM_AVR32_SECTIONS_H */ diff --git a/include/asm-avr32/setup.h b/include/asm-avr32/setup.h new file mode 100644 index 00000000000..e6ef8d6b50c --- /dev/null +++ b/include/asm-avr32/setup.h @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * Based on linux/include/asm-arm/setup.h + * Copyright (C) 1997-1999 Russel King + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_SETUP_H__ +#define __ASM_AVR32_SETUP_H__ + +#define COMMAND_LINE_SIZE 256 + +/* Magic number indicating that a tag table is present */ +#define ATAG_MAGIC 0xa2a25441 + +#ifndef __ASSEMBLY__ + +/* + * Generic memory range, used by several tags. + * + * addr is always physical. + * size is measured in bytes. + * next is for use by the OS, e.g. for grouping regions into + * linked lists. + */ +struct tag_mem_range { + u32 addr; + u32 size; + struct tag_mem_range * next; +}; + +/* The list ends with an ATAG_NONE node. */ +#define ATAG_NONE 0x00000000 + +struct tag_header { + u32 size; + u32 tag; +}; + +/* The list must start with an ATAG_CORE node */ +#define ATAG_CORE 0x54410001 + +struct tag_core { + u32 flags; + u32 pagesize; + u32 rootdev; +}; + +/* it is allowed to have multiple ATAG_MEM nodes */ +#define ATAG_MEM 0x54410002 +/* ATAG_MEM uses tag_mem_range */ + +/* command line: \0 terminated string */ +#define ATAG_CMDLINE 0x54410003 + +struct tag_cmdline { + char cmdline[1]; /* this is the minimum size */ +}; + +/* Ramdisk image (may be compressed) */ +#define ATAG_RDIMG 0x54410004 +/* ATAG_RDIMG uses tag_mem_range */ + +/* Information about various clocks present in the system */ +#define ATAG_CLOCK 0x54410005 + +struct tag_clock { + u32 clock_id; /* Which clock are we talking about? */ + u32 clock_flags; /* Special features */ + u64 clock_hz; /* Clock speed in Hz */ +}; + +/* The clock types we know about */ +#define ACLOCK_BOOTCPU 0 /* The CPU we're booting from */ +#define ACLOCK_HSB 1 /* Deprecated */ + +/* Memory reserved for the system (e.g. the bootloader) */ +#define ATAG_RSVD_MEM 0x54410006 +/* ATAG_RSVD_MEM uses tag_mem_range */ + +/* Ethernet information */ + +#define ATAG_ETHERNET 0x54410007 + +struct tag_ethernet { + u8 mac_index; + u8 mii_phy_addr; + u8 hw_address[6]; +}; + +#define AETH_INVALID_PHY 0xff + +struct tag { + struct tag_header hdr; + union { + struct tag_core core; + struct tag_mem_range mem_range; + struct tag_cmdline cmdline; + struct tag_clock clock; + struct tag_ethernet ethernet; + } u; +}; + +struct tagtable { + u32 tag; + int (*parse)(struct tag *); +}; + +#define __tag __attribute_used__ __attribute__((__section__(".taglist"))) +#define __tagtable(tag, fn) \ + static struct tagtable __tagtable_##fn __tag = { tag, fn } + +#define tag_member_present(tag,member) \ + ((unsigned long)(&((struct tag *)0L)->member + 1) \ + <= (tag)->hdr.size * 4) + +#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) +#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) + +#define for_each_tag(t,base) \ + for (t = base; t->hdr.size; t = tag_next(t)) + +#endif /* !__ASSEMBLY__ */ + +#endif /* __ASM_AVR32_SETUP_H__ */ diff --git a/include/asm-avr32/string.h b/include/asm-avr32/string.h new file mode 100644 index 00000000000..8b05d1a031e --- /dev/null +++ b/include/asm-avr32/string.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_STRING_H +#define __ASM_AVR32_STRING_H + +#define __HAVE_ARCH_MEMSET +extern void *memset(void *s, int c, size_t n); + +#endif /* __ASM_AVR32_STRING_H */ diff --git a/include/asm-avr32/sysreg.h b/include/asm-avr32/sysreg.h new file mode 100644 index 00000000000..72ad49e5e2d --- /dev/null +++ b/include/asm-avr32/sysreg.h @@ -0,0 +1,279 @@ +/* + * System registers for AVR32 + */ +#ifndef __ASM_AVR32_SYSREG_H__ +#define __ASM_AVR32_SYSREG_H__ + +/* system register offsets */ +#define SYSREG_SR 0x0000 +#define SYSREG_EVBA 0x0004 +#define SYSREG_ACBA 0x0008 +#define SYSREG_CPUCR 0x000c +#define SYSREG_ECR 0x0010 +#define SYSREG_RSR_SUP 0x0014 +#define SYSREG_RSR_INT0 0x0018 +#define SYSREG_RSR_INT1 0x001c +#define SYSREG_RSR_INT2 0x0020 +#define SYSREG_RSR_INT3 0x0024 +#define SYSREG_RSR_EX 0x0028 +#define SYSREG_RSR_NMI 0x002c +#define SYSREG_RSR_DBG 0x0030 +#define SYSREG_RAR_SUP 0x0034 +#define SYSREG_RAR_INT0 0x0038 +#define SYSREG_RAR_INT1 0x003c +#define SYSREG_RAR_INT2 0x0040 +#define SYSREG_RAR_INT3 0x0044 +#define SYSREG_RAR_EX 0x0048 +#define SYSREG_RAR_NMI 0x004c +#define SYSREG_RAR_DBG 0x0050 +#define SYSREG_JECR 0x0054 +#define SYSREG_JOSP 0x0058 +#define SYSREG_JAVA_LV0 0x005c +#define SYSREG_JAVA_LV1 0x0060 +#define SYSREG_JAVA_LV2 0x0064 +#define SYSREG_JAVA_LV3 0x0068 +#define SYSREG_JAVA_LV4 0x006c +#define SYSREG_JAVA_LV5 0x0070 +#define SYSREG_JAVA_LV6 0x0074 +#define SYSREG_JAVA_LV7 0x0078 +#define SYSREG_JTBA 0x007c +#define SYSREG_JBCR 0x0080 +#define SYSREG_CONFIG0 0x0100 +#define SYSREG_CONFIG1 0x0104 +#define SYSREG_COUNT 0x0108 +#define SYSREG_COMPARE 0x010c +#define SYSREG_TLBEHI 0x0110 +#define SYSREG_TLBELO 0x0114 +#define SYSREG_PTBR 0x0118 +#define SYSREG_TLBEAR 0x011c +#define SYSREG_MMUCR 0x0120 +#define SYSREG_TLBARLO 0x0124 +#define SYSREG_TLBARHI 0x0128 +#define SYSREG_PCCNT 0x012c +#define SYSREG_PCNT0 0x0130 +#define SYSREG_PCNT1 0x0134 +#define SYSREG_PCCR 0x0138 +#define SYSREG_BEAR 0x013c +#define SYSREG_SABAL 0x0300 +#define SYSREG_SABAH 0x0304 +#define SYSREG_SABD 0x0308 + +/* Bitfields in SR */ +#define SYSREG_SR_C_OFFSET 0 +#define SYSREG_SR_C_SIZE 1 +#define SYSREG_Z_OFFSET 1 +#define SYSREG_Z_SIZE 1 +#define SYSREG_SR_N_OFFSET 2 +#define SYSREG_SR_N_SIZE 1 +#define SYSREG_SR_V_OFFSET 3 +#define SYSREG_SR_V_SIZE 1 +#define SYSREG_Q_OFFSET 4 +#define SYSREG_Q_SIZE 1 +#define SYSREG_L_OFFSET 5 +#define SYSREG_L_SIZE 1 +#define SYSREG_T_OFFSET 14 +#define SYSREG_T_SIZE 1 +#define SYSREG_SR_R_OFFSET 15 +#define SYSREG_SR_R_SIZE 1 +#define SYSREG_GM_OFFSET 16 +#define SYSREG_GM_SIZE 1 +#define SYSREG_I0M_OFFSET 17 +#define SYSREG_I0M_SIZE 1 +#define SYSREG_I1M_OFFSET 18 +#define SYSREG_I1M_SIZE 1 +#define SYSREG_I2M_OFFSET 19 +#define SYSREG_I2M_SIZE 1 +#define SYSREG_I3M_OFFSET 20 +#define SYSREG_I3M_SIZE 1 +#define SYSREG_EM_OFFSET 21 +#define SYSREG_EM_SIZE 1 +#define SYSREG_M0_OFFSET 22 +#define SYSREG_M0_SIZE 1 +#define SYSREG_M1_OFFSET 23 +#define SYSREG_M1_SIZE 1 +#define SYSREG_M2_OFFSET 24 +#define SYSREG_M2_SIZE 1 +#define SYSREG_SR_D_OFFSET 26 +#define SYSREG_SR_D_SIZE 1 +#define SYSREG_DM_OFFSET 27 +#define SYSREG_DM_SIZE 1 +#define SYSREG_SR_J_OFFSET 28 +#define SYSREG_SR_J_SIZE 1 +#define SYSREG_H_OFFSET 29 +#define SYSREG_H_SIZE 1 + +/* Bitfields in CPUCR */ +#define SYSREG_BI_OFFSET 0 +#define SYSREG_BI_SIZE 1 +#define SYSREG_BE_OFFSET 1 +#define SYSREG_BE_SIZE 1 +#define SYSREG_FE_OFFSET 2 +#define SYSREG_FE_SIZE 1 +#define SYSREG_RE_OFFSET 3 +#define SYSREG_RE_SIZE 1 +#define SYSREG_IBE_OFFSET 4 +#define SYSREG_IBE_SIZE 1 +#define SYSREG_IEE_OFFSET 5 +#define SYSREG_IEE_SIZE 1 + +/* Bitfields in ECR */ +#define SYSREG_ECR_OFFSET 0 +#define SYSREG_ECR_SIZE 32 + +/* Bitfields in CONFIG0 */ +#define SYSREG_CONFIG0_R_OFFSET 0 +#define SYSREG_CONFIG0_R_SIZE 1 +#define SYSREG_CONFIG0_D_OFFSET 1 +#define SYSREG_CONFIG0_D_SIZE 1 +#define SYSREG_CONFIG0_S_OFFSET 2 +#define SYSREG_CONFIG0_S_SIZE 1 +#define SYSREG_O_OFFSET 3 +#define SYSREG_O_SIZE 1 +#define SYSREG_P_OFFSET 4 +#define SYSREG_P_SIZE 1 +#define SYSREG_CONFIG0_J_OFFSET 5 +#define SYSREG_CONFIG0_J_SIZE 1 +#define SYSREG_F_OFFSET 6 +#define SYSREG_F_SIZE 1 +#define SYSREG_MMUT_OFFSET 7 +#define SYSREG_MMUT_SIZE 3 +#define SYSREG_AR_OFFSET 10 +#define SYSREG_AR_SIZE 3 +#define SYSREG_AT_OFFSET 13 +#define SYSREG_AT_SIZE 3 +#define SYSREG_PROCESSORREVISION_OFFSET 16 +#define SYSREG_PROCESSORREVISION_SIZE 8 +#define SYSREG_PROCESSORID_OFFSET 24 +#define SYSREG_PROCESSORID_SIZE 8 + +/* Bitfields in CONFIG1 */ +#define SYSREG_DASS_OFFSET 0 +#define SYSREG_DASS_SIZE 3 +#define SYSREG_DLSZ_OFFSET 3 +#define SYSREG_DLSZ_SIZE 3 +#define SYSREG_DSET_OFFSET 6 +#define SYSREG_DSET_SIZE 4 +#define SYSREG_IASS_OFFSET 10 +#define SYSREG_IASS_SIZE 3 +#define SYSREG_ILSZ_OFFSET 13 +#define SYSREG_ILSZ_SIZE 3 +#define SYSREG_ISET_OFFSET 16 +#define SYSREG_ISET_SIZE 4 +#define SYSREG_DMMUSZ_OFFSET 20 +#define SYSREG_DMMUSZ_SIZE 6 +#define SYSREG_IMMUSZ_OFFSET 26 +#define SYSREG_IMMUSZ_SIZE 6 + +/* Bitfields in TLBEHI */ +#define SYSREG_ASID_OFFSET 0 +#define SYSREG_ASID_SIZE 8 +#define SYSREG_TLBEHI_I_OFFSET 8 +#define SYSREG_TLBEHI_I_SIZE 1 +#define SYSREG_TLBEHI_V_OFFSET 9 +#define SYSREG_TLBEHI_V_SIZE 1 +#define SYSREG_VPN_OFFSET 10 +#define SYSREG_VPN_SIZE 22 + +/* Bitfields in TLBELO */ +#define SYSREG_W_OFFSET 0 +#define SYSREG_W_SIZE 1 +#define SYSREG_TLBELO_D_OFFSET 1 +#define SYSREG_TLBELO_D_SIZE 1 +#define SYSREG_SZ_OFFSET 2 +#define SYSREG_SZ_SIZE 2 +#define SYSREG_AP_OFFSET 4 +#define SYSREG_AP_SIZE 3 +#define SYSREG_B_OFFSET 7 +#define SYSREG_B_SIZE 1 +#define SYSREG_G_OFFSET 8 +#define SYSREG_G_SIZE 1 +#define SYSREG_TLBELO_C_OFFSET 9 +#define SYSREG_TLBELO_C_SIZE 1 +#define SYSREG_PFN_OFFSET 10 +#define SYSREG_PFN_SIZE 22 + +/* Bitfields in MMUCR */ +#define SYSREG_E_OFFSET 0 +#define SYSREG_E_SIZE 1 +#define SYSREG_M_OFFSET 1 +#define SYSREG_M_SIZE 1 +#define SYSREG_MMUCR_I_OFFSET 2 +#define SYSREG_MMUCR_I_SIZE 1 +#define SYSREG_MMUCR_N_OFFSET 3 +#define SYSREG_MMUCR_N_SIZE 1 +#define SYSREG_MMUCR_S_OFFSET 4 +#define SYSREG_MMUCR_S_SIZE 1 +#define SYSREG_DLA_OFFSET 8 +#define SYSREG_DLA_SIZE 6 +#define SYSREG_DRP_OFFSET 14 +#define SYSREG_DRP_SIZE 6 +#define SYSREG_ILA_OFFSET 20 +#define SYSREG_ILA_SIZE 6 +#define SYSREG_IRP_OFFSET 26 +#define SYSREG_IRP_SIZE 6 + +/* Bitfields in PCCR */ +#define SYSREG_PCCR_R_OFFSET 1 +#define SYSREG_PCCR_R_SIZE 1 +#define SYSREG_PCCR_C_OFFSET 2 +#define SYSREG_PCCR_C_SIZE 1 +#define SYSREG_PCCR_S_OFFSET 3 +#define SYSREG_PCCR_S_SIZE 1 +#define SYSREG_IEC_OFFSET 4 +#define SYSREG_IEC_SIZE 1 +#define SYSREG_IE0_OFFSET 5 +#define SYSREG_IE0_SIZE 1 +#define SYSREG_IE1_OFFSET 6 +#define SYSREG_IE1_SIZE 1 +#define SYSREG_FC_OFFSET 8 +#define SYSREG_FC_SIZE 1 +#define SYSREG_F0_OFFSET 9 +#define SYSREG_F0_SIZE 1 +#define SYSREG_F1_OFFSET 10 +#define SYSREG_F1_SIZE 1 +#define SYSREG_CONF0_OFFSET 12 +#define SYSREG_CONF0_SIZE 6 +#define SYSREG_CONF1_OFFSET 18 +#define SYSREG_CONF1_SIZE 6 + +/* Constants for ECR */ +#define ECR_UNRECOVERABLE 0 +#define ECR_TLB_MULTIPLE 1 +#define ECR_BUS_ERROR_WRITE 2 +#define ECR_BUS_ERROR_READ 3 +#define ECR_NMI 4 +#define ECR_ADDR_ALIGN_X 5 +#define ECR_PROTECTION_X 6 +#define ECR_DEBUG 7 +#define ECR_ILLEGAL_OPCODE 8 +#define ECR_UNIMPL_INSTRUCTION 9 +#define ECR_PRIVILEGE_VIOLATION 10 +#define ECR_FPE 11 +#define ECR_COPROC_ABSENT 12 +#define ECR_ADDR_ALIGN_R 13 +#define ECR_ADDR_ALIGN_W 14 +#define ECR_PROTECTION_R 15 +#define ECR_PROTECTION_W 16 +#define ECR_DTLB_MODIFIED 17 +#define ECR_TLB_MISS_X 20 +#define ECR_TLB_MISS_R 24 +#define ECR_TLB_MISS_W 28 + +/* Bit manipulation macros */ +#define SYSREG_BIT(name) (1 << SYSREG_##name##_OFFSET) +#define SYSREG_BF(name,value) \ + (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) \ + << SYSREG_##name##_OFFSET) +#define SYSREG_BFEXT(name,value) \ + (((value) >> SYSREG_##name##_OFFSET) \ + & ((1 << SYSREG_##name##_SIZE) - 1)) +#define SYSREG_BFINS(name,value,old) \ + (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) \ + << SYSREG_##name##_OFFSET)) \ + | SYSREG_BF(name,value)) + +/* Register access macros */ +#define sysreg_read(reg) __builtin_mfsr(SYSREG_##reg) +#define sysreg_write(reg, value) __builtin_mtsr(SYSREG_##reg, value) + +#endif /* __ASM_AVR32_SYSREG_H__ */ diff --git a/include/asm-avr32/types.h b/include/asm-avr32/types.h new file mode 100644 index 00000000000..e6c65d9179b --- /dev/null +++ b/include/asm-avr32/types.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_TYPES_H +#define __ASM_AVR32_TYPES_H + +#ifndef __ASSEMBLY__ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +#endif /* __ASSEMBLY__ */ + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +#define BITS_PER_LONG 32 + +#ifndef __ASSEMBLY__ + +typedef __signed__ char s8; +typedef unsigned char u8; + +typedef __signed__ short s16; +typedef unsigned short u16; + +typedef __signed__ int s32; +typedef unsigned int u32; + +typedef __signed__ long long s64; +typedef unsigned long long u64; + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +#ifdef CONFIG_LBD +typedef u64 sector_t; +#define HAVE_SECTOR_T +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __KERNEL__ */ + + +#endif /* __ASM_AVR32_TYPES_H */ diff --git a/include/asm-avr32/u-boot.h b/include/asm-avr32/u-boot.h new file mode 100644 index 00000000000..71dfcaf2840 --- /dev/null +++ b/include/asm-avr32/u-boot.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_U_BOOT_H__ +#define __ASM_U_BOOT_H__ 1 + +typedef struct bd_info { + unsigned long bi_baudrate; + unsigned long bi_ip_addr; + unsigned char bi_enetaddr[6]; + unsigned char bi_phy_id[4]; + struct environment_s *bi_env; + unsigned long bi_board_number; + void *bi_boot_params; + struct { + unsigned long start; + unsigned long size; + } bi_dram[CONFIG_NR_DRAM_BANKS]; + unsigned long bi_flashstart; + unsigned long bi_flashsize; + unsigned long bi_flashoffset; +} bd_t; + +#define bi_memstart bi_dram[0].start +#define bi_memsize bi_dram[0].size + +/** + * container_of - cast a member of a structure out to the containing structure + * + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + +#endif /* __ASM_U_BOOT_H__ */ diff --git a/lib_avr32/Makefile b/lib_avr32/Makefile new file mode 100644 index 00000000000..5b6300ba78a --- /dev/null +++ b/lib_avr32/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2002-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2004-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(ARCH).a + +SOBJS = memset.o + +COBJS = board.o interrupts.o avr32_linux.o div64.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/lib_avr32/avr32_linux.c b/lib_avr32/avr32_linux.c new file mode 100644 index 00000000000..d128dfb53f0 --- /dev/null +++ b/lib_avr32/avr32_linux.c @@ -0,0 +1,315 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +/* CPU-specific hook to allow flushing of caches, etc. */ +extern void prepare_to_boot(void); + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +extern image_header_t header; /* from cmd_bootm.c */ + +static struct tag *setup_start_tag(struct tag *params) +{ + params->hdr.tag = ATAG_CORE; + params->hdr.size = tag_size(tag_core); + + params->u.core.flags = 0; + params->u.core.pagesize = 4096; + params->u.core.rootdev = 0; + + return tag_next(params); +} + +static struct tag *setup_memory_tags(struct tag *params) +{ + bd_t *bd = gd->bd; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + params->hdr.tag = ATAG_MEM; + params->hdr.size = tag_size(tag_mem_range); + + params->u.mem_range.addr = bd->bi_dram[i].start; + params->u.mem_range.size = bd->bi_dram[i].size; + + params = tag_next(params); + } + + return params; +} + +static struct tag *setup_commandline_tag(struct tag *params, char *cmdline) +{ + if (!cmdline) + return params; + + /* eat leading white space */ + while (*cmdline == ' ') cmdline++; + + /* + * Don't include tags for empty command lines; let the kernel + * use its default command line. + */ + if (*cmdline == '\0') + return params; + + params->hdr.tag = ATAG_CMDLINE; + params->hdr.size = + (sizeof (struct tag_header) + strlen(cmdline) + 1 + 3) >> 2; + strcpy(params->u.cmdline.cmdline, cmdline); + + return tag_next(params); +} + +static struct tag *setup_ramdisk_tag(struct tag *params, + unsigned long rd_start, + unsigned long rd_end) +{ + if (rd_start == rd_end) + return params; + + params->hdr.tag = ATAG_RDIMG; + params->hdr.size = tag_size(tag_mem_range); + + params->u.mem_range.addr = rd_start; + params->u.mem_range.size = rd_end - rd_start; + + return tag_next(params); +} + +static struct tag *setup_clock_tags(struct tag *params) +{ + params->hdr.tag = ATAG_CLOCK; + params->hdr.size = tag_size(tag_clock); + params->u.clock.clock_id = ACLOCK_BOOTCPU; + params->u.clock.clock_flags = 0; + params->u.clock.clock_hz = gd->cpu_hz; + +#ifdef CONFIG_AT32AP7000 + /* + * New kernels don't need this, but we should be backwards + * compatible for a while... + */ + params = tag_next(params); + + params->hdr.tag = ATAG_CLOCK; + params->hdr.size = tag_size(tag_clock); + params->u.clock.clock_id = ACLOCK_HSB; + params->u.clock.clock_flags = 0; + params->u.clock.clock_hz = pm_get_clock_freq(CLOCK_HSB); +#endif + + return tag_next(params); +} + +static struct tag *setup_ethernet_tag(struct tag *params, + char *addr, int index) +{ + char *s, *e; + int i; + + params->hdr.tag = ATAG_ETHERNET; + params->hdr.size = tag_size(tag_ethernet); + + params->u.ethernet.mac_index = index; + params->u.ethernet.mii_phy_addr = gd->bd->bi_phy_id[index]; + + s = addr; + for (i = 0; i < 6; i++) { + params->u.ethernet.hw_address[i] = simple_strtoul(s, &e, 16); + s = e + 1; + } + + return tag_next(params); +} + +static struct tag *setup_ethernet_tags(struct tag *params) +{ + char name[16] = "ethaddr"; + char *addr; + int i = 0; + + do { + addr = getenv(name); + if (addr) + params = setup_ethernet_tag(params, addr, i); + sprintf(name, "eth%daddr", ++i); + } while (i < 4); + + return params; +} + +static void setup_end_tag(struct tag *params) +{ + params->hdr.tag = ATAG_NONE; + params->hdr.size = 0; +} + +void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + unsigned long addr, unsigned long *len_ptr, int verify) +{ + unsigned long data, len = 0; + unsigned long initrd_start, initrd_end; + unsigned long image_start, image_end; + unsigned long checksum; + void (*theKernel)(int magic, void *tagtable); + image_header_t *hdr; + struct tag *params, *params_start; + char *commandline = getenv("bootargs"); + + hdr = (image_header_t *)addr; + image_start = addr; + image_end = addr + hdr->ih_size; + + theKernel = (void *)ntohl(hdr->ih_ep); + + /* + * Check if there is an initrd image + */ + if (argc >= 3) { + SHOW_BOOT_PROGRESS(9); + + addr = simple_strtoul(argv[2], NULL, 16); + + printf("## Loading RAMDISK image at %08lx ...\n", addr); + + memcpy(&header, (char *)addr, sizeof(header)); + hdr = &header; + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + puts("Bad Magic Number\n"); + SHOW_BOOT_PROGRESS(-10); + do_reset(cmdtp, flag, argc, argv); + } + + data = (unsigned long)hdr; + len = sizeof(*hdr); + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32(0, (unsigned char *)data, len) != checksum) { + puts("Bad Header Checksum\n"); + SHOW_BOOT_PROGRESS(-11); + do_reset(cmdtp, flag, argc, argv); + } + + SHOW_BOOT_PROGRESS(10); + + print_image_hdr(hdr); + + data = addr + sizeof(header); + len = ntohl(hdr->ih_size); + + if (verify) { + unsigned long csum = 0; + + puts(" Verifying Checksum ... "); + csum = crc32(0, (unsigned char *)data, len); + if (csum != ntohl(hdr->ih_dcrc)) { + puts("Bad Data CRC\n"); + SHOW_BOOT_PROGRESS(-12); + do_reset(cmdtp, flag, argc, argv); + } + puts("OK\n"); + } + + SHOW_BOOT_PROGRESS(11); + + if ((hdr->ih_os != IH_OS_LINUX) || + (hdr->ih_arch != IH_CPU_AVR32) || + (hdr->ih_type != IH_TYPE_RAMDISK)) { + puts("Not a Linux/AVR32 RAMDISK image\n"); + SHOW_BOOT_PROGRESS(-13); + do_reset(cmdtp, flag, argc, argv); + } + } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) { + ulong tail = ntohl (len_ptr[0]) % 4; + int i; + + SHOW_BOOT_PROGRESS (13); + + /* skip kernel length and terminator */ + data = (ulong) (&len_ptr[2]); + /* skip any additional image length fields */ + for (i = 1; len_ptr[i]; ++i) + data += 4; + /* add kernel length, and align */ + data += ntohl (len_ptr[0]); + if (tail) { + data += 4 - tail; + } + + len = ntohl (len_ptr[1]); + } else { + /* no initrd image */ + SHOW_BOOT_PROGRESS(14); + len = data = 0; + } + + if (data) { + initrd_start = data; + initrd_end = initrd_start + len; + } else { + initrd_start = 0; + initrd_end = 0; + } + + SHOW_BOOT_PROGRESS(15); + + params = params_start = (struct tag *)gd->bd->bi_boot_params; + params = setup_start_tag(params); + params = setup_memory_tags(params); + if (initrd_start) { + params = setup_ramdisk_tag(params, + PHYSADDR(initrd_start), + PHYSADDR(initrd_end)); + } + params = setup_commandline_tag(params, commandline); + params = setup_clock_tags(params); + params = setup_ethernet_tags(params); + setup_end_tag(params); + + printf("\nStarting kernel at %p (params at %p)...\n\n", + theKernel, params_start); + + prepare_to_boot(); + + theKernel(ATAG_MAGIC, params_start); +} diff --git a/lib_avr32/board.c b/lib_avr32/board.c new file mode 100644 index 00000000000..02c106b80ed --- /dev/null +++ b/lib_avr32/board.c @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const char version_string[] = + U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ") " CONFIG_IDENT_STRING; + +unsigned long monitor_flash_len; + +/* + * Begin and end of memory area for malloc(), and current "brk" + */ +static unsigned long mem_malloc_start = 0; +static unsigned long mem_malloc_end = 0; +static unsigned long mem_malloc_brk = 0; + +/* The malloc area is wherever the board wants it to be */ +static void mem_malloc_init(void) +{ + mem_malloc_start = CFG_MALLOC_START; + mem_malloc_end = CFG_MALLOC_END; + mem_malloc_brk = mem_malloc_start; + + printf("malloc: Using memory from 0x%08lx to 0x%08lx\n", + mem_malloc_start, mem_malloc_end); + + memset ((void *)mem_malloc_start, 0, + mem_malloc_end - mem_malloc_start); +} + +void *sbrk(ptrdiff_t increment) +{ + unsigned long old = mem_malloc_brk; + unsigned long new = old + increment; + + if ((new < mem_malloc_start) || (new > mem_malloc_end)) + return NULL; + + mem_malloc_brk = new; + return ((void *)old); +} + +static int init_baudrate(void) +{ + char tmp[64]; + int i; + + i = getenv_r("baudrate", tmp, sizeof(tmp)); + if (i > 0) { + gd->baudrate = simple_strtoul(tmp, NULL, 10); + } else { + gd->baudrate = CONFIG_BAUDRATE; + } + return 0; +} + + +static int display_banner (void) +{ + printf ("\n\n%s\n\n", version_string); + printf ("U-Boot code: %p -> %p data: %p -> %p\n", + _text, _etext, _data, _end); + return 0; +} + +void hang(void) +{ + for (;;) ; +} + +static int display_dram_config (void) +{ + int i; + + puts ("DRAM Configuration:\n"); + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); + print_size (gd->bd->bi_dram[i].size, "\n"); + } + + return 0; +} + +static void display_flash_config (void) +{ + puts ("Flash: "); + print_size(gd->bd->bi_flashsize, " "); + printf("at address 0x%08lx\n", gd->bd->bi_flashstart); +} + +void start_u_boot (void) +{ + gd_t gd_data; + + /* Initialize the global data pointer */ + memset(&gd_data, 0, sizeof(gd_data)); + gd = &gd_data; + + monitor_flash_len = _edata - _text; + + /* Perform initialization sequence */ + cpu_init(); + timer_init(); + env_init(); + init_baudrate(); + serial_init(); + console_init_f(); + display_banner(); + + board_init_memories(); + mem_malloc_init(); + + gd->bd = malloc(sizeof(bd_t)); + memset(gd->bd, 0, sizeof(bd_t)); + gd->bd->bi_baudrate = gd->baudrate; + gd->bd->bi_dram[0].start = CFG_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->sdram_size; + + board_init_info(); + flash_init(); + + if (gd->bd->bi_flashsize) + display_flash_config(); + if (gd->bd->bi_dram[0].size) + display_dram_config(); + + gd->bd->bi_boot_params = malloc(CFG_BOOTPARAMS_LEN); + if (!gd->bd->bi_boot_params) + puts("WARNING: Cannot allocate space for boot parameters\n"); + + /* initialize environment */ + env_relocate(); + + devices_init(); + jumptable_init(); + console_init_r(); + + for (;;) { + main_loop(); + } +} diff --git a/lib_avr32/div64.c b/lib_avr32/div64.c new file mode 100644 index 00000000000..99726e325da --- /dev/null +++ b/lib_avr32/div64.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2003 Bernardo Innocenti + * + * Based on former do_div() implementation from asm-parisc/div64.h: + * Copyright (C) 1999 Hewlett-Packard Co + * Copyright (C) 1999 David Mosberger-Tang + * + * + * Generic C version of 64bit/32bit division and modulo, with + * 64bit result and 32bit remainder. + * + * The fast case for (n>>32 == 0) is handled inline by do_div(). + * + * Code generated for this function might be very inefficient + * for some CPUs. __div64_32() can be overridden by linking arch-specific + * assembly versions such as arch/ppc/lib/div64.S and arch/sh/lib/div64.S. + */ + +#include + +#include + +uint32_t __div64_32(uint64_t *n, uint32_t base) +{ + uint64_t rem = *n; + uint64_t b = base; + uint64_t res, d = 1; + uint32_t high = rem >> 32; + + /* Reduce the thing a bit first */ + res = 0; + if (high >= base) { + high /= base; + res = (uint64_t) high << 32; + rem -= (uint64_t) (high*base) << 32; + } + + while ((int64_t)b > 0 && b < rem) { + b = b+b; + d = d+d; + } + + do { + if (rem >= b) { + rem -= b; + res += d; + } + b >>= 1; + d >>= 1; + } while (d); + + *n = res; + return rem; +} diff --git a/lib_avr32/interrupts.c b/lib_avr32/interrupts.c new file mode 100644 index 00000000000..ce538f3d924 --- /dev/null +++ b/lib_avr32/interrupts.c @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +void enable_interrupts(void) +{ + asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET)); +} + +int disable_interrupts(void) +{ + unsigned long sr; + + sr = sysreg_read(SR); + asm volatile("ssrf %0" : : "n"(SYSREG_GM_OFFSET)); + + return SYSREG_BFEXT(GM, sr); +} diff --git a/lib_avr32/memset.S b/lib_avr32/memset.S new file mode 100644 index 00000000000..dc3b09b42f9 --- /dev/null +++ b/lib_avr32/memset.S @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + /* + * r12: void *b + * r11: int c + * r10: size_t len + * + * Returns b in r12 + */ + .text + + .global memset + .type memset, @function + .align 2 +memset: + mov r9, r12 + mov r8, r12 + or r11, r11, r11 << 8 + andl r9, 3, COH + brne 1f + +2: or r11, r11, r11 << 16 + sub r10, 4 + brlt 5f + + /* Let's do some real work */ +4: st.w r8++, r11 + sub r10, 4 + brge 4b + + /* + * When we get here, we've got less than 4 bytes to set. r10 + * might be negative. + */ +5: sub r10, -4 + reteq r12 + + /* Fastpath ends here, exactly 32 bytes from memset */ + + /* Handle unaligned count or pointer */ + bld r10, 1 + brcc 6f + st.b r8++, r11 + st.b r8++, r11 + bld r10, 0 + retcc r12 +6: st.b r8++, r11 + mov pc, lr + + /* Handle unaligned pointer */ +1: sub r10, 4 + brlt 5b + add r10, r9 + lsl r9, 1 + add pc, r9 + st.b r8++, r11 + st.b r8++, r11 + st.b r8++, r11 + rjmp 2b + + .size memset, . - memset -- cgit v1.3.1 From 72a087e04705c26cad982879ebd06b5281bf825a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 24 Oct 2006 14:27:35 +0200 Subject: Add AT32AP CPU and AT32AP7000 SoC support Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the AT32AP CPU family and the AT32AP7000 chip, which is the first chip implementing the AVR32 architecture. The AT32AP CPU core is a high-performance implementation featuring a 7-stage pipeline, separate instruction- and data caches, and a MMU. For more information, please see the "AVR32 AP Technical Reference": http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf In addition to this, the AT32AP7000 chip comes with a large set of integrated peripherals, many of which are shared with the AT91 series of ARM-based microcontrollers from Atmel. Full data sheet is available here: http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf Signed-off-by: Haavard Skinnemoen --- Makefile | 3 + README | 4 + cpu/at32ap/Makefile | 50 +++ cpu/at32ap/at32ap7000/Makefile | 43 +++ cpu/at32ap/at32ap7000/devices.c | 448 +++++++++++++++++++++++++ cpu/at32ap/at32ap7000/hebi.c | 38 +++ cpu/at32ap/cache.c | 97 ++++++ cpu/at32ap/config.mk | 22 ++ cpu/at32ap/cpu.c | 83 +++++ cpu/at32ap/device.c | 126 +++++++ cpu/at32ap/entry.S | 65 ++++ cpu/at32ap/exception.c | 119 +++++++ cpu/at32ap/hsdramc.c | 155 +++++++++ cpu/at32ap/hsdramc1.h | 143 ++++++++ cpu/at32ap/hsmc3.h | 126 +++++++ cpu/at32ap/interrupts.c | 154 +++++++++ cpu/at32ap/pio.c | 94 ++++++ cpu/at32ap/pio2.h | 44 +++ cpu/at32ap/pm.c | 163 +++++++++ cpu/at32ap/sm.h | 204 +++++++++++ cpu/at32ap/start.S | 113 +++++++ include/asm-avr32/arch-at32ap7000/hmatrix2.h | 232 +++++++++++++ include/asm-avr32/arch-at32ap7000/memory-map.h | 61 ++++ include/asm-avr32/arch-at32ap7000/platform.h | 146 ++++++++ 24 files changed, 2733 insertions(+) create mode 100644 cpu/at32ap/Makefile create mode 100644 cpu/at32ap/at32ap7000/Makefile create mode 100644 cpu/at32ap/at32ap7000/devices.c create mode 100644 cpu/at32ap/at32ap7000/hebi.c create mode 100644 cpu/at32ap/cache.c create mode 100644 cpu/at32ap/config.mk create mode 100644 cpu/at32ap/cpu.c create mode 100644 cpu/at32ap/device.c create mode 100644 cpu/at32ap/entry.S create mode 100644 cpu/at32ap/exception.c create mode 100644 cpu/at32ap/hsdramc.c create mode 100644 cpu/at32ap/hsdramc1.h create mode 100644 cpu/at32ap/hsmc3.h create mode 100644 cpu/at32ap/interrupts.c create mode 100644 cpu/at32ap/pio.c create mode 100644 cpu/at32ap/pio2.h create mode 100644 cpu/at32ap/pm.c create mode 100644 cpu/at32ap/sm.h create mode 100644 cpu/at32ap/start.S create mode 100644 include/asm-avr32/arch-at32ap7000/hmatrix2.h create mode 100644 include/asm-avr32/arch-at32ap7000/memory-map.h create mode 100644 include/asm-avr32/arch-at32ap7000/platform.h (limited to 'include') diff --git a/Makefile b/Makefile index 5260a612ff3..2f3e886a969 100644 --- a/Makefile +++ b/Makefile @@ -2105,6 +2105,9 @@ pb1000_config : unconfig #======================================================================== # AVR32 #======================================================================== +######################################################################### +## AT32AP7xxx +######################################################################### ######################################################################### ## MIPS64 5Kc diff --git a/README b/README index 8405a9b0cd1..69af79a4576 100644 --- a/README +++ b/README @@ -132,6 +132,7 @@ Directory Hierarchy: - arm925t Files specific to ARM 925 CPUs - arm926ejs Files specific to ARM 926 CPUs - arm1136 Files specific to ARM 1136 CPUs + - at32ap Files specific to Atmel AVR32 AP CPUs - i386 Files specific to i386 CPUs - ixp Files specific to Intel XScale IXP CPUs - mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs @@ -257,6 +258,9 @@ The following options need to be configured: ---------------------- CONFIG_NIOS2 + AVR32 based CPUs: + ---------------------- + CONFIG_AT32AP - Board Type: Define exactly one of diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile new file mode 100644 index 00000000000..8ce79e9ef69 --- /dev/null +++ b/cpu/at32ap/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2005-2006 Atmel Corporation. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(CPU).a + +START := start.o +SOBJS := entry.o +COBJS := cpu.o hsdramc.o exception.o cache.o +COBJS += interrupts.o device.o pm.o pio.o +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $^ + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/at32ap/at32ap7000/Makefile b/cpu/at32ap/at32ap7000/Makefile new file mode 100644 index 00000000000..1cd94448663 --- /dev/null +++ b/cpu/at32ap/at32ap7000/Makefile @@ -0,0 +1,43 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(SOC).a + +COBJS := hebi.o devices.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $^ + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/at32ap/at32ap7000/devices.c b/cpu/at32ap/at32ap7000/devices.c new file mode 100644 index 00000000000..8b216e906a2 --- /dev/null +++ b/cpu/at32ap/at32ap7000/devices.c @@ -0,0 +1,448 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include + +#include "../sm.h" + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +const struct clock_domain chip_clock[] = { + [CLOCK_CPU] = { + .reg = SM_PM_CPU_MASK, + .id = CLOCK_CPU, + .bridge = NO_DEVICE, + }, + [CLOCK_HSB] = { + .reg = SM_PM_HSB_MASK, + .id = CLOCK_HSB, + .bridge = NO_DEVICE, + }, + [CLOCK_PBA] = { + .reg = SM_PM_PBA_MASK, + .id = CLOCK_PBA, + .bridge = DEVICE_PBA_BRIDGE, + }, + [CLOCK_PBB] = { + .reg = SM_PM_PBB_MASK, + .id = CLOCK_PBB, + .bridge = DEVICE_PBB_BRIDGE, + }, +}; + +static const struct resource hebi_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_HSB, 0 }, + }, + }, { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBB, 13 }, + }, + }, { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBB, 14 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 27, DEVICE_PIOE, GPIO_FUNC_A, 0 }, + }, + }, +}; +static const struct resource pba_bridge_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_HSB, 1 }, + } + }, { + .type = RESOURCE_CLOCK, + .u = { + /* HSB-HSB Bridge */ + .clock = { CLOCK_HSB, 4 }, + }, + }, +}; +static const struct resource pbb_bridge_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_HSB, 2 }, + }, + }, +}; +static const struct resource hramc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_HSB, 3 }, + }, + }, +}; +static const struct resource pioa_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBA, 10 }, + }, + }, +}; +static const struct resource piob_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBA, 11 }, + }, + }, +}; +static const struct resource pioc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBA, 12 }, + }, + }, +}; +static const struct resource piod_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBA, 13 }, + }, + }, +}; +static const struct resource pioe_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBA, 14 }, + }, + }, +}; +static const struct resource sm_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBB, 0 }, + }, + }, +}; +static const struct resource intc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBB, 1 }, + }, + }, +}; +static const struct resource hmatrix_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBB, 2 }, + }, + }, +}; +#if defined(CFG_HPDC) +static const struct resource hpdc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBA, 16 }, + }, + }, +}; +#endif +#if defined(CFG_MACB0) +static const struct resource macb0_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_HSB, 8 }, + }, + }, { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBB, 6 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 19, DEVICE_PIOC, GPIO_FUNC_A, 0 }, + }, + }, +}; +#endif +#if defined(CFG_MACB1) +static const struct resource macb1_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_HSB, 9 }, + }, + }, { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBB, 7 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 12, DEVICE_PIOC, GPIO_FUNC_B, 19 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 14, DEVICE_PIOD, GPIO_FUNC_B, 2 }, + }, + }, +}; +#endif +#if defined(CFG_LCDC) +static const struct resource lcdc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_HSB, 7 }, + }, + }, +}; +#endif +#if defined(CFG_USART0) +static const struct resource usart0_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBA, 3 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 2, DEVICE_PIOA, GPIO_FUNC_B, 8 }, + }, + }, +}; +#endif +#if defined(CFG_USART1) +static const struct resource usart1_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBA, 4 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 2, DEVICE_PIOA, GPIO_FUNC_A, 17 }, + }, + }, +}; +#endif +#if defined(CFG_USART2) +static const struct resource usart2_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBA, 5 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 26 }, + }, + }, +}; +#endif +#if defined(CFG_USART3) +static const struct resource usart3_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBA, 6 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 17 }, + }, + }, +}; +#endif +#if defined(CFG_MMCI) +static const struct resource mmci_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_PBB, 9 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 6, DEVICE_PIOA, GPIO_FUNC_A, 10 }, + }, + }, +}; +#endif +#if defined(CFG_DMAC) +static const struct resource dmac_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_HSB, 10 }, + }, + }, +}; +#endif + +const struct device chip_device[] = { + [DEVICE_HEBI] = { + .regs = (void *)HSMC_BASE, + .nr_resources = ARRAY_SIZE(hebi_resource), + .resource = hebi_resource, + }, + [DEVICE_PBA_BRIDGE] = { + .nr_resources = ARRAY_SIZE(pba_bridge_resource), + .resource = pba_bridge_resource, + }, + [DEVICE_PBB_BRIDGE] = { + .nr_resources = ARRAY_SIZE(pbb_bridge_resource), + .resource = pbb_bridge_resource, + }, + [DEVICE_HRAMC] = { + .nr_resources = ARRAY_SIZE(hramc_resource), + .resource = hramc_resource, + }, + [DEVICE_PIOA] = { + .regs = (void *)PIOA_BASE, + .nr_resources = ARRAY_SIZE(pioa_resource), + .resource = pioa_resource, + }, + [DEVICE_PIOB] = { + .regs = (void *)PIOB_BASE, + .nr_resources = ARRAY_SIZE(piob_resource), + .resource = piob_resource, + }, + [DEVICE_PIOC] = { + .regs = (void *)PIOC_BASE, + .nr_resources = ARRAY_SIZE(pioc_resource), + .resource = pioc_resource, + }, + [DEVICE_PIOD] = { + .regs = (void *)PIOD_BASE, + .nr_resources = ARRAY_SIZE(piod_resource), + .resource = piod_resource, + }, + [DEVICE_PIOE] = { + .regs = (void *)PIOE_BASE, + .nr_resources = ARRAY_SIZE(pioe_resource), + .resource = pioe_resource, + }, + [DEVICE_SM] = { + .regs = (void *)SM_BASE, + .nr_resources = ARRAY_SIZE(sm_resource), + .resource = sm_resource, + }, + [DEVICE_INTC] = { + .regs = (void *)INTC_BASE, + .nr_resources = ARRAY_SIZE(intc_resource), + .resource = intc_resource, + }, + [DEVICE_HMATRIX] = { + .regs = (void *)HMATRIX_BASE, + .nr_resources = ARRAY_SIZE(hmatrix_resource), + .resource = hmatrix_resource, + }, +#if defined(CFG_HPDC) + [DEVICE_HPDC] = { + .nr_resources = ARRAY_SIZE(hpdc_resource), + .resource = hpdc_resource, + }, +#endif +#if defined(CFG_MACB0) + [DEVICE_MACB0] = { + .regs = (void *)MACB0_BASE, + .nr_resources = ARRAY_SIZE(macb0_resource), + .resource = macb0_resource, + }, +#endif +#if defined(CFG_MACB1) + [DEVICE_MACB1] = { + .regs = (void *)MACB1_BASE, + .nr_resources = ARRAY_SIZE(macb1_resource), + .resource = macb1_resource, + }, +#endif +#if defined(CFG_LCDC) + [DEVICE_LCDC] = { + .nr_resources = ARRAY_SIZE(lcdc_resource), + .resource = lcdc_resource, + }, +#endif +#if defined(CFG_USART0) + [DEVICE_USART0] = { + .regs = (void *)USART0_BASE, + .nr_resources = ARRAY_SIZE(usart0_resource), + .resource = usart0_resource, + }, +#endif +#if defined(CFG_USART1) + [DEVICE_USART1] = { + .regs = (void *)USART1_BASE, + .nr_resources = ARRAY_SIZE(usart1_resource), + .resource = usart1_resource, + }, +#endif +#if defined(CFG_USART2) + [DEVICE_USART2] = { + .regs = (void *)USART2_BASE, + .nr_resources = ARRAY_SIZE(usart2_resource), + .resource = usart2_resource, + }, +#endif +#if defined(CFG_USART3) + [DEVICE_USART3] = { + .regs = (void *)USART3_BASE, + .nr_resources = ARRAY_SIZE(usart3_resource), + .resource = usart3_resource, + }, +#endif +#if defined(CFG_MMCI) + [DEVICE_MMCI] = { + .regs = (void *)MMCI_BASE, + .nr_resources = ARRAY_SIZE(mmci_resource), + .resource = mmci_resource, + }, +#endif +#if defined(CFG_DMAC) + [DEVICE_DMAC] = { + .regs = (void *)DMAC_BASE, + .nr_resources = ARRAY_SIZE(dmac_resource), + .resource = dmac_resource, + }, +#endif +}; diff --git a/cpu/at32ap/at32ap7000/hebi.c b/cpu/at32ap/at32ap7000/hebi.c new file mode 100644 index 00000000000..3b32adf1ea9 --- /dev/null +++ b/cpu/at32ap/at32ap7000/hebi.c @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +#include +#include +#include + +void cpu_enable_sdram(void) +{ + const struct device *hmatrix; + + hmatrix = get_device(DEVICE_HMATRIX); + + /* Set the SDRAM_ENABLE bit in the HEBI SFR */ + hmatrix2_writel(hmatrix, SFR4, 1 << 1); +} diff --git a/cpu/at32ap/cache.c b/cpu/at32ap/cache.c new file mode 100644 index 00000000000..41fb5aa0473 --- /dev/null +++ b/cpu/at32ap/cache.c @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include + +void dcache_clean_range(volatile void *start, size_t size) +{ + unsigned long v, begin, end, linesz; + + linesz = CFG_DCACHE_LINESZ; + + /* You asked for it, you got it */ + begin = (unsigned long)start & ~(linesz - 1); + end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); + + for (v = begin; v < end; v += linesz) + dcache_clean_line((void *)v); + + sync_write_buffer(); +} + +void dcache_invalidate_range(volatile void *start, size_t size) +{ + unsigned long v, begin, end, linesz; + + linesz = CFG_DCACHE_LINESZ; + + /* You asked for it, you got it */ + begin = (unsigned long)start & ~(linesz - 1); + end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); + + for (v = begin; v < end; v += linesz) + dcache_invalidate_line((void *)v); +} + +void dcache_flush_range(volatile void *start, size_t size) +{ + unsigned long v, begin, end, linesz; + + linesz = CFG_DCACHE_LINESZ; + + /* You asked for it, you got it */ + begin = (unsigned long)start & ~(linesz - 1); + end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); + + for (v = begin; v < end; v += linesz) + dcache_flush_line((void *)v); + + sync_write_buffer(); +} + +void icache_invalidate_range(volatile void *start, size_t size) +{ + unsigned long v, begin, end, linesz; + + linesz = CFG_ICACHE_LINESZ; + + /* You asked for it, you got it */ + begin = (unsigned long)start & ~(linesz - 1); + end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); + + for (v = begin; v < end; v += linesz) + icache_invalidate_line((void *)v); +} + +/* + * This is called after loading something into memory. We need to + * make sure that everything that was loaded is actually written to + * RAM, and that the icache will look for it. Cleaning the dcache and + * invalidating the icache will do the trick. + */ +void flush_cache (unsigned long start_addr, unsigned long size) +{ + dcache_clean_range((void *)start_addr, size); + icache_invalidate_range((void *)start_addr, size); +} diff --git a/cpu/at32ap/config.mk b/cpu/at32ap/config.mk new file mode 100644 index 00000000000..1c12169221f --- /dev/null +++ b/cpu/at32ap/config.mk @@ -0,0 +1,22 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -mcpu=ap7000 diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c new file mode 100644 index 00000000000..37e3ea040be --- /dev/null +++ b/cpu/at32ap/cpu.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include + +#include +#include +#include + +#include +#include + +#include "hsmc3.h" + +DECLARE_GLOBAL_DATA_PTR; + +int cpu_init(void) +{ + const struct device *hebi; + extern void _evba(void); + char *p; + + gd->cpu_hz = CFG_OSC0_HZ; + + /* fff03400: 00010001 04030402 00050005 10011103 */ + hebi = get_device(DEVICE_HEBI); + hsmc3_writel(hebi, MODE0, 0x00031103); + hsmc3_writel(hebi, CYCLE0, 0x000c000d); + hsmc3_writel(hebi, PULSE0, 0x0b0a0906); + hsmc3_writel(hebi, SETUP0, 0x00010002); + + pm_init(); + + sysreg_write(EVBA, (unsigned long)&_evba); + asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET)); + gd->console_uart = get_device(CFG_CONSOLE_UART_DEV); + + /* Lock everything that mess with the flash in the icache */ + for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ); + p += CFG_ICACHE_LINESZ) + asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory"); + + return 0; +} + +void prepare_to_boot(void) +{ + /* Flush both caches and the write buffer */ + asm volatile("cache %0[4], 010\n\t" + "cache %0[0], 000\n\t" + "sync 0" : : "r"(0) : "memory"); +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + /* This will reset the CPU core, caches, MMU and all internal busses */ + __builtin_mtdr(8, 1 << 13); /* set DC:DBE */ + __builtin_mtdr(8, 1 << 30); /* set DC:RES */ + + /* Flush the pipeline before we declare it a failure */ + asm volatile("sub pc, pc, -4"); + + return -1; +} diff --git a/cpu/at32ap/device.c b/cpu/at32ap/device.c new file mode 100644 index 00000000000..89914b6b56b --- /dev/null +++ b/cpu/at32ap/device.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +#include "sm.h" + +struct device_state { + int refcount; +}; + +static struct device_state device_state[NR_DEVICES]; + +static int claim_resource(const struct resource *res) +{ + int ret = 0; + + switch (res->type) { + case RESOURCE_GPIO: + ret = gpio_set_func(res->u.gpio.gpio_dev, + res->u.gpio.start, + res->u.gpio.nr_pins, + res->u.gpio.func); + break; + case RESOURCE_CLOCK: + ret = pm_enable_clock(res->u.clock.id, res->u.clock.index); + break; + } + + return ret; +} + +static void free_resource(const struct resource *res) +{ + switch (res->type) { + case RESOURCE_GPIO: + gpio_free(res->u.gpio.gpio_dev, res->u.gpio.start, + res->u.gpio.nr_pins); + break; + case RESOURCE_CLOCK: + pm_disable_clock(res->u.clock.id, res->u.clock.index); + break; + } +} + +static int init_dev(const struct device *dev) +{ + unsigned int i; + int ret = 0; + + for (i = 0; i < dev->nr_resources; i++) { + ret = claim_resource(&dev->resource[i]); + if (ret) + goto cleanup; + } + + return 0; + +cleanup: + while (i--) + free_resource(&dev->resource[i]); + + return ret; +} + +const struct device *get_device(enum device_id devid) +{ + struct device_state *devstate; + const struct device *dev; + unsigned long flags; + int initialized = 0; + int ret = 0; + + devstate = &device_state[devid]; + dev = &chip_device[devid]; + + flags = disable_interrupts(); + if (devstate->refcount++) + initialized = 1; + if (flags) + enable_interrupts(); + + if (!initialized) + ret = init_dev(dev); + + return ret ? NULL : dev; +} + +void put_device(const struct device *dev) +{ + struct device_state *devstate; + unsigned long devid, flags; + + devid = (unsigned long)(dev - chip_device) / sizeof(struct device); + devstate = &device_state[devid]; + + flags = disable_interrupts(); + devstate--; + if (!devstate) { + unsigned int i; + for (i = 0; i < dev->nr_resources; i++) + free_resource(&dev->resource[i]); + } + if (flags) + enable_interrupts(); +} diff --git a/cpu/at32ap/entry.S b/cpu/at32ap/entry.S new file mode 100644 index 00000000000..b52d798be3d --- /dev/null +++ b/cpu/at32ap/entry.S @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include + + .section .text.exception,"ax" + .global _evba + .type _evba,@function + .align 10 +_evba: + .irp x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 + .align 2 + rjmp unknown_exception + .endr + + .global timer_interrupt_handler + .type timer_interrupt_handler,@function + .align 2 +timer_interrupt_handler: + /* + * Increment timer_overflow and re-write COMPARE with 0xffffffff. + * + * We're running at interrupt level 3, so we don't need to save + * r8-r12 or lr to the stack. + */ + mov r8, lo(timer_overflow) + orh r8, hi(timer_overflow) + ld.w r9, r8[0] + mov r10, -1 + mtsr SYSREG_COMPARE, r10 + sub r9, -1 + st.w r8[0], r9 + rete + + .type unknown_exception, @function +unknown_exception: + pushm r0-r12 + sub r8, sp, REG_R12 - REG_R0 - 4 + mov r9, lr + mfsr r10, SYSREG_RAR_EX + mfsr r11, SYSREG_RSR_EX + pushm r8-r11 + mfsr r12, SYSREG_ECR + mov r11, sp + rcall do_unknown_exception +1: rjmp 1b diff --git a/cpu/at32ap/exception.c b/cpu/at32ap/exception.c new file mode 100644 index 00000000000..4123c446167 --- /dev/null +++ b/cpu/at32ap/exception.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include + +static const char * const cpu_modes[8] = { + "Application", "Supervisor", "Interrupt level 0", "Interrupt level 1", + "Interrupt level 2", "Interrupt level 3", "Exception", "NMI" +}; + +static void dump_mem(const char *str, unsigned long bottom, unsigned long top) +{ + unsigned long p; + int i; + + printf("%s(0x%08lx to 0x%08lx)\n", str, bottom, top); + + for (p = bottom & ~31; p < top; ) { + printf("%04lx: ", p & 0xffff); + + for (i = 0; i < 8; i++, p += 4) { + unsigned int val; + + if (p < bottom || p >= top) + printf(" "); + else { + val = *(unsigned long *)p; + printf("%08x ", val); + } + } + printf("\n"); + } +} + +void do_unknown_exception(unsigned int ecr, struct pt_regs *regs) +{ + unsigned int mode; + + printf("\n *** Unhandled exception %u at PC=0x%08lx\n", ecr, regs->pc); + + switch (ecr) { + case ECR_BUS_ERROR_WRITE: + case ECR_BUS_ERROR_READ: + printf("Bus error at address 0x%08lx\n", + sysreg_read(BEAR)); + break; + case ECR_TLB_MULTIPLE: + case ECR_ADDR_ALIGN_X: + case ECR_PROTECTION_X: + case ECR_ADDR_ALIGN_R: + case ECR_ADDR_ALIGN_W: + case ECR_PROTECTION_R: + case ECR_PROTECTION_W: + case ECR_DTLB_MODIFIED: + case ECR_TLB_MISS_X: + case ECR_TLB_MISS_R: + case ECR_TLB_MISS_W: + printf("MMU exception at address 0x%08lx\n", + sysreg_read(TLBEAR)); + break; + } + + printf(" pc: %08lx lr: %08lx sp: %08lx r12: %08lx\n", + regs->pc, regs->lr, regs->sp, regs->r12); + printf(" r11: %08lx r10: %08lx r9: %08lx r8: %08lx\n", + regs->r11, regs->r10, regs->r9, regs->r8); + printf(" r7: %08lx r6: %08lx r5: %08lx r4: %08lx\n", + regs->r7, regs->r6, regs->r5, regs->r4); + printf(" r3: %08lx r2: %08lx r1: %08lx r0: %08lx\n", + regs->r3, regs->r2, regs->r1, regs->r0); + printf("Flags: %c%c%c%c%c\n", + regs->sr & SR_Q ? 'Q' : 'q', + regs->sr & SR_V ? 'V' : 'v', + regs->sr & SR_N ? 'N' : 'n', + regs->sr & SR_Z ? 'Z' : 'z', + regs->sr & SR_C ? 'C' : 'c'); + printf("Mode bits: %c%c%c%c%c%c%c%c%c\n", + regs->sr & SR_H ? 'H' : 'h', + regs->sr & SR_R ? 'R' : 'r', + regs->sr & SR_J ? 'J' : 'j', + regs->sr & SR_EM ? 'E' : 'e', + regs->sr & SR_I3M ? '3' : '.', + regs->sr & SR_I2M ? '2' : '.', + regs->sr & SR_I1M ? '1' : '.', + regs->sr & SR_I0M ? '0' : '.', + regs->sr & SR_GM ? 'G' : 'g'); + mode = (regs->sr >> SYSREG_M0_OFFSET) & 7; + printf("CPU Mode: %s\n", cpu_modes[mode]); + + /* Avoid exception loops */ + if (regs->sp >= CFG_INIT_SP_ADDR + || regs->sp < (CFG_INIT_SP_ADDR - CONFIG_STACKSIZE)) + printf("\nStack pointer seems bogus, won't do stack dump\n"); + else + dump_mem("\nStack: ", regs->sp, CFG_INIT_SP_ADDR); + + panic("Unhandled exception\n"); +} diff --git a/cpu/at32ap/hsdramc.c b/cpu/at32ap/hsdramc.c new file mode 100644 index 00000000000..f36da354528 --- /dev/null +++ b/cpu/at32ap/hsdramc.c @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifdef CFG_HSDRAMC +#include +#include + +#include + +#include "hsdramc1.h" + +struct hsdramc { + const struct device *hebi; + void *regs; +}; + +static struct hsdramc hsdramc; + +unsigned long sdram_init(const struct sdram_info *info) +{ + unsigned long *sdram = (unsigned long *)uncached(info->phys_addr); + unsigned long sdram_size; + unsigned long tmp; + unsigned long bus_hz; + unsigned int i; + + hsdramc.hebi = get_device(DEVICE_HEBI); + if (!hsdramc.hebi) + return 0; + + /* FIXME: Both of these lines are complete hacks */ + hsdramc.regs = hsdramc.hebi->regs + 0x400; + bus_hz = pm_get_clock_freq(hsdramc.hebi->resource[0].u.clock.id); + + cpu_enable_sdram(); + + tmp = (HSDRAMC1_BF(NC, info->col_bits - 8) + | HSDRAMC1_BF(NR, info->row_bits - 11) + | HSDRAMC1_BF(NB, info->bank_bits - 1) + | HSDRAMC1_BF(CAS, info->cas) + | HSDRAMC1_BF(TWR, info->twr) + | HSDRAMC1_BF(TRC, info->trc) + | HSDRAMC1_BF(TRP, info->trp) + | HSDRAMC1_BF(TRCD, info->trcd) + | HSDRAMC1_BF(TRAS, info->tras) + | HSDRAMC1_BF(TXSR, info->txsr)); + +#ifdef CFG_SDRAM_16BIT + tmp |= HSDRAMC1_BIT(DBW); + sdram_size = 1 << (info->row_bits + info->col_bits + + info->bank_bits + 1); +#else + sdram_size = 1 << (info->row_bits + info->col_bits + + info->bank_bits + 2); +#endif + + hsdramc1_writel(&hsdramc, CR, tmp); + + /* + * Initialization sequence for SDRAM, from the data sheet: + * + * 1. A minimum pause of 200 us is provided to precede any + * signal toggle. + */ + udelay(200); + + /* + * 2. A Precharge All command is issued to the SDRAM + */ + hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_BANKS_PRECHARGE); + hsdramc1_readl(&hsdramc, MR); + writel(0, sdram); + + /* + * 3. Eight auto-refresh (CBR) cycles are provided + */ + hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_AUTO_REFRESH); + hsdramc1_readl(&hsdramc, MR); + for (i = 0; i < 8; i++) + writel(0, sdram); + + /* + * 4. A mode register set (MRS) cycle is issued to program + * SDRAM parameters, in particular CAS latency and burst + * length. + * + * CAS from info struct, burst length 1, serial burst type + */ + hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_LOAD_MODE); + hsdramc1_readl(&hsdramc, MR); + writel(0, sdram + (info->cas << 4)); + + /* + * 5. A Normal Mode command is provided, 3 clocks after tMRD + * is met. + * + * From the timing diagram, it looks like tMRD is 3 + * cycles...try a dummy read from the peripheral bus. + */ + hsdramc1_readl(&hsdramc, MR); + hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_NORMAL); + hsdramc1_readl(&hsdramc, MR); + writel(0, sdram); + + /* + * 6. Write refresh rate into SDRAMC refresh timer count + * register (refresh rate = timing between refresh cycles). + * + * 15.6 us is a typical value for a burst of length one + */ + hsdramc1_writel(&hsdramc, TR, (156 * (bus_hz / 1000)) / 10000); + + printf("SDRAM: %u MB at address 0x%08lx\n", + sdram_size >> 20, info->phys_addr); + + printf("Testing SDRAM..."); + for (i = 0; i < sdram_size / 4; i++) + sdram[i] = i; + + for (i = 0; i < sdram_size / 4; i++) { + tmp = sdram[i]; + if (tmp != i) { + printf("FAILED at address 0x%08lx\n", + info->phys_addr + i * 4); + printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i); + return 0; + } + } + + puts("OK\n"); + + return sdram_size; +} + +#endif /* CFG_HSDRAMC */ diff --git a/cpu/at32ap/hsdramc1.h b/cpu/at32ap/hsdramc1.h new file mode 100644 index 00000000000..ce229bca1fb --- /dev/null +++ b/cpu/at32ap/hsdramc1.h @@ -0,0 +1,143 @@ +/* + * Register definitions for SDRAM Controller + */ +#ifndef __ASM_AVR32_HSDRAMC1_H__ +#define __ASM_AVR32_HSDRAMC1_H__ + +/* HSDRAMC1 register offsets */ +#define HSDRAMC1_MR 0x0000 +#define HSDRAMC1_TR 0x0004 +#define HSDRAMC1_CR 0x0008 +#define HSDRAMC1_HSR 0x000c +#define HSDRAMC1_LPR 0x0010 +#define HSDRAMC1_IER 0x0014 +#define HSDRAMC1_IDR 0x0018 +#define HSDRAMC1_IMR 0x001c +#define HSDRAMC1_ISR 0x0020 +#define HSDRAMC1_MDR 0x0024 +#define HSDRAMC1_VERSION 0x00fc + +/* Bitfields in MR */ +#define HSDRAMC1_MODE_OFFSET 0 +#define HSDRAMC1_MODE_SIZE 3 + +/* Bitfields in TR */ +#define HSDRAMC1_COUNT_OFFSET 0 +#define HSDRAMC1_COUNT_SIZE 12 + +/* Bitfields in CR */ +#define HSDRAMC1_NC_OFFSET 0 +#define HSDRAMC1_NC_SIZE 2 +#define HSDRAMC1_NR_OFFSET 2 +#define HSDRAMC1_NR_SIZE 2 +#define HSDRAMC1_NB_OFFSET 4 +#define HSDRAMC1_NB_SIZE 1 +#define HSDRAMC1_CAS_OFFSET 5 +#define HSDRAMC1_CAS_SIZE 2 +#define HSDRAMC1_DBW_OFFSET 7 +#define HSDRAMC1_DBW_SIZE 1 +#define HSDRAMC1_TWR_OFFSET 8 +#define HSDRAMC1_TWR_SIZE 4 +#define HSDRAMC1_TRC_OFFSET 12 +#define HSDRAMC1_TRC_SIZE 4 +#define HSDRAMC1_TRP_OFFSET 16 +#define HSDRAMC1_TRP_SIZE 4 +#define HSDRAMC1_TRCD_OFFSET 20 +#define HSDRAMC1_TRCD_SIZE 4 +#define HSDRAMC1_TRAS_OFFSET 24 +#define HSDRAMC1_TRAS_SIZE 4 +#define HSDRAMC1_TXSR_OFFSET 28 +#define HSDRAMC1_TXSR_SIZE 4 + +/* Bitfields in HSR */ +#define HSDRAMC1_DA_OFFSET 0 +#define HSDRAMC1_DA_SIZE 1 + +/* Bitfields in LPR */ +#define HSDRAMC1_LPCB_OFFSET 0 +#define HSDRAMC1_LPCB_SIZE 2 +#define HSDRAMC1_PASR_OFFSET 4 +#define HSDRAMC1_PASR_SIZE 3 +#define HSDRAMC1_TCSR_OFFSET 8 +#define HSDRAMC1_TCSR_SIZE 2 +#define HSDRAMC1_DS_OFFSET 10 +#define HSDRAMC1_DS_SIZE 2 +#define HSDRAMC1_TIMEOUT_OFFSET 12 +#define HSDRAMC1_TIMEOUT_SIZE 2 + +/* Bitfields in IDR */ +#define HSDRAMC1_RES_OFFSET 0 +#define HSDRAMC1_RES_SIZE 1 + +/* Bitfields in MDR */ +#define HSDRAMC1_MD_OFFSET 0 +#define HSDRAMC1_MD_SIZE 2 + +/* Bitfields in VERSION */ +#define HSDRAMC1_VERSION_OFFSET 0 +#define HSDRAMC1_VERSION_SIZE 12 +#define HSDRAMC1_MFN_OFFSET 16 +#define HSDRAMC1_MFN_SIZE 3 + +/* Constants for MODE */ +#define HSDRAMC1_MODE_NORMAL 0 +#define HSDRAMC1_MODE_NOP 1 +#define HSDRAMC1_MODE_BANKS_PRECHARGE 2 +#define HSDRAMC1_MODE_LOAD_MODE 3 +#define HSDRAMC1_MODE_AUTO_REFRESH 4 +#define HSDRAMC1_MODE_EXT_LOAD_MODE 5 +#define HSDRAMC1_MODE_POWER_DOWN 6 + +/* Constants for NC */ +#define HSDRAMC1_NC_8_COLUMN_BITS 0 +#define HSDRAMC1_NC_9_COLUMN_BITS 1 +#define HSDRAMC1_NC_10_COLUMN_BITS 2 +#define HSDRAMC1_NC_11_COLUMN_BITS 3 + +/* Constants for NR */ +#define HSDRAMC1_NR_11_ROW_BITS 0 +#define HSDRAMC1_NR_12_ROW_BITS 1 +#define HSDRAMC1_NR_13_ROW_BITS 2 + +/* Constants for NB */ +#define HSDRAMC1_NB_TWO_BANKS 0 +#define HSDRAMC1_NB_FOUR_BANKS 1 + +/* Constants for CAS */ +#define HSDRAMC1_CAS_ONE_CYCLE 1 +#define HSDRAMC1_CAS_TWO_CYCLES 2 + +/* Constants for DBW */ +#define HSDRAMC1_DBW_32_BITS 0 +#define HSDRAMC1_DBW_16_BITS 1 + +/* Constants for TIMEOUT */ +#define HSDRAMC1_TIMEOUT_AFTER_END 0 +#define HSDRAMC1_TIMEOUT_64_CYC_AFTER_END 1 +#define HSDRAMC1_TIMEOUT_128_CYC_AFTER_END 2 + +/* Constants for MD */ +#define HSDRAMC1_MD_SDRAM 0 +#define HSDRAMC1_MD_LOW_POWER_SDRAM 1 + +/* Bit manipulation macros */ +#define HSDRAMC1_BIT(name) \ + (1 << HSDRAMC1_##name##_OFFSET) +#define HSDRAMC1_BF(name,value) \ + (((value) & ((1 << HSDRAMC1_##name##_SIZE) - 1)) \ + << HSDRAMC1_##name##_OFFSET) +#define HSDRAMC1_BFEXT(name,value) \ + (((value) >> HSDRAMC1_##name##_OFFSET) \ + & ((1 << HSDRAMC1_##name##_SIZE) - 1)) +#define HSDRAMC1_BFINS(name,value,old) \ + (((old) & ~(((1 << HSDRAMC1_##name##_SIZE) - 1) \ + << HSDRAMC1_##name##_OFFSET)) \ + | HSDRAMC1_BF(name,value)) + +/* Register access macros */ +#define hsdramc1_readl(port,reg) \ + readl((port)->regs + HSDRAMC1_##reg) +#define hsdramc1_writel(port,reg,value) \ + writel((value), (port)->regs + HSDRAMC1_##reg) + +#endif /* __ASM_AVR32_HSDRAMC1_H__ */ diff --git a/cpu/at32ap/hsmc3.h b/cpu/at32ap/hsmc3.h new file mode 100644 index 00000000000..ec78cee7147 --- /dev/null +++ b/cpu/at32ap/hsmc3.h @@ -0,0 +1,126 @@ +/* + * Register definitions for Static Memory Controller + */ +#ifndef __CPU_AT32AP_HSMC3_H__ +#define __CPU_AT32AP_HSMC3_H__ + +/* HSMC3 register offsets */ +#define HSMC3_SETUP0 0x0000 +#define HSMC3_PULSE0 0x0004 +#define HSMC3_CYCLE0 0x0008 +#define HSMC3_MODE0 0x000c +#define HSMC3_SETUP1 0x0010 +#define HSMC3_PULSE1 0x0014 +#define HSMC3_CYCLE1 0x0018 +#define HSMC3_MODE1 0x001c +#define HSMC3_SETUP2 0x0020 +#define HSMC3_PULSE2 0x0024 +#define HSMC3_CYCLE2 0x0028 +#define HSMC3_MODE2 0x002c +#define HSMC3_SETUP3 0x0030 +#define HSMC3_PULSE3 0x0034 +#define HSMC3_CYCLE3 0x0038 +#define HSMC3_MODE3 0x003c +#define HSMC3_SETUP4 0x0040 +#define HSMC3_PULSE4 0x0044 +#define HSMC3_CYCLE4 0x0048 +#define HSMC3_MODE4 0x004c +#define HSMC3_SETUP5 0x0050 +#define HSMC3_PULSE5 0x0054 +#define HSMC3_CYCLE5 0x0058 +#define HSMC3_MODE5 0x005c + +/* Bitfields in SETUP0 */ +#define HSMC3_NWE_SETUP_OFFSET 0 +#define HSMC3_NWE_SETUP_SIZE 6 +#define HSMC3_NCS_WR_SETUP_OFFSET 8 +#define HSMC3_NCS_WR_SETUP_SIZE 6 +#define HSMC3_NRD_SETUP_OFFSET 16 +#define HSMC3_NRD_SETUP_SIZE 6 +#define HSMC3_NCS_RD_SETUP_OFFSET 24 +#define HSMC3_NCS_RD_SETUP_SIZE 6 + +/* Bitfields in PULSE0 */ +#define HSMC3_NWE_PULSE_OFFSET 0 +#define HSMC3_NWE_PULSE_SIZE 7 +#define HSMC3_NCS_WR_PULSE_OFFSET 8 +#define HSMC3_NCS_WR_PULSE_SIZE 7 +#define HSMC3_NRD_PULSE_OFFSET 16 +#define HSMC3_NRD_PULSE_SIZE 7 +#define HSMC3_NCS_RD_PULSE_OFFSET 24 +#define HSMC3_NCS_RD_PULSE_SIZE 7 + +/* Bitfields in CYCLE0 */ +#define HSMC3_NWE_CYCLE_OFFSET 0 +#define HSMC3_NWE_CYCLE_SIZE 9 +#define HSMC3_NRD_CYCLE_OFFSET 16 +#define HSMC3_NRD_CYCLE_SIZE 9 + +/* Bitfields in MODE0 */ +#define HSMC3_READ_MODE_OFFSET 0 +#define HSMC3_READ_MODE_SIZE 1 +#define HSMC3_WRITE_MODE_OFFSET 1 +#define HSMC3_WRITE_MODE_SIZE 1 +#define HSMC3_EXNW_MODE_OFFSET 4 +#define HSMC3_EXNW_MODE_SIZE 2 +#define HSMC3_BAT_OFFSET 8 +#define HSMC3_BAT_SIZE 1 +#define HSMC3_DBW_OFFSET 12 +#define HSMC3_DBW_SIZE 2 +#define HSMC3_TDF_CYCLES_OFFSET 16 +#define HSMC3_TDF_CYCLES_SIZE 4 +#define HSMC3_TDF_MODE_OFFSET 20 +#define HSMC3_TDF_MODE_SIZE 1 +#define HSMC3_PMEN_OFFSET 24 +#define HSMC3_PMEN_SIZE 1 +#define HSMC3_PS_OFFSET 28 +#define HSMC3_PS_SIZE 2 + +/* Bitfields in MODE1 */ +#define HSMC3_PD_OFFSET 28 +#define HSMC3_PD_SIZE 2 + +/* Constants for READ_MODE */ +#define HSMC3_READ_MODE_NCS_CONTROLLED 0 +#define HSMC3_READ_MODE_NRD_CONTROLLED 1 + +/* Constants for WRITE_MODE */ +#define HSMC3_WRITE_MODE_NCS_CONTROLLED 0 +#define HSMC3_WRITE_MODE_NWE_CONTROLLED 1 + +/* Constants for EXNW_MODE */ +#define HSMC3_EXNW_MODE_DISABLED 0 +#define HSMC3_EXNW_MODE_RESERVED 1 +#define HSMC3_EXNW_MODE_FROZEN 2 +#define HSMC3_EXNW_MODE_READY 3 + +/* Constants for BAT */ +#define HSMC3_BAT_BYTE_SELECT 0 +#define HSMC3_BAT_BYTE_WRITE 1 + +/* Constants for DBW */ +#define HSMC3_DBW_8_BITS 0 +#define HSMC3_DBW_16_BITS 1 +#define HSMC3_DBW_32_BITS 2 + +/* Bit manipulation macros */ +#define HSMC3_BIT(name) \ + (1 << HSMC3_##name##_OFFSET) +#define HSMC3_BF(name,value) \ + (((value) & ((1 << HSMC3_##name##_SIZE) - 1)) \ + << HSMC3_##name##_OFFSET) +#define HSMC3_BFEXT(name,value) \ + (((value) >> HSMC3_##name##_OFFSET) \ + & ((1 << HSMC3_##name##_SIZE) - 1)) +#define HSMC3_BFINS(name,value,old)\ + (((old) & ~(((1 << HSMC3_##name##_SIZE) - 1) \ + << HSMC3_##name##_OFFSET)) \ + | HSMC3_BF(name,value)) + +/* Register access macros */ +#define hsmc3_readl(port,reg) \ + readl((port)->regs + HSMC3_##reg) +#define hsmc3_writel(port,reg,value) \ + writel((value), (port)->regs + HSMC3_##reg) + +#endif /* __CPU_AT32AP_HSMC3_H__ */ diff --git a/cpu/at32ap/interrupts.c b/cpu/at32ap/interrupts.c new file mode 100644 index 00000000000..d720cfa942b --- /dev/null +++ b/cpu/at32ap/interrupts.c @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include +#include +#include +#include + +#include + +#define HANDLER_MASK 0x00ffffff +#define INTLEV_SHIFT 30 +#define INTLEV_MASK 0x00000003 + +DECLARE_GLOBAL_DATA_PTR; + +/* Incremented whenever COUNT reaches 0xffffffff by timer_interrupt_handler */ +volatile unsigned long timer_overflow; + +/* + * Instead of dividing by get_tbclk(), multiply by this constant and + * right-shift the result by 32 bits. + */ +static unsigned long tb_factor; + +static const struct device *intc_dev; + +unsigned long get_tbclk(void) +{ + return gd->cpu_hz; +} + +unsigned long long get_ticks(void) +{ + unsigned long lo, hi_now, hi_prev; + + do { + hi_prev = timer_overflow; + lo = sysreg_read(COUNT); + hi_now = timer_overflow; + } while (hi_prev != hi_now); + + return ((unsigned long long)hi_now << 32) | lo; +} + +void reset_timer(void) +{ + sysreg_write(COUNT, 0); + cpu_sync_pipeline(); /* process any pending interrupts */ + timer_overflow = 0; +} + +unsigned long get_timer(unsigned long base) +{ + u64 now = get_ticks(); + + now *= tb_factor; + return (unsigned long)(now >> 32) - base; +} + +void set_timer(unsigned long t) +{ + unsigned long long ticks = t; + unsigned long lo, hi, hi_new; + + ticks = (ticks * get_tbclk()) / CFG_HZ; + hi = ticks >> 32; + lo = ticks & 0xffffffffUL; + + do { + timer_overflow = hi; + sysreg_write(COUNT, lo); + hi_new = timer_overflow; + } while (hi_new != hi); +} + +/* + * For short delays only. It will overflow after a few seconds. + */ +void udelay(unsigned long usec) +{ + unsigned long now, end; + + now = sysreg_read(COUNT); + + end = ((usec * (get_tbclk() / 10000)) + 50) / 100; + end += now; + + while (now > end) + now = sysreg_read(COUNT); + + while (now < end) + now = sysreg_read(COUNT); +} + +static int set_interrupt_handler(unsigned int nr, void (*handler)(void), + unsigned int priority) +{ + unsigned long intpr; + unsigned long handler_addr = (unsigned long)handler; + + if ((handler_addr & HANDLER_MASK) != handler_addr + || (priority & INTLEV_MASK) != priority) + return -EINVAL; + + intpr = (handler_addr & HANDLER_MASK); + intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT; + writel(intpr, intc_dev->regs + 4 * nr); + + return 0; +} + +void timer_init(void) +{ + extern void timer_interrupt_handler(void); + u64 tmp; + + sysreg_write(COUNT, 0); + + tmp = (u64)CFG_HZ << 32; + tmp += gd->cpu_hz / 2; + do_div(tmp, gd->cpu_hz); + tb_factor = (u32)tmp; + + intc_dev = get_device(DEVICE_INTC); + + if (!intc_dev + || set_interrupt_handler(0, &timer_interrupt_handler, 3)) + return; + + /* For all practical purposes, this gives us an overflow interrupt */ + sysreg_write(COMPARE, 0xffffffff); +} diff --git a/cpu/at32ap/pio.c b/cpu/at32ap/pio.c new file mode 100644 index 00000000000..8b6c3a35df5 --- /dev/null +++ b/cpu/at32ap/pio.c @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include +#include + +#include "pio2.h" + +struct pio_state { + const struct device *dev; + u32 alloc_mask; +}; + +static struct pio_state pio_state[CFG_NR_PIOS]; + +int gpio_set_func(enum device_id gpio_devid, unsigned int start, + unsigned int nr_pins, enum gpio_func func) +{ + const struct device *gpio; + struct pio_state *state; + u32 mask; + + state = &pio_state[gpio_devid - DEVICE_PIOA]; + + gpio = get_device(gpio_devid); + if (!gpio) + return -EBUSY; + + state->dev = gpio; + mask = ((1 << nr_pins) - 1) << start; + + if (mask & state->alloc_mask) { + put_device(gpio); + return -EBUSY; + } + state->alloc_mask |= mask; + + switch (func) { + case GPIO_FUNC_GPIO: + /* TODO */ + return -EINVAL; + case GPIO_FUNC_A: + pio2_writel(gpio, ASR, mask); + pio2_writel(gpio, PDR, mask); + pio2_writel(gpio, PUDR, mask); + break; + case GPIO_FUNC_B: + pio2_writel(gpio, BSR, mask); + pio2_writel(gpio, PDR, mask); + pio2_writel(gpio, PUDR, mask); + break; + } + + return 0; +} + +void gpio_free(enum device_id gpio_devid, unsigned int start, + unsigned int nr_pins) +{ + const struct device *gpio; + struct pio_state *state; + u32 mask; + + state = &pio_state[gpio_devid - DEVICE_PIOA]; + gpio = state->dev; + mask = ((1 << nr_pins) - 1) << start; + + pio2_writel(gpio, ODR, mask); + pio2_writel(gpio, PER, mask); + + state->alloc_mask &= ~mask; + put_device(gpio); +} diff --git a/cpu/at32ap/pio2.h b/cpu/at32ap/pio2.h new file mode 100644 index 00000000000..6b79de3c72b --- /dev/null +++ b/cpu/at32ap/pio2.h @@ -0,0 +1,44 @@ +/* + * Register definitions for Parallel Input/Output Controller + */ +#ifndef __CPU_AT32AP_PIO2_H__ +#define __CPU_AT32AP_PIO2_H__ + +/* PIO2 register offsets */ +#define PIO2_PER 0x0000 +#define PIO2_PDR 0x0004 +#define PIO2_PSR 0x0008 +#define PIO2_OER 0x0010 +#define PIO2_ODR 0x0014 +#define PIO2_OSR 0x0018 +#define PIO2_IFER 0x0020 +#define PIO2_IFDR 0x0024 +#define PIO2_ISFR 0x0028 +#define PIO2_SODR 0x0030 +#define PIO2_CODR 0x0034 +#define PIO2_ODSR 0x0038 +#define PIO2_PDSR 0x003c +#define PIO2_IER 0x0040 +#define PIO2_IDR 0x0044 +#define PIO2_IMR 0x0048 +#define PIO2_ISR 0x004c +#define PIO2_MDER 0x0050 +#define PIO2_MDDR 0x0054 +#define PIO2_MDSR 0x0058 +#define PIO2_PUDR 0x0060 +#define PIO2_PUER 0x0064 +#define PIO2_PUSR 0x0068 +#define PIO2_ASR 0x0070 +#define PIO2_BSR 0x0074 +#define PIO2_ABSR 0x0078 +#define PIO2_OWER 0x00a0 +#define PIO2_OWDR 0x00a4 +#define PIO2_OWSR 0x00a8 + +/* Register access macros */ +#define pio2_readl(port,reg) \ + readl((port)->regs + PIO2_##reg) +#define pio2_writel(port,reg,value) \ + writel((value), (port)->regs + PIO2_##reg) + +#endif /* __CPU_AT32AP_PIO2_H__ */ diff --git a/cpu/at32ap/pm.c b/cpu/at32ap/pm.c new file mode 100644 index 00000000000..01ac325ee8f --- /dev/null +++ b/cpu/at32ap/pm.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifdef CFG_POWER_MANAGER +#include +#include + +#include +#include + +#include "sm.h" + +/* Sanity checks */ +#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \ + || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \ + || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB) +# error Constraint fCPU >= fHSB >= fPB{A,B} violated +#endif +#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1)) +# error Invalid PLL multiplier and/or divider +#endif + +DECLARE_GLOBAL_DATA_PTR; + +struct clock_domain_state { + const struct device *bridge; + unsigned long freq; + u32 mask; +}; +static struct clock_domain_state ckd_state[NR_CLOCK_DOMAINS]; + +int pm_enable_clock(enum clock_domain_id id, unsigned int index) +{ + const struct clock_domain *ckd = &chip_clock[id]; + struct clock_domain_state *state = &ckd_state[id]; + + if (ckd->bridge != NO_DEVICE) { + state->bridge = get_device(ckd->bridge); + if (!state->bridge) + return -EBUSY; + } + + state->mask |= 1 << index; + if (gd->sm) + writel(state->mask, gd->sm->regs + ckd->reg); + + return 0; +} + +void pm_disable_clock(enum clock_domain_id id, unsigned int index) +{ + const struct clock_domain *ckd = &chip_clock[id]; + struct clock_domain_state *state = &ckd_state[id]; + + state->mask &= ~(1 << index); + if (gd->sm) + writel(state->mask, gd->sm->regs + ckd->reg); + + if (ckd->bridge) + put_device(state->bridge); +} + +unsigned long pm_get_clock_freq(enum clock_domain_id domain) +{ + return ckd_state[domain].freq; +} + +void pm_init(void) +{ + uint32_t cksel = 0; + unsigned long main_clock; + + /* Make sure we don't disable any device we're already using */ + get_device(DEVICE_HRAMC); + get_device(DEVICE_HEBI); + + /* Enable the PICO as well */ + ckd_state[CLOCK_CPU].mask |= 1; + + gd->sm = get_device(DEVICE_SM); + if (!gd->sm) + panic("Unable to claim system manager device!\n"); + + /* Disable any devices that haven't been explicitly claimed */ + sm_writel(gd->sm, PM_PBB_MASK, ckd_state[CLOCK_PBB].mask); + sm_writel(gd->sm, PM_PBA_MASK, ckd_state[CLOCK_PBA].mask); + sm_writel(gd->sm, PM_HSB_MASK, ckd_state[CLOCK_HSB].mask); + sm_writel(gd->sm, PM_CPU_MASK, ckd_state[CLOCK_CPU].mask); + +#ifdef CONFIG_PLL + /* Initialize the PLL */ + main_clock = (CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL; + + sm_writel(gd->sm, PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES) + | SM_BF(PLLMUL, CFG_PLL0_MUL - 1) + | SM_BF(PLLDIV, CFG_PLL0_DIV - 1) + | SM_BF(PLLOPT, CFG_PLL0_OPT) + | SM_BF(PLLOSC, 0) + | SM_BIT(PLLEN))); + + /* Wait for lock */ + while (!(sm_readl(gd->sm, PM_ISR) & SM_BIT(LOCK0))) ; +#else + main_clock = CFG_OSC0_HZ; +#endif + + /* Set up clocks for the CPU and all peripheral buses */ + if (CFG_CLKDIV_CPU) { + cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1); + ckd_state[CLOCK_CPU].freq = main_clock / (1 << CFG_CLKDIV_CPU); + } else { + ckd_state[CLOCK_CPU].freq = main_clock; + } + if (CFG_CLKDIV_HSB) { + cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1); + ckd_state[CLOCK_HSB].freq = main_clock / (1 << CFG_CLKDIV_HSB); + } else { + ckd_state[CLOCK_HSB].freq = main_clock; + } + if (CFG_CLKDIV_PBA) { + cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1); + ckd_state[CLOCK_PBA].freq = main_clock / (1 << CFG_CLKDIV_PBA); + } else { + ckd_state[CLOCK_PBA].freq = main_clock; + } + if (CFG_CLKDIV_PBB) { + cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1); + ckd_state[CLOCK_PBB].freq = main_clock / (1 << CFG_CLKDIV_PBB); + } else { + ckd_state[CLOCK_PBB].freq = main_clock; + } + sm_writel(gd->sm, PM_CKSEL, cksel); + + /* CFG_HZ currently depends on cpu_hz */ + gd->cpu_hz = ckd_state[CLOCK_CPU].freq; + +#ifdef CONFIG_PLL + /* Use PLL0 as main clock */ + sm_writel(gd->sm, PM_MCCTRL, SM_BIT(PLLSEL)); +#endif +} + +#endif /* CFG_POWER_MANAGER */ diff --git a/cpu/at32ap/sm.h b/cpu/at32ap/sm.h new file mode 100644 index 00000000000..ce81ef0a463 --- /dev/null +++ b/cpu/at32ap/sm.h @@ -0,0 +1,204 @@ +/* + * Register definitions for System Manager + */ +#ifndef __CPU_AT32AP_SM_H__ +#define __CPU_AT32AP_SM_H__ + +/* SM register offsets */ +#define SM_PM_MCCTRL 0x0000 +#define SM_PM_CKSEL 0x0004 +#define SM_PM_CPU_MASK 0x0008 +#define SM_PM_HSB_MASK 0x000c +#define SM_PM_PBA_MASK 0x0010 +#define SM_PM_PBB_MASK 0x0014 +#define SM_PM_PLL0 0x0020 +#define SM_PM_PLL1 0x0024 +#define SM_PM_VCTRL 0x0030 +#define SM_PM_VMREF 0x0034 +#define SM_PM_VMV 0x0038 +#define SM_PM_IER 0x0040 +#define SM_PM_IDR 0x0044 +#define SM_PM_IMR 0x0048 +#define SM_PM_ISR 0x004c +#define SM_PM_ICR 0x0050 +#define SM_PM_GCCTRL 0x0060 +#define SM_RTC_CTRL 0x0080 +#define SM_RTC_VAL 0x0084 +#define SM_RTC_TOP 0x0088 +#define SM_RTC_IER 0x0090 +#define SM_RTC_IDR 0x0094 +#define SM_RTC_IMR 0x0098 +#define SM_RTC_ISR 0x009c +#define SM_RTC_ICR 0x00a0 +#define SM_WDT_CTRL 0x00b0 +#define SM_WDT_CLR 0x00b4 +#define SM_WDT_EXT 0x00b8 +#define SM_RC_RCAUSE 0x00c0 +#define SM_EIM_IER 0x0100 +#define SM_EIM_IDR 0x0104 +#define SM_EIM_IMR 0x0108 +#define SM_EIM_ISR 0x010c +#define SM_EIM_ICR 0x0110 +#define SM_EIM_MODE 0x0114 +#define SM_EIM_EDGE 0x0118 +#define SM_EIM_LEVEL 0x011c +#define SM_EIM_TEST 0x0120 +#define SM_EIM_NMIC 0x0124 + +/* Bitfields in PM_CKSEL */ +#define SM_CPUSEL_OFFSET 0 +#define SM_CPUSEL_SIZE 3 +#define SM_CPUDIV_OFFSET 7 +#define SM_CPUDIV_SIZE 1 +#define SM_HSBSEL_OFFSET 8 +#define SM_HSBSEL_SIZE 3 +#define SM_HSBDIV_OFFSET 15 +#define SM_HSBDIV_SIZE 1 +#define SM_PBASEL_OFFSET 16 +#define SM_PBASEL_SIZE 3 +#define SM_PBADIV_OFFSET 23 +#define SM_PBADIV_SIZE 1 +#define SM_PBBSEL_OFFSET 24 +#define SM_PBBSEL_SIZE 3 +#define SM_PBBDIV_OFFSET 31 +#define SM_PBBDIV_SIZE 1 + +/* Bitfields in PM_PLL0 */ +#define SM_PLLEN_OFFSET 0 +#define SM_PLLEN_SIZE 1 +#define SM_PLLOSC_OFFSET 1 +#define SM_PLLOSC_SIZE 1 +#define SM_PLLOPT_OFFSET 2 +#define SM_PLLOPT_SIZE 3 +#define SM_PLLDIV_OFFSET 8 +#define SM_PLLDIV_SIZE 8 +#define SM_PLLMUL_OFFSET 16 +#define SM_PLLMUL_SIZE 8 +#define SM_PLLCOUNT_OFFSET 24 +#define SM_PLLCOUNT_SIZE 6 +#define SM_PLLTEST_OFFSET 31 +#define SM_PLLTEST_SIZE 1 + +/* Bitfields in PM_VCTRL */ +#define SM_VAUTO_OFFSET 0 +#define SM_VAUTO_SIZE 1 +#define SM_PM_VCTRL_VAL_OFFSET 8 +#define SM_PM_VCTRL_VAL_SIZE 7 + +/* Bitfields in PM_VMREF */ +#define SM_REFSEL_OFFSET 0 +#define SM_REFSEL_SIZE 4 + +/* Bitfields in PM_VMV */ +#define SM_PM_VMV_VAL_OFFSET 0 +#define SM_PM_VMV_VAL_SIZE 8 + +/* Bitfields in PM_ICR */ +#define SM_LOCK0_OFFSET 0 +#define SM_LOCK0_SIZE 1 +#define SM_LOCK1_OFFSET 1 +#define SM_LOCK1_SIZE 1 +#define SM_WAKE_OFFSET 2 +#define SM_WAKE_SIZE 1 +#define SM_VOK_OFFSET 3 +#define SM_VOK_SIZE 1 +#define SM_VMRDY_OFFSET 4 +#define SM_VMRDY_SIZE 1 +#define SM_CKRDY_OFFSET 5 +#define SM_CKRDY_SIZE 1 + +/* Bitfields in PM_GCCTRL */ +#define SM_OSCSEL_OFFSET 0 +#define SM_OSCSEL_SIZE 1 +#define SM_PLLSEL_OFFSET 1 +#define SM_PLLSEL_SIZE 1 +#define SM_CEN_OFFSET 2 +#define SM_CEN_SIZE 1 +#define SM_CPC_OFFSET 3 +#define SM_CPC_SIZE 1 +#define SM_DIVEN_OFFSET 4 +#define SM_DIVEN_SIZE 1 +#define SM_DIV_OFFSET 8 +#define SM_DIV_SIZE 8 + +/* Bitfields in RTC_CTRL */ +#define SM_PCLR_OFFSET 1 +#define SM_PCLR_SIZE 1 +#define SM_TOPEN_OFFSET 2 +#define SM_TOPEN_SIZE 1 +#define SM_CLKEN_OFFSET 3 +#define SM_CLKEN_SIZE 1 +#define SM_PSEL_OFFSET 8 +#define SM_PSEL_SIZE 16 + +/* Bitfields in RTC_VAL */ +#define SM_RTC_VAL_VAL_OFFSET 0 +#define SM_RTC_VAL_VAL_SIZE 31 + +/* Bitfields in RTC_TOP */ +#define SM_RTC_TOP_VAL_OFFSET 0 +#define SM_RTC_TOP_VAL_SIZE 32 + +/* Bitfields in RTC_ICR */ +#define SM_TOPI_OFFSET 0 +#define SM_TOPI_SIZE 1 + +/* Bitfields in WDT_CTRL */ +#define SM_KEY_OFFSET 24 +#define SM_KEY_SIZE 8 + +/* Bitfields in RC_RCAUSE */ +#define SM_POR_OFFSET 0 +#define SM_POR_SIZE 1 +#define SM_BOD_OFFSET 1 +#define SM_BOD_SIZE 1 +#define SM_EXT_OFFSET 2 +#define SM_EXT_SIZE 1 +#define SM_WDT_OFFSET 3 +#define SM_WDT_SIZE 1 +#define SM_NTAE_OFFSET 4 +#define SM_NTAE_SIZE 1 +#define SM_SERP_OFFSET 5 +#define SM_SERP_SIZE 1 + +/* Bitfields in EIM_EDGE */ +#define SM_INT0_OFFSET 0 +#define SM_INT0_SIZE 1 +#define SM_INT1_OFFSET 1 +#define SM_INT1_SIZE 1 +#define SM_INT2_OFFSET 2 +#define SM_INT2_SIZE 1 +#define SM_INT3_OFFSET 3 +#define SM_INT3_SIZE 1 + +/* Bitfields in EIM_LEVEL */ + +/* Bitfields in EIM_TEST */ +#define SM_TESTEN_OFFSET 31 +#define SM_TESTEN_SIZE 1 + +/* Bitfields in EIM_NMIC */ +#define SM_EN_OFFSET 0 +#define SM_EN_SIZE 1 + +/* Bit manipulation macros */ +#define SM_BIT(name) \ + (1 << SM_##name##_OFFSET) +#define SM_BF(name,value) \ + (((value) & ((1 << SM_##name##_SIZE) - 1)) \ + << SM_##name##_OFFSET) +#define SM_BFEXT(name,value) \ + (((value) >> SM_##name##_OFFSET) \ + & ((1 << SM_##name##_SIZE) - 1)) +#define SM_BFINS(name,value,old) \ + (((old) & ~(((1 << SM_##name##_SIZE) - 1) \ + << SM_##name##_OFFSET)) \ + | SM_BF(name,value)) + +/* Register access macros */ +#define sm_readl(port,reg) \ + readl((port)->regs + SM_##reg) +#define sm_writel(port,reg,value) \ + writel((value), (port)->regs + SM_##reg) + +#endif /* __CPU_AT32AP_SM_H__ */ diff --git a/cpu/at32ap/start.S b/cpu/at32ap/start.S new file mode 100644 index 00000000000..79ee33b1fac --- /dev/null +++ b/cpu/at32ap/start.S @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include + +#ifndef PART_SPECIFIC_BOOTSTRAP +# define PART_SPECIFIC_BOOTSTRAP +#endif + +#define SYSREG_MMUCR_I_OFFSET 2 +#define SYSREG_MMUCR_S_OFFSET 4 + +#define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0)) +#define CPUCR_INIT (SYSREG_BIT(BI) | SYSREG_BIT(BE) \ + | SYSREG_BIT(FE) | SYSREG_BIT(RE) \ + | SYSREG_BIT(IBE) | SYSREG_BIT(IEE)) + + .text + .global _start +_start: + PART_SPECIFIC_BOOTSTRAP + + /* Reset the Status Register */ + mov r0, lo(SR_INIT) + orh r0, hi(SR_INIT) + mtsr SYSREG_SR, r0 + + /* Reset CPUCR and invalidate the BTB */ + mov r2, CPUCR_INIT + mtsr SYSREG_CPUCR, r2 + + /* Flush the caches */ + mov r1, 0 + cache r1[4], 8 + cache r1[0], 0 + sync 0 + + /* Reset the MMU to default settings */ + mov r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I) + mtsr SYSREG_MMUCR, r0 + + /* Internal RAM should not need any initialization. We might + have to initialize external RAM here if the part doesn't + have internal RAM (or we may use the data cache) */ + + /* Jump to cacheable segment */ + lddpc pc, 1f + + .align 2 +1: .long 2f + +2: lddpc sp, sp_init + + /* + * Relocate the data section and initialize .bss. Everything + * is guaranteed to be at least doubleword aligned by the + * linker script. + */ + lddpc r12, .Ldata_vma + lddpc r11, .Ldata_lma + lddpc r10, .Ldata_end + sub r10, r12 +4: ld.d r8, r11++ + sub r10, 8 + st.d r12++, r8 + brne 4b + + mov r8, 0 + mov r9, 0 + lddpc r10, .Lbss_end + sub r10, r12 +4: sub r10, 8 + st.d r12++, r8 + brne 4b + + /* Initialize the GOT pointer */ + lddpc r6, got_init +3: rsub r6, pc + ld.w pc, r6[start_u_boot@got] + + .align 2 + .type sp_init,@object +sp_init: + .long CFG_INIT_SP_ADDR +got_init: + .long 3b - _GLOBAL_OFFSET_TABLE_ +.Ldata_lma: + .long __data_lma +.Ldata_vma: + .long _data +.Ldata_end: + .long _edata +.Lbss_end: + .long _end diff --git a/include/asm-avr32/arch-at32ap7000/hmatrix2.h b/include/asm-avr32/arch-at32ap7000/hmatrix2.h new file mode 100644 index 00000000000..e6df4b7fe33 --- /dev/null +++ b/include/asm-avr32/arch-at32ap7000/hmatrix2.h @@ -0,0 +1,232 @@ +/* + * Register definition for the High-speed Bus Matrix + */ +#ifndef __ASM_AVR32_HMATRIX2_H__ +#define __ASM_AVR32_HMATRIX2_H__ + +/* HMATRIX2 register offsets */ +#define HMATRIX2_MCFG0 0x0000 +#define HMATRIX2_MCFG1 0x0004 +#define HMATRIX2_MCFG2 0x0008 +#define HMATRIX2_MCFG3 0x000c +#define HMATRIX2_MCFG4 0x0010 +#define HMATRIX2_MCFG5 0x0014 +#define HMATRIX2_MCFG6 0x0018 +#define HMATRIX2_MCFG7 0x001c +#define HMATRIX2_MCFG8 0x0020 +#define HMATRIX2_MCFG9 0x0024 +#define HMATRIX2_MCFG10 0x0028 +#define HMATRIX2_MCFG11 0x002c +#define HMATRIX2_MCFG12 0x0030 +#define HMATRIX2_MCFG13 0x0034 +#define HMATRIX2_MCFG14 0x0038 +#define HMATRIX2_MCFG15 0x003c +#define HMATRIX2_SCFG0 0x0040 +#define HMATRIX2_SCFG1 0x0044 +#define HMATRIX2_SCFG2 0x0048 +#define HMATRIX2_SCFG3 0x004c +#define HMATRIX2_SCFG4 0x0050 +#define HMATRIX2_SCFG5 0x0054 +#define HMATRIX2_SCFG6 0x0058 +#define HMATRIX2_SCFG7 0x005c +#define HMATRIX2_SCFG8 0x0060 +#define HMATRIX2_SCFG9 0x0064 +#define HMATRIX2_SCFG10 0x0068 +#define HMATRIX2_SCFG11 0x006c +#define HMATRIX2_SCFG12 0x0070 +#define HMATRIX2_SCFG13 0x0074 +#define HMATRIX2_SCFG14 0x0078 +#define HMATRIX2_SCFG15 0x007c +#define HMATRIX2_PRAS0 0x0080 +#define HMATRIX2_PRBS0 0x0084 +#define HMATRIX2_PRAS1 0x0088 +#define HMATRIX2_PRBS1 0x008c +#define HMATRIX2_PRAS2 0x0090 +#define HMATRIX2_PRBS2 0x0094 +#define HMATRIX2_PRAS3 0x0098 +#define HMATRIX2_PRBS3 0x009c +#define HMATRIX2_PRAS4 0x00a0 +#define HMATRIX2_PRBS4 0x00a4 +#define HMATRIX2_PRAS5 0x00a8 +#define HMATRIX2_PRBS5 0x00ac +#define HMATRIX2_PRAS6 0x00b0 +#define HMATRIX2_PRBS6 0x00b4 +#define HMATRIX2_PRAS7 0x00b8 +#define HMATRIX2_PRBS7 0x00bc +#define HMATRIX2_PRAS8 0x00c0 +#define HMATRIX2_PRBS8 0x00c4 +#define HMATRIX2_PRAS9 0x00c8 +#define HMATRIX2_PRBS9 0x00cc +#define HMATRIX2_PRAS10 0x00d0 +#define HMATRIX2_PRBS10 0x00d4 +#define HMATRIX2_PRAS11 0x00d8 +#define HMATRIX2_PRBS11 0x00dc +#define HMATRIX2_PRAS12 0x00e0 +#define HMATRIX2_PRBS12 0x00e4 +#define HMATRIX2_PRAS13 0x00e8 +#define HMATRIX2_PRBS13 0x00ec +#define HMATRIX2_PRAS14 0x00f0 +#define HMATRIX2_PRBS14 0x00f4 +#define HMATRIX2_PRAS15 0x00f8 +#define HMATRIX2_PRBS15 0x00fc +#define HMATRIX2_MRCR 0x0100 +#define HMATRIX2_SFR0 0x0110 +#define HMATRIX2_SFR1 0x0114 +#define HMATRIX2_SFR2 0x0118 +#define HMATRIX2_SFR3 0x011c +#define HMATRIX2_SFR4 0x0120 +#define HMATRIX2_SFR5 0x0124 +#define HMATRIX2_SFR6 0x0128 +#define HMATRIX2_SFR7 0x012c +#define HMATRIX2_SFR8 0x0130 +#define HMATRIX2_SFR9 0x0134 +#define HMATRIX2_SFR10 0x0138 +#define HMATRIX2_SFR11 0x013c +#define HMATRIX2_SFR12 0x0140 +#define HMATRIX2_SFR13 0x0144 +#define HMATRIX2_SFR14 0x0148 +#define HMATRIX2_SFR15 0x014c +#define HMATRIX2_VERSION 0x01fc + +/* Bitfields in MCFG0 */ +#define HMATRIX2_ULBT_OFFSET 0 +#define HMATRIX2_ULBT_SIZE 3 + +/* Bitfields in SCFG0 */ +#define HMATRIX2_SLOT_CYCLE_OFFSET 0 +#define HMATRIX2_SLOT_CYCLE_SIZE 8 +#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16 +#define HMATRIX2_DEFMSTR_TYPE_SIZE 2 +#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18 +#define HMATRIX2_FIXED_DEFMSTR_SIZE 4 +#define HMATRIX2_ARBT_OFFSET 24 +#define HMATRIX2_ARBT_SIZE 2 + +/* Bitfields in PRAS0 */ +#define HMATRIX2_M0PR_OFFSET 0 +#define HMATRIX2_M0PR_SIZE 4 +#define HMATRIX2_M1PR_OFFSET 4 +#define HMATRIX2_M1PR_SIZE 4 +#define HMATRIX2_M2PR_OFFSET 8 +#define HMATRIX2_M2PR_SIZE 4 +#define HMATRIX2_M3PR_OFFSET 12 +#define HMATRIX2_M3PR_SIZE 4 +#define HMATRIX2_M4PR_OFFSET 16 +#define HMATRIX2_M4PR_SIZE 4 +#define HMATRIX2_M5PR_OFFSET 20 +#define HMATRIX2_M5PR_SIZE 4 +#define HMATRIX2_M6PR_OFFSET 24 +#define HMATRIX2_M6PR_SIZE 4 +#define HMATRIX2_M7PR_OFFSET 28 +#define HMATRIX2_M7PR_SIZE 4 + +/* Bitfields in PRBS0 */ +#define HMATRIX2_M8PR_OFFSET 0 +#define HMATRIX2_M8PR_SIZE 4 +#define HMATRIX2_M9PR_OFFSET 4 +#define HMATRIX2_M9PR_SIZE 4 +#define HMATRIX2_M10PR_OFFSET 8 +#define HMATRIX2_M10PR_SIZE 4 +#define HMATRIX2_M11PR_OFFSET 12 +#define HMATRIX2_M11PR_SIZE 4 +#define HMATRIX2_M12PR_OFFSET 16 +#define HMATRIX2_M12PR_SIZE 4 +#define HMATRIX2_M13PR_OFFSET 20 +#define HMATRIX2_M13PR_SIZE 4 +#define HMATRIX2_M14PR_OFFSET 24 +#define HMATRIX2_M14PR_SIZE 4 +#define HMATRIX2_M15PR_OFFSET 28 +#define HMATRIX2_M15PR_SIZE 4 + +/* Bitfields in MRCR */ +#define HMATRIX2_RBC0_OFFSET 0 +#define HMATRIX2_RBC0_SIZE 1 +#define HMATRIX2_RBC1_OFFSET 1 +#define HMATRIX2_RBC1_SIZE 1 +#define HMATRIX2_RBC2_OFFSET 2 +#define HMATRIX2_RBC2_SIZE 1 +#define HMATRIX2_RBC3_OFFSET 3 +#define HMATRIX2_RBC3_SIZE 1 +#define HMATRIX2_RBC4_OFFSET 4 +#define HMATRIX2_RBC4_SIZE 1 +#define HMATRIX2_RBC5_OFFSET 5 +#define HMATRIX2_RBC5_SIZE 1 +#define HMATRIX2_RBC6_OFFSET 6 +#define HMATRIX2_RBC6_SIZE 1 +#define HMATRIX2_RBC7_OFFSET 7 +#define HMATRIX2_RBC7_SIZE 1 +#define HMATRIX2_RBC8_OFFSET 8 +#define HMATRIX2_RBC8_SIZE 1 +#define HMATRIX2_RBC9_OFFSET 9 +#define HMATRIX2_RBC9_SIZE 1 +#define HMATRIX2_RBC10_OFFSET 10 +#define HMATRIX2_RBC10_SIZE 1 +#define HMATRIX2_RBC11_OFFSET 11 +#define HMATRIX2_RBC11_SIZE 1 +#define HMATRIX2_RBC12_OFFSET 12 +#define HMATRIX2_RBC12_SIZE 1 +#define HMATRIX2_RBC13_OFFSET 13 +#define HMATRIX2_RBC13_SIZE 1 +#define HMATRIX2_RBC14_OFFSET 14 +#define HMATRIX2_RBC14_SIZE 1 +#define HMATRIX2_RBC15_OFFSET 15 +#define HMATRIX2_RBC15_SIZE 1 + +/* Bitfields in SFR0 */ +#define HMATRIX2_SFR_OFFSET 0 +#define HMATRIX2_SFR_SIZE 32 + +/* Bitfields in SFR4 */ +#define HMATRIX2_CS1A_OFFSET 1 +#define HMATRIX2_CS1A_SIZE 1 +#define HMATRIX2_CS3A_OFFSET 3 +#define HMATRIX2_CS3A_SIZE 1 +#define HMATRIX2_CS4A_OFFSET 4 +#define HMATRIX2_CS4A_SIZE 1 +#define HMATRIX2_CS5A_OFFSET 5 +#define HMATRIX2_CS5A_SIZE 1 +#define HMATRIX2_DBPUC_OFFSET 8 +#define HMATRIX2_DBPUC_SIZE 1 + +/* Bitfields in VERSION */ +#define HMATRIX2_VERSION_OFFSET 0 +#define HMATRIX2_VERSION_SIZE 12 +#define HMATRIX2_MFN_OFFSET 16 +#define HMATRIX2_MFN_SIZE 3 + +/* Constants for ULBT */ +#define HMATRIX2_ULBT_INFINITE 0 +#define HMATRIX2_ULBT_SINGLE 1 +#define HMATRIX2_ULBT_FOUR_BEAT 2 +#define HMATRIX2_ULBT_SIXTEEN_BEAT 4 + +/* Constants for DEFMSTR_TYPE */ +#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0 +#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1 +#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2 + +/* Constants for ARBT */ +#define HMATRIX2_ARBT_ROUND_ROBIN 0 +#define HMATRIX2_ARBT_FIXED_PRIORITY 1 + +/* Bit manipulation macros */ +#define HMATRIX2_BIT(name) \ + (1 << HMATRIX2_##name##_OFFSET) +#define HMATRIX2_BF(name,value) \ + (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \ + << HMATRIX2_##name##_OFFSET) +#define HMATRIX2_BFEXT(name,value) \ + (((value) >> HMATRIX2_##name##_OFFSET) \ + & ((1 << HMATRIX2_##name##_SIZE) - 1)) +#define HMATRIX2_BFINS(name,value,old) \ + (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \ + << HMATRIX2_##name##_OFFSET)) \ + | HMATRIX2_BF(name,value)) + +/* Register access macros */ +#define hmatrix2_readl(port,reg) \ + readl((port)->regs + HMATRIX2_##reg) +#define hmatrix2_writel(port,reg,value) \ + writel((value), (port)->regs + HMATRIX2_##reg) + +#endif /* __ASM_AVR32_HMATRIX2_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/memory-map.h b/include/asm-avr32/arch-at32ap7000/memory-map.h new file mode 100644 index 00000000000..8ffe851c89e --- /dev/null +++ b/include/asm-avr32/arch-at32ap7000/memory-map.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PART_MEMORY_MAP_H__ +#define __ASM_AVR32_PART_MEMORY_MAP_H__ + +#define AUDIOC_BASE 0xFFF02800 +#define DAC_BASE 0xFFF02000 +#define DMAC_BASE 0xFF200000 +#define ECC_BASE 0xFFF03C00 +#define HISI_BASE 0xFFF02C00 +#define HMATRIX_BASE 0xFFF00800 +#define HSDRAMC_BASE 0xFFF03800 +#define HSMC_BASE 0xFFF03400 +#define LCDC_BASE 0xFF000000 +#define MACB0_BASE 0xFFF01800 +#define MACB1_BASE 0xFFF01C00 +#define MMCI_BASE 0xFFF02400 +#define PIOA_BASE 0xFFE02800 +#define PIOB_BASE 0xFFE02C00 +#define PIOC_BASE 0xFFE03000 +#define PIOD_BASE 0xFFE03400 +#define PIOE_BASE 0xFFE03800 +#define PSIF_BASE 0xFFE03C00 +#define PWM_BASE 0xFFF01400 +#define SM_BASE 0xFFF00000 +#define INTC_BASE 0XFFF00400 +#define SPI0_BASE 0xFFE00000 +#define SPI1_BASE 0xFFE00400 +#define SSC0_BASE 0xFFE01C00 +#define SSC1_BASE 0xFFE02000 +#define SSC2_BASE 0xFFE02400 +#define TIMER0_BASE 0xFFF00C00 +#define TIMER1_BASE 0xFFF01000 +#define TWI_BASE 0xFFE00800 +#define USART0_BASE 0xFFE00C00 +#define USART1_BASE 0xFFE01000 +#define USART2_BASE 0xFFE01400 +#define USART3_BASE 0xFFE01800 +#define USB_FIFO 0xFF300000 +#define USB_BASE 0xFFF03000 + +#endif /* __ASM_AVR32_PART_MEMORY_MAP_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/platform.h b/include/asm-avr32/arch-at32ap7000/platform.h new file mode 100644 index 00000000000..759050116a9 --- /dev/null +++ b/include/asm-avr32/arch-at32ap7000/platform.h @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _ASM_AVR32_ARCH_PM_H +#define _ASM_AVR32_ARCH_PM_H + +#include + +enum clock_domain_id { + CLOCK_CPU, + CLOCK_HSB, + CLOCK_PBA, + CLOCK_PBB, + NR_CLOCK_DOMAINS, +}; + +enum resource_type { + RESOURCE_GPIO, + RESOURCE_CLOCK, +}; + +enum gpio_func { + GPIO_FUNC_GPIO, + GPIO_FUNC_A, + GPIO_FUNC_B, +}; + +enum device_id { + DEVICE_HEBI, + DEVICE_PBA_BRIDGE, + DEVICE_PBB_BRIDGE, + DEVICE_HRAMC, + /* GPIO controllers must be kept together */ + DEVICE_PIOA, + DEVICE_PIOB, + DEVICE_PIOC, + DEVICE_PIOD, + DEVICE_PIOE, + DEVICE_SM, + DEVICE_INTC, + DEVICE_HMATRIX, +#if defined(CFG_HPDC) + DEVICE_HPDC, +#endif +#if defined(CFG_MACB0) + DEVICE_MACB0, +#endif +#if defined(CFG_MACB1) + DEVICE_MACB1, +#endif +#if defined(CFG_LCDC) + DEVICE_LCDC, +#endif +#if defined(CFG_USART0) + DEVICE_USART0, +#endif +#if defined(CFG_USART1) + DEVICE_USART1, +#endif +#if defined(CFG_USART2) + DEVICE_USART2, +#endif +#if defined(CFG_USART3) + DEVICE_USART3, +#endif +#if defined(CFG_MMCI) + DEVICE_MMCI, +#endif +#if defined(CFG_DMAC) + DEVICE_DMAC, +#endif + NR_DEVICES, + NO_DEVICE = -1, +}; + +struct resource { + enum resource_type type; + union { + struct { + unsigned long base; + } iomem; + struct { + unsigned char nr_pins; + enum device_id gpio_dev; + enum gpio_func func; + unsigned short start; + } gpio; + struct { + enum clock_domain_id id; + unsigned char index; + } clock; + } u; +}; + +struct device { + void *regs; + unsigned int nr_resources; + const struct resource *resource; +}; + +struct clock_domain { + unsigned short reg; + enum clock_domain_id id; + enum device_id bridge; +}; + +extern const struct device chip_device[NR_DEVICES]; +extern const struct clock_domain chip_clock[NR_CLOCK_DOMAINS]; + +/** + * Set up PIO, clock management and I/O memory for a device. + */ +const struct device *get_device(enum device_id devid); +void put_device(const struct device *dev); + +int gpio_set_func(enum device_id gpio_devid, unsigned int start, + unsigned int nr_pins, enum gpio_func func); +void gpio_free(enum device_id gpio_devid, unsigned int start, + unsigned int nr_pins); + +void pm_init(void); +int pm_enable_clock(enum clock_domain_id id, unsigned int index); +void pm_disable_clock(enum clock_domain_id id, unsigned int index); +unsigned long pm_get_clock_freq(enum clock_domain_id domain); + +void cpu_enable_sdram(void); + +#endif /* _ASM_AVR32_ARCH_PM_H */ -- cgit v1.3.1 From 6ccec4492e77428fd6eafd3dfe94fbdf08e91d37 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 24 Oct 2006 14:42:37 +0200 Subject: Add ATSTK1000 and ATSTK1002 board support Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the ATSTK1000 with the ATSTK1002 CPU daughterboard. ATSTK1000 is a full-featured development board for AT32AP CPUs. It has two ethernet ports, a high quality QVGA LCD panel, a loudspeaker, and connectors for USART, PS/2, VGA, USB, MMC/SD cards and CompactFlash cards. For more information, please see this page: http://www.atmel.com/dyn/products/tools.asp?family_id=682 The ATSTK1002 is a daughterboard for the ATSTK1000 supporting the AT32AP7000 chip. Signed-off-by: Haavard Skinnemoen --- MAINTAINERS | 4 + MAKEALL | 9 +- README | 9 ++ board/atstk1000/Makefile | 44 +++++++++ board/atstk1000/atstk1000.c | 52 ++++++++++ board/atstk1000/config.mk | 4 + board/atstk1000/flash.c | 223 +++++++++++++++++++++++++++++++++++++++++++ board/atstk1000/u-boot.lds.S | 79 +++++++++++++++ include/configs/atstk1002.h | 183 +++++++++++++++++++++++++++++++++++ 9 files changed, 606 insertions(+), 1 deletion(-) create mode 100644 board/atstk1000/Makefile create mode 100644 board/atstk1000/atstk1000.c create mode 100644 board/atstk1000/config.mk create mode 100644 board/atstk1000/flash.c create mode 100644 board/atstk1000/u-boot.lds.S create mode 100644 include/configs/atstk1002.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index d7ef203e551..cff39571223 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -561,6 +561,10 @@ Zachary P. Landau # Board CPU # ######################################################################### +Haavard Skinnemoen + + ATSTK1000 AT32AP7000 + ######################################################################### # End of MAINTAINERS list # ######################################################################### diff --git a/MAKEALL b/MAKEALL index 4409f2b3441..879a17f9cc5 100755 --- a/MAKEALL +++ b/MAKEALL @@ -302,6 +302,12 @@ LIST_coldfire=" \ r5200 M5271EVB \ " +######################################################################### +## AVR32 Systems +######################################################################### + +LIST_avr32="atstk1002" + #----------------------------------------------------------------------- #----- for now, just run PPC by default ----- @@ -334,7 +340,8 @@ do mips|mips_el| \ nios|nios2| \ x86|I486| \ - coldfire) + coldfire| \ + avr32) for target in `eval echo '$LIST_'${arg}` do build_target ${target} diff --git a/README b/README index 69af79a4576..f83d7745d3d 100644 --- a/README +++ b/README @@ -330,6 +330,15 @@ The following options need to be configured: CONFIG_PCI5441 CONFIG_PK1C20 CONFIG_EP1C20 CONFIG_EP1S10 CONFIG_EP1S40 + AVR32 based boards: + ------------------- + + CONFIG_ATSTK1000 + +- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined) + Define exactly one of + CONFIG_ATSTK1002 + - CPU Module Type: (if CONFIG_COGENT is defined) Define exactly one of diff --git a/board/atstk1000/Makefile b/board/atstk1000/Makefile new file mode 100644 index 00000000000..22ac02aa330 --- /dev/null +++ b/board/atstk1000/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o flash.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/atstk1000/atstk1000.c b/board/atstk1000/atstk1000.c new file mode 100644 index 00000000000..4d737d293ad --- /dev/null +++ b/board/atstk1000/atstk1000.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct sdram_info sdram = { + .phys_addr = CFG_SDRAM_BASE, + .row_bits = 11, + .col_bits = 8, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 5, + .txsr = 5, +}; + +void board_init_memories(void) +{ + gd->sdram_size = sdram_init(&sdram); +} + +void board_init_info(void) +{ + gd->bd->bi_phy_id[0] = 0x10; + gd->bd->bi_phy_id[1] = 0x11; +} diff --git a/board/atstk1000/config.mk b/board/atstk1000/config.mk new file mode 100644 index 00000000000..a72c80e2f94 --- /dev/null +++ b/board/atstk1000/config.mk @@ -0,0 +1,4 @@ +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_LDFLAGS += --gc-sections +TEXT_BASE = 0x00000000 +LDSCRIPT = $(obj)board/atstk1000/u-boot.lds diff --git a/board/atstk1000/flash.c b/board/atstk1000/flash.c new file mode 100644 index 00000000000..3aebf66ee24 --- /dev/null +++ b/board/atstk1000/flash.c @@ -0,0 +1,223 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifdef CONFIG_ATSTK1000_EXT_FLASH +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +flash_info_t flash_info[1]; + +static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info) +{ + unsigned long flags; + + flags = disable_interrupts(); + + dcache_flush_unlocked(); + + writew(0xaa, flash + 0x555); + writew(0x55, flash + 0xaaa); + writew(0x90, flash + 0x555); + info->flash_id = readl(flash); + writew(0xff, flash); + + readw(flash); + + if (flags) + enable_interrupts(); +} + +unsigned long flash_init(void) +{ + unsigned long addr; + unsigned int i; + + gd->bd->bi_flashstart = CFG_FLASH_BASE; + gd->bd->bi_flashsize = CFG_FLASH_SIZE; + gd->bd->bi_flashoffset = __edata_lma - _text; + + flash_info[0].size = CFG_FLASH_SIZE; + flash_info[0].sector_count = 135; + + flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]); + + for (i = 0, addr = 0; i < 8; i++, addr += 0x2000) + flash_info[0].start[i] = addr; + for (; i < flash_info[0].sector_count; i++, addr += 0x10000) + flash_info[0].start[i] = addr; + + return CFG_FLASH_SIZE; +} + +void flash_print_info(flash_info_t *info) +{ + printf("Flash: Vendor ID: 0x%02x, Product ID: 0x%02x\n", + info->flash_id >> 16, info->flash_id & 0xffff); + printf("Size: %ld MB in %d sectors\n", + info->size >> 10, info->sector_count); +} + +int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last) +{ + unsigned long flags; + unsigned long start_time; + uint16_t *fb, *sb; + unsigned int i; + int ret; + uint16_t status; + + if ((s_first < 0) || (s_first > s_last) + || (s_last >= info->sector_count)) { + puts("Error: first and/or last sector out of range\n"); + return ERR_INVAL; + } + + for (i = s_first; i < s_last; i++) + if (info->protect[i]) { + printf("Error: sector %d is protected\n", i); + return ERR_PROTECTED; + } + + fb = (uint16_t *)uncached(info->start[0]); + + dcache_flush_unlocked(); + + for (i = s_first; (i <= s_last) && !ctrlc(); i++) { + printf("Erasing sector %3d...", i); + + sb = (uint16_t *)uncached(info->start[i]); + + flags = disable_interrupts(); + + start_time = get_timer(0); + + /* Unlock sector */ + writew(0xaa, fb + 0x555); + writew(0x70, sb); + + /* Erase sector */ + writew(0xaa, fb + 0x555); + writew(0x55, fb + 0xaaa); + writew(0x80, fb + 0x555); + writew(0xaa, fb + 0x555); + writew(0x55, fb + 0xaaa); + writew(0x30, sb); + + /* Wait for completion */ + ret = ERR_OK; + do { + /* TODO: Timeout */ + status = readw(sb); + } while ((status != 0xffff) && !(status & 0x28)); + + writew(0xf0, fb); + + /* + * Make sure the command actually makes it to the bus + * before we re-enable interrupts. + */ + readw(fb); + + if (flags) + enable_interrupts(); + + if (status != 0xffff) { + printf("Flash erase error at address 0x%p: 0x%02x\n", + sb, status); + ret = ERR_PROG_ERROR; + break; + } + } + + if (ctrlc()) + printf("User interrupt!\n"); + + return ERR_OK; +} + +int __flashprog write_buff(flash_info_t *info, uchar *src, + ulong addr, ulong count) +{ + unsigned long flags; + uint16_t *base, *p, *s, *end; + uint16_t word, status; + int ret = ERR_OK; + + if (addr < info->start[0] + || (addr + count) > (info->start[0] + info->size) + || (addr + count) < addr) { + puts("Error: invalid address range\n"); + return ERR_INVAL; + } + + if (addr & 1 || count & 1 || (unsigned int)src & 1) { + puts("Error: misaligned source, destination or count\n"); + return ERR_ALIGN; + } + + base = (uint16_t *)uncached(info->start[0]); + end = (uint16_t *)uncached(addr + count); + + flags = disable_interrupts(); + + dcache_flush_unlocked(); + sync_write_buffer(); + + for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src; + p < end && !ctrlc(); p++, s++) { + word = *s; + + writew(0xaa, base + 0x555); + writew(0x55, base + 0xaaa); + writew(0xa0, base + 0x555); + writew(word, p); + + sync_write_buffer(); + + /* Wait for completion */ + do { + /* TODO: Timeout */ + status = readw(p); + } while ((status != word) && !(status & 0x28)); + + writew(0xf0, base); + readw(base); + + if (status != word) { + printf("Flash write error at address 0x%p: 0x%02x\n", + p, status); + ret = ERR_PROG_ERROR; + break; + } + } + + if (flags) + enable_interrupts(); + + return ret; +} + +#endif /* CONFIG_ATSTK1000_EXT_FLASH */ diff --git a/board/atstk1000/u-boot.lds.S b/board/atstk1000/u-boot.lds.S new file mode 100644 index 00000000000..d46b82ceb23 --- /dev/null +++ b/board/atstk1000/u-boot.lds.S @@ -0,0 +1,79 @@ +/* -*- Fundamental -*- + * + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = CFG_FLASH_BASE; + _text = .; + .text : { + *(.text) + *(.text.*) + } + + . = ALIGN(CFG_ICACHE_LINESZ); + __flashprog_start = .; + .flashprog : { + *(.flashprog) + } + . = ALIGN(CFG_ICACHE_LINESZ); + __flashprog_end = .; + + . = ALIGN(8); + .rodata : { + *(.rodata) + *(.rodata.*) + } + _etext = .; + + __data_lma = ALIGN(8); + . = CFG_INTRAM_BASE; + _data = .; + .data : AT(__data_lma) { + *(.data) + *(.data.*) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + __u_boot_cmd_lma = __data_lma + (__u_boot_cmd_start - _data); + .u_boot_cmd : AT(__u_boot_cmd_lma) { + KEEP(*(.u_boot_cmd)) + } + __u_boot_cmd_end = .; + + . = ALIGN(8); + _edata = .; + __edata_lma = __u_boot_cmd_lma + (_edata - __u_boot_cmd_start); + + .bss : AT(__edata_lma) { + *(.bss) + *(.bss.*) + } + . = ALIGN(8); + _end = .; +} diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h new file mode 100644 index 00000000000..458ebabeb9a --- /dev/null +++ b/include/configs/atstk1002.h @@ -0,0 +1,183 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * Configuration settings for the ATSTK1002 CPU daughterboard + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_ATSTK1002 1 +#define CONFIG_ATSTK1000 1 + +#define CONFIG_ATSTK1000_EXT_FLASH 1 + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL + * frequency and the peripherals to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 20000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 7 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +#define CFG_CLKDIV_CPU 0 +#define CFG_CLKDIV_HSB 1 +#define CFG_CLKDIV_PBA 2 +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#define CFG_USART1 1 + +#define CFG_CONSOLE_UART_DEV DEVICE_USART1 + +/* User serviceable stuff */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyUS0 root=/dev/mtdblock1 fbmem=600k" + +#define CONFIG_COMMANDS (CFG_CMD_BDI \ + | CFG_CMD_LOADS \ + | CFG_CMD_LOADB \ + /* | CFG_CMD_IMI */ \ + /* | CFG_CMD_CACHE */ \ + | CFG_CMD_FLASH \ + | CFG_CMD_MEMORY \ + /* | CFG_CMD_NET */ \ + | CFG_CMD_ENV \ + /* | CFG_CMD_IRQ */ \ + | CFG_CMD_BOOTD \ + | CFG_CMD_CONSOLE \ + /* | CFG_CMD_EEPROM */ \ + | CFG_CMD_ASKENV \ + | CFG_CMD_RUN \ + | CFG_CMD_ECHO \ + /* | CFG_CMD_I2C */ \ + | CFG_CMD_REGINFO \ + /* | CFG_CMD_DATE */ \ + /* | CFG_CMD_DHCP */ \ + /* | CFG_CMD_AUTOSCRIPT */ \ + /* | CFG_CMD_MII */ \ + | CFG_CMD_MISC \ + /* | CFG_CMD_SDRAM */ \ + /* | CFG_CMD_DIAG */ \ + /* | CFG_CMD_HWFLOW */ \ + /* | CFG_CMD_SAVES */ \ + /* | CFG_CMD_SPI */ \ + /* | CFG_CMD_PING */ \ + /* | CFG_CMD_MMC */ \ + /* | CFG_CMD_FAT */ \ + /* | CFG_CMD_IMLS */ \ + /* | CFG_CMD_ITEST */ \ + /* | CFG_CMD_EXT2 */ \ + ) + +#include + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +/* External flash on STK1000 */ +#if 0 +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#endif + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE 0x24000000 +#define CFG_INTRAM_SIZE 0x8000 + +#define CFG_SDRAM_BASE 0x10000000 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) +#define CFG_MALLOC_END \ + ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + CFG_SDRAM_BASE + gd->sdram_size; \ + }) +#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN) + +#define CFG_DMA_ALLOC_LEN (16384) +#define CFG_DMA_ALLOC_END (CFG_MALLOC_START) +#define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN) +/* Allow 2MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "Uboot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 8 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START \ + ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; }) +#define CFG_MEMTEST_END \ + ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \ + }) +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 8078f1a5f63a739b8533478f6c2b62fb1e2f79d7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 28 Oct 2006 02:28:02 +0200 Subject: README says CFG_AUTO_COMPLETE, but ocde uses CONFIG_AUTO_COMPLETE --- README | 6 +++++- include/configs/CPCI750.h | 2 +- include/configs/KAREF.h | 1 - include/configs/METROBOX.h | 2 +- include/configs/ep82xxm.h | 2 +- 5 files changed, 8 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/README b/README index 8d876e435e2..b78ea6124dc 100644 --- a/README +++ b/README @@ -1466,10 +1466,14 @@ The following options need to be configured: default value of 5 is used. - Command Interpreter: - CFG_AUTO_COMPLETE + CONFIG_AUTO_COMPLETE Enable auto completion of commands using TAB. + Note that this feature has NOT been implemented yet + for the "hush" shell. + + CFG_HUSH_PARSER Define this variable to enable the "hush" shell (from diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 244e45a7505..bc23fc02788 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -74,7 +74,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_AUTO_COMPLETE 1 +#define CONFIG_AUTO_COMPLETE 1 /* Define which ETH port will be used for connecting the network */ #define CFG_ETH_PORT ETH_0 diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 7bbceb01bd4..2ad6f06985a 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -200,7 +200,6 @@ /* Include auto complete with tabs */ #define CONFIG_AUTO_COMPLETE 1 -#define CFG_AUTO_COMPLETE 1 #define CFG_ALT_MEMTEST 1 /* use real memory test */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index b96557148aa..465a4ecb8b9 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -268,7 +268,7 @@ /* Include auto complete with tabs */ #define CONFIG_AUTO_COMPLETE 1 -#define CFG_AUTO_COMPLETE 1 +#define CONFIG_AUTO_COMPLETE 1 #define CFG_ALT_MEMTEST 1 /* use real memory test */ diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index 372b10c623e..a77ccef63b9 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h @@ -135,7 +135,7 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CFG_ENV_IN_OWN_SECT 1 -#define CFG_AUTO_COMPLETE +#define CONFIG_AUTO_COMPLETE 1 #define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3 ETHERNET" #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -- cgit v1.3.1 From 2751a95abd1b96911081c357e96a12fa97b40dee Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 28 Oct 2006 02:29:14 +0200 Subject: Enable commandline editing and hush shell on all TQM boards. --- include/configs/TQM5200.h | 1 + include/configs/TQM823L.h | 5 ++--- include/configs/TQM823M.h | 5 ++--- include/configs/TQM8260.h | 7 +++++++ include/configs/TQM834x.h | 6 ++++++ include/configs/TQM850L.h | 5 ++--- include/configs/TQM850M.h | 5 ++--- include/configs/TQM855L.h | 5 ++--- include/configs/TQM855M.h | 5 ++--- include/configs/TQM85xx.h | 6 +++--- include/configs/TQM860L.h | 5 ++--- include/configs/TQM860M.h | 5 ++--- include/configs/TQM862L.h | 5 ++--- include/configs/TQM862M.h | 5 ++--- include/configs/TQM866M.h | 7 +++---- include/configs/TQM885D.h | 7 +++---- 16 files changed, 43 insertions(+), 41 deletions(-) (limited to 'include') diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 897d1b262b2..4bae103e09c 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -566,6 +566,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ #define CFG_PROMPT_HUSH_PS2 "> " diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index b1c70f88c26..247f705fb66 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -123,9 +123,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 9f958f54774..1461b5f2031 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -112,9 +112,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index 49c3872630c..ffd5c0b95ca 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -237,6 +237,13 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 92c7016e6bc..4bbee97db5a 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -353,6 +353,12 @@ extern int tqm834x_num_flash_banks; #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 16b2ce3f058..90ecbadb2e1 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -104,9 +104,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index bbc69608b26..b3f8f8d835a 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -102,9 +102,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 198db1954d8..49aaeea44de 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -107,9 +107,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index e25a7a204ff..50df49e93cc 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -141,9 +141,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index cce46249048..f45f3a2f5ac 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -186,10 +186,10 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 4a1a4325dc0..9be5db1e424 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -110,9 +110,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 4b754ba9cb9..37f6c985d3a 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -108,9 +108,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 1dc9f74d5e1..f03690a7b21 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -110,9 +110,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 3df060c619a..495934045f9 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -110,9 +110,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index 8f9c2c9cbb5..148490b5863 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -151,11 +151,10 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " #endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index ede4e3b9b34..d470ade847d 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -160,11 +160,10 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " #endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -- cgit v1.3.1 From fae684e89844856383bdf101440889557df3e6b1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 28 Oct 2006 16:45:00 +0200 Subject: [PATCH] omap925.c: Remove unused functions Signed-off-by: Ladislav Michl Signed-off-by: Stefan Roese --- cpu/arm925t/omap925.c | 34 ---------------------------------- include/arm925t.h | 4 ---- 2 files changed, 38 deletions(-) (limited to 'include') diff --git a/cpu/arm925t/omap925.c b/cpu/arm925t/omap925.c index ae62656f33d..65dab9f88d6 100644 --- a/cpu/arm925t/omap925.c +++ b/cpu/arm925t/omap925.c @@ -25,40 +25,6 @@ #include #include -ushort gpioreserved; - -void gpioreserve(ushort mask) -{ - gpioreserved |= mask; -} - -void gpiosetdir(ushort mask, ushort in) -{ - *(ushort *)GPIO_DIR_CONTROL_REG = (*(ushort *)GPIO_DIR_CONTROL_REG & ~mask) | (in & mask); -} - - -void gpiosetout(ushort mask, ushort out) -{ - ushort *r_ptr, r_val; - - r_ptr = (ushort *)GPIO_DATA_OUTPUT_REG; /* set pointer */ - r_val = *r_ptr & ~mask; /* get previous val, clear bits we want to change */ - r_val |= (out & mask); /* set specified bits in value + plus origional ones */ - *r_ptr = r_val; /* write it out */ -/* - * gcc screwed this one up :(. - * - * *(ushort *)GPIO_DATA_OUTPUT_REG = (*(ushort *)GPIO_DATA_OUTPUT_REG & ~mask) | (out & mask); - */ - -} - -void gpioinit(void) -{ -} - - #define MIF_CONFIG_REG 0xFFFECC0C #define FLASH_GLOBAL_CTRL_NWP 1 diff --git a/include/arm925t.h b/include/arm925t.h index ab343eaace5..3d767b35c04 100644 --- a/include/arm925t.h +++ b/include/arm925t.h @@ -6,10 +6,6 @@ #ifndef __ARM925T_H__ #define __ARM925T_H__ -void gpioreserve(ushort mask); -void gpiosetdir(ushort mask, ushort in); -void gpiosetout(ushort mask, ushort out); -void gpioinit(void); void archflashwp(void *archdata, int wp); #endif /*__ARM925T_H__*/ -- cgit v1.3.1 From 82d9c9ec29a1bec1b03ba616425ebaed231072c8 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Wed, 1 Nov 2006 01:34:29 +0100 Subject: Changed MarelV38B board make target to lowercase. Config file cleanup. --- Makefile | 2 +- include/configs/V38B.h | 368 ------------------------------------------------- include/configs/v38b.h | 343 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 344 insertions(+), 369 deletions(-) delete mode 100644 include/configs/V38B.h create mode 100644 include/configs/v38b.h (limited to 'include') diff --git a/Makefile b/Makefile index 62dafc5ed9f..ca35dc1586b 100644 --- a/Makefile +++ b/Makefile @@ -412,7 +412,7 @@ icecube_5100_config: unconfig @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube v38b_config: unconfig - @./mkconfig -a V38B ppc mpc5xxx v38b + @./mkconfig -a v38b ppc mpc5xxx v38b inka4x0_config: unconfig @$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0 diff --git a/include/configs/V38B.h b/include/configs/V38B.h deleted file mode 100644 index 8eea504742a..00000000000 --- a/include/configs/V38B.h +++ /dev/null @@ -1,368 +0,0 @@ -/* - * (C) Copyright 2003-2004 Wolfgang Denk, DENX Software Engineering, - * wd@denx.de. - * - * See file CREDITS for list of people who contributed to this project. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., 59 - * Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#if 0 -#define DEBUG 0xFFF -#endif - -#if 0 -#define DEBUG 0x01 -#endif - -/* - * High Level Configuration Options - * (easy to change) -*/ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_V38B 1 /* ... on V38B board */ -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ -#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ -#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ - -#define CONFIG_NETCONSOLE 1 - -#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ - -#define CFG_XLB_PIPELINING 1 /* gives better performance */ - - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -/* - * DDR - */ -#define SDRAM_DDR 1 /* is DDR */ -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x704f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - - -/* - * PCI - no suport - */ -#undef CONFIG_PCI - -/* - * Partitions - */ -#define CONFIG_MAC_PARTITION 1 -#define CONFIG_DOS_PARTITION 1 - -/* - * USB - */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_PING | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_SDRAMi | \ - CFG_CMD_DATE | \ - CFG_CMD_USB | \ - CFG_CMD_FAT) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Boot low with 16 MB Flash - */ -# define CFG_LOWBOOT 1 -# define CFG_LOWBOOT16 1 - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "devno=5\0" \ - "hostname=V38B_$(devno)\0" \ - "ipaddr=10.100.99.$(devno)\0" \ - "netmask=255.255.0.0\0" \ - "serverip=10.100.10.90\0" \ - "gatewayip=10.100.254.254\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=mpc5200/uImage\0" \ - "bootcmd=run net_nfs\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;bootm $(kernel_addr) " \ - "$(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs " \ - "addip;bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#if defined(CONFIG_MPC5200) -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ -#endif -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 - -/* - * RTC configuration - */ -#define CFG_I2C_RTC_ADDR 0x51 - -/* - * Flash configuration - use CFI driver - */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 -#define CFG_FLASH_BASE 0xFF000000 -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 - -/* - * GPIO configuration - */ -#define CFG_GPS_PORT_CONFIG 0x90000404 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x00047801 -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -#define CFG_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -/* Status LED */ - -#define CONFIG_STATUS_LED /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ - -#define CFG_LED_BASE (0xf0000600 + 0x70) /* Timer 7 GPIO */ - -#ifndef __ASSEMBLY__ -/* LEDs */ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \ - else \ - *((volatile long *) (CFG_LED_BASE)) |= (_msk); \ - } while(0) - -#define __led_init(_msk, st) \ - { \ - *((volatile long *) (CFG_LED_BASE)) |= 0x34; \ - } - -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h new file mode 100644 index 00000000000..cf2d031c9f1 --- /dev/null +++ b/include/configs/v38b.h @@ -0,0 +1,343 @@ +/* + * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering, + * wd@denx.de. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ +#define CONFIG_V38B 1 /* ...on V38B board */ +#define CFG_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */ + +#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ +#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ + +#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ + +#define CONFIG_NETCONSOLE 1 + +#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */ + +#define CFG_XLB_PIPELINING 1 /* gives better performance */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * DDR + */ +#define SDRAM_DDR 1 /* is DDR */ +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x704f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +/* + * PCI - no suport + */ +#undef CONFIG_PCI + +/* + * Partitions + */ +#define CONFIG_MAC_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 + +/* + * USB + */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_SDRAMi | \ + CFG_CMD_DATE | \ + CFG_CMD_USB | \ + CFG_CMD_FAT) + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Boot low with 16 MB Flash + */ +#define CFG_LOWBOOT 1 +#define CFG_LOWBOOT16 1 + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootcmd=run net_nfs\0" \ + "bootdelay=3\0" \ + "baudrate=115200\0" \ + "preboot=echo;echo Type \"run flash_nfs\" to mount root " \ + "filesystem over NFS; echo\0" \ + "netdev=eth0\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off panic=1\0" \ + "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip;bootm $(kernel_addr) " \ + "$(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "hostname=v38b\0" \ + "ethact=FEC ETHERNET\0" \ + "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \ + "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ + "cp.b 200000 ff000000 $(filesize);" \ + "prot on ff000000 ff03ffff\0" \ + "load=tftp 200000 $(u-boot)\0" \ + "netmask=255.255.0.0\0" \ + "ipaddr=192.168.160.18\0" \ + "serverip=192.168.1.1\0" \ + "ethaddr=00:e0:ee:00:05:2e\0" \ + "bootfile=/tftpboot/v38b/uImage\0" \ + "u-boot=/tftpboot/v38b/u-boot.bin\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#if defined(CONFIG_MPC5200) +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#endif + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 + +/* + * RTC configuration + */ +#define CFG_I2C_RTC_ADDR 0x51 + +/* + * Flash configuration - use CFI driver + */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII 1 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x90000404 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00047801 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/* + * IDE/ATA (supports IDE harddisk) + */ +#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +#define CFG_ATA_DATA_OFFSET (0x0060) /* data I/O offset */ + +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* normal register accesses offset */ + +#define CFG_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */ + +#define CFG_ATA_STRIDE 4 /* Interval between registers */ + +/* + * Status LED + */ +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ + +#define CFG_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */ +#ifndef __ASSEMBLY__ +typedef unsigned int led_id_t; + +#define __led_toggle(_msk) \ + do { \ + *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \ + } while(0) + +#define __led_set(_msk, _st) \ + do { \ + if ((_st)) \ + *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \ + else \ + *((volatile long *) (CFG_LED_BASE)) |= (_msk); \ + } while(0) + +#define __led_init(_msk, st) \ + do { \ + *((volatile long *) (CFG_LED_BASE)) |= 0x34; \ + } while(0) +#endif /* __ASSEMBLY__ */ + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From dae80f3caf9754a6dd3ddf3cf903d0c46cbd4385 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Wed, 1 Nov 2006 01:38:16 +0100 Subject: - Add MPC5XXX register definition MPC5XXX_WU_GPIO_DATA_I and change the MPC5XXX_WU_GPIO_DATA macro to MPC5XXX_WU_GPIO_DATA_O (per MPC5200 User's Manual). Replace the uses of MPC5XXX_WU_GPIO_DATA with MPC5XXX_WU_GPIO_DATA_O for affected boards. - Add defintions for some MPC5XXX GPIO pins. --- board/bc3450/bc3450.c | 5 ++--- board/emk/top5200/top5200.c | 6 ++---- board/esd/cpci5200/cpci5200.c | 8 +++----- board/esd/pf5200/pf5200.c | 12 +++++------- board/icecube/icecube.c | 8 +++----- board/inka4x0/inka4x0.c | 15 +++++---------- board/tqm5200/tqm5200.c | 8 +++----- include/mpc5xxx.h | 9 ++++++++- 8 files changed, 31 insertions(+), 40 deletions(-) (limited to 'include') diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c index 0d865186ae0..05bb7235f8b 100644 --- a/board/bc3450/bc3450.c +++ b/board/bc3450/bc3450.c @@ -295,7 +295,6 @@ void pci_init_board(void) #endif #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) -#define GPIO_PSC1_4 0x01000000UL void init_ide_reset (void) { @@ -311,9 +310,9 @@ void ide_set_reset (int idereset) debug ("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } } #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c index 4508438ca37..12acc57171b 100644 --- a/board/emk/top5200/top5200.c +++ b/board/emk/top5200/top5200.c @@ -186,8 +186,6 @@ void pci_init_board(void) *****************************************************************************/ #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) -#define GPIO_PSC1_4 0x01000000UL - void init_ide_reset (void) { debug ("init_ide_reset\n"); @@ -202,9 +200,9 @@ void ide_set_reset (int idereset) debug ("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } } #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c index 6c98f13fb6a..f14331bebc4 100644 --- a/board/esd/cpci5200/cpci5200.c +++ b/board/esd/cpci5200/cpci5200.c @@ -199,8 +199,6 @@ void pci_init_board(void #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) -#define GPIO_PSC1_4 0x01000000UL - void init_ide_reset(void) { debug("init_ide_reset\n"); @@ -215,9 +213,9 @@ void ide_set_reset(int idereset) debug("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } } #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ @@ -242,7 +240,7 @@ void init_ata_reset(void) debug("init_ata_reset\n"); /* Configure GPIO_WU6 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; __asm__ volatile ("sync"); diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c index 2b47012cfaf..1f30d454fff 100644 --- a/board/esd/pf5200/pf5200.c +++ b/board/esd/pf5200/pf5200.c @@ -199,8 +199,6 @@ void pci_init_board(void #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) -#define GPIO_PSC1_4 0x01000000UL - void init_ide_reset(void) { debug("init_ide_reset\n"); @@ -215,9 +213,9 @@ void ide_set_reset(int idereset) debug("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } } #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ @@ -242,7 +240,7 @@ void init_power_switch(void) debug("init_power_switch\n"); /* Configure GPIO_WU6 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; __asm__ volatile ("sync"); @@ -272,10 +270,10 @@ void power_set_reset(int power) debug("ide_set_reset(%d)\n", power); if (power) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6; *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) { *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 4f056b2fa44..f958b32dbd8 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -308,8 +308,6 @@ void pci_init_board(void) #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) -#define GPIO_PSC1_4 0x01000000UL - void init_ide_reset (void) { debug ("init_ide_reset\n"); @@ -318,7 +316,7 @@ void init_ide_reset (void) *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; /* Deassert reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } void ide_set_reset (int idereset) @@ -326,11 +324,11 @@ void ide_set_reset (int idereset) debug ("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; /* Make a delay. MPC5200 spec says 25 usec min */ udelay(500000); } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } } #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c index 29878f9b44d..d670cc35a00 100644 --- a/board/inka4x0/inka4x0.c +++ b/board/inka4x0/inka4x0.c @@ -173,9 +173,6 @@ void flash_preinit(void) *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } -#define GPIO_WKUP_7 0x80000000UL -#define GPIO_PSC3_9 0x04000000UL - int misc_init_f (void) { uchar tmp[10]; @@ -218,13 +215,13 @@ int misc_init_f (void) *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000; /* Set LR mirror bit because it is low-active */ - *(vu_long *)MPC5XXX_WU_GPIO_DATA |= GPIO_WKUP_7; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WKUP_7; /* * Reset Coral-P graphics controller */ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9; - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC3_9; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC3_9; return 0; } @@ -241,8 +238,6 @@ void pci_init_board(void) #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) -#define GPIO_PSC1_4 0x01000000UL - void init_ide_reset (void) { debug ("init_ide_reset\n"); @@ -251,7 +246,7 @@ void init_ide_reset (void) *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; /* Deassert reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } void ide_set_reset (int idereset) @@ -259,11 +254,11 @@ void ide_set_reset (int idereset) debug ("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; /* Make a delay. MPC5200 spec says 25 usec min */ udelay(500000); } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } } #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 1d81dce6090..cb57a5e2694 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -341,9 +341,7 @@ void pci_init_board(void) #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL #define SM501_GPIO_DATA_HIGH 0x00010004UL #define SM501_GPIO_51 0x00080000UL -#else -#define GPIO_PSC1_4 0x01000000UL -#endif +#endif /* CONFIG MINIFAP */ void init_ide_reset (void) { @@ -381,9 +379,9 @@ void ide_set_reset (int idereset) } #else if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } #endif } diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index 1d20d1dcf55..089aa1322b8 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -188,7 +188,14 @@ #define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000) #define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004) #define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008) -#define MPC5XXX_WU_GPIO_DATA (MPC5XXX_WU_GPIO + 0x000c) +#define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c) +#define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020) + +/* GPIO pins */ +#define GPIO_WKUP_7 0x80000000UL +#define GPIO_PSC6_0 0x10000000UL +#define GPIO_PSC3_9 0x04000000UL +#define GPIO_PSC1_4 0x01000000UL /* PCI registers */ #define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04) -- cgit v1.3.1 From 91650b3e4de688038d4f71279c44858e3e2c6870 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 6 Nov 2006 17:06:36 +0100 Subject: Sequential accesses to non-existent memory must be synchronized, at least on G2 cores. This fixes get_ram_size() problems on MPC5200 Rev. B boards. --- board/mcc200/mcc200.c | 19 +++++++++++++++++++ common/memsize.c | 17 +++++++++++++++++ include/common.h | 2 +- 3 files changed, 37 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index 71a691b5dbf..8b475c690d9 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -27,6 +27,7 @@ #include #include #include +#include /* Two MT48LC8M32B2 for 32 MB */ /* #include "mt48lc8m32b2-6-7.h" */ @@ -98,6 +99,7 @@ long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; + uint svr, pvr; #ifndef CFG_RAMBOOT ulong test1, test2; @@ -192,6 +194,23 @@ long int initdram (int board_type) #endif /* CFG_RAMBOOT */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && + (PVR_MIN(pvr) == 4)) { + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + return dramsize + dramsize2; } diff --git a/common/memsize.c b/common/memsize.c index dbc812dfc51..6c275c9b25f 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -21,6 +21,16 @@ * MA 02111-1307 USA */ +#include +#ifdef __PPC__ +/* + * At least on G2 PowerPC cores, sequential accesses to non-existent + * memory must be synchronized. + */ +# include /* for sync() */ +#else +# define sync() /* nothing */ +#endif /* * Check memory range for valid RAM. A simple memory test determines @@ -38,20 +48,27 @@ long get_ram_size(volatile long *base, long maxsize) for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { addr = base + cnt; /* pointer arith! */ + sync (); save[i++] = *addr; + sync (); *addr = ~cnt; } addr = base; + sync (); save[i] = *addr; + sync (); *addr = 0; + sync (); if ((val = *addr) != 0) { /* Restore the original data before leaving the function. */ + sync (); *addr = save[i]; for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) { addr = base + cnt; + sync (); *addr = save[--i]; } return (0); diff --git a/include/common.h b/include/common.h index 349d5cf726b..ac78d1c001c 100644 --- a/include/common.h +++ b/include/common.h @@ -270,7 +270,7 @@ int misc_init_r (void); void jumptable_init(void); /* common/memsize.c */ -int get_ram_size (volatile long *, long); +long get_ram_size (volatile long *, long); /* $(BOARD)/$(BOARD).c */ void reset_phy (void); -- cgit v1.3.1 From 44a47e6db2694841211f1c8fdbafd36992e9cd1a Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Sat, 11 Nov 2006 22:43:00 +0100 Subject: Change the GPIO pin multiplexing configuration for V38B. The USB GPIO pin group is enabled for USB earlier (in cpu_init_f() instead of usb_lowlevel_init()). --- include/configs/v38b.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/v38b.h b/include/configs/v38b.h index cf2d031c9f1..deabc1761a6 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -246,7 +246,7 @@ /* * GPIO configuration */ -#define CFG_GPS_PORT_CONFIG 0x90000404 +#define CFG_GPS_PORT_CONFIG 0x90001404 /* * Miscellaneous configurable options -- cgit v1.3.1 From ce3f1a40c507afbab06c5eb58ccdc6713eda3245 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Sat, 11 Nov 2006 22:48:22 +0100 Subject: Disable the watchdog in the default config for the V38B board. --- include/configs/v38b.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/v38b.h b/include/configs/v38b.h index deabc1761a6..554a7a41b8e 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -34,7 +34,7 @@ #define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ #define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ -#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ +#undef CONFIG_HW_WATCHDOG /* don't use watchdog */ #define CONFIG_NETCONSOLE 1 -- cgit v1.3.1 From 260421a21e934a68d31fb6125b0fbd2631a8ca20 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 13 Nov 2006 13:55:24 +0100 Subject: [PATCH] CFI driver AMD Command Set Top boot geometry reversal, etc. [Updated] * Adds support for AMD command set Top Boot flash geometry reversal * Adds support for reading JEDEC Manufacturer ID and Device ID * Adds support for displaying command set, manufacturer id and device ids (flinfo) * Makes flinfo output to be consistent when CFG_FLASH_EMPTY_INFO defined * Removes outdated change history (refer to git log instead) Signed-off-by: Tolunay Orkun Signed-off-by: Stefan Roese --- drivers/cfi_flash.c | 214 ++++++++++++++++++++++++++++++++++++++-------------- include/flash.h | 8 +- 2 files changed, 164 insertions(+), 58 deletions(-) (limited to 'include') diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index fd0a186828d..9b10220fc74 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -4,11 +4,12 @@ * * Copyright (C) 2003 Arabella Software Ltd. * Yuli Barcohen - * Modified to work with AMD flashes * * Copyright (C) 2004 * Ed Okerson - * Modified to work with little-endian systems. + * + * Copyright (C) 2006 + * Tolunay Orkun * * See file CREDITS for list of people who contributed to this * project. @@ -28,17 +29,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * - * History - * 01/20/2004 - combined variants of original driver. - * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay) - * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud) - * 01/27/2004 - Little endian support Ed Okerson - * - * Tested Architectures - * Port Width Chip Width # of banks Flash Chip Board - * 32 16 1 28F128J3 seranoa/eagle - * 64 16 1 28F128J3 seranoa/falcon - * */ /* The DEBUG define must be before common to enable debugging */ @@ -54,21 +44,16 @@ * This file implements a Common Flash Interface (CFI) driver for U-Boot. * The width of the port and the width of the chips are determined at initialization. * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation and AMD 29F016D. * * References * JEDEC Standard JESD68 - Common Flash Interface (CFI) * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * AMD CFI Specification, Release 2.0 December 1, 2001 + * AMD/Spansion Application Note: Migration from Single-byte to Three-byte + * Device IDs, Publication Number 25538 Revision A, November 8, 2001 * - * TODO - * - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query - * Table (ALT) to determine if protection is available - * - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. */ #ifndef CFG_FLASH_BANKS_LIST @@ -114,6 +99,10 @@ #define AMD_ADDR_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555) #define AMD_ADDR_ACK ((info->portwidth == FLASH_CFI_8BIT) ? 0x555 : 0x2AA) +#define FLASH_OFFSET_MANUFACTURER_ID 0x00 +#define FLASH_OFFSET_DEVICE_ID 0x01 +#define FLASH_OFFSET_DEVICE_ID2 0x0E +#define FLASH_OFFSET_DEVICE_ID3 0x0F #define FLASH_OFFSET_CFI 0x55 #define FLASH_OFFSET_CFI_RESP 0x10 #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 @@ -135,25 +124,20 @@ #define FLASH_OFFSET_USER_PROTECTION 0x85 #define FLASH_OFFSET_INTEL_PROTECTION 0x81 - -#define FLASH_MAN_CFI 0x01000000 - -#define CFI_CMDSET_NONE 0 -#define CFI_CMDSET_INTEL_EXTENDED 1 -#define CFI_CMDSET_AMD_STANDARD 2 -#define CFI_CMDSET_INTEL_STANDARD 3 -#define CFI_CMDSET_AMD_EXTENDED 4 -#define CFI_CMDSET_MITSU_STANDARD 256 -#define CFI_CMDSET_MITSU_EXTENDED 257 -#define CFI_CMDSET_SST 258 - +#define CFI_CMDSET_NONE 0 +#define CFI_CMDSET_INTEL_EXTENDED 1 +#define CFI_CMDSET_AMD_STANDARD 2 +#define CFI_CMDSET_INTEL_STANDARD 3 +#define CFI_CMDSET_AMD_EXTENDED 4 +#define CFI_CMDSET_MITSU_STANDARD 256 +#define CFI_CMDSET_MITSU_EXTENDED 257 +#define CFI_CMDSET_SST 258 #ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ # undef FLASH_CMD_RESET -# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ +# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ #endif - typedef union { unsigned char c; unsigned short w; @@ -168,7 +152,7 @@ typedef union { volatile unsigned long long *llp; } cfiptr_t; -#define NUM_ERASE_REGIONS 4 +#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ /* use CFG_MAX_FLASH_BANKS_DETECT if defined */ #ifdef CFG_MAX_FLASH_BANKS_DETECT @@ -200,6 +184,7 @@ static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect); static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static void flash_read_jedec_ids (flash_info_t * info); static int flash_detect_cfi (flash_info_t * info); static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword); static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, @@ -307,7 +292,7 @@ ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset) } /*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum + * read a long word by picking the least significant byte of each maximum * port size word. Swap for ppc format. */ ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset) @@ -529,14 +514,42 @@ void flash_print_info (flash_info_t * info) (info->portwidth << 3), (info->chipwidth << 3)); printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + printf (" "); + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + printf ("Intel Standard"); + break; + case CFI_CMDSET_INTEL_EXTENDED: + printf ("Intel Extended"); + break; + case CFI_CMDSET_AMD_STANDARD: + printf ("AMD Standard"); + break; + case CFI_CMDSET_AMD_EXTENDED: + printf ("AMD Extended"); + break; + default: + printf ("Unknown (%d)", info->vendor); + break; + } + printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x%02X", + info->manufacturer_id, info->device_id); + if (info->device_id == 0x7E) { + printf("%04X", info->device_id2); + } + printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n", info->erase_blk_tout, - info->write_tout, + info->write_tout); + if (info->buffer_size > 1) { + printf (" Buffer write timeout: %ld ms, buffer size: %d bytes\n", info->buffer_write_tout, info->buffer_size); + } - puts (" Sector Start Addresses:"); + puts ("\n Sector Start Addresses:"); for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n"); #ifdef CFG_FLASH_EMPTY_INFO int k; int size; @@ -560,18 +573,15 @@ void flash_print_info (flash_info_t * info) } } - if ((i % 5) == 0) - printf ("\n"); /* print empty and read-only info */ - printf (" %08lX%s%s", + printf (" %08lX %c %s ", info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); + erased ? 'E' : ' ', + info->protect[i] ? "RO" : " "); #else /* ! CFG_FLASH_EMPTY_INFO */ - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); + printf (" %08lX %s ", + info->start[i], + info->protect[i] ? "RO" : " "); #endif } putc ('\n'); @@ -1070,6 +1080,55 @@ static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uc return retval; } +/*----------------------------------------------------------------------- + * read jedec ids from device and set corresponding fields in info struct + * + * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct + * +*/ +static void flash_read_jedec_ids (flash_info_t * info) +{ + info->manufacturer_id = 0; + info->device_id = 0; + info->device_id2 = 0; + + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); + udelay(1000); /* some flash are slow to respond */ + info->manufacturer_id = flash_read_uchar (info, + FLASH_OFFSET_MANUFACTURER_ID); + info->device_id = flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID); + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); + flash_unlock_seq(info, 0); + flash_write_cmd(info, 0, AMD_ADDR_START, FLASH_CMD_READ_ID); + udelay(1000); /* some flash are slow to respond */ + info->manufacturer_id = flash_read_uchar (info, + FLASH_OFFSET_MANUFACTURER_ID); + info->device_id = flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID); + if (info->device_id == 0x7E) { + /* AMD 3-byte (expanded) device ids */ + info->device_id2 = flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID2); + info->device_id2 <<= 8; + info->device_id2 |= flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID3); + } + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); + break; + default: + break; + } +} + /*----------------------------------------------------------------------- * detect if flash is compatible with the Common Flash Interface (CFI) * http://www.jedec.org/download/search/jesd68.pdf @@ -1120,15 +1179,31 @@ ulong flash_get_size (ulong base, int banknum) uchar num_erase_regions; int erase_region_size; int erase_region_count; + int geometry_reversed = 0; + + info->ext_addr = 0; + info->cfi_version = 0; #ifdef CFG_FLASH_PROTECTION - int ext_addr; info->legacy_unlock = 0; #endif info->start[0] = base; if (flash_detect_cfi (info)) { - info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR); + info->vendor = flash_read_ushort (info, 0, + FLASH_OFFSET_PRIMARY_VENDOR); + flash_read_jedec_ids (info); + flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + num_erase_regions = flash_read_uchar (info, + FLASH_OFFSET_NUM_ERASE_REGIONS); + info->ext_addr = flash_read_ushort (info, 0, + FLASH_OFFSET_EXT_QUERY_T_P_ADDR); + if (info->ext_addr) { + info->cfi_version = (ushort) flash_read_uchar (info, + info->ext_addr + 3) << 8; + info->cfi_version |= (ushort) flash_read_uchar (info, + info->ext_addr + 4); + } #ifdef DEBUG flash_printqry (info, 0); #endif @@ -1139,26 +1214,46 @@ ulong flash_get_size (ulong base, int banknum) info->cmd_reset = FLASH_CMD_RESET; #ifdef CFG_FLASH_PROTECTION /* read legacy lock/unlock bit from intel flash */ - ext_addr = flash_read_ushort (info, 0, - FLASH_OFFSET_EXT_QUERY_T_P_ADDR); - info->legacy_unlock = - flash_read_uchar (info, ext_addr + 5) & 0x08; + if (info->ext_addr) { + info->legacy_unlock = flash_read_uchar (info, + info->ext_addr + 5) & 0x08; + } #endif break; case CFI_CMDSET_AMD_STANDARD: case CFI_CMDSET_AMD_EXTENDED: info->cmd_reset = AMD_CMD_RESET; + /* check if flash geometry needs reversal */ + if (num_erase_regions <= 1) + break; + /* reverse geometry if top boot part */ + if (info->cfi_version < 0x3131) { + /* CFI < 1.1, try to guess from device id */ + if ((info->device_id & 0x80) != 0) { + geometry_reversed = 1; + } + break; + } + /* CFI >= 1.1, deduct from top/bottom flag */ + /* note: ext_addr is valid since cfi_version > 0 */ + if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { + geometry_reversed = 1; + } break; } debug ("manufacturer is %d\n", info->vendor); + debug ("manufacturer id is 0x%x\n", info->manufacturer_id); + debug ("device id is 0x%x\n", info->device_id); + debug ("device id2 is 0x%x\n", info->device_id2); + debug ("cfi version is 0x%04x\n", info->cfi_version); + size_ratio = info->portwidth / info->chipwidth; /* if the chip is x8/x16 reduce the ratio by half */ if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) { size_ratio >>= 1; } - num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS); debug ("size_ratio %d port %d bits chip %d bits\n", size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); @@ -1171,7 +1266,12 @@ ulong flash_get_size (ulong base, int banknum) num_erase_regions, NUM_ERASE_REGIONS); break; } - tmp = flash_read_long (info, 0, + if (geometry_reversed) + tmp = flash_read_long (info, 0, + FLASH_OFFSET_ERASE_REGIONS + + (num_erase_regions - 1 - i) * 4); + else + tmp = flash_read_long (info, 0, FLASH_OFFSET_ERASE_REGIONS + i * 4); erase_region_size = diff --git a/include/flash.h b/include/flash.h index d91589a6c02..9c57cbc427c 100644 --- a/include/flash.h +++ b/include/flash.h @@ -43,9 +43,14 @@ typedef struct { ulong write_tout; /* maximum write timeout */ ulong buffer_write_tout; /* maximum buffer write timeout */ ushort vendor; /* the primary vendor id */ - ushort cmd_reset; /* Vendor specific reset command */ + ushort cmd_reset; /* vendor specific reset command */ ushort interface; /* used for x8/x16 adjustments */ ushort legacy_unlock; /* support Intel legacy (un)locking */ + uchar manufacturer_id; /* manufacturer id */ + ushort device_id; /* device id */ + ushort device_id2; /* extended device id */ + ushort ext_addr; /* extended query table address */ + ushort cfi_version; /* cfi version */ #endif } flash_info_t; @@ -439,6 +444,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define FLASH_MAN_MT 0x00400000 #define FLASH_MAN_SHARP 0x00500000 #define FLASH_MAN_ATM 0x00600000 +#define FLASH_MAN_CFI 0x01000000 #define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */ -- cgit v1.3.1 From 4ef6251403f637841000e0fef9e832aa01339822 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 20 Nov 2006 20:39:52 +0100 Subject: [PATCH] Update AMCC Sequoia config file to support 64MByte NOR FLASH Signed-off-by: Stefan Roese --- include/configs/sequoia.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 3a76315b444..1a460cde067 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -53,7 +53,7 @@ #define CFG_BOOT_BASE_ADDR 0xf0000000 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ #define CFG_MONITOR_BASE TEXT_BASE #define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ #define CFG_OCM_BASE 0xe0010000 /* ocm */ @@ -234,10 +234,10 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ + "rootpath=/opt/eldk/ppc_4xxFP\0" \ "bootfile=/tftpboot/sequoia/uImage\0" \ - "kernel_addr=FE000000\0" \ - "ramdisk_addr=FE180000\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC180000\0" \ "load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ "cp.b 100000 FFFA0000 60000\0" \ @@ -378,7 +378,7 @@ #define CFG_NAND_CS 3 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x03017300 -#define CFG_EBC_PB0CR (CFG_FLASH | 0xba000) +#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) /* Memory Bank 3 (NAND-FLASH) initialization */ #define CFG_EBC_PB3AP 0x018003c0 @@ -387,7 +387,7 @@ #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ /* Memory Bank 3 (NOR-FLASH) initialization */ #define CFG_EBC_PB3AP 0x03017300 -#define CFG_EBC_PB3CR (CFG_FLASH | 0xba000) +#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000) /* Memory Bank 0 (NAND-FLASH) initialization */ #define CFG_EBC_PB0AP 0x018003c0 -- cgit v1.3.1 From 78d620ebb5871d252270dedfad60c6568993b780 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 23 Nov 2006 22:58:58 +0100 Subject: Updates for TQM5200 modules: - fix off-by-one error in board/tqm5200/cam5200_flash.c error message - simplify "udate" definitions --- board/tqm5200/cam5200_flash.c | 2 +- board/tqm5200/tqm5200.c | 2 +- include/configs/TQM5200.h | 46 +++++++++++-------------------------------- 3 files changed, 13 insertions(+), 37 deletions(-) (limited to 'include') diff --git a/board/tqm5200/cam5200_flash.c b/board/tqm5200/cam5200_flash.c index 1a40633e569..8c3f62e398c 100644 --- a/board/tqm5200/cam5200_flash.c +++ b/board/tqm5200/cam5200_flash.c @@ -759,7 +759,7 @@ unsigned long flash_init(void) if (flash_info[i].flash_id == FLASH_UNKNOWN) { printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); + i+1, size_b[i], size_b[i] << 20); flash_info[i].sector_count = -1; flash_info[i].size = 0; } diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index cb57a5e2694..a4322b6661a 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -289,7 +289,7 @@ int checkboard (void) #elif defined(CONFIG_TB5200) # define CARRIER_NAME "TB5200" #elif defined(CONFIG_CAM5200) -# define CARRIER_NAME "Cam5200" +# define CARRIER_NAME "CAM5200" #elif defined(CONFIG_FO300) # define CARRIER_NAME "FO300" #else diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 4bae103e09c..08674ca49f5 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -217,43 +217,19 @@ #undef CONFIG_BOOTARGS -#ifdef CONFIG_STK52XX -# if defined(CONFIG_TQM5200_B) -# if defined(CFG_LOWBOOT) -# define ENV_UPDT \ - "update=protect off FC000000 FC07FFFF;" \ - "erase FC000000 FC07FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC07FFFF\0" -# else /* highboot */ -# define ENV_UPDT \ - "update=protect off FFF00000 FFF7FFFF;" \ - "erase FFF00000 FFF7FFFF;" \ +#if defined(CONFIG_TQM5200_B) && !defined(CFG_LOWBOOT) +# define ENV_UPDT \ + "update=protect off FFF00000 +${filesize};" \ + "erase FFF00000 +${filesize};" \ "cp.b 200000 FFF00000 ${filesize};" \ - "protect on FFF00000 FFF7FFFF\0" -# endif /* CFG_LOWBOOT */ -# else /* !CONFIG_TQM5200_B */ -# define ENV_UPDT \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" -# endif /* CONFIG_TQM5200_B */ -#elif defined (CONFIG_CAM5200) -# define ENV_UPDT \ - "update=protect off FC000000 FC03FFFF;" \ - "erase FC000000 FC03FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC03FFFF\0" -#elif defined (CONFIG_FO300) + "protect on FFF00000 +${filesize}\0" +#else /* default lowboot configuration */ # define ENV_UPDT \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ + "update=protect off FC000000 +${filesize};" \ + "erase FC000000 +${filesize};" \ "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" -#else -# error "Unknown Carrier Board" -#endif /* CONFIG_STK52XX */ + "protect on FC000000 +${filesize}\0" +#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ @@ -432,7 +408,7 @@ */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */ -#if defined(CONFIG_TQM5200_B) +#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200) #define CFG_ENV_SECT_SIZE 0x40000 #else #define CFG_ENV_SECT_SIZE 0x20000 -- cgit v1.3.1