From 821ad16fa9900c9b48e9af678b4a5d7808a58f7c Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Mon, 9 Aug 2010 17:57:47 -0400
Subject: Blackfin: move CONFIG_BFIN_CPU to board config.mk

The CONFIG_BFIN_CPU option is largely used in the build system, so move
it out of the board config.h and into the board config.mk.  It'd be nice
to keep everything in the config.h, but the patch to extract that value
early was rejected.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bf518f-ezbrd.h      | 1 -
 include/configs/bf526-ezbrd.h       | 1 -
 include/configs/bf527-ad7160-eval.h | 1 -
 include/configs/bf527-ezkit.h       | 1 -
 include/configs/bf533-ezkit.h       | 1 -
 include/configs/bf533-stamp.h       | 1 -
 include/configs/bf537-minotaur.h    | 1 -
 include/configs/bf537-pnav.h        | 1 -
 include/configs/bf537-srv1.h        | 1 -
 include/configs/bf537-stamp.h       | 1 -
 include/configs/bf538f-ezkit.h      | 1 -
 include/configs/bf548-ezkit.h       | 1 -
 include/configs/bf561-acvilon.h     | 1 -
 include/configs/bf561-ezkit.h       | 1 -
 include/configs/blackstamp.h        | 1 -
 include/configs/cm-bf527.h          | 1 -
 include/configs/cm-bf533.h          | 1 -
 include/configs/cm-bf537e.h         | 1 -
 include/configs/cm-bf537u.h         | 1 -
 include/configs/cm-bf548.h          | 1 -
 include/configs/cm-bf561.h          | 1 -
 include/configs/ibf-dsp561.h        | 1 -
 include/configs/ip04.h              | 1 -
 include/configs/tcm-bf518.h         | 1 -
 include/configs/tcm-bf537.h         | 1 -
 25 files changed, 25 deletions(-)

(limited to 'include')

diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
index 6eec1c91a7e..64ca9ed4393 100644
--- a/include/configs/bf518f-ezbrd.h
+++ b/include/configs/bf518f-ezbrd.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf518-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index 82396d0ed25..eeca9caf8bc 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf526-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h
index eb3a2b7dc11..fbcf019051c 100644
--- a/include/configs/bf527-ad7160-eval.h
+++ b/include/configs/bf527-ad7160-eval.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf527-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
 
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index 07e4ce86e12..54fc063f9a1 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf527-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index 95d3afa85cc..e1bb5944388 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf533-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index f39bfee0a4f..b8cea99959d 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf533-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
index 86aa1f61e66..0ba29bc0cd8 100644
--- a/include/configs/bf537-minotaur.h
+++ b/include/configs/bf537-minotaur.h
@@ -24,7 +24,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
 
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
index 39bbb41fb3e..30607d91fd1 100644
--- a/include/configs/bf537-pnav.h
+++ b/include/configs/bf537-pnav.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
 
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
index 7e9dd36bce2..559428f4845 100644
--- a/include/configs/bf537-srv1.h
+++ b/include/configs/bf537-srv1.h
@@ -24,7 +24,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
 
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index fc9784e0830..60087da1142 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
index 1c14b6bdd37..1d475647aac 100644
--- a/include/configs/bf538f-ezkit.h
+++ b/include/configs/bf538f-ezkit.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf538-0.4
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index 60cca0c07a3..d299dc18f5f 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf548-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
index 0c0204fbd79..2b12c3fbe11 100644
--- a/include/configs/bf561-acvilon.h
+++ b/include/configs/bf561-acvilon.h
@@ -12,7 +12,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU				bf561-0.5
 #define CONFIG_BFIN_BOOT_MODE		BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 4e293b58a82..1557e14f523 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf561-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h
index 85f08ea8880..3f5c95917d0 100644
--- a/include/configs/blackstamp.h
+++ b/include/configs/blackstamp.h
@@ -24,7 +24,6 @@
 /* CPU Options
  * Be sure to set the Silicon Revision Correctly
  */
-#define CONFIG_BFIN_CPU		bf532-0.5
 #define CONFIG_BFIN_BOOT_MODE	BFIN_BOOT_SPI_MASTER
 
 /*
diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h
index e0c6d53b2c7..84c93099ce9 100644
--- a/include/configs/cm-bf527.h
+++ b/include/configs/cm-bf527.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf527-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h
index 75152964b61..dbc4a5b1002 100644
--- a/include/configs/cm-bf533.h
+++ b/include/configs/cm-bf533.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf533-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 742df9c0199..df3fe48f655 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index 9def99f7283..e5b0ecfc5e9 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
index fa62a8e9c1d..27b1cc519cc 100644
--- a/include/configs/cm-bf548.h
+++ b/include/configs/cm-bf548.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf548-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h
index c60401c8fec..8c350bc2639 100644
--- a/include/configs/cm-bf561.h
+++ b/include/configs/cm-bf561.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf561-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h
index 53b5197112e..cd856ac79c3 100644
--- a/include/configs/ibf-dsp561.h
+++ b/include/configs/ibf-dsp561.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf561-0.5
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/ip04.h b/include/configs/ip04.h
index c024d78c18a..528363c6b49 100644
--- a/include/configs/ip04.h
+++ b/include/configs/ip04.h
@@ -20,7 +20,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf532-0.5
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_NAND
 
 
diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h
index 52055e80dcb..042d78915c8 100644
--- a/include/configs/tcm-bf518.h
+++ b/include/configs/tcm-bf518.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf518-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index 24ce8f854a1..dceff308b8b 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
-- 
cgit v1.3.1


From f453220c1ef176409197f67e064646ffd143de64 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Sun, 19 Sep 2010 16:26:55 -0400
Subject: Blackfin: adi config: add an "all spi flashes" option to unify board
 lists

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bf533-stamp.h     |  5 +----
 include/configs/bf537-stamp.h     |  5 +----
 include/configs/bf538f-ezkit.h    |  5 +----
 include/configs/bfin_adi_common.h | 12 ++++++++++++
 4 files changed, 15 insertions(+), 12 deletions(-)

(limited to 'include')

diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index b8cea99959d..03bc811036f 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -92,10 +92,7 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_ALL
 
 
 /*
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 60087da1142..22d31508eb9 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -88,10 +88,7 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_ALL
 
 
 /*
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
index 1d475647aac..04ba2101716 100644
--- a/include/configs/bf538f-ezkit.h
+++ b/include/configs/bf538f-ezkit.h
@@ -85,10 +85,7 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_ALL
 
 
 /*
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 91dcaccb4fb..bf3952cec34 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -254,6 +254,18 @@
 # define CONFIG_NET_RETRY_COUNT 20
 #endif
 
+/*
+ * SPI Settings
+ */
+#ifdef CONFIG_SPI_FLASH_ALL
+# define CONFIG_SPI_FLASH_ATMEL
+# define CONFIG_SPI_FLASH_MACRONIX
+# define CONFIG_SPI_FLASH_SPANSION
+# define CONFIG_SPI_FLASH_SST
+# define CONFIG_SPI_FLASH_STMICRO
+# define CONFIG_SPI_FLASH_WINBOND
+#endif
+
 /*
  * I2C Settings
  */
-- 
cgit v1.3.1


From c2d8b9652ed4c62d579eb9e090efbdc04702e087 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Sun, 19 Sep 2010 16:27:24 -0400
Subject: Blackfin: adi config: add a hook for boards to append the env

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bfin_adi_common.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index bf3952cec34..55b8b0be343 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -231,10 +231,14 @@
 #else
 # define NETWORK_ENV_SETTINGS
 #endif
+#ifndef BOARD_ENV_SETTINGS
+# define BOARD_ENV_SETTINGS
+#endif
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	NAND_ENV_SETTINGS \
 	NETWORK_ENV_SETTINGS \
-	FLASHBOOT_ENV_SETTINGS
+	FLASHBOOT_ENV_SETTINGS \
+	BOARD_ENV_SETTINGS
 
 /*
  * Network Settings
-- 
cgit v1.3.1


From 581e97df38dd23bf0b0e3840bbebd0cd730ddfc5 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Sun, 19 Sep 2010 16:28:40 -0400
Subject: Blackfin: bf527-sdp: new board port

Support for the Blackfin System Development Platform (SDP) base module.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 MAINTAINERS                 |   1 +
 board/bf527-sdp/Makefile    |  54 ++++++++++++++++++++
 board/bf527-sdp/bf527-sdp.c |  32 ++++++++++++
 board/bf527-sdp/config.mk   |  36 +++++++++++++
 boards.cfg                  |   1 +
 include/configs/bf527-sdp.h | 121 ++++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 245 insertions(+)
 create mode 100644 board/bf527-sdp/Makefile
 create mode 100644 board/bf527-sdp/bf527-sdp.c
 create mode 100644 board/bf527-sdp/config.mk
 create mode 100644 include/configs/bf527-sdp.h

(limited to 'include')

diff --git a/MAINTAINERS b/MAINTAINERS
index 2cf29dd1d79..b0cc8254e0e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -993,6 +993,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 	BF526-EZBRD	BF526
 	BF527-EZKIT	BF527
 	BF527-EZKIT-V2	BF527
+	BF527-SDP	BF527
 	BF533-EZKIT	BF533
 	BF533-STAMP	BF533
 	BF537-PNAV	BF537
diff --git a/board/bf527-sdp/Makefile b/board/bf527-sdp/Makefile
new file mode 100644
index 00000000000..f2bd2c247d4
--- /dev/null
+++ b/board/bf527-sdp/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf527-sdp/bf527-sdp.c b/board/bf527-sdp/bf527-sdp.c
new file mode 100644
index 00000000000..504869d72a4
--- /dev/null
+++ b/board/bf527-sdp/bf527-sdp.c
@@ -0,0 +1,32 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/mach-common/bits/pll.h>
+
+int checkboard(void)
+{
+	printf("Board: ADI BF527 SDP board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+
+	/* Enable access to parallel flash */
+	gpio_request(GPIO_PG0, "parallel-flash");
+	gpio_direction_output(GPIO_PG0, 0);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	/* CLKIN Buffer Output Enable */
+	bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
+
+	return 0;
+}
diff --git a/board/bf527-sdp/config.mk b/board/bf527-sdp/config.mk
new file mode 100644
index 00000000000..744e7a5d0d5
--- /dev/null
+++ b/board/bf527-sdp/config.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf527-0.2
+
+CFLAGS_lib_generic += -O2
+CFLAGS_lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/boards.cfg b/boards.cfg
index 02eb15328f4..8689ba4cd06 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -283,6 +283,7 @@ bf518f-ezbrd	blackfin	blackfin
 bf526-ezbrd	blackfin	blackfin
 bf527-ad7160-eval blackfin	blackfin
 bf527-ezkit	blackfin	blackfin
+bf527-sdp	blackfin	blackfin
 bf533-ezkit	blackfin	blackfin
 bf533-stamp	blackfin	blackfin
 bf537-minotaur	blackfin	blackfin
diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h
new file mode 100644
index 00000000000..358284619c7
--- /dev/null
+++ b/include/configs/bf527-sdp.h
@@ -0,0 +1,121 @@
+/*
+ * U-boot - Configuration file for BF527 SDP board
+ */
+
+#ifndef __CONFIG_BF527_SDP_H__
+#define __CONFIG_BF527_SDP_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			24000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			25
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+#define CONFIG_PLL_LOCKCNT_VAL	0x0200
+#define CONFIG_PLL_CTL_VAL		0x2a00
+#define CONFIG_VR_CTL_VAL		0x7090
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		32
+
+#define CONFIG_EBIU_SDRRC_VAL	0x00FE
+#define CONFIG_EBIU_SDGCTL_VAL	0x8011998d
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	259
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ALL
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_UART_CONSOLE	0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
-- 
cgit v1.3.1


From 56f0c57b4be8da1e0bbfb52e8aa0fa93f8f8a4e9 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Mon, 20 Sep 2010 15:14:58 -0400
Subject: Blackfin: adi config: allow boards to tweak a little more

Let people easily override bootdelay and network settings.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bfin_adi_common.h | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

(limited to 'include')

diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 55b8b0be343..22312f5f5cf 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -119,10 +119,12 @@
 /*
  * Env Settings
  */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
-# define CONFIG_BOOTDELAY	-1
-#else
-# define CONFIG_BOOTDELAY	5
+#ifndef CONFIG_BOOTDELAY
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+#  define CONFIG_BOOTDELAY	-1
+# else
+#  define CONFIG_BOOTDELAY	5
+# endif
 #endif
 #ifndef CONFIG_BOOTCOMMAND
 # define CONFIG_BOOTCOMMAND	"run ramboot"
@@ -244,11 +246,15 @@
  * Network Settings
  */
 #ifdef CONFIG_CMD_NET
-# define CONFIG_IPADDR		192.168.0.15
 # define CONFIG_NETMASK		255.255.255.0
-# define CONFIG_GATEWAYIP	192.168.0.1
-# define CONFIG_SERVERIP	192.168.0.2
-# define CONFIG_ROOTPATH	/romfs
+# ifndef CONFIG_IPADDR
+#  define CONFIG_IPADDR		192.168.0.15
+#  define CONFIG_GATEWAYIP	192.168.0.1
+#  define CONFIG_SERVERIP	192.168.0.2
+# endif
+# ifndef CONFIG_ROOTPATH
+#  define CONFIG_ROOTPATH	/romfs
+# endif
 # ifdef CONFIG_CMD_DHCP
 #  ifndef CONFIG_SYS_AUTOLOAD
 #   define CONFIG_SYS_AUTOLOAD "no"
-- 
cgit v1.3.1


From 063993299f65146b31bdf82e3628b0c4b0d3bd20 Mon Sep 17 00:00:00 2001
From: Peter Meerwald <pmeerw@pmeerw.net>
Date: Mon, 20 Sep 2010 14:08:57 -0400
Subject: Blackfin: bct-brettl2: new board port

Signed-off-by: Peter Meerwald <pmeerw@pmeerw.net>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 MAINTAINERS                        |   4 +
 board/bct-brettl2/Makefile         |  51 +++++++++++
 board/bct-brettl2/bct-brettl2.c    | 123 ++++++++++++++++++++++++++
 board/bct-brettl2/cled.c           |  32 +++++++
 board/bct-brettl2/config.mk        |  35 ++++++++
 board/bct-brettl2/gpio_cfi_flash.c |   4 +
 board/bct-brettl2/smsc9303.c       | 176 +++++++++++++++++++++++++++++++++++++
 board/bct-brettl2/smsc9303.h       |   9 ++
 boards.cfg                         |   1 +
 include/configs/bct-brettl2.h      | 155 ++++++++++++++++++++++++++++++++
 10 files changed, 590 insertions(+)
 create mode 100644 board/bct-brettl2/Makefile
 create mode 100644 board/bct-brettl2/bct-brettl2.c
 create mode 100644 board/bct-brettl2/cled.c
 create mode 100644 board/bct-brettl2/config.mk
 create mode 100644 board/bct-brettl2/gpio_cfi_flash.c
 create mode 100644 board/bct-brettl2/smsc9303.c
 create mode 100644 board/bct-brettl2/smsc9303.h
 create mode 100644 include/configs/bct-brettl2.h

(limited to 'include')

diff --git a/MAINTAINERS b/MAINTAINERS
index b0cc8254e0e..d6a701d9967 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1041,6 +1041,10 @@ Brent Kandetzki <brentk@teleco.com>
 
 	IP04		BF532
 
+Peter Meerwald <devel@bct-electronic.com>
+
+	bct-brettl2	BF536
+
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/board/bct-brettl2/Makefile b/board/bct-brettl2/Makefile
new file mode 100644
index 00000000000..cf99d29f1c1
--- /dev/null
+++ b/board/bct-brettl2/Makefile
@@ -0,0 +1,51 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o gpio_cfi_flash.o cled.o
+COBJS-$(CONFIG_BFIN_MAC) += smsc9303.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/bct-brettl2/bct-brettl2.c b/board/bct-brettl2/bct-brettl2.c
new file mode 100644
index 00000000000..de5b9ff0e75
--- /dev/null
+++ b/board/bct-brettl2/bct-brettl2.c
@@ -0,0 +1,123 @@
+/*
+ * U-boot - main board file for BCT brettl2
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/portmux.h>
+#include <asm/gpio.h>
+#include <asm/net.h>
+#include <net.h>
+#include <netdev.h>
+#include <miiphy.h>
+
+#include "../cm-bf537e/gpio_cfi_flash.h"
+#include "smsc9303.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: bct-brettl2 board\n");
+	printf("       Support: http://www.bct-electronic.com/\n");
+	return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+	puts("Warning: Generating 'random' MAC address\n");
+	bfin_gen_rand_mac(mac_addr);
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int retry = 3;
+	int ret;
+
+	ret = bfin_EMAC_initialize(bis);
+
+	uchar enetaddr[6];
+	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		printf("setting MAC %pM\n", enetaddr);
+	}
+	puts("       ");
+
+	puts("initialize SMSC LAN9303i ethernet switch\n");
+
+	while (retry-- > 0) {
+		if (init_smsc9303i_mii())
+			return ret;
+	}
+
+	return ret;
+}
+#endif
+
+static void init_tlv320aic31(void)
+{
+	puts("Audio: setup TIMER0 to enable 16.384 MHz clock for tlv320aic31\n");
+	peripheral_request(P_TMR0, "tlv320aic31 clock");
+	bfin_write_TIMER0_CONFIG(0x020d);
+	bfin_write_TIMER0_PERIOD(0x0008);
+	bfin_write_TIMER0_WIDTH(0x0008/2);
+	bfin_write_TIMER_ENABLE(bfin_read_TIMER_ENABLE() | 1);
+	SSYNC();
+	udelay(10000);
+
+	puts("       resetting tlv320aic31\n");
+
+	gpio_request(GPIO_PF2, "tlv320aic31");
+	gpio_direction_output(GPIO_PF2, 0);
+	udelay(10000);
+	gpio_direction_output(GPIO_PF2, 1);
+	udelay(10000);
+	gpio_free(GPIO_PF2);
+}
+
+static void init_mute_pin(void)
+{
+	printf("       unmute class D amplifier\n");
+
+	gpio_request(GPIO_PF5, "mute");
+	gpio_direction_output(GPIO_PF5, 1);
+	gpio_free(GPIO_PF5);
+}
+
+/* sometimes LEDs (speech, status) are still on after reboot, turn 'em off */
+static void turn_leds_off(void)
+{
+	printf("       turn LEDs off\n");
+
+	gpio_request(GPIO_PF6, "led");
+	gpio_direction_output(GPIO_PF6, 0);
+	gpio_free(GPIO_PF6);
+
+	gpio_request(GPIO_PF15, "led");
+	gpio_direction_output(GPIO_PF15, 0);
+	gpio_free(GPIO_PF15);
+}
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+	gpio_cfi_flash_init();
+	init_tlv320aic31();
+	init_mute_pin();
+	turn_leds_off();
+
+	return 0;
+}
diff --git a/board/bct-brettl2/cled.c b/board/bct-brettl2/cled.c
new file mode 100644
index 00000000000..9e73c57b878
--- /dev/null
+++ b/board/bct-brettl2/cled.c
@@ -0,0 +1,32 @@
+/*
+ * cled.c - control color led
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+
+int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr = 0x20000000 + 0x200000; // AMS2
+	uchar data;
+
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	data = simple_strtoul(argv[1], NULL, 10);
+	outb(data, addr);
+
+	printf("cled, write %02x\n", data);
+
+	return 0;
+}
+
+U_BOOT_CMD(cled, 2, 0, do_cled,
+	"set/clear color LED",
+	"");
diff --git a/board/bct-brettl2/config.mk b/board/bct-brettl2/config.mk
new file mode 100644
index 00000000000..dfd94569e1b
--- /dev/null
+++ b/board/bct-brettl2/config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf536-0.3
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/bct-brettl2/gpio_cfi_flash.c b/board/bct-brettl2/gpio_cfi_flash.c
new file mode 100644
index 00000000000..b385c7fc0ed
--- /dev/null
+++ b/board/bct-brettl2/gpio_cfi_flash.c
@@ -0,0 +1,4 @@
+#define GPIO_PIN_1 GPIO_PG5
+#define GPIO_PIN_2 GPIO_PG6
+#define GPIO_PIN_3 GPIO_PG7
+#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/bct-brettl2/smsc9303.c b/board/bct-brettl2/smsc9303.c
new file mode 100644
index 00000000000..15eea7a4841
--- /dev/null
+++ b/board/bct-brettl2/smsc9303.c
@@ -0,0 +1,176 @@
+/*
+ * smsc9303.c - routines to initialize SMSC 9303 switch
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <miiphy.h>
+
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+
+static int smc9303i_write_mii(unsigned char addr, unsigned char reg, unsigned short data)
+{
+	const char *devname = miiphy_get_current_dev();
+
+	if (!devname)
+	    return 0;
+
+	if (miiphy_write(devname, addr, reg, data) != 0)
+	    return 0;
+
+	return 1;
+}
+
+static int smc9303i_write_reg(unsigned short reg, unsigned int data)
+{
+	const char *devname = miiphy_get_current_dev();
+	unsigned char mii_addr = 0x10 | (reg >> 6);
+	unsigned char mii_reg = (reg & 0x3c) >> 1;
+
+	if (!devname)
+	    return 0;
+
+	if (miiphy_write(devname, mii_addr, mii_reg|0, data & 0xffff) != 0)
+	    return 0;
+
+	if (miiphy_write(devname, mii_addr, mii_reg|1, data >> 16) != 0)
+	    return 0;
+
+	return 1;
+}
+
+static int smc9303i_read_reg(unsigned short reg, unsigned int *data)
+{
+	const char *devname = miiphy_get_current_dev();
+	unsigned char mii_addr = 0x10 | (reg >> 6);
+	unsigned char mii_reg = (reg & 0x3c) >> 1;
+	unsigned short tmp1, tmp2;
+
+	if (!devname)
+	    return 0;
+
+	if (miiphy_read(devname, mii_addr, mii_reg|0, &tmp1) != 0)
+	    return 0;
+
+	if (miiphy_read(devname, mii_addr, mii_reg|1, &tmp2) != 0)
+	    return 0;
+
+	*data = (tmp2 << 16) | tmp1;
+
+	return 1;
+}
+
+#if 0
+static int smc9303i_read_mii(unsigned char addr, unsigned char reg, unsigned short *data)
+{
+	const char *devname = miiphy_get_current_dev();
+
+	if (!devname)
+	    return 0;
+
+	if (miiphy_read(devname, addr, reg, data) != 0)
+	    return 0;
+
+	return 1;
+}
+#endif
+
+typedef struct {
+	unsigned short reg;
+	unsigned int value;
+} smsc9303i_config_entry1_t;
+
+static const smsc9303i_config_entry1_t smsc9303i_config_table1[] =
+{
+	{0x1a0, 0x00000006}, /* Port 1 Manual Flow Control Register */
+	{0x1a4, 0x00000006}, /* Port 2 Manual Flow Control Register */
+	{0x1a8, 0x00000006}, /* Port 0 Manual Flow Control Register */
+};
+
+typedef struct
+{
+	unsigned char addr;
+	unsigned char reg;
+	unsigned short value;
+} smsc9303i_config_entry2_t;
+
+static const smsc9303i_config_entry2_t smsc9303i_config_table2[] =
+{
+	{0x01, 0x00, 0x0100}, /* Port0 PHY Basic Control Register */
+	{0x02, 0x00, 0x1100}, /* Port1 PHY Basic Control Register */
+	{0x03, 0x00, 0x1100}, /* Port2 PHY Basic Control Register */
+
+	{0x01, 0x04, 0x0001}, /* Port0 PHY Auto-Negotiation Advertisement Register */
+	{0x02, 0x04, 0x2de1}, /* Port1 PHY Auto-Negotiation Advertisement Register */
+	{0x03, 0x04, 0x2de1}, /* Port2 PHY Auto-Negotiation Advertisement Register */
+
+	{0x01, 0x11, 0x0000}, /* Port0 PHY Mode Control/Status Register */
+	{0x02, 0x11, 0x0000}, /* Port1 PHY Mode Control/Status Register */
+	{0x03, 0x11, 0x0000}, /* Port2 PHY Mode Control/Status Register */
+
+	{0x01, 0x12, 0x0021}, /* Port0 PHY Special Modes Register */
+	{0x02, 0x12, 0x00e2}, /* Port1 PHY Special Modes Register */
+	{0x03, 0x12, 0x00e3}, /* Port2 PHY Special Modes Register */
+	{0x01, 0x1b, 0x0000}, /* Port0 PHY Special Control/Status Indication Register */
+	{0x02, 0x1b, 0x0000}, /* Port1 PHY Special Control/Status Indication Register */
+	{0x03, 0x1b, 0x0000}, /* Port2 PHY Special Control/Status Indication Register */
+	{0x01, 0x1e, 0x0000}, /* Port0 PHY Interrupt Source Flags Register */
+	{0x02, 0x1e, 0x0000}, /* Port1 PHY Interrupt Source Flags Register */
+	{0x03, 0x1e, 0x0000}, /* Port2 PHY Interrupt Source Flags Register */
+};
+
+int init_smsc9303i_mii(void)
+{
+	unsigned int data;
+	unsigned int i;
+
+	printf("       reset SMSC LAN9303i\n");
+
+	gpio_request(GPIO_PG10, "smsc9303");
+	gpio_direction_output(GPIO_PG10, 0);
+	udelay(10000);
+	gpio_direction_output(GPIO_PG10, 1);
+	udelay(10000);
+
+	gpio_free(GPIO_PG10);
+
+#if defined(CONFIG_MII_INIT)
+	mii_init();
+#endif
+
+	printf("       write SMSC LAN9303i configuration\n");
+
+	if (!smc9303i_read_reg(0x50, &data))
+		return 0;
+
+	if ((data >> 16) != 0x9303)	{
+		/* chip id not found */
+		printf("       error identifying SMSC LAN9303i\n");
+		return 0;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table1); i++) {
+		const smsc9303i_config_entry1_t *entry = &smsc9303i_config_table1[i];
+
+		if (!smc9303i_write_reg(entry->reg, entry->value)) {
+			printf("       error writing SMSC LAN9303i configuration\n");
+			return 0;
+		}
+	}
+
+	for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table2); i++) {
+		const smsc9303i_config_entry2_t *entry = &smsc9303i_config_table2[i];
+
+		if (!smc9303i_write_mii(entry->addr, entry->reg, entry->value)) {
+			printf("       error writing SMSC LAN9303i configuration\n");
+			return 0;
+		}
+	}
+
+	return 1;
+}
diff --git a/board/bct-brettl2/smsc9303.h b/board/bct-brettl2/smsc9303.h
new file mode 100644
index 00000000000..a4ba40ef730
--- /dev/null
+++ b/board/bct-brettl2/smsc9303.h
@@ -0,0 +1,9 @@
+/*
+ * smsc9303.h - routines to initialize SMSC 9303 switch
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+int init_smsc9303i_mii(void);
diff --git a/boards.cfg b/boards.cfg
index 8689ba4cd06..86838f21bb0 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -279,6 +279,7 @@ atstk1004	avr32	at32ap		atstk1000	atmel		at32ap700x
 atstk1006	avr32	at32ap		atstk1000	atmel		at32ap700x
 favr-32-ezkit	avr32	at32ap		-		earthlcd	at32ap700x
 hammerhead	avr32	at32ap		-		miromico	at32ap700x
+bct-brettl2	blackfin	blackfin
 bf518f-ezbrd	blackfin	blackfin
 bf526-ezbrd	blackfin	blackfin
 bf527-ad7160-eval blackfin	blackfin
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
new file mode 100644
index 00000000000..09691d37377
--- /dev/null
+++ b/include/configs/bct-brettl2.h
@@ -0,0 +1,155 @@
+/*
+ * U-boot - Configuration file for BF536 brettl2 board
+ */
+
+#ifndef __CONFIG_BCT_BRETTL2_H__
+#define __CONFIG_BCT_BRETTL2_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			16384000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			24
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			3
+#define CONFIG_VR_CTL_VAL       (VLEV_110 | GAIN_20 | FREQ_1000)
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		32
+
+
+/*
+ * SDRAM Settings
+ */
+#define CONFIG_EBIU_SDRRC_VAL	0x07f6
+#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC		1
+#define CONFIG_NETCONSOLE	1
+#define CONFIG_NET_MULTI	1
+#define CONFIG_HOSTNAME		brettl2
+#define CONFIG_IPADDR		192.168.233.224
+#define CONFIG_GATEWAYIP	192.168.233.1
+#define CONFIG_SERVERIP		192.168.233.53
+#define CONFIG_ROOTPATH		/romfs/brettl2
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+#endif
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_BASE			0x20000000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+#ifdef ENV_IS_EMBEDDED
+/* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+# define LDS_BOARD_TEXT \
+        arch/blackfin/cpu/traps.o            (.text .text.*); \
+        arch/blackfin/cpu/interrupt.o        (.text .text.*); \
+        arch/blackfin/cpu/serial.o           (.text .text.*); \
+        common/dlmalloc.o               (.text .text.*); \
+        lib/crc32.o             (.text .text.*); \
+        . = DEFINED(env_offset) ? env_offset : .; \
+        common/env_embedded.o           (.text .text.*);
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BOOTDELAY	1
+#define CONFIG_LOADADDR		0x800000
+#define CONFIG_MISC_INIT_R
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+/* disable unnecessary features */
+#undef CONFIG_BOOTM_RTEMS
+#undef CONFIG_BZIP2
+#undef CONFIG_KALLSYMS
+
+#endif
-- 
cgit v1.3.1


From 4cd4c2d20af520ebb75da8d44a5326765f6b44e0 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Tue, 21 Sep 2010 19:33:53 -0400
Subject: Blackfin: adi config: enable nand lock/unlock support

We use the lock/unlock options in our default nand code, so enabl
support for the options.

Reported-by: Vivi Li <vivi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bfin_adi_common.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include')

diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 22312f5f5cf..3e9f3b2c90d 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -47,6 +47,7 @@
 # endif
 # if defined(CONFIG_NAND_PLAT) || defined(CONFIG_DRIVER_NAND_BFIN)
 #  define CONFIG_CMD_NAND
+#  define CONFIG_CMD_NAND_LOCK_UNLOCK
 # endif
 # ifdef CONFIG_POST
 #  define CONFIG_CMD_DIAG
-- 
cgit v1.3.1


From 301e66a956db6401f4f008a1667b12d2546b1e7b Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Tue, 21 Sep 2010 19:47:27 -0400
Subject: Blackfin: bf526-ezbrd: enable BootROM-OOB layout when booting from
 NAND

We need to use the Blackfin BootROM-specific OOB layout when we boot out
of NAND as that is what the on-chip ROM expects.

Also need to increase the monitor size a little to accommodate the extra
NAND code overhead.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bf526-ezbrd.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'include')

diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index eeca9caf8bc..4c30c25392d 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -52,7 +52,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
 #define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
 
-#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024)
 
 
@@ -61,7 +61,8 @@
  * (can't be used same time as ethernet)
  */
 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-#define CONFIG_BFIN_NFC
+# define CONFIG_BFIN_NFC
+# define CONFIG_BFIN_NFC_BOOTROM_ECC
 #endif
 #ifdef CONFIG_BFIN_NFC
 #define CONFIG_BFIN_NFC_CTL_VAL	0x0033
-- 
cgit v1.3.1


From 3bbed7f88a433b6cd5e9260d88c82dfac4ef7aa1 Mon Sep 17 00:00:00 2001
From: Wojtek Skulski <skulski@pas.rochester.edu>
Date: Mon, 27 Sep 2010 18:21:59 -0400
Subject: Blackfin: blackvme: new board port

The board includes:
 * ADSP-BF561 rev. 0.5
 * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG)
 * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell)
 * SPI  boot flash on PF2 (M25P64 8MB, or M25P128 16 MB)
 * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB)
 * Spartan6-LX150 (memory-mapped; both PPIs also connected)
 * See http://www.skutek.com/

Signed-off-by: Wojtek Skulski <skulski@pas.rochester.edu>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 MAINTAINERS                |   5 +-
 board/blackvme/Makefile    |  54 ++++++++++
 board/blackvme/blackvme.c  |  31 ++++++
 board/blackvme/config.mk   |  32 ++++++
 boards.cfg                 |   1 +
 include/configs/blackvme.h | 246 +++++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 368 insertions(+), 1 deletion(-)
 create mode 100644 board/blackvme/Makefile
 create mode 100644 board/blackvme/blackvme.c
 create mode 100644 board/blackvme/config.mk
 create mode 100644 include/configs/blackvme.h

(limited to 'include')

diff --git a/MAINTAINERS b/MAINTAINERS
index d6a701d9967..4b23c8366a3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1023,9 +1023,12 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 	BF537-srv1	BF537
 
 Wojtek Skulski <skulski@pas.rochester.edu>
+Wojtek Skulski <info@skutek.com>
+Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Benjamin Matthews <mben12@gmail.com>
 
-	BLACKSTAMP	BF532
+	BlackStamp	BF533
+	BlackVME	BF561
 
 I-SYST Micromodule <support@i-syst.com>
 Blackfin Team <u-boot-devel@blackfin.uclinux.org>
diff --git a/board/blackvme/Makefile b/board/blackvme/Makefile
new file mode 100644
index 00000000000..f2bd2c247d4
--- /dev/null
+++ b/board/blackvme/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/blackvme/blackvme.c b/board/blackvme/blackvme.c
new file mode 100644
index 00000000000..eccdaf3a487
--- /dev/null
+++ b/board/blackvme/blackvme.c
@@ -0,0 +1,31 @@
+/* U-boot - blackvme.c  board specific routines
+ * (c) Wojtek Skulski 2010 info@skutek.com
+ * Board info: http://www.skutek.com
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+int checkboard(void)
+{
+	printf("Board: BlackVME\n");
+	printf("Support: http://www.skutek.com/\n");
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_AX88180
+/*
+ * The ax88180 driver had to be patched to work around a bug
+ * in Marvell 88E1111 B2 silicon. E-mail me for explanations.
+ */
+int board_eth_init(bd_t *bis)
+{
+	return ax88180_initialize(bis);
+}
+#endif	/* CONFIG_DRIVER_AX88180 */
diff --git a/board/blackvme/config.mk b/board/blackvme/config.mk
new file mode 100644
index 00000000000..8d0fe3934dd
--- /dev/null
+++ b/board/blackvme/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf561-0.5
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/boards.cfg b/boards.cfg
index 86838f21bb0..d1a0ac21e86 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -296,6 +296,7 @@ bf548-ezkit	blackfin	blackfin
 bf561-acvilon	blackfin	blackfin
 bf561-ezkit	blackfin	blackfin
 blackstamp	blackfin	blackfin
+blackvme	blackfin	blackfin
 cm-bf527	blackfin	blackfin
 cm-bf533	blackfin	blackfin
 cm-bf537e	blackfin	blackfin
diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h
new file mode 100644
index 00000000000..8b2bdc715d6
--- /dev/null
+++ b/include/configs/blackvme.h
@@ -0,0 +1,246 @@
+/* U-boot for BlackVME. (C) Wojtek Skulski 2010.
+ * The board includes ADSP-BF561 rev. 0.5,
+ * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG),
+ * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell),
+ * SPI  boot flash on PF2 (M25P64 8MB, or M25P128 16 MB),
+ * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB),
+ * Spartan6-LX150 (memory-mapped; both PPIs also connected).
+ * See http://www.skutek.com
+ */
+
+#ifndef __CONFIG_BLACKVME_H__
+#define __CONFIG_BLACKVME_H__
+
+#include <asm/config-pre.h>
+
+/* Debugging: Set these options if you're having problems
+ * #define CONFIG_DEBUG_EARLY_SERIAL
+ * #define DEBUG
+ * #define CONFIG_DEBUG_DUMP
+ * #define CONFIG_DEBUG_DUMP_SYMS
+ * CONFIG_PANIC_HANG means that the board will not auto-reboot
+ */
+#define CONFIG_PANIC_HANG 0
+
+/* CPU Options */
+#define CONFIG_BFIN_BOOT_MODE	BFIN_BOOT_SPI_MASTER
+
+/*
+ *		CLOCK SETTINGS CAVEAT
+ * You CANNOT just change the clock settings, esp. the SCLK.
+ * The SDRAM timing, SPI baud, and the serial UART baud
+ * use SCLK frequency to set their own frequencies. Therefore,
+ * if you change the SCLK_DIV, you may also have to adjust
+ * SDRAM refresh and other timings.
+ * --------------------------------------------------------------
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *		25 *  8 / 1 = 200 MHz
+ *		25 * 16 / 1 = 400 MHz
+ *		25 * 24 / 1 = 600 MHz
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ *		25 *  8 / 2 = 100 MHz
+ *		25 * 24 / 6 = 100 MHz
+ *		25 * 24 / 5 = 120 MHz
+ *		25 * 16 / 3 = 133 MHz
+ * 25 MHz because the oscillator also feeds the ether chip.
+ * CONFIG_CLKIN_HZ is 25 MHz written in Hz
+ * CLKIN_HALF controls the DF bit in PLL_CTL
+ *	0 = CLKIN	1 = CLKIN / 2
+ * PLL_BYPASS controls the BYPASS bit in PLL_CTL
+ *	0 = do not bypass	1 = bypass PLL
+ * VCO_MULT = MSEL (multiplier) in PLL_CTL
+ * Values can range from 0-63 (where 0 means 64)
+ * CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY)
+ * SCLK_DIV = system clock divider, 1 to 15
+ */
+#define CONFIG_CLKIN_HZ		25000000
+#define CONFIG_CLKIN_HALF	0
+#define CONFIG_PLL_BYPASS	0
+#define CONFIG_VCO_MULT		8
+#define CONFIG_CCLK_DIV		1
+#define CONFIG_SCLK_DIV		2
+
+/*
+ * Ether chip in async memory space AMS3, same as BF561-EZ-KIT.
+ * Used in 32-bit mode. 16-bit mode not supported.
+ * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
+ */
+/*
+ * Network settings using a dedicated 2nd ether card in PC
+ * Windows will automatically acquire IP of that card
+ * Then use the dedicated card IP + 1 for the board
+ * http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network
+ */
+#define CONFIG_NET_MULTI
+
+#define CONFIG_DRIVER_AX88180	1
+#define AX88180_BASE		0x2c000000
+#define CONFIG_CMD_MII		/* enable probing PHY */
+
+#ifdef CONFIG_NET_MULTI		/* also used as the network enabler */
+# define CONFIG_HOSTNAME	blackvme	/* Bfin board  */
+# define CONFIG_IPADDR		169.254.144.145	/* Bfin board  */
+# define CONFIG_GATEWAYIP	169.254.144.144	/* dedic card  */
+# define CONFIG_SERVERIP	169.254.144.144	/* tftp server */
+# define CONFIG_NETMASK		255.255.255.0
+# define CONFIG_ROOTPATH	/export/uClinux-dist/romfs	/*NFS*/
+# define CFG_AUTOLOAD		"no"
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+# define CONFIG_ENV_OVERWRITE	1	/* enable changing MAC at runtime */
+/* Comment out hardcoded MAC to enable MAC storage in EEPROM */
+/* # define CONFIG_ETHADDR	ff:ee:dd:cc:bb:aa */
+#endif
+
+/*
+ * SDRAM settings & memory map
+ */
+
+#define CONFIG_MEM_SIZE		64	/* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH	 9	/* 8, 9, 10, 11    */
+/*
+ * SDRAM reference page
+ * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
+ * NOTE: BlackVME populates only SDRAM bank 0
+ */
+/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */
+#define CONFIG_EBIU_SDGCTL_VAL  0x91114d  /* global control */
+#define CONFIG_EBIU_SDRRC_VAL   0x306     /* refresh rate */
+
+/* Async memory global settings. (ASRAM, not SDRAM)
+ * HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1
+ * CLKOUT enabled, all async banks enabled, core has priority
+ * bank 0&1 16 bit (FPGA)
+ * bank 2&3 32 bit (ether and USB chips)
+ */
+#define CONFIG_EBIU_AMGCTL_VAL  0x3F   /* ASRAM setup */
+
+/* Async mem timing: BF561 HRM page 16-12 and 16-15.
+ * Default values 0xFFC2 FFC2 are the slowest supported.
+ * Example settings of CONFIG_EBIU_AMBCTL1_VAL
+ * 1. EZ-KIT settings: 0xFFC2 7BB0
+ * 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx
+ *    See the following page:
+ *    http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
+ * 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz:
+ * AX88180  WEN = 5 clocks  REN 6 clocks @ SCLK = 100 MHz
+ * One extra clock needed because AX88180 is asynchronous to CPU.
+ */
+                           /* bank 1   0 */
+#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2
+                           /* bank 3   2 */
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2
+
+/* memory layout */
+
+#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
+#define CONFIG_SYS_MALLOC_LEN	(384 << 10)
+
+/*
+ * Serial SPI Flash
+ * For the M25P64 SCK should be kept < 15 MHz
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x40000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x40000
+
+#define CONFIG_ENV_SPI_MAX_HZ	15000000
+#define CONFIG_SF_DEFAULT_SPEED	15000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+/*
+ * Interactive command settings
+ */
+
+#define CONFIG_SYS_LONGHELP	1
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_AUTO_COMPLETE	1
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTLDR
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CPLBINFO
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_ELF
+
+/*
+ * Default: boot from SPI flash.
+ * "sfboot" is a composite command defined in extra settings
+ */
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOTCOMMAND	"run sfboot"
+
+/*
+ * Console settings
+ */
+#define CONFIG_BAUDRATE		57600
+#define CONFIG_LOADS_ECHO	1
+#define CONFIG_UART_CONSOLE	0
+
+/*
+ * U-Boot environment variables. Use "printenv" to examine.
+ * http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env
+ */
+#define CONFIG_BOOTARGS \
+	"root=/dev/mtdblock0 rw " \
+	"clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
+	"earlyprintk=serial,uart0," \
+	MK_STR(CONFIG_BAUDRATE) " " \
+	"console=ttyBF0," MK_STR(CONFIG_BAUDRATE) " "
+
+/* Convenience env variables & commands.
+ * Reserve kernstart = 0x20000  = 128 kB for U-Boot.
+ * Reserve kernarea  = 0x500000 = 5 MB   for kernel (reasonable size).
+ * U-Boot image is saved at flash offset=0.
+ * Kernel image is saved at flash offset=$kernstart.
+ * Instructions. Ksave takes about a minute to complete.
+ *	1. Update U-Boot: run uget; run usave
+ *	2. Update kernel: run kget; run ksave
+ * After updating U-Boot also update the kernel per above instructions
+ * to make the saved environment consistent with the flash.
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernstart=0x20000\0" \
+	"kernarea=0x500000\0" \
+	"uget=tftp u-boot.ldr\0" \
+	"kget=tftp uImage\0" \
+	"usave=sf probe 2; " \
+		"sf erase 0 $(kernstart); " \
+		"sf write $(fileaddr) 0 $(filesize)\0" \
+	"ksave=sf probe 2; " \
+		"saveenv; " \
+		"echo Now patiently wait for the prompt...; " \
+		"sf erase $(kernstart) $(kernarea); " \
+		"sf write $(fileaddr) $(kernstart) $(filesize)\0" \
+	"sfboot=sf probe 2; " \
+		"sf read $(loadaddr) $(kernstart) $(filesize); " \
+		"run addip; bootm\0" \
+	"addip=setenv bootargs $(bootargs) " \
+	"ip=$(ipaddr):$(serverip):$(gatewayip):" \
+		"$(netmask):$(hostname):eth0:off\0"
+
+/*
+ * Soft I2C settings (BF561 does not have hard I2C)
+ * PF12,13 on SPI connector 0.
+ */
+#ifdef CONFIG_SOFT_I2C
+# define CONFIG_CMD_I2C
+# define CONFIG_SOFT_I2C_GPIO_SCL	GPIO_PF12
+# define CONFIG_SOFT_I2C_GPIO_SDA	GPIO_PF13
+# define CONFIG_SYS_I2C_SPEED		50000
+# define CONFIG_SYS_I2C_SLAVE		0xFE
+#endif
+
+/*
+ * No Parallel Flash on this board
+ */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_FLASH
+
+#endif
-- 
cgit v1.3.1


From abaa5ba4e3b52f82b8158044cba6cf7986309d43 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Wed, 29 Sep 2010 20:24:16 +0000
Subject: Blackfin: bf548-ezkit: bump SPI flash size up

The current size used (256KiB) is smaller than the LDR created for
the bf548-ezkit, so 'run update' doesn't work correctly.  So bump
up the size a bit by making this flexible per-board config.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bf548-ezkit.h     | 1 +
 include/configs/bfin_adi_common.h | 5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index d299dc18f5f..4412177ff09 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -182,6 +182,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
+#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
 
 #ifndef __ADSPBF542__
 /* Don't waste time transferring a logo over the UART */
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 3e9f3b2c90d..608788a66f9 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -172,9 +172,12 @@
 #   define UBOOT_ENV_UPDATE \
 		"eeprom write $(loadaddr) 0x0 $(filesize)"
 #  else
+#   ifndef CONFIG_BFIN_SPI_IMG_SIZE
+#    define CONFIG_BFIN_SPI_IMG_SIZE 0x40000
+#   endif
 #   define UBOOT_ENV_UPDATE \
 		"sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
-		"sf erase 0 0x40000;" \
+		"sf erase 0 " MK_STR(CONFIG_BFIN_SPI_IMG_SIZE) ";" \
 		"sf write $(loadaddr) 0 $(filesize)"
 #  endif
 # elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-- 
cgit v1.3.1


From 504af55edff2bcf98fc3578d79d7a2df0b5cb128 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Fri, 1 Oct 2010 16:59:19 -0400
Subject: Blackfin: bf527-ad7160-eval: fix GPIO CS define

Rather than use a hardcoded "7", use the new Blackfin global define.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bf527-ad7160-eval.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h
index fbcf019051c..14ade1b1e64 100644
--- a/include/configs/bf527-ad7160-eval.h
+++ b/include/configs/bf527-ad7160-eval.h
@@ -129,7 +129,7 @@
 #define CONFIG_MMC
 #define CONFIG_CMD_EXT2
 #define CONFIG_SPI_MMC
-#define CONFIG_SPI_MMC_DEFAULT_CS (7 + GPIO_PH3)
+#define CONFIG_SPI_MMC_DEFAULT_CS (MAX_CTRL_CS + GPIO_PH3)
 
 
 /*
-- 
cgit v1.3.1


From 4c95ff64199c79bf2662c49e2d1efffbf6546993 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Fri, 1 Oct 2010 19:42:08 -0400
Subject: Blackfin: bf537-pnav: increase monitor len

Building this board for parallel flash fills up the bss section and thus
fails to link, so bump up the monitor size a bit.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bf537-pnav.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
index 30607d91fd1..730ae279b6c 100644
--- a/include/configs/bf537-pnav.h
+++ b/include/configs/bf537-pnav.h
@@ -51,7 +51,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL	0x7BB033B0
 #define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
 
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
 
 
-- 
cgit v1.3.1