From d92ea983b9dfc99063373c167dae6b7705bc552b Mon Sep 17 00:00:00 2001 From: Stanislav Galabov Date: Wed, 17 Feb 2016 15:23:29 +0200 Subject: Properly calculate ATA_SECTORWORDS, using a fixed-size integer, so it works for both 32-bit and 64-bit targets Signed-off-by: Stanislav Galabov --- include/ata.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/ata.h b/include/ata.h index 9d6f59c97bf..dde377c99ec 100644 --- a/include/ata.h +++ b/include/ata.h @@ -126,7 +126,7 @@ #define ATA_BLOCKSIZE 512 /* bytes */ #define ATA_BLOCKSHIFT 9 /* 2 ^ ATA_BLOCKSIZESHIFT = 512 */ -#define ATA_SECTORWORDS (512 / sizeof(unsigned long)) +#define ATA_SECTORWORDS (512 / sizeof(uint32_t)) #ifndef ATA_RESET_TIME #define ATA_RESET_TIME 60 /* spec allows up to 31 seconds */ -- cgit v1.3.1 From 713a9e15bba4a5b6582d5e85fef2f282782cbed7 Mon Sep 17 00:00:00 2001 From: Stanislav Galabov Date: Wed, 17 Feb 2016 15:23:30 +0200 Subject: Use CONFIG_IDE_SWAP_IO when running on big-endian MIPS (32 or 64-bit) in QEMU so that IDE transfers work properly Signed-off-by: Stanislav Galabov --- include/configs/qemu-mips.h | 4 ++++ include/configs/qemu-mips64.h | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index a7cd00350d4..702967c4e8e 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -58,6 +58,10 @@ #define CONFIG_CMD_IDE #define CONFIG_DOS_PARTITION +#ifdef CONFIG_SYS_BIG_ENDIAN +#define CONFIG_IDE_SWAP_IO +#endif + #define CONFIG_SYS_IDE_MAXBUS 2 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index 394382c4587..239454984ae 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -58,6 +58,10 @@ #define CONFIG_CMD_IDE #define CONFIG_DOS_PARTITION +#ifdef CONFIG_SYS_BIG_ENDIAN +#define CONFIG_IDE_SWAP_IO +#endif + #define CONFIG_SYS_IDE_MAXBUS 2 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 -- cgit v1.3.1 From 6a7b52bc8d30090633d098f9e988276beb7a53d5 Mon Sep 17 00:00:00 2001 From: Wills Wang Date: Wed, 16 Mar 2016 16:59:59 +0800 Subject: mips: ath79: add AP121 reference board This patch add board-level code and base DT for AP121. Signed-off-by: Wills Wang [updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y] Signed-off-by: Daniel Schwierzeck --- arch/mips/dts/Makefile | 1 + arch/mips/dts/ap121.dts | 43 ++++++++++++++++++++++ arch/mips/dts/ar933x.dtsi | 82 ++++++++++++++++++++++++++++++++++++++++++ arch/mips/mach-ath79/Kconfig | 11 ++++++ board/qca/ap121/Kconfig | 12 +++++++ board/qca/ap121/MAINTAINERS | 6 ++++ board/qca/ap121/Makefile | 5 +++ board/qca/ap121/ap121.c | 50 ++++++++++++++++++++++++++ configs/ap121_defconfig | 47 ++++++++++++++++++++++++ include/configs/ap121.h | 86 ++++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 343 insertions(+) create mode 100644 arch/mips/dts/ap121.dts create mode 100644 arch/mips/dts/ar933x.dtsi create mode 100644 board/qca/ap121/Kconfig create mode 100644 board/qca/ap121/MAINTAINERS create mode 100644 board/qca/ap121/Makefile create mode 100644 board/qca/ap121/ap121.c create mode 100644 configs/ap121_defconfig create mode 100644 include/configs/ap121.h (limited to 'include') diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index b5139187c20..30e5c6871ac 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -2,6 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +dtb-$(CONFIG_TARGET_AP121) += ap121.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts new file mode 100644 index 00000000000..e31f601d039 --- /dev/null +++ b/arch/mips/dts/ap121.dts @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2015-2016 Wills Wang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ar933x.dtsi" + +/ { + model = "AP121 Reference Board"; + compatible = "qca,ap121", "qca,ar933x"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&xtal { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + spi-max-frequency = <25000000>; + status = "okay"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + memory-map = <0x9f000000 0x00800000>; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi new file mode 100644 index 00000000000..11f60a2864f --- /dev/null +++ b/arch/mips/dts/ar933x.dtsi @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2015-2016 Wills Wang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "skeleton.dtsi" + +/ { + compatible = "qca,ar933x"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips24Kc"; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xtal"; + }; + }; + + pinctrl { + u-boot,dm-pre-reloc; + compatible = "qca,ar933x-pinctrl"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x18040000 0x100>; + }; + + ahb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + apb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@18020000 { + compatible = "qca,ar9330-uart"; + reg = <0x18020000 0x20>; + interrupts = <128 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + }; + + spi0: spi@1f000000 { + compatible = "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + interrupts = <129 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index e35f1b578fe..c3012f8b530 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -22,4 +22,15 @@ config SOC_QCA953X help This supports QCA/Atheros qca953x family SOCs. +choice + prompt "Board select" + +config TARGET_AP121 + bool "AP121 Reference Board" + select SOC_AR933X + +endchoice + +source "board/qca/ap121/Kconfig" + endmenu diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig new file mode 100644 index 00000000000..f7e768ad586 --- /dev/null +++ b/board/qca/ap121/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AP121 + +config SYS_VENDOR + default "qca" + +config SYS_BOARD + default "ap121" + +config SYS_CONFIG_NAME + default "ap121" + +endif diff --git a/board/qca/ap121/MAINTAINERS b/board/qca/ap121/MAINTAINERS new file mode 100644 index 00000000000..8b02988d605 --- /dev/null +++ b/board/qca/ap121/MAINTAINERS @@ -0,0 +1,6 @@ +AP121 BOARD +M: Wills Wang +S: Maintained +F: board/qca/ap121/ +F: include/configs/ap121.h +F: configs/ap121_defconfig diff --git a/board/qca/ap121/Makefile b/board/qca/ap121/Makefile new file mode 100644 index 00000000000..ced5432e86f --- /dev/null +++ b/board/qca/ap121/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = ap121.o diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c new file mode 100644 index 00000000000..d6c60fea86d --- /dev/null +++ b/board/qca/ap121/ap121.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2015-2016 Wills Wang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + void __iomem *regs; + u32 val; + + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, + MAP_NOCACHE); + + /* + * GPIO9 as input, GPIO10 as output + */ + val = readl(regs + AR71XX_GPIO_REG_OE); + val &= ~AR933X_GPIO(9); + val |= AR933X_GPIO(10); + writel(val, regs + AR71XX_GPIO_REG_OE); + + /* + * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO + */ + val = readl(regs + AR71XX_GPIO_REG_FUNC); + val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE; + writel(val, regs + AR71XX_GPIO_REG_FUNC); +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + ddr_init(); + return 0; +} diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig new file mode 100644 index 00000000000..7604e2ee16f --- /dev/null +++ b/configs/ap121_defconfig @@ -0,0 +1,47 @@ +CONFIG_MIPS=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ARCH_ATH79=y +CONFIG_DEFAULT_DEVICE_TREE="ap121" +CONFIG_SYS_PROMPT="ap121 # " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_AR933X_PINCTRL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_AR933X=y +CONFIG_DEBUG_UART_BASE=0xb8020000 +CONFIG_DEBUG_UART_CLOCK=25000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_AR933X_UART=y +CONFIG_ATH79_SPI=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/ap121.h b/include/configs/ap121.h new file mode 100644 index 00000000000..2beffa4805b --- /dev/null +++ b/include/configs/ap121.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2015-2016 Wills Wang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_TEXT_BASE 0x9f000000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 200 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 0x8000 +#define CONFIG_SYS_ICACHE_SIZE 0x10000 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x40000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x81000000 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {9600, 19200, 38400, 57600, 115200} + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock2 " \ + "rootfstype=squashfs" +#define CONFIG_BOOTCOMMAND "sf probe;" \ + "mtdparts default;" \ + "bootm 0x9f300000" +#define CONFIG_LZMA + +#define MTDIDS_DEFAULT "nor0=spi-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \ + "256k(u-boot),64k(u-boot-env)," \ + "2752k(rootfs),896k(uImage)," \ + "64k(NVRAM),64k(ART)" + +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x10000 + +/* + * Command + */ +#define CONFIG_CMD_MTDPARTS + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* + * Diagnostics + */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x83f00000 +#define CONFIG_CMD_MEMTEST + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From a2277cc30cdb40298aca80344f3764db6a0cfb8d Mon Sep 17 00:00:00 2001 From: Wills Wang Date: Wed, 16 Mar 2016 17:00:00 +0800 Subject: mips: ath79: add AP143 reference board This patch add board-level code and base DT for AP143. Signed-off-by: Wills Wang [updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y] Signed-off-by: Daniel Schwierzeck --- arch/mips/dts/Makefile | 1 + arch/mips/dts/ap143.dts | 43 +++++++++++++++++++++ arch/mips/dts/qca953x.dtsi | 84 +++++++++++++++++++++++++++++++++++++++++ arch/mips/mach-ath79/Kconfig | 5 +++ board/qca/ap143/Kconfig | 12 ++++++ board/qca/ap143/MAINTAINERS | 6 +++ board/qca/ap143/Makefile | 5 +++ board/qca/ap143/ap143.c | 66 ++++++++++++++++++++++++++++++++ configs/ap143_defconfig | 47 +++++++++++++++++++++++ include/configs/ap143.h | 90 ++++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 359 insertions(+) create mode 100644 arch/mips/dts/ap143.dts create mode 100644 arch/mips/dts/qca953x.dtsi create mode 100644 board/qca/ap143/Kconfig create mode 100644 board/qca/ap143/MAINTAINERS create mode 100644 board/qca/ap143/Makefile create mode 100644 board/qca/ap143/ap143.c create mode 100644 configs/ap143_defconfig create mode 100644 include/configs/ap143.h (limited to 'include') diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 30e5c6871ac..bd87ead9723 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -3,6 +3,7 @@ # dtb-$(CONFIG_TARGET_AP121) += ap121.dtb +dtb-$(CONFIG_TARGET_AP143) += ap143.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/ap143.dts b/arch/mips/dts/ap143.dts new file mode 100644 index 00000000000..f53207e7710 --- /dev/null +++ b/arch/mips/dts/ap143.dts @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2015-2016 Wills Wang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "qca953x.dtsi" + +/ { + model = "AP143 Reference Board"; + compatible = "qca,ap143", "qca,qca953x"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&xtal { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + spi-max-frequency = <25000000>; + status = "okay"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + memory-map = <0x9f000000 0x00800000>; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/dts/qca953x.dtsi b/arch/mips/dts/qca953x.dtsi new file mode 100644 index 00000000000..870010f0e40 --- /dev/null +++ b/arch/mips/dts/qca953x.dtsi @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2015-2016 Wills Wang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "skeleton.dtsi" + +/ { + compatible = "qca,qca953x"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips24Kc"; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xtal"; + }; + }; + + pinctrl { + u-boot,dm-pre-reloc; + compatible = "qca,qca953x-pinctrl"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x18040000 0x100>; + }; + + ahb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + apb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@18020000 { + compatible = "ns16550"; + reg = <0x18020000 0x20>; + reg-shift = <2>; + clock-frequency = <25000000>; + interrupts = <128 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + }; + + spi0: spi@1f000000 { + compatible = "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + interrupts = <129 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index c3012f8b530..f45403bda94 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -29,8 +29,13 @@ config TARGET_AP121 bool "AP121 Reference Board" select SOC_AR933X +config TARGET_AP143 + bool "AP143 Reference Board" + select SOC_QCA953X + endchoice source "board/qca/ap121/Kconfig" +source "board/qca/ap143/Kconfig" endmenu diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig new file mode 100644 index 00000000000..4cdac0d06d0 --- /dev/null +++ b/board/qca/ap143/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AP143 + +config SYS_VENDOR + default "qca" + +config SYS_BOARD + default "ap143" + +config SYS_CONFIG_NAME + default "ap143" + +endif diff --git a/board/qca/ap143/MAINTAINERS b/board/qca/ap143/MAINTAINERS new file mode 100644 index 00000000000..11cb14fc74d --- /dev/null +++ b/board/qca/ap143/MAINTAINERS @@ -0,0 +1,6 @@ +AP143 BOARD +M: Wills Wang +S: Maintained +F: board/qca/ap143/ +F: include/configs/ap143.h +F: configs/ap143_defconfig diff --git a/board/qca/ap143/Makefile b/board/qca/ap143/Makefile new file mode 100644 index 00000000000..00f78376ec5 --- /dev/null +++ b/board/qca/ap143/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = ap143.o diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c new file mode 100644 index 00000000000..1572472ca30 --- /dev/null +++ b/board/qca/ap143/ap143.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2015-2016 Wills Wang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + void __iomem *regs; + u32 val; + + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, + MAP_NOCACHE); + + /* + * GPIO9 as input, GPIO10 as output + */ + val = readl(regs + AR71XX_GPIO_REG_OE); + val |= QCA953X_GPIO(9); + val &= ~QCA953X_GPIO(10); + writel(val, regs + AR71XX_GPIO_REG_OE); + + /* + * Enable GPIO10 as UART0_SOUT + */ + val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2); + val &= ~QCA953X_GPIO_MUX_MASK(16); + val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16; + writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2); + + /* + * Enable GPIO9 as UART0_SIN + */ + val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0); + val &= ~QCA953X_GPIO_MUX_MASK(8); + val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8; + writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0); + + /* + * Enable GPIO10 output + */ + val = readl(regs + AR71XX_GPIO_REG_OUT); + val |= QCA953X_GPIO(10); + writel(val, regs + AR71XX_GPIO_REG_OUT); +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + ddr_init(); + return 0; +} diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig new file mode 100644 index 00000000000..1aa6e5d7abd --- /dev/null +++ b/configs/ap143_defconfig @@ -0,0 +1,47 @@ +CONFIG_MIPS=y +CONFIG_SYS_MALLOC_F_LEN=0x800 +CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ARCH_ATH79=y +CONFIG_TARGET_AP143=y +CONFIG_DEFAULT_DEVICE_TREE="ap143" +CONFIG_SYS_PROMPT="ap143 # " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PINCTRL=y +CONFIG_QCA953X_PINCTRL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xb8020000 +CONFIG_DEBUG_UART_CLOCK=25000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_SYS_NS16550=y +CONFIG_ATH79_SPI=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/ap143.h b/include/configs/ap143.h new file mode 100644 index 00000000000..7b69e10be44 --- /dev/null +++ b/include/configs/ap143.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2015-2016 Wills Wang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_TEXT_BASE 0x9f000000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 325 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 0x8000 +#define CONFIG_SYS_ICACHE_SIZE 0x10000 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x40000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x81000000 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_CLK 25000000 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {9600, 19200, 38400, 57600, 115200} + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock2 " \ + "rootfstype=squashfs" +#define CONFIG_BOOTCOMMAND "sf probe;" \ + "mtdparts default;" \ + "bootm 0x9f300000" +#define CONFIG_LZMA + +#define MTDIDS_DEFAULT "nor0=spi-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \ + "256k(u-boot),64k(u-boot-env)," \ + "2752k(rootfs),896k(uImage)," \ + "64k(NVRAM),64k(ART)" + +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x10000 + +/* + * Command + */ +#define CONFIG_CMD_MTDPARTS + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* + * Diagnostics + */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x83f00000 +#define CONFIG_CMD_MEMTEST + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 30fd42cba6e7d4147e2dd4e9dbe9728efbcd24fe Mon Sep 17 00:00:00 2001 From: Purna Chandra Mandal Date: Fri, 18 Mar 2016 18:36:07 +0530 Subject: flash: add device ID for Microchip PIC32 internal flash. Microchip PIC32 has internal parallel flash (non-CFI compliant). These flash devices do not support any identifier command so no standard IDs. Added unique IDs to seperate these flash devices from others supported by U-Boot. Signed-off-by: Purna Chandra Mandal --- include/flash.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/flash.h b/include/flash.h index c6321a02ef8..2a5e13a13d3 100644 --- a/include/flash.h +++ b/include/flash.h @@ -400,6 +400,9 @@ extern flash_info_t *flash_get_info(ulong base); #define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */ #define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/ +#define FLASH_MCHP100T 0x0060 /* MCHP internal (1M = 64K x 16) */ +#define FLASH_MCHP100B 0x0061 /* MCHP internal (1M = 64K x 16) */ + #define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ #define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ @@ -486,7 +489,7 @@ extern flash_info_t *flash_get_info(ulong base); #define FLASH_MAN_SHARP 0x00500000 #define FLASH_MAN_ATM 0x00600000 #define FLASH_MAN_CFI 0x01000000 - +#define FLASH_MAN_MCHP 0x02000000 /* Microchip Technology */ #define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */ #define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */ -- cgit v1.3.1 From 400df3099896bdd43dd72dbb5d3930cf573d14f0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 6 May 2016 20:10:41 +0200 Subject: mips: ath79: Add support for TPLink WDR4300 Add support for the TPLink WDR4300 router, which is based on the AR9344 MIPS 74Kc CPU and has 128 MiB of RAM. The USB is supported on this system as well. Signed-off-by: Marek Vasut Cc: Daniel Schwierzeck Cc: Wills Wang --- arch/mips/dts/Makefile | 1 + arch/mips/dts/tplink_wdr4300.dts | 53 +++++++++++++++++++++++ arch/mips/mach-ath79/Kconfig | 5 +++ board/tplink/wdr4300/Kconfig | 15 +++++++ board/tplink/wdr4300/MAINTAINERS | 6 +++ board/tplink/wdr4300/Makefile | 5 +++ board/tplink/wdr4300/wdr4300.c | 74 ++++++++++++++++++++++++++++++++ configs/tplink_wdr4300_defconfig | 43 +++++++++++++++++++ include/configs/tplink_wdr4300.h | 93 ++++++++++++++++++++++++++++++++++++++++ 9 files changed, 295 insertions(+) create mode 100644 arch/mips/dts/tplink_wdr4300.dts create mode 100644 board/tplink/wdr4300/Kconfig create mode 100644 board/tplink/wdr4300/MAINTAINERS create mode 100644 board/tplink/wdr4300/Makefile create mode 100644 board/tplink/wdr4300/wdr4300.c create mode 100644 configs/tplink_wdr4300_defconfig create mode 100644 include/configs/tplink_wdr4300.h (limited to 'include') diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index bd87ead9723..a94b7455507 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -5,6 +5,7 @@ dtb-$(CONFIG_TARGET_AP121) += ap121.dtb dtb-$(CONFIG_TARGET_AP143) += ap143.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb +dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/tplink_wdr4300.dts b/arch/mips/dts/tplink_wdr4300.dts new file mode 100644 index 00000000000..cfda4df72b7 --- /dev/null +++ b/arch/mips/dts/tplink_wdr4300.dts @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2016 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ar934x.dtsi" + +/ { + model = "TP-Link WDR4300 Board"; + compatible = "tplink,wdr4300", "qca,ar934x"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii"; + status = "okay"; +}; + +&spi0 { + spi-max-frequency = <25000000>; + status = "okay"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + memory-map = <0x1e000000 0x00800000>; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; + +&uart0 { + clock-frequency = <40000000>; + status = "okay"; +}; + +&xtal { + clock-frequency = <40000000>; +}; diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index 527960f4eb7..7d483aa8dce 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -42,9 +42,14 @@ config TARGET_AP143 bool "AP143 Reference Board" select SOC_QCA953X +config BOARD_TPLINK_WDR4300 + bool "TP-Link WDR4300 Board" + select SOC_AR934X + endchoice source "board/qca/ap121/Kconfig" source "board/qca/ap143/Kconfig" +source "board/tplink/wdr4300/Kconfig" endmenu diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig new file mode 100644 index 00000000000..902abf560d1 --- /dev/null +++ b/board/tplink/wdr4300/Kconfig @@ -0,0 +1,15 @@ +if BOARD_TPLINK_WDR4300 + +config SYS_VENDOR + default "tplink" + +config SYS_SOC + default "ath79" + +config SYS_BOARD + default "wdr4300" + +config SYS_CONFIG_NAME + default "tplink_wdr4300" + +endif diff --git a/board/tplink/wdr4300/MAINTAINERS b/board/tplink/wdr4300/MAINTAINERS new file mode 100644 index 00000000000..db239c291a7 --- /dev/null +++ b/board/tplink/wdr4300/MAINTAINERS @@ -0,0 +1,6 @@ +TPLINK_WDR4300 BOARD +M: Marek Vasut +S: Maintained +F: board/tplink/wdr4300/ +F: include/configs/tplink_wdr4300.h +F: configs/tplink_wdr4300_defconfig diff --git a/board/tplink/wdr4300/Makefile b/board/tplink/wdr4300/Makefile new file mode 100644 index 00000000000..4f0c2966287 --- /dev/null +++ b/board/tplink/wdr4300/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = wdr4300.o diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c new file mode 100644 index 00000000000..6e070fd5580 --- /dev/null +++ b/board/tplink/wdr4300/wdr4300.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2016 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_USB +static void wdr4300_usb_start(void) +{ + void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE, + AR71XX_GPIO_SIZE, MAP_NOCACHE); + if (!gpio_regs) + return; + + /* Power up the USB HUB. */ + clrbits_be32(gpio_regs + AR71XX_GPIO_REG_OE, BIT(21) | BIT(22)); + writel(BIT(21) | BIT(22), gpio_regs + AR71XX_GPIO_REG_SET); + mdelay(1); + + ath79_usb_reset(); +} +#else +static inline void wdr4300_usb_start(void) {} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + void __iomem *regs; + + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, + MAP_NOCACHE); + + /* Assure JTAG is not disconnected. */ + writel(0x40, regs + AR934X_GPIO_REG_FUNC); + + /* Configure default GPIO input/output regs. */ + writel(0x3031b, regs + AR71XX_GPIO_REG_OE); + writel(0x0f804, regs + AR71XX_GPIO_REG_OUT); + + /* Configure pin multiplexing. */ + writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC0); + writel(0x0b0a0980, regs + AR934X_GPIO_REG_OUT_FUNC1); + writel(0x00180000, regs + AR934X_GPIO_REG_OUT_FUNC2); + writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC3); + writel(0x0000004d, regs + AR934X_GPIO_REG_OUT_FUNC4); + writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC5); + +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + ar934x_pll_init(560, 480, 240); + ar934x_ddr_init(560, 480, 240); +#endif + + wdr4300_usb_start(); + ath79_eth_reset(); + + return 0; +} +#endif diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig new file mode 100644 index 00000000000..b1af2f6f35f --- /dev/null +++ b/configs/tplink_wdr4300_defconfig @@ -0,0 +1,43 @@ +CONFIG_MIPS=y +CONFIG_ARCH_ATH79=y +CONFIG_BOARD_TPLINK_WDR4300=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_NS16550=y +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300" +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_NET=y +CONFIG_CMD_NFS=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_ETH=y +CONFIG_AG7XXX=y +CONFIG_CLK=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_ATH79_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PINCTRL=y diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h new file mode 100644 index 00000000000..2b9e92ed2b1 --- /dev/null +++ b/include/configs/tplink_wdr4300.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2016 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_TEXT_BASE 0xa1000000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 280 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 0x8000 +#define CONFIG_SYS_ICACHE_SIZE 0x10000 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x40000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0xa0000000 +#define CONFIG_SYS_LOAD_ADDR 0xa1000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_CLK 40000000 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {9600, 19200, 38400, 57600, 115200} + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" +#define CONFIG_BOOTCOMMAND \ + "dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr" +#define CONFIG_LZMA + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x10000 + +/* + * Command + */ +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* USB, USB storage, USB ethernet */ +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_IS_TDI + +#define CONFIG_DOS_PARTITION + +/* + * Diagnostics + */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x83f00000 +#define CONFIG_CMD_MEMTEST + +#define CONFIG_USE_PRIVATE_LIBGCC + +#define CONFIG_CMD_MII +#define CONFIG_PHY_GIGE + +#endif /* __CONFIG_H */ -- cgit v1.3.1