From 405d8205d76b57184e24eae573c7dd61474b56e0 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:41 +0800 Subject: x86: Add crownbay defconfig and config.h Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/configs/crownbay.h | 52 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 include/configs/crownbay.h (limited to 'include') diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h new file mode 100644 index 00000000000..2314e62a876 --- /dev/null +++ b/include/configs/crownbay.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_SYS_X86_START16 0xfffff800 +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_X86_RESET_VECTOR +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_COREBOOT_SERIAL +#define CONFIG_SMSC_LPC47M + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x80000000 + +#define CONFIG_PCI_PREF_BUS 0xc0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x20000000 + +#define CONFIG_PCI_IO_BUS 0x2000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xe000 + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA} + +/* Video is not supported */ +#undef CONFIG_VIDEO +#undef CONFIG_CFB_CONSOLE + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 8c5224c9f5c8a24ff5153f018e10a3ac4da5783a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:42 +0800 Subject: x86: Use consistent name XXX_ADDR for binary blob flash address Signed-off-by: Bin Meng Acked-by: Simon Glass --- Makefile | 2 +- arch/x86/cpu/ivybridge/sdram.c | 2 +- arch/x86/cpu/queensbay/Kconfig | 4 ++-- arch/x86/cpu/queensbay/fsp_support.c | 2 +- arch/x86/cpu/queensbay/tnc_car.S | 2 +- include/configs/chromebook_link.h | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/Makefile b/Makefile index bda8222af43..d962576c34f 100644 --- a/Makefile +++ b/Makefile @@ -958,7 +958,7 @@ IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin endif ifneq ($(CONFIG_HAVE_MRC),) -IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin +IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin endif ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),) diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index df2b9901fc0..b95e781bbfb 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -177,7 +177,7 @@ int sdram_initialise(struct pei_data *pei_data) debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data)); - data = (char *)CONFIG_X86_MRC_START; + data = (char *)CONFIG_X86_MRC_ADDR; if (data) { int rv; int (*func)(struct pei_data *); diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig index 56fe85ccad0..f6b52010c37 100644 --- a/arch/x86/cpu/queensbay/Kconfig +++ b/arch/x86/cpu/queensbay/Kconfig @@ -29,7 +29,7 @@ config FSP_FILE The filename of the file to use as Firmware Support Package binary in the board directory. -config FSP_LOCATION +config FSP_ADDR hex "Firmware Support Package binary location" depends on HAVE_FSP default 0xfffc0000 @@ -65,7 +65,7 @@ config CMC_FILE The filename of the file to use as Chipset Micro Code state machine binary in the board directory. -config CMC_LOCATION +config CMC_ADDR hex "Chipset Micro Code state machine binary location" depends on HAVE_CMC default 0xfffb0000 diff --git a/arch/x86/cpu/queensbay/fsp_support.c b/arch/x86/cpu/queensbay/fsp_support.c index df3bbd07c9e..f830eeb33da 100644 --- a/arch/x86/cpu/queensbay/fsp_support.c +++ b/arch/x86/cpu/queensbay/fsp_support.c @@ -64,7 +64,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void) volatile register u8 *fsp asm("eax"); /* Initalize the FSP base */ - fsp = (u8 *)CONFIG_FSP_LOCATION; + fsp = (u8 *)CONFIG_FSP_ADDR; /* Check the FV signature, _FVH */ if (((struct fv_header_t *)fsp)->sign == 0x4856465F) { diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/cpu/queensbay/tnc_car.S index 2e9139eb8c2..5e09568b85b 100644 --- a/arch/x86/cpu/queensbay/tnc_car.S +++ b/arch/x86/cpu/queensbay/tnc_car.S @@ -29,7 +29,7 @@ find_fsp_header_ret: mov %eax, %ebp /* sanity test */ - cmp $CONFIG_FSP_LOCATION, %eax + cmp $CONFIG_FSP_ADDR, %eax jb die /* calculate TempRamInitEntry address */ diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 645b31c2e28..c9d84e4f062 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -25,7 +25,7 @@ #define CONFIG_X86_RESET_VECTOR #define CONFIG_NR_DRAM_BANKS 8 -#define CONFIG_X86_MRC_START 0xfffa0000 +#define CONFIG_X86_MRC_ADDR 0xfffa0000 #define CONFIG_CACHE_MRC_SIZE_KB 512 #define CONFIG_COREBOOT_SERIAL -- cgit v1.3.1 From 63faf2507d263bbd6285b3fe637fd80df05a58a0 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:43 +0800 Subject: x86: Include FSP and CMC binary in the u-boot.rom build rules Signed-off-by: Bin Meng Acked-by: Simon Glass --- Makefile | 10 +++++++++- include/configs/chromebook_link.h | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/Makefile b/Makefile index d962576c34f..397edc19e2e 100644 --- a/Makefile +++ b/Makefile @@ -961,8 +961,16 @@ ifneq ($(CONFIG_HAVE_MRC),) IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin endif +ifneq ($(CONFIG_HAVE_FSP),) +IFDTOOL_FLAGS += -w $(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE) +endif + +ifneq ($(CONFIG_HAVE_CMC),) +IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE) +endif + ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),) -IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME) +IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE) endif quiet_cmd_ifdtool = IFDTOOL $@ diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index c9d84e4f062..b311f4c5e6f 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -39,7 +39,7 @@ {PCI_VENDOR_ID_INTEL, \ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} -#define CONFIG_X86_OPTION_ROM_FILENAME pci8086,0166.bin +#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin #define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 #define CONFIG_VIDEO_X86 -- cgit v1.3.1 From adfe3b247a7a281931f0fd865e9d00600e9dd384 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:44 +0800 Subject: x86: crownbay: Add SPI flash support The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/queensbay/tnc.c | 26 +++++++++++++++++++++++++- arch/x86/include/asm/arch-queensbay/tnc.h | 15 +++++++++++++++ include/configs/crownbay.h | 2 ++ 3 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 arch/x86/include/asm/arch-queensbay/tnc.h (limited to 'include') diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 8b9815fa005..8637cdca2dd 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -6,18 +6,42 @@ #include #include +#include #include +#include #include #include +static void unprotect_spi_flash(void) +{ + u32 bc; + + bc = pci_read_config32(PCH_LPC_DEV, 0xd8); + bc |= 0x1; /* unprotect the flash */ + pci_write_config32(PCH_LPC_DEV, 0xd8, bc); +} + int arch_cpu_init(void) { + struct pci_controller *hose; + int ret; + post_code(POST_CPU_INIT); #ifdef CONFIG_SYS_X86_TSC_TIMER timer_set_base(rdtsc()); #endif - return x86_cpu_init_f(); + ret = x86_cpu_init_f(); + if (ret) + return ret; + + ret = pci_early_init_hose(&hose); + if (ret) + return ret; + + unprotect_spi_flash(); + + return 0; } int print_cpuinfo(void) diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h new file mode 100644 index 00000000000..67c5e0586c3 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/tnc.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_ARCH_TNC_H_ +#define _X86_ARCH_TNC_H_ + +#include + +/* PCI Configuration Space (D31:F0): LPC */ +#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0) + +#endif /* _X86_ARCH_TNC_H_ */ diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 2314e62a876..a051b1149b5 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -45,6 +45,8 @@ #define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA} +#define CONFIG_SPI_FLASH_SST + /* Video is not supported */ #undef CONFIG_VIDEO #undef CONFIG_CFB_CONSOLE -- cgit v1.3.1 From 0ff65eb99c3ed4d452b9c74dae8c4f736d92303f Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:45 +0800 Subject: x86: crownbay: Enable Intel E1000 NIC support We don't have driver for the Intel Topcliff PCH Gigabit Ethernet controller for now, so enable the Intle E1000 NIC support, which can be plugged into any PCIe slot on the Crown Bay board. Signed-off-by: Bin Meng Acked-by: Simon Glass --- board/intel/crownbay/crownbay.c | 6 ++++++ include/configs/crownbay.h | 1 + 2 files changed, 7 insertions(+) (limited to 'include') diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index 54670d3ac7e..2a254efe3dd 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #define SERIAL_DEV PNP_DEV(0x2e, 4) @@ -24,3 +25,8 @@ void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) { return; } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index a051b1149b5..09a52ab0df4 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -37,6 +37,7 @@ #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP +#define CONFIG_E1000 #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ -- cgit v1.3.1 From aada6276c68daf0229442aa8bf6e60aae4c4fd0d Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:46 +0800 Subject: x86: crownbay: Add SDHCI support There are two standard SD card slots on the Crown Bay board, which are connected to the Topcliff PCH SDIO controllers. Enable the SDHC support so that we can use them. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/queensbay/Makefile | 2 +- arch/x86/cpu/queensbay/topcliff.c | 47 +++++++++++++++++++++++++++++++++++++++ include/configs/crownbay.h | 6 +++++ 3 files changed, 54 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/queensbay/topcliff.c (limited to 'include') diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile index ace04ca4d03..2c2ec01ed29 100644 --- a/arch/x86/cpu/queensbay/Makefile +++ b/arch/x86/cpu/queensbay/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += tnc_car.o tnc_dram.o tnc.o +obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o obj-y += fsp_configs.o fsp_support.o obj-$(CONFIG_PCI) += tnc_pci.o diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c new file mode 100644 index 00000000000..b01422a9655 --- /dev/null +++ b/arch/x86/cpu/queensbay/topcliff.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct pci_device_id mmc_supported[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 }, + { } +}; + +int cpu_mmc_init(bd_t *bis) +{ + struct sdhci_host *mmc_host; + pci_dev_t devbusfn; + u32 iobase; + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) { + devbusfn = pci_find_devices(mmc_supported, i); + if (devbusfn == -1) + return -ENODEV; + + mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); + if (!mmc_host) + return -ENOMEM; + + mmc_host->name = "Topcliff SDHCI"; + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); + mmc_host->ioaddr = (void *)iobase; + mmc_host->quirks = 0; + ret = add_sdhci(mmc_host, 0, 0); + if (ret) + return ret; + } + + return 0; +} diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 09a52ab0df4..b9db6b7649e 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -48,6 +48,12 @@ #define CONFIG_SPI_FLASH_SST +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_CMD_MMC + /* Video is not supported */ #undef CONFIG_VIDEO #undef CONFIG_CFB_CONSOLE -- cgit v1.3.1 From 41702bac01c585cc11fa5dd1f38dea1e5a7c642d Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:47 +0800 Subject: x86: Rename coreboot-serial to x86-serial Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/dts/coreboot.dtsi | 2 +- drivers/serial/Makefile | 2 +- drivers/serial/serial_coreboot.c | 38 -------------------------------------- drivers/serial/serial_x86.c | 38 ++++++++++++++++++++++++++++++++++++++ include/configs/chromebook_link.h | 2 +- include/configs/coreboot.h | 2 +- include/configs/crownbay.h | 2 +- 7 files changed, 43 insertions(+), 43 deletions(-) delete mode 100644 drivers/serial/serial_coreboot.c create mode 100644 drivers/serial/serial_x86.c (limited to 'include') diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi index c8dc4cec3c9..65a93acd3d5 100644 --- a/arch/x86/dts/coreboot.dtsi +++ b/arch/x86/dts/coreboot.dtsi @@ -6,7 +6,7 @@ }; serial { - compatible = "coreboot-uart"; + compatible = "x86-uart"; reg = <0x3f8 0x10>; reg-shift = <0>; io-mapped = <1>; diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 8c849427611..4cc00cd2f84 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -43,7 +43,7 @@ obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o -obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o +obj-$(CONFIG_X86_SERIAL) += serial_x86.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_coreboot.c deleted file mode 100644 index 5c6a76c59c0..00000000000 --- a/drivers/serial/serial_coreboot.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2014 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static const struct udevice_id coreboot_serial_ids[] = { - { .compatible = "coreboot-uart" }, - { } -}; - -static int coreboot_serial_ofdata_to_platdata(struct udevice *dev) -{ - struct ns16550_platdata *plat = dev_get_platdata(dev); - int ret; - - ret = ns16550_serial_ofdata_to_platdata(dev); - if (ret) - return ret; - plat->clock = 1843200; - - return 0; -} -U_BOOT_DRIVER(serial_ns16550) = { - .name = "serial_coreboot", - .id = UCLASS_SERIAL, - .of_match = coreboot_serial_ids, - .ofdata_to_platdata = coreboot_serial_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), - .priv_auto_alloc_size = sizeof(struct NS16550), - .probe = ns16550_serial_probe, - .ops = &ns16550_serial_ops, -}; diff --git a/drivers/serial/serial_x86.c b/drivers/serial/serial_x86.c new file mode 100644 index 00000000000..e81e035ec2f --- /dev/null +++ b/drivers/serial/serial_x86.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static const struct udevice_id x86_serial_ids[] = { + { .compatible = "x86-uart" }, + { } +}; + +static int x86_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev_get_platdata(dev); + int ret; + + ret = ns16550_serial_ofdata_to_platdata(dev); + if (ret) + return ret; + plat->clock = 1843200; + + return 0; +} +U_BOOT_DRIVER(serial_ns16550) = { + .name = "serial_x86", + .id = UCLASS_SERIAL, + .of_match = x86_serial_ids, + .ofdata_to_platdata = x86_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), + .priv_auto_alloc_size = sizeof(struct NS16550), + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, +}; diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index b311f4c5e6f..8930210908f 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -28,7 +28,7 @@ #define CONFIG_X86_MRC_ADDR 0xfffa0000 #define CONFIG_CACHE_MRC_SIZE_KB 512 -#define CONFIG_COREBOOT_SERIAL +#define CONFIG_X86_SERIAL #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 25813804834..990a2d186e3 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -49,7 +49,7 @@ {PCI_VENDOR_ID_INTEL, \ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} -#define CONFIG_COREBOOT_SERIAL +#define CONFIG_X86_SERIAL #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ "stdout=vga,serial,cbmem\0" \ diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index b9db6b7649e..eadb339a0f0 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -20,7 +20,7 @@ #define CONFIG_X86_RESET_VECTOR #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_COREBOOT_SERIAL +#define CONFIG_X86_SERIAL #define CONFIG_SMSC_LPC47M #define CONFIG_PCI_MEM_BUS 0x40000000 -- cgit v1.3.1