From 074596c0b5f4e9a3642a3159a9fc7f8b8064c18a Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 7 Apr 2016 16:22:21 +0800 Subject: armv8/ls1043: Add workaround for DDR erratum A-008850 Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- include/fsl_ddr_sdram.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index cf316a4665f..44ae7fbb9ce 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -146,6 +146,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define WR_DATA_DELAY_SHIFT 10 #endif +/* DDR_EOR register */ +#define DDR_EOR_RD_REOD_DIS 0x07000000 +#define DDR_EOR_WD_REOD_DIS 0x00100000 + /* DDR_MD_CNTL */ #define MD_CNTL_MD_EN 0x80000000 #define MD_CNTL_CS_SEL_CS0 0x00000000 -- cgit v1.3.1 From 4a68489e12313a7fa8740463dee0eea2985eb563 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 16 Mar 2016 13:50:22 +0800 Subject: drivers/ddr/fsl: update workaround for erratum A-008511 Per the latest erratum document, update step 4 and step 8, only DEBUG_29[21] is changed, all other bits should not be changed. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- drivers/ddr/fsl/fsl_ddr_gen4.c | 10 +++++++--- include/fsl_ddr_sdram.h | 3 +++ 2 files changed, 10 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 608810d4e29..7cdb7008b46 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -240,8 +240,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, /* Disable DRAM VRef training */ ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); - /* Disable deskew */ - ddr_out32(&ddr->debug[28], 0x400); + /* disable transmit bit deskew */ + temp32 = ddr_in32(&ddr->debug[28]); + temp32 |= DDR_TX_BD_DIS; + ddr_out32(&ddr->debug[28], temp32); /* Disable D_INIT */ ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); @@ -358,7 +360,9 @@ step2: debug("MR6 = 0x%08x\n", temp32); } ddr_out32(&ddr->sdram_md_cntl, 0); - ddr_out32(&ddr->debug[28], 0); /* Enable deskew */ + temp32 = ddr_in32(&ddr->debug[28]); + temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */ + ddr_out32(&ddr->debug[28], temp32); ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */ /* wait for idle */ timeout = 40; diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 44ae7fbb9ce..acddf14a3f5 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -189,6 +189,9 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ +/* DEBUG_29 register */ +#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */ + #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) -- cgit v1.3.1 From 5fc62fe57097e195a8047859cd3c278a5d6790b6 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 16 Mar 2016 13:50:23 +0800 Subject: driver/ddr/fsl: Add workaround for erratum A-009801 The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + drivers/ddr/fsl/fsl_ddr_gen4.c | 7 +++++++ include/fsl_ddr_sdram.h | 4 ++++ 3 files changed, 12 insertions(+) (limited to 'include') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index a24dc2805d4..6529281c94d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -134,6 +134,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A008751 #define CONFIG_SYS_FSL_ERRATUM_A009635 #define CONFIG_SYS_FSL_ERRATUM_A009663 +#define CONFIG_SYS_FSL_ERRATUM_A009801 #define CONFIG_SYS_FSL_ERRATUM_A009803 #define CONFIG_SYS_FSL_ERRATUM_A009942 diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 7cdb7008b46..1dc06314409 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -251,6 +251,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009801 + temp32 = ddr_in32(&ddr->debug[25]); + temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK; + temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT; + ddr_out32(&ddr->debug[25], temp32); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; tmp = ddr_in32(&ddr->debug[28]); diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index acddf14a3f5..486e47e508d 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -189,6 +189,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ +/* DEBUG_26 register */ +#define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */ +#define DDR_CAS_TO_PRE_SUB_SHIFT 12 + /* DEBUG_29 register */ #define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */ -- cgit v1.3.1 From bcb55f67f22b297d6c10e039bfcef9847a20fbfb Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Wed, 6 Apr 2016 22:25:51 +0530 Subject: armv8: ls2080: enable sec_init in U-Boot Define CONFIG_FSL_CAAM for LS2080 which would enable call to sec_init() during U-Boot. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- include/configs/ls2080a_common.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index a3aad1b99d9..c78aeb57ed4 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -26,6 +26,8 @@ /* We need architecture specific misc initializations */ #define CONFIG_ARCH_MISC_INIT +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + /* Link Definitions */ #ifdef CONFIG_SPL #define CONFIG_SYS_TEXT_BASE 0x80400000 @@ -292,4 +294,10 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #endif /* __LS2_COMMON_H */ -- cgit v1.3.1 From 7ad9cc969b00cd5e238f4a194f0e974d74706b8e Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 19 Apr 2016 08:53:42 +0530 Subject: armv8: ls2080a: update eth prime As per new PHY framework, DPNI naming convetion is no more used. Use new naming convention. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- include/configs/ls2080aqds.h | 2 +- include/configs/ls2080ardb.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 2d7567f394f..16a536aa625 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -374,7 +374,7 @@ unsigned long get_board_ddr_clk(void); #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf #define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "DPNI1" +#define CONFIG_ETHPRIME "DPMAC1@xgmii" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 5bec5099af7..45827f6a038 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -366,7 +366,7 @@ unsigned long get_board_sys_clk(void); #define AQR405_IRQ_MASK 0x36 #define CONFIG_MII -#define CONFIG_ETHPRIME "DPNI1" +#define CONFIG_ETHPRIME "DPMAC1@xgmii" #define CONFIG_PHY_GIGE #define CONFIG_PHY_AQUANTIA #endif -- cgit v1.3.1 From 1297cdb452fcdc6e7149c6761e43629f9c732010 Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Mon, 25 Apr 2016 16:53:53 +0800 Subject: armv8: ls1043a: copy kernel from QSPI when booting with QSPI enabled IFC won't be initialized in U-Boot if QSPI is enabled on LS1043AQDS. So this patch could fix 'sync abort' caused by autoboot that tries to access IFC address. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- include/configs/ls1043a_common.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 54968b52312..a7d49ed6e84 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -257,8 +257,13 @@ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500" +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ + "e0000 f00000 && bootm $kernel_load" +#else #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" +#endif #define CONFIG_BOOTDELAY 10 /* Monitor Command Prompt */ -- cgit v1.3.1 From 76394c9c9139b82e21a6e52da0e7341a3374f4be Mon Sep 17 00:00:00 2001 From: Alex Porosanu Date: Fri, 29 Apr 2016 15:18:00 +0300 Subject: crypto/fsl: add support for multiple SEC engines initialization For SoCs that contain multiple SEC engines, each of them needs to be initialized (by means of initializing among others the random number generator). Signed-off-by: Alex Porosanu Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 ++ drivers/crypto/fsl/jr.c | 271 +++++++++++++++++++++--------------- drivers/crypto/fsl/jr.h | 3 + include/fsl_sec.h | 6 +- 4 files changed, 172 insertions(+), 117 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index f168375b45d..61f5639e0de 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -958,6 +958,15 @@ int cpu_init_r(void) #ifdef CONFIG_FSL_CAAM sec_init(); + +#if defined(CONFIG_PPC_C29X) + if ((SVR_SOC_VER(svr) == SVR_C292) || + (SVR_SOC_VER(svr) == SVR_C293)) + sec_init_idx(1); + + if (SVR_SOC_VER(svr) == SVR_C293) + sec_init_idx(2); +#endif #endif #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 8bc517dadcf..510fa4e3760 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -19,11 +19,26 @@ #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size)) -struct jobring jr; +uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = { + 0, +#if defined(CONFIG_PPC_C29X) + CONFIG_SYS_FSL_SEC_IDX_OFFSET, + 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET +#endif +}; + +#define SEC_ADDR(idx) \ + ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx])) + +#define SEC_JR0_ADDR(idx) \ + (SEC_ADDR(idx) + \ + (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET)) + +struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC]; -static inline void start_jr0(void) +static inline void start_jr0(uint8_t sec_idx) { - ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); u32 ctpr_ms = sec_in32(&sec->ctpr_ms); u32 scfgr = sec_in32(&sec->scfgr); @@ -42,15 +57,15 @@ static inline void start_jr0(void) } } -static inline void jr_reset_liodn(void) +static inline void jr_reset_liodn(uint8_t sec_idx) { - ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); sec_out32(&sec->jrliodnr[0].ls, 0); } -static inline void jr_disable_irq(void) +static inline void jr_disable_irq(uint8_t sec_idx) { - struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; + struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); uint32_t jrcfg = sec_in32(®s->jrcfg1); jrcfg = jrcfg | JR_INTMASK; @@ -58,11 +73,12 @@ static inline void jr_disable_irq(void) sec_out32(®s->jrcfg1, jrcfg); } -static void jr_initregs(void) +static void jr_initregs(uint8_t sec_idx) { - struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; - phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring); - phys_addr_t op_base = virt_to_phys((void *)jr.output_ring); + struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); + struct jobring *jr = &jr0[sec_idx]; + phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring); + phys_addr_t op_base = virt_to_phys((void *)jr->output_ring); #ifdef CONFIG_PHYS_64BIT sec_out32(®s->irba_h, ip_base >> 32); @@ -79,59 +95,63 @@ static void jr_initregs(void) sec_out32(®s->ors, JR_SIZE); sec_out32(®s->irs, JR_SIZE); - if (!jr.irq) - jr_disable_irq(); + if (!jr->irq) + jr_disable_irq(sec_idx); } -static int jr_init(void) +static int jr_init(uint8_t sec_idx) { - memset(&jr, 0, sizeof(struct jobring)); + struct jobring *jr = &jr0[sec_idx]; - jr.jq_id = DEFAULT_JR_ID; - jr.irq = DEFAULT_IRQ; + memset(jr, 0, sizeof(struct jobring)); + + jr->jq_id = DEFAULT_JR_ID; + jr->irq = DEFAULT_IRQ; #ifdef CONFIG_FSL_CORENET - jr.liodn = DEFAULT_JR_LIODN; + jr->liodn = DEFAULT_JR_LIODN; #endif - jr.size = JR_SIZE; - jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, + jr->size = JR_SIZE; + jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, JR_SIZE * sizeof(dma_addr_t)); - if (!jr.input_ring) + if (!jr->input_ring) return -1; - jr.op_size = roundup(JR_SIZE * sizeof(struct op_ring), - ARCH_DMA_MINALIGN); - jr.output_ring = - (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr.op_size); - if (!jr.output_ring) + jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring), + ARCH_DMA_MINALIGN); + jr->output_ring = + (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size); + if (!jr->output_ring) return -1; - memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t)); - memset(jr.output_ring, 0, jr.op_size); + memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t)); + memset(jr->output_ring, 0, jr->op_size); - start_jr0(); + start_jr0(sec_idx); - jr_initregs(); + jr_initregs(sec_idx); return 0; } -static int jr_sw_cleanup(void) +static int jr_sw_cleanup(uint8_t sec_idx) { - jr.head = 0; - jr.tail = 0; - jr.read_idx = 0; - jr.write_idx = 0; - memset(jr.info, 0, sizeof(jr.info)); - memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t)); - memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring)); + struct jobring *jr = &jr0[sec_idx]; + + jr->head = 0; + jr->tail = 0; + jr->read_idx = 0; + jr->write_idx = 0; + memset(jr->info, 0, sizeof(jr->info)); + memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t)); + memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring)); return 0; } -static int jr_hw_reset(void) +static int jr_hw_reset(uint8_t sec_idx) { - struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; + struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); uint32_t timeout = 100000; uint32_t jrint, jrcr; @@ -161,10 +181,11 @@ static int jr_hw_reset(void) /* -1 --- error, can't enqueue -- no space available */ static int jr_enqueue(uint32_t *desc_addr, void (*callback)(uint32_t status, void *arg), - void *arg) + void *arg, uint8_t sec_idx) { - struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; - int head = jr.head; + struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); + struct jobring *jr = &jr0[sec_idx]; + int head = jr->head; uint32_t desc_word; int length = desc_len(desc_addr); int i; @@ -184,18 +205,14 @@ static int jr_enqueue(uint32_t *desc_addr, phys_addr_t desc_phys_addr = virt_to_phys(desc_addr); - if (sec_in32(®s->irsa) == 0 || - CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0) - return -1; - - jr.info[head].desc_phys_addr = desc_phys_addr; - jr.info[head].callback = (void *)callback; - jr.info[head].arg = arg; - jr.info[head].op_done = 0; + jr->info[head].desc_phys_addr = desc_phys_addr; + jr->info[head].callback = (void *)callback; + jr->info[head].arg = arg; + jr->info[head].op_done = 0; - unsigned long start = (unsigned long)&jr.info[head] & + unsigned long start = (unsigned long)&jr->info[head] & ~(ARCH_DMA_MINALIGN - 1); - unsigned long end = ALIGN((unsigned long)&jr.info[head] + + unsigned long end = ALIGN((unsigned long)&jr->info[head] + sizeof(struct jr_info), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); @@ -205,11 +222,11 @@ static int jr_enqueue(uint32_t *desc_addr, * depend on endianness of SEC block. */ #ifdef CONFIG_SYS_FSL_SEC_LE - addr_lo = (uint32_t *)(&jr.input_ring[head]); - addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1; + addr_lo = (uint32_t *)(&jr->input_ring[head]); + addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1; #elif defined(CONFIG_SYS_FSL_SEC_BE) - addr_hi = (uint32_t *)(&jr.input_ring[head]); - addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1; + addr_hi = (uint32_t *)(&jr->input_ring[head]); + addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1; #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */ sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32)); @@ -217,21 +234,21 @@ static int jr_enqueue(uint32_t *desc_addr, #else /* Write the 32 bit Descriptor address on Input Ring. */ - sec_out32(&jr.input_ring[head], desc_phys_addr); + sec_out32(&jr->input_ring[head], desc_phys_addr); #endif /* ifdef CONFIG_PHYS_64BIT */ - start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); - end = ALIGN((unsigned long)&jr.input_ring[head] + + start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)&jr->input_ring[head] + sizeof(dma_addr_t), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); - jr.head = (head + 1) & (jr.size - 1); + jr->head = (head + 1) & (jr->size - 1); /* Invalidate output ring */ - start = (unsigned long)jr.output_ring & + start = (unsigned long)jr->output_ring & ~(ARCH_DMA_MINALIGN - 1); - end = ALIGN((unsigned long)jr.output_ring + jr.op_size, - ARCH_DMA_MINALIGN); + end = ALIGN((unsigned long)jr->output_ring + jr->op_size, + ARCH_DMA_MINALIGN); invalidate_dcache_range(start, end); sec_out32(®s->irja, 1); @@ -239,11 +256,12 @@ static int jr_enqueue(uint32_t *desc_addr, return 0; } -static int jr_dequeue(void) +static int jr_dequeue(int sec_idx) { - struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; - int head = jr.head; - int tail = jr.tail; + struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); + struct jobring *jr = &jr0[sec_idx]; + int head = jr->head; + int tail = jr->tail; int idx, i, found; void (*callback)(uint32_t status, void *arg); void *arg = NULL; @@ -253,7 +271,8 @@ static int jr_dequeue(void) uint32_t *addr; #endif - while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) { + while (sec_in32(®s->orsf) && CIRC_CNT(jr->head, jr->tail, + jr->size)) { found = 0; @@ -264,11 +283,11 @@ static int jr_dequeue(void) * depend on endianness of SEC block. */ #ifdef CONFIG_SYS_FSL_SEC_LE - addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc); - addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1; + addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc); + addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1; #elif defined(CONFIG_SYS_FSL_SEC_BE) - addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc); - addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1; + addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc); + addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1; #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */ op_desc = ((u64)sec_in32(addr_hi) << 32) | @@ -276,15 +295,15 @@ static int jr_dequeue(void) #else /* Read the 32 bit Descriptor address from Output Ring. */ - addr = (uint32_t *)&jr.output_ring[jr.tail].desc; + addr = (uint32_t *)&jr->output_ring[jr->tail].desc; op_desc = sec_in32(addr); #endif /* ifdef CONFIG_PHYS_64BIT */ - uint32_t status = sec_in32(&jr.output_ring[jr.tail].status); + uint32_t status = sec_in32(&jr->output_ring[jr->tail].status); - for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) { - idx = (tail + i) & (jr.size - 1); - if (op_desc == jr.info[idx].desc_phys_addr) { + for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) { + idx = (tail + i) & (jr->size - 1); + if (op_desc == jr->info[idx].desc_phys_addr) { found = 1; break; } @@ -294,9 +313,9 @@ static int jr_dequeue(void) if (!found) return -1; - jr.info[idx].op_done = 1; - callback = (void *)jr.info[idx].callback; - arg = jr.info[idx].arg; + jr->info[idx].op_done = 1; + callback = (void *)jr->info[idx].callback; + arg = jr->info[idx].arg; /* When the job on tail idx gets done, increment * tail till the point where job completed out of oredr has @@ -304,14 +323,14 @@ static int jr_dequeue(void) */ if (idx == tail) do { - tail = (tail + 1) & (jr.size - 1); - } while (jr.info[tail].op_done); + tail = (tail + 1) & (jr->size - 1); + } while (jr->info[tail].op_done); - jr.tail = tail; - jr.read_idx = (jr.read_idx + 1) & (jr.size - 1); + jr->tail = tail; + jr->read_idx = (jr->read_idx + 1) & (jr->size - 1); sec_out32(®s->orjr, 1); - jr.info[idx].op_done = 0; + jr->info[idx].op_done = 0; callback(status, arg); } @@ -327,7 +346,7 @@ static void desc_done(uint32_t status, void *arg) x->done = 1; } -int run_descriptor_jr(uint32_t *desc) +static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) { unsigned long long timeval = get_ticks(); unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); @@ -336,7 +355,7 @@ int run_descriptor_jr(uint32_t *desc) memset(&op, 0, sizeof(op)); - ret = jr_enqueue(desc, desc_done, &op); + ret = jr_enqueue(desc, desc_done, &op, sec_idx); if (ret) { debug("Error in SEC enq\n"); ret = JQ_ENQ_ERR; @@ -346,7 +365,7 @@ int run_descriptor_jr(uint32_t *desc) timeval = get_ticks(); timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); while (op.done != 1) { - ret = jr_dequeue(); + ret = jr_dequeue(sec_idx); if (ret) { debug("Error in SEC deq\n"); ret = JQ_DEQ_ERR; @@ -368,20 +387,30 @@ out: return ret; } -int jr_reset(void) +int run_descriptor_jr(uint32_t *desc) +{ + return run_descriptor_jr_idx(desc, 0); +} + +static inline int jr_reset_sec(uint8_t sec_idx) { - if (jr_hw_reset() < 0) + if (jr_hw_reset(sec_idx) < 0) return -1; /* Clean up the jobring structure maintained by software */ - jr_sw_cleanup(); + jr_sw_cleanup(sec_idx); return 0; } -int sec_reset(void) +int jr_reset(void) { - ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + return jr_reset_sec(0); +} + +static inline int sec_reset_idx(uint8_t sec_idx) +{ + ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); uint32_t mcfgr = sec_in32(&sec->mcfgr); uint32_t timeout = 100000; @@ -408,14 +437,13 @@ int sec_reset(void) return 0; } -static int instantiate_rng(void) +static int instantiate_rng(uint8_t sec_idx) { struct result op; u32 *desc; u32 rdsta_val; int ret = 0; - ccsr_sec_t __iomem *sec = - (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; @@ -432,7 +460,7 @@ static int instantiate_rng(void) flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); - ret = run_descriptor_jr(desc); + ret = run_descriptor_jr_idx(desc, sec_idx); if (ret) printf("RNG: Instantiation failed with error %x\n", ret); @@ -444,9 +472,14 @@ static int instantiate_rng(void) return ret; } -static u8 get_rng_vid(void) +int sec_reset(void) +{ + return sec_reset_idx(0); +} + +static u8 get_rng_vid(uint8_t sec_idx) { - ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); u32 cha_vid = sec_in32(&sec->chavid_ls); return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT; @@ -456,10 +489,9 @@ static u8 get_rng_vid(void) * By default, the TRNG runs for 200 clocks per sample; * 1200 clocks per sample generates better entropy. */ -static void kick_trng(int ent_delay) +static void kick_trng(int ent_delay, uint8_t sec_idx) { - ccsr_sec_t __iomem *sec = - (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; u32 val; @@ -486,11 +518,10 @@ static void kick_trng(int ent_delay) sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM); } -static int rng_init(void) +static int rng_init(uint8_t sec_idx) { int ret, ent_delay = RTSDCTL_ENT_DLY_MIN; - ccsr_sec_t __iomem *sec = - (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; @@ -509,7 +540,7 @@ static int rng_init(void) * Also, if a handle was instantiated, do not change * the TRNG parameters. */ - kick_trng(ent_delay); + kick_trng(ent_delay, sec_idx); ent_delay += 400; /* * if instantiate_rng(...) fails, the loop will rerun @@ -518,7 +549,7 @@ static int rng_init(void) * interval, leading to a sucessful initialization of * the RNG. */ - ret = instantiate_rng(); + ret = instantiate_rng(sec_idx); } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); if (ret) { printf("RNG: Failed to instantiate RNG\n"); @@ -531,9 +562,9 @@ static int rng_init(void) return ret; } -int sec_init(void) +int sec_init_idx(uint8_t sec_idx) { - ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); uint32_t mcr = sec_in32(&sec->mcfgr); int ret = 0; @@ -543,6 +574,11 @@ int sec_init(void) uint32_t liodn_s; #endif + if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) { + printf("SEC initialization failed\n"); + return -1; + } + /* * Modifying CAAM Read/Write Attributes * For LS2080A @@ -568,7 +604,7 @@ int sec_init(void) liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT; #endif - ret = jr_init(); + ret = jr_init(sec_idx); if (ret < 0) { printf("SEC initialization failed\n"); return -1; @@ -582,13 +618,18 @@ int sec_init(void) pamu_enable(); #endif - if (get_rng_vid() >= 4) { - if (rng_init() < 0) { - printf("RNG instantiation failed\n"); + if (get_rng_vid(sec_idx) >= 4) { + if (rng_init(sec_idx) < 0) { + printf("SEC%u: RNG instantiation failed\n", sec_idx); return -1; } - printf("SEC: RNG instantiated\n"); + printf("SEC%u: RNG instantiated\n", sec_idx); } return ret; } + +int sec_init(void) +{ + return sec_init_idx(0); +} diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 1642dbbf4c2..d897e572d6e 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -90,6 +90,9 @@ struct jobring { /* This ring can be on the stack */ struct jr_info info[JR_SIZE]; struct op_ring *output_ring; + /* Offset in CCSR to the SEC engine to which this JR belongs */ + uint32_t sec_offset; + }; struct result { diff --git a/include/fsl_sec.h b/include/fsl_sec.h index a52110a625c..bffabc89b99 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -294,8 +294,6 @@ struct sg_entry { #endif -int sec_init(void); - /* blob_dek: * Encapsulates the src in a secure blob and stores it dst * @src: reference to the plaintext @@ -305,6 +303,10 @@ int sec_init(void); */ int blob_dek(const u8 *src, u8 *dst, u8 len); +#if defined(CONFIG_PPC_C29X) +int sec_init_idx(uint8_t); +#endif +int sec_init(void); #endif #endif /* __FSL_SEC_H */ -- cgit v1.3.1 From 7942550a146f3eaf00add0e13442946365cc9775 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Fri, 29 Apr 2016 22:07:21 +0800 Subject: armv8: ls1043ardb: invert irq pin polarity for AQR105 PHY To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by setting relative bit in SCFG_INTPCR register, because AQR105 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie Reviewed-by: York Sun --- board/freescale/ls1043ardb/ls1043ardb.c | 4 ++++ include/configs/ls1043ardb.h | 1 + 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index b1691393e6e..14365207da1 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -82,6 +82,8 @@ int board_early_init_f(void) int board_init(void) { + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + #ifdef CONFIG_FSL_IFC init_final_memctl_regs(); #endif @@ -93,6 +95,8 @@ int board_init(void) #ifdef CONFIG_U_QE u_qe_init(); #endif + /* invert AQR105 IRQ pins polarity */ + out_be32(&scfg->intpcr, AQR105_IRQ_MASK); return 0; } diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 6d35be2e473..39687cfef4d 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -253,6 +253,7 @@ #define CONFIG_PHY_VITESSE #define CONFIG_PHY_REALTEK #define CONFIG_PHY_AQUANTIA +#define AQR105_IRQ_MASK 0x40000000 #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 -- cgit v1.3.1 From bc323b3fa7cbf1008f02d342c0505231961b5fa6 Mon Sep 17 00:00:00 2001 From: Po Liu Date: Wed, 18 May 2016 10:09:38 +0800 Subject: armv8: ls1043ardb: enable scsi command and pcie to sata converter Enable scsi command and pcie to sata chip 88SE9170. Signed-off-by: Po Liu Reviewed-by: York Sun --- include/configs/ls1043ardb.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'include') diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 39687cfef4d..aca8d95c153 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -286,6 +286,27 @@ #define CONFIG_USB_STORAGE #endif +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_CMD_SCSI +#ifndef CONFIG_CMD_FAT +#define CONFIG_CMD_FAT +#endif +#ifndef CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT2 +#endif +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 2 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define SCSI_VEND_ID 0x1b4b +#define SCSI_DEV_ID 0x9170 +#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#define CONFIG_PCI + #include #endif /* __LS1043ARDB_H__ */ -- cgit v1.3.1 From 46caebc1dff8f456b4f076bbebbb2ba32236d06d Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 7 Apr 2016 09:52:11 -0700 Subject: powerpc/t2080qds: Enable qixis commands to reboot from NAND and SD Signed-off-by: York Sun CC: Shengzhou Liu --- include/configs/T208xQDS.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index d8c57a833b8..f48697c0339 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -291,6 +291,10 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_RCW_SRC_NAND 0x104 +#define QIXIS_RCW_SRC_SD 0x040 #define QIXIS_RST_CTL_RESET 0x83 #define QIXIS_RST_FORCE_MEM 0x1 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -- cgit v1.3.1 From 030b9e34c97e94c0a1a30ed391058b130ba6d314 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sat, 7 May 2016 07:46:35 -0700 Subject: x86: Remove acpi=off boot parameter when ACPI is on Remove the kernel boot parameter acpi=off so that kernel can turn on ACPI support. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Tested-by: Stefan Roese Reviewed-by: Simon Glass --- include/configs/x86-common.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index b79f47baf3f..b4aad6cd24f 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -193,14 +193,19 @@ #define CONFIG_HOSTNAME x86 #define CONFIG_BOOTFILE "bzImage" #define CONFIG_LOADADDR 0x1000000 -#define CONFIG_RAMDISK_ADDR 0x4000000 +#define CONFIG_RAMDISK_ADDR 0x4000000 +#ifdef CONFIG_GENERATE_ACPI_TABLE +#define CONFIG_OTHBOOTARGS "othbootargs=\0" +#else +#define CONFIG_OTHBOOTARGS "othbootargs=acpi=off\0" +#endif #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_STD_DEVICES_SETTINGS \ "pciconfighost=1\0" \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "othbootargs=acpi=off\0" \ + CONFIG_OTHBOOTARGS \ "ramdiskaddr=0x4000000\0" \ "ramdiskfile=initramfs.gz\0" -- cgit v1.3.1 From dd6f3abbb81d4d0f8883a523e26fd45833a6b0d3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 6 May 2016 10:40:22 -0400 Subject: x86: qemu: Move qfw command over to cmd and add Kconfig entry - Move the command portion of arch/x86/cpu/qemu/fw_cfg.c into cmd/qemu_fw_cfg.c - Move arch/x86/include/asm/fw_cfg.h to include/qemu_fw_cfg.h - Rename ACPI table portion to arch/x86/cpu/qemu/acpi_table.c Signed-off-by: Tom Rini Reviewed-by: Bin Meng --- arch/x86/cpu/mp_init.c | 2 +- arch/x86/cpu/qemu/Makefile | 3 +- arch/x86/cpu/qemu/acpi_table.c | 243 ++++++++++++++++++ arch/x86/cpu/qemu/cpu.c | 2 +- arch/x86/cpu/qemu/fw_cfg.c | 570 ----------------------------------------- arch/x86/cpu/qemu/qemu.c | 2 +- arch/x86/include/asm/fw_cfg.h | 157 ------------ arch/x86/lib/acpi_table.c | 2 +- cmd/Kconfig | 7 + cmd/Makefile | 1 + cmd/qemu_fw_cfg.c | 343 +++++++++++++++++++++++++ configs/qemu-x86_defconfig | 1 + include/qemu_fw_cfg.h | 162 ++++++++++++ 13 files changed, 763 insertions(+), 732 deletions(-) create mode 100644 arch/x86/cpu/qemu/acpi_table.c delete mode 100644 arch/x86/cpu/qemu/fw_cfg.c delete mode 100644 arch/x86/include/asm/fw_cfg.h create mode 100644 cmd/qemu_fw_cfg.c create mode 100644 include/qemu_fw_cfg.h (limited to 'include') diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 2604a687ab9..13bec7ae1ed 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -21,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index 6eeddf154ed..97b965c3de5 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -7,4 +7,5 @@ ifndef CONFIG_EFI_STUB obj-y += car.o dram.o endif -obj-y += cpu.o fw_cfg.o qemu.o +obj-y += cpu.o qemu.o +obj-$(CONFIG_QEMU_ACPI_TABLE) += acpi_table.o diff --git a/arch/x86/cpu/qemu/acpi_table.c b/arch/x86/cpu/qemu/acpi_table.c new file mode 100644 index 00000000000..49381acd29f --- /dev/null +++ b/arch/x86/cpu/qemu/acpi_table.c @@ -0,0 +1,243 @@ +/* + * (C) Copyright 2015 Miao Yan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * This function allocates memory for ACPI tables + * + * @entry : BIOS linker command entry which tells where to allocate memory + * (either high memory or low memory) + * @addr : The address that should be used for low memory allcation. If the + * memory allocation request is 'ZONE_HIGH' then this parameter will + * be ignored. + * @return: 0 on success, or negative value on failure + */ +static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr) +{ + uint32_t size, align; + struct fw_file *file; + unsigned long aligned_addr; + + align = le32_to_cpu(entry->alloc.align); + /* align must be power of 2 */ + if (align & (align - 1)) { + printf("error: wrong alignment %u\n", align); + return -EINVAL; + } + + file = qemu_fwcfg_find_file(entry->alloc.file); + if (!file) { + printf("error: can't find file %s\n", entry->alloc.file); + return -ENOENT; + } + + size = be32_to_cpu(file->cfg.size); + + /* + * ZONE_HIGH means we need to allocate from high memory, since + * malloc space is already at the end of RAM, so we directly use it. + * If allocation zone is ZONE_FSEG, then we use the 'addr' passed + * in which is low memory + */ + if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) { + aligned_addr = (unsigned long)memalign(align, size); + if (!aligned_addr) { + printf("error: allocating resource\n"); + return -ENOMEM; + } + } else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) { + aligned_addr = ALIGN(*addr, align); + } else { + printf("error: invalid allocation zone\n"); + return -EINVAL; + } + + debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n", + file->cfg.name, size, entry->alloc.zone, align, aligned_addr); + + qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select), + size, (void *)aligned_addr); + file->addr = aligned_addr; + + /* adjust address for low memory allocation */ + if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) + *addr = (aligned_addr + size); + + return 0; +} + +/* + * This function patches ACPI tables previously loaded + * by bios_linker_allocate() + * + * @entry : BIOS linker command entry which tells how to patch + * ACPI tables + * @return: 0 on success, or negative value on failure + */ +static int bios_linker_add_pointer(struct bios_linker_entry *entry) +{ + struct fw_file *dest, *src; + uint32_t offset = le32_to_cpu(entry->pointer.offset); + uint64_t pointer = 0; + + dest = qemu_fwcfg_find_file(entry->pointer.dest_file); + if (!dest || !dest->addr) + return -ENOENT; + src = qemu_fwcfg_find_file(entry->pointer.src_file); + if (!src || !src->addr) + return -ENOENT; + + debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n", + dest->addr, src->addr, offset, entry->pointer.size, pointer); + + memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size); + pointer = le64_to_cpu(pointer); + pointer += (unsigned long)src->addr; + pointer = cpu_to_le64(pointer); + memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size); + + return 0; +} + +/* + * This function updates checksum fields of ACPI tables previously loaded + * by bios_linker_allocate() + * + * @entry : BIOS linker command entry which tells where to update ACPI table + * checksums + * @return: 0 on success, or negative value on failure + */ +static int bios_linker_add_checksum(struct bios_linker_entry *entry) +{ + struct fw_file *file; + uint8_t *data, cksum = 0; + uint8_t *cksum_start; + + file = qemu_fwcfg_find_file(entry->cksum.file); + if (!file || !file->addr) + return -ENOENT; + + data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset)); + cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start)); + cksum = table_compute_checksum(cksum_start, + le32_to_cpu(entry->cksum.length)); + *data = cksum; + + return 0; +} + +unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) +{ + entries[0].addr = 0; + entries[0].size = ISA_START_ADDRESS; + entries[0].type = E820_RAM; + + entries[1].addr = ISA_START_ADDRESS; + entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS; + entries[1].type = E820_RESERVED; + + /* + * since we use memalign(malloc) to allocate high memory for + * storing ACPI tables, we need to reserve them in e820 tables, + * otherwise kernel will reclaim them and data will be corrupted + */ + entries[2].addr = ISA_END_ADDRESS; + entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS; + entries[2].type = E820_RAM; + + /* for simplicity, reserve entire malloc space */ + entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN; + entries[3].size = TOTAL_MALLOC_LEN; + entries[3].type = E820_RESERVED; + + entries[4].addr = gd->relocaddr; + entries[4].size = gd->ram_size - gd->relocaddr; + entries[4].type = E820_RESERVED; + + entries[5].addr = CONFIG_PCIE_ECAM_BASE; + entries[5].size = CONFIG_PCIE_ECAM_SIZE; + entries[5].type = E820_RESERVED; + + return 6; +} + +/* This function loads and patches ACPI tables provided by QEMU */ +u32 write_acpi_tables(u32 addr) +{ + int i, ret = 0; + struct fw_file *file; + struct bios_linker_entry *table_loader; + struct bios_linker_entry *entry; + uint32_t size; + + /* make sure fw_list is loaded */ + ret = qemu_fwcfg_read_firmware_list(); + if (ret) { + printf("error: can't read firmware file list\n"); + return addr; + } + + file = qemu_fwcfg_find_file("etc/table-loader"); + if (!file) { + printf("error: can't find etc/table-loader\n"); + return addr; + } + + size = be32_to_cpu(file->cfg.size); + if ((size % sizeof(*entry)) != 0) { + printf("error: table-loader maybe corrupted\n"); + return addr; + } + + table_loader = malloc(size); + if (!table_loader) { + printf("error: no memory for table-loader\n"); + return addr; + } + + qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select), + size, table_loader); + + for (i = 0; i < (size / sizeof(*entry)); i++) { + entry = table_loader + i; + switch (le32_to_cpu(entry->command)) { + case BIOS_LINKER_LOADER_COMMAND_ALLOCATE: + ret = bios_linker_allocate(entry, &addr); + if (ret) + goto out; + break; + case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER: + ret = bios_linker_add_pointer(entry); + if (ret) + goto out; + break; + case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM: + ret = bios_linker_add_checksum(entry); + if (ret) + goto out; + break; + default: + break; + } + } + +out: + if (ret) + qemu_fwcfg_free_files(); + + free(table_loader); + return addr; +} diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c index a1b70c6bde7..4d2989a7084 100644 --- a/arch/x86/cpu/qemu/cpu.c +++ b/arch/x86/cpu/qemu/cpu.c @@ -8,8 +8,8 @@ #include #include #include +#include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c deleted file mode 100644 index 2e2794ebd7f..00000000000 --- a/arch/x86/cpu/qemu/fw_cfg.c +++ /dev/null @@ -1,570 +0,0 @@ -/* - * (C) Copyright 2015 Miao Yan - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static bool fwcfg_present; -static bool fwcfg_dma_present; - -static LIST_HEAD(fw_list); - -/* Read configuration item using fw_cfg PIO interface */ -static void qemu_fwcfg_read_entry_pio(uint16_t entry, - uint32_t size, void *address) -{ - uint32_t i = 0; - uint8_t *data = address; - - /* - * writting FW_CFG_INVALID will cause read operation to resume at - * last offset, otherwise read will start at offset 0 - */ - if (entry != FW_CFG_INVALID) - outw(entry, FW_CONTROL_PORT); - while (size--) - data[i++] = inb(FW_DATA_PORT); -} - -/* Read configuration item using fw_cfg DMA interface */ -static void qemu_fwcfg_read_entry_dma(uint16_t entry, - uint32_t size, void *address) -{ - struct fw_cfg_dma_access dma; - - dma.length = cpu_to_be32(size); - dma.address = cpu_to_be64((uintptr_t)address); - dma.control = cpu_to_be32(FW_CFG_DMA_READ); - - /* - * writting FW_CFG_INVALID will cause read operation to resume at - * last offset, otherwise read will start at offset 0 - */ - if (entry != FW_CFG_INVALID) - dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16)); - - barrier(); - - debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n", - address, size, be32_to_cpu(dma.control)); - - outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH); - - while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR) - __asm__ __volatile__ ("pause"); -} - -static bool qemu_fwcfg_present(void) -{ - uint32_t qemu; - - qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu); - return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE; -} - -static bool qemu_fwcfg_dma_present(void) -{ - uint8_t dma_enabled; - - qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled); - if (dma_enabled & FW_CFG_DMA_ENABLED) - return true; - - return false; -} - -static void qemu_fwcfg_read_entry(uint16_t entry, - uint32_t length, void *address) -{ - if (fwcfg_dma_present) - qemu_fwcfg_read_entry_dma(entry, length, address); - else - qemu_fwcfg_read_entry_pio(entry, length, address); -} - -int qemu_fwcfg_online_cpus(void) -{ - uint16_t nb_cpus; - - if (!fwcfg_present) - return -ENODEV; - - qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus); - - return le16_to_cpu(nb_cpus); -} - -/* - * This function prepares kernel for zboot. It loads kernel data - * to 'load_addr', initrd to 'initrd_addr' and kernel command - * line using qemu fw_cfg interface. - */ -static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr) -{ - char *data_addr; - uint32_t setup_size, kernel_size, cmdline_size, initrd_size; - - qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size); - qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size); - - if (setup_size == 0 || kernel_size == 0) { - printf("warning: no kernel available\n"); - return -1; - } - - data_addr = load_addr; - qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA, - le32_to_cpu(setup_size), data_addr); - data_addr += le32_to_cpu(setup_size); - - qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA, - le32_to_cpu(kernel_size), data_addr); - data_addr += le32_to_cpu(kernel_size); - - data_addr = initrd_addr; - qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size); - if (initrd_size == 0) { - printf("warning: no initrd available\n"); - } else { - qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA, - le32_to_cpu(initrd_size), data_addr); - data_addr += le32_to_cpu(initrd_size); - } - - qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size); - if (cmdline_size) { - qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA, - le32_to_cpu(cmdline_size), data_addr); - /* - * if kernel cmdline only contains '\0', (e.g. no -append - * when invoking qemu), do not update bootargs - */ - if (*data_addr != '\0') { - if (setenv("bootargs", data_addr) < 0) - printf("warning: unable to change bootargs\n"); - } - } - - printf("loading kernel to address %p size %x", load_addr, - le32_to_cpu(kernel_size)); - if (initrd_size) - printf(" initrd %p size %x\n", - initrd_addr, - le32_to_cpu(initrd_size)); - else - printf("\n"); - - return 0; -} - -static int qemu_fwcfg_read_firmware_list(void) -{ - int i; - uint32_t count; - struct fw_file *file; - struct list_head *entry; - - /* don't read it twice */ - if (!list_empty(&fw_list)) - return 0; - - qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count); - if (!count) - return 0; - - count = be32_to_cpu(count); - for (i = 0; i < count; i++) { - file = malloc(sizeof(*file)); - if (!file) { - printf("error: allocating resource\n"); - goto err; - } - qemu_fwcfg_read_entry(FW_CFG_INVALID, - sizeof(struct fw_cfg_file), &file->cfg); - file->addr = 0; - list_add_tail(&file->list, &fw_list); - } - - return 0; - -err: - list_for_each(entry, &fw_list) { - file = list_entry(entry, struct fw_file, list); - free(file); - } - - return -ENOMEM; -} - -#ifdef CONFIG_QEMU_ACPI_TABLE -static struct fw_file *qemu_fwcfg_find_file(const char *name) -{ - struct list_head *entry; - struct fw_file *file; - - list_for_each(entry, &fw_list) { - file = list_entry(entry, struct fw_file, list); - if (!strcmp(file->cfg.name, name)) - return file; - } - - return NULL; -} - -/* - * This function allocates memory for ACPI tables - * - * @entry : BIOS linker command entry which tells where to allocate memory - * (either high memory or low memory) - * @addr : The address that should be used for low memory allcation. If the - * memory allocation request is 'ZONE_HIGH' then this parameter will - * be ignored. - * @return: 0 on success, or negative value on failure - */ -static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr) -{ - uint32_t size, align; - struct fw_file *file; - unsigned long aligned_addr; - - align = le32_to_cpu(entry->alloc.align); - /* align must be power of 2 */ - if (align & (align - 1)) { - printf("error: wrong alignment %u\n", align); - return -EINVAL; - } - - file = qemu_fwcfg_find_file(entry->alloc.file); - if (!file) { - printf("error: can't find file %s\n", entry->alloc.file); - return -ENOENT; - } - - size = be32_to_cpu(file->cfg.size); - - /* - * ZONE_HIGH means we need to allocate from high memory, since - * malloc space is already at the end of RAM, so we directly use it. - * If allocation zone is ZONE_FSEG, then we use the 'addr' passed - * in which is low memory - */ - if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) { - aligned_addr = (unsigned long)memalign(align, size); - if (!aligned_addr) { - printf("error: allocating resource\n"); - return -ENOMEM; - } - } else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) { - aligned_addr = ALIGN(*addr, align); - } else { - printf("error: invalid allocation zone\n"); - return -EINVAL; - } - - debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n", - file->cfg.name, size, entry->alloc.zone, align, aligned_addr); - - qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select), - size, (void *)aligned_addr); - file->addr = aligned_addr; - - /* adjust address for low memory allocation */ - if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) - *addr = (aligned_addr + size); - - return 0; -} - -/* - * This function patches ACPI tables previously loaded - * by bios_linker_allocate() - * - * @entry : BIOS linker command entry which tells how to patch - * ACPI tables - * @return: 0 on success, or negative value on failure - */ -static int bios_linker_add_pointer(struct bios_linker_entry *entry) -{ - struct fw_file *dest, *src; - uint32_t offset = le32_to_cpu(entry->pointer.offset); - uint64_t pointer = 0; - - dest = qemu_fwcfg_find_file(entry->pointer.dest_file); - if (!dest || !dest->addr) - return -ENOENT; - src = qemu_fwcfg_find_file(entry->pointer.src_file); - if (!src || !src->addr) - return -ENOENT; - - debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n", - dest->addr, src->addr, offset, entry->pointer.size, pointer); - - memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size); - pointer = le64_to_cpu(pointer); - pointer += (unsigned long)src->addr; - pointer = cpu_to_le64(pointer); - memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size); - - return 0; -} - -/* - * This function updates checksum fields of ACPI tables previously loaded - * by bios_linker_allocate() - * - * @entry : BIOS linker command entry which tells where to update ACPI table - * checksums - * @return: 0 on success, or negative value on failure - */ -static int bios_linker_add_checksum(struct bios_linker_entry *entry) -{ - struct fw_file *file; - uint8_t *data, cksum = 0; - uint8_t *cksum_start; - - file = qemu_fwcfg_find_file(entry->cksum.file); - if (!file || !file->addr) - return -ENOENT; - - data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset)); - cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start)); - cksum = table_compute_checksum(cksum_start, - le32_to_cpu(entry->cksum.length)); - *data = cksum; - - return 0; -} - -unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) -{ - entries[0].addr = 0; - entries[0].size = ISA_START_ADDRESS; - entries[0].type = E820_RAM; - - entries[1].addr = ISA_START_ADDRESS; - entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS; - entries[1].type = E820_RESERVED; - - /* - * since we use memalign(malloc) to allocate high memory for - * storing ACPI tables, we need to reserve them in e820 tables, - * otherwise kernel will reclaim them and data will be corrupted - */ - entries[2].addr = ISA_END_ADDRESS; - entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS; - entries[2].type = E820_RAM; - - /* for simplicity, reserve entire malloc space */ - entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN; - entries[3].size = TOTAL_MALLOC_LEN; - entries[3].type = E820_RESERVED; - - entries[4].addr = gd->relocaddr; - entries[4].size = gd->ram_size - gd->relocaddr; - entries[4].type = E820_RESERVED; - - entries[5].addr = CONFIG_PCIE_ECAM_BASE; - entries[5].size = CONFIG_PCIE_ECAM_SIZE; - entries[5].type = E820_RESERVED; - - return 6; -} - -/* This function loads and patches ACPI tables provided by QEMU */ -u32 write_acpi_tables(u32 addr) -{ - int i, ret = 0; - struct fw_file *file; - struct bios_linker_entry *table_loader; - struct bios_linker_entry *entry; - uint32_t size; - struct list_head *list; - - /* make sure fw_list is loaded */ - ret = qemu_fwcfg_read_firmware_list(); - if (ret) { - printf("error: can't read firmware file list\n"); - return addr; - } - - file = qemu_fwcfg_find_file("etc/table-loader"); - if (!file) { - printf("error: can't find etc/table-loader\n"); - return addr; - } - - size = be32_to_cpu(file->cfg.size); - if ((size % sizeof(*entry)) != 0) { - printf("error: table-loader maybe corrupted\n"); - return addr; - } - - table_loader = malloc(size); - if (!table_loader) { - printf("error: no memory for table-loader\n"); - return addr; - } - - qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select), - size, table_loader); - - for (i = 0; i < (size / sizeof(*entry)); i++) { - entry = table_loader + i; - switch (le32_to_cpu(entry->command)) { - case BIOS_LINKER_LOADER_COMMAND_ALLOCATE: - ret = bios_linker_allocate(entry, &addr); - if (ret) - goto out; - break; - case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER: - ret = bios_linker_add_pointer(entry); - if (ret) - goto out; - break; - case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM: - ret = bios_linker_add_checksum(entry); - if (ret) - goto out; - break; - default: - break; - } - } - -out: - if (ret) { - list_for_each(list, &fw_list) { - file = list_entry(list, struct fw_file, list); - if (file->addr) - free((void *)file->addr); - } - } - - free(table_loader); - return addr; -} -#endif - -static int qemu_fwcfg_list_firmware(void) -{ - int ret; - struct list_head *entry; - struct fw_file *file; - - /* make sure fw_list is loaded */ - ret = qemu_fwcfg_read_firmware_list(); - if (ret) - return ret; - - list_for_each(entry, &fw_list) { - file = list_entry(entry, struct fw_file, list); - printf("%-56s\n", file->cfg.name); - } - - return 0; -} - -void qemu_fwcfg_init(void) -{ - fwcfg_present = qemu_fwcfg_present(); - if (fwcfg_present) - fwcfg_dma_present = qemu_fwcfg_dma_present(); -} - -static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) -{ - if (qemu_fwcfg_list_firmware() < 0) - return CMD_RET_FAILURE; - - return 0; -} - -static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) -{ - int ret = qemu_fwcfg_online_cpus(); - if (ret < 0) { - printf("QEMU fw_cfg interface not found\n"); - return CMD_RET_FAILURE; - } - - printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus()); - - return 0; -} - -static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) -{ - char *env; - void *load_addr; - void *initrd_addr; - - env = getenv("loadaddr"); - load_addr = env ? - (void *)simple_strtoul(env, NULL, 16) : - (void *)CONFIG_LOADADDR; - - env = getenv("ramdiskaddr"); - initrd_addr = env ? - (void *)simple_strtoul(env, NULL, 16) : - (void *)CONFIG_RAMDISK_ADDR; - - if (argc == 2) { - load_addr = (void *)simple_strtoul(argv[0], NULL, 16); - initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16); - } else if (argc == 1) { - load_addr = (void *)simple_strtoul(argv[0], NULL, 16); - } - - return qemu_fwcfg_setup_kernel(load_addr, initrd_addr); -} - -static cmd_tbl_t fwcfg_commands[] = { - U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""), - U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""), - U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""), -}; - -static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int ret; - cmd_tbl_t *fwcfg_cmd; - - if (!fwcfg_present) { - printf("QEMU fw_cfg interface not found\n"); - return CMD_RET_USAGE; - } - - fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands, - ARRAY_SIZE(fwcfg_commands)); - argc -= 2; - argv += 2; - if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs) - return CMD_RET_USAGE; - - ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv); - - return cmd_process_error(fwcfg_cmd, ret); -} - -U_BOOT_CMD( - qfw, 4, 1, do_qemu_fw, - "QEMU firmware interface", - "\n" - " - list : print firmware(s) currently loaded\n" - " - cpus : print online cpu number\n" - " - load : load kernel and initrd (if any), and setup for zboot\n" -) diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 7ad0ee49a19..b41e4ecbec2 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -6,12 +6,12 @@ #include #include +#include #include #include #include #include #include -#include static bool i440fx; diff --git a/arch/x86/include/asm/fw_cfg.h b/arch/x86/include/asm/fw_cfg.h deleted file mode 100644 index e9450c61968..00000000000 --- a/arch/x86/include/asm/fw_cfg.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2015 Miao Yan - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FW_CFG__ -#define __FW_CFG__ - -#define FW_CONTROL_PORT 0x510 -#define FW_DATA_PORT 0x511 -#define FW_DMA_PORT_LOW 0x514 -#define FW_DMA_PORT_HIGH 0x518 - -#include - -enum qemu_fwcfg_items { - FW_CFG_SIGNATURE = 0x00, - FW_CFG_ID = 0x01, - FW_CFG_UUID = 0x02, - FW_CFG_RAM_SIZE = 0x03, - FW_CFG_NOGRAPHIC = 0x04, - FW_CFG_NB_CPUS = 0x05, - FW_CFG_MACHINE_ID = 0x06, - FW_CFG_KERNEL_ADDR = 0x07, - FW_CFG_KERNEL_SIZE = 0x08, - FW_CFG_KERNEL_CMDLINE = 0x09, - FW_CFG_INITRD_ADDR = 0x0a, - FW_CFG_INITRD_SIZE = 0x0b, - FW_CFG_BOOT_DEVICE = 0x0c, - FW_CFG_NUMA = 0x0d, - FW_CFG_BOOT_MENU = 0x0e, - FW_CFG_MAX_CPUS = 0x0f, - FW_CFG_KERNEL_ENTRY = 0x10, - FW_CFG_KERNEL_DATA = 0x11, - FW_CFG_INITRD_DATA = 0x12, - FW_CFG_CMDLINE_ADDR = 0x13, - FW_CFG_CMDLINE_SIZE = 0x14, - FW_CFG_CMDLINE_DATA = 0x15, - FW_CFG_SETUP_ADDR = 0x16, - FW_CFG_SETUP_SIZE = 0x17, - FW_CFG_SETUP_DATA = 0x18, - FW_CFG_FILE_DIR = 0x19, - FW_CFG_FILE_FIRST = 0x20, - FW_CFG_WRITE_CHANNEL = 0x4000, - FW_CFG_ARCH_LOCAL = 0x8000, - FW_CFG_INVALID = 0xffff, -}; - -enum { - BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1, - BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2, - BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3, -}; - -enum { - BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1, - BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2, -}; - -#define FW_CFG_FILE_SLOTS 0x10 -#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS) -#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL) - -#define FW_CFG_MAX_FILE_PATH 56 -#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH - -#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U') - -#define FW_CFG_DMA_ERROR (1 << 0) -#define FW_CFG_DMA_READ (1 << 1) -#define FW_CFG_DMA_SKIP (1 << 2) -#define FW_CFG_DMA_SELECT (1 << 3) - -#define FW_CFG_DMA_ENABLED (1 << 1) - -struct fw_cfg_file { - __be32 size; - __be16 select; - __be16 reserved; - char name[FW_CFG_MAX_FILE_PATH]; -}; - -struct fw_file { - struct fw_cfg_file cfg; /* firmware file information */ - unsigned long addr; /* firmware file in-memory address */ - struct list_head list; /* list node to link to fw_list */ -}; - -struct fw_cfg_dma_access { - __be32 control; - __be32 length; - __be64 address; -}; - -struct bios_linker_entry { - __le32 command; - union { - /* - * COMMAND_ALLOCATE - allocate a table from @alloc.file - * subject to @alloc.align alignment (must be power of 2) - * and @alloc.zone (can be HIGH or FSEG) requirements. - * - * Must appear exactly once for each file, and before - * this file is referenced by any other command. - */ - struct { - char file[BIOS_LINKER_LOADER_FILESZ]; - __le32 align; - uint8_t zone; - } alloc; - - /* - * COMMAND_ADD_POINTER - patch the table (originating from - * @dest_file) at @pointer.offset, by adding a pointer to the - * table originating from @src_file. 1,2,4 or 8 byte unsigned - * addition is used depending on @pointer.size. - */ - struct { - char dest_file[BIOS_LINKER_LOADER_FILESZ]; - char src_file[BIOS_LINKER_LOADER_FILESZ]; - __le32 offset; - uint8_t size; - } pointer; - - /* - * COMMAND_ADD_CHECKSUM - calculate checksum of the range - * specified by @cksum_start and @cksum_length fields, - * and then add the value at @cksum.offset. - * Checksum simply sums -X for each byte X in the range - * using 8-bit math. - */ - struct { - char file[BIOS_LINKER_LOADER_FILESZ]; - __le32 offset; - __le32 start; - __le32 length; - } cksum; - - /* padding */ - char pad[124]; - }; -} __packed; - -/** - * Initialize QEMU fw_cfg interface - */ -void qemu_fwcfg_init(void); - -/** - * Get system cpu number - * - * @return: cpu number in system - */ -int qemu_fwcfg_online_cpus(void); - -#endif diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 989cf7d5de0..be7b8245258 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -303,7 +303,7 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg) /* * QEMU's version of write_acpi_tables is defined in - * arch/x86/cpu/qemu/fw_cfg.c + * arch/x86/cpu/qemu/acpi_table.c */ u32 write_acpi_tables(u32 start) { diff --git a/cmd/Kconfig b/cmd/Kconfig index 93367521286..c0fffe305c0 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -593,6 +593,13 @@ config CMD_SOUND sound init - set up sound system sound play - play a sound +config CMD_QEMU_FW_CFG + bool "qfw" + depends on X86 + help + This provides access to the QEMU firmware interface. The main + feature is to allow easy loading of files passed to qemu-system + via -kernel / -initrd endmenu config CMD_BOOTSTAGE diff --git a/cmd/Makefile b/cmd/Makefile index e3e0c74ffc6..d4432c84d9a 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -105,6 +105,7 @@ endif obj-y += pcmcia.o obj-$(CONFIG_CMD_PORTIO) += portio.o obj-$(CONFIG_CMD_PXE) += pxe.o +obj-$(CONFIG_CMD_QEMU_FW_CFG) += qemu_fw_cfg.o obj-$(CONFIG_CMD_READ) += read.o obj-$(CONFIG_CMD_REGINFO) += reginfo.o obj-$(CONFIG_CMD_REISER) += reiser.o diff --git a/cmd/qemu_fw_cfg.c b/cmd/qemu_fw_cfg.c new file mode 100644 index 00000000000..48ae47683f9 --- /dev/null +++ b/cmd/qemu_fw_cfg.c @@ -0,0 +1,343 @@ +/* + * (C) Copyright 2015 Miao Yan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +static bool fwcfg_present; +static bool fwcfg_dma_present; + +static LIST_HEAD(fw_list); + +/* Read configuration item using fw_cfg PIO interface */ +static void qemu_fwcfg_read_entry_pio(uint16_t entry, + uint32_t size, void *address) +{ + uint32_t i = 0; + uint8_t *data = address; + + /* + * writting FW_CFG_INVALID will cause read operation to resume at + * last offset, otherwise read will start at offset 0 + */ + if (entry != FW_CFG_INVALID) + outw(entry, FW_CONTROL_PORT); + while (size--) + data[i++] = inb(FW_DATA_PORT); +} + +/* Read configuration item using fw_cfg DMA interface */ +static void qemu_fwcfg_read_entry_dma(uint16_t entry, + uint32_t size, void *address) +{ + struct fw_cfg_dma_access dma; + + dma.length = cpu_to_be32(size); + dma.address = cpu_to_be64((uintptr_t)address); + dma.control = cpu_to_be32(FW_CFG_DMA_READ); + + /* + * writting FW_CFG_INVALID will cause read operation to resume at + * last offset, otherwise read will start at offset 0 + */ + if (entry != FW_CFG_INVALID) + dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16)); + + barrier(); + + debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n", + address, size, be32_to_cpu(dma.control)); + + outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH); + + while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR) + __asm__ __volatile__ ("pause"); +} + +static bool qemu_fwcfg_present(void) +{ + uint32_t qemu; + + qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu); + return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE; +} + +static bool qemu_fwcfg_dma_present(void) +{ + uint8_t dma_enabled; + + qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled); + if (dma_enabled & FW_CFG_DMA_ENABLED) + return true; + + return false; +} + +void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address) +{ + if (fwcfg_dma_present) + qemu_fwcfg_read_entry_dma(entry, length, address); + else + qemu_fwcfg_read_entry_pio(entry, length, address); +} + +int qemu_fwcfg_online_cpus(void) +{ + uint16_t nb_cpus; + + if (!fwcfg_present) + return -ENODEV; + + qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus); + + return le16_to_cpu(nb_cpus); +} + +/* + * This function prepares kernel for zboot. It loads kernel data + * to 'load_addr', initrd to 'initrd_addr' and kernel command + * line using qemu fw_cfg interface. + */ +static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr) +{ + char *data_addr; + uint32_t setup_size, kernel_size, cmdline_size, initrd_size; + + qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size); + qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size); + + if (setup_size == 0 || kernel_size == 0) { + printf("warning: no kernel available\n"); + return -1; + } + + data_addr = load_addr; + qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA, + le32_to_cpu(setup_size), data_addr); + data_addr += le32_to_cpu(setup_size); + + qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA, + le32_to_cpu(kernel_size), data_addr); + data_addr += le32_to_cpu(kernel_size); + + data_addr = initrd_addr; + qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size); + if (initrd_size == 0) { + printf("warning: no initrd available\n"); + } else { + qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA, + le32_to_cpu(initrd_size), data_addr); + data_addr += le32_to_cpu(initrd_size); + } + + qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size); + if (cmdline_size) { + qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA, + le32_to_cpu(cmdline_size), data_addr); + /* + * if kernel cmdline only contains '\0', (e.g. no -append + * when invoking qemu), do not update bootargs + */ + if (*data_addr != '\0') { + if (setenv("bootargs", data_addr) < 0) + printf("warning: unable to change bootargs\n"); + } + } + + printf("loading kernel to address %p size %x", load_addr, + le32_to_cpu(kernel_size)); + if (initrd_size) + printf(" initrd %p size %x\n", + initrd_addr, + le32_to_cpu(initrd_size)); + else + printf("\n"); + + return 0; +} + +int qemu_fwcfg_read_firmware_list(void) +{ + int i; + uint32_t count; + struct fw_file *file; + struct list_head *entry; + + /* don't read it twice */ + if (!list_empty(&fw_list)) + return 0; + + qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count); + if (!count) + return 0; + + count = be32_to_cpu(count); + for (i = 0; i < count; i++) { + file = malloc(sizeof(*file)); + if (!file) { + printf("error: allocating resource\n"); + goto err; + } + qemu_fwcfg_read_entry(FW_CFG_INVALID, + sizeof(struct fw_cfg_file), &file->cfg); + file->addr = 0; + list_add_tail(&file->list, &fw_list); + } + + return 0; + +err: + list_for_each(entry, &fw_list) { + file = list_entry(entry, struct fw_file, list); + free(file); + } + + return -ENOMEM; +} + +struct fw_file *qemu_fwcfg_find_file(const char *name) +{ + struct list_head *entry; + struct fw_file *file; + + list_for_each(entry, &fw_list) { + file = list_entry(entry, struct fw_file, list); + if (!strcmp(file->cfg.name, name)) + return file; + } + + return NULL; +} + +void qemu_fwcfg_free_files(void) +{ + struct fw_file *file; + struct list_head *list; + + list_for_each(list, &fw_list) { + file = list_entry(list, struct fw_file, list); + if (file->addr) + free((void *)file->addr); + } +} + +static int qemu_fwcfg_list_firmware(void) +{ + int ret; + struct list_head *entry; + struct fw_file *file; + + /* make sure fw_list is loaded */ + ret = qemu_fwcfg_read_firmware_list(); + if (ret) + return ret; + + list_for_each(entry, &fw_list) { + file = list_entry(entry, struct fw_file, list); + printf("%-56s\n", file->cfg.name); + } + + return 0; +} + +void qemu_fwcfg_init(void) +{ + fwcfg_present = qemu_fwcfg_present(); + if (fwcfg_present) + fwcfg_dma_present = qemu_fwcfg_dma_present(); +} + +static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + if (qemu_fwcfg_list_firmware() < 0) + return CMD_RET_FAILURE; + + return 0; +} + +static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int ret = qemu_fwcfg_online_cpus(); + if (ret < 0) { + printf("QEMU fw_cfg interface not found\n"); + return CMD_RET_FAILURE; + } + + printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus()); + + return 0; +} + +static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + char *env; + void *load_addr; + void *initrd_addr; + + env = getenv("loadaddr"); + load_addr = env ? + (void *)simple_strtoul(env, NULL, 16) : + (void *)CONFIG_LOADADDR; + + env = getenv("ramdiskaddr"); + initrd_addr = env ? + (void *)simple_strtoul(env, NULL, 16) : + (void *)CONFIG_RAMDISK_ADDR; + + if (argc == 2) { + load_addr = (void *)simple_strtoul(argv[0], NULL, 16); + initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16); + } else if (argc == 1) { + load_addr = (void *)simple_strtoul(argv[0], NULL, 16); + } + + return qemu_fwcfg_setup_kernel(load_addr, initrd_addr); +} + +static cmd_tbl_t fwcfg_commands[] = { + U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""), + U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""), + U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""), +}; + +static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret; + cmd_tbl_t *fwcfg_cmd; + + if (!fwcfg_present) { + printf("QEMU fw_cfg interface not found\n"); + return CMD_RET_USAGE; + } + + fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands, + ARRAY_SIZE(fwcfg_commands)); + argc -= 2; + argv += 2; + if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs) + return CMD_RET_USAGE; + + ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv); + + return cmd_process_error(fwcfg_cmd, ret); +} + +U_BOOT_CMD( + qfw, 4, 1, do_qemu_fw, + "QEMU firmware interface", + "\n" + " - list : print firmware(s) currently loaded\n" + " - cpus : print online cpu number\n" + " - load : load kernel and initrd (if any), and setup for zboot\n" +) diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 53b1ff65afd..a813e5b4389 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_PING=y CONFIG_CMD_TIME=y +CONFIG_CMD_QEMU_FW_CFG=y CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y diff --git a/include/qemu_fw_cfg.h b/include/qemu_fw_cfg.h new file mode 100644 index 00000000000..e21f1503c0e --- /dev/null +++ b/include/qemu_fw_cfg.h @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2015 Miao Yan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FW_CFG__ +#define __FW_CFG__ + +#define FW_CONTROL_PORT 0x510 +#define FW_DATA_PORT 0x511 +#define FW_DMA_PORT_LOW 0x514 +#define FW_DMA_PORT_HIGH 0x518 + +#include + +enum qemu_fwcfg_items { + FW_CFG_SIGNATURE = 0x00, + FW_CFG_ID = 0x01, + FW_CFG_UUID = 0x02, + FW_CFG_RAM_SIZE = 0x03, + FW_CFG_NOGRAPHIC = 0x04, + FW_CFG_NB_CPUS = 0x05, + FW_CFG_MACHINE_ID = 0x06, + FW_CFG_KERNEL_ADDR = 0x07, + FW_CFG_KERNEL_SIZE = 0x08, + FW_CFG_KERNEL_CMDLINE = 0x09, + FW_CFG_INITRD_ADDR = 0x0a, + FW_CFG_INITRD_SIZE = 0x0b, + FW_CFG_BOOT_DEVICE = 0x0c, + FW_CFG_NUMA = 0x0d, + FW_CFG_BOOT_MENU = 0x0e, + FW_CFG_MAX_CPUS = 0x0f, + FW_CFG_KERNEL_ENTRY = 0x10, + FW_CFG_KERNEL_DATA = 0x11, + FW_CFG_INITRD_DATA = 0x12, + FW_CFG_CMDLINE_ADDR = 0x13, + FW_CFG_CMDLINE_SIZE = 0x14, + FW_CFG_CMDLINE_DATA = 0x15, + FW_CFG_SETUP_ADDR = 0x16, + FW_CFG_SETUP_SIZE = 0x17, + FW_CFG_SETUP_DATA = 0x18, + FW_CFG_FILE_DIR = 0x19, + FW_CFG_FILE_FIRST = 0x20, + FW_CFG_WRITE_CHANNEL = 0x4000, + FW_CFG_ARCH_LOCAL = 0x8000, + FW_CFG_INVALID = 0xffff, +}; + +enum { + BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1, + BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2, + BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3, +}; + +enum { + BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1, + BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2, +}; + +#define FW_CFG_FILE_SLOTS 0x10 +#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS) +#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL) + +#define FW_CFG_MAX_FILE_PATH 56 +#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH + +#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U') + +#define FW_CFG_DMA_ERROR (1 << 0) +#define FW_CFG_DMA_READ (1 << 1) +#define FW_CFG_DMA_SKIP (1 << 2) +#define FW_CFG_DMA_SELECT (1 << 3) + +#define FW_CFG_DMA_ENABLED (1 << 1) + +struct fw_cfg_file { + __be32 size; + __be16 select; + __be16 reserved; + char name[FW_CFG_MAX_FILE_PATH]; +}; + +struct fw_file { + struct fw_cfg_file cfg; /* firmware file information */ + unsigned long addr; /* firmware file in-memory address */ + struct list_head list; /* list node to link to fw_list */ +}; + +struct fw_cfg_dma_access { + __be32 control; + __be32 length; + __be64 address; +}; + +struct bios_linker_entry { + __le32 command; + union { + /* + * COMMAND_ALLOCATE - allocate a table from @alloc.file + * subject to @alloc.align alignment (must be power of 2) + * and @alloc.zone (can be HIGH or FSEG) requirements. + * + * Must appear exactly once for each file, and before + * this file is referenced by any other command. + */ + struct { + char file[BIOS_LINKER_LOADER_FILESZ]; + __le32 align; + uint8_t zone; + } alloc; + + /* + * COMMAND_ADD_POINTER - patch the table (originating from + * @dest_file) at @pointer.offset, by adding a pointer to the + * table originating from @src_file. 1,2,4 or 8 byte unsigned + * addition is used depending on @pointer.size. + */ + struct { + char dest_file[BIOS_LINKER_LOADER_FILESZ]; + char src_file[BIOS_LINKER_LOADER_FILESZ]; + __le32 offset; + uint8_t size; + } pointer; + + /* + * COMMAND_ADD_CHECKSUM - calculate checksum of the range + * specified by @cksum_start and @cksum_length fields, + * and then add the value at @cksum.offset. + * Checksum simply sums -X for each byte X in the range + * using 8-bit math. + */ + struct { + char file[BIOS_LINKER_LOADER_FILESZ]; + __le32 offset; + __le32 start; + __le32 length; + } cksum; + + /* padding */ + char pad[124]; + }; +} __packed; + +/** + * Initialize QEMU fw_cfg interface + */ +void qemu_fwcfg_init(void); + +void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address); +int qemu_fwcfg_read_firmware_list(void); +struct fw_file *qemu_fwcfg_find_file(const char *name); +void qemu_fwcfg_free_files(void); + +/** + * Get system cpu number + * + * @return: cpu number in system + */ +int qemu_fwcfg_online_cpus(void); + +#endif -- cgit v1.3.1 From 099b2196e4a693968fd6205ac6d61f6eaab79fb1 Mon Sep 17 00:00:00 2001 From: Miao Yan Date: Sun, 22 May 2016 19:37:11 -0700 Subject: cmd: qfw: add API to iterate firmware list This patch is part of the refactor work of qfw. It adds 3 APIs to qfw core to iterate firmware list. Signed-off-by: Miao Yan Reviewed-by: Bin Meng --- cmd/qemu_fw_cfg.c | 25 ++++++++++++++++++++++--- include/qemu_fw_cfg.h | 9 +++++++++ 2 files changed, 31 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/cmd/qemu_fw_cfg.c b/cmd/qemu_fw_cfg.c index 48ae47683f9..192b7d18d81 100644 --- a/cmd/qemu_fw_cfg.c +++ b/cmd/qemu_fw_cfg.c @@ -229,10 +229,27 @@ void qemu_fwcfg_free_files(void) } } +struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter) +{ + iter->entry = fw_list.next; + return list_entry(iter->entry, struct fw_file, list); +} + +struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter) +{ + iter->entry = iter->entry->next; + return list_entry(iter->entry, struct fw_file, list); +} + +bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter) +{ + return iter->entry == &fw_list; +} + static int qemu_fwcfg_list_firmware(void) { int ret; - struct list_head *entry; + struct fw_cfg_file_iter iter; struct fw_file *file; /* make sure fw_list is loaded */ @@ -240,8 +257,10 @@ static int qemu_fwcfg_list_firmware(void) if (ret) return ret; - list_for_each(entry, &fw_list) { - file = list_entry(entry, struct fw_file, list); + + for (file = qemu_fwcfg_file_iter_init(&iter); + !qemu_fwcfg_file_iter_end(&iter); + file = qemu_fwcfg_file_iter_next(&iter)) { printf("%-56s\n", file->cfg.name); } diff --git a/include/qemu_fw_cfg.h b/include/qemu_fw_cfg.h index e21f1503c0e..19d0ba08b4c 100644 --- a/include/qemu_fw_cfg.h +++ b/include/qemu_fw_cfg.h @@ -87,6 +87,10 @@ struct fw_file { struct list_head list; /* list node to link to fw_list */ }; +struct fw_cfg_file_iter { + struct list_head *entry; /* structure to iterate file list */ +}; + struct fw_cfg_dma_access { __be32 control; __be32 length; @@ -159,4 +163,9 @@ void qemu_fwcfg_free_files(void); */ int qemu_fwcfg_online_cpus(void); +/* helper functions to iterate firmware file list */ +struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter); +struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter); +bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter); + #endif -- cgit v1.3.1 From 05dd6f183c8c20f0176a67ac885f8143c0052203 Mon Sep 17 00:00:00 2001 From: Miao Yan Date: Sun, 22 May 2016 19:37:12 -0700 Subject: cmd: qfw: remove qemu_fwcfg_free_files() This patch is part of the qfw refactor work. The qemu_fwcfg_free_files() function is only used in error handling in ACPI table generation, let's not make this a core function and move it to the right place. Signed-off-by: Miao Yan Reviewed-by: Bin Meng --- arch/x86/cpu/qemu/acpi_table.c | 13 +++++++++++-- cmd/qemu_fw_cfg.c | 12 ------------ include/qemu_fw_cfg.h | 1 - 3 files changed, 11 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/arch/x86/cpu/qemu/acpi_table.c b/arch/x86/cpu/qemu/acpi_table.c index 49381acd29f..b17fa03bc89 100644 --- a/arch/x86/cpu/qemu/acpi_table.c +++ b/arch/x86/cpu/qemu/acpi_table.c @@ -235,8 +235,17 @@ u32 write_acpi_tables(u32 addr) } out: - if (ret) - qemu_fwcfg_free_files(); + if (ret) { + struct fw_cfg_file_iter iter; + for (file = qemu_fwcfg_file_iter_init(&iter); + !qemu_fwcfg_file_iter_end(&iter); + file = qemu_fwcfg_file_iter_next(&iter)) { + if (file->addr) { + free((void *)file->addr); + file->addr = 0; + } + } + } free(table_loader); return addr; diff --git a/cmd/qemu_fw_cfg.c b/cmd/qemu_fw_cfg.c index 192b7d18d81..9f03ab60ab1 100644 --- a/cmd/qemu_fw_cfg.c +++ b/cmd/qemu_fw_cfg.c @@ -217,18 +217,6 @@ struct fw_file *qemu_fwcfg_find_file(const char *name) return NULL; } -void qemu_fwcfg_free_files(void) -{ - struct fw_file *file; - struct list_head *list; - - list_for_each(list, &fw_list) { - file = list_entry(list, struct fw_file, list); - if (file->addr) - free((void *)file->addr); - } -} - struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter) { iter->entry = fw_list.next; diff --git a/include/qemu_fw_cfg.h b/include/qemu_fw_cfg.h index 19d0ba08b4c..986f4b2e5ac 100644 --- a/include/qemu_fw_cfg.h +++ b/include/qemu_fw_cfg.h @@ -154,7 +154,6 @@ void qemu_fwcfg_init(void); void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address); int qemu_fwcfg_read_firmware_list(void); struct fw_file *qemu_fwcfg_find_file(const char *name); -void qemu_fwcfg_free_files(void); /** * Get system cpu number -- cgit v1.3.1 From d3ad06239291d89c1c598248d577cde5470ac1ee Mon Sep 17 00:00:00 2001 From: Miao Yan Date: Sun, 22 May 2016 19:37:13 -0700 Subject: cmd: qfw: make fwcfg_present and fwcfg_dma_present public This patch is part of the qfw refactor work. This patch makes qemu_fwcfg_present() and qemu_fwcfg_dma_present() public functions. Signed-off-by: Miao Yan Reviewed-by: Bin Meng --- cmd/qemu_fw_cfg.c | 37 ++++++++++++++++++++----------------- include/qemu_fw_cfg.h | 3 +++ 2 files changed, 23 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/cmd/qemu_fw_cfg.c b/cmd/qemu_fw_cfg.c index 9f03ab60ab1..aab6b1a4526 100644 --- a/cmd/qemu_fw_cfg.c +++ b/cmd/qemu_fw_cfg.c @@ -62,23 +62,14 @@ static void qemu_fwcfg_read_entry_dma(uint16_t entry, __asm__ __volatile__ ("pause"); } -static bool qemu_fwcfg_present(void) +bool qemu_fwcfg_present(void) { - uint32_t qemu; - - qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu); - return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE; + return fwcfg_present; } -static bool qemu_fwcfg_dma_present(void) +bool qemu_fwcfg_dma_present(void) { - uint8_t dma_enabled; - - qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled); - if (dma_enabled & FW_CFG_DMA_ENABLED) - return true; - - return false; + return fwcfg_dma_present; } void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address) @@ -257,9 +248,21 @@ static int qemu_fwcfg_list_firmware(void) void qemu_fwcfg_init(void) { - fwcfg_present = qemu_fwcfg_present(); - if (fwcfg_present) - fwcfg_dma_present = qemu_fwcfg_dma_present(); + uint32_t qemu; + uint32_t dma_enabled; + + fwcfg_present = false; + fwcfg_dma_present = false; + + qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu); + if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE) + fwcfg_present = true; + + if (fwcfg_present) { + qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled); + if (dma_enabled & FW_CFG_DMA_ENABLED) + fwcfg_dma_present = true; + } } static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag, @@ -323,7 +326,7 @@ static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int ret; cmd_tbl_t *fwcfg_cmd; - if (!fwcfg_present) { + if (!qemu_fwcfg_present()) { printf("QEMU fw_cfg interface not found\n"); return CMD_RET_USAGE; } diff --git a/include/qemu_fw_cfg.h b/include/qemu_fw_cfg.h index 986f4b2e5ac..f718e09e315 100644 --- a/include/qemu_fw_cfg.h +++ b/include/qemu_fw_cfg.h @@ -167,4 +167,7 @@ struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter); struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter); bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter); +bool qemu_fwcfg_present(void); +bool qemu_fwcfg_dma_present(void); + #endif -- cgit v1.3.1 From 2e82e745a4cf6bad10d9fe5a53db6592f40ff903 Mon Sep 17 00:00:00 2001 From: Miao Yan Date: Sun, 22 May 2016 19:37:15 -0700 Subject: x86: qemu: move x86 specific operations out of qfw core The original implementation of qfw includes several x86 specific operations, like directly calling outb/inb and using some inline assembly code which prevents it being ported to other architectures. This patch adds callback functions and moves those to arch/x86/ Signed-off-by: Miao Yan Reviewed-by: Bin Meng --- arch/x86/cpu/qemu/qemu.c | 39 ++++++++++++++++++++++++++++++++++++++- drivers/misc/qemu_fw_cfg.c | 30 +++++++++++++----------------- include/qemu_fw_cfg.h | 15 +++++++++------ 3 files changed, 60 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 32a43518744..6ff99474bfc 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -15,6 +15,43 @@ static bool i440fx; +#ifdef CONFIG_QFW + +#define FW_CONTROL_PORT 0x510 +#define FW_DATA_PORT 0x511 +#define FW_DMA_PORT_LOW 0x514 +#define FW_DMA_PORT_HIGH 0x518 + +static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry, + uint32_t size, void *address) +{ + uint32_t i = 0; + uint8_t *data = address; + + /* + * writting FW_CFG_INVALID will cause read operation to resume at + * last offset, otherwise read will start at offset 0 + */ + if (entry != FW_CFG_INVALID) + outw(entry, FW_CONTROL_PORT); + while (size--) + data[i++] = inb(FW_DATA_PORT); +} + +static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma) +{ + outl(cpu_to_be32((uint32_t)dma), FW_DMA_PORT_HIGH); + + while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR) + __asm__ __volatile__ ("pause"); +} + +static struct fw_cfg_arch_ops fwcfg_x86_ops = { + .arch_read_pio = qemu_x86_fwcfg_read_entry_pio, + .arch_read_dma = qemu_x86_fwcfg_read_entry_dma +}; +#endif + static void enable_pm_piix(void) { u8 en; @@ -89,7 +126,7 @@ static void qemu_chipset_init(void) } #ifdef CONFIG_QFW - qemu_fwcfg_init(); + qemu_fwcfg_init(&fwcfg_x86_ops); #endif } diff --git a/drivers/misc/qemu_fw_cfg.c b/drivers/misc/qemu_fw_cfg.c index a574bd1ec18..0f72549321c 100644 --- a/drivers/misc/qemu_fw_cfg.c +++ b/drivers/misc/qemu_fw_cfg.c @@ -14,6 +14,7 @@ static bool fwcfg_present; static bool fwcfg_dma_present; +static struct fw_cfg_arch_ops *fwcfg_arch_ops; static LIST_HEAD(fw_list); @@ -21,17 +22,10 @@ static LIST_HEAD(fw_list); static void qemu_fwcfg_read_entry_pio(uint16_t entry, uint32_t size, void *address) { - uint32_t i = 0; - uint8_t *data = address; + debug("qemu_fwcfg_read_entry_pio: entry 0x%x, size %u address %p\n", + entry, size, address); - /* - * writting FW_CFG_INVALID will cause read operation to resume at - * last offset, otherwise read will start at offset 0 - */ - if (entry != FW_CFG_INVALID) - outw(entry, FW_CONTROL_PORT); - while (size--) - data[i++] = inb(FW_DATA_PORT); + return fwcfg_arch_ops->arch_read_pio(entry, size, address); } /* Read configuration item using fw_cfg DMA interface */ @@ -53,13 +47,10 @@ static void qemu_fwcfg_read_entry_dma(uint16_t entry, barrier(); - debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n", - address, size, be32_to_cpu(dma.control)); - - outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH); + debug("qemu_fwcfg_read_entry_dma: entry 0x%x, size %u address %p, control 0x%x\n", + entry, size, address, be32_to_cpu(dma.control)); - while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR) - __asm__ __volatile__ ("pause"); + fwcfg_arch_ops->arch_read_dma(&dma); } bool qemu_fwcfg_present(void) @@ -164,13 +155,18 @@ bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter) return iter->entry == &fw_list; } -void qemu_fwcfg_init(void) +void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops) { uint32_t qemu; uint32_t dma_enabled; fwcfg_present = false; fwcfg_dma_present = false; + fwcfg_arch_ops = NULL; + + if (!ops || !ops->arch_read_pio || !ops->arch_read_dma) + return; + fwcfg_arch_ops = ops; qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu); if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE) diff --git a/include/qemu_fw_cfg.h b/include/qemu_fw_cfg.h index f718e09e315..b0b3b5945ef 100644 --- a/include/qemu_fw_cfg.h +++ b/include/qemu_fw_cfg.h @@ -7,11 +7,6 @@ #ifndef __FW_CFG__ #define __FW_CFG__ -#define FW_CONTROL_PORT 0x510 -#define FW_DATA_PORT 0x511 -#define FW_DMA_PORT_LOW 0x514 -#define FW_DMA_PORT_HIGH 0x518 - #include enum qemu_fwcfg_items { @@ -97,6 +92,12 @@ struct fw_cfg_dma_access { __be64 address; }; +struct fw_cfg_arch_ops { + void (*arch_read_pio)(uint16_t selector, uint32_t size, + void *address); + void (*arch_read_dma)(struct fw_cfg_dma_access *dma); +}; + struct bios_linker_entry { __le32 command; union { @@ -148,8 +149,10 @@ struct bios_linker_entry { /** * Initialize QEMU fw_cfg interface + * + * @ops: arch specific read operations */ -void qemu_fwcfg_init(void); +void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops); void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address); int qemu_fwcfg_read_firmware_list(void); -- cgit v1.3.1 From 1868659002a6b7ab3b1da7be74f53d3e10e915be Mon Sep 17 00:00:00 2001 From: Miao Yan Date: Sun, 22 May 2016 19:37:17 -0700 Subject: cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h] Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW Signed-off-by: Miao Yan Reviewed-by: Bin Meng --- arch/x86/cpu/mp_init.c | 2 +- arch/x86/cpu/qemu/acpi_table.c | 2 +- arch/x86/cpu/qemu/cpu.c | 2 +- arch/x86/cpu/qemu/qemu.c | 2 +- cmd/Kconfig | 2 +- cmd/Makefile | 2 +- cmd/qfw.c | 2 +- configs/qemu-x86_defconfig | 2 +- drivers/misc/Kconfig | 2 +- drivers/misc/Makefile | 2 +- drivers/misc/qemu_fw_cfg.c | 180 ----------------------------------------- drivers/misc/qfw.c | 180 +++++++++++++++++++++++++++++++++++++++++ include/qemu_fw_cfg.h | 176 ---------------------------------------- include/qfw.h | 176 ++++++++++++++++++++++++++++++++++++++++ 14 files changed, 366 insertions(+), 366 deletions(-) delete mode 100644 drivers/misc/qemu_fw_cfg.c create mode 100644 drivers/misc/qfw.c delete mode 100644 include/qemu_fw_cfg.h create mode 100644 include/qfw.h (limited to 'include') diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index c44a286e5bb..8207274879c 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/x86/cpu/qemu/acpi_table.c b/arch/x86/cpu/qemu/acpi_table.c index b17fa03bc89..5bb1756c530 100644 --- a/arch/x86/cpu/qemu/acpi_table.c +++ b/arch/x86/cpu/qemu/acpi_table.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c index 4d2989a7084..b1a965e7156 100644 --- a/arch/x86/cpu/qemu/cpu.c +++ b/arch/x86/cpu/qemu/cpu.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index c29add39b26..680e558ee8b 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -6,7 +6,7 @@ #include #include -#include +#include #include #include #include diff --git a/cmd/Kconfig b/cmd/Kconfig index 08b761f6db9..c5a7a590644 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -593,7 +593,7 @@ config CMD_SOUND sound init - set up sound system sound play - play a sound -config CMD_QEMU_FW_CFG +config CMD_QFW bool "qfw" depends on X86 select QFW diff --git a/cmd/Makefile b/cmd/Makefile index ff4fc5b98e8..9ce7861f822 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -105,7 +105,7 @@ endif obj-y += pcmcia.o obj-$(CONFIG_CMD_PORTIO) += portio.o obj-$(CONFIG_CMD_PXE) += pxe.o -obj-$(CONFIG_CMD_QEMU_FW_CFG) += qfw.o +obj-$(CONFIG_CMD_QFW) += qfw.o obj-$(CONFIG_CMD_READ) += read.o obj-$(CONFIG_CMD_REGINFO) += reginfo.o obj-$(CONFIG_CMD_REISER) += reiser.o diff --git a/cmd/qfw.c b/cmd/qfw.c index 37f1aa6fc7b..c6730bf2d3e 100644 --- a/cmd/qfw.c +++ b/cmd/qfw.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include /* * This function prepares kernel for zboot. It loads kernel data diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index a813e5b4389..45bb3ec0e9e 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -20,7 +20,7 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_PING=y CONFIG_CMD_TIME=y -CONFIG_CMD_QEMU_FW_CFG=y +CONFIG_CMD_QFW=y CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index fa537002d4b..c40f6b577f3 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -142,6 +142,6 @@ config QFW bool help Hidden option to enable QEMU fw_cfg interface. This will be selected by - either CONFIG_CMD_QEMU_FW_CFG or CONFIG_GENERATE_ACPI_TABLE. + either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 4893086b72c..98704f2085d 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -43,4 +43,4 @@ obj-$(CONFIG_PCA9551_LED) += pca9551_led.o obj-$(CONFIG_RESET) += reset-uclass.o obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o -obj-$(CONFIG_QFW) += qemu_fw_cfg.o +obj-$(CONFIG_QFW) += qfw.o diff --git a/drivers/misc/qemu_fw_cfg.c b/drivers/misc/qemu_fw_cfg.c deleted file mode 100644 index 0f72549321c..00000000000 --- a/drivers/misc/qemu_fw_cfg.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2015 Miao Yan - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -static bool fwcfg_present; -static bool fwcfg_dma_present; -static struct fw_cfg_arch_ops *fwcfg_arch_ops; - -static LIST_HEAD(fw_list); - -/* Read configuration item using fw_cfg PIO interface */ -static void qemu_fwcfg_read_entry_pio(uint16_t entry, - uint32_t size, void *address) -{ - debug("qemu_fwcfg_read_entry_pio: entry 0x%x, size %u address %p\n", - entry, size, address); - - return fwcfg_arch_ops->arch_read_pio(entry, size, address); -} - -/* Read configuration item using fw_cfg DMA interface */ -static void qemu_fwcfg_read_entry_dma(uint16_t entry, - uint32_t size, void *address) -{ - struct fw_cfg_dma_access dma; - - dma.length = cpu_to_be32(size); - dma.address = cpu_to_be64((uintptr_t)address); - dma.control = cpu_to_be32(FW_CFG_DMA_READ); - - /* - * writting FW_CFG_INVALID will cause read operation to resume at - * last offset, otherwise read will start at offset 0 - */ - if (entry != FW_CFG_INVALID) - dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16)); - - barrier(); - - debug("qemu_fwcfg_read_entry_dma: entry 0x%x, size %u address %p, control 0x%x\n", - entry, size, address, be32_to_cpu(dma.control)); - - fwcfg_arch_ops->arch_read_dma(&dma); -} - -bool qemu_fwcfg_present(void) -{ - return fwcfg_present; -} - -bool qemu_fwcfg_dma_present(void) -{ - return fwcfg_dma_present; -} - -void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address) -{ - if (fwcfg_dma_present) - qemu_fwcfg_read_entry_dma(entry, length, address); - else - qemu_fwcfg_read_entry_pio(entry, length, address); -} - -int qemu_fwcfg_online_cpus(void) -{ - uint16_t nb_cpus; - - if (!fwcfg_present) - return -ENODEV; - - qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus); - - return le16_to_cpu(nb_cpus); -} - -int qemu_fwcfg_read_firmware_list(void) -{ - int i; - uint32_t count; - struct fw_file *file; - struct list_head *entry; - - /* don't read it twice */ - if (!list_empty(&fw_list)) - return 0; - - qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count); - if (!count) - return 0; - - count = be32_to_cpu(count); - for (i = 0; i < count; i++) { - file = malloc(sizeof(*file)); - if (!file) { - printf("error: allocating resource\n"); - goto err; - } - qemu_fwcfg_read_entry(FW_CFG_INVALID, - sizeof(struct fw_cfg_file), &file->cfg); - file->addr = 0; - list_add_tail(&file->list, &fw_list); - } - - return 0; - -err: - list_for_each(entry, &fw_list) { - file = list_entry(entry, struct fw_file, list); - free(file); - } - - return -ENOMEM; -} - -struct fw_file *qemu_fwcfg_find_file(const char *name) -{ - struct list_head *entry; - struct fw_file *file; - - list_for_each(entry, &fw_list) { - file = list_entry(entry, struct fw_file, list); - if (!strcmp(file->cfg.name, name)) - return file; - } - - return NULL; -} - -struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter) -{ - iter->entry = fw_list.next; - return list_entry((struct list_head *)iter->entry, - struct fw_file, list); -} - -struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter) -{ - iter->entry = ((struct list_head *)iter->entry)->next; - return list_entry((struct list_head *)iter->entry, - struct fw_file, list); -} - -bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter) -{ - return iter->entry == &fw_list; -} - -void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops) -{ - uint32_t qemu; - uint32_t dma_enabled; - - fwcfg_present = false; - fwcfg_dma_present = false; - fwcfg_arch_ops = NULL; - - if (!ops || !ops->arch_read_pio || !ops->arch_read_dma) - return; - fwcfg_arch_ops = ops; - - qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu); - if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE) - fwcfg_present = true; - - if (fwcfg_present) { - qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled); - if (dma_enabled & FW_CFG_DMA_ENABLED) - fwcfg_dma_present = true; - } -} diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c new file mode 100644 index 00000000000..59d9376d768 --- /dev/null +++ b/drivers/misc/qfw.c @@ -0,0 +1,180 @@ +/* + * (C) Copyright 2015 Miao Yan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +static bool fwcfg_present; +static bool fwcfg_dma_present; +static struct fw_cfg_arch_ops *fwcfg_arch_ops; + +static LIST_HEAD(fw_list); + +/* Read configuration item using fw_cfg PIO interface */ +static void qemu_fwcfg_read_entry_pio(uint16_t entry, + uint32_t size, void *address) +{ + debug("qemu_fwcfg_read_entry_pio: entry 0x%x, size %u address %p\n", + entry, size, address); + + return fwcfg_arch_ops->arch_read_pio(entry, size, address); +} + +/* Read configuration item using fw_cfg DMA interface */ +static void qemu_fwcfg_read_entry_dma(uint16_t entry, + uint32_t size, void *address) +{ + struct fw_cfg_dma_access dma; + + dma.length = cpu_to_be32(size); + dma.address = cpu_to_be64((uintptr_t)address); + dma.control = cpu_to_be32(FW_CFG_DMA_READ); + + /* + * writting FW_CFG_INVALID will cause read operation to resume at + * last offset, otherwise read will start at offset 0 + */ + if (entry != FW_CFG_INVALID) + dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16)); + + barrier(); + + debug("qemu_fwcfg_read_entry_dma: entry 0x%x, size %u address %p, control 0x%x\n", + entry, size, address, be32_to_cpu(dma.control)); + + fwcfg_arch_ops->arch_read_dma(&dma); +} + +bool qemu_fwcfg_present(void) +{ + return fwcfg_present; +} + +bool qemu_fwcfg_dma_present(void) +{ + return fwcfg_dma_present; +} + +void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address) +{ + if (fwcfg_dma_present) + qemu_fwcfg_read_entry_dma(entry, length, address); + else + qemu_fwcfg_read_entry_pio(entry, length, address); +} + +int qemu_fwcfg_online_cpus(void) +{ + uint16_t nb_cpus; + + if (!fwcfg_present) + return -ENODEV; + + qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus); + + return le16_to_cpu(nb_cpus); +} + +int qemu_fwcfg_read_firmware_list(void) +{ + int i; + uint32_t count; + struct fw_file *file; + struct list_head *entry; + + /* don't read it twice */ + if (!list_empty(&fw_list)) + return 0; + + qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count); + if (!count) + return 0; + + count = be32_to_cpu(count); + for (i = 0; i < count; i++) { + file = malloc(sizeof(*file)); + if (!file) { + printf("error: allocating resource\n"); + goto err; + } + qemu_fwcfg_read_entry(FW_CFG_INVALID, + sizeof(struct fw_cfg_file), &file->cfg); + file->addr = 0; + list_add_tail(&file->list, &fw_list); + } + + return 0; + +err: + list_for_each(entry, &fw_list) { + file = list_entry(entry, struct fw_file, list); + free(file); + } + + return -ENOMEM; +} + +struct fw_file *qemu_fwcfg_find_file(const char *name) +{ + struct list_head *entry; + struct fw_file *file; + + list_for_each(entry, &fw_list) { + file = list_entry(entry, struct fw_file, list); + if (!strcmp(file->cfg.name, name)) + return file; + } + + return NULL; +} + +struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter) +{ + iter->entry = fw_list.next; + return list_entry((struct list_head *)iter->entry, + struct fw_file, list); +} + +struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter) +{ + iter->entry = ((struct list_head *)iter->entry)->next; + return list_entry((struct list_head *)iter->entry, + struct fw_file, list); +} + +bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter) +{ + return iter->entry == &fw_list; +} + +void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops) +{ + uint32_t qemu; + uint32_t dma_enabled; + + fwcfg_present = false; + fwcfg_dma_present = false; + fwcfg_arch_ops = NULL; + + if (!ops || !ops->arch_read_pio || !ops->arch_read_dma) + return; + fwcfg_arch_ops = ops; + + qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu); + if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE) + fwcfg_present = true; + + if (fwcfg_present) { + qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled); + if (dma_enabled & FW_CFG_DMA_ENABLED) + fwcfg_dma_present = true; + } +} diff --git a/include/qemu_fw_cfg.h b/include/qemu_fw_cfg.h deleted file mode 100644 index b0b3b5945ef..00000000000 --- a/include/qemu_fw_cfg.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * (C) Copyright 2015 Miao Yan - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FW_CFG__ -#define __FW_CFG__ - -#include - -enum qemu_fwcfg_items { - FW_CFG_SIGNATURE = 0x00, - FW_CFG_ID = 0x01, - FW_CFG_UUID = 0x02, - FW_CFG_RAM_SIZE = 0x03, - FW_CFG_NOGRAPHIC = 0x04, - FW_CFG_NB_CPUS = 0x05, - FW_CFG_MACHINE_ID = 0x06, - FW_CFG_KERNEL_ADDR = 0x07, - FW_CFG_KERNEL_SIZE = 0x08, - FW_CFG_KERNEL_CMDLINE = 0x09, - FW_CFG_INITRD_ADDR = 0x0a, - FW_CFG_INITRD_SIZE = 0x0b, - FW_CFG_BOOT_DEVICE = 0x0c, - FW_CFG_NUMA = 0x0d, - FW_CFG_BOOT_MENU = 0x0e, - FW_CFG_MAX_CPUS = 0x0f, - FW_CFG_KERNEL_ENTRY = 0x10, - FW_CFG_KERNEL_DATA = 0x11, - FW_CFG_INITRD_DATA = 0x12, - FW_CFG_CMDLINE_ADDR = 0x13, - FW_CFG_CMDLINE_SIZE = 0x14, - FW_CFG_CMDLINE_DATA = 0x15, - FW_CFG_SETUP_ADDR = 0x16, - FW_CFG_SETUP_SIZE = 0x17, - FW_CFG_SETUP_DATA = 0x18, - FW_CFG_FILE_DIR = 0x19, - FW_CFG_FILE_FIRST = 0x20, - FW_CFG_WRITE_CHANNEL = 0x4000, - FW_CFG_ARCH_LOCAL = 0x8000, - FW_CFG_INVALID = 0xffff, -}; - -enum { - BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1, - BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2, - BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3, -}; - -enum { - BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1, - BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2, -}; - -#define FW_CFG_FILE_SLOTS 0x10 -#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS) -#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL) - -#define FW_CFG_MAX_FILE_PATH 56 -#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH - -#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U') - -#define FW_CFG_DMA_ERROR (1 << 0) -#define FW_CFG_DMA_READ (1 << 1) -#define FW_CFG_DMA_SKIP (1 << 2) -#define FW_CFG_DMA_SELECT (1 << 3) - -#define FW_CFG_DMA_ENABLED (1 << 1) - -struct fw_cfg_file { - __be32 size; - __be16 select; - __be16 reserved; - char name[FW_CFG_MAX_FILE_PATH]; -}; - -struct fw_file { - struct fw_cfg_file cfg; /* firmware file information */ - unsigned long addr; /* firmware file in-memory address */ - struct list_head list; /* list node to link to fw_list */ -}; - -struct fw_cfg_file_iter { - struct list_head *entry; /* structure to iterate file list */ -}; - -struct fw_cfg_dma_access { - __be32 control; - __be32 length; - __be64 address; -}; - -struct fw_cfg_arch_ops { - void (*arch_read_pio)(uint16_t selector, uint32_t size, - void *address); - void (*arch_read_dma)(struct fw_cfg_dma_access *dma); -}; - -struct bios_linker_entry { - __le32 command; - union { - /* - * COMMAND_ALLOCATE - allocate a table from @alloc.file - * subject to @alloc.align alignment (must be power of 2) - * and @alloc.zone (can be HIGH or FSEG) requirements. - * - * Must appear exactly once for each file, and before - * this file is referenced by any other command. - */ - struct { - char file[BIOS_LINKER_LOADER_FILESZ]; - __le32 align; - uint8_t zone; - } alloc; - - /* - * COMMAND_ADD_POINTER - patch the table (originating from - * @dest_file) at @pointer.offset, by adding a pointer to the - * table originating from @src_file. 1,2,4 or 8 byte unsigned - * addition is used depending on @pointer.size. - */ - struct { - char dest_file[BIOS_LINKER_LOADER_FILESZ]; - char src_file[BIOS_LINKER_LOADER_FILESZ]; - __le32 offset; - uint8_t size; - } pointer; - - /* - * COMMAND_ADD_CHECKSUM - calculate checksum of the range - * specified by @cksum_start and @cksum_length fields, - * and then add the value at @cksum.offset. - * Checksum simply sums -X for each byte X in the range - * using 8-bit math. - */ - struct { - char file[BIOS_LINKER_LOADER_FILESZ]; - __le32 offset; - __le32 start; - __le32 length; - } cksum; - - /* padding */ - char pad[124]; - }; -} __packed; - -/** - * Initialize QEMU fw_cfg interface - * - * @ops: arch specific read operations - */ -void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops); - -void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address); -int qemu_fwcfg_read_firmware_list(void); -struct fw_file *qemu_fwcfg_find_file(const char *name); - -/** - * Get system cpu number - * - * @return: cpu number in system - */ -int qemu_fwcfg_online_cpus(void); - -/* helper functions to iterate firmware file list */ -struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter); -struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter); -bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter); - -bool qemu_fwcfg_present(void); -bool qemu_fwcfg_dma_present(void); - -#endif diff --git a/include/qfw.h b/include/qfw.h new file mode 100644 index 00000000000..b0b3b5945ef --- /dev/null +++ b/include/qfw.h @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2015 Miao Yan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FW_CFG__ +#define __FW_CFG__ + +#include + +enum qemu_fwcfg_items { + FW_CFG_SIGNATURE = 0x00, + FW_CFG_ID = 0x01, + FW_CFG_UUID = 0x02, + FW_CFG_RAM_SIZE = 0x03, + FW_CFG_NOGRAPHIC = 0x04, + FW_CFG_NB_CPUS = 0x05, + FW_CFG_MACHINE_ID = 0x06, + FW_CFG_KERNEL_ADDR = 0x07, + FW_CFG_KERNEL_SIZE = 0x08, + FW_CFG_KERNEL_CMDLINE = 0x09, + FW_CFG_INITRD_ADDR = 0x0a, + FW_CFG_INITRD_SIZE = 0x0b, + FW_CFG_BOOT_DEVICE = 0x0c, + FW_CFG_NUMA = 0x0d, + FW_CFG_BOOT_MENU = 0x0e, + FW_CFG_MAX_CPUS = 0x0f, + FW_CFG_KERNEL_ENTRY = 0x10, + FW_CFG_KERNEL_DATA = 0x11, + FW_CFG_INITRD_DATA = 0x12, + FW_CFG_CMDLINE_ADDR = 0x13, + FW_CFG_CMDLINE_SIZE = 0x14, + FW_CFG_CMDLINE_DATA = 0x15, + FW_CFG_SETUP_ADDR = 0x16, + FW_CFG_SETUP_SIZE = 0x17, + FW_CFG_SETUP_DATA = 0x18, + FW_CFG_FILE_DIR = 0x19, + FW_CFG_FILE_FIRST = 0x20, + FW_CFG_WRITE_CHANNEL = 0x4000, + FW_CFG_ARCH_LOCAL = 0x8000, + FW_CFG_INVALID = 0xffff, +}; + +enum { + BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1, + BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2, + BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3, +}; + +enum { + BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1, + BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2, +}; + +#define FW_CFG_FILE_SLOTS 0x10 +#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS) +#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL) + +#define FW_CFG_MAX_FILE_PATH 56 +#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH + +#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U') + +#define FW_CFG_DMA_ERROR (1 << 0) +#define FW_CFG_DMA_READ (1 << 1) +#define FW_CFG_DMA_SKIP (1 << 2) +#define FW_CFG_DMA_SELECT (1 << 3) + +#define FW_CFG_DMA_ENABLED (1 << 1) + +struct fw_cfg_file { + __be32 size; + __be16 select; + __be16 reserved; + char name[FW_CFG_MAX_FILE_PATH]; +}; + +struct fw_file { + struct fw_cfg_file cfg; /* firmware file information */ + unsigned long addr; /* firmware file in-memory address */ + struct list_head list; /* list node to link to fw_list */ +}; + +struct fw_cfg_file_iter { + struct list_head *entry; /* structure to iterate file list */ +}; + +struct fw_cfg_dma_access { + __be32 control; + __be32 length; + __be64 address; +}; + +struct fw_cfg_arch_ops { + void (*arch_read_pio)(uint16_t selector, uint32_t size, + void *address); + void (*arch_read_dma)(struct fw_cfg_dma_access *dma); +}; + +struct bios_linker_entry { + __le32 command; + union { + /* + * COMMAND_ALLOCATE - allocate a table from @alloc.file + * subject to @alloc.align alignment (must be power of 2) + * and @alloc.zone (can be HIGH or FSEG) requirements. + * + * Must appear exactly once for each file, and before + * this file is referenced by any other command. + */ + struct { + char file[BIOS_LINKER_LOADER_FILESZ]; + __le32 align; + uint8_t zone; + } alloc; + + /* + * COMMAND_ADD_POINTER - patch the table (originating from + * @dest_file) at @pointer.offset, by adding a pointer to the + * table originating from @src_file. 1,2,4 or 8 byte unsigned + * addition is used depending on @pointer.size. + */ + struct { + char dest_file[BIOS_LINKER_LOADER_FILESZ]; + char src_file[BIOS_LINKER_LOADER_FILESZ]; + __le32 offset; + uint8_t size; + } pointer; + + /* + * COMMAND_ADD_CHECKSUM - calculate checksum of the range + * specified by @cksum_start and @cksum_length fields, + * and then add the value at @cksum.offset. + * Checksum simply sums -X for each byte X in the range + * using 8-bit math. + */ + struct { + char file[BIOS_LINKER_LOADER_FILESZ]; + __le32 offset; + __le32 start; + __le32 length; + } cksum; + + /* padding */ + char pad[124]; + }; +} __packed; + +/** + * Initialize QEMU fw_cfg interface + * + * @ops: arch specific read operations + */ +void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops); + +void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address); +int qemu_fwcfg_read_firmware_list(void); +struct fw_file *qemu_fwcfg_find_file(const char *name); + +/** + * Get system cpu number + * + * @return: cpu number in system + */ +int qemu_fwcfg_online_cpus(void); + +/* helper functions to iterate firmware file list */ +struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter); +struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter); +bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter); + +bool qemu_fwcfg_present(void); +bool qemu_fwcfg_dma_present(void); + +#endif -- cgit v1.3.1 From 91fc5bf652c1e959373cd21df4809a74d31e75fe Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 11 May 2016 07:44:55 -0700 Subject: x86: minnowmax: Adjust U-Boot environment address in SPI flash Currently U-Boot environment address is at offset 0x7fe00 of a 8MB SPI flash. When creating a partial u-boot.rom image without flash descriptor and ME firmware, U-Boot actually occupies the last 1MB of the flash, and reprograming U-Boot causes previous environment settings get lost which is not convenient during testing. Adjust the environment address to 0x6ef000 instead (before the MRC cache data region in the flash). Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass --- doc/README.x86 | 2 +- include/configs/minnowmax.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/doc/README.x86 b/doc/README.x86 index ce806ee424e..25cb218c2a7 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -304,12 +304,12 @@ Offset Description Controlling config 000000 descriptor.bin Hard-coded to 0 in ifdtool 001000 me.bin Set by the descriptor 500000 +6ef000 Environment CONFIG_ENV_OFFSET 6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE 700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE 790000 vga.bin CONFIG_VGA_BIOS_ADDR 7c0000 fsp.bin CONFIG_FSP_ADDR 7f8000 (depends on size of fsp.bin) -7fe000 Environment CONFIG_ENV_OFFSET 7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16 Overall ROM image size is controlled by CONFIG_ROM_SIZE. diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 674d1f602b9..95ad1287f60 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -40,6 +40,6 @@ #define CONFIG_X86EMU_RAW_IO #define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x007fe000 +#define CONFIG_ENV_OFFSET 0x006ef000 #endif /* __CONFIG_H */ -- cgit v1.3.1 From 9989c1567d53a2558b872fabc39d1f8a9383c3ca Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 26 Feb 2016 17:20:26 +0800 Subject: board: atmel: add SAMA5D2 PTC Engineering board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The board supports following features: - Boot media support: NAND Flash/SPI Flash - Support ethernet - Support USB mass storage Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann --- arch/arm/mach-at91/Kconfig | 6 + board/atmel/sama5d2_ptc/Kconfig | 15 ++ board/atmel/sama5d2_ptc/MAINTAINERS | 7 + board/atmel/sama5d2_ptc/Makefile | 8 + board/atmel/sama5d2_ptc/sama5d2_ptc.c | 285 ++++++++++++++++++++++++++++++++ configs/sama5d2_ptc_nandflash_defconfig | 12 ++ configs/sama5d2_ptc_spiflash_defconfig | 12 ++ include/configs/sama5d2_ptc.h | 155 +++++++++++++++++ 8 files changed, 500 insertions(+) create mode 100644 board/atmel/sama5d2_ptc/Kconfig create mode 100644 board/atmel/sama5d2_ptc/MAINTAINERS create mode 100644 board/atmel/sama5d2_ptc/Makefile create mode 100644 board/atmel/sama5d2_ptc/sama5d2_ptc.c create mode 100644 configs/sama5d2_ptc_nandflash_defconfig create mode 100644 configs/sama5d2_ptc_spiflash_defconfig create mode 100644 include/configs/sama5d2_ptc.h (limited to 'include') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 9ce775e0da2..73a9c74512a 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -71,6 +71,11 @@ config TARGET_AT91SAM9X5EK select CPU_ARM926EJS select SUPPORT_SPL +config TARGET_SAMA5D2_PTC + bool "SAMA5D2 PTC board" + select CPU_V7 + select SUPPORT_SPL + config TARGET_SAMA5D2_XPLAINED bool "SAMA5D2 Xplained board" select CPU_V7 @@ -138,6 +143,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig" source "board/atmel/at91sam9n12ek/Kconfig" source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" +source "board/atmel/sama5d2_ptc/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" diff --git a/board/atmel/sama5d2_ptc/Kconfig b/board/atmel/sama5d2_ptc/Kconfig new file mode 100644 index 00000000000..d2661c689a2 --- /dev/null +++ b/board/atmel/sama5d2_ptc/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D2_PTC + +config SYS_BOARD + default "sama5d2_ptc" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d2_ptc" + +endif diff --git a/board/atmel/sama5d2_ptc/MAINTAINERS b/board/atmel/sama5d2_ptc/MAINTAINERS new file mode 100644 index 00000000000..7ab03d6eafa --- /dev/null +++ b/board/atmel/sama5d2_ptc/MAINTAINERS @@ -0,0 +1,7 @@ +SAMA5D2 PTC Engineering BOARD +M: Wenyou Yang +S: Maintained +F: board/atmel/sama5d2_ptc/ +F: include/configs/sama5d2_ptc.h +F: configs/sama5d2_ptc_spiflash_defconfig +F: configs/sama5d2_ptc_nandflash_defconfig diff --git a/board/atmel/sama5d2_ptc/Makefile b/board/atmel/sama5d2_ptc/Makefile new file mode 100644 index 00000000000..1fe0392da09 --- /dev/null +++ b/board/atmel/sama5d2_ptc/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2016 Atmel +# Wenyou Yang +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d2_ptc.o diff --git a/board/atmel/sama5d2_ptc/sama5d2_ptc.c b/board/atmel/sama5d2_ptc/sama5d2_ptc.c new file mode 100644 index 00000000000..9e6544bc075 --- /dev/null +++ b/board/atmel/sama5d2_ptc/sama5d2_ptc.c @@ -0,0 +1,285 @@ +/* + * Copyright (C) 2016 Atmel + * Wenyou.Yang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); +} + +static void board_spi0_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0); + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0); + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0); + + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); + + at91_periph_clk_enable(ATMEL_ID_SPI0); +} + +static void board_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + + at91_periph_clk_enable(ATMEL_ID_HSMC); + + writel(AT91_SFR_EBICFG_DRIVE0_HIGH | + AT91_SFR_EBICFG_PULL0_NONE | + AT91_SFR_EBICFG_DRIVE1_HIGH | + AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg); + + /* Configure SMC CS3 for NAND */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | + AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | + AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) | + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0); /* D0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0); /* D1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0); /* D2 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0); /* D3 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0); /* D4 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0); /* D5 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0); /* D6 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0); /* D7 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0); /* RE */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0); /* WE */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1); /* NCS */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1); /* RDY */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1); /* ALE */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1); /* CLE */ +} + +static void board_usb_hw_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1); +} + +static void board_gmac_hw_init(void) +{ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */ + + at91_periph_clk_enable(ATMEL_ID_GMAC); +} + +static void board_uart0_hw_init(void) +{ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */ + + at91_periph_clk_enable(CONFIG_USART_ID); +} + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + + board_uart0_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_ATMEL_SPI + board_spi0_hw_init(); +#endif +#ifdef CONFIG_NAND_ATMEL + board_nand_hw_init(); +#endif +#ifdef CONFIG_MACB + board_gmac_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + board_usb_hw_init(); +#endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); + if (rc) + printf("GMAC register failed\n"); +#endif + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + usba_udc_probe(&pdata); +#ifdef CONFIG_USB_ETH_RNDIS + usb_eth_initialize(bis); +#endif +#endif + + return rc; +} + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_SERIALFLASH + board_spi0_hw_init(); +#endif + +#ifdef CONFIG_SYS_USE_NANDFLASH + board_nand_hw_init(); +#endif +} + +static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{ + ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); + + ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS5 | + ATMEL_MPDDRC_CR_DIC_DS | + ATMEL_MPDDRC_CR_DIS_DLL | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddrc->rtr = 0x511; + + ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | + (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); + + ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | + (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | + (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | + (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); + + ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | + (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | + (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); +} + +void mem_init(void) +{ + struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + struct atmel_mpddrc_config ddrc_config; + u32 reg; + + ddrc_conf(&ddrc_config); + + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + at91_system_clk_enable(AT91_PMC_DDR); + + reg = readl(&mpddrc->io_calibr); + reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; + reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; + reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; + reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); + writel(reg, &mpddrc->io_calibr); + + writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE, + &mpddrc->rd_data_path); + + ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); + + writel(0x3, &mpddrc->cal_mr4); + writel(64, &mpddrc->tim_cal); +} + +void at91_pmc_init(void) +{ + at91_plla_init(AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(82) | + AT91_PMC_PLLXR_DIV(1)); + + at91_pllicpr_init(0); + + at91_mck_init(AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA); +} +#endif diff --git a/configs/sama5d2_ptc_nandflash_defconfig b/configs/sama5d2_ptc_nandflash_defconfig new file mode 100644 index 00000000000..74251840fce --- /dev/null +++ b/configs/sama5d2_ptc_nandflash_defconfig @@ -0,0 +1,12 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D2_PTC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_SPI_FLASH=y diff --git a/configs/sama5d2_ptc_spiflash_defconfig b/configs/sama5d2_ptc_spiflash_defconfig new file mode 100644 index 00000000000..27fc394d42a --- /dev/null +++ b/configs/sama5d2_ptc_spiflash_defconfig @@ -0,0 +1,12 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D2_PTC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_SPI_FLASH=y diff --git a/include/configs/sama5d2_ptc.h b/include/configs/sama5d2_ptc.h new file mode 100644 index 00000000000..d91d75eb402 --- /dev/null +++ b/include/configs/sama5d2_ptc.h @@ -0,0 +1,155 @@ +/* + * Configuration settings for the SAMA5D2 PTC Engineering board. + * + * Copyright (C) 2016 Atmel + * Wenyou Yang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* No NOR flash, this definition should put before common header */ +#define CONFIG_SYS_NO_FLASH + +#include "at91-sama5_common.h" + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_UART0 +#define CONFIG_USART_ID ATMEL_ID_UART0 + +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x210000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#undef CONFIG_AT91_GPIO +#define CONFIG_ATMEL_PIO4 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 + +/* SerialFlash */ +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#endif + +/* NAND flash */ +#define CONFIG_CMD_NAND + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#define CONFIG_CMD_NAND_TRIMFFS +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE +#endif + +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2_PTC" + +#if defined(CONFIG_CMD_USB) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +#ifdef CONFIG_SYS_USE_NANDFLASH +#undef CONFIG_ENV_OFFSET +#undef CONFIG_ENV_OFFSET_REDUND +#undef CONFIG_BOOTCOMMAND +/* u-boot env in nand flash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x200000 +#define CONFIG_ENV_OFFSET_REDUND 0x400000 +#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xb80000 0x80000;" \ + "nand read 0x22000000 0x600000 0x600000;" \ + "bootz 0x22000000 - 0x21000000" +#endif + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS \ + "console=ttyS0,57600 earlyprintk " \ + "mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) " \ + "rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs" + +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x200000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SYS_USE_SERIALFLASH +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 + +#elif CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_PMECC_CAP 8 +#define CONFIG_PMECC_SECTOR_SIZE 512 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 224 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER +#endif + +#endif -- cgit v1.3.1 From 7f307d93ed147fc831425189463d92e50d5c7566 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 14 Apr 2016 06:52:26 +0900 Subject: ARM: zynq: load u-boot.img whether CONFIG_OF_SEPARATE is defined or not Since commit ad1ecd2063da ("fdt: Build a U-Boot binary without device tree"), u-boot-dtb.img is identical to u-boot.img, so SPL can always load u-boot.img whether CONFIG_OF_SEPARATE is defined or not. Signed-off-by: Masahiro Yamada Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index a3e4aecb571..82ece0df2d6 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -315,11 +315,7 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_FAT_SUPPORT -#ifdef CONFIG_OF_SEPARATE -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" -#else -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif /* Disable dcache for SPL just for sure */ -- cgit v1.3.1 From a1207de0e6d6526e470361fac42f2c077b43a0ad Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 22 Apr 2016 14:28:17 +0200 Subject: ARM64: zynqmp: Enable missing distro default options Enable all options which distros requires. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 6b8e3ea8657..f41a2cbaa26 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -65,6 +65,7 @@ #define CONFIG_CMD_ENV #define CONFIG_DOS_PARTITION #define CONFIG_EFI_PARTITION +#define CONFIG_ISO_PARTITION #define CONFIG_MP /* BOOTP options */ @@ -74,6 +75,19 @@ #define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_MAY_FAIL #define CONFIG_BOOTP_SERVERIP +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 + +/* Diff from config_distro_defaults.h */ +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_AUTO_COMPLETE + +/* PXE */ +#define CONFIG_CMD_PXE +#define CONFIG_MENU #if defined(CONFIG_ZYNQ_SDHCI) # define CONFIG_MMC -- cgit v1.3.1 From 6919b4bf36357463b419c4b848b5778d7ba0874e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 22 Apr 2016 11:48:49 +0200 Subject: ARM64: zynqmp: Add support for reading MAC from eeprom Add support for on board eeprom with programmed MAC for using in u-boot to have uniq address for every board. Most of the time uniq MAC address is on a label on the board. If address is not programmed use these command to program it. On zcu102: ZynqMP> mm.b 0 00000000: 00 ? 00 00000001: a0 ? 0a 00000002: 35 ? 35 00000003: 02 ? 02 00000004: 00 ? ef 00000005: 00 ? 67 00000006: 00 ? q i2c dev 5 i2c write 0 54 20 6 i2c md 54 20 Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 17 +++++++++++++++++ include/configs/xilinx_zynqmp_zcu102.h | 6 ++++++ 2 files changed, 23 insertions(+) (limited to 'include') diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 132d724fbdf..4623cd49e9c 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -15,6 +15,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +51,22 @@ int board_early_init_r(void) return 0; } +int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) +{ +#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ + defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \ + defined(CONFIG_ZYNQ_EEPROM_BUS) + i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS); + + if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, + CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, + ethaddr, 6)) + printf("I2C EEPROM MAC address read failed\n"); +#endif + + return 0; +} + #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) /* * fdt_get_reg - Fill buffer by information from DT diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h index 30db2e45324..81079fe7d8b 100644 --- a/include/configs/xilinx_zynqmp_zcu102.h +++ b/include/configs/xilinx_zynqmp_zcu102.h @@ -48,6 +48,12 @@ #define CONFIG_IDENT_STRING " Xilinx ZynqMP ZCU102" +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_CMD_EEPROM +#define CONFIG_ZYNQ_EEPROM_BUS 5 +#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 +#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20 + #define CONFIG_KERNEL_FDT_OFST_SIZE \ "kernel_offset=0x180000\0" \ "fdt_offset=0x100000\0" \ -- cgit v1.3.1 From 926782cdf8be8769ae2f9a40ec7a62af1b91ac77 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 26 Apr 2016 16:03:42 +0200 Subject: ARM64: zynqmp: Enable eMMC boot partitions commands Enable some additional features of the eMMC boot partitions. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index f41a2cbaa26..e36dde61dd8 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -92,6 +92,7 @@ #if defined(CONFIG_ZYNQ_SDHCI) # define CONFIG_MMC # define CONFIG_GENERIC_MMC +# define CONFIG_SUPPORT_EMMC_BOOT # define CONFIG_SDHCI # ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ # define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000 -- cgit v1.3.1 From 013642c2d4a652878a4e7583fe125ea76582ce55 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 29 Apr 2016 13:04:02 +0200 Subject: ARM64: zynqmp: Remove CONFIG_PREBOOT CONFIG_PREBOOT variable is breaking ./test/py framework. Remove it. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index e36dde61dd8..e6c38a5819f 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -159,7 +159,6 @@ "booti $kernel_addr - $fdt_addr\0" \ DFU_ALT_INFO -#define CONFIG_PREBOOT "run bootargs" #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 3 -- cgit v1.3.1 From 3a3b9147892cb47f96dff1075f1494dca17b6eaf Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 May 2016 07:54:20 +0200 Subject: spl: Introduce new function spl_board_prepare_for_boot Call this function before passing control from SPL. For fpga case it is necessary to enable for example level shifters when bitstream is programmed. Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- common/spl/spl.c | 6 ++++++ include/spl.h | 1 + 2 files changed, 7 insertions(+) (limited to 'include') diff --git a/common/spl/spl.c b/common/spl/spl.c index 93f9bd13fcd..caaf135f9ad 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -64,6 +64,11 @@ __weak void spl_board_prepare_for_linux(void) /* Nothing to do! */ } +__weak void spl_board_prepare_for_boot(void) +{ + /* Nothing to do! */ +} + void spl_set_header_raw_uboot(void) { spl_image.size = CONFIG_SYS_MONITOR_LEN; @@ -404,6 +409,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) #endif debug("loaded - jumping to U-Boot..."); + spl_board_prepare_for_boot(); jump_to_image_no_args(&spl_image); } diff --git a/include/spl.h b/include/spl.h index 7edfab46dcd..335b76a1b15 100644 --- a/include/spl.h +++ b/include/spl.h @@ -58,6 +58,7 @@ u32 spl_boot_mode(void); void spl_set_header_raw_uboot(void); int spl_parse_image_header(const struct image_header *header); void spl_board_prepare_for_linux(void); +void spl_board_prepare_for_boot(void); void __noreturn jump_to_image_linux(void *arg); int spl_start_uboot(void); void spl_display_print(void); -- cgit v1.3.1 From 27640fda55bf998d1eb5109b3410bf62e445e191 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 May 2016 09:50:35 +0200 Subject: ARM64: zynqmp: Enable option to overwrite default variables Enable overwriting variables out of main config file. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index e6c38a5819f..1a1892dff6a 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -148,6 +148,7 @@ #endif /* Initial environment variables */ +#ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "kernel_addr=0x80000\0" \ "fdt_addr=0x7000000\0" \ @@ -158,6 +159,7 @@ "load mmc $sdbootdev:$partid $kernel_addr Image && " \ "booti $kernel_addr - $fdt_addr\0" \ DFU_ALT_INFO +#endif #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 3 -- cgit v1.3.1 From d9b58b303120fb8fe0b7c9799e2b7682da4bec16 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 27 Apr 2016 14:03:29 +0200 Subject: tools: zynqmpimage: Add Xilinx ZynqMP boot header generation Add support for the zynqmpimage to mkimage. Only basic functionality is supported without encryption and register initialization with one partition which is filled by U-Boot SPL. For more detail information look at Xilinx ZynqMP TRM. Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- common/image.c | 1 + include/image.h | 3 +- scripts/Makefile.spl | 7 ++ tools/Makefile | 1 + tools/zynqmpimage.c | 269 +++++++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 280 insertions(+), 1 deletion(-) create mode 100644 tools/zynqmpimage.c (limited to 'include') diff --git a/common/image.c b/common/image.c index 26d6c9a5927..9824685344b 100644 --- a/common/image.c +++ b/common/image.c @@ -159,6 +159,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" }, { IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" }, { IH_TYPE_ZYNQIMAGE, "zynqimage", "Xilinx Zynq Boot Image" }, + { IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" }, { -1, "", "", }, }; diff --git a/include/image.h b/include/image.h index f9ee5649c54..a8488f2b392 100644 --- a/include/image.h +++ b/include/image.h @@ -246,8 +246,9 @@ struct lmb; #define IH_TYPE_RKSD 24 /* Rockchip SD card */ #define IH_TYPE_RKSPI 25 /* Rockchip SPI image */ #define IH_TYPE_ZYNQIMAGE 26 /* Xilinx Zynq Boot Image */ +#define IH_TYPE_ZYNQMPIMAGE 27 /* Xilinx ZynqMP Boot Image */ -#define IH_TYPE_COUNT 27 /* Number of image types */ +#define IH_TYPE_COUNT 28 /* Number of image types */ /* * Compression Types diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index ec8d8f1b72a..6d2017da7e9 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -129,7 +129,12 @@ endif boot.bin: $(obj)/u-boot-spl.bin FORCE $(call if_changed,mkimage) else +ifdef CONFIG_ARCH_ZYNQ MKIMAGEFLAGS_boot.bin = -T zynqimage +endif +ifdef CONFIG_ARCH_ZYNQMP +MKIMAGEFLAGS_boot.bin = -T zynqmpimage +endif spl/boot.bin: $(obj)/u-boot-spl.bin FORCE $(call if_changed,mkimage) @@ -157,6 +162,8 @@ ifdef CONFIG_ARCH_ZYNQ ALL-y += $(obj)/boot.bin endif +ALL-(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin + all: $(ALL-y) quiet_cmd_cat = CAT $@ diff --git a/tools/Makefile b/tools/Makefile index da50e1bffca..63355aa36d8 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -98,6 +98,7 @@ dumpimage-mkimage-objs := aisimage.o \ common/hash.o \ ublimage.o \ zynqimage.o \ + zynqmpimage.o \ $(LIBFDT_OBJS) \ $(RSA_OBJS-y) diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c new file mode 100644 index 00000000000..3f28eb401d9 --- /dev/null +++ b/tools/zynqmpimage.c @@ -0,0 +1,269 @@ +/* + * Copyright (C) 2016 Michal Simek + * Copyright (C) 2015 Nathan Rossi + * + * SPDX-License-Identifier: GPL-2.0+ + * + * The following Boot Header format/structures and values are defined in the + * following documents: + * * ug1085 ZynqMP TRM (Chapter 9, Table 9-3) + * + * Expected Header Size = 0x9C0 + * Forced as 'little' endian, 32-bit words + * + * 0x 0 - Interrupt table (8 words) + * ... (Default value = 0xeafffffe) + * 0x 1f + * 0x 20 - Width detection + * * DEFAULT_WIDTHDETECTION 0xaa995566 + * 0x 24 - Image identifier + * * DEFAULT_IMAGEIDENTIFIER 0x584c4e58 + * 0x 28 - Encryption + * * 0x00000000 - None + * * 0xa5c3c5a3 - eFuse + * * 0xa5c3c5a7 - obfuscated key in eFUSE + * * 0x3a5c3c5a - bbRam + * * 0xa35c7ca5 - obfuscated key in boot header + * 0x 2C - Image load + * 0x 30 - Image offset + * 0x 34 - PFW image length + * 0x 38 - Total PFW image length + * 0x 3C - Image length + * 0x 40 - Total image length + * 0x 44 - Image attributes + * 0x 48 - Header checksum + * 0x 4c - Obfuscated key + * ... + * 0x 68 + * 0x 6c - Reserved + * 0x 70 - User defined + * ... + * 0x 9c + * 0x a0 - Secure header initialization vector + * ... + * 0x a8 + * 0x ac - Obfuscated key initialization vector + * ... + * 0x b4 + * 0x b8 - Register Initialization, 511 Address and Data word pairs + * * List is terminated with an address of 0xffffffff or + * ... * at the max number of entries + * 0x8b4 + * 0x8b8 - Reserved + * ... + * 0x9bf + * 0x9c0 - Data/Image starts here or above + */ + +#include "imagetool.h" +#include "mkimage.h" +#include + +#define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe)) +#define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff)) +#define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566)) +#define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58)) + +enum { + ENCRYPTION_EFUSE = 0xa5c3c5a3, + ENCRYPTION_OEFUSE = 0xa5c3c5a7, + ENCRYPTION_BBRAM = 0x3a5c3c5a, + ENCRYPTION_OBBRAM = 0xa35c7ca5, + ENCRYPTION_NONE = 0x0, +}; + +struct zynqmp_reginit { + uint32_t address; + uint32_t data; +}; + +#define HEADER_INTERRUPT_VECTORS 8 +#define HEADER_REGINITS 256 + +struct zynqmp_header { + uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */ + uint32_t width_detection; /* 0x20 */ + uint32_t image_identifier; /* 0x24 */ + uint32_t encryption; /* 0x28 */ + uint32_t image_load; /* 0x2c */ + uint32_t image_offset; /* 0x30 */ + uint32_t pfw_image_length; /* 0x34 */ + uint32_t total_pfw_image_length; /* 0x38 */ + uint32_t image_size; /* 0x3c */ + uint32_t image_stored_size; /* 0x40 */ + uint32_t image_attributes; /* 0x44 */ + uint32_t checksum; /* 0x48 */ + uint32_t __reserved1[27]; /* 0x4c */ + struct zynqmp_reginit register_init[HEADER_REGINITS]; /* 0xb8 */ + uint32_t __reserved4[66]; /* 0x9c0 */ +}; + +static struct zynqmp_header zynqmpimage_header; + +static uint32_t zynqmpimage_checksum(struct zynqmp_header *ptr) +{ + uint32_t checksum = 0; + + if (ptr == NULL) + return 0; + + checksum += le32_to_cpu(ptr->width_detection); + checksum += le32_to_cpu(ptr->image_identifier); + checksum += le32_to_cpu(ptr->encryption); + checksum += le32_to_cpu(ptr->image_load); + checksum += le32_to_cpu(ptr->image_offset); + checksum += le32_to_cpu(ptr->pfw_image_length); + checksum += le32_to_cpu(ptr->total_pfw_image_length); + checksum += le32_to_cpu(ptr->image_size); + checksum += le32_to_cpu(ptr->image_stored_size); + checksum += le32_to_cpu(ptr->image_attributes); + checksum = ~checksum; + + return cpu_to_le32(checksum); +} + +static void zynqmpimage_default_header(struct zynqmp_header *ptr) +{ + int i; + + if (ptr == NULL) + return; + + ptr->width_detection = HEADER_WIDTHDETECTION; + ptr->image_attributes = 0x800; + ptr->image_identifier = HEADER_IMAGEIDENTIFIER; + ptr->encryption = cpu_to_le32(ENCRYPTION_NONE); + + /* Setup not-supported/constant/reserved fields */ + for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) + ptr->interrupt_vectors[i] = HEADER_INTERRUPT_DEFAULT; + + for (i = 0; i < HEADER_REGINITS; i++) { + ptr->register_init[i].address = HEADER_REGINIT_NULL; + ptr->register_init[i].data = 0; + } + + /* + * Certain reserved fields are required to be set to 0, ensure they are + * set as such. + */ + ptr->pfw_image_length = 0x0; + ptr->total_pfw_image_length = 0x0; +} + +/* mkimage glue functions */ +static int zynqmpimage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr; + + if (image_size < sizeof(struct zynqmp_header)) + return -1; + + if (zynqhdr->width_detection != HEADER_WIDTHDETECTION) + return -1; + if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER) + return -1; + + if (zynqmpimage_checksum(zynqhdr) != zynqhdr->checksum) + return -1; + + return 0; +} + +static void zynqmpimage_print_header(const void *ptr) +{ + struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr; + int i; + + printf("Image Type : Xilinx Zynq Boot Image support\n"); + printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset)); + printf("Image Size : %lu bytes (%lu bytes packed)\n", + (unsigned long)le32_to_cpu(zynqhdr->image_size), + (unsigned long)le32_to_cpu(zynqhdr->image_stored_size)); + printf("Image Load : 0x%08x\n", le32_to_cpu(zynqhdr->image_load)); + printf("Checksum : 0x%08x\n", le32_to_cpu(zynqhdr->checksum)); + + for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) { + if (zynqhdr->interrupt_vectors[i] == HEADER_INTERRUPT_DEFAULT) + continue; + + printf("Modified Interrupt Vector Address [%d]: 0x%08x\n", i, + le32_to_cpu(zynqhdr->interrupt_vectors[i])); + } + + for (i = 0; i < HEADER_REGINITS; i++) { + if (zynqhdr->register_init[i].address == HEADER_REGINIT_NULL) + break; + + if (i == 0) + printf("Custom Register Initialization:\n"); + + printf(" @ 0x%08x -> 0x%08x\n", + le32_to_cpu(zynqhdr->register_init[i].address), + le32_to_cpu(zynqhdr->register_init[i].data)); + } +} + +static int zynqmpimage_check_params(struct image_tool_params *params) +{ + if (!params) + return 0; + + if (params->addr != 0x0) { + fprintf(stderr, "Error: Load Address cannot be specified.\n"); + return -1; + } + + /* + * If the entry point is specified ensure it is 64 byte aligned. + */ + if (params->eflag && (params->ep % 64 != 0)) { + fprintf(stderr, + "Error: Entry Point must be aligned to a 64-byte boundary.\n"); + return -1; + } + + return !(params->lflag || params->dflag); +} + +static int zynqmpimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_ZYNQMPIMAGE) + return EXIT_SUCCESS; + return EXIT_FAILURE; +} + +static void zynqmpimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr; + zynqmpimage_default_header(zynqhdr); + + /* place image directly after header */ + zynqhdr->image_offset = + cpu_to_le32((uint32_t)sizeof(struct zynqmp_header)); + zynqhdr->image_size = cpu_to_le32(params->file_size - + sizeof(struct zynqmp_header)); + zynqhdr->image_stored_size = zynqhdr->image_size; + zynqhdr->image_load = 0xfffc0000; + if (params->eflag) + zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep); + + zynqhdr->checksum = zynqmpimage_checksum(zynqhdr); +} + +U_BOOT_IMAGE_TYPE( + zynqmpimage, + "Xilinx ZynqMP Boot Image support", + sizeof(struct zynqmp_header), + (void *)&zynqmpimage_header, + zynqmpimage_check_params, + zynqmpimage_verify_header, + zynqmpimage_print_header, + zynqmpimage_set_header, + NULL, + zynqmpimage_check_image_types, + NULL, + NULL +); -- cgit v1.3.1 From e6a9ed04e78cf87ec97e306fa4e7a1669ef98df6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 20 Nov 2015 13:17:22 +0100 Subject: ARM64: zynqmp: Add SPL support support Support RAM and MMC boot mode in SPL also with SPL_FIT images. In MMC boot mode two boot options are available: 1) Boot flow with ATF(EL3) and full U-Boot(EL2): aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000 -d bl31.bin atf.ub cp spl/boot.bin cp atf.ub cp u-boot.bin 2) Boot flow with full U-Boot(EL3): cp spl/boot.bin cp u-boot*.img 3) emmc boot mode dd if=/dev/zero of=sd.img bs=1024 count=1024 parted sd.img mktable msdos parted sd.img mkpart p fat32 0% 100% kpartx -a sd.img mkfs.vfat /dev/mapper/loop0p1 mount /dev/mapper/loop0p1 /mnt/ cp spl/boot.bin /mnt cp u-boot.img /mnt cp u-boot.bin /mnt cp atf.ub /mnt umount /dev/mapper/loop0p1 kpartx -d sd.img cp sd.img /tftpboot/ and program it via u-boot tftpb 10000 sd.img mmcinfo mmc write 10000 0 $filesize mmc rescan mmc part ls mmc 0 psu_init() function contains low level SoC setup generated for every HW design by Xilinx design tools. xil_io.h is only supporting file to fix all dependencies from tools. The same solution was used on Xilinx Zynq. The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which stays at the same location all the time. Bootrom expects starting address to be at 0xfffc0000 that's why this address is SPL_TEXT_BASE. Signed-off-by: Michal Simek --- arch/arm/Kconfig | 1 + arch/arm/cpu/armv8/zynqmp/Makefile | 1 + arch/arm/cpu/armv8/zynqmp/spl.c | 107 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-zynqmp/sys_proto.h | 2 + board/xilinx/zynqmp/Makefile | 23 +++++- board/xilinx/zynqmp/xil_io.h | 35 +++++++++ include/configs/xilinx_zynqmp.h | 43 ++++++++++- 7 files changed, 209 insertions(+), 3 deletions(-) create mode 100644 arch/arm/cpu/armv8/zynqmp/spl.c create mode 100644 board/xilinx/zynqmp/xil_io.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6b65d8e76a4..729b1816bf7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -594,6 +594,7 @@ config ARCH_ZYNQMP select DM select OF_CONTROL select DM_SERIAL + select SUPPORT_SPL config TEGRA bool "NVIDIA Tegra" diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile index d0ed2223ff7..be8673a7db4 100644 --- a/arch/arm/cpu/armv8/zynqmp/Makefile +++ b/arch/arm/cpu/armv8/zynqmp/Makefile @@ -9,3 +9,4 @@ obj-y += clk.o obj-y += cpu.o obj-$(CONFIG_MP) += mp.o obj-y += slcr.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c new file mode 100644 index 00000000000..e3e2a4fb5ad --- /dev/null +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -0,0 +1,107 @@ +/* + * Copyright 2015 - 2016 Xilinx, Inc. + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include +#include +#include +#include + +void board_init_f(ulong dummy) +{ + psu_init(); + board_early_init_r(); + +#ifdef CONFIG_DEBUG_UART + /* Uart debug for sure */ + debug_uart_init(); + puts("Debug uart enabled\n"); /* or printch() */ +#endif + /* Delay is required for clocks to be propagated */ + udelay(1000000); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* No need to call timer init - it is empty for ZynqMP */ + board_init_r(NULL, 0); +} + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + preloader_console_init(); + board_init(); +} +#endif + +u32 spl_boot_device(void) +{ + u32 reg = 0; + u8 bootmode; + + reg = readl(&crlapb_base->boot_mode); + bootmode = reg & BOOT_MODES_MASK; + + switch (bootmode) { + case JTAG_MODE: + return BOOT_DEVICE_RAM; +#ifdef CONFIG_SPL_MMC_SUPPORT + case EMMC_MODE: + case SD_MODE: + case SD_MODE1: + return BOOT_DEVICE_MMC1; +#endif + default: + printf("Invalid Boot Mode:0x%x\n", bootmode); + break; + } + + return 0; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_RAM: + return 0; + case BOOT_DEVICE_MMC1: + return MMCSD_MODE_FS; + default: + puts("spl: error: unsupported device\n"); + hang(); + } +} + +__weak void psu_init(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists. + */ +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + return 0; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 021626dc140..1db2bd6a4f7 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -17,4 +17,6 @@ int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); +void psu_init(void); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 2ab3f190ac3..90f00c650a8 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -1,8 +1,29 @@ # -# (C) Copyright 2014 - 2015 Xilinx, Inc. +# (C) Copyright 2014 - 2016 Xilinx, Inc. # Michal Simek # # SPDX-License-Identifier: GPL-2.0+ # obj-y := zynqmp.o + +hw-platform-y :=$(shell echo $(CONFIG_SYS_CONFIG_NAME)) + +init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\ + $(hw-platform-y)/psu_init_gpl.o) + +ifeq ($(init-objs),) +ifneq ($(wildcard $(srctree)/$(src)/psu_init_gpl.c),) +init-objs := psu_init_gpl.o +$(if $(CONFIG_SPL_BUILD),\ +$(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/)) +endif +endif + +obj-$(CONFIG_SPL_BUILD) += $(init-objs) + +# Suppress "warning: function declaration isn't a prototype" +CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes + +# To include xil_io.h +CFLAGS_psu_init_gpl.o := -I$(srctree)/$(src) diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h new file mode 100644 index 00000000000..57ca4adf11b --- /dev/null +++ b/board/xilinx/zynqmp/xil_io.h @@ -0,0 +1,35 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H + +/* FIXME remove this when vivado is fixed */ +#include + +#define xil_printf(...) + +void Xil_ICacheEnable(void) +{} + +void Xil_DCacheEnable(void) +{} + +void Xil_ICacheDisable(void) +{} + +void Xil_DCacheDisable(void) +{} + +void Xil_Out32(unsigned long addr, unsigned long val) +{ + writel(val, addr); +} + +int Xil_In32(unsigned long addr) +{ + return readl(addr); +} + +#endif /* XIL_IO_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 1a1892dff6a..b2fa164f652 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -41,7 +41,7 @@ # define CONFIG_IDENT_STRING " Xilinx ZynqMP" #endif -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_INIT_SP_ADDR 0xfffffffc /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ #if !defined(COUNTER_FREQUENCY) @@ -65,7 +65,9 @@ #define CONFIG_CMD_ENV #define CONFIG_DOS_PARTITION #define CONFIG_EFI_PARTITION -#define CONFIG_ISO_PARTITION +#ifndef CONFIG_SPL_BUILD +# define CONFIG_ISO_PARTITION +#endif #define CONFIG_MP /* BOOTP options */ @@ -228,4 +230,41 @@ #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_CLOCKS +#define CONFIG_SPL_TEXT_BASE 0xfffc0000 +#define CONFIG_SPL_MAX_SIZE 0x20000 + +/* Just random location in OCM */ +#define CONFIG_SPL_BSS_START_ADDR 0x1000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000000 + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_RAM_DEVICE + +#define CONFIG_SPL_OS_BOOT +/* u-boot is like dtb */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x8000000 + +/* ATF is my kernel image */ +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf.ub" + +/* FIT load address for RAM boot */ +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000 + +/* MMC support */ +#ifdef CONFIG_ZYNQ_SDHCI +# define CONFIG_SPL_MMC_SUPPORT +# define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */ +# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */ +# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* unused */ +# define CONFIG_SPL_LIBDISK_SUPPORT +# define CONFIG_SPL_FAT_SUPPORT +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif + #endif /* __XILINX_ZYNQMP_H */ -- cgit v1.3.1 From ed0cea7c5271cbfd37089f3a6392ba383eda06f7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 17 May 2016 13:58:44 +0200 Subject: mkimage: Report information about fpga Add FIT_FPGA_PROP that user can identify an optional entry for fpga. Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- common/image-fit.c | 4 +++ common/image.c | 1 + doc/uImage.FIT/multi-with-fpga.its | 67 +++++++++++++++++++++++++++++++++++ doc/uImage.FIT/source_file_format.txt | 3 ++ include/image.h | 4 ++- 5 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 doc/uImage.FIT/multi-with-fpga.its (limited to 'include') diff --git a/common/image-fit.c b/common/image-fit.c index c86b7c6b118..8a0ca2a8038 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1483,6 +1483,10 @@ void fit_conf_print(const void *fit, int noffset, const char *p) if (uname) printf("%s FDT: %s\n", p, uname); + uname = (char *)fdt_getprop(fit, noffset, FIT_FPGA_PROP, NULL); + if (uname) + printf("%s FPGA: %s\n", p, uname); + /* Print out all of the specified loadables */ for (loadables_index = 0; fdt_get_string_index(fit, noffset, diff --git a/common/image.c b/common/image.c index 9824685344b..ec78b7eab33 100644 --- a/common/image.c +++ b/common/image.c @@ -160,6 +160,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" }, { IH_TYPE_ZYNQIMAGE, "zynqimage", "Xilinx Zynq Boot Image" }, { IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" }, + { IH_TYPE_FPGA, "fpga", "FPGA Image" }, { -1, "", "", }, }; diff --git a/doc/uImage.FIT/multi-with-fpga.its b/doc/uImage.FIT/multi-with-fpga.its new file mode 100644 index 00000000000..0cdb31fe91c --- /dev/null +++ b/doc/uImage.FIT/multi-with-fpga.its @@ -0,0 +1,67 @@ +/* + * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs + * This example makes use of the 'loadables' field + */ + +/dts-v1/; + +/ { + description = "Configuration to load fpga before Kernel"; + #address-cells = <1>; + + images { + fdt@1 { + description = "zc706"; + data = /incbin/("/tftpboot/devicetree.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + load = <0x10000000>; + hash@1 { + algo = "md5"; + }; + }; + + fpga@1 { + description = "FPGA"; + data = /incbin/("/tftpboot/download.bit"); + type = "fpga"; + arch = "arm"; + compression = "none"; + load = <0x30000000>; + hash@1 { + algo = "md5"; + }; + }; + + linux_kernel@1 { + description = "Linux"; + data = /incbin/("/tftpboot/zImage"); + type = "kernel"; + arch = "arm"; + os = "linux"; + compression = "none"; + load = <0x8000>; + entry = <0x8000>; + hash@1 { + algo = "md5"; + }; + }; + }; + + configurations { + default = "config@2"; + config@1 { + description = "Linux"; + kernel = "linux_kernel@1"; + fdt = "fdt@1"; + }; + + config@2 { + description = "Linux with fpga"; + kernel = "linux_kernel@1"; + fdt = "fdt@1"; + fpga = "fpga@1"; + }; + }; +}; diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt index 9c527c3e012..3f5418045e5 100644 --- a/doc/uImage.FIT/source_file_format.txt +++ b/doc/uImage.FIT/source_file_format.txt @@ -236,6 +236,7 @@ o config@1 |- kernel = "kernel sub-node unit name" |- ramdisk = "ramdisk sub-node unit name" |- fdt = "fdt sub-node unit-name" + |- fpga = "fpga sub-node unit-name" |- loadables = "loadables sub-node unit-name" @@ -251,6 +252,8 @@ o config@1 "fdt type"). - setup : Unit name of the corresponding setup binary (used for booting an x86 kernel). This contains the setup.bin file built by the kernel. + - fpga : Unit name of the corresponding fpga bitstream blob + (component image node of a "fpga type"). - loadables : Unit name containing a list of additional binaries to be loaded at their given locations. "loadables" is a comma-separated list of strings. U-Boot will load each binary at its given start-address. diff --git a/include/image.h b/include/image.h index a8488f2b392..e2a90ca202b 100644 --- a/include/image.h +++ b/include/image.h @@ -247,8 +247,9 @@ struct lmb; #define IH_TYPE_RKSPI 25 /* Rockchip SPI image */ #define IH_TYPE_ZYNQIMAGE 26 /* Xilinx Zynq Boot Image */ #define IH_TYPE_ZYNQMPIMAGE 27 /* Xilinx ZynqMP Boot Image */ +#define IH_TYPE_FPGA 28 /* FPGA Image */ -#define IH_TYPE_COUNT 28 /* Number of image types */ +#define IH_TYPE_COUNT 29 /* Number of image types */ /* * Compression Types @@ -810,6 +811,7 @@ int bootz_setup(ulong image, ulong *start, ulong *end); #define FIT_LOADABLE_PROP "loadables" #define FIT_DEFAULT_PROP "default" #define FIT_SETUP_PROP "setup" +#define FIT_FPGA_PROP "fpga" #define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE -- cgit v1.3.1 From 62afc601883e788f3f22291202d5b2a23c1a8b06 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 17 May 2016 14:03:50 +0200 Subject: image: Add boot_get_fpga() to load fpga with bootm Add function boot_get_fpga() which find and load bitstream to programmable logic if fpga entry is present. Function is supported on Xilinx devices for full and partial bitstreams in BIN and BIT format. Signed-off-by: Michal Simek Remove additional blankline in image.h --- common/bootm.c | 10 ++++++ common/image-fit.c | 7 ++-- common/image.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++++++++ include/bootstage.h | 1 + include/image.h | 2 ++ 5 files changed, 110 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/common/bootm.c b/common/bootm.c index c965326db41..49414142dcd 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -246,6 +246,16 @@ int bootm_find_images(int flag, int argc, char * const argv[]) #endif #if IMAGE_ENABLE_FIT +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX) + /* find bitstreams */ + ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT, + NULL, NULL); + if (ret) { + printf("FPGA image is corrupted or invalid\n"); + return 1; + } +#endif + /* find all of the loadables */ ret = boot_get_loadable(argc, argv, &images, IH_ARCH_DEFAULT, NULL, NULL); diff --git a/common/image-fit.c b/common/image-fit.c index 8a0ca2a8038..98739572a1b 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -422,7 +422,8 @@ void fit_image_print(const void *fit, int image_noffset, const char *p) } if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) || - (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK)) { + (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK) || + (type == IH_TYPE_FPGA)) { ret = fit_image_get_load(fit, image_noffset, &load); printf("%s Load Address: ", p); if (ret) @@ -1571,6 +1572,8 @@ static const char *fit_get_image_type_property(int type) return FIT_SETUP_PROP; case IH_TYPE_LOADABLE: return FIT_LOADABLE_PROP; + case IH_TYPE_FPGA: + return FIT_FPGA_PROP; } return "unknown"; @@ -1685,7 +1688,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr, fit_image_check_type(fit, noffset, IH_TYPE_KERNEL_NOLOAD)); - os_ok = image_type == IH_TYPE_FLATDT || + os_ok = image_type == IH_TYPE_FLATDT || IH_TYPE_FPGA || fit_image_check_os(fit, noffset, IH_OS_LINUX) || fit_image_check_os(fit, noffset, IH_OS_OPENRTOS); diff --git a/common/image.c b/common/image.c index ec78b7eab33..0be09e5c630 100644 --- a/common/image.c +++ b/common/image.c @@ -32,6 +32,8 @@ #if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT #include #include +#include +#include #endif #include @@ -1212,6 +1214,96 @@ int boot_get_setup(bootm_headers_t *images, uint8_t arch, } #if IMAGE_ENABLE_FIT +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX) +int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images, + uint8_t arch, const ulong *ld_start, ulong * const ld_len) +{ + ulong tmp_img_addr, img_data, img_len; + void *buf; + int conf_noffset; + int fit_img_result; + char *uname, *name; + int err; + int devnum = 0; /* TODO support multi fpga platforms */ + const fpga_desc * const desc = fpga_get_desc(devnum); + xilinx_desc *desc_xilinx = desc->devdesc; + + /* Check to see if the images struct has a FIT configuration */ + if (!genimg_has_config(images)) { + debug("## FIT configuration was not specified\n"); + return 0; + } + + /* + * Obtain the os FIT header from the images struct + * copy from dataflash if needed + */ + tmp_img_addr = map_to_sysmem(images->fit_hdr_os); + tmp_img_addr = genimg_get_image(tmp_img_addr); + buf = map_sysmem(tmp_img_addr, 0); + /* + * Check image type. For FIT images get FIT node + * and attempt to locate a generic binary. + */ + switch (genimg_get_format(buf)) { + case IMAGE_FORMAT_FIT: + conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg); + + err = fdt_get_string_index(buf, conf_noffset, FIT_FPGA_PROP, 0, + (const char **)&uname); + if (err < 0) { + debug("## FPGA image is not specified\n"); + return 0; + } + fit_img_result = fit_image_load(images, + tmp_img_addr, + (const char **)&uname, + &(images->fit_uname_cfg), + arch, + IH_TYPE_FPGA, + BOOTSTAGE_ID_FPGA_INIT, + FIT_LOAD_OPTIONAL_NON_ZERO, + &img_data, &img_len); + + debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n", + uname, img_data, img_len); + + if (fit_img_result < 0) { + /* Something went wrong! */ + return fit_img_result; + } + + if (img_len >= desc_xilinx->size) { + name = "full"; + err = fpga_loadbitstream(devnum, (char *)img_data, + img_len, BIT_FULL); + if (err) + err = fpga_load(devnum, (const void *)img_data, + img_len, BIT_FULL); + } else { + name = "partial"; + err = fpga_loadbitstream(devnum, (char *)img_data, + img_len, BIT_PARTIAL); + if (err) + err = fpga_load(devnum, (const void *)img_data, + img_len, BIT_PARTIAL); + } + + printf(" Programming %s bitstream... ", name); + if (err) + printf("failed\n"); + else + printf("OK\n"); + break; + default: + printf("The given image format is not supported (corrupt?)\n"); + return 1; + } + + return 0; +} +#endif + int boot_get_loadable(int argc, char * const argv[], bootm_headers_t *images, uint8_t arch, const ulong *ld_start, ulong * const ld_len) { diff --git a/include/bootstage.h b/include/bootstage.h index 97653602d3d..0880a680b9e 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -198,6 +198,7 @@ enum bootstage_id { BOOTSTAGE_ID_ACCUM_SCSI, BOOTSTAGE_ID_ACCUM_SPI, BOOTSTAGE_ID_ACCUM_DECOMP, + BOOTSTAGE_ID_FPGA_INIT, /* a few spare for the user, from here */ BOOTSTAGE_ID_USER, diff --git a/include/image.h b/include/image.h index e2a90ca202b..a8f6bd16f69 100644 --- a/include/image.h +++ b/include/image.h @@ -496,6 +496,8 @@ int genimg_get_format(const void *img_addr); int genimg_has_config(bootm_headers_t *images); ulong genimg_get_image(ulong img_addr); +int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images, + uint8_t arch, const ulong *ld_start, ulong * const ld_len); int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, uint8_t arch, ulong *rd_start, ulong *rd_end); -- cgit v1.3.1 From 83c05515d8b428b9dd1ce6e7031048d4c1971152 Mon Sep 17 00:00:00 2001 From: Kevin Smith Date: Thu, 31 Mar 2016 19:33:12 +0000 Subject: net: Remove unused mv88e61xx switch driver No boards are using this driver. Remove in preparation for a new driver with integrated PHY support. Signed-off-by: Kevin Smith Acked-by: Joe Hershberger Cc: Prafulla Wadaskar Cc: Albert ARIBAUD Cc: Stefan Roese Cc: Marek Vasut --- drivers/net/phy/mv88e61xx.c | 537 -------------------------------------------- drivers/net/phy/mv88e61xx.h | 61 ----- include/netdev.h | 58 ----- 3 files changed, 656 deletions(-) delete mode 100644 drivers/net/phy/mv88e61xx.c delete mode 100644 drivers/net/phy/mv88e61xx.h (limited to 'include') diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c deleted file mode 100644 index 302abe86c6e..00000000000 --- a/drivers/net/phy/mv88e61xx.c +++ /dev/null @@ -1,537 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include "mv88e61xx.h" - -/* - * Uncomment either of the following line for local debug control; - * otherwise global debug control will apply. - */ - -/* #undef DEBUG */ -/* #define DEBUG */ - -#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE -/* Chip Address mode - * The Switch support two modes of operation - * 1. single chip mode and - * 2. Multi-chip mode - * Refer section 9.2 &9.3 in chip datasheet-02 for more details - * - * By default single chip mode is configured - * multichip mode operation can be configured in board header - */ -static int mv88e61xx_busychk_multic(char *name, u32 devaddr) -{ - u16 reg = 0; - u32 timeout = MV88E61XX_PHY_TIMEOUT; - - /* Poll till SMIBusy bit is clear */ - do { - miiphy_read(name, devaddr, 0x0, ®); - if (timeout-- == 0) { - printf("SMI busy timeout\n"); - return -1; - } - } while (reg & (1 << 15)); - return 0; -} - -static void mv88e61xx_switch_write(char *name, u32 phy_adr, - u32 reg_ofs, u16 data) -{ - u16 mii_dev_addr; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { - printf("Error..could not read PHY dev address\n"); - return; - } - mv88e61xx_busychk_multic(name, mii_dev_addr); - /* Write data to Switch indirect data register */ - miiphy_write(name, mii_dev_addr, 0x1, data); - /* Write command to Switch indirect command register (write) */ - miiphy_write(name, mii_dev_addr, 0x0, - reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 << - 15)); -} - -static void mv88e61xx_switch_read(char *name, u32 phy_adr, - u32 reg_ofs, u16 *data) -{ - u16 mii_dev_addr; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { - printf("Error..could not read PHY dev address\n"); - return; - } - mv88e61xx_busychk_multic(name, mii_dev_addr); - /* Write command to Switch indirect command register (read) */ - miiphy_write(name, mii_dev_addr, 0x0, - reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 << - 15)); - mv88e61xx_busychk_multic(name, mii_dev_addr); - /* Read data from Switch indirect data register */ - miiphy_read(name, mii_dev_addr, 0x1, data); -} -#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ - -/* - * Convenience macros for switch device/port reads/writes - * These macros output valid 'mv88e61xx' U_BOOT_CMDs - */ - -#ifndef DEBUG -#define WR_SWITCH_REG wr_switch_reg -#define RD_SWITCH_REG rd_switch_reg -#define WR_SWITCH_PORT_REG(n, p, r, d) \ - WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d) -#define RD_SWITCH_PORT_REG(n, p, r, d) \ - RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d) -#else -static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data) -{ - printf("mv88e61xx %s dev %02x reg %02x write %04x\n", - name, dev_adr, reg_ofs, data); - wr_switch_reg(name, dev_adr, reg_ofs, data); -} -static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data) -{ - rd_switch_reg(name, dev_adr, reg_ofs, data); - printf("mv88e61xx %s dev %02x reg %02x read %04x\n", - name, dev_adr, reg_ofs, *data); -} -static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs, - u16 data) -{ - printf("mv88e61xx %s port %02x reg %02x write %04x\n", - name, prt_adr, reg_ofs, data); - wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data); -} -static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs, - u16 *data) -{ - rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data); - printf("mv88e61xx %s port %02x reg %02x read %04x\n", - name, prt_adr, reg_ofs, *data); -} -#endif - -/* - * Local functions to read/write registers on the switch PHYs. - * NOTE! This goes through switch, not direct miiphy, writes and reads! - */ - -/* - * Make sure SMIBusy bit cleared before another - * SMI operation can take place - */ -static int mv88e61xx_busychk(char *name) -{ - u16 reg = 0; - u32 timeout = MV88E61XX_PHY_TIMEOUT; - do { - rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, ®); - if (timeout-- == 0) { - printf("SMI busy timeout\n"); - return -1; - } - } while (reg & 1 << 15); /* busy mask */ - return 0; -} - -static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy, - u32 reg, u16 data) -{ - /* write switch data reg then cmd reg then check completion */ - wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, - data); - wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, - (MV88E61XX_PHY_WRITE_CMD | (phy << 5) | reg)); - return mv88e61xx_busychk(name); -} - -static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy, - u32 reg, u16 *data) -{ - /* write switch cmd reg, check for completion */ - wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, - (MV88E61XX_PHY_READ_CMD | (phy << 5) | reg)); - if (mv88e61xx_busychk(name)) - return -1; - /* read switch data reg and return success */ - rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data); - return 0; -} - -/* - * Convenience macros for switch PHY reads/writes - */ - -#ifndef DEBUG -#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write -#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read -#else -static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr, - u32 reg_ofs, u16 data) -{ - int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data); - if (r) - printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n", - name, phy_adr, reg_ofs); - else - printf("mv88e61xx %s phy %02x reg %02x write %04x\n", - name, phy_adr, reg_ofs, data); - return r; -} -static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr, - u32 reg_ofs, u16 *data) -{ - int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data); - if (r) - printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n", - name, phy_adr, reg_ofs); - else - printf("mv88e61xx %s phy %02x reg %02x read %04x\n", - name, phy_adr, reg_ofs, *data); - return r; -} -#endif - -static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig) -{ - u32 prt; - u16 reg; - char *name = swconfig->name; - u32 port_mask = swconfig->ports_enabled; - - /* apply internal vlan config */ - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { - /* only for enabled ports */ - if ((1 << prt) & port_mask) { - /* take vlan map from swconfig */ - u8 vlanmap = swconfig->vlancfg[prt]; - /* remove disabled ports from vlan map */ - vlanmap &= swconfig->ports_enabled; - /* apply vlan map to port */ - RD_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_VMAP_REG, ®); - reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1); - reg |= vlanmap; - WR_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_VMAP_REG, reg); - } - } -} - -/* - * Power up the specified port and reset PHY - */ -static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy) -{ - char *name = swconfig->name; - - /* Write Copper Specific control reg1 (0x10) for- - * Enable Phy power up - * Energy Detect on (sense&Xmit NLP Periodically - * reset other settings default - */ - if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360)) - return -1; - - /* Write PHY ctrl reg (0x0) to apply - * Phy reset (set bit 15 low) - * reset other default values - */ - if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140)) - return -1; - - return 0; -} - -/* - * Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3) - * is set to "On-1000Mb/s Link, Off Else" - * This function sets it to "On-Link, Blink-Activity, Off-NoLink" - * - * This is optional settings may be needed on some boards - * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s - * Link status - */ -static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy) -{ - char *name = swconfig->name; - - if (swconfig->led_init != MV88E61XX_LED_INIT_EN) - return 0; - - /* set page address to 3 */ - if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003)) - return -1; - - /* - * set LED Func Ctrl reg - * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink - */ - if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001)) - return -1; - - /* set page address to 0 */ - if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000)) - return -1; - - return 0; -} - -/* - * Reverse Transmit polarity for Media Dependent Interface - * Pins (MDIP) bits in Copper Specific Control Register 3 - * (Page 0, Reg 20 for each phy (except cpu port) - * Reference: Section 1.1 Switch datasheet-3 - * - * This is optional settings may be needed on some boards - * for PHY<->magnetics h/w tuning - */ -static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy) -{ - char *name = swconfig->name; - - if (swconfig->mdip != MV88E61XX_MDIP_REVERSE) - return 0; - - /*Reverse MDIP/N[3:0] bits */ - if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f)) - return -1; - - return 0; -} - -/* - * Marvell 88E61XX Switch initialization - */ -int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) -{ - u32 prt; - u16 reg; - char *idstr; - char *name = swconfig->name; - int time; - - if (miiphy_set_current_dev(name)) { - printf("%s failed\n", __FUNCTION__); - return -1; - } - - if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) { - swconfig->cpuport = (1 << 5); - printf("Invalid cpu port config, using default port5\n"); - } - - RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, ®); - switch (reg &= 0xfff0) { - case 0x1610: - idstr = "88E6161"; - break; - case 0x1650: - idstr = "88E6165"; - break; - case 0x1210: - idstr = "88E6123"; - /* ports 2,3,4 not available */ - swconfig->ports_enabled &= 0x023; - break; - default: - /* Could not detect switch id */ - idstr = "88E61??"; - break; - } - - /* be sure all ports are disabled */ - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { - RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, ®); - reg &= ~0x3; - WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg); - } - - /* wait 2 ms for queues to drain */ - udelay(2000); - - /* reset switch */ - RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, ®); - reg |= 0x8000; - WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg); - - /* wait up to 1 second for switch reset complete */ - for (time = 1000; time; time--) { - RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR, - ®); - if ((reg & 0xc800) == 0xc800) - break; - udelay(1000); - } - if (!time) - return -1; - - /* Port based VLANs configuration */ - mv88e61xx_port_vlan_config(swconfig); - - if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) { - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 9.5 of chip datasheet-02 - */ - /*Force port link down */ - WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10); - /* configure port RGMII delay */ - WR_SWITCH_PORT_REG(name, 4, - MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7); - RD_SWITCH_PORT_REG(name, 5, - MV88E61XX_RGMII_TIMECTRL_REG, ®); - WR_SWITCH_PORT_REG(name, 5, - MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18); - WR_SWITCH_PORT_REG(name, 4, - MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); - /* Force port to RGMII FDX 1000Base then up */ - WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e); - WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e); - } - - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { - - /* configure port's PHY */ - if (!((1 << prt) & swconfig->cpuport)) { - /* port 4 has phy 6, not 4 */ - int phy = (prt == 4) ? 6 : prt; - if (mv88361xx_powerup(swconfig, phy)) - return -1; - if (mv88361xx_reverse_mdipn(swconfig, phy)) - return -1; - if (mv88361xx_led_init(swconfig, phy)) - return -1; - } - - /* set port VID to port+1 except for cpu port */ - if (!((1 << prt) & swconfig->cpuport)) { - RD_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_VID_REG, ®); - WR_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_VID_REG, - (reg & ~1023) | (prt+1)); - } - - /*Program port state */ - RD_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_CTRL_REG, ®); - WR_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_CTRL_REG, - reg | (swconfig->portstate & 0x03)); - - } - - printf("%s Initialized on %s\n", idstr, name); - return 0; -} - -#ifdef CONFIG_MV88E61XX_CMD -static int -do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *name, *endp; - int write = 0; - enum { dev, prt, phy } target = dev; - u32 addrlo, addrhi, addr; - u32 reglo, reghi, reg; - u16 data, rdata; - - if (argc < 7) - return -1; - - name = argv[1]; - - if (strcmp(argv[2], "phy") == 0) - target = phy; - else if (strcmp(argv[2], "port") == 0) - target = prt; - else if (strcmp(argv[2], "dev") != 0) - return 1; - - addrlo = simple_strtoul(argv[3], &endp, 16); - - if (!*endp) { - addrhi = addrlo; - } else { - while (*endp < '0' || *endp > '9') - endp++; - addrhi = simple_strtoul(endp, NULL, 16); - } - - reglo = simple_strtoul(argv[5], &endp, 16); - if (!*endp) { - reghi = reglo; - } else { - while (*endp < '0' || *endp > '9') - endp++; - reghi = simple_strtoul(endp, NULL, 16); - } - - if (strcmp(argv[6], "write") == 0) - write = 1; - else if (strcmp(argv[6], "read") != 0) - return 1; - - data = simple_strtoul(argv[7], NULL, 16); - - for (addr = addrlo; addr <= addrhi; addr++) { - for (reg = reglo; reg <= reghi; reg++) { - if (write) { - if (target == phy) - mv88e61xx_switch_miiphy_write( - name, addr, reg, data); - else if (target == prt) - wr_switch_reg(name, - addr+MV88E61XX_PRT_OFST, - reg, data); - else - wr_switch_reg(name, addr, reg, data); - } else { - if (target == phy) - mv88e61xx_switch_miiphy_read( - name, addr, reg, &rdata); - else if (target == prt) - rd_switch_reg(name, - addr+MV88E61XX_PRT_OFST, - reg, &rdata); - else - rd_switch_reg(name, addr, reg, &rdata); - printf("%s %s %s %02x %s %02x %s %04x\n", - argv[0], argv[1], argv[2], addr, - argv[4], reg, argv[6], rdata); - if (write && argc == 7 && rdata != data) - return 1; - } - } - } - return 0; -} - -U_BOOT_CMD(mv88e61xx, 8, 0, do_switch, - "Read or write mv88e61xx switch registers", - " dev|port|phy reg write \n" - " dev|port|phy reg read []\n" - " - read/write switch device, port or phy at (addr,reg)\n" - " addr=0..0x1C for dev, 0..5 for port or phy.\n" - " reg=0..0x1F.\n" - " data=0..0xFFFF (tested if present against actual read).\n" - " All numeric parameters are assumed to be hex.\n" - " and < arguments can be ranges (x..y)" -); -#endif /* CONFIG_MV88E61XX_CMD */ diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h deleted file mode 100644 index 9c62e4a7756..00000000000 --- a/drivers/net/phy/mv88e61xx.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MV88E61XX_H -#define _MV88E61XX_H - -#include - -#define MV88E61XX_CPU_PORT 0x5 - -#define MV88E61XX_PHY_TIMEOUT 100000 - -/* port dev-addr (= port + 0x10) */ -#define MV88E61XX_PRT_OFST 0x10 -/* port registers */ -#define MV88E61XX_PCS_CTRL_REG 0x1 -#define MV88E61XX_PRT_CTRL_REG 0x4 -#define MV88E61XX_PRT_VMAP_REG 0x6 -#define MV88E61XX_PRT_VID_REG 0x7 -#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A - -/* global registers dev-addr */ -#define MV88E61XX_GLBREG_DEVADR 0x1B -/* global registers */ -#define MV88E61XX_SGSR 0x00 -#define MV88E61XX_SGCR 0x04 - -/* global 2 registers dev-addr */ -#define MV88E61XX_GLB2REG_DEVADR 0x1C -/* global 2 registers */ -#define MV88E61XX_PHY_CMD 0x18 -#define MV88E61XX_PHY_DATA 0x19 -/* global 2 phy commands */ -#define MV88E61XX_PHY_WRITE_CMD 0x9400 -#define MV88E61XX_PHY_READ_CMD 0x9800 - -#define MV88E61XX_BUSY_OFST 15 -#define MV88E61XX_MODE_OFST 12 -#define MV88E61XX_OP_OFST 10 -#define MV88E61XX_ADDR_OFST 5 - -#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE -static int mv88e61xx_busychk_multic(char *name, u32 devaddr); -static void mv88e61xx_switch_write(char *name, u32 phy_adr, - u32 reg_ofs, u16 data); -static void mv88e61xx_switch_read(char *name, u32 phy_adr, - u32 reg_ofs, u16 *data); -#define wr_switch_reg mv88e61xx_switch_write -#define rd_switch_reg mv88e61xx_switch_read -#else -/* switch appears a s simple PHY and can thus use miiphy */ -#define wr_switch_reg miiphy_write -#define rd_switch_reg miiphy_read -#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ - -#endif /* _MV88E61XX_H */ diff --git a/include/netdev.h b/include/netdev.h index 244f23f93c3..7a211bc609d 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -134,64 +134,6 @@ static inline int pci_eth_init(bd_t *bis) return num; } -/* - * Boards with mv88e61xx switch can use this by defining - * CONFIG_MV88E61XX_SWITCH in respective board configheader file - * the stuct and enums here are used to specify switch configuration params - */ -#if defined(CONFIG_MV88E61XX_SWITCH) - -/* constants for any 88E61xx switch */ -#define MV88E61XX_MAX_PORTS_NUM 6 - -enum mv88e61xx_cfg_mdip { - MV88E61XX_MDIP_NOCHANGE, - MV88E61XX_MDIP_REVERSE -}; - -enum mv88e61xx_cfg_ledinit { - MV88E61XX_LED_INIT_DIS, - MV88E61XX_LED_INIT_EN -}; - -enum mv88e61xx_cfg_rgmiid { - MV88E61XX_RGMII_DELAY_DIS, - MV88E61XX_RGMII_DELAY_EN -}; - -enum mv88e61xx_cfg_prtstt { - MV88E61XX_PORTSTT_DISABLED, - MV88E61XX_PORTSTT_BLOCKING, - MV88E61XX_PORTSTT_LEARNING, - MV88E61XX_PORTSTT_FORWARDING -}; - -struct mv88e61xx_config { - char *name; - u8 vlancfg[MV88E61XX_MAX_PORTS_NUM]; - enum mv88e61xx_cfg_rgmiid rgmii_delay; - enum mv88e61xx_cfg_prtstt portstate; - enum mv88e61xx_cfg_ledinit led_init; - enum mv88e61xx_cfg_mdip mdip; - u32 ports_enabled; - u8 cpuport; -}; - -/* - * Common mappings for Internal VLANs - * These mappings consider that all ports are useable; the driver - * will mask inexistent/unused ports. - */ - -/* Switch mode : routes any port to any port */ -#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F } - -/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */ -#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F } - -int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); -#endif /* CONFIG_MV88E61XX_SWITCH */ - struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id); #ifdef CONFIG_PHYLIB struct phy_device; -- cgit v1.3.1 From 24ae3961f811ee79e6c98474e21e07f8ce222dfc Mon Sep 17 00:00:00 2001 From: Kevin Smith Date: Thu, 31 Mar 2016 19:33:12 +0000 Subject: net: phy: Add PHY driver for mv88e61xx switches The previous mv88e61xx driver was a driver for configuring the switch, but did not integrate with the PHY/networking system, so it could not be used as a PHY by U-boot. This is a complete rework to support this device as a PHY. Signed-off-by: Kevin Smith Acked-by: Prafulla Wadaskar Cc: Albert ARIBAUD Cc: Joe Hershberger Cc: Stefan Roese Cc: Marek Vasut Acked-by: Joe Hershberger --- drivers/net/phy/mv88e61xx.c | 1017 +++++++++++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 3 + include/phy.h | 1 + 3 files changed, 1021 insertions(+) create mode 100644 drivers/net/phy/mv88e61xx.c (limited to 'include') diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c new file mode 100644 index 00000000000..74d56098b5c --- /dev/null +++ b/drivers/net/phy/mv88e61xx.c @@ -0,0 +1,1017 @@ +/* + * (C) Copyright 2015 + * Elecsys Corporation + * Kevin Smith + * + * Original driver: + * (C) Copyright 2009 + * Marvell Semiconductor + * Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * PHY driver for mv88e61xx ethernet switches. + * + * This driver configures the mv88e61xx for basic use as a PHY. The switch + * supports a VLAN configuration that determines how traffic will be routed + * between the ports. This driver uses a simple configuration that routes + * traffic from each PHY port only to the CPU port, and from the CPU port to + * any PHY port. + * + * The configuration determines which PHY ports to activate using the + * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit + * 1 activates port 1, etc. Do not set the bit for the port the CPU is + * connected to unless it is connected over a PHY interface (not MII). + * + * This driver was written for and tested on the mv88e6176 with an SGMII + * connection. Other configurations should be supported, but some additions or + * changes may be required. + */ + +#include + +#include +#include +#include +#include +#include + +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 + +#define PORT_COUNT 7 +#define PORT_MASK ((1 << PORT_COUNT) - 1) + +/* Device addresses */ +#define DEVADDR_PHY(p) (p) +#define DEVADDR_PORT(p) (0x10 + (p)) +#define DEVADDR_SERDES 0x0F +#define DEVADDR_GLOBAL_1 0x1B +#define DEVADDR_GLOBAL_2 0x1C + +/* SMI indirection registers for multichip addressing mode */ +#define SMI_CMD_REG 0x00 +#define SMI_DATA_REG 0x01 + +/* Global registers */ +#define GLOBAL1_STATUS 0x00 +#define GLOBAL1_CTRL 0x04 +#define GLOBAL1_MON_CTRL 0x1A + +/* Global 2 registers */ +#define GLOBAL2_REG_PHY_CMD 0x18 +#define GLOBAL2_REG_PHY_DATA 0x19 + +/* Port registers */ +#define PORT_REG_STATUS 0x00 +#define PORT_REG_PHYS_CTRL 0x01 +#define PORT_REG_SWITCH_ID 0x03 +#define PORT_REG_CTRL 0x04 +#define PORT_REG_VLAN_MAP 0x06 +#define PORT_REG_VLAN_ID 0x07 + +/* Phy registers */ +#define PHY_REG_CTRL1 0x10 +#define PHY_REG_STATUS1 0x11 +#define PHY_REG_PAGE 0x16 + +/* Serdes registers */ +#define SERDES_REG_CTRL_1 0x10 + +/* Phy page numbers */ +#define PHY_PAGE_COPPER 0 +#define PHY_PAGE_SERDES 1 + +/* Register fields */ +#define GLOBAL1_CTRL_SWRESET BIT(15) + +#define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4 +#define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4 + +#define PORT_REG_STATUS_LINK BIT(11) +#define PORT_REG_STATUS_DUPLEX BIT(10) + +#define PORT_REG_STATUS_SPEED_SHIFT 8 +#define PORT_REG_STATUS_SPEED_WIDTH 2 +#define PORT_REG_STATUS_SPEED_10 0 +#define PORT_REG_STATUS_SPEED_100 1 +#define PORT_REG_STATUS_SPEED_1000 2 + +#define PORT_REG_STATUS_CMODE_MASK 0xF +#define PORT_REG_STATUS_CMODE_100BASE_X 0x8 +#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 +#define PORT_REG_STATUS_CMODE_SGMII 0xa + +#define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5) +#define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4) + +#define PORT_REG_CTRL_PSTATE_SHIFT 0 +#define PORT_REG_CTRL_PSTATE_WIDTH 2 + +#define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0 +#define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12 + +#define PORT_REG_VLAN_MAP_TABLE_SHIFT 0 +#define PORT_REG_VLAN_MAP_TABLE_WIDTH 11 + +#define SERDES_REG_CTRL_1_FORCE_LINK BIT(10) + +#define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8 +#define PHY_REG_CTRL1_ENERGY_DET_WIDTH 2 + +/* Field values */ +#define PORT_REG_CTRL_PSTATE_DISABLED 0 +#define PORT_REG_CTRL_PSTATE_FORWARD 3 + +#define PHY_REG_CTRL1_ENERGY_DET_OFF 0 +#define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2 +#define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3 + +/* PHY Status Register */ +#define PHY_REG_STATUS1_SPEED 0xc000 +#define PHY_REG_STATUS1_GBIT 0x8000 +#define PHY_REG_STATUS1_100 0x4000 +#define PHY_REG_STATUS1_DUPLEX 0x2000 +#define PHY_REG_STATUS1_SPDDONE 0x0800 +#define PHY_REG_STATUS1_LINK 0x0400 +#define PHY_REG_STATUS1_ENERGY 0x0010 + +/* + * Macros for building commands for indirect addressing modes. These are valid + * for both the indirect multichip addressing mode and the PHY indirection + * required for the writes to any PHY register. + */ +#define SMI_BUSY BIT(15) +#define SMI_CMD_CLAUSE_22 BIT(12) +#define SMI_CMD_CLAUSE_22_OP_READ (2 << 10) +#define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10) + +#define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \ + SMI_CMD_CLAUSE_22_OP_READ) +#define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \ + SMI_CMD_CLAUSE_22_OP_WRITE) + +#define SMI_CMD_ADDR_SHIFT 5 +#define SMI_CMD_ADDR_WIDTH 5 +#define SMI_CMD_REG_SHIFT 0 +#define SMI_CMD_REG_WIDTH 5 + +/* Check for required macros */ +#ifndef CONFIG_MV88E61XX_PHY_PORTS +#error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \ + to activate +#endif +#ifndef CONFIG_MV88E61XX_CPU_PORT +#error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to +#endif + +/* ID register values for different switch models */ +#define PORT_SWITCH_ID_6172 0x1720 +#define PORT_SWITCH_ID_6176 0x1760 +#define PORT_SWITCH_ID_6240 0x2400 +#define PORT_SWITCH_ID_6352 0x3520 + +struct mv88e61xx_phy_priv { + struct mii_dev *mdio_bus; + int smi_addr; + int id; +}; + +static inline int smi_cmd(int cmd, int addr, int reg) +{ + cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH, + addr); + cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg); + return cmd; +} + +static inline int smi_cmd_read(int addr, int reg) +{ + return smi_cmd(SMI_CMD_READ, addr, reg); +} + +static inline int smi_cmd_write(int addr, int reg) +{ + return smi_cmd(SMI_CMD_WRITE, addr, reg); +} + +__weak int mv88e61xx_hw_reset(struct phy_device *phydev) +{ + return 0; +} + +/* Wait for the current SMI indirect command to complete */ +static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr) +{ + int val; + u32 timeout = 100; + + do { + val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG); + if (val >= 0 && (val & SMI_BUSY) == 0) + return 0; + + mdelay(1); + } while (--timeout); + + puts("SMI busy timeout\n"); + return -ETIMEDOUT; +} + +/* + * The mv88e61xx has three types of addresses: the smi bus address, the device + * address, and the register address. The smi bus address distinguishes it on + * the smi bus from other PHYs or switches. The device address determines + * which on-chip register set you are reading/writing (the various PHYs, their + * associated ports, or global configuration registers). The register address + * is the offset of the register you are reading/writing. + * + * When the mv88e61xx is hardware configured to have address zero, it behaves in + * single-chip addressing mode, where it responds to all SMI addresses, using + * the smi address as its device address. This obviously only works when this + * is the only chip on the SMI bus. This allows the driver to access device + * registers without using indirection. When the chip is configured to a + * non-zero address, it only responds to that SMI address and requires indirect + * writes to access the different device addresses. + */ +static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg) +{ + struct mv88e61xx_phy_priv *priv = phydev->priv; + struct mii_dev *mdio_bus = priv->mdio_bus; + int smi_addr = priv->smi_addr; + int res; + + /* In single-chip mode, the device can be addressed directly */ + if (smi_addr == 0) + return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg); + + /* Wait for the bus to become free */ + res = mv88e61xx_smi_wait(mdio_bus, smi_addr); + if (res < 0) + return res; + + /* Issue the read command */ + res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG, + smi_cmd_read(dev, reg)); + if (res < 0) + return res; + + /* Wait for the read command to complete */ + res = mv88e61xx_smi_wait(mdio_bus, smi_addr); + if (res < 0) + return res; + + /* Read the data */ + res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG); + if (res < 0) + return res; + + return bitfield_extract(res, 0, 16); +} + +/* See the comment above mv88e61xx_reg_read */ +static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg, + u16 val) +{ + struct mv88e61xx_phy_priv *priv = phydev->priv; + struct mii_dev *mdio_bus = priv->mdio_bus; + int smi_addr = priv->smi_addr; + int res; + + /* In single-chip mode, the device can be addressed directly */ + if (smi_addr == 0) { + return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg, + val); + } + + /* Wait for the bus to become free */ + res = mv88e61xx_smi_wait(mdio_bus, smi_addr); + if (res < 0) + return res; + + /* Set the data to write */ + res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, + SMI_DATA_REG, val); + if (res < 0) + return res; + + /* Issue the write command */ + res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG, + smi_cmd_write(dev, reg)); + if (res < 0) + return res; + + /* Wait for the write command to complete */ + res = mv88e61xx_smi_wait(mdio_bus, smi_addr); + if (res < 0) + return res; + + return 0; +} + +static int mv88e61xx_phy_wait(struct phy_device *phydev) +{ + int val; + u32 timeout = 100; + + do { + val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2, + GLOBAL2_REG_PHY_CMD); + if (val >= 0 && (val & SMI_BUSY) == 0) + return 0; + + mdelay(1); + } while (--timeout); + + return -ETIMEDOUT; +} + +static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev, + int devad, int reg) +{ + struct phy_device *phydev; + int res; + + phydev = (struct phy_device *)smi_wrapper->priv; + + /* Issue command to read */ + res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2, + GLOBAL2_REG_PHY_CMD, + smi_cmd_read(dev, reg)); + + /* Wait for data to be read */ + res = mv88e61xx_phy_wait(phydev); + if (res < 0) + return res; + + /* Read retrieved data */ + return mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2, + GLOBAL2_REG_PHY_DATA); +} + +static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev, + int devad, int reg, u16 data) +{ + struct phy_device *phydev; + int res; + + phydev = (struct phy_device *)smi_wrapper->priv; + + /* Set the data to write */ + res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2, + GLOBAL2_REG_PHY_DATA, data); + if (res < 0) + return res; + /* Issue the write command */ + res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2, + GLOBAL2_REG_PHY_CMD, + smi_cmd_write(dev, reg)); + if (res < 0) + return res; + + /* Wait for command to complete */ + return mv88e61xx_phy_wait(phydev); +} + +/* Wrapper function to make calls to phy_read_indirect simpler */ +static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg) +{ + return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy), + MDIO_DEVAD_NONE, reg); +} + +/* Wrapper function to make calls to phy_read_indirect simpler */ +static int mv88e61xx_phy_write(struct phy_device *phydev, int phy, + int reg, u16 val) +{ + return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy), + MDIO_DEVAD_NONE, reg, val); +} + +static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg) +{ + return mv88e61xx_reg_read(phydev, DEVADDR_PORT(port), reg); +} + +static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg, + u16 val) +{ + return mv88e61xx_reg_write(phydev, DEVADDR_PORT(port), reg, val); +} + +static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page) +{ + return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page); +} + +static int mv88e61xx_get_switch_id(struct phy_device *phydev) +{ + int res; + + res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID); + if (res < 0) + return res; + return res & 0xfff0; +} + +static bool mv88e61xx_6352_family(struct phy_device *phydev) +{ + struct mv88e61xx_phy_priv *priv = phydev->priv; + + switch (priv->id) { + case PORT_SWITCH_ID_6172: + case PORT_SWITCH_ID_6176: + case PORT_SWITCH_ID_6240: + case PORT_SWITCH_ID_6352: + return true; + } + return false; +} + +static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port) +{ + int res; + + res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS); + if (res < 0) + return res; + return res & PORT_REG_STATUS_CMODE_MASK; +} + +static int mv88e61xx_parse_status(struct phy_device *phydev) +{ + unsigned int speed; + unsigned int mii_reg; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1); + + if ((mii_reg & PHY_REG_STATUS1_LINK) && + !(mii_reg & PHY_REG_STATUS1_SPDDONE)) { + int i = 0; + + puts("Waiting for PHY realtime link"); + while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) { + /* Timeout reached ? */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts(" TIMEOUT !\n"); + phydev->link = 0; + break; + } + + if ((i++ % 1000) == 0) + putc('.'); + udelay(1000); + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, + PHY_REG_STATUS1); + } + puts(" done\n"); + udelay(500000); /* another 500 ms (results in faster booting) */ + } else { + if (mii_reg & PHY_REG_STATUS1_LINK) + phydev->link = 1; + else + phydev->link = 0; + } + + if (mii_reg & PHY_REG_STATUS1_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + speed = mii_reg & PHY_REG_STATUS1_SPEED; + + switch (speed) { + case PHY_REG_STATUS1_GBIT: + phydev->speed = SPEED_1000; + break; + case PHY_REG_STATUS1_100: + phydev->speed = SPEED_100; + break; + default: + phydev->speed = SPEED_10; + break; + } + + return 0; +} + +static int mv88e61xx_switch_reset(struct phy_device *phydev) +{ + int time; + int val; + u8 port; + + /* Disable all ports */ + for (port = 0; port < PORT_COUNT; port++) { + val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL); + if (val < 0) + return val; + val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT, + PORT_REG_CTRL_PSTATE_WIDTH, + PORT_REG_CTRL_PSTATE_DISABLED); + val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val); + if (val < 0) + return val; + } + + /* Wait 2 ms for queues to drain */ + udelay(2000); + + /* Reset switch */ + val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_CTRL); + if (val < 0) + return val; + val |= GLOBAL1_CTRL_SWRESET; + val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1, + GLOBAL1_CTRL, val); + if (val < 0) + return val; + + /* Wait up to 1 second for switch reset complete */ + for (time = 1000; time; time--) { + val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, + GLOBAL1_CTRL); + if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0)) + break; + udelay(1000); + } + if (!time) + return -ETIMEDOUT; + + return 0; +} + +static int mv88e61xx_serdes_init(struct phy_device *phydev) +{ + int val; + + val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES); + if (val < 0) + return val; + + /* Power up serdes module */ + val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR); + if (val < 0) + return val; + val &= ~(BMCR_PDOWN); + val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val); + if (val < 0) + return val; + + return 0; +} + +static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port) +{ + int val; + + val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL); + if (val < 0) + return val; + val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT, + PORT_REG_CTRL_PSTATE_WIDTH, + PORT_REG_CTRL_PSTATE_FORWARD); + val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val); + if (val < 0) + return val; + + return 0; +} + +static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port, + u8 mask) +{ + int val; + + /* Set VID to port number plus one */ + val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID); + if (val < 0) + return val; + val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT, + PORT_REG_VLAN_ID_DEF_VID_WIDTH, + port + 1); + val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val); + if (val < 0) + return val; + + /* Set VID mask */ + val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP); + if (val < 0) + return val; + val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT, + PORT_REG_VLAN_MAP_TABLE_WIDTH, + mask); + val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val); + if (val < 0) + return val; + + return 0; +} + +static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port) +{ + int res; + int val; + bool forced = false; + + val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS); + if (val < 0) + return val; + if (!(val & PORT_REG_STATUS_LINK)) { + /* Temporarily force link to read port configuration */ + u32 timeout = 100; + forced = true; + + val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); + if (val < 0) + return val; + val |= (PORT_REG_PHYS_CTRL_LINK_FORCE | + PORT_REG_PHYS_CTRL_LINK_VALUE); + val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, + val); + if (val < 0) + return val; + + /* Wait for status register to reflect forced link */ + do { + val = mv88e61xx_port_read(phydev, port, + PORT_REG_STATUS); + if (val < 0) + goto unforce; + if (val & PORT_REG_STATUS_LINK) + break; + } while (--timeout); + + if (timeout == 0) { + res = -ETIMEDOUT; + goto unforce; + } + } + + if (val & PORT_REG_STATUS_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT, + PORT_REG_STATUS_SPEED_WIDTH); + switch (val) { + case PORT_REG_STATUS_SPEED_1000: + phydev->speed = SPEED_1000; + break; + case PORT_REG_STATUS_SPEED_100: + phydev->speed = SPEED_100; + break; + default: + phydev->speed = SPEED_10; + break; + } + + res = 0; + +unforce: + if (forced) { + val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); + if (val < 0) + return val; + val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE | + PORT_REG_PHYS_CTRL_LINK_VALUE); + val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, + val); + if (val < 0) + return val; + } + + return res; +} + +static int mv88e61xx_set_cpu_port(struct phy_device *phydev) +{ + int val; + + /* Set CPUDest */ + val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_MON_CTRL); + if (val < 0) + return val; + val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT, + GLOBAL1_MON_CTRL_CPUDEST_WIDTH, + CONFIG_MV88E61XX_CPU_PORT); + val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1, + GLOBAL1_MON_CTRL, val); + if (val < 0) + return val; + + /* Allow CPU to route to any port */ + val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT); + val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val); + if (val < 0) + return val; + + /* Enable CPU port */ + val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT); + if (val < 0) + return val; + + val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT); + if (val < 0) + return val; + + /* If CPU is connected to serdes, initialize serdes */ + if (mv88e61xx_6352_family(phydev)) { + val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT); + if (val < 0) + return val; + if (val == PORT_REG_STATUS_CMODE_100BASE_X || + val == PORT_REG_STATUS_CMODE_1000BASE_X || + val == PORT_REG_STATUS_CMODE_SGMII) { + val = mv88e61xx_serdes_init(phydev); + if (val < 0) + return val; + } + } + + return 0; +} + +static int mv88e61xx_switch_init(struct phy_device *phydev) +{ + static int init; + int res; + + if (init) + return 0; + + res = mv88e61xx_switch_reset(phydev); + if (res < 0) + return res; + + res = mv88e61xx_set_cpu_port(phydev); + if (res < 0) + return res; + + init = 1; + + return 0; +} + +static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy) +{ + int val; + + val = mv88e61xx_phy_read(phydev, phy, MII_BMCR); + if (val < 0) + return val; + val &= ~(BMCR_PDOWN); + val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val); + if (val < 0) + return val; + + return 0; +} + +static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy) +{ + int val; + + /* + * Enable energy-detect sensing on PHY, used to determine when a PHY + * port is physically connected + */ + val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1); + if (val < 0) + return val; + val = bitfield_replace(val, PHY_REG_CTRL1_ENERGY_DET_SHIFT, + PHY_REG_CTRL1_ENERGY_DET_WIDTH, + PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT); + val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val); + if (val < 0) + return val; + + return 0; +} + +static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy) +{ + int val; + + val = mv88e61xx_port_enable(phydev, phy); + if (val < 0) + return val; + + val = mv88e61xx_port_set_vlan(phydev, phy, + 1 << CONFIG_MV88E61XX_CPU_PORT); + if (val < 0) + return val; + + return 0; +} + +static int mv88e61xx_probe(struct phy_device *phydev) +{ + struct mii_dev *smi_wrapper; + struct mv88e61xx_phy_priv *priv; + int res; + + res = mv88e61xx_hw_reset(phydev); + if (res < 0) + return res; + + priv = malloc(sizeof(*priv)); + if (!priv) + return -ENOMEM; + + memset(priv, 0, sizeof(*priv)); + + /* + * This device requires indirect reads/writes to the PHY registers + * which the generic PHY code can't handle. Make a wrapper MII device + * to handle reads/writes + */ + smi_wrapper = mdio_alloc(); + if (!smi_wrapper) { + free(priv); + return -ENOMEM; + } + + /* + * Store the mdio bus in the private data, as we are going to replace + * the bus with the wrapper bus + */ + priv->mdio_bus = phydev->bus; + + /* + * Store the smi bus address in private data. This lets us use the + * phydev addr field for device address instead, as the genphy code + * expects. + */ + priv->smi_addr = phydev->addr; + + /* + * Store the phy_device in the wrapper mii device. This lets us get it + * back when genphy functions call phy_read/phy_write. + */ + smi_wrapper->priv = phydev; + strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name)); + smi_wrapper->read = mv88e61xx_phy_read_indirect; + smi_wrapper->write = mv88e61xx_phy_write_indirect; + + /* Replace the bus with the wrapper device */ + phydev->bus = smi_wrapper; + + phydev->priv = priv; + + priv->id = mv88e61xx_get_switch_id(phydev); + + return 0; +} + +static int mv88e61xx_phy_config(struct phy_device *phydev) +{ + int res; + int i; + int ret = -1; + + res = mv88e61xx_switch_init(phydev); + if (res < 0) + return res; + + for (i = 0; i < PORT_COUNT; i++) { + if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) { + phydev->addr = i; + + res = mv88e61xx_phy_enable(phydev, i); + if (res < 0) { + printf("Error enabling PHY %i\n", i); + continue; + } + res = mv88e61xx_phy_setup(phydev, i); + if (res < 0) { + printf("Error setting up PHY %i\n", i); + continue; + } + res = mv88e61xx_phy_config_port(phydev, i); + if (res < 0) { + printf("Error configuring PHY %i\n", i); + continue; + } + + res = genphy_config_aneg(phydev); + if (res < 0) { + printf("Error setting PHY %i autoneg\n", i); + continue; + } + res = phy_reset(phydev); + if (res < 0) { + printf("Error resetting PHY %i\n", i); + continue; + } + + /* Return success if any PHY succeeds */ + ret = 0; + } + } + + return ret; +} + +static int mv88e61xx_phy_is_connected(struct phy_device *phydev) +{ + int val; + + val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1); + if (val < 0) + return 0; + + /* + * After reset, the energy detect signal remains high for a few seconds + * regardless of whether a cable is connected. This function will + * return false positives during this time. + */ + return (val & PHY_REG_STATUS1_ENERGY) == 0; +} + +static int mv88e61xx_phy_startup(struct phy_device *phydev) +{ + int i; + int link = 0; + int res; + int speed = phydev->speed; + int duplex = phydev->duplex; + + for (i = 0; i < PORT_COUNT; i++) { + if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) { + phydev->addr = i; + if (!mv88e61xx_phy_is_connected(phydev)) + continue; + res = genphy_update_link(phydev); + if (res < 0) + continue; + res = mv88e61xx_parse_status(phydev); + if (res < 0) + continue; + link = (link || phydev->link); + } + } + phydev->link = link; + + /* Restore CPU interface speed and duplex after it was changed for + * other ports */ + phydev->speed = speed; + phydev->duplex = duplex; + + return 0; +} + +static struct phy_driver mv88e61xx_driver = { + .name = "Marvell MV88E61xx", + .uid = 0x01410eb1, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .probe = mv88e61xx_probe, + .config = mv88e61xx_phy_config, + .startup = mv88e61xx_phy_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_mv88e61xx_init(void) +{ + phy_register(&mv88e61xx_driver); + + return 0; +} + +/* + * Overload weak get_phy_id definition since we need non-standard functions + * to read PHY registers + */ +int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id) +{ + struct phy_device temp_phy; + struct mv88e61xx_phy_priv temp_priv; + struct mii_dev temp_mii; + int val; + + /* + * Buid temporary data structures that the chip reading code needs to + * read the ID + */ + temp_priv.mdio_bus = bus; + temp_priv.smi_addr = smi_addr; + temp_phy.priv = &temp_priv; + temp_mii.priv = &temp_phy; + + val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1); + if (val < 0) + return -EIO; + + *phy_id = val << 16; + + val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2); + if (val < 0) + return -EIO; + + *phy_id |= (val & 0xffff); + + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 23c82bb36e9..539319f02d0 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -458,6 +458,9 @@ static LIST_HEAD(phy_drivers); int phy_init(void) { +#ifdef CONFIG_MV88E61XX_SWITCH + phy_mv88e61xx_init(); +#endif #ifdef CONFIG_PHY_AQUANTIA phy_aquantia_init(); #endif diff --git a/include/phy.h b/include/phy.h index 21459a8c809..969992c747f 100644 --- a/include/phy.h +++ b/include/phy.h @@ -249,6 +249,7 @@ int gen10g_startup(struct phy_device *phydev); int gen10g_shutdown(struct phy_device *phydev); int gen10g_discover_mmds(struct phy_device *phydev); +int phy_mv88e61xx_init(void); int phy_aquantia_init(void); int phy_atheros_init(void); int phy_broadcom_init(void); -- cgit v1.3.1 From 73443b9e4c451b17d1e08164ea933ee6a849b2b3 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Thu, 28 Apr 2016 15:36:02 +0530 Subject: drivers: core: device: add support to check dt compatible for a device/machine Provide an api to check whether the given device or machine is compatible with the given compat string which helps in making decisions in drivers based on device or machine compatible. Idea taken from Linux. Signed-off-by: Mugunthan V N Reviewed-by: Joe Hershberger --- drivers/core/device.c | 14 ++++++++++++++ include/dm/device.h | 23 +++++++++++++++++++++++ 2 files changed, 37 insertions(+) (limited to 'include') diff --git a/drivers/core/device.c b/drivers/core/device.c index 5c2dc7021fb..45d5e3e12c0 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -721,3 +721,17 @@ int device_set_name(struct udevice *dev, const char *name) return 0; } + +bool of_device_is_compatible(struct udevice *dev, const char *compat) +{ + const void *fdt = gd->fdt_blob; + + return !fdt_node_check_compatible(fdt, dev->of_offset, compat); +} + +bool of_machine_is_compatible(const char *compat) +{ + const void *fdt = gd->fdt_blob; + + return !fdt_node_check_compatible(fdt, 0, compat); +} diff --git a/include/dm/device.h b/include/dm/device.h index e9a8ec72c90..f03bcd3b49e 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -547,6 +547,29 @@ int device_set_name(struct udevice *dev, const char *name); */ void device_set_name_alloced(struct udevice *dev); +/** + * of_device_is_compatible() - check if the device is compatible with the compat + * + * This allows to check whether the device is comaptible with the compat. + * + * @dev: udevice pointer for which compatible needs to be verified. + * @compat: Compatible string which needs to verified in the given + * device + * @return true if OK, false if the compatible is not found + */ +bool of_device_is_compatible(struct udevice *dev, const char *compat); + +/** + * of_machine_is_compatible() - check if the machine is compatible with + * the compat + * + * This allows to check whether the machine is comaptible with the compat. + * + * @compat: Compatible string which needs to verified + * @return true if OK, false if the compatible is not found + */ +bool of_machine_is_compatible(const char *compat); + /** * device_is_on_pci_bus - Test if a device is on a PCI bus * -- cgit v1.3.1 From 3d12e804956ca996b6621cd1e04fabd39b401882 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Thu, 28 Apr 2016 15:36:03 +0530 Subject: ti_omap5_common: eth: do not define DM_ETH for spl Since omap's spl doesn't support DM currently, do not define DM_ETH for spl build. Signed-off-by: Mugunthan V N Reviewed-by: Simon Glass Reviewed-by: Tom Rini Acked-by: Joe Hershberger --- include/configs/ti_omap5_common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index b049be49eef..2135af0db73 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -153,6 +153,7 @@ #ifdef CONFIG_SPL_BUILD #undef CONFIG_DM_MMC #undef CONFIG_TIMER +#undef CONFIG_DM_ETH #endif #endif /* __CONFIG_TI_OMAP5_COMMON_H */ -- cgit v1.3.1 From e4310566deb7533301eb0de78d3640f4f307d267 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Thu, 28 Apr 2016 15:36:07 +0530 Subject: drivers: net: cpsw: add support for reading mac address from efuse Different TI platforms has to read with different combination to get the mac address from efuse. So add support to read mac address based on machine/device compatibles. The code is taken from Linux drivers/net/ethernet/ti/cpsw-common.c done by Tony Lindgren. Signed-off-by: Mugunthan V N Reviewed-by: Tom Rini Acked-by: Joe Hershberger --- drivers/net/Makefile | 2 +- drivers/net/cpsw-common.c | 121 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/cpsw.c | 24 +++------ include/cpsw.h | 1 + 4 files changed, 131 insertions(+), 17 deletions(-) create mode 100644 drivers/net/cpsw-common.c (limited to 'include') diff --git a/drivers/net/Makefile b/drivers/net/Makefile index fbedd04f7a3..d5e4a9734b2 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -59,7 +59,7 @@ obj-$(CONFIG_SMC91111) += smc91111.o obj-$(CONFIG_SMC911X) += smc911x.o obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o -obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o +obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o obj-$(CONFIG_ULI526X) += uli526x.o diff --git a/drivers/net/cpsw-common.c b/drivers/net/cpsw-common.c new file mode 100644 index 00000000000..e828e85d8b3 --- /dev/null +++ b/drivers/net/cpsw-common.c @@ -0,0 +1,121 @@ +/* + * CPSW common - libs used across TI ethernet devices. + * + * Copyright (C) 2016, Texas Instruments, Incorporated + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define CTRL_MAC_REG(offset, id) ((offset) + 0x8 * (id)) + +static int davinci_emac_3517_get_macid(struct udevice *dev, u16 offset, + int slave, u8 *mac_addr) +{ + void *fdt = (void *)gd->fdt_blob; + int node = dev->of_offset; + u32 macid_lsb; + u32 macid_msb; + fdt32_t gmii = 0; + int syscon; + u32 addr; + + syscon = fdtdec_lookup_phandle(fdt, node, "syscon"); + if (syscon < 0) { + error("Syscon offset not found\n"); + return -ENOENT; + } + + addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii), + sizeof(u32), MAP_NOCACHE); + if (addr == FDT_ADDR_T_NONE) { + error("Not able to get syscon address to get mac efuse address\n"); + return -ENOENT; + } + + addr += CTRL_MAC_REG(offset, slave); + + /* try reading mac address from efuse */ + macid_lsb = readl(addr); + macid_msb = readl(addr + 4); + + mac_addr[0] = (macid_msb >> 16) & 0xff; + mac_addr[1] = (macid_msb >> 8) & 0xff; + mac_addr[2] = macid_msb & 0xff; + mac_addr[3] = (macid_lsb >> 16) & 0xff; + mac_addr[4] = (macid_lsb >> 8) & 0xff; + mac_addr[5] = macid_lsb & 0xff; + + return 0; +} + +static int cpsw_am33xx_cm_get_macid(struct udevice *dev, u16 offset, int slave, + u8 *mac_addr) +{ + void *fdt = (void *)gd->fdt_blob; + int node = dev->of_offset; + u32 macid_lo; + u32 macid_hi; + fdt32_t gmii = 0; + int syscon; + u32 addr; + + syscon = fdtdec_lookup_phandle(fdt, node, "syscon"); + if (syscon < 0) { + error("Syscon offset not found\n"); + return -ENOENT; + } + + addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii), + sizeof(u32), MAP_NOCACHE); + if (addr == FDT_ADDR_T_NONE) { + error("Not able to get syscon address to get mac efuse address\n"); + return -ENOENT; + } + + addr += CTRL_MAC_REG(offset, slave); + + /* try reading mac address from efuse */ + macid_lo = readl(addr); + macid_hi = readl(addr + 4); + + mac_addr[5] = (macid_lo >> 8) & 0xff; + mac_addr[4] = macid_lo & 0xff; + mac_addr[3] = (macid_hi >> 24) & 0xff; + mac_addr[2] = (macid_hi >> 16) & 0xff; + mac_addr[1] = (macid_hi >> 8) & 0xff; + mac_addr[0] = macid_hi & 0xff; + + return 0; +} + +int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr) +{ + if (of_machine_is_compatible("ti,dm8148")) + return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr); + + if (of_machine_is_compatible("ti,am33xx")) + return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr); + + if (of_device_is_compatible(dev, "ti,am3517-emac")) + return davinci_emac_3517_get_macid(dev, 0x110, slave, mac_addr); + + if (of_device_is_compatible(dev, "ti,dm816-emac")) + return cpsw_am33xx_cm_get_macid(dev, 0x30, slave, mac_addr); + + if (of_machine_is_compatible("ti,am4372")) + return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr); + + if (of_machine_is_compatible("ti,dra7")) + return davinci_emac_3517_get_macid(dev, 0x514, slave, mac_addr); + + dev_err(dev, "incompatible machine/device type for reading mac address\n"); + return -ENOENT; +} diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 9b1e37b1c1b..b8111197b3f 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -26,6 +26,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -1151,9 +1152,8 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) int node = dev->of_offset; int subnode; int slave_index = 0; - uint32_t mac_hi, mac_lo; - fdt32_t gmii = 0; int active_slave; + int ret; pdata->iobase = dev_get_addr(dev); priv->data.version = CPSW_CTRL_VERSION_2; @@ -1250,20 +1250,11 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET; } - subnode = fdtdec_lookup_phandle(fdt, node, "syscon"); - priv->data.mac_id = fdt_translate_address((void *)fdt, subnode, &gmii); - priv->data.mac_id += AM335X_GMII_SEL_OFFSET; - priv->data.mac_id += active_slave * 8; - - /* try reading mac address from efuse */ - mac_lo = readl(priv->data.mac_id); - mac_hi = readl(priv->data.mac_id + 4); - pdata->enetaddr[0] = mac_hi & 0xFF; - pdata->enetaddr[1] = (mac_hi & 0xFF00) >> 8; - pdata->enetaddr[2] = (mac_hi & 0xFF0000) >> 16; - pdata->enetaddr[3] = (mac_hi & 0xFF000000) >> 24; - pdata->enetaddr[4] = mac_lo & 0xFF; - pdata->enetaddr[5] = (mac_lo & 0xFF00) >> 8; + ret = ti_cm_get_macid(dev, active_slave, pdata->enetaddr); + if (ret < 0) { + error("cpsw read efuse mac failed\n"); + return ret; + } pdata->phy_interface = priv->data.slave_data[active_slave].phy_if; if (pdata->phy_interface == -1) { @@ -1284,6 +1275,7 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) writel(RGMII_MODE_ENABLE, priv->data.gmii_sel); break; } + return 0; } diff --git a/include/cpsw.h b/include/cpsw.h index cf1d30bfdcf..6255cd80ef2 100644 --- a/include/cpsw.h +++ b/include/cpsw.h @@ -51,5 +51,6 @@ struct cpsw_platform_data { }; int cpsw_register(struct cpsw_platform_data *data); +int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr); #endif /* _CPSW_H_ */ -- cgit v1.3.1 From cb3862277b73b57ade3774b8fa684d3d7c324ba3 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Mon, 2 May 2016 15:45:56 -0500 Subject: drivers: net: cpsw: Add reading of DT phy-handle node Add the ability to read the phy-handle node of the cpsw slave. Upon reading this handle the phy-id can be stored based on the reg node in the DT. The phy-handle also needs to be stored and passed to the phy to access any phy data that is available. Signed-off-by: Dan Murphy Tested-by: Mugunthan V N Acked-by: Joe Hershberger --- drivers/net/cpsw.c | 23 +++++++++++++++++++++-- include/cpsw.h | 1 + 2 files changed, 22 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index b8111197b3f..2ce4ec69f1d 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -966,6 +966,11 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave) phydev->supported &= supported; phydev->advertising = phydev->supported; +#ifdef CONFIG_DM_ETH + if (slave->data->phy_of_handle) + phydev->dev->of_offset = slave->data->phy_of_handle; +#endif + priv->phydev = phydev; phy_config(phydev); @@ -1226,8 +1231,22 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) if (phy_mode) priv->data.slave_data[slave_index].phy_if = phy_get_interface_by_name(phy_mode); - fdtdec_get_int_array(fdt, subnode, "phy_id", phy_id, 2); - priv->data.slave_data[slave_index].phy_addr = phy_id[1]; + + priv->data.slave_data[slave_index].phy_of_handle = + fdtdec_lookup_phandle(fdt, subnode, + "phy-handle"); + + if (priv->data.slave_data[slave_index].phy_of_handle >= 0) { + priv->data.slave_data[slave_index].phy_addr = + fdtdec_get_int(gd->fdt_blob, + priv->data.slave_data[slave_index].phy_of_handle, + "reg", -1); + } else { + fdtdec_get_int_array(fdt, subnode, "phy_id", + phy_id, 2); + priv->data.slave_data[slave_index].phy_addr = + phy_id[1]; + } slave_index++; } diff --git a/include/cpsw.h b/include/cpsw.h index 6255cd80ef2..257d12a08d7 100644 --- a/include/cpsw.h +++ b/include/cpsw.h @@ -21,6 +21,7 @@ struct cpsw_slave_data { u32 sliver_reg_ofs; int phy_addr; int phy_if; + int phy_of_handle; }; enum { -- cgit v1.3.1 From c7ba7bdc9d9940313ff5a63644ae3d74c77636cc Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Mon, 2 May 2016 15:45:58 -0500 Subject: net: phy: dp83867: Add device tree bindings and documentation Add the device tree bindings and the accompanying documentation for the TI DP83867 Giga bit ethernet phy driver. The original document was from: [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel] Signed-off-by: Dan Murphy Reviewed-by: Mugunthan V N Tested-by: Mugunthan V N Acked-by: Joe Hershberger --- doc/device-tree-bindings/net/ti,dp83867.txt | 25 +++++++++++++++++++++ include/dt-bindings/net/ti-dp83867.h | 35 +++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 doc/device-tree-bindings/net/ti,dp83867.txt create mode 100644 include/dt-bindings/net/ti-dp83867.h (limited to 'include') diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt new file mode 100644 index 00000000000..cb77fdf0825 --- /dev/null +++ b/doc/device-tree-bindings/net/ti,dp83867.txt @@ -0,0 +1,25 @@ +* Texas Instruments - dp83867 Giga bit ethernet phy + +Required properties: + - reg - The ID number for the phy, usually a small integer + - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values + - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values + - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h + for applicable values + +Default child nodes are standard Ethernet PHY device +nodes as described in doc/devicetree/bindings/net/ethernet.txt + +Example: + + ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + }; + +Datasheet can be found: +http://www.ti.com/product/DP83867IR/datasheet diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h new file mode 100644 index 00000000000..1843757a5c0 --- /dev/null +++ b/include/dt-bindings/net/ti-dp83867.h @@ -0,0 +1,35 @@ +/* + * TI DP83867 PHY drivers + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#ifndef _DT_BINDINGS_TI_DP83867_H +#define _DT_BINDINGS_TI_DP83867_H + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 +#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 +#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 +#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 + +/* RGMIIDCTL internal delay for rx and tx */ +#define DP83867_RGMIIDCTL_250_PS 0x0 +#define DP83867_RGMIIDCTL_500_PS 0x1 +#define DP83867_RGMIIDCTL_750_PS 0x2 +#define DP83867_RGMIIDCTL_1_NS 0x3 +#define DP83867_RGMIIDCTL_1_25_NS 0x4 +#define DP83867_RGMIIDCTL_1_50_NS 0x5 +#define DP83867_RGMIIDCTL_1_75_NS 0x6 +#define DP83867_RGMIIDCTL_2_00_NS 0x7 +#define DP83867_RGMIIDCTL_2_25_NS 0x8 +#define DP83867_RGMIIDCTL_2_50_NS 0x9 +#define DP83867_RGMIIDCTL_2_75_NS 0xa +#define DP83867_RGMIIDCTL_3_00_NS 0xb +#define DP83867_RGMIIDCTL_3_25_NS 0xc +#define DP83867_RGMIIDCTL_3_50_NS 0xd +#define DP83867_RGMIIDCTL_3_75_NS 0xe +#define DP83867_RGMIIDCTL_4_00_NS 0xf + +#endif -- cgit v1.3.1 From 3ab72fe8075b137c238665008c356239d1e6bc54 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Mon, 2 May 2016 15:46:00 -0500 Subject: net: phy: Move is_rgmii helper to phy.h Move the phy_interface_is_rgmii to the phy.h file for all phy's to be able to use the API. This now aligns with the Linux kernel based on commit e463d88c36d42211aa72ed76d32fb8bf37820ef1 Signed-off-by: Dan Murphy Reviewed-by: Mugunthan V N Reviewed-by: Michal Simek Tested-by: Mugunthan V N Acked-by: Joe Hershberger --- drivers/net/phy/ti.c | 11 ----------- include/phy.h | 11 +++++++++++ 2 files changed, 11 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index 4c4f0c1bf31..4c19353f662 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -156,17 +156,6 @@ void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, phy_write(phydev, addr, MII_MMD_DATA, data); } -/** - * phy_interface_is_rgmii - Convenience function for testing if a PHY interface - * is RGMII (all variants) - * @phydev: the phy_device struct - */ -static inline bool phy_interface_is_rgmii(struct phy_device *phydev) -{ - return phydev->interface >= PHY_INTERFACE_MODE_RGMII && - phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; -} - #if defined(CONFIG_DM_ETH) /** * dp83867_data_init - Convenience function for setting PHY specific data diff --git a/include/phy.h b/include/phy.h index 969992c747f..7346da7cb63 100644 --- a/include/phy.h +++ b/include/phy.h @@ -278,6 +278,17 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); */ int phy_get_interface_by_name(const char *str); +/** + * phy_interface_is_rgmii - Convenience function for testing if a PHY interface + * is RGMII (all variants) + * @phydev: the phy_device struct + */ +static inline bool phy_interface_is_rgmii(struct phy_device *phydev) +{ + return phydev->interface >= PHY_INTERFACE_MODE_RGMII && + phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; +} + /* PHY UIDs for various PHYs that are referenced in external code */ #define PHY_UID_CS4340 0x13e51002 #define PHY_UID_TN2020 0x00a19410 -- cgit v1.3.1 From 3c221af3c3bb4eadc0899f611c8b25bb95a1e09f Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Mon, 2 May 2016 15:46:01 -0500 Subject: net: phy: Add phy_interface_is_sgmii to phy.h Add a helper to phy.h to identify whether the phy is configured for SGMII all variables. Signed-off-by: Dan Murphy Reviewed-by: Mugunthan V N Reviewed-by: Michal Simek Tested-by: Mugunthan V N Acked-by: Joe Hershberger --- include/phy.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/phy.h b/include/phy.h index 7346da7cb63..268d9a1823f 100644 --- a/include/phy.h +++ b/include/phy.h @@ -289,6 +289,17 @@ static inline bool phy_interface_is_rgmii(struct phy_device *phydev) phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; } +/** + * phy_interface_is_sgmii - Convenience function for testing if a PHY interface + * is SGMII (all variants) + * @phydev: the phy_device struct + */ +static inline bool phy_interface_is_sgmii(struct phy_device *phydev) +{ + return phydev->interface >= PHY_INTERFACE_MODE_SGMII && + phydev->interface <= PHY_INTERFACE_MODE_QSGMII; +} + /* PHY UIDs for various PHYs that are referenced in external code */ #define PHY_UID_CS4340 0x13e51002 #define PHY_UID_TN2020 0x00a19410 -- cgit v1.3.1 From 166097e8775343898cab84f1f23b4aacb35783db Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sat, 23 Apr 2016 22:18:09 +0530 Subject: clk: exynos: add clock driver for Exynos7420 Soc Add a clock driver for Exynos7420 SoC. There are about 25 clock controller blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks are added in this initial version of the driver. Cc: Minkyu Kang Cc: Simon Glass Signed-off-by: Thomas Abraham Reviewed-by: Simon Glass Signed-off-by: Minkyu Kang --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/exynos/Kconfig | 18 +++ drivers/clk/exynos/Makefile | 9 ++ drivers/clk/exynos/clk-exynos7420.c | 236 +++++++++++++++++++++++++++++ drivers/clk/exynos/clk-pll.c | 33 ++++ drivers/clk/exynos/clk-pll.h | 9 ++ include/dt-bindings/clock/exynos7420-clk.h | 207 +++++++++++++++++++++++++ 8 files changed, 514 insertions(+) create mode 100644 drivers/clk/exynos/Kconfig create mode 100644 drivers/clk/exynos/Makefile create mode 100644 drivers/clk/exynos/clk-exynos7420.c create mode 100644 drivers/clk/exynos/clk-pll.c create mode 100644 drivers/clk/exynos/clk-pll.h create mode 100644 include/dt-bindings/clock/exynos7420-clk.h (limited to 'include') diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index a98b74bbc0c..6eee8eb369b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -21,5 +21,6 @@ config SPL_CLK used as U-Boot proper. source "drivers/clk/uniphier/Kconfig" +source "drivers/clk/exynos/Kconfig" endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index c51db1562b6..81fe600188c 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o obj-$(CONFIG_MACH_PIC32) += clk_pic32.o obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ +obj-$(CONFIG_CLK_EXYNOS) += exynos/ diff --git a/drivers/clk/exynos/Kconfig b/drivers/clk/exynos/Kconfig new file mode 100644 index 00000000000..eb0efa97d15 --- /dev/null +++ b/drivers/clk/exynos/Kconfig @@ -0,0 +1,18 @@ +config CLK_EXYNOS + bool + select CLK + help + This enables support for common clock driver API on Samsung + Exynos SoCs. + +menu "Clock drivers for Exynos SoCs" + depends on CLK_EXYNOS + +config CLK_EXYNOS7420 + bool "Clock driver for Samsung's Exynos7420 SoC" + default y + help + This enables common clock driver support for platforms based + on Samsung Exynos7420 SoC. + +endmenu diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile new file mode 100644 index 00000000000..1df10fe84a1 --- /dev/null +++ b/drivers/clk/exynos/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2016 Samsung Electronics +# Thomas Abraham +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += clk-pll.o +obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c new file mode 100644 index 00000000000..bf5d0e6e603 --- /dev/null +++ b/drivers/clk/exynos/clk-exynos7420.c @@ -0,0 +1,236 @@ +/* + * Samsung Exynos7420 clock driver. + * Copyright (C) 2016 Samsung Electronics + * Thomas Abraham + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "clk-pll.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define DIVIDER(reg, shift, mask) \ + (((readl(reg) >> shift) & mask) + 1) + +/* CMU TOPC block device structure */ +struct exynos7420_clk_cmu_topc { + unsigned int rsvd1[68]; + unsigned int bus0_pll_con[2]; + unsigned int rsvd2[2]; + unsigned int bus1_pll_con[2]; + unsigned int rsvd3[54]; + unsigned int mux_sel[6]; + unsigned int rsvd4[250]; + unsigned int div[4]; +}; + +/* CMU TOP0 block device structure */ +struct exynos7420_clk_cmu_top0 { + unsigned int rsvd0[128]; + unsigned int mux_sel[7]; + unsigned int rsvd1[261]; + unsigned int div_peric[5]; +}; + +/** + * struct exynos7420_clk_topc_priv - private data for CMU topc clock driver. + * + * @topc: base address of the memory mapped CMU TOPC controller. + * @fin_freq: frequency of the Oscillator clock. + * @sclk_bus0_pll_a: frequency of sclk_bus0_pll_a clock. + * @sclk_bus1_pll_a: frequency of sclk_bus1_pll_a clock. + */ +struct exynos7420_clk_topc_priv { + struct exynos7420_clk_cmu_topc *topc; + unsigned long fin_freq; + unsigned long sclk_bus0_pll_a; + unsigned long sclk_bus1_pll_a; +}; + +/** + * struct exynos7420_clk_top0_priv - private data for CMU top0 clock driver. + * + * @top0: base address of the memory mapped CMU TOP0 controller. + * @mout_top0_bus0_pll_half: frequency of mout_top0_bus0_pll_half clock + * @sclk_uart2: frequency of sclk_uart2 clock. + */ +struct exynos7420_clk_top0_priv { + struct exynos7420_clk_cmu_top0 *top0; + unsigned long mout_top0_bus0_pll_half; + unsigned long sclk_uart2; +}; + +static ulong exynos7420_topc_get_periph_rate(struct udevice *dev, int periph) +{ + struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev); + + switch (periph) { + case DOUT_SCLK_BUS0_PLL: + case SCLK_BUS0_PLL_A: + case SCLK_BUS0_PLL_B: + return priv->sclk_bus0_pll_a; + case DOUT_SCLK_BUS1_PLL: + case SCLK_BUS1_PLL_A: + case SCLK_BUS1_PLL_B: + return priv->sclk_bus1_pll_a; + default: + return 0; + } +} + +static struct clk_ops exynos7420_clk_topc_ops = { + .get_periph_rate = exynos7420_topc_get_periph_rate, +}; + +static int exynos7420_clk_topc_probe(struct udevice *dev) +{ + struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev); + struct exynos7420_clk_cmu_topc *topc; + struct udevice *clk_dev; + unsigned long rate; + fdt_addr_t base; + int ret; + + base = dev_get_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + topc = (struct exynos7420_clk_cmu_topc *)base; + priv->topc = topc; + + ret = clk_get_by_index(dev, 0, &clk_dev); + if (ret >= 0) + priv->fin_freq = clk_get_rate(clk_dev); + + rate = pll145x_get_rate(&topc->bus0_pll_con[0], priv->fin_freq); + if (readl(&topc->mux_sel[1]) & (1 << 16)) + rate >>= 1; + rate /= DIVIDER(&topc->div[3], 0, 0xf); + priv->sclk_bus0_pll_a = rate; + + rate = pll145x_get_rate(&topc->bus1_pll_con[0], priv->fin_freq) / + DIVIDER(&topc->div[3], 8, 0xf); + priv->sclk_bus1_pll_a = rate; + + return 0; +} + +static ulong exynos7420_top0_get_periph_rate(struct udevice *dev, int periph) +{ + struct exynos7420_clk_top0_priv *priv = dev_get_priv(dev); + struct exynos7420_clk_cmu_top0 *top0 = priv->top0; + + switch (periph) { + case CLK_SCLK_UART2: + return priv->mout_top0_bus0_pll_half / + DIVIDER(&top0->div_peric[3], 8, 0xf); + default: + return 0; + } +} + +static struct clk_ops exynos7420_clk_top0_ops = { + .get_periph_rate = exynos7420_top0_get_periph_rate, +}; + +static int exynos7420_clk_top0_probe(struct udevice *dev) +{ + struct exynos7420_clk_top0_priv *priv; + struct exynos7420_clk_cmu_top0 *top0; + struct udevice *clk_dev; + fdt_addr_t base; + int ret; + + priv = dev_get_priv(dev); + if (!priv) + return -EINVAL; + + base = dev_get_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + top0 = (struct exynos7420_clk_cmu_top0 *)base; + priv->top0 = top0; + + ret = clk_get_by_index(dev, 1, &clk_dev); + if (ret >= 0) { + priv->mout_top0_bus0_pll_half = + clk_get_periph_rate(clk_dev, ret); + if (readl(&top0->mux_sel[1]) & (1 << 16)) + priv->mout_top0_bus0_pll_half >>= 1; + } + + return 0; +} + +static ulong exynos7420_peric1_get_periph_rate(struct udevice *dev, int periph) +{ + struct udevice *clk_dev; + unsigned int ret; + unsigned long freq = 0; + + switch (periph) { + case SCLK_UART2: + ret = clk_get_by_index(dev, 3, &clk_dev); + if (ret < 0) + return ret; + freq = clk_get_periph_rate(clk_dev, ret); + break; + } + + return freq; +} + +static struct clk_ops exynos7420_clk_peric1_ops = { + .get_periph_rate = exynos7420_peric1_get_periph_rate, +}; + +static const struct udevice_id exynos7420_clk_topc_compat[] = { + { .compatible = "samsung,exynos7-clock-topc" }, + { } +}; + +U_BOOT_DRIVER(exynos7420_clk_topc) = { + .name = "exynos7420-clock-topc", + .id = UCLASS_CLK, + .of_match = exynos7420_clk_topc_compat, + .probe = exynos7420_clk_topc_probe, + .priv_auto_alloc_size = sizeof(struct exynos7420_clk_topc_priv), + .ops = &exynos7420_clk_topc_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +static const struct udevice_id exynos7420_clk_top0_compat[] = { + { .compatible = "samsung,exynos7-clock-top0" }, + { } +}; + +U_BOOT_DRIVER(exynos7420_clk_top0) = { + .name = "exynos7420-clock-top0", + .id = UCLASS_CLK, + .of_match = exynos7420_clk_top0_compat, + .probe = exynos7420_clk_top0_probe, + .priv_auto_alloc_size = sizeof(struct exynos7420_clk_top0_priv), + .ops = &exynos7420_clk_top0_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +static const struct udevice_id exynos7420_clk_peric1_compat[] = { + { .compatible = "samsung,exynos7-clock-peric1" }, + { } +}; + +U_BOOT_DRIVER(exynos7420_clk_peric1) = { + .name = "exynos7420-clock-peric1", + .id = UCLASS_CLK, + .of_match = exynos7420_clk_peric1_compat, + .ops = &exynos7420_clk_peric1_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c new file mode 100644 index 00000000000..27220c5911a --- /dev/null +++ b/drivers/clk/exynos/clk-pll.c @@ -0,0 +1,33 @@ +/* + * Exynos PLL helper functions for clock drivers. + * Copyright (C) 2016 Samsung Electronics + * Thomas Abraham + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define PLL145X_MDIV_SHIFT 16 +#define PLL145X_MDIV_MASK 0x3ff +#define PLL145X_PDIV_SHIFT 8 +#define PLL145X_PDIV_MASK 0x3f +#define PLL145X_SDIV_SHIFT 0 +#define PLL145X_SDIV_MASK 0x7 + +unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq) +{ + unsigned long pll_con1 = readl(con1); + unsigned long mdiv, sdiv, pdiv; + uint64_t fvco = fin_freq; + + mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK; + pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK; + sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + return (unsigned long)fvco; +} diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h new file mode 100644 index 00000000000..631d035f833 --- /dev/null +++ b/drivers/clk/exynos/clk-pll.h @@ -0,0 +1,9 @@ +/* + * Exynos PLL helper functions for clock drivers. + * Copyright (C) 2016 Samsung Electronics + * Thomas Abraham + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq); diff --git a/include/dt-bindings/clock/exynos7420-clk.h b/include/dt-bindings/clock/exynos7420-clk.h new file mode 100644 index 00000000000..10c55861108 --- /dev/null +++ b/include/dt-bindings/clock/exynos7420-clk.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Author: Naveen Krishna Ch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H +#define _DT_BINDINGS_CLOCK_EXYNOS7_H + +/* TOPC */ +#define DOUT_ACLK_PERIS 1 +#define DOUT_SCLK_BUS0_PLL 2 +#define DOUT_SCLK_BUS1_PLL 3 +#define DOUT_SCLK_CC_PLL 4 +#define DOUT_SCLK_MFC_PLL 5 +#define DOUT_ACLK_CCORE_133 6 +#define DOUT_ACLK_MSCL_532 7 +#define ACLK_MSCL_532 8 +#define DOUT_SCLK_AUD_PLL 9 +#define FOUT_AUD_PLL 10 +#define SCLK_AUD_PLL 11 +#define SCLK_MFC_PLL_B 12 +#define SCLK_MFC_PLL_A 13 +#define SCLK_BUS1_PLL_B 14 +#define SCLK_BUS1_PLL_A 15 +#define SCLK_BUS0_PLL_B 16 +#define SCLK_BUS0_PLL_A 17 +#define SCLK_CC_PLL_B 18 +#define SCLK_CC_PLL_A 19 +#define ACLK_CCORE_133 20 +#define ACLK_PERIS_66 21 +#define TOPC_NR_CLK 22 + +/* TOP0 */ +#define DOUT_ACLK_PERIC1 1 +#define DOUT_ACLK_PERIC0 2 +#define CLK_SCLK_UART0 3 +#define CLK_SCLK_UART1 4 +#define CLK_SCLK_UART2 5 +#define CLK_SCLK_UART3 6 +#define CLK_SCLK_SPI0 7 +#define CLK_SCLK_SPI1 8 +#define CLK_SCLK_SPI2 9 +#define CLK_SCLK_SPI3 10 +#define CLK_SCLK_SPI4 11 +#define CLK_SCLK_SPDIF 12 +#define CLK_SCLK_PCM1 13 +#define CLK_SCLK_I2S1 14 +#define CLK_ACLK_PERIC0_66 15 +#define CLK_ACLK_PERIC1_66 16 +#define TOP0_NR_CLK 17 + +/* TOP1 */ +#define DOUT_ACLK_FSYS1_200 1 +#define DOUT_ACLK_FSYS0_200 2 +#define DOUT_SCLK_MMC2 3 +#define DOUT_SCLK_MMC1 4 +#define DOUT_SCLK_MMC0 5 +#define CLK_SCLK_MMC2 6 +#define CLK_SCLK_MMC1 7 +#define CLK_SCLK_MMC0 8 +#define CLK_ACLK_FSYS0_200 9 +#define CLK_ACLK_FSYS1_200 10 +#define CLK_SCLK_PHY_FSYS1 11 +#define CLK_SCLK_PHY_FSYS1_26M 12 +#define MOUT_SCLK_UFSUNIPRO20 13 +#define DOUT_SCLK_UFSUNIPRO20 14 +#define CLK_SCLK_UFSUNIPRO20 15 +#define DOUT_SCLK_PHY_FSYS1 16 +#define DOUT_SCLK_PHY_FSYS1_26M 17 +#define TOP1_NR_CLK 18 + +/* CCORE */ +#define PCLK_RTC 1 +#define CCORE_NR_CLK 2 + +/* PERIC0 */ +#define PCLK_UART0 1 +#define SCLK_UART0 2 +#define PCLK_HSI2C0 3 +#define PCLK_HSI2C1 4 +#define PCLK_HSI2C4 5 +#define PCLK_HSI2C5 6 +#define PCLK_HSI2C9 7 +#define PCLK_HSI2C10 8 +#define PCLK_HSI2C11 9 +#define PCLK_PWM 10 +#define SCLK_PWM 11 +#define PCLK_ADCIF 12 +#define PERIC0_NR_CLK 13 + +/* PERIC1 */ +#define PCLK_UART1 1 +#define PCLK_UART2 2 +#define PCLK_UART3 3 +#define SCLK_UART1 4 +#define SCLK_UART2 5 +#define SCLK_UART3 6 +#define PCLK_HSI2C2 7 +#define PCLK_HSI2C3 8 +#define PCLK_HSI2C6 9 +#define PCLK_HSI2C7 10 +#define PCLK_HSI2C8 11 +#define PCLK_SPI0 12 +#define PCLK_SPI1 13 +#define PCLK_SPI2 14 +#define PCLK_SPI3 15 +#define PCLK_SPI4 16 +#define SCLK_SPI0 17 +#define SCLK_SPI1 18 +#define SCLK_SPI2 19 +#define SCLK_SPI3 20 +#define SCLK_SPI4 21 +#define PCLK_I2S1 22 +#define PCLK_PCM1 23 +#define PCLK_SPDIF 24 +#define SCLK_I2S1 25 +#define SCLK_PCM1 26 +#define SCLK_SPDIF 27 +#define PERIC1_NR_CLK 28 + +/* PERIS */ +#define PCLK_CHIPID 1 +#define SCLK_CHIPID 2 +#define PCLK_WDT 3 +#define PCLK_TMU 4 +#define SCLK_TMU 5 +#define PERIS_NR_CLK 6 + +/* FSYS0 */ +#define ACLK_MMC2 1 +#define ACLK_AXIUS_USBDRD30X_FSYS0X 2 +#define ACLK_USBDRD300 3 +#define SCLK_USBDRD300_SUSPENDCLK 4 +#define SCLK_USBDRD300_REFCLK 5 +#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 +#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 +#define OSCCLK_PHY_CLKOUT_USB30_PHY 8 +#define ACLK_PDMA0 9 +#define ACLK_PDMA1 10 +#define FSYS0_NR_CLK 11 + +/* FSYS1 */ +#define ACLK_MMC1 1 +#define ACLK_MMC0 2 +#define PHYCLK_UFS20_TX0_SYMBOL 3 +#define PHYCLK_UFS20_RX0_SYMBOL 4 +#define PHYCLK_UFS20_RX1_SYMBOL 5 +#define ACLK_UFS20_LINK 6 +#define SCLK_UFSUNIPRO20_USER 7 +#define PHYCLK_UFS20_RX1_SYMBOL_USER 8 +#define PHYCLK_UFS20_RX0_SYMBOL_USER 9 +#define PHYCLK_UFS20_TX0_SYMBOL_USER 10 +#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11 +#define SCLK_COMBO_PHY_EMBEDDED_26M 12 +#define DOUT_PCLK_FSYS1 13 +#define PCLK_GPIO_FSYS1 14 +#define MOUT_FSYS1_PHYCLK_SEL1 15 +#define FSYS1_NR_CLK 16 + +/* MSCL */ +#define USERMUX_ACLK_MSCL_532 1 +#define DOUT_PCLK_MSCL 2 +#define ACLK_MSCL_0 3 +#define ACLK_MSCL_1 4 +#define ACLK_JPEG 5 +#define ACLK_G2D 6 +#define ACLK_LH_ASYNC_SI_MSCL_0 7 +#define ACLK_LH_ASYNC_SI_MSCL_1 8 +#define ACLK_AXI2ACEL_BRIDGE 9 +#define ACLK_XIU_MSCLX_0 10 +#define ACLK_XIU_MSCLX_1 11 +#define ACLK_QE_MSCL_0 12 +#define ACLK_QE_MSCL_1 13 +#define ACLK_QE_JPEG 14 +#define ACLK_QE_G2D 15 +#define ACLK_PPMU_MSCL_0 16 +#define ACLK_PPMU_MSCL_1 17 +#define ACLK_MSCLNP_133 18 +#define ACLK_AHB2APB_MSCL0P 19 +#define ACLK_AHB2APB_MSCL1P 20 + +#define PCLK_MSCL_0 21 +#define PCLK_MSCL_1 22 +#define PCLK_JPEG 23 +#define PCLK_G2D 24 +#define PCLK_QE_MSCL_0 25 +#define PCLK_QE_MSCL_1 26 +#define PCLK_QE_JPEG 27 +#define PCLK_QE_G2D 28 +#define PCLK_PPMU_MSCL_0 29 +#define PCLK_PPMU_MSCL_1 30 +#define PCLK_AXI2ACEL_BRIDGE 31 +#define PCLK_PMU_MSCL 32 +#define MSCL_NR_CLK 33 + +/* AUD */ +#define SCLK_I2S 1 +#define SCLK_PCM 2 +#define PCLK_I2S 3 +#define PCLK_PCM 4 +#define ACLK_ADMA 5 +#define AUD_NR_CLK 6 +#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ -- cgit v1.3.1 From e39448e8be8389f5ddeabae0ec9c6a3b7b8a2ca6 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sat, 23 Apr 2016 22:18:13 +0530 Subject: arm: exynos: add support for Exynos7420 SoC Add support for Exynos7420 SoC. The Exynos7420 SoC has four Cortex-A57 and four Cortex-A53 CPUs and includes various peripheral controllers. Signed-off-by: Thomas Abraham Reviewed-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos7420.dtsi | 83 ++++++++++++++++++++++++++ arch/arm/mach-exynos/Kconfig | 8 +++ arch/arm/mach-exynos/Makefile | 1 + arch/arm/mach-exynos/mmu-arm64.c | 35 +++++++++++ arch/arm/mach-exynos/soc.c | 8 +++ include/configs/espresso7420.h | 34 +++++++++++ include/configs/exynos7420-common.h | 113 ++++++++++++++++++++++++++++++++++++ 7 files changed, 282 insertions(+) create mode 100644 arch/arm/dts/exynos7420.dtsi create mode 100644 arch/arm/mach-exynos/mmu-arm64.c create mode 100644 include/configs/espresso7420.h create mode 100644 include/configs/exynos7420-common.h (limited to 'include') diff --git a/arch/arm/dts/exynos7420.dtsi b/arch/arm/dts/exynos7420.dtsi new file mode 100644 index 00000000000..b398021e308 --- /dev/null +++ b/arch/arm/dts/exynos7420.dtsi @@ -0,0 +1,83 @@ +/* + * Samsung Exynos7420 SoC device tree source + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "skeleton.dtsi" +#include +/ { + compatible = "samsung,exynos7420"; + + fin_pll: xxti { + compatible = "fixed-clock"; + clock-output-names = "fin_pll"; + u-boot,dm-pre-reloc; + #clock-cells = <0>; + }; + + clock_topc: clock-controller@10570000 { + compatible = "samsung,exynos7-clock-topc"; + reg = <0x10570000 0x10000>; + u-boot,dm-pre-reloc; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + clock_top0: clock-controller@105d0000 { + compatible = "samsung,exynos7-clock-top0"; + reg = <0x105d0000 0xb000>; + u-boot,dm-pre-reloc; + #clock-cells = <1>; + clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, + <&clock_topc DOUT_SCLK_BUS1_PLL>, + <&clock_topc DOUT_SCLK_CC_PLL>, + <&clock_topc DOUT_SCLK_MFC_PLL>; + clock-names = "fin_pll", "dout_sclk_bus0_pll", + "dout_sclk_bus1_pll", "dout_sclk_cc_pll", + "dout_sclk_mfc_pll"; + }; + + clock_peric1: clock-controller@14c80000 { + compatible = "samsung,exynos7-clock-peric1"; + reg = <0x14c80000 0xd00>; + u-boot,dm-pre-reloc; + #clock-cells = <1>; + clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, + <&clock_top0 CLK_SCLK_UART1>, + <&clock_top0 CLK_SCLK_UART2>, + <&clock_top0 CLK_SCLK_UART3>; + clock-names = "fin_pll", "dout_aclk_peric1_66", + "sclk_uart1", "sclk_uart2", "sclk_uart3"; + }; + + pinctrl@13470000 { + compatible = "samsung,exynos7420-pinctrl"; + reg = <0x13470000 0x1000>; + u-boot,dm-pre-reloc; + + serial2_bus: serial2-bus { + samsung,pins = "gpd1-4", "gpd1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + u-boot,dm-pre-reloc; + }; + }; + + serial@14C30000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x14C30000 0x100>; + u-boot,dm-pre-reloc; + clocks = <&clock_peric1 PCLK_UART2>, + <&clock_peric1 SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&serial2_bus>; + }; +}; diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 28a6a60f7c7..0a6cb33bab3 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -20,6 +20,14 @@ config ARCH_EXYNOS5 Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs in this family including Exynos5250, Exynos5420 and Exynos5800. +config ARCH_EXYNOS7 + bool "Exynos7 SoC family" + select ARM64 + help + Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or + Cortex-A53 CPU (and some in a big.LITTLE configuration). There are + multiple SoCs in this family including Exynos7420. + endchoice if ARCH_EXYNOS4 diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index f3c07b76cec..0cc6c3253ac 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -7,6 +7,7 @@ obj-y += soc.o obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o system.o +obj-$(CONFIG_ARM64) += mmu-arm64.o obj-$(CONFIG_EXYNOS5420) += sec_boot.o diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c new file mode 100644 index 00000000000..ba6d99d329d --- /dev/null +++ b/arch/arm/mach-exynos/mmu-arm64.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2016 Samsung Electronics + * Thomas Abraham + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_EXYNOS7420 +static struct mm_region exynos7420_mem_map[] = { + { + .base = 0x10000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + .base = 0x40000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* List terminator */ + .base = 0, + .size = 0, + .attrs = 0, + }, +}; + +struct mm_region *mem_map = exynos7420_mem_map; +#endif diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c index 737a8ddbcf3..f9c74686119 100644 --- a/arch/arm/mach-exynos/soc.c +++ b/arch/arm/mach-exynos/soc.c @@ -23,3 +23,11 @@ void enable_caches(void) dcache_enable(); } #endif + +#ifdef CONFIG_ARM64 +void lowlevel_init(void) +{ + armv8_switch_to_el2(); + armv8_switch_to_el1(); +} +#endif diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h new file mode 100644 index 00000000000..c6a756d2b9e --- /dev/null +++ b/include/configs/espresso7420.h @@ -0,0 +1,34 @@ +/* + * Configuration settings for the SAMSUNG ESPRESSO7420 board. + * Copyright (C) 2016 Samsung Electronics + * Thomas Abraham + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ESPRESSO7420_H +#define __CONFIG_ESPRESSO7420_H + +#include + +#define CONFIG_BOARD_COMMON + +#define CONFIG_ESPRESSO7420 +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 +#define CONFIG_SPL_STACK CONFIG_IRAM_END +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_END + +/* select serial console configuration */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + +#define CONFIG_IDENT_STRING " for ESPRESSO7420" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 8 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + +#endif /* __CONFIG_ESPRESSO7420_H */ diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h new file mode 100644 index 00000000000..9e0396208ab --- /dev/null +++ b/include/configs/exynos7420-common.h @@ -0,0 +1,113 @@ +/* + * Configuration settings for the Espresso7420 board. + * Copyright (C) 2016 Samsung Electronics + * Thomas Abraham + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS7420_COMMON_H +#define __CONFIG_EXYNOS7420_COMMON_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_EXYNOS7420 /* Exynos7 Family */ +#define CONFIG_S5P + +#include /* get chip and board defs */ +#include + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F + +/* Size of malloc() pool before and after relocation */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* select serial console configuration */ +#define CONFIG_BAUDRATE 115200 + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +/* Timer input clock frequency */ +#define COUNTER_FREQUENCY 24000000 + +/* Device Tree */ +#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420" + +/* IRAM Layout */ +#define CONFIG_IRAM_BASE 0x02100000 +#define CONFIG_IRAM_SIZE 0x58000 +#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE) + +/* Number of CPUs available */ +#define CONFIG_CORE_COUNT 0x8 + +/* select serial console configuration */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SILENT_CONSOLE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_CONSOLE_MUX + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE + +/* Configuration of ENV Blocks */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + +#ifndef MEM_LAYOUT_ENV_SETTINGS +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x42000000\0" \ + "fdt_addr_r=0x43000000\0" \ + "ramdisk_addr_r=0x43300000\0" \ + "scriptaddr=0x50000000\0" \ + "pxefile_addr_r=0x51000000\0" +#endif + +#ifndef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" +#endif + +#ifndef EXYNOS_FDTFILE_SETTING +#define EXYNOS_FDTFILE_SETTING +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS \ + EXYNOS_FDTFILE_SETTING \ + MEM_LAYOUT_ENV_SETTINGS + +#endif /* __CONFIG_EXYNOS7420_COMMON_H */ -- cgit v1.3.1 From b6feb2675b75c687b9ddb9e5a493cfe4035e387d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 21 Feb 2016 21:08:39 -0700 Subject: exynos: video: Drop dead code We always use device tree with video, so can drop these #ifdefs. Some of the hardware addresses are not needed either. Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin Acked-by: Anatolij Gustschin Signed-off-by: Minkyu Kang --- arch/arm/mach-exynos/include/mach/cpu.h | 2 -- drivers/video/exynos/exynos_dp_lowlevel.c | 4 ---- drivers/video/exynos/exynos_fb.c | 11 ----------- drivers/video/exynos/exynos_fimd.c | 7 ------- drivers/video/exynos/exynos_mipi_dsi.c | 4 ---- include/exynos_lcd.h | 2 -- 6 files changed, 30 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h index f12e3d610b3..1f722df9dd9 100644 --- a/arch/arm/mach-exynos/include/mach/cpu.h +++ b/arch/arm/mach-exynos/include/mach/cpu.h @@ -288,9 +288,7 @@ static inline unsigned long __attribute__((no_instrument_function)) \ SAMSUNG_BASE(adc, ADC_BASE) SAMSUNG_BASE(clock, CLOCK_BASE) SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE) -SAMSUNG_BASE(dp, DP_BASE) SAMSUNG_BASE(sysreg, SYSREG_BASE) -SAMSUNG_BASE(fimd, FIMD_BASE) SAMSUNG_BASE(i2c, I2C_BASE) SAMSUNG_BASE(i2s, I2S_BASE) SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE) diff --git a/drivers/video/exynos/exynos_dp_lowlevel.c b/drivers/video/exynos/exynos_dp_lowlevel.c index acb5bc8eb7b..e417cf86c6a 100644 --- a/drivers/video/exynos/exynos_dp_lowlevel.c +++ b/drivers/video/exynos/exynos_dp_lowlevel.c @@ -22,7 +22,6 @@ struct exynos_dp *dp_regs; void exynos_dp_set_base_addr(void) { -#if CONFIG_IS_ENABLED(OF_CONTROL) unsigned int node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_SAMSUNG_EXYNOS5_DP); if (node <= 0) @@ -32,9 +31,6 @@ void exynos_dp_set_base_addr(void) node, "reg"); if (dp_regs == NULL) debug("Can't get the DP base address\n"); -#else - dp_regs = (struct exynos_dp *)samsung_get_base_dp(); -#endif } static void exynos_dp_enable_video_input(unsigned int enable) diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c index 69edc3a3a4a..39e3adeceaa 100644 --- a/drivers/video/exynos/exynos_fb.c +++ b/drivers/video/exynos/exynos_fb.c @@ -28,7 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; static unsigned int panel_width, panel_height; -#if CONFIG_IS_ENABLED(OF_CONTROL) vidinfo_t panel_info = { /* * Insert a value here so that we don't end up in the BSS @@ -36,7 +35,6 @@ vidinfo_t panel_info = { */ .vl_col = -1, }; -#endif ushort *configuration_get_cmap(void) { @@ -126,7 +124,6 @@ static void lcd_panel_on(vidinfo_t *vid) exynos_backlight_on(1); -#if CONFIG_IS_ENABLED(OF_CONTROL) node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD); if (node <= 0) { @@ -141,7 +138,6 @@ static void lcd_panel_on(vidinfo_t *vid) &bl_en_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); -#endif exynos_cfg_ldo(); exynos_enable_ldo(1); @@ -150,7 +146,6 @@ static void lcd_panel_on(vidinfo_t *vid) exynos_mipi_dsi_init(); } -#if CONFIG_IS_ENABLED(OF_CONTROL) int exynos_lcd_early_init(const void *blob) { unsigned int node; @@ -288,22 +283,16 @@ int exynos_lcd_early_init(const void *blob) return 0; } -#endif void lcd_ctrl_init(void *lcdbase) { set_system_display_ctrl(); set_lcd_clk(); -#if CONFIG_IS_ENABLED(OF_CONTROL) #ifdef CONFIG_EXYNOS_MIPI_DSIM exynos_init_dsim_platform_data(&panel_info); #endif exynos_lcd_misc_init(&panel_info); -#else - /* initialize parameters which is specific to panel. */ - init_panel_info(&panel_info); -#endif panel_width = panel_info.vl_width; panel_height = panel_info.vl_height; diff --git a/drivers/video/exynos/exynos_fimd.c b/drivers/video/exynos/exynos_fimd.c index ac001a801e0..019d88f990a 100644 --- a/drivers/video/exynos/exynos_fimd.c +++ b/drivers/video/exynos/exynos_fimd.c @@ -251,7 +251,6 @@ void exynos_fimd_window_off(unsigned int win_id) writel(cfg, &fimd_ctrl->winshmap); } -#if CONFIG_IS_ENABLED(OF_CONTROL) /* * The reset value for FIMD SYSMMU register MMU_CTRL is 3 * on Exynos5420 and newer versions. @@ -289,13 +288,11 @@ void exynos_fimd_disable_sysmmu(void) writel(0x0, sysmmufimd); } } -#endif void exynos_fimd_lcd_init(vidinfo_t *vid) { unsigned int cfg = 0, rgb_mode; unsigned int offset; -#if CONFIG_IS_ENABLED(OF_CONTROL) unsigned int node; node = fdtdec_next_compatible(gd->fdt_blob, @@ -311,10 +308,6 @@ void exynos_fimd_lcd_init(vidinfo_t *vid) if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu")) exynos_fimd_disable_sysmmu(); -#else - fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd(); -#endif - offset = exynos_fimd_get_base_offset(); /* store panel info to global variable */ diff --git a/drivers/video/exynos/exynos_mipi_dsi.c b/drivers/video/exynos/exynos_mipi_dsi.c index b597accf3d8..5001e163d99 100644 --- a/drivers/video/exynos/exynos_mipi_dsi.c +++ b/drivers/video/exynos/exynos_mipi_dsi.c @@ -28,11 +28,9 @@ DECLARE_GLOBAL_DATA_PTR; static struct exynos_platform_mipi_dsim *dsim_pd; -#if CONFIG_IS_ENABLED(OF_CONTROL) static struct mipi_dsim_config dsim_config_dt; static struct exynos_platform_mipi_dsim dsim_platform_data_dt; static struct mipi_dsim_lcd_device mipi_lcd_device_dt; -#endif struct mipi_dsim_ddi { int bus_id; @@ -249,7 +247,6 @@ void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd) dsim_pd = pd; } -#if CONFIG_IS_ENABLED(OF_CONTROL) int exynos_dsim_config_parse_dt(const void *blob) { int node; @@ -334,4 +331,3 @@ void exynos_init_dsim_platform_data(vidinfo_t *vid) dsim_pd = &dsim_platform_data_dt; } -#endif diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h index 3969a6a0666..e1769f09d1b 100644 --- a/include/exynos_lcd.h +++ b/include/exynos_lcd.h @@ -77,6 +77,4 @@ typedef struct vidinfo { unsigned int dual_lcd_enabled; } vidinfo_t; -void init_panel_info(vidinfo_t *vid); - #endif -- cgit v1.3.1 From 162fa53c8d3c2f832d791d0bb7a72fec1562fba4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 21 Feb 2016 21:08:42 -0700 Subject: exynos: video: Drop static variables in exynos_fimd.c Drop these and use parameters instead. Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin Signed-off-by: Minkyu Kang --- drivers/video/exynos/exynos_fb.h | 2 +- drivers/video/exynos/exynos_fimd.c | 51 ++++++++++++++++++++++---------------- include/exynos_lcd.h | 1 + 3 files changed, 31 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/drivers/video/exynos/exynos_fb.h b/drivers/video/exynos/exynos_fb.h index 833be6a62f0..f59cce0acdb 100644 --- a/drivers/video/exynos/exynos_fb.h +++ b/drivers/video/exynos/exynos_fb.h @@ -36,6 +36,6 @@ enum exynos_cpu_auto_cmd_rate { void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size, unsigned long palette_size); void exynos_fimd_lcd_init(struct vidinfo *vid, ulong lcd_base_address); -unsigned long exynos_fimd_calc_fbsize(void); +unsigned long exynos_fimd_calc_fbsize(struct vidinfo *pvid); #endif diff --git a/drivers/video/exynos/exynos_fimd.c b/drivers/video/exynos/exynos_fimd.c index a1de9ac38cd..039d4c5433d 100644 --- a/drivers/video/exynos/exynos_fimd.c +++ b/drivers/video/exynos/exynos_fimd.c @@ -21,11 +21,9 @@ DECLARE_GLOBAL_DATA_PTR; -static struct vidinfo *pvid; -static struct exynos_fb *fimd_ctrl; - -static void exynos_fimd_set_dualrgb(unsigned int enabled) +static void exynos_fimd_set_dualrgb(struct vidinfo *pvid, unsigned int enabled) { + struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; unsigned int cfg = 0; if (enabled) { @@ -43,6 +41,7 @@ static void exynos_fimd_set_dualrgb(unsigned int enabled) static void exynos_fimd_set_dp_clkcon(struct vidinfo *pvid, unsigned int enabled) { + struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; unsigned int cfg = 0; if (enabled) @@ -53,6 +52,7 @@ static void exynos_fimd_set_dp_clkcon(struct vidinfo *pvid, static void exynos_fimd_set_par(struct vidinfo *pvid, unsigned int win_id) { + struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; unsigned int cfg = 0; /* set window control */ @@ -107,6 +107,7 @@ static void exynos_fimd_set_buffer_address(struct vidinfo *pvid, unsigned int win_id, ulong lcd_base_addr) { + struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; unsigned long start_addr, end_addr; start_addr = lcd_base_addr; @@ -121,6 +122,7 @@ static void exynos_fimd_set_buffer_address(struct vidinfo *pvid, static void exynos_fimd_set_clock(struct vidinfo *pvid) { + struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; unsigned int cfg = 0, div = 0, remainder, remainder_div; unsigned long pixel_clock; unsigned long long src_clock; @@ -172,8 +174,9 @@ static void exynos_fimd_set_clock(struct vidinfo *pvid) writel(cfg, &fimd_ctrl->vidcon0); } -void exynos_set_trigger(void) +void exynos_set_trigger(struct vidinfo *pvid) { + struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; unsigned int cfg = 0; cfg = readl(&fimd_ctrl->trigcon); @@ -183,8 +186,9 @@ void exynos_set_trigger(void) writel(cfg, &fimd_ctrl->trigcon); } -int exynos_is_i80_frame_done(void) +int exynos_is_i80_frame_done(struct vidinfo *pvid) { + struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; unsigned int cfg = 0; int status; @@ -197,8 +201,9 @@ int exynos_is_i80_frame_done(void) return status; } -static void exynos_fimd_lcd_on(void) +static void exynos_fimd_lcd_on(struct vidinfo *pvid) { + struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; unsigned int cfg = 0; /* display on */ @@ -207,8 +212,9 @@ static void exynos_fimd_lcd_on(void) writel(cfg, &fimd_ctrl->vidcon0); } -static void exynos_fimd_window_on(unsigned int win_id) +static void exynos_fimd_window_on(struct vidinfo *pvid, unsigned int win_id) { + struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; unsigned int cfg = 0; /* enable window */ @@ -223,8 +229,9 @@ static void exynos_fimd_window_on(unsigned int win_id) writel(cfg, &fimd_ctrl->winshmap); } -void exynos_fimd_lcd_off(void) +void exynos_fimd_lcd_off(struct vidinfo *pvid) { + struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; unsigned int cfg = 0; cfg = readl(&fimd_ctrl->vidcon0); @@ -232,8 +239,9 @@ void exynos_fimd_lcd_off(void) writel(cfg, &fimd_ctrl->vidcon0); } -void exynos_fimd_window_off(unsigned int win_id) +void exynos_fimd_window_off(struct vidinfo *pvid, unsigned int win_id) { + struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; unsigned int cfg = 0; cfg = readl((unsigned int)&fimd_ctrl->wincon0 + @@ -285,8 +293,9 @@ void exynos_fimd_disable_sysmmu(void) } } -void exynos_fimd_lcd_init(struct vidinfo *vid, ulong lcd_base_address) +void exynos_fimd_lcd_init(struct vidinfo *pvid, ulong lcd_base_address) { + struct exynos_fb *fimd_ctrl; unsigned int cfg = 0, rgb_mode; unsigned int offset; unsigned int node; @@ -296,22 +305,20 @@ void exynos_fimd_lcd_init(struct vidinfo *vid, ulong lcd_base_address) if (node <= 0) debug("exynos_fb: Can't get device node for fimd\n"); - fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, - node, "reg"); + fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, node, + "reg"); if (fimd_ctrl == NULL) debug("Can't get the FIMD base address\n"); + pvid->fimd_ctrl = fimd_ctrl; if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu")) exynos_fimd_disable_sysmmu(); offset = exynos_fimd_get_base_offset(); - /* store panel info to global variable */ - pvid = vid; - - rgb_mode = vid->rgb_mode; + rgb_mode = pvid->rgb_mode; - if (vid->interface_mode == FIMD_RGB_INTERFACE) { + if (pvid->interface_mode == FIMD_RGB_INTERFACE) { cfg |= EXYNOS_VIDCON0_VIDOUT_RGB; writel(cfg, &fimd_ctrl->vidcon0); @@ -381,18 +388,18 @@ void exynos_fimd_lcd_init(struct vidinfo *vid, ulong lcd_base_address) exynos_fimd_set_clock(pvid); /* set rgb mode to dual lcd. */ - exynos_fimd_set_dualrgb(pvid->dual_lcd_enabled); + exynos_fimd_set_dualrgb(pvid, pvid->dual_lcd_enabled); /* display on */ - exynos_fimd_lcd_on(); + exynos_fimd_lcd_on(pvid); /* window on */ - exynos_fimd_window_on(pvid->win_id); + exynos_fimd_window_on(pvid, pvid->win_id); exynos_fimd_set_dp_clkcon(pvid, pvid->dp_enabled); } -unsigned long exynos_fimd_calc_fbsize(void) +unsigned long exynos_fimd_calc_fbsize(struct vidinfo *pvid) { return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8); } diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h index e1769f09d1b..1f6c6c75a27 100644 --- a/include/exynos_lcd.h +++ b/include/exynos_lcd.h @@ -75,6 +75,7 @@ typedef struct vidinfo { unsigned int sclk_div; unsigned int dual_lcd_enabled; + struct exynos_fb *fimd_ctrl; } vidinfo_t; #endif -- cgit v1.3.1 From 652d15c06e65ea910bada28925b37483b2a1a0d6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 21 Feb 2016 21:08:46 -0700 Subject: exynos: video: Move struct exynos_platform_mipi_dsim into vidinfo Put the pointer to this structure in struct vidinfo so that we can reference it without it being global. Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin Signed-off-by: Minkyu Kang --- arch/arm/mach-exynos/include/mach/mipi_dsim.h | 5 +++-- drivers/video/exynos/exynos_fb.c | 2 +- drivers/video/exynos/exynos_mipi_dsi.c | 19 ++++--------------- include/exynos_lcd.h | 1 + 4 files changed, 9 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-exynos/include/mach/mipi_dsim.h b/arch/arm/mach-exynos/include/mach/mipi_dsim.h index a77b5c8b1c4..df68186c106 100644 --- a/arch/arm/mach-exynos/include/mach/mipi_dsim.h +++ b/arch/arm/mach-exynos/include/mach/mipi_dsim.h @@ -347,9 +347,10 @@ struct mipi_dsim_lcd_driver { }; #ifdef CONFIG_EXYNOS_MIPI_DSIM -int exynos_mipi_dsi_init(void); +int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd); #else -static inline int exynos_mipi_dsi_init(void) +static inline int exynos_mipi_dsi_init( + struct exynos_platform_mipi_dsim *dsim_pd) { return 0; } diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c index abc6091049e..22b9723e549 100644 --- a/drivers/video/exynos/exynos_fb.c +++ b/drivers/video/exynos/exynos_fb.c @@ -128,7 +128,7 @@ static void lcd_panel_on(struct vidinfo *vid) exynos_enable_ldo(1); if (vid->mipi_enabled) - exynos_mipi_dsi_init(); + exynos_mipi_dsi_init(panel_info.dsim_platform_data_dt); } int exynos_lcd_early_init(const void *blob) diff --git a/drivers/video/exynos/exynos_mipi_dsi.c b/drivers/video/exynos/exynos_mipi_dsi.c index fd963821ac7..b39858a28f8 100644 --- a/drivers/video/exynos/exynos_mipi_dsi.c +++ b/drivers/video/exynos/exynos_mipi_dsi.c @@ -27,8 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct exynos_platform_mipi_dsim *dsim_pd; -static struct exynos_platform_mipi_dsim dsim_platform_data_dt; static struct mipi_dsim_lcd_device mipi_lcd_device_dt; struct mipi_dsim_ddi { @@ -175,7 +173,7 @@ static struct mipi_dsim_master_ops master_ops = { .clear_dsim_frame_done = exynos_mipi_dsi_clear_frame_done, }; -int exynos_mipi_dsi_init(void) +int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd) { struct mipi_dsim_device *dsim; struct mipi_dsim_config *dsim_config; @@ -236,16 +234,6 @@ int exynos_mipi_dsi_init(void) return 0; } -void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd) -{ - if (pd == NULL) { - debug("pd is NULL\n"); - return; - } - - dsim_pd = pd; -} - int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt) { int node; @@ -316,7 +304,8 @@ int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt) void exynos_init_dsim_platform_data(vidinfo_t *vid) { - struct mipi_dsim_config dsim_config_dt; + static struct mipi_dsim_config dsim_config_dt; + static struct exynos_platform_mipi_dsim dsim_platform_data_dt; if (exynos_dsim_config_parse_dt(gd->fdt_blob, &dsim_config_dt)) debug("Can't get proper dsim config.\n"); @@ -330,5 +319,5 @@ void exynos_init_dsim_platform_data(vidinfo_t *vid) mipi_lcd_device_dt.platform_data = (void *)&dsim_platform_data_dt; exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device_dt); - dsim_pd = &dsim_platform_data_dt; + vid->dsim_platform_data_dt = &dsim_platform_data_dt; } diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h index 1f6c6c75a27..0aa0fc71a3b 100644 --- a/include/exynos_lcd.h +++ b/include/exynos_lcd.h @@ -76,6 +76,7 @@ typedef struct vidinfo { unsigned int dual_lcd_enabled; struct exynos_fb *fimd_ctrl; + struct exynos_platform_mipi_dsim *dsim_platform_data_dt; } vidinfo_t; #endif -- cgit v1.3.1 From 21c561b7c906a05700534a4e420277e6c6012efb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 21 Feb 2016 21:08:50 -0700 Subject: video: Add an enum for active low/high This is used for video signals in some drivers so provide a standard way of representing it in an enum. Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin Signed-off-by: Minkyu Kang --- include/video.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/video.h b/include/video.h index c434bc71ae5..0d5bd21c600 100644 --- a/include/video.h +++ b/include/video.h @@ -23,6 +23,11 @@ struct video_uc_platdata { ulong base; }; +enum video_polarity { + VIDEO_ACTIVE_HIGH, /* Pins are active high */ + VIDEO_ACTIVE_LOW, /* Pins are active low */ +}; + /* * Bits per pixel selector. Each value n is such that the bits-per-pixel is * 2 ^ n -- cgit v1.3.1 From c309365089283da1cb32c2a6eeaea9eb3f638f7c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 21 Feb 2016 21:08:52 -0700 Subject: exynos: Allow tizen to be built without an LCD This file currently requires an LCD. Adjust it to work without one. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- include/libtizen.h | 2 ++ lib/tizen/tizen.c | 2 ++ 2 files changed, 4 insertions(+) (limited to 'include') diff --git a/include/libtizen.h b/include/libtizen.h index 6490fb52ba3..55dccff715d 100644 --- a/include/libtizen.h +++ b/include/libtizen.h @@ -10,6 +10,8 @@ #define HD_RESOLUTION 0 +#ifdef CONFIG_LCD void get_tizen_logo_info(vidinfo_t *vid); +#endif #endif /* _LIBTIZEN_H_ */ diff --git a/lib/tizen/tizen.c b/lib/tizen/tizen.c index 814ed18329e..d207f77d0b3 100644 --- a/lib/tizen/tizen.c +++ b/lib/tizen/tizen.c @@ -12,6 +12,7 @@ #include "tizen_logo_16bpp.h" #include "tizen_logo_16bpp_gzip.h" +#ifdef CONFIG_LCD void get_tizen_logo_info(vidinfo_t *vid) { switch (vid->vl_bpix) { @@ -31,3 +32,4 @@ void get_tizen_logo_info(vidinfo_t *vid) break; } } +#endif -- cgit v1.3.1 From ea743e659fbfa9ba4b00ba076cdbf212d6fff081 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 21 Feb 2016 21:08:54 -0700 Subject: exynos: Disable LCD display for boards we can't convert Some boards have the LCD enabled but I cannot test operation for the driver model conversion. Disable the LCD on these to avoid build errors. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- board/samsung/trats/trats.c | 2 ++ board/samsung/universal_c210/universal.c | 2 ++ include/configs/s5pc210_universal.h | 3 --- include/configs/smdk5250.h | 3 +++ include/configs/smdk5420.h | 4 ++++ include/configs/trats.h | 4 ---- include/configs/trats2.h | 4 ---- 7 files changed, 11 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 54d01ec439a..66a54d436de 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -596,6 +596,7 @@ int mipi_power(void) return 0; } +#ifdef CONFIG_LCD void exynos_lcd_misc_init(vidinfo_t *vid) { #ifdef CONFIG_TIZEN @@ -606,3 +607,4 @@ void exynos_lcd_misc_init(vidinfo_t *vid) setenv("lcdinfo", "lcd=s6e8ax0"); #endif } +#endif diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 426ae14af26..81e35b6f759 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -367,6 +367,7 @@ int exynos_init(void) return 0; } +#ifdef CONFIG_LCD void exynos_lcd_misc_init(vidinfo_t *vid) { #ifdef CONFIG_TIZEN @@ -379,3 +380,4 @@ void exynos_lcd_misc_init(vidinfo_t *vid) setenv("lcdinfo", "lcd=ld9040"); } +#endif diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index bdb368ed33b..99153067b29 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -217,9 +217,6 @@ int universal_spi_read(void); /* * LCD Settings */ -#define CONFIG_EXYNOS_FB -#define CONFIG_LCD -#define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP #define CONFIG_LD9040 #define CONFIG_VIDEO_BMP_GZIP diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index f66bb121f32..92a08332a3c 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -13,6 +13,9 @@ #include #include +#undef CONFIG_LCD +#undef CONFIG_EXYNOS_FB +#undef CONFIG_EXYNOS_DP #undef CONFIG_KEYBOARD #define CONFIG_BOARD_COMMON diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 9cf886c0664..5fe21d9afd8 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -13,6 +13,10 @@ #include #include +#undef CONFIG_LCD +#undef CONFIG_EXYNOS_FB +#undef CONFIG_EXYNOS_DP + #undef CONFIG_KEYBOARD #define CONFIG_BOARD_COMMON diff --git a/include/configs/trats.h b/include/configs/trats.h index 0c875cb47fc..22b0c90ee96 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -242,12 +242,8 @@ #define CONFIG_SYS_WHITE_ON_BLACK /* LCD */ -#define CONFIG_EXYNOS_FB -#define CONFIG_LCD -#define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP #define CONFIG_FB_ADDR 0x52504000 -#define CONFIG_S6E8AX0 #define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 492a253d73a..1febaaef51f 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -222,12 +222,8 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_SYS_WHITE_ON_BLACK /* LCD */ -#define CONFIG_EXYNOS_FB -#define CONFIG_LCD -#define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP #define CONFIG_FB_ADDR 0x52504000 -#define CONFIG_S6E8AX0 #define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) -- cgit v1.3.1 From 7b0789e8fcfe052113bcf06dad1d6da6b4d6b108 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 21 Feb 2016 21:08:55 -0700 Subject: dts: Add clock and regulator binding files for max77802 These are used by peach_pit and peach_pi. Add them so they can be referenced in the device tree files. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- include/dt-bindings/clock/maxim,max77802.h | 22 ++++++++++++++++++++++ include/dt-bindings/regulator/maxim,max77802.h | 18 ++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 include/dt-bindings/clock/maxim,max77802.h create mode 100644 include/dt-bindings/regulator/maxim,max77802.h (limited to 'include') diff --git a/include/dt-bindings/clock/maxim,max77802.h b/include/dt-bindings/clock/maxim,max77802.h new file mode 100644 index 00000000000..997312edcbb --- /dev/null +++ b/include/dt-bindings/clock/maxim,max77802.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants clocks for the Maxim 77802 PMIC. + */ + +#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H +#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H + +/* Fixed rate clocks. */ + +#define MAX77802_CLK_32K_AP 0 +#define MAX77802_CLK_32K_CP 1 + +/* Total number of clocks. */ +#define MAX77802_CLKS_NUM (MAX77802_CLK_32K_CP + 1) + +#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */ diff --git a/include/dt-bindings/regulator/maxim,max77802.h b/include/dt-bindings/regulator/maxim,max77802.h new file mode 100644 index 00000000000..cf28631d710 --- /dev/null +++ b/include/dt-bindings/regulator/maxim,max77802.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for the Maxim 77802 PMIC regulators + */ + +#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H +#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H + +/* Regulator operating modes */ +#define MAX77802_OPMODE_LP 1 +#define MAX77802_OPMODE_NORMAL 3 + +#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */ -- cgit v1.3.1 From 8b449a6639c6bee1a97c0eba2ab142a7c471d9b1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 21 Feb 2016 21:09:00 -0700 Subject: exynos: video: Rename variables for driver model Use 'priv' for a private pointer and 'regs' for a register pointer. Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin Signed-off-by: Minkyu Kang --- drivers/video/exynos/exynos_dp.c | 434 +++++++++++++++--------------- drivers/video/exynos/exynos_dp_lowlevel.c | 71 +++-- drivers/video/exynos/exynos_dp_lowlevel.h | 2 +- drivers/video/exynos/exynos_fb.c | 234 ++++++++-------- include/exynos_lcd.h | 2 +- 5 files changed, 370 insertions(+), 373 deletions(-) (limited to 'include') diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c index 0d4ceef62bb..d7bccc3708f 100644 --- a/drivers/video/exynos/exynos_dp.c +++ b/drivers/video/exynos/exynos_dp.c @@ -33,20 +33,20 @@ static void exynos_dp_disp_info(struct edp_disp_info *disp_info) return; } -static int exynos_dp_init_dp(struct exynos_dp *dp_regs) +static int exynos_dp_init_dp(struct exynos_dp *regs) { int ret; - exynos_dp_reset(dp_regs); + exynos_dp_reset(regs); /* SW defined function Normal operation */ - exynos_dp_enable_sw_func(dp_regs, DP_ENABLE); + exynos_dp_enable_sw_func(regs, DP_ENABLE); - ret = exynos_dp_init_analog_func(dp_regs); + ret = exynos_dp_init_analog_func(regs); if (ret != EXYNOS_DP_SUCCESS) return ret; - exynos_dp_init_hpd(dp_regs); - exynos_dp_init_aux(dp_regs); + exynos_dp_init_hpd(regs); + exynos_dp_init_aux(regs); return ret; } @@ -62,7 +62,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data) return sum; } -static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs) +static unsigned int exynos_dp_read_edid(struct exynos_dp *regs) { unsigned char edid[EDID_BLOCK_LENGTH * 2]; unsigned int extend_block = 0; @@ -77,14 +77,14 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs) */ /* Read Extension Flag, Number of 128-byte EDID extension blocks */ - exynos_dp_read_byte_from_i2c(dp_regs, I2C_EDID_DEVICE_ADDR, + exynos_dp_read_byte_from_i2c(regs, I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG, &extend_block); if (extend_block > 0) { printf("DP EDID data includes a single extension!\n"); /* Read EDID data */ - retval = exynos_dp_read_bytes_from_i2c(dp_regs, + retval = exynos_dp_read_bytes_from_i2c(regs, I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, EDID_BLOCK_LENGTH, @@ -100,7 +100,7 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs) } /* Read additional EDID data */ - retval = exynos_dp_read_bytes_from_i2c(dp_regs, + retval = exynos_dp_read_bytes_from_i2c(regs, I2C_EDID_DEVICE_ADDR, EDID_BLOCK_LENGTH, EDID_BLOCK_LENGTH, @@ -115,13 +115,13 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs) return -1; } - exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_TEST_REQUEST, + exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST, &test_vector); if (test_vector & DPCD_TEST_EDID_READ) { - exynos_dp_write_byte_to_dpcd(dp_regs, + exynos_dp_write_byte_to_dpcd(regs, DPCD_TEST_EDID_CHECKSUM, edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); - exynos_dp_write_byte_to_dpcd(dp_regs, + exynos_dp_write_byte_to_dpcd(regs, DPCD_TEST_RESPONSE, DPCD_TEST_EDID_CHECKSUM_WRITE); } @@ -129,7 +129,7 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs) debug("DP EDID data does not include any extensions.\n"); /* Read EDID data */ - retval = exynos_dp_read_bytes_from_i2c(dp_regs, + retval = exynos_dp_read_bytes_from_i2c(regs, I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, EDID_BLOCK_LENGTH, @@ -145,12 +145,12 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs) return -1; } - exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_TEST_REQUEST, + exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST, &test_vector); if (test_vector & DPCD_TEST_EDID_READ) { - exynos_dp_write_byte_to_dpcd(dp_regs, + exynos_dp_write_byte_to_dpcd(regs, DPCD_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); - exynos_dp_write_byte_to_dpcd(dp_regs, + exynos_dp_write_byte_to_dpcd(regs, DPCD_TEST_RESPONSE, DPCD_TEST_EDID_CHECKSUM_WRITE); } @@ -161,8 +161,8 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs) return 0; } -static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs, - struct exynos_dp_priv *edp_info) +static unsigned int exynos_dp_handle_edid(struct exynos_dp *regs, + struct exynos_dp_priv *priv) { unsigned char buf[12]; unsigned int ret; @@ -180,7 +180,7 @@ static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs, retry_cnt = 5; while (retry_cnt) { /* Read DPCD 0x0000-0x000b */ - ret = exynos_dp_read_bytes_from_dpcd(dp_regs, DPCD_DPCD_REV, 12, + ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_DPCD_REV, 12, buf); if (ret != EXYNOS_DP_SUCCESS) { if (retry_cnt == 0) { @@ -195,7 +195,7 @@ static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs, /* */ temp = buf[DPCD_DPCD_REV]; if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11) - edp_info->dpcd_rev = temp; + priv->dpcd_rev = temp; else { printf("DP Wrong DPCD Rev : %x\n", temp); return -ENODEV; @@ -203,33 +203,33 @@ static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs, temp = buf[DPCD_MAX_LINK_RATE]; if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70) - edp_info->lane_bw = temp; + priv->lane_bw = temp; else { printf("DP Wrong MAX LINK RATE : %x\n", temp); return -EINVAL; } /* Refer VESA Display Port Standard Ver1.1a Page 120 */ - if (edp_info->dpcd_rev == DP_DPCD_REV_11) { + if (priv->dpcd_rev == DP_DPCD_REV_11) { temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f; if (buf[DPCD_MAX_LANE_COUNT] & 0x80) - edp_info->dpcd_efc = 1; + priv->dpcd_efc = 1; else - edp_info->dpcd_efc = 0; + priv->dpcd_efc = 0; } else { temp = buf[DPCD_MAX_LANE_COUNT]; - edp_info->dpcd_efc = 0; + priv->dpcd_efc = 0; } if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 || temp == DP_LANE_CNT_4) { - edp_info->lane_cnt = temp; + priv->lane_cnt = temp; } else { printf("DP Wrong MAX LANE COUNT : %x\n", temp); return -EINVAL; } - ret = exynos_dp_read_edid(dp_regs); + ret = exynos_dp_read_edid(regs); if (ret != EXYNOS_DP_SUCCESS) { printf("DP exynos_dp_read_edid() failed\n"); return -EINVAL; @@ -238,35 +238,35 @@ static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs, return ret; } -static void exynos_dp_init_training(struct exynos_dp *dp_regs) +static void exynos_dp_init_training(struct exynos_dp *regs) { /* * MACRO_RST must be applied after the PLL_LOCK to avoid * the DP inter pair skew issue for at least 10 us */ - exynos_dp_reset_macro(dp_regs); + exynos_dp_reset_macro(regs); /* All DP analog module power up */ - exynos_dp_set_analog_power_down(dp_regs, POWER_ALL, 0); + exynos_dp_set_analog_power_down(regs, POWER_ALL, 0); } -static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs, - struct exynos_dp_priv *edp_info) +static unsigned int exynos_dp_link_start(struct exynos_dp *regs, + struct exynos_dp_priv *priv) { unsigned char buf[5]; unsigned int ret = 0; debug("DP: %s was called\n", __func__); - edp_info->lt_info.lt_status = DP_LT_CR; - edp_info->lt_info.ep_loop = 0; - edp_info->lt_info.cr_loop[0] = 0; - edp_info->lt_info.cr_loop[1] = 0; - edp_info->lt_info.cr_loop[2] = 0; - edp_info->lt_info.cr_loop[3] = 0; + priv->lt_info.lt_status = DP_LT_CR; + priv->lt_info.ep_loop = 0; + priv->lt_info.cr_loop[0] = 0; + priv->lt_info.cr_loop[1] = 0; + priv->lt_info.cr_loop[2] = 0; + priv->lt_info.cr_loop[3] = 0; /* Set sink to D0 (Sink Not Ready) mode. */ - ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_SINK_POWER_STATE, + ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_SINK_POWER_STATE, DPCD_SET_POWER_STATE_D0); if (ret != EXYNOS_DP_SUCCESS) { printf("DP write_dpcd_byte failed\n"); @@ -274,24 +274,24 @@ static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs, } /* Set link rate and count as you want to establish */ - exynos_dp_set_link_bandwidth(dp_regs, edp_info->lane_bw); - exynos_dp_set_lane_count(dp_regs, edp_info->lane_cnt); + exynos_dp_set_link_bandwidth(regs, priv->lane_bw); + exynos_dp_set_lane_count(regs, priv->lane_cnt); /* Setup RX configuration */ - buf[0] = edp_info->lane_bw; - buf[1] = edp_info->lane_cnt; + buf[0] = priv->lane_bw; + buf[1] = priv->lane_cnt; - ret = exynos_dp_write_bytes_to_dpcd(dp_regs, DPCD_LINK_BW_SET, 2, buf); + ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_LINK_BW_SET, 2, buf); if (ret != EXYNOS_DP_SUCCESS) { printf("DP write_dpcd_byte failed\n"); return ret; } - exynos_dp_set_lane_pre_emphasis(dp_regs, PRE_EMPHASIS_LEVEL_0, - edp_info->lane_cnt); + exynos_dp_set_lane_pre_emphasis(regs, PRE_EMPHASIS_LEVEL_0, + priv->lane_cnt); /* Set training pattern 1 */ - exynos_dp_set_training_pattern(dp_regs, TRAINING_PTN1); + exynos_dp_set_training_pattern(regs, TRAINING_PTN1); /* Set RX training pattern */ buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1; @@ -305,7 +305,7 @@ static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs, buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; - ret = exynos_dp_write_bytes_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET, + ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET, 5, buf); if (ret != EXYNOS_DP_SUCCESS) { printf("DP write_dpcd_byte failed\n"); @@ -315,13 +315,13 @@ static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs, return ret; } -static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *dp_regs) +static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs) { unsigned int ret = EXYNOS_DP_SUCCESS; - exynos_dp_set_training_pattern(dp_regs, DP_NONE); + exynos_dp_set_training_pattern(regs, DP_NONE); - ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET, + ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET, DPCD_TRAINING_PATTERN_DISABLED); if (ret != EXYNOS_DP_SUCCESS) { printf("DP request_link_training_req failed\n"); @@ -332,12 +332,12 @@ static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *dp_regs) } static unsigned int exynos_dp_enable_rx_to_enhanced_mode( - struct exynos_dp *dp_regs, unsigned char enable) + struct exynos_dp *regs, unsigned char enable) { unsigned char data; unsigned int ret = EXYNOS_DP_SUCCESS; - ret = exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_LANE_COUNT_SET, + ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET, &data); if (ret != EXYNOS_DP_SUCCESS) { printf("DP read_from_dpcd failed\n"); @@ -349,7 +349,7 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode( else data = DPCD_LN_COUNT_SET(data); - ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_LANE_COUNT_SET, data); + ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_LANE_COUNT_SET, data); if (ret != EXYNOS_DP_SUCCESS) { printf("DP write_to_dpcd failed\n"); return -EAGAIN; @@ -359,24 +359,24 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode( return ret; } -static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *dp_regs, +static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs, unsigned char enhance_mode) { unsigned int ret = EXYNOS_DP_SUCCESS; - ret = exynos_dp_enable_rx_to_enhanced_mode(dp_regs, enhance_mode); + ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode); if (ret != EXYNOS_DP_SUCCESS) { printf("DP rx_enhance_mode failed\n"); return -EAGAIN; } - exynos_dp_enable_enhanced_mode(dp_regs, enhance_mode); + exynos_dp_enable_enhanced_mode(regs, enhance_mode); return ret; } -static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *dp_regs, - struct exynos_dp_priv *edp_info, +static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *regs, + struct exynos_dp_priv *priv, unsigned char *status) { unsigned int ret, i; @@ -389,14 +389,14 @@ static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *dp_regs, shift_val[2] = 0; shift_val[3] = 4; - ret = exynos_dp_read_bytes_from_dpcd(dp_regs, DPCD_LANE0_1_STATUS, 2, + ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_LANE0_1_STATUS, 2, buf); if (ret != EXYNOS_DP_SUCCESS) { printf("DP read lane status failed\n"); return ret; } - for (i = 0; i < edp_info->lane_cnt; i++) { + for (i = 0; i < priv->lane_cnt; i++) { lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f; if (lane_stat[0] != lane_stat[i]) { printf("Wrong lane status\n"); @@ -409,7 +409,7 @@ static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *dp_regs, return ret; } -static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *dp_regs, +static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs, unsigned char lane_num, unsigned char *sw, unsigned char *em) { unsigned int ret = EXYNOS_DP_SUCCESS; @@ -420,7 +420,7 @@ static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *dp_regs, /* lane_num value is used as array index, so this range 0 ~ 3 */ dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2); - ret = exynos_dp_read_byte_from_dpcd(dp_regs, dpcd_addr, &buf); + ret = exynos_dp_read_byte_from_dpcd(regs, dpcd_addr, &buf); if (ret != EXYNOS_DP_SUCCESS) { printf("DP read adjust request failed\n"); return -EAGAIN; @@ -432,53 +432,53 @@ static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *dp_regs, return ret; } -static int exynos_dp_equalizer_err_link(struct exynos_dp *dp_regs, - struct exynos_dp_priv *edp_info) +static int exynos_dp_equalizer_err_link(struct exynos_dp *regs, + struct exynos_dp_priv *priv) { int ret; - ret = exynos_dp_training_pattern_dis(dp_regs); + ret = exynos_dp_training_pattern_dis(regs); if (ret != EXYNOS_DP_SUCCESS) { printf("DP training_pattern_disable() failed\n"); - edp_info->lt_info.lt_status = DP_LT_FAIL; + priv->lt_info.lt_status = DP_LT_FAIL; } - ret = exynos_dp_set_enhanced_mode(dp_regs, edp_info->dpcd_efc); + ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc); if (ret != EXYNOS_DP_SUCCESS) { printf("DP set_enhanced_mode() failed\n"); - edp_info->lt_info.lt_status = DP_LT_FAIL; + priv->lt_info.lt_status = DP_LT_FAIL; } return ret; } -static int exynos_dp_reduce_link_rate(struct exynos_dp *dp_regs, - struct exynos_dp_priv *edp_info) +static int exynos_dp_reduce_link_rate(struct exynos_dp *regs, + struct exynos_dp_priv *priv) { int ret; - if (edp_info->lane_bw == DP_LANE_BW_2_70) { - edp_info->lane_bw = DP_LANE_BW_1_62; + if (priv->lane_bw == DP_LANE_BW_2_70) { + priv->lane_bw = DP_LANE_BW_1_62; printf("DP Change lane bw to 1.62Gbps\n"); - edp_info->lt_info.lt_status = DP_LT_START; + priv->lt_info.lt_status = DP_LT_START; ret = EXYNOS_DP_SUCCESS; } else { - ret = exynos_dp_training_pattern_dis(dp_regs); + ret = exynos_dp_training_pattern_dis(regs); if (ret != EXYNOS_DP_SUCCESS) printf("DP training_patter_disable() failed\n"); - ret = exynos_dp_set_enhanced_mode(dp_regs, edp_info->dpcd_efc); + ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc); if (ret != EXYNOS_DP_SUCCESS) printf("DP set_enhanced_mode() failed\n"); - edp_info->lt_info.lt_status = DP_LT_FAIL; + priv->lt_info.lt_status = DP_LT_FAIL; } return ret; } -static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs, - struct exynos_dp_priv *edp_info) +static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs, + struct exynos_dp_priv *priv) { unsigned int ret = EXYNOS_DP_SUCCESS; unsigned char lane_stat; @@ -491,22 +491,22 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs, debug("DP: %s was called\n", __func__); mdelay(1); - ret = exynos_dp_read_dpcd_lane_stat(dp_regs, edp_info, &lane_stat); + ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat); if (ret != EXYNOS_DP_SUCCESS) { printf("DP read lane status failed\n"); - edp_info->lt_info.lt_status = DP_LT_FAIL; + priv->lt_info.lt_status = DP_LT_FAIL; return ret; } if (lane_stat & DP_LANE_STAT_CR_DONE) { debug("DP clock Recovery training succeed\n"); - exynos_dp_set_training_pattern(dp_regs, TRAINING_PTN2); + exynos_dp_set_training_pattern(regs, TRAINING_PTN2); - for (i = 0; i < edp_info->lane_cnt; i++) { - ret = exynos_dp_read_dpcd_adj_req(dp_regs, i, + for (i = 0; i < priv->lane_cnt; i++) { + ret = exynos_dp_read_dpcd_adj_req(regs, i, &adj_req_sw, &adj_req_em); if (ret != EXYNOS_DP_SUCCESS) { - edp_info->lt_info.lt_status = DP_LT_FAIL; + priv->lt_info.lt_status = DP_LT_FAIL; return ret; } @@ -518,7 +518,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs, lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 | MAX_PRE_EMPHASIS_REACH_3; } - exynos_dp_set_lanex_pre_emphasis(dp_regs, + exynos_dp_set_lanex_pre_emphasis(regs, lt_ctl_val[i], i); } @@ -528,39 +528,39 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs, buf[3] = lt_ctl_val[2]; buf[4] = lt_ctl_val[3]; - ret = exynos_dp_write_bytes_to_dpcd(dp_regs, + ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET, 5, buf); if (ret != EXYNOS_DP_SUCCESS) { printf("DP write training pattern1 failed\n"); - edp_info->lt_info.lt_status = DP_LT_FAIL; + priv->lt_info.lt_status = DP_LT_FAIL; return ret; } else - edp_info->lt_info.lt_status = DP_LT_ET; + priv->lt_info.lt_status = DP_LT_ET; } else { - for (i = 0; i < edp_info->lane_cnt; i++) { + for (i = 0; i < priv->lane_cnt; i++) { lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis( - dp_regs, i); - ret = exynos_dp_read_dpcd_adj_req(dp_regs, i, + regs, i); + ret = exynos_dp_read_dpcd_adj_req(regs, i, &adj_req_sw, &adj_req_em); if (ret != EXYNOS_DP_SUCCESS) { printf("DP read adj req failed\n"); - edp_info->lt_info.lt_status = DP_LT_FAIL; + priv->lt_info.lt_status = DP_LT_FAIL; return ret; } if ((adj_req_sw == VOLTAGE_LEVEL_3) || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) - ret = exynos_dp_reduce_link_rate(dp_regs, - edp_info); + ret = exynos_dp_reduce_link_rate(regs, + priv); if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) == adj_req_sw) && (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) == adj_req_em)) { - edp_info->lt_info.cr_loop[i]++; - if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP) + priv->lt_info.cr_loop[i]++; + if (priv->lt_info.cr_loop[i] == MAX_CR_LOOP) ret = exynos_dp_reduce_link_rate( - dp_regs, edp_info); + regs, priv); } lt_ctl_val[i] = 0; @@ -571,15 +571,15 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs, lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 | MAX_PRE_EMPHASIS_REACH_3; } - exynos_dp_set_lanex_pre_emphasis(dp_regs, + exynos_dp_set_lanex_pre_emphasis(regs, lt_ctl_val[i], i); } - ret = exynos_dp_write_bytes_to_dpcd(dp_regs, + ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val); if (ret != EXYNOS_DP_SUCCESS) { printf("DP write training pattern2 failed\n"); - edp_info->lt_info.lt_status = DP_LT_FAIL; + priv->lt_info.lt_status = DP_LT_FAIL; return ret; } } @@ -588,7 +588,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs, } static unsigned int exynos_dp_process_equalizer_training( - struct exynos_dp *dp_regs, struct exynos_dp_priv *edp_info) + struct exynos_dp *regs, struct exynos_dp_priv *priv) { unsigned int ret = EXYNOS_DP_SUCCESS; unsigned char lane_stat, adj_req_sw, adj_req_em, i; @@ -600,33 +600,33 @@ static unsigned int exynos_dp_process_equalizer_training( mdelay(1); - ret = exynos_dp_read_dpcd_lane_stat(dp_regs, edp_info, &lane_stat); + ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat); if (ret != EXYNOS_DP_SUCCESS) { printf("DP read lane status failed\n"); - edp_info->lt_info.lt_status = DP_LT_FAIL; + priv->lt_info.lt_status = DP_LT_FAIL; return ret; } debug("DP lane stat : %x\n", lane_stat); if (lane_stat & DP_LANE_STAT_CR_DONE) { - ret = exynos_dp_read_byte_from_dpcd(dp_regs, + ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LN_ALIGN_UPDATED, &sink_stat); if (ret != EXYNOS_DP_SUCCESS) { - edp_info->lt_info.lt_status = DP_LT_FAIL; + priv->lt_info.lt_status = DP_LT_FAIL; return ret; } interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE); - for (i = 0; i < edp_info->lane_cnt; i++) { - ret = exynos_dp_read_dpcd_adj_req(dp_regs, i, + for (i = 0; i < priv->lane_cnt; i++) { + ret = exynos_dp_read_dpcd_adj_req(regs, i, &adj_req_sw, &adj_req_em); if (ret != EXYNOS_DP_SUCCESS) { printf("DP read adj req 1 failed\n"); - edp_info->lt_info.lt_status = DP_LT_FAIL; + priv->lt_info.lt_status = DP_LT_FAIL; return ret; } @@ -646,91 +646,91 @@ static unsigned int exynos_dp_process_equalizer_training( && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) { debug("DP Equalizer training succeed\n"); - f_bw = exynos_dp_get_link_bandwidth(dp_regs); - f_lane_cnt = exynos_dp_get_lane_count(dp_regs); + f_bw = exynos_dp_get_link_bandwidth(regs); + f_lane_cnt = exynos_dp_get_lane_count(regs); debug("DP final BandWidth : %x\n", f_bw); debug("DP final Lane Count : %x\n", f_lane_cnt); - edp_info->lt_info.lt_status = DP_LT_FINISHED; + priv->lt_info.lt_status = DP_LT_FINISHED; - exynos_dp_equalizer_err_link(dp_regs, edp_info); + exynos_dp_equalizer_err_link(regs, priv); } else { - edp_info->lt_info.ep_loop++; + priv->lt_info.ep_loop++; - if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) { - if (edp_info->lane_bw == DP_LANE_BW_2_70) { + if (priv->lt_info.ep_loop > MAX_EQ_LOOP) { + if (priv->lane_bw == DP_LANE_BW_2_70) { ret = exynos_dp_reduce_link_rate( - dp_regs, edp_info); + regs, priv); } else { - edp_info->lt_info.lt_status = + priv->lt_info.lt_status = DP_LT_FAIL; - exynos_dp_equalizer_err_link(dp_regs, - edp_info); + exynos_dp_equalizer_err_link(regs, + priv); } } else { - for (i = 0; i < edp_info->lane_cnt; i++) + for (i = 0; i < priv->lane_cnt; i++) exynos_dp_set_lanex_pre_emphasis( - dp_regs, lt_ctl_val[i], i); + regs, lt_ctl_val[i], i); - ret = exynos_dp_write_bytes_to_dpcd(dp_regs, + ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val); if (ret != EXYNOS_DP_SUCCESS) { printf("DP set lt pattern failed\n"); - edp_info->lt_info.lt_status = + priv->lt_info.lt_status = DP_LT_FAIL; - exynos_dp_equalizer_err_link(dp_regs, - edp_info); + exynos_dp_equalizer_err_link(regs, + priv); } } } - } else if (edp_info->lane_bw == DP_LANE_BW_2_70) { - ret = exynos_dp_reduce_link_rate(dp_regs, edp_info); + } else if (priv->lane_bw == DP_LANE_BW_2_70) { + ret = exynos_dp_reduce_link_rate(regs, priv); } else { - edp_info->lt_info.lt_status = DP_LT_FAIL; - exynos_dp_equalizer_err_link(dp_regs, edp_info); + priv->lt_info.lt_status = DP_LT_FAIL; + exynos_dp_equalizer_err_link(regs, priv); } return ret; } -static unsigned int exynos_dp_sw_link_training(struct exynos_dp *dp_regs, - struct exynos_dp_priv *edp_info) +static unsigned int exynos_dp_sw_link_training(struct exynos_dp *regs, + struct exynos_dp_priv *priv) { unsigned int ret = 0; int training_finished; /* Turn off unnecessary lane */ - if (edp_info->lane_cnt == 1) - exynos_dp_set_analog_power_down(dp_regs, CH1_BLOCK, 1); + if (priv->lane_cnt == 1) + exynos_dp_set_analog_power_down(regs, CH1_BLOCK, 1); training_finished = 0; - edp_info->lt_info.lt_status = DP_LT_START; + priv->lt_info.lt_status = DP_LT_START; /* Process here */ while (!training_finished) { - switch (edp_info->lt_info.lt_status) { + switch (priv->lt_info.lt_status) { case DP_LT_START: - ret = exynos_dp_link_start(dp_regs, edp_info); + ret = exynos_dp_link_start(regs, priv); if (ret != EXYNOS_DP_SUCCESS) { printf("DP LT:link start failed\n"); return ret; } break; case DP_LT_CR: - ret = exynos_dp_process_clock_recovery(dp_regs, - edp_info); + ret = exynos_dp_process_clock_recovery(regs, + priv); if (ret != EXYNOS_DP_SUCCESS) { printf("DP LT:clock recovery failed\n"); return ret; } break; case DP_LT_ET: - ret = exynos_dp_process_equalizer_training(dp_regs, - edp_info); + ret = exynos_dp_process_equalizer_training(regs, + priv); if (ret != EXYNOS_DP_SUCCESS) { printf("DP LT:equalizer training failed\n"); return ret; @@ -747,75 +747,75 @@ static unsigned int exynos_dp_sw_link_training(struct exynos_dp *dp_regs, return ret; } -static unsigned int exynos_dp_set_link_train(struct exynos_dp *dp_regs, - struct exynos_dp_priv *edp_info) +static unsigned int exynos_dp_set_link_train(struct exynos_dp *regs, + struct exynos_dp_priv *priv) { unsigned int ret; - exynos_dp_init_training(dp_regs); + exynos_dp_init_training(regs); - ret = exynos_dp_sw_link_training(dp_regs, edp_info); + ret = exynos_dp_sw_link_training(regs, priv); if (ret != EXYNOS_DP_SUCCESS) printf("DP dp_sw_link_training() failed\n"); return ret; } -static void exynos_dp_enable_scramble(struct exynos_dp *dp_regs, +static void exynos_dp_enable_scramble(struct exynos_dp *regs, unsigned int enable) { unsigned char data; if (enable) { - exynos_dp_enable_scrambling(dp_regs, DP_ENABLE); + exynos_dp_enable_scrambling(regs, DP_ENABLE); - exynos_dp_read_byte_from_dpcd(dp_regs, + exynos_dp_read_byte_from_dpcd(regs, DPCD_TRAINING_PATTERN_SET, &data); - exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET, + exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET, (u8)(data & ~DPCD_SCRAMBLING_DISABLED)); } else { - exynos_dp_enable_scrambling(dp_regs, DP_DISABLE); - exynos_dp_read_byte_from_dpcd(dp_regs, + exynos_dp_enable_scrambling(regs, DP_DISABLE); + exynos_dp_read_byte_from_dpcd(regs, DPCD_TRAINING_PATTERN_SET, &data); - exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET, + exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET, (u8)(data | DPCD_SCRAMBLING_DISABLED)); } } -static unsigned int exynos_dp_config_video(struct exynos_dp *dp_regs, - struct exynos_dp_priv *edp_info) +static unsigned int exynos_dp_config_video(struct exynos_dp *regs, + struct exynos_dp_priv *priv) { unsigned int ret = 0; unsigned int retry_cnt; mdelay(1); - if (edp_info->video_info.master_mode) { + if (priv->video_info.master_mode) { printf("DP does not support master mode\n"); return -ENODEV; } else { /* debug slave */ - exynos_dp_config_video_slave_mode(dp_regs, - &edp_info->video_info); + exynos_dp_config_video_slave_mode(regs, + &priv->video_info); } - exynos_dp_set_video_color_format(dp_regs, &edp_info->video_info); + exynos_dp_set_video_color_format(regs, &priv->video_info); - if (edp_info->video_info.bist_mode) { - if (exynos_dp_config_video_bist(dp_regs, edp_info) != 0) + if (priv->video_info.bist_mode) { + if (exynos_dp_config_video_bist(regs, priv) != 0) return -1; } - ret = exynos_dp_get_pll_lock_status(dp_regs); + ret = exynos_dp_get_pll_lock_status(regs); if (ret != PLL_LOCKED) { printf("DP PLL is not locked yet\n"); return -EIO; } - if (edp_info->video_info.master_mode == 0) { + if (priv->video_info.master_mode == 0) { retry_cnt = 10; while (retry_cnt) { - ret = exynos_dp_is_slave_video_stream_clock_on(dp_regs); + ret = exynos_dp_is_slave_video_stream_clock_on(regs); if (ret != EXYNOS_DP_SUCCESS) { if (retry_cnt == 0) { printf("DP stream_clock_on failed\n"); @@ -829,34 +829,34 @@ static unsigned int exynos_dp_config_video(struct exynos_dp *dp_regs, } /* Set to use the register calculated M/N video */ - exynos_dp_set_video_cr_mn(dp_regs, CALCULATED_M, 0, 0); + exynos_dp_set_video_cr_mn(regs, CALCULATED_M, 0, 0); /* For video bist, Video timing must be generated by register */ - exynos_dp_set_video_timing_mode(dp_regs, VIDEO_TIMING_FROM_CAPTURE); + exynos_dp_set_video_timing_mode(regs, VIDEO_TIMING_FROM_CAPTURE); /* Enable video bist */ - if (edp_info->video_info.bist_pattern != COLOR_RAMP && - edp_info->video_info.bist_pattern != BALCK_WHITE_V_LINES && - edp_info->video_info.bist_pattern != COLOR_SQUARE) - exynos_dp_enable_video_bist(dp_regs, - edp_info->video_info.bist_mode); + if (priv->video_info.bist_pattern != COLOR_RAMP && + priv->video_info.bist_pattern != BALCK_WHITE_V_LINES && + priv->video_info.bist_pattern != COLOR_SQUARE) + exynos_dp_enable_video_bist(regs, + priv->video_info.bist_mode); else - exynos_dp_enable_video_bist(dp_regs, DP_DISABLE); + exynos_dp_enable_video_bist(regs, DP_DISABLE); /* Disable video mute */ - exynos_dp_enable_video_mute(dp_regs, DP_DISABLE); + exynos_dp_enable_video_mute(regs, DP_DISABLE); /* Configure video Master or Slave mode */ - exynos_dp_enable_video_master(dp_regs, - edp_info->video_info.master_mode); + exynos_dp_enable_video_master(regs, + priv->video_info.master_mode); /* Enable video */ - exynos_dp_start_video(dp_regs); + exynos_dp_start_video(regs); - if (edp_info->video_info.master_mode == 0) { + if (priv->video_info.master_mode == 0) { retry_cnt = 100; while (retry_cnt) { - ret = exynos_dp_is_video_stream_on(dp_regs); + ret = exynos_dp_is_video_stream_on(regs); if (ret != EXYNOS_DP_SUCCESS) { if (retry_cnt == 0) { printf("DP Timeout of video stream\n"); @@ -872,7 +872,7 @@ static unsigned int exynos_dp_config_video(struct exynos_dp *dp_regs, return ret; } -int exynos_dp_parse_dt(const void *blob, struct exynos_dp_priv *edp_info) +int exynos_dp_parse_dt(const void *blob, struct exynos_dp_priv *priv) { unsigned int node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_DP); @@ -881,47 +881,47 @@ int exynos_dp_parse_dt(const void *blob, struct exynos_dp_priv *edp_info) return -ENODEV; } - edp_info->disp_info.h_res = fdtdec_get_int(blob, node, + priv->disp_info.h_res = fdtdec_get_int(blob, node, "samsung,h-res", 0); - edp_info->disp_info.h_sync_width = fdtdec_get_int(blob, node, + priv->disp_info.h_sync_width = fdtdec_get_int(blob, node, "samsung,h-sync-width", 0); - edp_info->disp_info.h_back_porch = fdtdec_get_int(blob, node, + priv->disp_info.h_back_porch = fdtdec_get_int(blob, node, "samsung,h-back-porch", 0); - edp_info->disp_info.h_front_porch = fdtdec_get_int(blob, node, + priv->disp_info.h_front_porch = fdtdec_get_int(blob, node, "samsung,h-front-porch", 0); - edp_info->disp_info.v_res = fdtdec_get_int(blob, node, + priv->disp_info.v_res = fdtdec_get_int(blob, node, "samsung,v-res", 0); - edp_info->disp_info.v_sync_width = fdtdec_get_int(blob, node, + priv->disp_info.v_sync_width = fdtdec_get_int(blob, node, "samsung,v-sync-width", 0); - edp_info->disp_info.v_back_porch = fdtdec_get_int(blob, node, + priv->disp_info.v_back_porch = fdtdec_get_int(blob, node, "samsung,v-back-porch", 0); - edp_info->disp_info.v_front_porch = fdtdec_get_int(blob, node, + priv->disp_info.v_front_porch = fdtdec_get_int(blob, node, "samsung,v-front-porch", 0); - edp_info->disp_info.v_sync_rate = fdtdec_get_int(blob, node, + priv->disp_info.v_sync_rate = fdtdec_get_int(blob, node, "samsung,v-sync-rate", 0); - edp_info->lt_info.lt_status = fdtdec_get_int(blob, node, + priv->lt_info.lt_status = fdtdec_get_int(blob, node, "samsung,lt-status", 0); - edp_info->video_info.master_mode = fdtdec_get_int(blob, node, + priv->video_info.master_mode = fdtdec_get_int(blob, node, "samsung,master-mode", 0); - edp_info->video_info.bist_mode = fdtdec_get_int(blob, node, + priv->video_info.bist_mode = fdtdec_get_int(blob, node, "samsung,bist-mode", 0); - edp_info->video_info.bist_pattern = fdtdec_get_int(blob, node, + priv->video_info.bist_pattern = fdtdec_get_int(blob, node, "samsung,bist-pattern", 0); - edp_info->video_info.h_sync_polarity = fdtdec_get_int(blob, node, + priv->video_info.h_sync_polarity = fdtdec_get_int(blob, node, "samsung,h-sync-polarity", 0); - edp_info->video_info.v_sync_polarity = fdtdec_get_int(blob, node, + priv->video_info.v_sync_polarity = fdtdec_get_int(blob, node, "samsung,v-sync-polarity", 0); - edp_info->video_info.interlaced = fdtdec_get_int(blob, node, + priv->video_info.interlaced = fdtdec_get_int(blob, node, "samsung,interlaced", 0); - edp_info->video_info.color_space = fdtdec_get_int(blob, node, + priv->video_info.color_space = fdtdec_get_int(blob, node, "samsung,color-space", 0); - edp_info->video_info.dynamic_range = fdtdec_get_int(blob, node, + priv->video_info.dynamic_range = fdtdec_get_int(blob, node, "samsung,dynamic-range", 0); - edp_info->video_info.ycbcr_coeff = fdtdec_get_int(blob, node, + priv->video_info.ycbcr_coeff = fdtdec_get_int(blob, node, "samsung,ycbcr-coeff", 0); - edp_info->video_info.color_depth = fdtdec_get_int(blob, node, + priv->video_info.color_depth = fdtdec_get_int(blob, node, "samsung,color-depth", 0); return 0; } @@ -929,17 +929,17 @@ int exynos_dp_parse_dt(const void *blob, struct exynos_dp_priv *edp_info) unsigned int exynos_init_dp(void) { unsigned int ret; - struct exynos_dp_priv *edp_info; - struct exynos_dp *dp_regs; + struct exynos_dp_priv *priv; + struct exynos_dp *regs; int node; - edp_info = kzalloc(sizeof(struct exynos_dp_priv), GFP_KERNEL); - if (!edp_info) { + priv = kzalloc(sizeof(struct exynos_dp_priv), GFP_KERNEL); + if (!priv) { debug("failed to allocate edp device object.\n"); return -EFAULT; } - if (exynos_dp_parse_dt(gd->fdt_blob, edp_info)) + if (exynos_dp_parse_dt(gd->fdt_blob, priv)) debug("unable to parse DP DT node\n"); node = fdtdec_next_compatible(gd->fdt_blob, 0, @@ -947,42 +947,42 @@ unsigned int exynos_init_dp(void) if (node <= 0) debug("exynos_dp: Can't get device node for dp\n"); - dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob, node, + regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); - if (dp_regs == NULL) + if (regs == NULL) debug("Can't get the DP base address\n"); - exynos_dp_disp_info(&edp_info->disp_info); + exynos_dp_disp_info(&priv->disp_info); exynos_dp_phy_ctrl(1); - ret = exynos_dp_init_dp(dp_regs); + ret = exynos_dp_init_dp(regs); if (ret != EXYNOS_DP_SUCCESS) { printf("DP exynos_dp_init_dp() failed\n"); return ret; } - ret = exynos_dp_handle_edid(dp_regs, edp_info); + ret = exynos_dp_handle_edid(regs, priv); if (ret != EXYNOS_DP_SUCCESS) { printf("EDP handle_edid fail\n"); return ret; } - ret = exynos_dp_set_link_train(dp_regs, edp_info); + ret = exynos_dp_set_link_train(regs, priv); if (ret != EXYNOS_DP_SUCCESS) { printf("DP link training fail\n"); return ret; } - exynos_dp_enable_scramble(dp_regs, DP_ENABLE); - exynos_dp_enable_rx_to_enhanced_mode(dp_regs, DP_ENABLE); - exynos_dp_enable_enhanced_mode(dp_regs, DP_ENABLE); + exynos_dp_enable_scramble(regs, DP_ENABLE); + exynos_dp_enable_rx_to_enhanced_mode(regs, DP_ENABLE); + exynos_dp_enable_enhanced_mode(regs, DP_ENABLE); - exynos_dp_set_link_bandwidth(dp_regs, edp_info->lane_bw); - exynos_dp_set_lane_count(dp_regs, edp_info->lane_cnt); + exynos_dp_set_link_bandwidth(regs, priv->lane_bw); + exynos_dp_set_lane_count(regs, priv->lane_cnt); - exynos_dp_init_video(dp_regs); - ret = exynos_dp_config_video(dp_regs, edp_info); + exynos_dp_init_video(regs); + ret = exynos_dp_config_video(regs, priv); if (ret != EXYNOS_DP_SUCCESS) { printf("Exynos DP init failed\n"); return ret; diff --git a/drivers/video/exynos/exynos_dp_lowlevel.c b/drivers/video/exynos/exynos_dp_lowlevel.c index 00a79ea7138..f9784738bb9 100644 --- a/drivers/video/exynos/exynos_dp_lowlevel.c +++ b/drivers/video/exynos/exynos_dp_lowlevel.c @@ -1066,49 +1066,46 @@ void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs, } int exynos_dp_config_video_bist(struct exynos_dp *dp_regs, - struct exynos_dp_priv *edp_info) + struct exynos_dp_priv *priv) { unsigned int reg; unsigned int bist_type = 0; - struct edp_video_info video_info = edp_info->video_info; + struct edp_video_info video_info = priv->video_info; /* For master mode, you don't need to set the video format */ if (video_info.master_mode == 0) { - writel(TOTAL_LINE_CFG_L(edp_info->disp_info.v_total), - &dp_regs->total_ln_cfg_l); - writel(TOTAL_LINE_CFG_H(edp_info->disp_info.v_total), - &dp_regs->total_ln_cfg_h); - writel(ACTIVE_LINE_CFG_L(edp_info->disp_info.v_res), - &dp_regs->active_ln_cfg_l); - writel(ACTIVE_LINE_CFG_H(edp_info->disp_info.v_res), - &dp_regs->active_ln_cfg_h); - writel(edp_info->disp_info.v_sync_width, - &dp_regs->vsw_cfg); - writel(edp_info->disp_info.v_back_porch, - &dp_regs->vbp_cfg); - writel(edp_info->disp_info.v_front_porch, - &dp_regs->vfp_cfg); - - writel(TOTAL_PIXEL_CFG_L(edp_info->disp_info.h_total), - &dp_regs->total_pix_cfg_l); - writel(TOTAL_PIXEL_CFG_H(edp_info->disp_info.h_total), - &dp_regs->total_pix_cfg_h); - writel(ACTIVE_PIXEL_CFG_L(edp_info->disp_info.h_res), - &dp_regs->active_pix_cfg_l); - writel(ACTIVE_PIXEL_CFG_H(edp_info->disp_info.h_res), - &dp_regs->active_pix_cfg_h); - writel(H_F_PORCH_CFG_L(edp_info->disp_info.h_front_porch), - &dp_regs->hfp_cfg_l); - writel(H_F_PORCH_CFG_H(edp_info->disp_info.h_front_porch), - &dp_regs->hfp_cfg_h); - writel(H_SYNC_PORCH_CFG_L(edp_info->disp_info.h_sync_width), - &dp_regs->hsw_cfg_l); - writel(H_SYNC_PORCH_CFG_H(edp_info->disp_info.h_sync_width), - &dp_regs->hsw_cfg_h); - writel(H_B_PORCH_CFG_L(edp_info->disp_info.h_back_porch), - &dp_regs->hbp_cfg_l); - writel(H_B_PORCH_CFG_H(edp_info->disp_info.h_back_porch), - &dp_regs->hbp_cfg_h); + writel(TOTAL_LINE_CFG_L(priv->disp_info.v_total), + &dp_regs->total_ln_cfg_l); + writel(TOTAL_LINE_CFG_H(priv->disp_info.v_total), + &dp_regs->total_ln_cfg_h); + writel(ACTIVE_LINE_CFG_L(priv->disp_info.v_res), + &dp_regs->active_ln_cfg_l); + writel(ACTIVE_LINE_CFG_H(priv->disp_info.v_res), + &dp_regs->active_ln_cfg_h); + writel(priv->disp_info.v_sync_width, &dp_regs->vsw_cfg); + writel(priv->disp_info.v_back_porch, &dp_regs->vbp_cfg); + writel(priv->disp_info.v_front_porch, &dp_regs->vfp_cfg); + + writel(TOTAL_PIXEL_CFG_L(priv->disp_info.h_total), + &dp_regs->total_pix_cfg_l); + writel(TOTAL_PIXEL_CFG_H(priv->disp_info.h_total), + &dp_regs->total_pix_cfg_h); + writel(ACTIVE_PIXEL_CFG_L(priv->disp_info.h_res), + &dp_regs->active_pix_cfg_l); + writel(ACTIVE_PIXEL_CFG_H(priv->disp_info.h_res), + &dp_regs->active_pix_cfg_h); + writel(H_F_PORCH_CFG_L(priv->disp_info.h_front_porch), + &dp_regs->hfp_cfg_l); + writel(H_F_PORCH_CFG_H(priv->disp_info.h_front_porch), + &dp_regs->hfp_cfg_h); + writel(H_SYNC_PORCH_CFG_L(priv->disp_info.h_sync_width), + &dp_regs->hsw_cfg_l); + writel(H_SYNC_PORCH_CFG_H(priv->disp_info.h_sync_width), + &dp_regs->hsw_cfg_h); + writel(H_B_PORCH_CFG_L(priv->disp_info.h_back_porch), + &dp_regs->hbp_cfg_l); + writel(H_B_PORCH_CFG_H(priv->disp_info.h_back_porch), + &dp_regs->hbp_cfg_h); /* * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1], diff --git a/drivers/video/exynos/exynos_dp_lowlevel.h b/drivers/video/exynos/exynos_dp_lowlevel.h index 0a7657ed70d..e4c867eef04 100644 --- a/drivers/video/exynos/exynos_dp_lowlevel.h +++ b/drivers/video/exynos/exynos_dp_lowlevel.h @@ -74,7 +74,7 @@ void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs, void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs, struct edp_video_info *video_info); int exynos_dp_config_video_bist(struct exynos_dp *dp_regs, - struct exynos_dp_priv *edp_info); + struct exynos_dp_priv *priv); unsigned int exynos_dp_is_slave_video_stream_clock_on( struct exynos_dp *dp_regs); void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type, diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c index e13d35af78a..83b1187c989 100644 --- a/drivers/video/exynos/exynos_fb.c +++ b/drivers/video/exynos/exynos_fb.c @@ -35,9 +35,9 @@ struct vidinfo panel_info = { .vl_col = -1, }; -static void exynos_fimd_set_dualrgb(struct vidinfo *pvid, unsigned int enabled) +static void exynos_fimd_set_dualrgb(struct vidinfo *priv, unsigned int enabled) { - struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; + struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; if (enabled) { @@ -45,32 +45,32 @@ static void exynos_fimd_set_dualrgb(struct vidinfo *pvid, unsigned int enabled) EXYNOS_DUALRGB_VDEN_EN_ENABLE; /* in case of Line Split mode, MAIN_CNT doesn't neet to set. */ - cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) | + cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) | EXYNOS_DUALRGB_MAIN_CNT(0); } - writel(cfg, &fimd_ctrl->dualrgb); + writel(cfg, ®->dualrgb); } -static void exynos_fimd_set_dp_clkcon(struct vidinfo *pvid, +static void exynos_fimd_set_dp_clkcon(struct vidinfo *priv, unsigned int enabled) { - struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; + struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; if (enabled) cfg = EXYNOS_DP_CLK_ENABLE; - writel(cfg, &fimd_ctrl->dp_mie_clkcon); + writel(cfg, ®->dp_mie_clkcon); } -static void exynos_fimd_set_par(struct vidinfo *pvid, unsigned int win_id) +static void exynos_fimd_set_par(struct vidinfo *priv, unsigned int win_id) { - struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; + struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; /* set window control */ - cfg = readl((unsigned int)&fimd_ctrl->wincon0 + + cfg = readl((unsigned int)®->wincon0 + EXYNOS_WINCON(win_id)); cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE | @@ -86,7 +86,7 @@ static void exynos_fimd_set_par(struct vidinfo *pvid, unsigned int win_id) /* dma burst is 16 */ cfg |= EXYNOS_WINCON_BURSTLEN_16WORD; - switch (pvid->vl_bpix) { + switch (priv->vl_bpix) { case 4: cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565; break; @@ -95,72 +95,72 @@ static void exynos_fimd_set_par(struct vidinfo *pvid, unsigned int win_id) break; } - writel(cfg, (unsigned int)&fimd_ctrl->wincon0 + + writel(cfg, (unsigned int)®->wincon0 + EXYNOS_WINCON(win_id)); /* set window position to x=0, y=0*/ cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0); - writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a + + writel(cfg, (unsigned int)®->vidosd0a + EXYNOS_VIDOSD(win_id)); - cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) | - EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) | + cfg = EXYNOS_VIDOSD_RIGHT_X(priv->vl_col - 1) | + EXYNOS_VIDOSD_BOTTOM_Y(priv->vl_row - 1) | EXYNOS_VIDOSD_RIGHT_X_E(1) | EXYNOS_VIDOSD_BOTTOM_Y_E(0); - writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b + + writel(cfg, (unsigned int)®->vidosd0b + EXYNOS_VIDOSD(win_id)); /* set window size for window0*/ - cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row); - writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c + + cfg = EXYNOS_VIDOSD_SIZE(priv->vl_col * priv->vl_row); + writel(cfg, (unsigned int)®->vidosd0c + EXYNOS_VIDOSD(win_id)); } -static void exynos_fimd_set_buffer_address(struct vidinfo *pvid, +static void exynos_fimd_set_buffer_address(struct vidinfo *priv, unsigned int win_id, ulong lcd_base_addr) { - struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; + struct exynos_fb *reg = priv->reg; unsigned long start_addr, end_addr; start_addr = lcd_base_addr; - end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) * - pvid->vl_row); + end_addr = start_addr + ((priv->vl_col * (NBITS(priv->vl_bpix) / 8)) * + priv->vl_row); - writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 + + writel(start_addr, (unsigned int)®->vidw00add0b0 + EXYNOS_BUFFER_OFFSET(win_id)); - writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 + + writel(end_addr, (unsigned int)®->vidw00add1b0 + EXYNOS_BUFFER_OFFSET(win_id)); } -static void exynos_fimd_set_clock(struct vidinfo *pvid) +static void exynos_fimd_set_clock(struct vidinfo *priv) { - struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; + struct exynos_fb *reg = priv->reg; unsigned int cfg = 0, div = 0, remainder, remainder_div; unsigned long pixel_clock; unsigned long long src_clock; - if (pvid->dual_lcd_enabled) { - pixel_clock = pvid->vl_freq * - (pvid->vl_hspw + pvid->vl_hfpd + - pvid->vl_hbpd + pvid->vl_col / 2) * - (pvid->vl_vspw + pvid->vl_vfpd + - pvid->vl_vbpd + pvid->vl_row); - } else if (pvid->interface_mode == FIMD_CPU_INTERFACE) { - pixel_clock = pvid->vl_freq * - pvid->vl_width * pvid->vl_height * - (pvid->cs_setup + pvid->wr_setup + - pvid->wr_act + pvid->wr_hold + 1); + if (priv->dual_lcd_enabled) { + pixel_clock = priv->vl_freq * + (priv->vl_hspw + priv->vl_hfpd + + priv->vl_hbpd + priv->vl_col / 2) * + (priv->vl_vspw + priv->vl_vfpd + + priv->vl_vbpd + priv->vl_row); + } else if (priv->interface_mode == FIMD_CPU_INTERFACE) { + pixel_clock = priv->vl_freq * + priv->vl_width * priv->vl_height * + (priv->cs_setup + priv->wr_setup + + priv->wr_act + priv->wr_hold + 1); } else { - pixel_clock = pvid->vl_freq * - (pvid->vl_hspw + pvid->vl_hfpd + - pvid->vl_hbpd + pvid->vl_col) * - (pvid->vl_vspw + pvid->vl_vfpd + - pvid->vl_vbpd + pvid->vl_row); + pixel_clock = priv->vl_freq * + (priv->vl_hspw + priv->vl_hfpd + + priv->vl_hbpd + priv->vl_col) * + (priv->vl_vspw + priv->vl_vfpd + + priv->vl_vbpd + priv->vl_row); } - cfg = readl(&fimd_ctrl->vidcon0); + cfg = readl(®->vidcon0); cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK | EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK | EXYNOS_VIDCON0_CLKDIR_MASK); @@ -181,32 +181,32 @@ static void exynos_fimd_set_clock(struct vidinfo *pvid) div++; /* in case of dual lcd mode. */ - if (pvid->dual_lcd_enabled) + if (priv->dual_lcd_enabled) div--; cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1); - writel(cfg, &fimd_ctrl->vidcon0); + writel(cfg, ®->vidcon0); } -void exynos_set_trigger(struct vidinfo *pvid) +void exynos_set_trigger(struct vidinfo *priv) { - struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; + struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; - cfg = readl(&fimd_ctrl->trigcon); + cfg = readl(®->trigcon); cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG); - writel(cfg, &fimd_ctrl->trigcon); + writel(cfg, ®->trigcon); } -int exynos_is_i80_frame_done(struct vidinfo *pvid) +int exynos_is_i80_frame_done(struct vidinfo *priv) { - struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; + struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; int status; - cfg = readl(&fimd_ctrl->trigcon); + cfg = readl(®->trigcon); /* frame done func is valid only when TRIMODE[0] is set to 1. */ status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) == @@ -215,58 +215,58 @@ int exynos_is_i80_frame_done(struct vidinfo *pvid) return status; } -static void exynos_fimd_lcd_on(struct vidinfo *pvid) +static void exynos_fimd_lcd_on(struct vidinfo *priv) { - struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; + struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; /* display on */ - cfg = readl(&fimd_ctrl->vidcon0); + cfg = readl(®->vidcon0); cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE); - writel(cfg, &fimd_ctrl->vidcon0); + writel(cfg, ®->vidcon0); } -static void exynos_fimd_window_on(struct vidinfo *pvid, unsigned int win_id) +static void exynos_fimd_window_on(struct vidinfo *priv, unsigned int win_id) { - struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; + struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; /* enable window */ - cfg = readl((unsigned int)&fimd_ctrl->wincon0 + + cfg = readl((unsigned int)®->wincon0 + EXYNOS_WINCON(win_id)); cfg |= EXYNOS_WINCON_ENWIN_ENABLE; - writel(cfg, (unsigned int)&fimd_ctrl->wincon0 + + writel(cfg, (unsigned int)®->wincon0 + EXYNOS_WINCON(win_id)); - cfg = readl(&fimd_ctrl->winshmap); + cfg = readl(®->winshmap); cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id); - writel(cfg, &fimd_ctrl->winshmap); + writel(cfg, ®->winshmap); } -void exynos_fimd_lcd_off(struct vidinfo *pvid) +void exynos_fimd_lcd_off(struct vidinfo *priv) { - struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; + struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; - cfg = readl(&fimd_ctrl->vidcon0); + cfg = readl(®->vidcon0); cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE); - writel(cfg, &fimd_ctrl->vidcon0); + writel(cfg, ®->vidcon0); } -void exynos_fimd_window_off(struct vidinfo *pvid, unsigned int win_id) +void exynos_fimd_window_off(struct vidinfo *priv, unsigned int win_id) { - struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; + struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; - cfg = readl((unsigned int)&fimd_ctrl->wincon0 + + cfg = readl((unsigned int)®->wincon0 + EXYNOS_WINCON(win_id)); cfg &= EXYNOS_WINCON_ENWIN_DISABLE; - writel(cfg, (unsigned int)&fimd_ctrl->wincon0 + + writel(cfg, (unsigned int)®->wincon0 + EXYNOS_WINCON(win_id)); - cfg = readl(&fimd_ctrl->winshmap); + cfg = readl(®->winshmap); cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id); - writel(cfg, &fimd_ctrl->winshmap); + writel(cfg, ®->winshmap); } /* @@ -307,9 +307,9 @@ void exynos_fimd_disable_sysmmu(void) } } -void exynos_fimd_lcd_init(struct vidinfo *pvid, ulong lcd_base_address) +void exynos_fimd_lcd_init(struct vidinfo *priv, ulong lcd_base_address) { - struct exynos_fb *fimd_ctrl; + struct exynos_fb *reg; unsigned int cfg = 0, rgb_mode; unsigned int offset; unsigned int node; @@ -319,105 +319,105 @@ void exynos_fimd_lcd_init(struct vidinfo *pvid, ulong lcd_base_address) if (node <= 0) debug("exynos_fb: Can't get device node for fimd\n"); - fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, node, + reg = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); - if (fimd_ctrl == NULL) + if (reg == NULL) debug("Can't get the FIMD base address\n"); - pvid->fimd_ctrl = fimd_ctrl; + priv->reg = reg; if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu")) exynos_fimd_disable_sysmmu(); offset = exynos_fimd_get_base_offset(); - rgb_mode = pvid->rgb_mode; + rgb_mode = priv->rgb_mode; - if (pvid->interface_mode == FIMD_RGB_INTERFACE) { + if (priv->interface_mode == FIMD_RGB_INTERFACE) { cfg |= EXYNOS_VIDCON0_VIDOUT_RGB; - writel(cfg, &fimd_ctrl->vidcon0); + writel(cfg, ®->vidcon0); - cfg = readl(&fimd_ctrl->vidcon2); + cfg = readl(®->vidcon2); cfg &= ~(EXYNOS_VIDCON2_WB_MASK | EXYNOS_VIDCON2_TVFORMATSEL_MASK | EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK); cfg |= EXYNOS_VIDCON2_WB_DISABLE; - writel(cfg, &fimd_ctrl->vidcon2); + writel(cfg, ®->vidcon2); /* set polarity */ cfg = 0; - if (!pvid->vl_clkp) + if (!priv->vl_clkp) cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE; - if (!pvid->vl_hsp) + if (!priv->vl_hsp) cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT; - if (!pvid->vl_vsp) + if (!priv->vl_vsp) cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT; - if (!pvid->vl_dp) + if (!priv->vl_dp) cfg |= EXYNOS_VIDCON1_IVDEN_INVERT; - writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset); + writel(cfg, (unsigned int)®->vidcon1 + offset); /* set timing */ - cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1); - cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1); - cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1); - writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset); + cfg = EXYNOS_VIDTCON0_VFPD(priv->vl_vfpd - 1); + cfg |= EXYNOS_VIDTCON0_VBPD(priv->vl_vbpd - 1); + cfg |= EXYNOS_VIDTCON0_VSPW(priv->vl_vspw - 1); + writel(cfg, (unsigned int)®->vidtcon0 + offset); - cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1); - cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1); - cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1); + cfg = EXYNOS_VIDTCON1_HFPD(priv->vl_hfpd - 1); + cfg |= EXYNOS_VIDTCON1_HBPD(priv->vl_hbpd - 1); + cfg |= EXYNOS_VIDTCON1_HSPW(priv->vl_hspw - 1); - writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset); + writel(cfg, (unsigned int)®->vidtcon1 + offset); /* set lcd size */ - cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) | - EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) | - EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) | - EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1); + cfg = EXYNOS_VIDTCON2_HOZVAL(priv->vl_col - 1) | + EXYNOS_VIDTCON2_LINEVAL(priv->vl_row - 1) | + EXYNOS_VIDTCON2_HOZVAL_E(priv->vl_col - 1) | + EXYNOS_VIDTCON2_LINEVAL_E(priv->vl_row - 1); - writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset); + writel(cfg, (unsigned int)®->vidtcon2 + offset); } /* set display mode */ - cfg = readl(&fimd_ctrl->vidcon0); + cfg = readl(®->vidcon0); cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK; cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT); - writel(cfg, &fimd_ctrl->vidcon0); + writel(cfg, ®->vidcon0); /* set par */ - exynos_fimd_set_par(pvid, pvid->win_id); + exynos_fimd_set_par(priv, priv->win_id); /* set memory address */ - exynos_fimd_set_buffer_address(pvid, pvid->win_id, lcd_base_address); + exynos_fimd_set_buffer_address(priv, priv->win_id, lcd_base_address); /* set buffer size */ - cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * - NBITS(pvid->vl_bpix) / 8) | - EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col * - NBITS(pvid->vl_bpix) / 8) | + cfg = EXYNOS_VIDADDR_PAGEWIDTH(priv->vl_col * + NBITS(priv->vl_bpix) / 8) | + EXYNOS_VIDADDR_PAGEWIDTH_E(priv->vl_col * + NBITS(priv->vl_bpix) / 8) | EXYNOS_VIDADDR_OFFSIZE(0) | EXYNOS_VIDADDR_OFFSIZE_E(0); - writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 + - EXYNOS_BUFFER_SIZE(pvid->win_id)); + writel(cfg, (unsigned int)®->vidw00add2 + + EXYNOS_BUFFER_SIZE(priv->win_id)); /* set clock */ - exynos_fimd_set_clock(pvid); + exynos_fimd_set_clock(priv); /* set rgb mode to dual lcd. */ - exynos_fimd_set_dualrgb(pvid, pvid->dual_lcd_enabled); + exynos_fimd_set_dualrgb(priv, priv->dual_lcd_enabled); /* display on */ - exynos_fimd_lcd_on(pvid); + exynos_fimd_lcd_on(priv); /* window on */ - exynos_fimd_window_on(pvid, pvid->win_id); + exynos_fimd_window_on(priv, priv->win_id); - exynos_fimd_set_dp_clkcon(pvid, pvid->dp_enabled); + exynos_fimd_set_dp_clkcon(priv, priv->dp_enabled); } -unsigned long exynos_fimd_calc_fbsize(struct vidinfo *pvid) +unsigned long exynos_fimd_calc_fbsize(struct vidinfo *priv) { - return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8); + return priv->vl_col * priv->vl_row * (NBITS(priv->vl_bpix) / 8); } ushort *configuration_get_cmap(void) diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h index 0aa0fc71a3b..ab92ffb72ad 100644 --- a/include/exynos_lcd.h +++ b/include/exynos_lcd.h @@ -75,7 +75,7 @@ typedef struct vidinfo { unsigned int sclk_div; unsigned int dual_lcd_enabled; - struct exynos_fb *fimd_ctrl; + struct exynos_fb *reg; struct exynos_platform_mipi_dsim *dsim_platform_data_dt; } vidinfo_t; -- cgit v1.3.1 From bb5930d5c97fa22ed2fe048106fcabb5b7c77c96 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 21 Feb 2016 21:09:01 -0700 Subject: exynos: video: Convert several boards to driver model for video Update several boards to use driver model for video. This involves changes to the EDP and FIMD (frame buffer) drivers. Existing PWM, simple-panel and pwm-backlight drivers are used. These work without additional configuration since they use the device tree settings in the same way as Linux. Boards converted are: - snow - spring - peach-pit - peach-pi All have been tested. Not converted: - MIPI display driver - s5pc210_universal - smdk5420 - smdk5250 - trats - trats2 Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin Signed-off-by: Minkyu Kang --- arch/arm/mach-exynos/include/mach/dp_info.h | 1 + board/samsung/common/board.c | 15 - configs/peach-pi_defconfig | 4 + configs/peach-pit_defconfig | 4 + configs/snow_defconfig | 4 + configs/spring_defconfig | 4 + drivers/video/exynos/exynos_dp.c | 146 ++++++++-- drivers/video/exynos/exynos_fb.c | 407 ++++++++++++++++------------ drivers/video/simple_panel.c | 2 + include/configs/exynos5-common.h | 1 - include/configs/exynos5-dt-common.h | 5 +- 11 files changed, 377 insertions(+), 216 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-exynos/include/mach/dp_info.h b/arch/arm/mach-exynos/include/mach/dp_info.h index 8ce33d64d7f..1079e1ef1e0 100644 --- a/arch/arm/mach-exynos/include/mach/dp_info.h +++ b/arch/arm/mach-exynos/include/mach/dp_info.h @@ -72,6 +72,7 @@ struct exynos_dp_priv { unsigned char dpcd_rev; /*support enhanced frame cap */ unsigned char dpcd_efc; + struct exynos_dp *regs; }; enum analog_power_block { diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 799517428db..0eb066ce478 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -158,21 +158,6 @@ int board_early_init_f(void) board_i2c_init(gd->fdt_blob); #endif -#if defined(CONFIG_EXYNOS_FB) - /* - * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs - * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, - * to reserve frame-buffer memory at a very early stage. So, we need - * to fill panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix - * before lcd_setmem() is called. - */ - err = exynos_lcd_early_init(gd->fdt_blob); - if (err) { - debug("LCD early init failed\n"); - return err; - } -#endif - return exynos_early_init_f(); } #endif diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index ce07052992c..fea8bde3244 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -47,6 +47,8 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_TPS65090=y CONFIG_DM_REGULATOR=y CONFIG_REGULATOR_TPS65090=y +CONFIG_DM_PWM=y +CONFIG_PWM_EXYNOS=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y @@ -56,6 +58,8 @@ CONFIG_EXYNOS_SPI=y CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_TPM=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index 4479fe8c228..41c3d1208de 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -47,6 +47,8 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_TPS65090=y CONFIG_DM_REGULATOR=y CONFIG_REGULATOR_TPS65090=y +CONFIG_DM_PWM=y +CONFIG_PWM_EXYNOS=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y @@ -56,6 +58,8 @@ CONFIG_EXYNOS_SPI=y CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_TPM=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index 77b97a32923..c16c90c4533 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -52,6 +52,8 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_MAX77686=y CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y +CONFIG_DM_PWM=y +CONFIG_PWM_EXYNOS=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_S5P=y CONFIG_DEBUG_UART_BASE=0x12c30000 @@ -65,6 +67,8 @@ CONFIG_EXYNOS_SPI=y CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_VIDEO_BRIDGE_NXP_PTN3460=y diff --git a/configs/spring_defconfig b/configs/spring_defconfig index d3b174a5482..b68cab05432 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -52,6 +52,8 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_MAX77686=y CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y +CONFIG_DM_PWM=y +CONFIG_PWM_EXYNOS=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_S5P=y CONFIG_DEBUG_UART_BASE=0x12c30000 @@ -65,6 +67,8 @@ CONFIG_EXYNOS_SPI=y CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_TPM=y diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c index d7bccc3708f..fc39f2c5620 100644 --- a/drivers/video/exynos/exynos_dp.c +++ b/drivers/video/exynos/exynos_dp.c @@ -7,17 +7,21 @@ */ #include +#include #include +#include +#include +#include #include +#include #include #include #include #include #include #include +#include #include -#include -#include #include "exynos_dp_lowlevel.h" @@ -872,15 +876,19 @@ static unsigned int exynos_dp_config_video(struct exynos_dp *regs, return ret; } -int exynos_dp_parse_dt(const void *blob, struct exynos_dp_priv *priv) +static int exynos_dp_ofdata_to_platdata(struct udevice *dev) { - unsigned int node = fdtdec_next_compatible(blob, 0, - COMPAT_SAMSUNG_EXYNOS5_DP); - if (node <= 0) { - debug("exynos_dp: Can't get device node for dp\n"); - return -ENODEV; - } + struct exynos_dp_priv *priv = dev_get_priv(dev); + const void *blob = gd->fdt_blob; + unsigned int node = dev->of_offset; + fdt_addr_t addr; + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) { + debug("Can't get the DP base address\n"); + return -EINVAL; + } + priv->regs = (struct exynos_dp *)addr; priv->disp_info.h_res = fdtdec_get_int(blob, node, "samsung,h-res", 0); priv->disp_info.h_sync_width = fdtdec_get_int(blob, node, @@ -926,34 +934,97 @@ int exynos_dp_parse_dt(const void *blob, struct exynos_dp_priv *priv) return 0; } -unsigned int exynos_init_dp(void) +static int exynos_dp_bridge_init(struct udevice *dev) { - unsigned int ret; - struct exynos_dp_priv *priv; - struct exynos_dp *regs; - int node; + const int max_tries = 10; + int num_tries; + int ret; - priv = kzalloc(sizeof(struct exynos_dp_priv), GFP_KERNEL); - if (!priv) { - debug("failed to allocate edp device object.\n"); - return -EFAULT; + debug("%s\n", __func__); + ret = video_bridge_attach(dev); + if (ret) { + debug("video bridge init failed: %d\n", ret); + return ret; } - if (exynos_dp_parse_dt(gd->fdt_blob, priv)) - debug("unable to parse DP DT node\n"); + /* + * We need to wait for 90ms after bringing up the bridge since there + * is a phantom "high" on the HPD chip during its bootup. The phantom + * high comes within 7ms of de-asserting PD and persists for at least + * 15ms. The real high comes roughly 50ms after PD is de-asserted. The + * phantom high makes it hard for us to know when the NXP chip is up. + */ + mdelay(90); - node = fdtdec_next_compatible(gd->fdt_blob, 0, - COMPAT_SAMSUNG_EXYNOS5_DP); - if (node <= 0) - debug("exynos_dp: Can't get device node for dp\n"); + for (num_tries = 0; num_tries < max_tries; num_tries++) { + /* Check HPD. If it's high, or we don't have it, all is well */ + ret = video_bridge_check_attached(dev); + if (!ret || ret == -ENOENT) + return 0; - regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob, node, - "reg"); - if (regs == NULL) - debug("Can't get the DP base address\n"); + debug("%s: eDP bridge failed to come up; try %d of %d\n", + __func__, num_tries, max_tries); + } + + /* Immediately go into bridge reset if the hp line is not high */ + return -EIO; +} + +static int exynos_dp_bridge_setup(const void *blob) +{ + const int max_tries = 2; + int num_tries; + struct udevice *dev; + int ret; + + /* Configure I2C registers for Parade bridge */ + ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev); + if (ret) { + debug("video bridge init failed: %d\n", ret); + return ret; + } + + if (strncmp(dev->driver->name, "parade", 6)) { + /* Mux HPHPD to the special hotplug detect mode */ + exynos_pinmux_config(PERIPH_ID_DPHPD, 0); + } + + for (num_tries = 0; num_tries < max_tries; num_tries++) { + ret = exynos_dp_bridge_init(dev); + if (!ret) + return 0; + if (num_tries == max_tries - 1) + break; + + /* + * If we're here, the bridge chip failed to initialise. + * Power down the bridge in an attempt to reset. + */ + video_bridge_set_active(dev, false); + + /* + * Arbitrarily wait 300ms here with DP_N low. Don't know for + * sure how long we should wait, but we're being paranoid. + */ + mdelay(300); + } + return ret; +} +int exynos_dp_enable(struct udevice *dev, int panel_bpp, + const struct display_timing *timing) +{ + struct exynos_dp_priv *priv = dev_get_priv(dev); + struct exynos_dp *regs = priv->regs; + unsigned int ret; + + debug("%s: start\n", __func__); exynos_dp_disp_info(&priv->disp_info); + ret = exynos_dp_bridge_setup(gd->fdt_blob); + if (ret && ret != -ENODEV) + printf("LCD bridge failed to enable: %d\n", ret); + exynos_dp_phy_ctrl(1); ret = exynos_dp_init_dp(regs); @@ -992,3 +1063,22 @@ unsigned int exynos_init_dp(void) return ret; } + + +static const struct dm_display_ops exynos_dp_ops = { + .enable = exynos_dp_enable, +}; + +static const struct udevice_id exynos_dp_ids[] = { + { .compatible = "samsung,exynos5-dp" }, + { } +}; + +U_BOOT_DRIVER(exynos_dp) = { + .name = "eexynos_dp", + .id = UCLASS_DISPLAY, + .of_match = exynos_dp_ids, + .ops = &exynos_dp_ops, + .ofdata_to_platdata = exynos_dp_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct exynos_dp_priv), +}; diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c index 83b1187c989..c8fef63937f 100644 --- a/drivers/video/exynos/exynos_fb.c +++ b/drivers/video/exynos/exynos_fb.c @@ -9,33 +9,98 @@ #include #include +#include #include -#include +#include #include #include +#include +#include +#include #include #include #include #include #include #include +#include +#include #include #include #include -#include "exynos_fb.h" - DECLARE_GLOBAL_DATA_PTR; -struct vidinfo panel_info = { - /* - * Insert a value here so that we don't end up in the BSS - * Reference: drivers/video/tegra.c - */ - .vl_col = -1, +enum { + FIMD_RGB_INTERFACE = 1, + FIMD_CPU_INTERFACE = 2, +}; + +enum exynos_fb_rgb_mode_t { + MODE_RGB_P = 0, + MODE_BGR_P = 1, + MODE_RGB_S = 2, + MODE_BGR_S = 3, }; -static void exynos_fimd_set_dualrgb(struct vidinfo *priv, unsigned int enabled) +struct exynos_fb_priv { + ushort vl_col; /* Number of columns (i.e. 640) */ + ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ + ushort vl_width; /* Width of display area in millimeters */ + ushort vl_height; /* Height of display area in millimeters */ + + /* LCD configuration register */ + u_char vl_freq; /* Frequency */ + u_char vl_clkp; /* Clock polarity */ + u_char vl_oep; /* Output Enable polarity */ + u_char vl_hsp; /* Horizontal Sync polarity */ + u_char vl_vsp; /* Vertical Sync polarity */ + u_char vl_dp; /* Data polarity */ + u_char vl_bpix; /* Bits per pixel */ + + /* Horizontal control register. Timing from data sheet */ + u_char vl_hspw; /* Horz sync pulse width */ + u_char vl_hfpd; /* Wait before of line */ + u_char vl_hbpd; /* Wait end of line */ + + /* Vertical control register. */ + u_char vl_vspw; /* Vertical sync pulse width */ + u_char vl_vfpd; /* Wait before of frame */ + u_char vl_vbpd; /* Wait end of frame */ + u_char vl_cmd_allow_len; /* Wait end of frame */ + + unsigned int win_id; + unsigned int init_delay; + unsigned int power_on_delay; + unsigned int reset_delay; + unsigned int interface_mode; + unsigned int mipi_enabled; + unsigned int dp_enabled; + unsigned int cs_setup; + unsigned int wr_setup; + unsigned int wr_act; + unsigned int wr_hold; + unsigned int logo_on; + unsigned int logo_width; + unsigned int logo_height; + int logo_x_offset; + int logo_y_offset; + unsigned long logo_addr; + unsigned int rgb_mode; + unsigned int resolution; + + /* parent clock name(MPLL, EPLL or VPLL) */ + unsigned int pclk_name; + /* ratio value for source clock from parent clock. */ + unsigned int sclk_div; + + unsigned int dual_lcd_enabled; + struct exynos_fb *reg; + struct exynos_platform_mipi_dsim *dsim_platform_data_dt; +}; + +static void exynos_fimd_set_dualrgb(struct exynos_fb_priv *priv, bool enabled) { struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; @@ -52,7 +117,7 @@ static void exynos_fimd_set_dualrgb(struct vidinfo *priv, unsigned int enabled) writel(cfg, ®->dualrgb); } -static void exynos_fimd_set_dp_clkcon(struct vidinfo *priv, +static void exynos_fimd_set_dp_clkcon(struct exynos_fb_priv *priv, unsigned int enabled) { struct exynos_fb *reg = priv->reg; @@ -64,7 +129,8 @@ static void exynos_fimd_set_dp_clkcon(struct vidinfo *priv, writel(cfg, ®->dp_mie_clkcon); } -static void exynos_fimd_set_par(struct vidinfo *priv, unsigned int win_id) +static void exynos_fimd_set_par(struct exynos_fb_priv *priv, + unsigned int win_id) { struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; @@ -117,7 +183,7 @@ static void exynos_fimd_set_par(struct vidinfo *priv, unsigned int win_id) EXYNOS_VIDOSD(win_id)); } -static void exynos_fimd_set_buffer_address(struct vidinfo *priv, +static void exynos_fimd_set_buffer_address(struct exynos_fb_priv *priv, unsigned int win_id, ulong lcd_base_addr) { @@ -125,7 +191,7 @@ static void exynos_fimd_set_buffer_address(struct vidinfo *priv, unsigned long start_addr, end_addr; start_addr = lcd_base_addr; - end_addr = start_addr + ((priv->vl_col * (NBITS(priv->vl_bpix) / 8)) * + end_addr = start_addr + ((priv->vl_col * (VNBITS(priv->vl_bpix) / 8)) * priv->vl_row); writel(start_addr, (unsigned int)®->vidw00add0b0 + @@ -134,7 +200,7 @@ static void exynos_fimd_set_buffer_address(struct vidinfo *priv, EXYNOS_BUFFER_OFFSET(win_id)); } -static void exynos_fimd_set_clock(struct vidinfo *priv) +static void exynos_fimd_set_clock(struct exynos_fb_priv *priv) { struct exynos_fb *reg = priv->reg; unsigned int cfg = 0, div = 0, remainder, remainder_div; @@ -188,7 +254,7 @@ static void exynos_fimd_set_clock(struct vidinfo *priv) writel(cfg, ®->vidcon0); } -void exynos_set_trigger(struct vidinfo *priv) +void exynos_set_trigger(struct exynos_fb_priv *priv) { struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; @@ -200,7 +266,7 @@ void exynos_set_trigger(struct vidinfo *priv) writel(cfg, ®->trigcon); } -int exynos_is_i80_frame_done(struct vidinfo *priv) +int exynos_is_i80_frame_done(struct exynos_fb_priv *priv) { struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; @@ -215,7 +281,7 @@ int exynos_is_i80_frame_done(struct vidinfo *priv) return status; } -static void exynos_fimd_lcd_on(struct vidinfo *priv) +static void exynos_fimd_lcd_on(struct exynos_fb_priv *priv) { struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; @@ -226,7 +292,8 @@ static void exynos_fimd_lcd_on(struct vidinfo *priv) writel(cfg, ®->vidcon0); } -static void exynos_fimd_window_on(struct vidinfo *priv, unsigned int win_id) +static void exynos_fimd_window_on(struct exynos_fb_priv *priv, + unsigned int win_id) { struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; @@ -243,7 +310,7 @@ static void exynos_fimd_window_on(struct vidinfo *priv, unsigned int win_id) writel(cfg, ®->winshmap); } -void exynos_fimd_lcd_off(struct vidinfo *priv) +void exynos_fimd_lcd_off(struct exynos_fb_priv *priv) { struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; @@ -253,7 +320,7 @@ void exynos_fimd_lcd_off(struct vidinfo *priv) writel(cfg, ®->vidcon0); } -void exynos_fimd_window_off(struct vidinfo *priv, unsigned int win_id) +void exynos_fimd_window_off(struct exynos_fb_priv *priv, unsigned int win_id) { struct exynos_fb *reg = priv->reg; unsigned int cfg = 0; @@ -307,24 +374,16 @@ void exynos_fimd_disable_sysmmu(void) } } -void exynos_fimd_lcd_init(struct vidinfo *priv, ulong lcd_base_address) +void exynos_fimd_lcd_init(struct udevice *dev) { - struct exynos_fb *reg; + struct exynos_fb_priv *priv = dev_get_priv(dev); + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct exynos_fb *reg = priv->reg; unsigned int cfg = 0, rgb_mode; unsigned int offset; unsigned int node; - node = fdtdec_next_compatible(gd->fdt_blob, - 0, COMPAT_SAMSUNG_EXYNOS_FIMD); - if (node <= 0) - debug("exynos_fb: Can't get device node for fimd\n"); - - reg = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, node, - "reg"); - if (reg == NULL) - debug("Can't get the FIMD base address\n"); - priv->reg = reg; - + node = dev->of_offset; if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu")) exynos_fimd_disable_sysmmu(); @@ -387,13 +446,13 @@ void exynos_fimd_lcd_init(struct vidinfo *priv, ulong lcd_base_address) exynos_fimd_set_par(priv, priv->win_id); /* set memory address */ - exynos_fimd_set_buffer_address(priv, priv->win_id, lcd_base_address); + exynos_fimd_set_buffer_address(priv, priv->win_id, plat->base); /* set buffer size */ cfg = EXYNOS_VIDADDR_PAGEWIDTH(priv->vl_col * - NBITS(priv->vl_bpix) / 8) | + VNBITS(priv->vl_bpix) / 8) | EXYNOS_VIDADDR_PAGEWIDTH_E(priv->vl_col * - NBITS(priv->vl_bpix) / 8) | + VNBITS(priv->vl_bpix) / 8) | EXYNOS_VIDADDR_OFFSIZE(0) | EXYNOS_VIDADDR_OFFSIZE_E(0); @@ -415,26 +474,9 @@ void exynos_fimd_lcd_init(struct vidinfo *priv, ulong lcd_base_address) exynos_fimd_set_dp_clkcon(priv, priv->dp_enabled); } -unsigned long exynos_fimd_calc_fbsize(struct vidinfo *priv) -{ - return priv->vl_col * priv->vl_row * (NBITS(priv->vl_bpix) / 8); -} - -ushort *configuration_get_cmap(void) -{ -#if defined(CONFIG_LCD_LOGO) - return bmp_logo_palette; -#else - return NULL; -#endif -} - -static void exynos_lcd_init(struct vidinfo *vid, ulong lcd_base) +unsigned long exynos_fimd_calc_fbsize(struct exynos_fb_priv *priv) { - exynos_fimd_lcd_init(vid, lcd_base); - - /* Enable flushing after LCD writes if requested */ - lcd_set_flush_dcache(1); + return priv->vl_col * priv->vl_row * (VNBITS(priv->vl_bpix) / 8); } __weak void exynos_cfg_lcd_gpio(void) @@ -470,217 +512,242 @@ __weak int exynos_lcd_misc_init(struct vidinfo *vid) return 0; } -static void lcd_panel_on(struct vidinfo *vid) +int exynos_fb_ofdata_to_platdata(struct udevice *dev) { - struct gpio_desc pwm_out_gpio; - struct gpio_desc bl_en_gpio; - unsigned int node; - - udelay(vid->init_delay); - - exynos_backlight_reset(); - - exynos_cfg_lcd_gpio(); - - exynos_lcd_power_on(); - - udelay(vid->power_on_delay); - - if (vid->dp_enabled) - exynos_init_dp(); - - exynos_reset_lcd(); - - udelay(vid->reset_delay); - - exynos_backlight_on(1); - - node = fdtdec_next_compatible(gd->fdt_blob, 0, - COMPAT_SAMSUNG_EXYNOS_FIMD); - if (node <= 0) { - debug("FIMD: Can't get device node for FIMD\n"); - return; - } - gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio", - 0, &pwm_out_gpio, - GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); - - gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0, - &bl_en_gpio, - GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); - - exynos_cfg_ldo(); + struct exynos_fb_priv *priv = dev_get_priv(dev); + unsigned int node = dev->of_offset; + const void *blob = gd->fdt_blob; + fdt_addr_t addr; - exynos_enable_ldo(1); - - if (vid->mipi_enabled) - exynos_mipi_dsi_init(panel_info.dsim_platform_data_dt); -} - -int exynos_lcd_early_init(const void *blob) -{ - unsigned int node; - node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD); - if (node <= 0) { - debug("exynos_fb: Can't get device node for fimd\n"); - return -ENODEV; + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) { + debug("Can't get the FIMD base address\n"); + return -EINVAL; } + priv->reg = (struct exynos_fb *)addr; - panel_info.vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0); - if (panel_info.vl_col == 0) { + priv->vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0); + if (priv->vl_col == 0) { debug("Can't get XRES\n"); return -ENXIO; } - panel_info.vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0); - if (panel_info.vl_row == 0) { + priv->vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0); + if (priv->vl_row == 0) { debug("Can't get YRES\n"); return -ENXIO; } - panel_info.vl_width = fdtdec_get_int(blob, node, + priv->vl_width = fdtdec_get_int(blob, node, "samsung,vl-width", 0); - panel_info.vl_height = fdtdec_get_int(blob, node, + priv->vl_height = fdtdec_get_int(blob, node, "samsung,vl-height", 0); - panel_info.vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0); - if (panel_info.vl_freq == 0) { + priv->vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0); + if (priv->vl_freq == 0) { debug("Can't get refresh rate\n"); return -ENXIO; } if (fdtdec_get_bool(blob, node, "samsung,vl-clkp")) - panel_info.vl_clkp = CONFIG_SYS_LOW; + priv->vl_clkp = VIDEO_ACTIVE_LOW; if (fdtdec_get_bool(blob, node, "samsung,vl-oep")) - panel_info.vl_oep = CONFIG_SYS_LOW; + priv->vl_oep = VIDEO_ACTIVE_LOW; if (fdtdec_get_bool(blob, node, "samsung,vl-hsp")) - panel_info.vl_hsp = CONFIG_SYS_LOW; + priv->vl_hsp = VIDEO_ACTIVE_LOW; if (fdtdec_get_bool(blob, node, "samsung,vl-vsp")) - panel_info.vl_vsp = CONFIG_SYS_LOW; + priv->vl_vsp = VIDEO_ACTIVE_LOW; if (fdtdec_get_bool(blob, node, "samsung,vl-dp")) - panel_info.vl_dp = CONFIG_SYS_LOW; + priv->vl_dp = VIDEO_ACTIVE_LOW; - panel_info.vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0); - if (panel_info.vl_bpix == 0) { + priv->vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0); + if (priv->vl_bpix == 0) { debug("Can't get bits per pixel\n"); return -ENXIO; } - panel_info.vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0); - if (panel_info.vl_hspw == 0) { + priv->vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0); + if (priv->vl_hspw == 0) { debug("Can't get hsync width\n"); return -ENXIO; } - panel_info.vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0); - if (panel_info.vl_hfpd == 0) { + priv->vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0); + if (priv->vl_hfpd == 0) { debug("Can't get right margin\n"); return -ENXIO; } - panel_info.vl_hbpd = (u_char)fdtdec_get_int(blob, node, + priv->vl_hbpd = (u_char)fdtdec_get_int(blob, node, "samsung,vl-hbpd", 0); - if (panel_info.vl_hbpd == 0) { + if (priv->vl_hbpd == 0) { debug("Can't get left margin\n"); return -ENXIO; } - panel_info.vl_vspw = (u_char)fdtdec_get_int(blob, node, + priv->vl_vspw = (u_char)fdtdec_get_int(blob, node, "samsung,vl-vspw", 0); - if (panel_info.vl_vspw == 0) { + if (priv->vl_vspw == 0) { debug("Can't get vsync width\n"); return -ENXIO; } - panel_info.vl_vfpd = fdtdec_get_int(blob, node, + priv->vl_vfpd = fdtdec_get_int(blob, node, "samsung,vl-vfpd", 0); - if (panel_info.vl_vfpd == 0) { + if (priv->vl_vfpd == 0) { debug("Can't get lower margin\n"); return -ENXIO; } - panel_info.vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0); - if (panel_info.vl_vbpd == 0) { + priv->vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0); + if (priv->vl_vbpd == 0) { debug("Can't get upper margin\n"); return -ENXIO; } - panel_info.vl_cmd_allow_len = fdtdec_get_int(blob, node, + priv->vl_cmd_allow_len = fdtdec_get_int(blob, node, "samsung,vl-cmd-allow-len", 0); - panel_info.win_id = fdtdec_get_int(blob, node, "samsung,winid", 0); - panel_info.init_delay = fdtdec_get_int(blob, node, + priv->win_id = fdtdec_get_int(blob, node, "samsung,winid", 0); + priv->init_delay = fdtdec_get_int(blob, node, "samsung,init-delay", 0); - panel_info.power_on_delay = fdtdec_get_int(blob, node, + priv->power_on_delay = fdtdec_get_int(blob, node, "samsung,power-on-delay", 0); - panel_info.reset_delay = fdtdec_get_int(blob, node, + priv->reset_delay = fdtdec_get_int(blob, node, "samsung,reset-delay", 0); - panel_info.interface_mode = fdtdec_get_int(blob, node, + priv->interface_mode = fdtdec_get_int(blob, node, "samsung,interface-mode", 0); - panel_info.mipi_enabled = fdtdec_get_int(blob, node, + priv->mipi_enabled = fdtdec_get_int(blob, node, "samsung,mipi-enabled", 0); - panel_info.dp_enabled = fdtdec_get_int(blob, node, + priv->dp_enabled = fdtdec_get_int(blob, node, "samsung,dp-enabled", 0); - panel_info.cs_setup = fdtdec_get_int(blob, node, + priv->cs_setup = fdtdec_get_int(blob, node, "samsung,cs-setup", 0); - panel_info.wr_setup = fdtdec_get_int(blob, node, + priv->wr_setup = fdtdec_get_int(blob, node, "samsung,wr-setup", 0); - panel_info.wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0); - panel_info.wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0); + priv->wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0); + priv->wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0); - panel_info.logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0); - if (panel_info.logo_on) { - panel_info.logo_width = fdtdec_get_int(blob, node, + priv->logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0); + if (priv->logo_on) { + priv->logo_width = fdtdec_get_int(blob, node, "samsung,logo-width", 0); - panel_info.logo_height = fdtdec_get_int(blob, node, + priv->logo_height = fdtdec_get_int(blob, node, "samsung,logo-height", 0); - panel_info.logo_addr = fdtdec_get_int(blob, node, + priv->logo_addr = fdtdec_get_int(blob, node, "samsung,logo-addr", 0); } - panel_info.rgb_mode = fdtdec_get_int(blob, node, + priv->rgb_mode = fdtdec_get_int(blob, node, "samsung,rgb-mode", 0); - panel_info.pclk_name = fdtdec_get_int(blob, node, + priv->pclk_name = fdtdec_get_int(blob, node, "samsung,pclk-name", 0); - panel_info.sclk_div = fdtdec_get_int(blob, node, + priv->sclk_div = fdtdec_get_int(blob, node, "samsung,sclk-div", 0); - panel_info.dual_lcd_enabled = fdtdec_get_int(blob, node, + priv->dual_lcd_enabled = fdtdec_get_int(blob, node, "samsung,dual-lcd-enabled", 0); return 0; } -void lcd_ctrl_init(void *lcdbase) +static int exynos_fb_probe(struct udevice *dev) { + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct exynos_fb_priv *priv = dev_get_priv(dev); + struct udevice *panel, *bridge; + struct udevice *dp; + int ret; + + debug("%s: start\n", __func__); set_system_display_ctrl(); set_lcd_clk(); #ifdef CONFIG_EXYNOS_MIPI_DSIM exynos_init_dsim_platform_data(&panel_info); #endif - exynos_lcd_misc_init(&panel_info); + exynos_fimd_lcd_init(dev); - exynos_lcd_init(&panel_info, (ulong)lcdbase); -} + ret = uclass_first_device(UCLASS_PANEL, &panel); + if (ret) { + printf("LCD panel failed to probe\n"); + return ret; + } + if (!panel) { + printf("LCD panel not found\n"); + return -ENODEV; + } -void lcd_enable(void) -{ - if (panel_info.logo_on) { - memset((void *)gd->fb_base, 0, - panel_info.vl_width * panel_info.vl_height * - (NBITS(panel_info.vl_bpix) >> 3)); + ret = uclass_first_device(UCLASS_DISPLAY, &dp); + if (ret) { + debug("%s: Display device error %d\n", __func__, ret); + return ret; + } + if (!dev) { + debug("%s: Display device missing\n", __func__); + return -ENODEV; + } + ret = display_enable(dp, 18, NULL); + if (ret) { + debug("%s: Display enable error %d\n", __func__, ret); + return ret; } - lcd_panel_on(&panel_info); + /* backlight / pwm */ + ret = panel_enable_backlight(panel); + if (ret) { + debug("%s: backlight error: %d\n", __func__, ret); + return ret; + } + + ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge); + if (!ret) + ret = video_bridge_set_backlight(bridge, 80); + if (ret) { + debug("%s: No video bridge, or no backlight on bridge\n", + __func__); + exynos_pinmux_config(PERIPH_ID_PWM0, 0); + } + + uc_priv->xsize = priv->vl_col; + uc_priv->ysize = priv->vl_row; + uc_priv->bpix = priv->vl_bpix; + + /* Enable flushing after LCD writes if requested */ + video_set_flush_dcache(dev, true); + + return 0; } -/* dummy function */ -void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +static int exynos_fb_bind(struct udevice *dev) { - return; + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + + /* This is the maximum panel size we expect to see */ + plat->size = 1920 * 1080 * 2; + + return 0; } + +static const struct video_ops exynos_fb_ops = { +}; + +static const struct udevice_id exynos_fb_ids[] = { + { .compatible = "samsung,exynos-fimd" }, + { } +}; + +U_BOOT_DRIVER(exynos_fb) = { + .name = "exynos_fb", + .id = UCLASS_VIDEO, + .of_match = exynos_fb_ids, + .ops = &exynos_fb_ops, + .bind = exynos_fb_bind, + .probe = exynos_fb_probe, + .ofdata_to_platdata = exynos_fb_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct exynos_fb_priv), +}; diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c index 62193000970..b2fe345ce3d 100644 --- a/drivers/video/simple_panel.c +++ b/drivers/video/simple_panel.c @@ -88,6 +88,8 @@ static const struct panel_ops simple_panel_ops = { static const struct udevice_id simple_panel_ids[] = { { .compatible = "simple-panel" }, { .compatible = "auo,b133xtn01" }, + { .compatible = "auo,b116xw03" }, + { .compatible = "auo,b133htn01" }, { } }; diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index b2ff4dd9277..311fd09d6bc 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -124,7 +124,6 @@ #define CONFIG_SYS_I2C_S3C24X0 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 -#define CONFIG_I2C_EDID /* SPI */ #ifdef CONFIG_SPI_FLASH diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index 8b61a52c5a2..3d81f9457d8 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -13,8 +13,8 @@ #undef EXYNOS_DEVICE_SETTINGS #define EXYNOS_DEVICE_SETTINGS \ "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,lcd\0" \ - "stderr=serial,lcd\0" + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" #define CONFIG_EXYNOS5_DT @@ -32,6 +32,7 @@ #define CONFIG_EXYNOS_FB #define CONFIG_EXYNOS_DP #define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK #endif /* Enable keyboard */ -- cgit v1.3.1 From 667dbcd01d35a69a0a01ecd09b9f18d9aa0efe72 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 24 May 2016 21:14:01 +0900 Subject: ARM: uniphier: add PH1-LD11 SoC support This is a low-cost ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/Kconfig | 5 + arch/arm/mach-uniphier/board_early_init_f.c | 7 ++ arch/arm/mach-uniphier/boards.c | 20 ++++ arch/arm/mach-uniphier/boot-mode/Makefile | 1 + arch/arm/mach-uniphier/boot-mode/boot-mode.c | 3 +- arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c | 3 +- arch/arm/mach-uniphier/clk/Makefile | 1 + arch/arm/mach-uniphier/clk/clk-ld11.c | 28 +++++ arch/arm/mach-uniphier/cpu_info.c | 2 +- arch/arm/mach-uniphier/dram/Makefile | 1 + arch/arm/mach-uniphier/dram/umc-ld11.c | 124 ++++++++++++++++++++++ arch/arm/mach-uniphier/dram/umc64-regs.h | 12 +++ arch/arm/mach-uniphier/early-clk/Makefile | 1 + arch/arm/mach-uniphier/early-clk/early-clk-ld11.c | 32 ++++++ arch/arm/mach-uniphier/early-pinctrl/Makefile | 1 + arch/arm/mach-uniphier/init.h | 4 + arch/arm/mach-uniphier/init/Makefile | 1 + arch/arm/mach-uniphier/init/init-ld11.c | 59 ++++++++++ arch/arm/mach-uniphier/init/init.c | 5 + arch/arm/mach-uniphier/pinctrl/Makefile | 1 + arch/arm/mach-uniphier/sbc/Makefile | 1 + arch/arm/mach-uniphier/sg-regs.h | 3 + configs/uniphier_ld11_defconfig | 31 ++++++ include/configs/uniphier.h | 12 ++- 24 files changed, 354 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mach-uniphier/clk/clk-ld11.c create mode 100644 arch/arm/mach-uniphier/dram/umc-ld11.c create mode 100644 arch/arm/mach-uniphier/early-clk/early-clk-ld11.c create mode 100644 arch/arm/mach-uniphier/init/init-ld11.c create mode 100644 configs/uniphier_ld11_defconfig (limited to 'include') diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 87d1675ffc3..ae763ad94e3 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -23,6 +23,11 @@ config ARCH_UNIPHIER_PRO5_PXS2_LD6B bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC" select CPU_V7 +config ARCH_UNIPHIER_LD11 + bool "UniPhier PH1-LD11 SoC" + select ARM64 + select SPL_SEPARATE_BSS + config ARCH_UNIPHIER_LD20 bool "UniPhier PH1-LD20 SoC" select ARM64 diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c index 2a7ae1b5297..f853701f44d 100644 --- a/arch/arm/mach-uniphier/board_early_init_f.c +++ b/arch/arm/mach-uniphier/board_early_init_f.c @@ -62,6 +62,13 @@ int board_early_init_f(void) uniphier_pxs2_clk_init(); break; #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD11) + case SOC_UNIPHIER_LD11: + uniphier_ld20_pin_init(); + led_puts("U1"); + uniphier_ld11_clk_init(); + break; +#endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) case SOC_UNIPHIER_LD20: uniphier_ld20_pin_init(); diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index f0547c336e0..ed308f3ecba 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -165,6 +165,23 @@ static const struct uniphier_board_data uniphier_ld6b_data = { }; #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD11) +static const struct uniphier_board_data uniphier_ld11_data = { + .dram_freq = 1600, + .dram_nr_ch = 2, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x20000000, + .width = 16, + }, + .dram_ch[1] = { + .base = 0xa0000000, + .size = 0x20000000, + .width = 16, + }, +}; +#endif + #if defined(CONFIG_ARCH_UNIPHIER_LD20) static const struct uniphier_board_data uniphier_ld20_data = { .dram_freq = 1866, @@ -216,6 +233,9 @@ static const struct uniphier_board_id uniphier_boards[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD6B) { "socionext,ph1-ld6b", &uniphier_ld6b_data, }, #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD11) + { "socionext,ph1-ld11", &uniphier_ld11_data, }, +#endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) { "socionext,ph1-ld20", &uniphier_ld20_data, }, #endif diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile index 6cd096ec5fb..d7fefc5bbd0 100644 --- a/arch/arm/mach-uniphier/boot-mode/Makefile +++ b/arch/arm/mach-uniphier/boot-mode/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-mode-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-mode-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-mode-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-mode-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-mode-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-mode-ld20.o obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c index b180f44ce8c..4b744da2529 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c @@ -39,7 +39,8 @@ u32 spl_boot_device_raw(void) case SOC_UNIPHIER_LD6B: return uniphier_pxs2_boot_device(); #endif -#if defined(CONFIG_ARCH_UNIPHIER_LD20) +#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) + case SOC_UNIPHIER_LD11: case SOC_UNIPHIER_LD20: return uniphier_ld20_boot_device(); #endif diff --git a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c index fa97dc58569..a8ee3822480 100644 --- a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c +++ b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c @@ -39,7 +39,8 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) uniphier_pxs2_boot_mode_show(); break; #endif -#if defined(CONFIG_ARCH_UNIPHIER_LD20) +#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) + case SOC_UNIPHIER_LD11: case SOC_UNIPHIER_LD20: uniphier_ld20_boot_mode_show(); break; diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 93e9d91e478..1428e0c9cc9 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c new file mode 100644 index 00000000000..92a07338a81 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/clk-ld11.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include "../init.h" +#include "../sg-regs.h" + +void uniphier_ld11_clk_init(void) +{ + if (readl(SG_PINMON0) & BIT(27)) { + /* if booted without stand-by MPU */ + + writel(1, SG_ETPHYPSHUT); + writel(1, SG_ETPHYCNT); + + udelay(1); /* wait for regulator level 1.1V -> 2.5V */ + + writel(3, SG_ETPHYCNT); + writel(3, SG_ETPHYPSHUT); + writel(7, SG_ETPHYCNT); + } +} diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c index f9646c0205b..6ad4c76dc48 100644 --- a/arch/arm/mach-uniphier/cpu_info.c +++ b/arch/arm/mach-uniphier/cpu_info.c @@ -45,7 +45,7 @@ int print_cpuinfo(void) puts("PH1-LD6b (MN2WS0320)"); break; case 0x31: - puts("PH1-LD11 ()"); + puts("PH1-LD11 (SC1405AP1)"); break; case 0x32: puts("PH1-LD20 (SC1401AJ1)"); diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index 41aa53b6b5e..5b9d8925114 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \ ddrphy-training.o ddrphy-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += umc-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += umc-ld20.o else diff --git a/arch/arm/mach-uniphier/dram/umc-ld11.c b/arch/arm/mach-uniphier/dram/umc-ld11.c new file mode 100644 index 00000000000..1be18a867ce --- /dev/null +++ b/arch/arm/mach-uniphier/dram/umc-ld11.c @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2016 Socionext Inc. + */ + +#include +#include +#include +#include + +#include "../init.h" +#include "umc64-regs.h" + +#define CONFIG_DDR_FREQ 1866 + +#define DRAM_CH_NR 2 + +enum dram_freq { + DRAM_FREQ_1600M, + DRAM_FREQ_NR, +}; + +enum dram_size { + DRAM_SZ_256M, + DRAM_SZ_512M, + DRAM_SZ_NR, +}; + +/* umc */ +static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20}; +static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08}; +static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04}; +static u32 umc_cmdctle[DRAM_FREQ_NR] = {0x0078071D}; +static u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200}; +static u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808}; + +static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000810}; +static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000810}; +static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000004}; +static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000004}; +static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002}; +static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002}; +static u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203}; +static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605}; + +static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, + unsigned long size, int ch) +{ + writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA); + writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB); + writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC); + writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE); + writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF); + writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG); + + writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0); + writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1); + + writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0); + writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1); + + writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0); + writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1); + + writel(0x00000003, dc_base + UMC_ACSSETA); + writel(0x00000103, dc_base + UMC_FLOWCTLG); + writel(umc_acssetb[ch], dc_base + UMC_ACSSETB); + writel(0x02020200, dc_base + UMC_SPCSETB); + writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH); + writel(0x00000002, dc_base + UMC_ACFETCHCTRL); + + return 0; +} + +static int umc_ch_init(void __iomem *umc_ch_base, + enum dram_freq freq, unsigned long size, int ch) +{ + void __iomem *dc_base = umc_ch_base; + + return umc_dc_init(dc_base, freq, size, ch); +} + +static void um_init(void __iomem *um_base) +{ + writel(0x00000001, um_base + UMC_SIORST); + writel(0x00000001, um_base + UMC_VO0RST); + writel(0x00000001, um_base + UMC_VPERST); + writel(0x00000001, um_base + UMC_RGLRST); + writel(0x00000001, um_base + UMC_A2DRST); + writel(0x00000001, um_base + UMC_DMDRST); +} + +int uniphier_ld11_umc_init(const struct uniphier_board_data *bd) +{ + void __iomem *um_base = (void __iomem *)0x5B800000; + void __iomem *umc_ch_base = (void __iomem *)0x5BC00000; + enum dram_freq freq; + int ch, ret; + + switch (bd->dram_freq) { + case 1600: + freq = DRAM_FREQ_1600M; + break; + default: + pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq); + return -EINVAL; + } + + for (ch = 0; ch < bd->dram_nr_ch; ch++) { + unsigned long size = bd->dram_ch[ch].size; + unsigned int width = bd->dram_ch[ch].width; + + ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch); + if (ret) { + pr_err("failed to initialize UMC ch%d\n", ch); + return ret; + } + + umc_ch_base += 0x00200000; + } + + um_init(um_base); + + return 0; +} diff --git a/arch/arm/mach-uniphier/dram/umc64-regs.h b/arch/arm/mach-uniphier/dram/umc64-regs.h index 1b6a838a4c1..860d04e3814 100644 --- a/arch/arm/mach-uniphier/dram/umc64-regs.h +++ b/arch/arm/mach-uniphier/dram/umc64-regs.h @@ -18,6 +18,8 @@ #define UMC_INITSET 0x00000040 #define UMC_INITSTAT 0x00000044 #define UMC_CMDCTLE 0x00000050 +#define UMC_CMDCTLF 0x00000054 +#define UMC_CMDCTLG 0x00000058 #define UMC_SPCSETB 0x00000084 #define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ #define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ @@ -32,6 +34,7 @@ #define UMC_FLOWCTLA 0x00000400 #define UMC_FLOWCTLB 0x00000404 #define UMC_FLOWCTLC 0x00000408 +#define UMC_ACFETCHCTRL 0x00000460 #define UMC_FLOWCTLG 0x00000508 #define UMC_RDATACTL_D0 0x00000600 #define UMC_WDATACTL_D0 0x00000604 @@ -42,6 +45,7 @@ #define UMC_ODTCTL_D1 0x0000061C #define UMC_RESPCTL 0x00000624 #define UMC_DIRECTBUSCTRLA 0x00000680 +#define UMC_DEBUGC 0x00000718 #define UMC_DCCGCTL 0x00000720 #define UMC_DICGCTLA 0x00000724 #define UMC_DICGCTLB 0x00000728 @@ -70,4 +74,12 @@ #define UMC_MBUS9 0x00002478 #define UMC_MBUS10 0x000024F8 +/* UMC1 register */ +#define UMC_SIORST 0x00000728 +#define UMC_VO0RST 0x0000073c +#define UMC_VPERST 0x00000744 +#define UMC_RGLRST 0x00000750 +#define UMC_A2DRST 0x00000764 +#define UMC_DMDRST 0x00000770 + #endif /* UMC_LD20_REGS_H */ diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile index 9242b416c5a..755a3618b57 100644 --- a/arch/arm/mach-uniphier/early-clk/Makefile +++ b/arch/arm/mach-uniphier/early-clk/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c new file mode 100644 index 00000000000..c94d83c4ed5 --- /dev/null +++ b/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include "../init.h" +#include "../sc64-regs.h" + +int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL7); + tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30; + writel(tmp, SC_RSTCTRL7); + + /* provide clocks */ + tmp = readl(SC_CLKCTRL4); + tmp |= SC_CLKCTRL4_PERI; + writel(tmp, SC_CLKCTRL4); + + tmp = readl(SC_CLKCTRL7); + tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30; + writel(tmp, SC_CLKCTRL7); + + return 0; +} diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile index a1039025ca4..7177a8cf8f0 100644 --- a/arch/arm/mach-uniphier/early-pinctrl/Makefile +++ b/arch/arm/mach-uniphier/early-pinctrl/Makefile @@ -3,4 +3,5 @@ # obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-pinctrl-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-pinctrl-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-pinctrl-ld20.o diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index ab0a68d83d8..cba0bc9d374 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -32,6 +32,7 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd); int uniphier_sld8_init(const struct uniphier_board_data *bd); int uniphier_pro5_init(const struct uniphier_board_data *bd); int uniphier_pxs2_init(const struct uniphier_board_data *bd); +int uniphier_ld11_init(const struct uniphier_board_data *bd); int uniphier_ld20_init(const struct uniphier_board_data *bd); #if defined(CONFIG_MICRO_SUPPORT_CARD) @@ -81,6 +82,7 @@ int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd); int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd); int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd); int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd); +int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd); int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd); int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd); @@ -91,6 +93,7 @@ int uniphier_pro4_umc_init(const struct uniphier_board_data *bd); int uniphier_sld8_umc_init(const struct uniphier_board_data *bd); int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd); int uniphier_ld20_umc_init(const struct uniphier_board_data *bd); +int uniphier_ld11_umc_init(const struct uniphier_board_data *bd); void uniphier_sld3_pin_init(void); void uniphier_ld4_pin_init(void); @@ -105,6 +108,7 @@ void uniphier_ld4_clk_init(void); void uniphier_pro4_clk_init(void); void uniphier_pro5_clk_init(void); void uniphier_pxs2_clk_init(void); +void uniphier_ld11_clk_init(void); void uniphier_ld20_clk_init(void); void cci500_init(int nr_slaves); diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile index b58e6c885a3..dcaa4451ad2 100644 --- a/arch/arm/mach-uniphier/init/Makefile +++ b/arch/arm/mach-uniphier/init/Makefile @@ -11,4 +11,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += init-sld8.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += init-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += init-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += init-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += init-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += init-ld20.o diff --git a/arch/arm/mach-uniphier/init/init-ld11.c b/arch/arm/mach-uniphier/init/init-ld11.c new file mode 100644 index 00000000000..de2dc62b5d2 --- /dev/null +++ b/arch/arm/mach-uniphier/init/init-ld11.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "../init.h" +#include "../micro-support-card.h" + +int uniphier_ld11_init(const struct uniphier_board_data *bd) +{ + uniphier_sbc_init_savepin(bd); + uniphier_pxs2_sbc_init(bd); + uniphier_ld20_early_pin_init(bd); + + support_card_reset(); + + support_card_init(); + + led_puts("L0"); + + memconf_init(bd); + + led_puts("L1"); + + uniphier_ld11_early_clk_init(bd); + + led_puts("L2"); + + led_puts("L3"); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_puts("L4"); + + { + int res; + + res = uniphier_ld11_umc_init(bd); + if (res < 0) { + while (1) + ; + } + } + + led_puts("L5"); + + dcache_disable(); + + led_puts("L6"); + + return 0; +} diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c index 15a53ce0689..77e5b99047b 100644 --- a/arch/arm/mach-uniphier/init/init.c +++ b/arch/arm/mach-uniphier/init/init.c @@ -55,6 +55,11 @@ void spl_board_init(void) uniphier_pxs2_init(param); break; #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD11) + case SOC_UNIPHIER_LD11: + uniphier_ld11_init(param); + break; +#endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) case SOC_UNIPHIER_LD20: uniphier_ld20_init(param); diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile index b579cb06e74..7f4d9f76a8d 100644 --- a/arch/arm/mach-uniphier/pinctrl/Makefile +++ b/arch/arm/mach-uniphier/pinctrl/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pinctrl-sld8.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += pinctrl-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += pinctrl-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += pinctrl-ld6b.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pinctrl-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pinctrl-ld20.o diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile index 38da253975c..ec3c22c28d8 100644 --- a/arch/arm/mach-uniphier/sbc/Makefile +++ b/arch/arm/mach-uniphier/sbc/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-savepin.o sbc-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-savepin.o sbc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o sbc-pxs2.o diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 1d71ce87ae8..a179d615be9 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -59,6 +59,9 @@ #define SG_MEMCONF_SPARSEMEM (0x1 << 4) +#define SG_ETPHYPSHUT (SG_CTRL_BASE | 0x554) +#define SG_ETPHYCNT (SG_CTRL_BASE | 0x550) + /* Pin Control */ #define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000) diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig new file mode 100644 index 00000000000..ffcac79762a --- /dev/null +++ b/configs/uniphier_ld11_defconfig @@ -0,0 +1,31 @@ +CONFIG_ARM=y +CONFIG_ARCH_UNIPHIER=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ARCH_UNIPHIER_LD11=y +CONFIG_MICRO_SUPPORT_CARD=y +CONFIG_SYS_TEXT_BASE=0x84000000 +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld11-ref" +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_ENV_EXISTS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_GPIO_UNIPHIER=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_UNIPHIER_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 18cb9638447..10fd8c21ea5 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -104,7 +104,11 @@ #define COUNTER_FREQUENCY 50000000 #define CONFIG_GICV3 #define GICD_BASE 0x5fe00000 +#if defined(CONFIG_ARCH_UNIPHIER_LD11) +#define GICR_BASE 0x5fe40000 +#elif defined(CONFIG_ARCH_UNIPHIER_LD20) #define GICR_BASE 0x5fe80000 +#endif #else /* Time clock 1MHz */ #define CONFIG_SYS_TIMER_RATE 1000000 @@ -270,7 +274,9 @@ #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif -#if defined(CONFIG_ARCH_UNIPHIER_LD20) +#if defined(CONFIG_ARCH_UNIPHIER_LD11) +#define CONFIG_SPL_STACK (0x30014c00) +#elif defined(CONFIG_ARCH_UNIPHIER_LD20) #define CONFIG_SPL_STACK (0x3001c000) #else #define CONFIG_SPL_STACK (0x00100000) @@ -301,7 +307,11 @@ #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 #define CONFIG_SPL_MAX_SIZE 0x10000 +#if defined(CONFIG_ARCH_UNIPHIER_LD11) +#define CONFIG_SPL_BSS_START_ADDR 0x30012000 +#elif defined(CONFIG_ARCH_UNIPHIER_LD20) #define CONFIG_SPL_BSS_START_ADDR 0x30016000 +#endif #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ -- cgit v1.3.1 From 15278ccb848dbcd8825874f943bc21afda987219 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 2 May 2016 10:28:12 +0800 Subject: sunxi: power: axp818: Add support for switch SW The AXP818 has a switchable output, SW. This is commonly used for controlling power to the LCD backlight. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede --- board/sunxi/board.c | 1 + drivers/power/Kconfig | 7 +++++++ drivers/power/axp818.c | 10 ++++++++++ include/axp818.h | 1 + include/axp_pmic.h | 1 + 5 files changed, 20 insertions(+) (limited to 'include') diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 3cf36147b24..6a0a8dbc4f5 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -523,6 +523,7 @@ void sunxi_board_init(void) power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); + power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); #endif #endif printf("DRAM:"); diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index b365fd46fa7..02cb8e7ba68 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -265,6 +265,13 @@ config AXP_FLDO3_VOLT Set the voltage (mV) to program the axp pmic fldo3 at, set to 0 to disable fldo3. +config AXP_SW_ON + bool "axp pmic sw on" + depends on AXP818_POWER + default n + ---help--- + Enable to turn on axp pmic sw. + config SY8106A_VOUT1_VOLT int "SY8106A pmic VOUT1 voltage" depends on SY8106A_POWER diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c index 3ac05ffefe0..bf6ecd6be59 100644 --- a/drivers/power/axp818.c +++ b/drivers/power/axp818.c @@ -225,6 +225,16 @@ int axp_set_fldo(int fldo_num, unsigned int mvolt) AXP818_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1)); } +int axp_set_sw(bool on) +{ + if (on) + return pmic_bus_setbits(AXP818_OUTPUT_CTRL2, + AXP818_OUTPUT_CTRL2_SW_EN); + + return pmic_bus_clrbits(AXP818_OUTPUT_CTRL2, + AXP818_OUTPUT_CTRL2_SW_EN); +} + int axp_init(void) { u8 axp_chip_id; diff --git a/include/axp818.h b/include/axp818.h index 5630eed04d8..f7f343a194a 100644 --- a/include/axp818.h +++ b/include/axp818.h @@ -24,6 +24,7 @@ #define AXP818_OUTPUT_CTRL2_DLDO2_EN (1 << 4) #define AXP818_OUTPUT_CTRL2_DLDO3_EN (1 << 5) #define AXP818_OUTPUT_CTRL2_DLDO4_EN (1 << 6) +#define AXP818_OUTPUT_CTRL2_SW_EN (1 << 7) #define AXP818_OUTPUT_CTRL3 0x13 #define AXP818_OUTPUT_CTRL3_FLDO1_EN (1 << 2) #define AXP818_OUTPUT_CTRL3_FLDO2_EN (1 << 3) diff --git a/include/axp_pmic.h b/include/axp_pmic.h index b203cc88ddb..2ed5196354e 100644 --- a/include/axp_pmic.h +++ b/include/axp_pmic.h @@ -32,6 +32,7 @@ int axp_set_aldo4(unsigned int mvolt); int axp_set_dldo(int dldo_num, unsigned int mvolt); int axp_set_eldo(int eldo_num, unsigned int mvolt); int axp_set_fldo(int fldo_num, unsigned int mvolt); +int axp_set_sw(bool on); int axp_init(void); int axp_get_sid(unsigned int *sid); -- cgit v1.3.1 From 511992695de9309b53a291caa5ff9bce62d44ae4 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 2 May 2016 10:28:14 +0800 Subject: sunxi: Implement poweroff support for axp818 pmic Adds poweroff support for axp818 pmic. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede --- drivers/power/Kconfig | 1 + drivers/power/axp818.c | 11 +++++++++++ include/axp818.h | 3 +++ 3 files changed, 15 insertions(+) (limited to 'include') diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 02cb8e7ba68..d1375369c19 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -44,6 +44,7 @@ config AXP221_POWER config AXP818_POWER boolean "axp818 pmic support" depends on MACH_SUN8I_A83T + select CMD_POWEROFF ---help--- Say y here to enable support for the axp818 pmic found on A83T dev board. diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c index bf6ecd6be59..af4d7a69032 100644 --- a/drivers/power/axp818.c +++ b/drivers/power/axp818.c @@ -255,3 +255,14 @@ int axp_init(void) return 0; } + +int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + pmic_bus_write(AXP818_SHUTDOWN, AXP818_SHUTDOWN_POWEROFF); + + /* infinite loop during shutdown */ + while (1) {} + + /* not reached */ + return 0; +} diff --git a/include/axp818.h b/include/axp818.h index f7f343a194a..959774c76fa 100644 --- a/include/axp818.h +++ b/include/axp818.h @@ -55,6 +55,9 @@ #define AXP818_ALDO2_CTRL 0x29 #define AXP818_ALDO3_CTRL 0x2a +#define AXP818_SHUTDOWN 0x32 +#define AXP818_SHUTDOWN_POWEROFF (1 << 7) + /* For axp_gpio.c */ #define AXP_POWER_STATUS 0x00 #define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) -- cgit v1.3.1 From 795857df413aea278af95305d4b6ffc48089d6e8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 2 May 2016 10:28:15 +0800 Subject: sunxi: power: add AXP809 support The A80 uses the AXP809 as its primary PMIC. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/pmic_bus.c | 6 +- board/sunxi/board.c | 20 +++- drivers/power/Kconfig | 72 ++++++++----- drivers/power/Makefile | 1 + drivers/power/axp809.c | 238 +++++++++++++++++++++++++++++++++++++++++ include/axp809.h | 60 +++++++++++ include/axp_pmic.h | 3 + 8 files changed, 367 insertions(+), 34 deletions(-) create mode 100644 drivers/power/axp809.c create mode 100644 include/axp809.h (limited to 'include') diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index ad3d6c49185..25367cf3800 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o obj-$(CONFIG_AXP152_POWER) += pmic_bus.o obj-$(CONFIG_AXP209_POWER) += pmic_bus.o obj-$(CONFIG_AXP221_POWER) += pmic_bus.o +obj-$(CONFIG_AXP809_POWER) += pmic_bus.o obj-$(CONFIG_AXP818_POWER) += pmic_bus.o ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c index 5b81a8d8e12..7c57f02792b 100644 --- a/arch/arm/mach-sunxi/pmic_bus.c +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -36,7 +36,7 @@ int pmic_bus_init(void) if (!needs_init) return 0; -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I p2wi_init(); ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR, @@ -62,7 +62,7 @@ int pmic_bus_read(u8 reg, u8 *data) return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1); #elif defined CONFIG_AXP209_POWER return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); -#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I return p2wi_read(reg, data); # else @@ -77,7 +77,7 @@ int pmic_bus_write(u8 reg, u8 data) return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1); #elif defined CONFIG_AXP209_POWER return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); -#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I return p2wi_write(reg, data); # else diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 6a0a8dbc4f5..103aafe14d9 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -483,10 +483,12 @@ void sunxi_board_init(void) #endif #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ - defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER + defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ + defined CONFIG_AXP818_POWER power_failed = axp_init(); -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ + defined CONFIG_AXP818_POWER power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); #endif power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); @@ -494,11 +496,13 @@ void sunxi_board_init(void) #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); #endif -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ + defined CONFIG_AXP818_POWER power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); #endif -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ + defined CONFIG_AXP818_POWER power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); #endif power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); @@ -509,11 +513,14 @@ void sunxi_board_init(void) power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); #endif -#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP818_POWER) +#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \ + defined(CONFIG_AXP818_POWER) power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); +#if !defined CONFIG_AXP809_POWER power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); +#endif power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); @@ -523,6 +530,9 @@ void sunxi_board_init(void) power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); +#endif + +#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); #endif #endif diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index d1375369c19..3c441678059 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -41,6 +41,13 @@ config AXP221_POWER Select this to enable support for the axp221/axp223 pmic found on most A23 and A31 boards. +config AXP809_POWER + boolean "axp809 pmic support" + depends on MACH_SUN9I + select CMD_POWEROFF + ---help--- + Say y here to enable support for the axp809 pmic found on A80 boards. + config AXP818_POWER boolean "axp818 pmic support" depends on MACH_SUN8I_A83T @@ -60,36 +67,39 @@ endchoice config AXP_DCDC1_VOLT int "axp pmic dcdc1 voltage" - depends on AXP221_POWER || AXP818_POWER + depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 3300 if AXP818_POWER - default 3000 if MACH_SUN6I || MACH_SUN8I + default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I ---help--- Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for generic 3.3V IO voltage for external devices like the lcd-panal and sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to - safe battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T - dcdc1 is used for VCC-IO, nand, usb0, sd , etc. + save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T + dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 normally + powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG. config AXP_DCDC2_VOLT int "axp pmic dcdc2 voltage" - depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER + depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER default 900 if AXP818_POWER default 1400 if AXP152_POWER || AXP209_POWER default 1200 if MACH_SUN6I default 1100 if MACH_SUN8I + default 0 if MACH_SUN9I ---help--- Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to disable dcdc2. On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V. On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V. On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V. + On A80 boards dcdc2 powers the GPU and can be left off. On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V. config AXP_DCDC3_VOLT int "axp pmic dcdc3 voltage" - depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER - default 900 if AXP818_POWER + depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER + default 900 if AXP809_POWER || AXP818_POWER default 1500 if AXP152_POWER default 1250 if AXP209_POWER default 1200 if MACH_SUN6I || MACH_SUN8I @@ -100,51 +110,55 @@ config AXP_DCDC3_VOLT should be 1.25V. On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V. On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V. + On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V. On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V. config AXP_DCDC4_VOLT int "axp pmic dcdc4 voltage" - depends on AXP152_POWER || AXP221_POWER || AXP818_POWER + depends on AXP152_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER default 1250 if AXP152_POWER default 1200 if MACH_SUN6I default 0 if MACH_SUN8I + default 900 if MACH_SUN9I ---help--- Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to disable dcdc4. On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V. On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V. On A23 / A33 boards dcdc4 is unused and should be disabled. + On A80 boards dcdc4 powers VDD-SYS, HDMI, USB OTG and should be 0.9V. On A83T boards dcdc4 is used for VDD-GPU. config AXP_DCDC5_VOLT int "axp pmic dcdc5 voltage" - depends on AXP221_POWER || AXP818_POWER - default 1500 if MACH_SUN6I || MACH_SUN8I + depends on AXP221_POWER || AXP809_POWER || AXP818_POWER + default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I ---help--- Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to disable dcdc5. - On A23 / A31 / A33 / A83T boards dcdc5 is VCC-DRAM and should be 1.5V, - 1.35V if DDR3L is used. + On A23 / A31 / A33 / A80 / A83T boards dcdc5 is VCC-DRAM and + should be 1.5V, 1.35V if DDR3L is used. config AXP_ALDO1_VOLT int "axp pmic (a)ldo1 voltage" - depends on AXP221_POWER || AXP818_POWER + depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 if MACH_SUN6I default 1800 if MACH_SUN8I_A83T - default 3000 if MACH_SUN8I + default 3000 if MACH_SUN8I || MACH_SUN9I ---help--- Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to disable aldo1. On A31 boards aldo1 is often used to power the wifi module. On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V. + On A80 boards aldo1 powers the USB hosts and should be 3.0V. On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and should be 1.8V. config AXP_ALDO2_VOLT int "axp pmic (a)ldo2 voltage" - depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER + depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER default 3000 if AXP152_POWER || AXP209_POWER - default 0 if MACH_SUN6I + default 0 if MACH_SUN6I || MACH_SUN9I default 1800 if MACH_SUN8I_A83T default 2500 if MACH_SUN8I ---help--- @@ -154,19 +168,21 @@ config AXP_ALDO2_VOLT On A31 boards aldo2 is typically unused and should be disabled. On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V. On A23 / A33 boards aldo2 is used for VDD-DLL and should be 2.5V. + On A80 boards aldo2 powers PB pingroup and camera IO and can be left off. On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC, LPDDR2, and the codec. It should be 1.8V. config AXP_ALDO3_VOLT int "axp pmic (a)ldo3 voltage" - depends on AXP209_POWER || AXP221_POWER || AXP818_POWER - default 0 if AXP209_POWER + depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER + default 0 if AXP209_POWER || MACH_SUN9I default 3000 if MACH_SUN6I || MACH_SUN8I ---help--- Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to disable aldo3. On A10(s) / A13 / A20 boards aldo3 should be 2.8V. On A23 / A31 / A33 boards aldo3 is VCC-PLL and AVCC and should be 3.0V. + On A80 boards aldo3 is normally not used. On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be 3.0V. @@ -181,21 +197,23 @@ config AXP_ALDO4_VOLT config AXP_DLDO1_VOLT int "axp pmic dldo1 voltage" - depends on AXP221_POWER || AXP818_POWER + depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 ---help--- Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to disable dldo1. On sun6i (A31) boards with ethernet dldo1 is often used - to power the ethernet phy. On sun8i (A23) boards this is often used to - power the wifi. + to power the ethernet phy. On A23, A33 and A80 boards this is often + used to power the wifi. config AXP_DLDO2_VOLT int "axp pmic dldo2 voltage" - depends on AXP221_POWER || AXP818_POWER + depends on AXP221_POWER || AXP809_POWER || AXP818_POWER + default 3000 if MACH_SUN9I default 0 ---help--- Set the voltage (mV) to program the axp pmic dldo2 at, set to 0 to disable dldo2. + On A80 boards dldo2 normally powers the PL pins and should be 3.0V. config AXP_DLDO3_VOLT int "axp pmic dldo3 voltage" @@ -215,7 +233,7 @@ config AXP_DLDO4_VOLT config AXP_ELDO1_VOLT int "axp pmic eldo1 voltage" - depends on AXP221_POWER || AXP818_POWER + depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 ---help--- Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to @@ -223,7 +241,7 @@ config AXP_ELDO1_VOLT config AXP_ELDO2_VOLT int "axp pmic eldo2 voltage" - depends on AXP221_POWER || AXP818_POWER + depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 ---help--- Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to @@ -231,13 +249,15 @@ config AXP_ELDO2_VOLT config AXP_ELDO3_VOLT int "axp pmic eldo3 voltage" - depends on AXP221_POWER || AXP818_POWER + depends on AXP221_POWER || AXP809_POWER || AXP818_POWER + default 3000 if MACH_SUN9I default 0 ---help--- Set the voltage (mV) to program the axp pmic eldo3 at, set to 0 to disable eldo3. On some A31(s) tablets it might be used to supply 1.2V for the SSD2828 chip (converter of parallel LCD interface into MIPI DSI). + On A80 boards it powers the PM pingroup and should be 3.0V. config AXP_FLDO1_VOLT int "axp pmic fldo1 voltage" @@ -268,7 +288,7 @@ config AXP_FLDO3_VOLT config AXP_SW_ON bool "axp pmic sw on" - depends on AXP818_POWER + depends on AXP809_POWER || AXP818_POWER default n ---help--- Enable to turn on axp pmic sw. diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 690faa0f5e4..b43523e6282 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_AS3722_POWER) += as3722.o obj-$(CONFIG_AXP152_POWER) += axp152.o obj-$(CONFIG_AXP209_POWER) += axp209.o obj-$(CONFIG_AXP221_POWER) += axp221.o +obj-$(CONFIG_AXP809_POWER) += axp809.o obj-$(CONFIG_AXP818_POWER) += axp818.o obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o diff --git a/drivers/power/axp809.c b/drivers/power/axp809.c new file mode 100644 index 00000000000..c8b76cf9b7f --- /dev/null +++ b/drivers/power/axp809.c @@ -0,0 +1,238 @@ +/* + * AXP809 driver based on AXP221 driver + * + * + * (C) Copyright 2016 Chen-Yu Tsai + * + * Based on axp221.c + * (C) Copyright 2014 Hans de Goede + * (C) Copyright 2013 Oliver Schinagl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static u8 axp809_mvolt_to_cfg(int mvolt, int min, int max, int div) +{ + if (mvolt < min) + mvolt = min; + else if (mvolt > max) + mvolt = max; + + return (mvolt - min) / div; +} + +int axp_set_dcdc1(unsigned int mvolt) +{ + int ret; + u8 cfg = axp809_mvolt_to_cfg(mvolt, 1600, 3400, 100); + + if (mvolt == 0) + return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1, + AXP809_OUTPUT_CTRL1_DCDC1_EN); + + ret = pmic_bus_write(AXP809_DCDC1_CTRL, cfg); + if (ret) + return ret; + + ret = pmic_bus_setbits(AXP809_OUTPUT_CTRL2, + AXP809_OUTPUT_CTRL2_DC1SW_EN); + if (ret) + return ret; + + return pmic_bus_setbits(AXP809_OUTPUT_CTRL1, + AXP809_OUTPUT_CTRL1_DCDC1_EN); +} + +int axp_set_dcdc2(unsigned int mvolt) +{ + int ret; + u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1540, 20); + + if (mvolt == 0) + return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1, + AXP809_OUTPUT_CTRL1_DCDC2_EN); + + ret = pmic_bus_write(AXP809_DCDC2_CTRL, cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP809_OUTPUT_CTRL1, + AXP809_OUTPUT_CTRL1_DCDC2_EN); +} + +int axp_set_dcdc3(unsigned int mvolt) +{ + int ret; + u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1860, 20); + + if (mvolt == 0) + return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1, + AXP809_OUTPUT_CTRL1_DCDC3_EN); + + ret = pmic_bus_write(AXP809_DCDC3_CTRL, cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP809_OUTPUT_CTRL1, + AXP809_OUTPUT_CTRL1_DCDC3_EN); +} + +int axp_set_dcdc4(unsigned int mvolt) +{ + int ret; + u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1540, 20); + + if (mvolt >= 1540) + cfg = 0x30 + axp809_mvolt_to_cfg(mvolt, 1800, 2600, 100); + + if (mvolt == 0) + return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1, + AXP809_OUTPUT_CTRL1_DCDC4_EN); + + ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP809_OUTPUT_CTRL1, + AXP809_OUTPUT_CTRL1_DCDC4_EN); +} + +int axp_set_dcdc5(unsigned int mvolt) +{ + int ret; + u8 cfg = axp809_mvolt_to_cfg(mvolt, 1000, 2550, 50); + + if (mvolt == 0) + return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1, + AXP809_OUTPUT_CTRL1_DCDC5_EN); + + ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP809_OUTPUT_CTRL1, + AXP809_OUTPUT_CTRL1_DCDC5_EN); +} + +int axp_set_aldo(int aldo_num, unsigned int mvolt) +{ + int ret; + u8 cfg; + + if (aldo_num < 1 || aldo_num > 3) + return -EINVAL; + + if (mvolt == 0 && aldo_num == 3) + return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2, + AXP809_OUTPUT_CTRL2_ALDO3_EN); + if (mvolt == 0) + return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1, + AXP809_OUTPUT_CTRL1_ALDO1_EN << (aldo_num - 1)); + + cfg = axp809_mvolt_to_cfg(mvolt, 700, 3300, 100); + ret = pmic_bus_write(AXP809_ALDO1_CTRL + (aldo_num - 1), cfg); + if (ret) + return ret; + + if (aldo_num == 3) + return pmic_bus_setbits(AXP809_OUTPUT_CTRL2, + AXP809_OUTPUT_CTRL2_ALDO3_EN); + return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1, + AXP809_OUTPUT_CTRL1_ALDO1_EN << (aldo_num - 1)); +} + +/* TODO: re-work other AXP drivers to consolidate ALDO functions. */ +int axp_set_aldo1(unsigned int mvolt) +{ + return axp_set_aldo(1, mvolt); +} + +int axp_set_aldo2(unsigned int mvolt) +{ + return axp_set_aldo(2, mvolt); +} + +int axp_set_aldo3(unsigned int mvolt) +{ + return axp_set_aldo(3, mvolt); +} + +int axp_set_dldo(int dldo_num, unsigned int mvolt) +{ + u8 cfg = axp809_mvolt_to_cfg(mvolt, 700, 3300, 100); + int ret; + + if (dldo_num < 1 || dldo_num > 2) + return -EINVAL; + + if (mvolt == 0) + return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2, + AXP809_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1)); + + if (dldo_num == 1 && mvolt > 3300) + cfg += 1 + axp809_mvolt_to_cfg(mvolt, 3400, 4200, 200); + ret = pmic_bus_write(AXP809_DLDO1_CTRL + (dldo_num - 1), cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP809_OUTPUT_CTRL2, + AXP809_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1)); +} + +int axp_set_eldo(int eldo_num, unsigned int mvolt) +{ + int ret; + u8 cfg = axp809_mvolt_to_cfg(mvolt, 700, 3300, 100); + + if (eldo_num < 1 || eldo_num > 3) + return -EINVAL; + + if (mvolt == 0) + return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2, + AXP809_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1)); + + ret = pmic_bus_write(AXP809_ELDO1_CTRL + (eldo_num - 1), cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP809_OUTPUT_CTRL2, + AXP809_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1)); +} + +int axp_set_sw(bool on) +{ + if (on) + return pmic_bus_setbits(AXP809_OUTPUT_CTRL2, + AXP809_OUTPUT_CTRL2_SWOUT_EN); + + return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2, + AXP809_OUTPUT_CTRL2_SWOUT_EN); +} + +int axp_init(void) +{ + int ret; + + ret = pmic_bus_init(); + if (ret) + return ret; + + return 0; +} + +int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + pmic_bus_write(AXP809_SHUTDOWN, AXP809_SHUTDOWN_POWEROFF); + + /* infinite loop during shutdown */ + while (1) {} + + /* not reached */ + return 0; +} diff --git a/include/axp809.h b/include/axp809.h new file mode 100644 index 00000000000..d27fb978d20 --- /dev/null +++ b/include/axp809.h @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2016 Chen-Yu Tsai + * + * X-Powers AXP809 Power Management IC driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define AXP809_CHIP_ID 0x03 + +#define AXP809_OUTPUT_CTRL1 0x10 +#define AXP809_OUTPUT_CTRL1_DC5LDO_EN (1 << 0) +#define AXP809_OUTPUT_CTRL1_DCDC1_EN (1 << 1) +#define AXP809_OUTPUT_CTRL1_DCDC2_EN (1 << 2) +#define AXP809_OUTPUT_CTRL1_DCDC3_EN (1 << 3) +#define AXP809_OUTPUT_CTRL1_DCDC4_EN (1 << 4) +#define AXP809_OUTPUT_CTRL1_DCDC5_EN (1 << 5) +#define AXP809_OUTPUT_CTRL1_ALDO1_EN (1 << 6) +#define AXP809_OUTPUT_CTRL1_ALDO2_EN (1 << 7) +#define AXP809_OUTPUT_CTRL2 0x12 +#define AXP809_OUTPUT_CTRL2_ELDO1_EN (1 << 0) +#define AXP809_OUTPUT_CTRL2_ELDO2_EN (1 << 1) +#define AXP809_OUTPUT_CTRL2_ELDO3_EN (1 << 2) +#define AXP809_OUTPUT_CTRL2_DLDO1_EN (1 << 3) +#define AXP809_OUTPUT_CTRL2_DLDO2_EN (1 << 4) +#define AXP809_OUTPUT_CTRL2_ALDO3_EN (1 << 5) +#define AXP809_OUTPUT_CTRL2_SWOUT_EN (1 << 6) +#define AXP809_OUTPUT_CTRL2_DC1SW_EN (1 << 7) + +#define AXP809_DLDO1_CTRL 0x15 +#define AXP809_DLDO2_CTRL 0x16 +#define AXP809_ELDO1_CTRL 0x19 +#define AXP809_ELDO2_CTRL 0x1a +#define AXP809_ELDO3_CTRL 0x1b +#define AXP809_DC5LDO_CTRL 0x1c +#define AXP809_DCDC1_CTRL 0x21 +#define AXP809_DCDC2_CTRL 0x22 +#define AXP809_DCDC3_CTRL 0x23 +#define AXP809_DCDC4_CTRL 0x24 +#define AXP809_DCDC5_CTRL 0x25 +#define AXP809_ALDO1_CTRL 0x28 +#define AXP809_ALDO2_CTRL 0x29 +#define AXP809_ALDO3_CTRL 0x2a +#define AXP809_SHUTDOWN 0x32 +#define AXP809_SHUTDOWN_POWEROFF (1 << 7) + +/* For axp_gpio.c */ +#define AXP_POWER_STATUS 0x00 +#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_VBUS_IPSOUT 0x30 +#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) +#define AXP_MISC_CTRL 0x8f +#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) +#define AXP_GPIO0_CTRL 0x90 +#define AXP_GPIO1_CTRL 0x92 +#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ +#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ +#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ +#define AXP_GPIO_STATE 0x94 +#define AXP_GPIO_STATE_OFFSET 0 diff --git a/include/axp_pmic.h b/include/axp_pmic.h index 2ed5196354e..d789ad80862 100644 --- a/include/axp_pmic.h +++ b/include/axp_pmic.h @@ -16,6 +16,9 @@ #ifdef CONFIG_AXP221_POWER #include #endif +#ifdef CONFIG_AXP809_POWER +#include +#endif #ifdef CONFIG_AXP818_POWER #include #endif -- cgit v1.3.1 From b19236fd1c1ef289bab9e243ee5b50d658fcac3f Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Sat, 14 May 2016 04:13:26 +0300 Subject: sunxi: Increase SPL header size to 64 bytes to avoid code corruption The current SPL header, created by the 'mksunxiboot' tool, has size 32 bytes. But the code in the boot ROM stores the information about the boot media at the offset 0x28 before passing control to the SPL. For example, when booting from the SD card, the magic number written by the boot ROM is 0. And when booting from the SPI flash, the magic number is 3. NAND and eMMC probably have their own special magic numbers too. Currently the corrupted byte is a part of one of the instructions in the reset vectors table: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt <- Corruption happens here ldr pc, _prefetch_abort ldr pc, _data_abort ldr pc, _not_used ldr pc, _irq ldr pc, _fiq In practice this does not cause any visible problems, but it's still better to fix it. As a bonus, the reported boot media type can be later used in the 'spl_boot_device' function, but this is out of the scope of this patch. Signed-off-by: Siarhei Siamashka Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/include/asm/arch-sunxi/spl.h | 8 +++++++- include/configs/sunxi-common.h | 12 ++++++------ 2 files changed, 13 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h index ca9a4f99ad2..a0f33b05b51 100644 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -18,6 +18,10 @@ #define SPL_ADDR 0x0 #endif +/* The low 8-bits of the 'boot_media' field in the SPL header */ +#define SUNXI_BOOTED_FROM_MMC0 0 +#define SUNXI_BOOTED_FROM_SPI 3 + /* boot head definition from sun4i boot code */ struct boot_file_head { uint32_t b_instruction; /* one intruction jumping to real code */ @@ -45,7 +49,9 @@ struct boot_file_head { uint8_t spl_signature[4]; }; uint32_t fel_script_address; - uint32_t reserved; /* padding, align to 32 bytes */ + uint32_t reserved1[3]; + uint32_t boot_media; /* written here by the boot ROM */ + uint32_t reserved2[5]; /* padding, align to 64 bytes */ }; #define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index ac2d93114b5..12b39589d67 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -189,14 +189,14 @@ #define CONFIG_SPL_BOARD_LOAD_IMAGE #if defined(CONFIG_MACH_SUN9I) -#define CONFIG_SPL_TEXT_BASE 0x10020 /* sram start+header */ -#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* ? KiB on sun9i */ +#define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x5fc0 /* ? KiB on sun9i */ #elif defined(CONFIG_MACH_SUN50I) -#define CONFIG_SPL_TEXT_BASE 0x10020 /* sram start+header */ -#define CONFIG_SPL_MAX_SIZE 0x7fe0 /* 32 KiB on sun50i */ +#define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x7fc0 /* 32 KiB on sun50i */ #else -#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */ -#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */ +#define CONFIG_SPL_TEXT_BASE 0x40 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x5fc0 /* 24KB on sun4i/sun7i */ #endif #define CONFIG_SPL_LIBDISK_SUPPORT -- cgit v1.3.1 From 671f9ad8aa61ac5163bfc8d80f9b707b336b4376 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 4 May 2016 22:15:32 +0100 Subject: arm64: sunxi: adjust default load addresses As arm64 has slightly different expectations about load addresses, lets use a different set of default addresses for things like the kernel. As arm64 kernels don't come with a decompressor right now, reserve some more space for really big uncompressed kernels. Signed-off-by: Andre Przywara Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- include/configs/sunxi-common.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'include') diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 12b39589d67..b33cfb86f82 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -390,6 +390,23 @@ extern int soft_i2c_gpio_scl; #define CONFIG_PRE_CONSOLE_BUFFER #define CONFIG_PRE_CON_BUF_SZ 4096 /* Aprox 2 80*25 screens */ +#ifdef CONFIG_ARM64 +/* + * Boards seem to come with at least 512MB of DRAM. + * The kernel should go at 512K, which is the default text offset (that will + * be adjusted at runtime if needed). + * There is no compression for arm64 kernels (yet), so leave some space + * for really big kernels, say 256MB for now. + * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd. + * Align the initrd to a 2MB page. + */ +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000)) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) + +#else /* * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, @@ -401,6 +418,7 @@ extern int soft_i2c_gpio_scl; #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000)) +#endif #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0xa000000\0" \ -- cgit v1.3.1 From 2e7eb12e5c81dedaff12b0cea2341dc681d8c726 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 17 May 2016 07:43:27 +0100 Subject: malta: Tidy up UART address selection The address of the UART differs based upon the system controller because it's actually within the I/O port region, which is in a different location for each system controller. Rather than handling this as 2 UARTs with the correct one selected at runtime, use I/O port accessors for the UART such that access to it gets translated into the I/O port region automatically. Signed-off-by: Paul Burton Reviewed-by: Daniel Schwierzeck --- board/imgtec/malta/malta.c | 13 ------------- include/configs/malta.h | 4 ++-- 2 files changed, 2 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 3a9e7807c69..495504372a0 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include @@ -161,18 +160,6 @@ int misc_init_r(void) return 0; } -struct serial_device *default_serial_console(void) -{ - switch (malta_sys_con()) { - case SYSCON_GT64120: - return &eserial1_device; - - default: - case SYSCON_MSC01: - return &eserial2_device; - } -} - void pci_init_board(void) { pci_dev_t bdf; diff --git a/include/configs/malta.h b/include/configs/malta.h index 04dca710366..1c3c83c25eb 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -67,10 +67,10 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_PORT_MAPPED #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (115200 * 16) -#define CONFIG_SYS_NS16550_COM1 0xb80003f8 -#define CONFIG_SYS_NS16550_COM2 0xbb0003f8 +#define CONFIG_SYS_NS16550_COM1 0x3f8 #define CONFIG_CONS_INDEX 1 /* -- cgit v1.3.1 From 6242aa137427f6da6ca47e7a8c9a9f78ad63e00d Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 17 May 2016 07:43:28 +0100 Subject: malta: Use device model & tree for UART Make use of device model & device tree to probe the UART driver. This is the initial step in bringing Malta up to date with driver model, and allows for cleaner handling of the different I/O addresses for different system controllers by specifying the ISA bus address instead of a translated memory address. Signed-off-by: Paul Burton Reviewed-by: Daniel Schwierzeck --- arch/mips/Kconfig | 4 ++++ arch/mips/dts/Makefile | 1 + arch/mips/dts/mti,malta.dts | 32 ++++++++++++++++++++++++++++++++ configs/malta_defconfig | 2 ++ configs/maltael_defconfig | 2 ++ include/configs/malta.h | 6 ------ 6 files changed, 41 insertions(+), 6 deletions(-) create mode 100644 arch/mips/dts/mti,malta.dts (limited to 'include') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index dc34c18258c..53363e38fe4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -23,7 +23,11 @@ config TARGET_QEMU_MIPS config TARGET_MALTA bool "Support malta" + select DM + select DM_SERIAL select DYNAMIC_IO_PORT_BASE + select OF_CONTROL + select OF_ISA_BUS select SUPPORTS_BIG_ENDIAN select SUPPORTS_LITTLE_ENDIAN select SUPPORTS_CPU_MIPS32_R1 diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index a94b7455507..2f04d73b83f 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -4,6 +4,7 @@ dtb-$(CONFIG_TARGET_AP121) += ap121.dtb dtb-$(CONFIG_TARGET_AP143) += ap143.dtb +dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb diff --git a/arch/mips/dts/mti,malta.dts b/arch/mips/dts/mti,malta.dts new file mode 100644 index 00000000000..d339229c2a8 --- /dev/null +++ b/arch/mips/dts/mti,malta.dts @@ -0,0 +1,32 @@ +/dts-v1/; + +/memreserve/ 0x00000000 0x00001000; /* Exception vectors */ +/memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mti,malta"; + + chosen { + stdout-path = &uart0; + }; + + isa@0 { + compatible = "isa"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0 0x1000>; + + uart0: serial@3f8 { + compatible = "ns16550a"; + + reg = <1 0x3f8 0x40>; + reg-shift = <0>; + + clock-frequency = <1843200>; + + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/configs/malta_defconfig b/configs/malta_defconfig index a16f10be6a0..3c3bb165224 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -1,5 +1,6 @@ CONFIG_MIPS=y CONFIG_TARGET_MALTA=y +CONFIG_DEFAULT_DEVICE_TREE="mti,malta" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="malta # " # CONFIG_CMD_LOADB is not set @@ -9,5 +10,6 @@ CONFIG_SYS_PROMPT="malta # " CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_PING=y +CONFIG_OF_EMBED=y CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index 52897977487..b245d915ef7 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -1,6 +1,7 @@ CONFIG_MIPS=y CONFIG_TARGET_MALTA=y CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_DEFAULT_DEVICE_TREE="mti,malta" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="maltael # " # CONFIG_CMD_LOADB is not set @@ -10,5 +11,6 @@ CONFIG_SYS_PROMPT="maltael # " CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_PING=y +CONFIG_OF_EMBED=y CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/malta.h b/include/configs/malta.h index 1c3c83c25eb..e03935b5732 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -65,13 +65,7 @@ * Serial driver */ #define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_PORT_MAPPED -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (115200 * 16) -#define CONFIG_SYS_NS16550_COM1 0x3f8 -#define CONFIG_CONS_INDEX 1 /* * Flash configuration -- cgit v1.3.1 From ec35e12331512cf5ed0f22005d7b6fb4ccc35969 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 17 May 2016 11:56:39 +0100 Subject: MIPS: Move CONFIG_SYS_TEXT_BASE to Kconfig Move CONFIG_SYS_TEXT_BASE to Kconfig, and add default values in board Kconfig files matching what was present in their config headers. This will make it cleaner to conditionalise the value for Malta based on 32 vs 64 bit builds. Signed-off-by: Paul Burton --- Kconfig | 2 +- board/dbau1x00/Kconfig | 3 +++ board/imgtec/malta/Kconfig | 3 +++ board/microchip/pic32mzda/Kconfig | 3 +++ board/micronas/vct/Kconfig | 3 +++ board/pb1x00/Kconfig | 3 +++ board/qca/ap121/Kconfig | 3 +++ board/qca/ap143/Kconfig | 3 +++ board/qemu-mips/Kconfig | 4 ++++ board/tplink/wdr4300/Kconfig | 3 +++ include/configs/ap121.h | 2 -- include/configs/ap143.h | 2 -- include/configs/dbau1x00.h | 6 ------ include/configs/malta.h | 1 - include/configs/pb1x00.h | 6 ------ include/configs/pic32mzdask.h | 1 - include/configs/qemu-mips.h | 1 - include/configs/qemu-mips64.h | 1 - include/configs/tplink_wdr4300.h | 2 -- include/configs/vct.h | 1 - 20 files changed, 29 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/Kconfig b/Kconfig index f53759a48e1..4b462166656 100644 --- a/Kconfig +++ b/Kconfig @@ -268,7 +268,7 @@ config SYS_EXTRA_OPTIONS config SYS_TEXT_BASE depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \ - (M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE + (M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS depends on !EFI_APP hex "Text Base" help diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig index b813adb840d..342ec59cb73 100644 --- a/board/dbau1x00/Kconfig +++ b/board/dbau1x00/Kconfig @@ -9,6 +9,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "dbau1x00" +config SYS_TEXT_BASE + default 0xbfc00000 + menu "dbau1x00 board options" choice diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig index 4c06d0c0d80..2bb8e8be16e 100644 --- a/board/imgtec/malta/Kconfig +++ b/board/imgtec/malta/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "malta" +config SYS_TEXT_BASE + default 0xbe000000 + endif diff --git a/board/microchip/pic32mzda/Kconfig b/board/microchip/pic32mzda/Kconfig index 8acb3933698..4f08e98b97a 100644 --- a/board/microchip/pic32mzda/Kconfig +++ b/board/microchip/pic32mzda/Kconfig @@ -10,4 +10,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "pic32mzdask" +config SYS_TEXT_BASE + default 0x9d004000 + endif diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig index c518079efac..535a77b2a32 100644 --- a/board/micronas/vct/Kconfig +++ b/board/micronas/vct/Kconfig @@ -9,6 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "vct" +config SYS_TEXT_BASE + default 0x87000000 + menu "vct board options" choice diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig index 251db6ab637..236a4108bfc 100644 --- a/board/pb1x00/Kconfig +++ b/board/pb1x00/Kconfig @@ -9,4 +9,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "pb1x00" +config SYS_TEXT_BASE + default 0x83800000 + endif diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig index f7e768ad586..c3ecc8f62ff 100644 --- a/board/qca/ap121/Kconfig +++ b/board/qca/ap121/Kconfig @@ -9,4 +9,7 @@ config SYS_BOARD config SYS_CONFIG_NAME default "ap121" +config SYS_TEXT_BASE + default 0x9f000000 + endif diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig index 4cdac0d06d0..5ea5d6fbb02 100644 --- a/board/qca/ap143/Kconfig +++ b/board/qca/ap143/Kconfig @@ -9,4 +9,7 @@ config SYS_BOARD config SYS_CONFIG_NAME default "ap143" +config SYS_TEXT_BASE + default 0x9f000000 + endif diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig index 18d78b51008..3de1f44a3da 100644 --- a/board/qemu-mips/Kconfig +++ b/board/qemu-mips/Kconfig @@ -7,4 +7,8 @@ config SYS_CONFIG_NAME default "qemu-mips" if 32BIT default "qemu-mips64" if 64BIT +config SYS_TEXT_BASE + default 0xbfc00000 if 32BIT + default 0xffffffffbfc00000 if 64BIT + endif diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig index 902abf560d1..65785bdb9c7 100644 --- a/board/tplink/wdr4300/Kconfig +++ b/board/tplink/wdr4300/Kconfig @@ -12,4 +12,7 @@ config SYS_BOARD config SYS_CONFIG_NAME default "tplink_wdr4300" +config SYS_TEXT_BASE + default 0xa1000000 + endif diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 2beffa4805b..6f69f31503c 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_TEXT_BASE 0x9f000000 - #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 7b69e10be44..f907c02af92 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_TEXT_BASE 0x9f000000 - #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index eb0a87cd592..68d9e36b19c 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -139,12 +139,6 @@ #define CONFIG_SYS_FLASH_CFI 1 #define CONFIG_FLASH_CFI_DRIVER 1 -/* The following #defines are needed to get flash environment right */ -/* ROM version */ -#define CONFIG_SYS_TEXT_BASE 0xbfc00000 -/* RAM version */ -/* #define CONFIG_SYS_TEXT_BASE 0x80100000 */ - #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (192 << 10) diff --git a/include/configs/malta.h b/include/configs/malta.h index e03935b5732..a36967848c5 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -37,7 +37,6 @@ /* * Memory map */ -#define CONFIG_SYS_TEXT_BASE 0xbe000000 /* Rom version */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index caf75a6b262..869768add05 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -80,12 +80,6 @@ #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ -/* The following #defines are needed to get flash environment right */ -/* ROM version */ -/* #define CONFIG_SYS_TEXT_BASE 0xbfc00000 */ -/* SDRAM version */ -#define CONFIG_SYS_TEXT_BASE 0x83800000 - #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (192 << 10) diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 108c6a2d62f..fb2e41fd92e 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -10,7 +10,6 @@ #define __PIC32MZDASK_CONFIG_H /* System Configuration */ -#define CONFIG_SYS_TEXT_BASE 0x9d004000 /* .text */ #define CONFIG_DISPLAY_BOARDINFO /*-------------------------------------------- diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 702967c4e8e..246ee0173a7 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -107,7 +107,6 @@ * FLASH and environment organization */ /* The following #defines are needed to get flash environment right */ -#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (192 << 10) diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index 239454984ae..60a3a71fbdc 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -107,7 +107,6 @@ * FLASH and environment organization */ /* The following #defines are needed to get flash environment right */ -#define CONFIG_SYS_TEXT_BASE 0xffffffffbfc00000 /* Rom version */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (192 << 10) diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 2b9e92ed2b1..09a69fec09d 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_TEXT_BASE 0xa1000000 - #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/vct.h b/include/configs/vct.h index 6489e08173c..68eb0893948 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -32,7 +32,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */ -#define CONFIG_SYS_TEXT_BASE 0x87000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) #define CONFIG_SYS_MALLOC_LEN (1 << 20) -- cgit v1.3.1 From 086e13c5f6f79a68246d6b803cf4736cb6815e44 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 1 May 2016 00:36:12 +0200 Subject: ARM: exynos: Disable serial support in SPL The exynos5 platforms use DM in U-Boot and do not use DM in SPL. The serial driver, serial_s5p.c, is DM-only. This is OK for U-Boot, but in SPL, this will fail with the following compile error: drivers/built-in.o: In function `get_current': ...u-boot/drivers/serial/serial.c:387: undefined reference to `default_serial_console' This warning happens because common/console.c is compiled into U-Boot SPL if CONFIG_SPL_SERIAL_SUPPORT . The common/console.c invokes serial_*() functions and since exynos5 does not use DM in SPL, these functions come from drivers/serial/serial.c . The serial_*() locate default serial port by calling default_serial_console(), but because the serial_s5p.c is DM-only, it does no longer define default_serial_console(). Thus the error. Signed-off-by: Marek Vasut Cc: Simon Glass Cc: Tom Rini Reviewed-by: Simon Glass Signed-off-by: Minkyu Kang --- include/configs/exynos5-common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 311fd09d6bc..061cac4227f 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -60,7 +60,6 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT /* specific .lds file */ -- cgit v1.3.1 From daac3bfee57247013cb8373683e9babb191abd75 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 11 May 2016 15:26:24 -0600 Subject: dm: allow setting driver_data before/during bind This will allow a driver's bind function to use the driver data. One example is the Tegra186 GPIO driver, which instantiates child devices for each of its GPIO ports, yet supports two different HW instances each with a different set of ports, and identified by the udevice_id .data field. Signed-off-by: Stephen Warren Acked-by: Simon Glass --- doc/driver-model/README.txt | 23 ++++++++++++++--------- drivers/core/device.c | 25 ++++++++++++++++++++++--- drivers/core/lists.c | 4 ++-- include/dm/device-internal.h | 24 ++++++++++++++++++++++++ 4 files changed, 62 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt index 7a24552560d..1b5ccec4b2e 100644 --- a/doc/driver-model/README.txt +++ b/doc/driver-model/README.txt @@ -606,19 +606,24 @@ methods actually defined. 1. Bind stage -A device and its driver are bound using one of these two methods: +U-Boot discovers devices using one of these two methods: - - Scan the U_BOOT_DEVICE() definitions. U-Boot It looks up the -name specified by each, to find the appropriate driver. It then calls -device_bind() to create a new device and bind' it to its driver. This will -call the device's bind() method. + - Scan the U_BOOT_DEVICE() definitions. U-Boot looks up the name specified +by each, to find the appropriate U_BOOT_DRIVER() definition. In this case, +there is no path by which driver_data may be provided, but the U_BOOT_DEVICE() +may provide platdata. - Scan through the device tree definitions. U-Boot looks at top-level nodes in the the device tree. It looks at the compatible string in each node -and uses the of_match part of the U_BOOT_DRIVER() structure to find the -right driver for each node. It then calls device_bind() to bind the -newly-created device to its driver (thereby creating a device structure). -This will also call the device's bind() method. +and uses the of_match table of the U_BOOT_DRIVER() structure to find the +right driver for each node. In this case, the of_match table may provide a +driver_data value, but platdata cannot be provided until later. + +For each device that is discovered, U-Boot then calls device_bind() to create a +new device, initializes various core fields of the device object such as name, +uclass & driver, initializes any optional fields of the device object that are +applicable such as of_offset, driver_data & platdata, and finally calls the +driver's bind() method if one is defined. At this point all the devices are known, and bound to their drivers. There is a 'struct udevice' allocated for all devices. However, nothing has been diff --git a/drivers/core/device.c b/drivers/core/device.c index 45d5e3e12c0..eb75b1734f9 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -26,9 +26,10 @@ DECLARE_GLOBAL_DATA_PTR; -int device_bind(struct udevice *parent, const struct driver *drv, - const char *name, void *platdata, int of_offset, - struct udevice **devp) +static int device_bind_common(struct udevice *parent, const struct driver *drv, + const char *name, void *platdata, + ulong driver_data, int of_offset, + struct udevice **devp) { struct udevice *dev; struct uclass *uc; @@ -56,6 +57,7 @@ int device_bind(struct udevice *parent, const struct driver *drv, INIT_LIST_HEAD(&dev->devres_head); #endif dev->platdata = platdata; + dev->driver_data = driver_data; dev->name = name; dev->of_offset = of_offset; dev->parent = parent; @@ -193,6 +195,23 @@ fail_alloc1: return ret; } +int device_bind_with_driver_data(struct udevice *parent, + const struct driver *drv, const char *name, + ulong driver_data, int of_offset, + struct udevice **devp) +{ + return device_bind_common(parent, drv, name, NULL, driver_data, + of_offset, devp); +} + +int device_bind(struct udevice *parent, const struct driver *drv, + const char *name, void *platdata, int of_offset, + struct udevice **devp) +{ + return device_bind_common(parent, drv, name, platdata, 0, of_offset, + devp); +} + int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, const struct driver_info *info, struct udevice **devp) { diff --git a/drivers/core/lists.c b/drivers/core/lists.c index a72db13a119..0c277177909 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -170,7 +170,8 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, } dm_dbg(" - found match at '%s'\n", entry->name); - ret = device_bind(parent, entry, name, NULL, offset, &dev); + ret = device_bind_with_driver_data(parent, entry, name, + id->data, offset, &dev); if (ret == -ENODEV) { dm_dbg("Driver '%s' refuses to bind\n", entry->name); continue; @@ -180,7 +181,6 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, ret); return ret; } else { - dev->driver_data = id->data; found = true; if (devp) *devp = dev; diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index b348ad5231b..0bf8707493a 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -38,6 +38,30 @@ int device_bind(struct udevice *parent, const struct driver *drv, const char *name, void *platdata, int of_offset, struct udevice **devp); +/** + * device_bind_with_driver_data() - Create a device and bind it to a driver + * + * Called to set up a new device attached to a driver, in the case where the + * driver was matched to the device by means of a match table that provides + * driver_data. + * + * Once bound a device exists but is not yet active until device_probe() is + * called. + * + * @parent: Pointer to device's parent, under which this driver will exist + * @drv: Device's driver + * @name: Name of device (e.g. device tree node name) + * @driver_data: The driver_data field from the driver's match table. + * @of_offset: Offset of device tree node for this device. This is -1 for + * devices which don't use device tree. + * @devp: if non-NULL, returns a pointer to the bound device + * @return 0 if OK, -ve on error + */ +int device_bind_with_driver_data(struct udevice *parent, + const struct driver *drv, const char *name, + ulong driver_data, int of_offset, + struct udevice **devp); + /** * device_bind_by_name: Create a device and bind it to a driver * -- cgit v1.3.1 From 11636258981a083957c19f3979796fde5e7e8080 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 12 May 2016 12:03:35 -0600 Subject: Rename reset to sysreset The current reset API implements a method to reset the entire system. In the near future, I'd like to introduce code that implements the device tree reset bindings; i.e. the equivalent of the Linux kernel's reset API. This controls resets to individual HW blocks or external chips with reset signals. It doesn't make sense to merge the two APIs into one since they have different semantic purposes. Resolve the naming conflict by renaming the existing reset API to sysreset instead, so the new reset API can be called just reset. Signed-off-by: Stephen Warren Acked-by: Simon Glass --- arch/arm/lib/Makefile | 2 +- arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 20 +++--- arch/arm/mach-rockchip/rk3288/reset_rk3288.c | 20 +++--- arch/arm/mach-snapdragon/reset.c | 18 ++--- arch/sandbox/cpu/state.c | 4 +- arch/sandbox/include/asm/state.h | 6 +- configs/chromebook_jerry_defconfig | 2 +- configs/dragonboard410c_defconfig | 2 +- configs/evb-rk3036_defconfig | 2 +- configs/firefly-rk3288_defconfig | 2 +- configs/kylin-rk3036_defconfig | 2 +- configs/rock2_defconfig | 2 +- configs/sandbox_defconfig | 2 +- configs/sandbox_noblk_defconfig | 2 +- drivers/clk/clk_rk3036.c | 2 +- drivers/clk/clk_rk3288.c | 2 +- drivers/misc/Kconfig | 10 +-- drivers/misc/Makefile | 4 +- drivers/misc/reset-uclass.c | 81 --------------------- drivers/misc/reset_sandbox.c | 100 -------------------------- drivers/misc/sysreset-uclass.c | 81 +++++++++++++++++++++ drivers/misc/sysreset_sandbox.c | 101 +++++++++++++++++++++++++++ include/dm/uclass-id.h | 2 +- include/reset.h | 71 ------------------- include/sysreset.h | 71 +++++++++++++++++++ test/dm/Makefile | 2 +- test/dm/reset.c | 74 -------------------- test/dm/sysreset.c | 74 ++++++++++++++++++++ 28 files changed, 381 insertions(+), 380 deletions(-) delete mode 100644 drivers/misc/reset-uclass.c delete mode 100644 drivers/misc/reset_sandbox.c create mode 100644 drivers/misc/sysreset-uclass.c create mode 100644 drivers/misc/sysreset_sandbox.c delete mode 100644 include/reset.h create mode 100644 include/sysreset.h delete mode 100644 test/dm/reset.c create mode 100644 test/dm/sysreset.c (limited to 'include') diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 7a0fb5862e1..b535dbef49a 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -46,7 +46,7 @@ obj-y += interrupts_64.o else obj-y += interrupts.o endif -ifndef CONFIG_RESET +ifndef CONFIG_SYSRESET obj-y += reset.o endif diff --git a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c index fefb568f7ae..b3d21132399 100644 --- a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c @@ -7,24 +7,24 @@ #include #include #include -#include +#include #include #include #include #include #include -int rk3036_reset_request(struct udevice *dev, enum reset_t type) +int rk3036_sysreset_request(struct udevice *dev, enum sysreset_t type) { struct rk3036_cru *cru = rockchip_get_cru(); if (IS_ERR(cru)) return PTR_ERR(cru); switch (type) { - case RESET_WARM: + case SYSRESET_WARM: writel(0xeca8, &cru->cru_glb_srst_snd_value); break; - case RESET_COLD: + case SYSRESET_COLD: writel(0xfdb9, &cru->cru_glb_srst_fst_value); break; default: @@ -34,12 +34,12 @@ int rk3036_reset_request(struct udevice *dev, enum reset_t type) return -EINPROGRESS; } -static struct reset_ops rk3036_reset = { - .request = rk3036_reset_request, +static struct sysreset_ops rk3036_sysreset = { + .request = rk3036_sysreset_request, }; -U_BOOT_DRIVER(reset_rk3036) = { - .name = "rk3036_reset", - .id = UCLASS_RESET, - .ops = &rk3036_reset, +U_BOOT_DRIVER(sysreset_rk3036) = { + .name = "rk3036_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3036_sysreset, }; diff --git a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c index bf7540a5d24..0aad1c21601 100644 --- a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c @@ -7,25 +7,25 @@ #include #include #include -#include +#include #include #include #include #include #include -int rk3288_reset_request(struct udevice *dev, enum reset_t type) +int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type) { struct rk3288_cru *cru = rockchip_get_cru(); if (IS_ERR(cru)) return PTR_ERR(cru); switch (type) { - case RESET_WARM: + case SYSRESET_WARM: rk_clrreg(&cru->cru_mode_con, 0xffff); writel(0xeca8, &cru->cru_glb_srst_snd_value); break; - case RESET_COLD: + case SYSRESET_COLD: rk_clrreg(&cru->cru_mode_con, 0xffff); writel(0xfdb9, &cru->cru_glb_srst_fst_value); break; @@ -36,12 +36,12 @@ int rk3288_reset_request(struct udevice *dev, enum reset_t type) return -EINPROGRESS; } -static struct reset_ops rk3288_reset = { - .request = rk3288_reset_request, +static struct sysreset_ops rk3288_sysreset = { + .request = rk3288_sysreset_request, }; -U_BOOT_DRIVER(reset_rk3288) = { - .name = "rk3288_reset", - .id = UCLASS_RESET, - .ops = &rk3288_reset, +U_BOOT_DRIVER(sysreset_rk3288) = { + .name = "rk3288_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3288_sysreset, }; diff --git a/arch/arm/mach-snapdragon/reset.c b/arch/arm/mach-snapdragon/reset.c index 2627eec1815..a6cabfb8b01 100644 --- a/arch/arm/mach-snapdragon/reset.c +++ b/arch/arm/mach-snapdragon/reset.c @@ -9,12 +9,12 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; -static int msm_reset_request(struct udevice *dev, enum reset_t type) +static int msm_sysreset_request(struct udevice *dev, enum sysreset_t type) { phys_addr_t addr = dev_get_addr(dev); if (!addr) @@ -23,18 +23,18 @@ static int msm_reset_request(struct udevice *dev, enum reset_t type) return -EINPROGRESS; } -static struct reset_ops msm_reset_ops = { - .request = msm_reset_request, +static struct sysreset_ops msm_sysreset_ops = { + .request = msm_sysreset_request, }; -static const struct udevice_id msm_reset_ids[] = { +static const struct udevice_id msm_sysreset_ids[] = { { .compatible = "qcom,pshold" }, { } }; U_BOOT_DRIVER(msm_reset) = { - .name = "msm_reset", - .id = UCLASS_RESET, - .of_match = msm_reset_ids, - .ops = &msm_reset_ops, + .name = "msm_sysreset", + .id = UCLASS_SYSRESET, + .of_match = msm_sysreset_ids, + .ops = &msm_sysreset_ops, }; diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index d2a7dc9b450..2b4dbd341ff 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -360,8 +360,8 @@ int state_init(void) assert(state->ram_buf); /* No reset yet, so mark it as such. Always allow power reset */ - state->last_reset = RESET_COUNT; - state->reset_allowed[RESET_POWER] = true; + state->last_sysreset = SYSRESET_COUNT; + state->sysreset_allowed[SYSRESET_POWER] = true; /* * Example of how to use GPIOs: diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 11856c2fede..149f28d8732 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -7,7 +7,7 @@ #define __SANDBOX_STATE_H #include -#include +#include #include #include @@ -60,8 +60,8 @@ struct sandbox_state { bool write_state; /* Write sandbox state on exit */ bool ignore_missing_state_on_read; /* No error if state missing */ bool show_lcd; /* Show LCD on start-up */ - enum reset_t last_reset; /* Last reset type */ - bool reset_allowed[RESET_COUNT]; /* Allowed reset types */ + enum sysreset_t last_sysreset; /* Last system reset type */ + bool sysreset_allowed[SYSRESET_COUNT]; /* Allowed system reset types */ enum state_terminal_raw term_raw; /* Terminal raw/cooked */ bool skip_delays; /* Ignore any time delays (for test) */ bool show_test_output; /* Don't suppress stdout in tests */ diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 25ead92778c..d5bc5153b1b 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 2566ded58a4..37c5ea7761c 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -23,7 +23,7 @@ CONFIG_MSM_GPIO=y CONFIG_PM8916_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_MSM_SDHCI=y CONFIG_DM_PMIC=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 4dd45862434..9894fffcca2 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -28,7 +28,7 @@ CONFIG_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 0995f9b329f..0cbc5398488 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -40,7 +40,7 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 50fbe654bf6..0ff6c6b9a4a 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -28,7 +28,7 @@ CONFIG_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index fd32fb521eb..3e16b805caa 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -38,7 +38,7 @@ CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 9e4a92dd6c0..6e30c5df8b6 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -97,7 +97,7 @@ CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_SANDBOX_MMC=y CONFIG_SPI_FLASH_SANDBOX=y diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig index 93167c2f65d..60c73398db4 100644 --- a/configs/sandbox_noblk_defconfig +++ b/configs/sandbox_noblk_defconfig @@ -94,7 +94,7 @@ CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH_SANDBOX=y CONFIG_SPI_FLASH=y diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c index bd5f22a753a..7ec65bdff02 100644 --- a/drivers/clk/clk_rk3036.c +++ b/drivers/clk/clk_rk3036.c @@ -407,7 +407,7 @@ static int rk3036_clk_bind(struct udevice *dev) } /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "rk3036_reset", "reset", &dev); + ret = device_bind_driver(gd->dm_root, "rk3036_sysreset", "reset", &dev); if (ret) debug("Warning: No RK3036 reset driver: ret=%d\n", ret); diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c index 2a85e93a6cc..e763a1c8e91 100644 --- a/drivers/clk/clk_rk3288.c +++ b/drivers/clk/clk_rk3288.c @@ -877,7 +877,7 @@ static int rk3288_clk_bind(struct udevice *dev) } /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "rk3288_reset", "reset", &dev); + ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev); if (ret) debug("Warning: No RK3288 reset driver: ret=%d\n", ret); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index c40f6b577f3..2373037685c 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -121,13 +121,13 @@ config PCA9551_I2C_ADDR help The I2C address of the PCA9551 LED controller. -config RESET - bool "Enable support for reset drivers" +config SYSRESET + bool "Enable support for system reset drivers" depends on DM help - Enable reset drivers which can be used to reset the CPU or board. - Each driver can provide a reset method which will be called to - effect a reset. The uclass will try all available drivers when + Enable system reset drivers which can be used to reset the CPU or + board. Each driver can provide a reset method which will be called + to effect a reset. The uclass will try all available drivers when reset_walk() is called. config WINBOND_W83627 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 98704f2085d..066639ba1f1 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -27,7 +27,7 @@ obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o obj-$(CONFIG_NS87308) += ns87308.o obj-$(CONFIG_PDSP188x) += pdsp188x.o obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o -obj-$(CONFIG_SANDBOX) += reset_sandbox.o +obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o ifdef CONFIG_DM_I2C obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o endif @@ -40,7 +40,7 @@ obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o -obj-$(CONFIG_RESET) += reset-uclass.o +obj-$(CONFIG_SYSRESET) += sysreset-uclass.o obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o obj-$(CONFIG_QFW) += qfw.o diff --git a/drivers/misc/reset-uclass.c b/drivers/misc/reset-uclass.c deleted file mode 100644 index fdb5c6fcff3..00000000000 --- a/drivers/misc/reset-uclass.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2015 Google, Inc - * Written by Simon Glass - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int reset_request(struct udevice *dev, enum reset_t type) -{ - struct reset_ops *ops = reset_get_ops(dev); - - if (!ops->request) - return -ENOSYS; - - return ops->request(dev, type); -} - -int reset_walk(enum reset_t type) -{ - struct udevice *dev; - int ret = -ENOSYS; - - while (ret != -EINPROGRESS && type < RESET_COUNT) { - for (uclass_first_device(UCLASS_RESET, &dev); - dev; - uclass_next_device(&dev)) { - ret = reset_request(dev, type); - if (ret == -EINPROGRESS) - break; - } - type++; - } - - return ret; -} - -void reset_walk_halt(enum reset_t type) -{ - int ret; - - ret = reset_walk(type); - - /* Wait for the reset to take effect */ - if (ret == -EINPROGRESS) - mdelay(100); - - /* Still no reset? Give up */ - printf("Reset not supported on this platform\n"); - hang(); -} - -/** - * reset_cpu() - calls reset_walk(RESET_WARM) - */ -void reset_cpu(ulong addr) -{ - reset_walk_halt(RESET_WARM); -} - - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - reset_walk_halt(RESET_WARM); - - return 0; -} - -UCLASS_DRIVER(reset) = { - .id = UCLASS_RESET, - .name = "reset", -}; diff --git a/drivers/misc/reset_sandbox.c b/drivers/misc/reset_sandbox.c deleted file mode 100644 index 2691bb031a5..00000000000 --- a/drivers/misc/reset_sandbox.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2015 Google, Inc - * Written by Simon Glass - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static int sandbox_warm_reset_request(struct udevice *dev, enum reset_t type) -{ - struct sandbox_state *state = state_get_current(); - - switch (type) { - case RESET_WARM: - state->last_reset = type; - break; - default: - return -ENOSYS; - } - if (!state->reset_allowed[type]) - return -EACCES; - - return -EINPROGRESS; -} - -static int sandbox_reset_request(struct udevice *dev, enum reset_t type) -{ - struct sandbox_state *state = state_get_current(); - - /* - * If we have a device tree, the device we created from platform data - * (see the U_BOOT_DEVICE() declaration below) should not do anything. - * If we are that device, return an error. - */ - if (state->fdt_fname && dev->of_offset == -1) - return -ENODEV; - - switch (type) { - case RESET_COLD: - state->last_reset = type; - break; - case RESET_POWER: - state->last_reset = type; - if (!state->reset_allowed[type]) - return -EACCES; - sandbox_exit(); - break; - default: - return -ENOSYS; - } - if (!state->reset_allowed[type]) - return -EACCES; - - return -EINPROGRESS; -} - -static struct reset_ops sandbox_reset_ops = { - .request = sandbox_reset_request, -}; - -static const struct udevice_id sandbox_reset_ids[] = { - { .compatible = "sandbox,reset" }, - { } -}; - -U_BOOT_DRIVER(reset_sandbox) = { - .name = "reset_sandbox", - .id = UCLASS_RESET, - .of_match = sandbox_reset_ids, - .ops = &sandbox_reset_ops, -}; - -static struct reset_ops sandbox_warm_reset_ops = { - .request = sandbox_warm_reset_request, -}; - -static const struct udevice_id sandbox_warm_reset_ids[] = { - { .compatible = "sandbox,warm-reset" }, - { } -}; - -U_BOOT_DRIVER(warm_reset_sandbox) = { - .name = "warm_reset_sandbox", - .id = UCLASS_RESET, - .of_match = sandbox_warm_reset_ids, - .ops = &sandbox_warm_reset_ops, -}; - -/* This is here in case we don't have a device tree */ -U_BOOT_DEVICE(reset_sandbox_non_fdt) = { - .name = "reset_sandbox", -}; diff --git a/drivers/misc/sysreset-uclass.c b/drivers/misc/sysreset-uclass.c new file mode 100644 index 00000000000..e41efcaca60 --- /dev/null +++ b/drivers/misc/sysreset-uclass.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct sysreset_ops *ops = sysreset_get_ops(dev); + + if (!ops->request) + return -ENOSYS; + + return ops->request(dev, type); +} + +int sysreset_walk(enum sysreset_t type) +{ + struct udevice *dev; + int ret = -ENOSYS; + + while (ret != -EINPROGRESS && type < SYSRESET_COUNT) { + for (uclass_first_device(UCLASS_SYSRESET, &dev); + dev; + uclass_next_device(&dev)) { + ret = sysreset_request(dev, type); + if (ret == -EINPROGRESS) + break; + } + type++; + } + + return ret; +} + +void sysreset_walk_halt(enum sysreset_t type) +{ + int ret; + + ret = sysreset_walk(type); + + /* Wait for the reset to take effect */ + if (ret == -EINPROGRESS) + mdelay(100); + + /* Still no reset? Give up */ + printf("System reset not supported on this platform\n"); + hang(); +} + +/** + * reset_cpu() - calls sysreset_walk(SYSRESET_WARM) + */ +void reset_cpu(ulong addr) +{ + sysreset_walk_halt(SYSRESET_WARM); +} + + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + sysreset_walk_halt(SYSRESET_WARM); + + return 0; +} + +UCLASS_DRIVER(sysreset) = { + .id = UCLASS_SYSRESET, + .name = "sysreset", +}; diff --git a/drivers/misc/sysreset_sandbox.c b/drivers/misc/sysreset_sandbox.c new file mode 100644 index 00000000000..7ae7f386ee0 --- /dev/null +++ b/drivers/misc/sysreset_sandbox.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int sandbox_warm_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ + struct sandbox_state *state = state_get_current(); + + switch (type) { + case SYSRESET_WARM: + state->last_sysreset = type; + break; + default: + return -ENOSYS; + } + if (!state->sysreset_allowed[type]) + return -EACCES; + + return -EINPROGRESS; +} + +static int sandbox_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct sandbox_state *state = state_get_current(); + + /* + * If we have a device tree, the device we created from platform data + * (see the U_BOOT_DEVICE() declaration below) should not do anything. + * If we are that device, return an error. + */ + if (state->fdt_fname && dev->of_offset == -1) + return -ENODEV; + + switch (type) { + case SYSRESET_COLD: + state->last_sysreset = type; + break; + case SYSRESET_POWER: + state->last_sysreset = type; + if (!state->sysreset_allowed[type]) + return -EACCES; + sandbox_exit(); + break; + default: + return -ENOSYS; + } + if (!state->sysreset_allowed[type]) + return -EACCES; + + return -EINPROGRESS; +} + +static struct sysreset_ops sandbox_sysreset_ops = { + .request = sandbox_sysreset_request, +}; + +static const struct udevice_id sandbox_sysreset_ids[] = { + { .compatible = "sandbox,reset" }, + { } +}; + +U_BOOT_DRIVER(sysreset_sandbox) = { + .name = "sysreset_sandbox", + .id = UCLASS_SYSRESET, + .of_match = sandbox_sysreset_ids, + .ops = &sandbox_sysreset_ops, +}; + +static struct sysreset_ops sandbox_warm_sysreset_ops = { + .request = sandbox_warm_sysreset_request, +}; + +static const struct udevice_id sandbox_warm_sysreset_ids[] = { + { .compatible = "sandbox,warm-reset" }, + { } +}; + +U_BOOT_DRIVER(warm_sysreset_sandbox) = { + .name = "warm_sysreset_sandbox", + .id = UCLASS_SYSRESET, + .of_match = sandbox_warm_sysreset_ids, + .ops = &sandbox_warm_sysreset_ops, +}; + +/* This is here in case we don't have a device tree */ +U_BOOT_DEVICE(sysreset_sandbox_non_fdt) = { + .name = "sysreset_sandbox", +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index a5cf6e201c0..f9ff45e010f 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -61,7 +61,6 @@ enum uclass_id { UCLASS_PWM, /* Pulse-width modulator */ UCLASS_PWRSEQ, /* Power sequence device */ UCLASS_REGULATOR, /* Regulator device */ - UCLASS_RESET, /* Reset device */ UCLASS_REMOTEPROC, /* Remote Processor device */ UCLASS_RTC, /* Real time clock device */ UCLASS_SERIAL, /* Serial UART */ @@ -70,6 +69,7 @@ enum uclass_id { UCLASS_SPI_FLASH, /* SPI flash */ UCLASS_SPI_GENERIC, /* Generic SPI flash target */ UCLASS_SYSCON, /* System configuration device */ + UCLASS_SYSRESET, /* System reset device */ UCLASS_THERMAL, /* Thermal sensor */ UCLASS_TIMER, /* Timer device */ UCLASS_TPM, /* Trusted Platform Module TIS interface */ diff --git a/include/reset.h b/include/reset.h deleted file mode 100644 index 383761eb1fb..00000000000 --- a/include/reset.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2015 Google, Inc - * Written by Simon Glass - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __RESET_H -#define __RESET_H - -enum reset_t { - RESET_WARM, /* Reset CPU, keep GPIOs active */ - RESET_COLD, /* Reset CPU and GPIOs */ - RESET_POWER, /* Reset PMIC (remove and restore power) */ - - RESET_COUNT, -}; - -struct reset_ops { - /** - * request() - request a reset of the given type - * - * Note that this function may return before the reset takes effect. - * - * @type: Reset type to request - * @return -EINPROGRESS if the reset has been started and - * will complete soon, -EPROTONOSUPPORT if not supported - * by this device, 0 if the reset has already happened - * (in which case this method will not actually return) - */ - int (*request)(struct udevice *dev, enum reset_t type); -}; - -#define reset_get_ops(dev) ((struct reset_ops *)(dev)->driver->ops) - -/** - * reset_request() - request a reset - * - * @type: Reset type to request - * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device - */ -int reset_request(struct udevice *dev, enum reset_t type); - -/** - * reset_walk() - cause a reset - * - * This works through the available reset devices until it finds one that can - * perform a reset. If the provided reset type is not available, the next one - * will be tried. - * - * If this function fails to reset, it will display a message and halt - * - * @type: Reset type to request - * @return -EINPROGRESS if a reset is in progress, -ENOSYS if not available - */ -int reset_walk(enum reset_t type); - -/** - * reset_walk_halt() - try to reset, otherwise halt - * - * This calls reset_walk(). If it returns, indicating that reset is not - * supported, it prints a message and halts. - */ -void reset_walk_halt(enum reset_t type); - -/** - * reset_cpu() - calls reset_walk(RESET_WARM) - */ -void reset_cpu(ulong addr); - -#endif diff --git a/include/sysreset.h b/include/sysreset.h new file mode 100644 index 00000000000..393c7be3d81 --- /dev/null +++ b/include/sysreset.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SYSRESET_H +#define __SYSRESET_H + +enum sysreset_t { + SYSRESET_WARM, /* Reset CPU, keep GPIOs active */ + SYSRESET_COLD, /* Reset CPU and GPIOs */ + SYSRESET_POWER, /* Reset PMIC (remove and restore power) */ + + SYSRESET_COUNT, +}; + +struct sysreset_ops { + /** + * request() - request a sysreset of the given type + * + * Note that this function may return before the reset takes effect. + * + * @type: Reset type to request + * @return -EINPROGRESS if the reset has been started and + * will complete soon, -EPROTONOSUPPORT if not supported + * by this device, 0 if the reset has already happened + * (in which case this method will not actually return) + */ + int (*request)(struct udevice *dev, enum sysreset_t type); +}; + +#define sysreset_get_ops(dev) ((struct sysreset_ops *)(dev)->driver->ops) + +/** + * sysreset_request() - request a sysreset + * + * @type: Reset type to request + * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device + */ +int sysreset_request(struct udevice *dev, enum sysreset_t type); + +/** + * sysreset_walk() - cause a system reset + * + * This works through the available sysreset devices until it finds one that can + * perform a reset. If the provided sysreset type is not available, the next one + * will be tried. + * + * If this function fails to reset, it will display a message and halt + * + * @type: Reset type to request + * @return -EINPROGRESS if a reset is in progress, -ENOSYS if not available + */ +int sysreset_walk(enum sysreset_t type); + +/** + * sysreset_walk_halt() - try to reset, otherwise halt + * + * This calls sysreset_walk(). If it returns, indicating that reset is not + * supported, it prints a message and halts. + */ +void sysreset_walk_halt(enum sysreset_t type); + +/** + * reset_cpu() - calls sysreset_walk(SYSRESET_WARM) + */ +void reset_cpu(ulong addr); + +#endif diff --git a/test/dm/Makefile b/test/dm/Makefile index 9a11ae0a147..fd781e82cfe 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -26,7 +26,7 @@ obj-$(CONFIG_DM_PCI) += pci.o obj-$(CONFIG_RAM) += ram.o obj-y += regmap.o obj-$(CONFIG_REMOTEPROC) += remoteproc.o -obj-$(CONFIG_RESET) += reset.o +obj-$(CONFIG_SYSRESET) += sysreset.o obj-$(CONFIG_DM_RTC) += rtc.o obj-$(CONFIG_DM_SPI_FLASH) += sf.o obj-$(CONFIG_DM_SPI) += spi.o diff --git a/test/dm/reset.c b/test/dm/reset.c deleted file mode 100644 index 5d53f252bb5..00000000000 --- a/test/dm/reset.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -/* Test that we can use particular reset devices */ -static int dm_test_reset_base(struct unit_test_state *uts) -{ - struct sandbox_state *state = state_get_current(); - struct udevice *dev; - - /* Device 0 is the platform data device - it should never respond */ - ut_assertok(uclass_get_device(UCLASS_RESET, 0, &dev)); - ut_asserteq(-ENODEV, reset_request(dev, RESET_WARM)); - ut_asserteq(-ENODEV, reset_request(dev, RESET_COLD)); - ut_asserteq(-ENODEV, reset_request(dev, RESET_POWER)); - - /* Device 1 is the warm reset device */ - ut_assertok(uclass_get_device(UCLASS_RESET, 1, &dev)); - ut_asserteq(-EACCES, reset_request(dev, RESET_WARM)); - ut_asserteq(-ENOSYS, reset_request(dev, RESET_COLD)); - ut_asserteq(-ENOSYS, reset_request(dev, RESET_POWER)); - - state->reset_allowed[RESET_WARM] = true; - ut_asserteq(-EINPROGRESS, reset_request(dev, RESET_WARM)); - state->reset_allowed[RESET_WARM] = false; - - /* Device 2 is the cold reset device */ - ut_assertok(uclass_get_device(UCLASS_RESET, 2, &dev)); - ut_asserteq(-ENOSYS, reset_request(dev, RESET_WARM)); - ut_asserteq(-EACCES, reset_request(dev, RESET_COLD)); - state->reset_allowed[RESET_POWER] = false; - ut_asserteq(-EACCES, reset_request(dev, RESET_POWER)); - state->reset_allowed[RESET_POWER] = true; - - return 0; -} -DM_TEST(dm_test_reset_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); - -/* Test that we can walk through the reset devices */ -static int dm_test_reset_walk(struct unit_test_state *uts) -{ - struct sandbox_state *state = state_get_current(); - - /* If we generate a power reset, we will exit sandbox! */ - state->reset_allowed[RESET_POWER] = false; - ut_asserteq(-EACCES, reset_walk(RESET_WARM)); - ut_asserteq(-EACCES, reset_walk(RESET_COLD)); - ut_asserteq(-EACCES, reset_walk(RESET_POWER)); - - /* - * Enable cold reset - this should make cold reset work, plus a warm - * reset should be promoted to cold, since this is the next step - * along. - */ - state->reset_allowed[RESET_COLD] = true; - ut_asserteq(-EINPROGRESS, reset_walk(RESET_WARM)); - ut_asserteq(-EINPROGRESS, reset_walk(RESET_COLD)); - ut_asserteq(-EACCES, reset_walk(RESET_POWER)); - state->reset_allowed[RESET_COLD] = false; - state->reset_allowed[RESET_POWER] = true; - - return 0; -} -DM_TEST(dm_test_reset_walk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c new file mode 100644 index 00000000000..5e94c072b65 --- /dev/null +++ b/test/dm/sysreset.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Test that we can use particular sysreset devices */ +static int dm_test_sysreset_base(struct unit_test_state *uts) +{ + struct sandbox_state *state = state_get_current(); + struct udevice *dev; + + /* Device 0 is the platform data device - it should never respond */ + ut_assertok(uclass_get_device(UCLASS_SYSRESET, 0, &dev)); + ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_WARM)); + ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_COLD)); + ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_POWER)); + + /* Device 1 is the warm sysreset device */ + ut_assertok(uclass_get_device(UCLASS_SYSRESET, 1, &dev)); + ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_WARM)); + ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_COLD)); + ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_POWER)); + + state->sysreset_allowed[SYSRESET_WARM] = true; + ut_asserteq(-EINPROGRESS, sysreset_request(dev, SYSRESET_WARM)); + state->sysreset_allowed[SYSRESET_WARM] = false; + + /* Device 2 is the cold sysreset device */ + ut_assertok(uclass_get_device(UCLASS_SYSRESET, 2, &dev)); + ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_WARM)); + ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_COLD)); + state->sysreset_allowed[SYSRESET_POWER] = false; + ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_POWER)); + state->sysreset_allowed[SYSRESET_POWER] = true; + + return 0; +} +DM_TEST(dm_test_sysreset_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that we can walk through the sysreset devices */ +static int dm_test_sysreset_walk(struct unit_test_state *uts) +{ + struct sandbox_state *state = state_get_current(); + + /* If we generate a power sysreset, we will exit sandbox! */ + state->sysreset_allowed[SYSRESET_POWER] = false; + ut_asserteq(-EACCES, sysreset_walk(SYSRESET_WARM)); + ut_asserteq(-EACCES, sysreset_walk(SYSRESET_COLD)); + ut_asserteq(-EACCES, sysreset_walk(SYSRESET_POWER)); + + /* + * Enable cold system reset - this should make cold system reset work, + * plus a warm system reset should be promoted to cold, since this is + * the next step along. + */ + state->sysreset_allowed[SYSRESET_COLD] = true; + ut_asserteq(-EINPROGRESS, sysreset_walk(SYSRESET_WARM)); + ut_asserteq(-EINPROGRESS, sysreset_walk(SYSRESET_COLD)); + ut_asserteq(-EACCES, sysreset_walk(SYSRESET_POWER)); + state->sysreset_allowed[SYSRESET_COLD] = false; + state->sysreset_allowed[SYSRESET_POWER] = true; + + return 0; +} +DM_TEST(dm_test_sysreset_walk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); -- cgit v1.3.1 From 6238935d018042d332aa7e90eae3addfeb11abdc Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 13 May 2016 15:50:29 -0600 Subject: Add a mailbox driver framework/uclass A mailbox is a hardware mechanism for transferring small message and/or notifications between the CPU on which U-Boot runs and some other device such as an auxilliary CPU running firmware or a hardware module. This patch defines a standard API that connects mailbox clients to mailbox providers (drivers). Initially, DT is the only supported method for connecting the two. The DT binding specification (mailbox.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/mailbox/mailbox.txt. Signed-off-by: Stephen Warren Acked-by: Simon Glass --- doc/device-tree-bindings/mailbox/mailbox.txt | 32 ++++++ drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/mailbox/Kconfig | 13 +++ drivers/mailbox/Makefile | 5 + drivers/mailbox/mailbox-uclass.c | 145 ++++++++++++++++++++++++++ include/dm/uclass-id.h | 1 + include/mailbox_client.h | 149 +++++++++++++++++++++++++++ include/mailbox_uclass.h | 83 +++++++++++++++ 9 files changed, 431 insertions(+) create mode 100644 doc/device-tree-bindings/mailbox/mailbox.txt create mode 100644 drivers/mailbox/Kconfig create mode 100644 drivers/mailbox/Makefile create mode 100644 drivers/mailbox/mailbox-uclass.c create mode 100644 include/mailbox_client.h create mode 100644 include/mailbox_uclass.h (limited to 'include') diff --git a/doc/device-tree-bindings/mailbox/mailbox.txt b/doc/device-tree-bindings/mailbox/mailbox.txt new file mode 100644 index 00000000000..be05b9746c6 --- /dev/null +++ b/doc/device-tree-bindings/mailbox/mailbox.txt @@ -0,0 +1,32 @@ +* Generic Mailbox Controller and client driver bindings + +Generic binding to provide a way for Mailbox controller drivers to +assign appropriate mailbox channel to client drivers. + +* Mailbox Controller + +Required property: +- #mbox-cells: Must be at least 1. Number of cells in a mailbox + specifier. + +Example: + mailbox: mailbox { + ... + #mbox-cells = <1>; + }; + + +* Mailbox Client + +Required property: +- mboxes: List of phandle and mailbox channel specifiers. + +Optional property: +- mbox-names: List of identifier strings for each mailbox channel. + +Example: + pwr_cntrl: power { + ... + mbox-names = "pwr-ctrl", "rpc"; + mboxes = <&mailbox 0 &mailbox 1>; + }; diff --git a/drivers/Kconfig b/drivers/Kconfig index 118b66ed0e1..f2a137ad87f 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -30,6 +30,8 @@ source "drivers/input/Kconfig" source "drivers/led/Kconfig" +source "drivers/mailbox/Kconfig" + source "drivers/memory/Kconfig" source "drivers/misc/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 99dd07fc769..f6295d285ec 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -64,6 +64,7 @@ obj-y += video/ obj-y += watchdog/ obj-$(CONFIG_QE) += qe/ obj-$(CONFIG_U_QE) += qe/ +obj-y += mailbox/ obj-y += memory/ obj-y += pwm/ obj-y += input/ diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig new file mode 100644 index 00000000000..295e6db0f28 --- /dev/null +++ b/drivers/mailbox/Kconfig @@ -0,0 +1,13 @@ +menu "Mailbox Controller Support" + +config DM_MAILBOX + bool "Enable mailbox controllers using Driver Model" + depends on DM && OF_CONTROL + help + Enable support for the mailbox driver class. Mailboxes provide the + ability to transfer small messages and/or notifications from one + CPU to another CPU, or sometimes to dedicated HW modules. They form + the basis of a variety of inter-process/inter-CPU communication + protocols. + +endmenu diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile new file mode 100644 index 00000000000..a2d96a4e3b9 --- /dev/null +++ b/drivers/mailbox/Makefile @@ -0,0 +1,5 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_DM_MAILBOX) += mailbox-uclass.o diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c new file mode 100644 index 00000000000..73fa32874a5 --- /dev/null +++ b/drivers/mailbox/mailbox-uclass.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static inline struct mbox_ops *mbox_dev_ops(struct udevice *dev) +{ + return (struct mbox_ops *)dev->driver->ops; +} + +static int mbox_of_xlate_default(struct mbox_chan *chan, + struct fdtdec_phandle_args *args) +{ + debug("%s(chan=%p)\n", __func__, chan); + + if (args->args_count != 1) { + debug("Invaild args_count: %d\n", args->args_count); + return -EINVAL; + } + + chan->id = args->args[0]; + + return 0; +} + +int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan) +{ + struct fdtdec_phandle_args args; + int ret; + struct udevice *dev_mbox; + struct mbox_ops *ops; + + debug("%s(dev=%p, index=%d, chan=%p)\n", __func__, dev, index, chan); + + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset, + "mboxes", "#mbox-cells", 0, + index, &args); + if (ret) { + debug("%s: fdtdec_parse_phandle_with_args failed: %d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_of_offset(UCLASS_MAILBOX, args.node, + &dev_mbox); + if (ret) { + debug("%s: uclass_get_device_by_of_offset failed: %d\n", + __func__, ret); + return ret; + } + ops = mbox_dev_ops(dev_mbox); + + chan->dev = dev_mbox; + if (ops->of_xlate) + ret = ops->of_xlate(chan, &args); + else + ret = mbox_of_xlate_default(chan, &args); + if (ret) { + debug("of_xlate() failed: %d\n", ret); + return ret; + } + + ret = ops->request(chan); + if (ret) { + debug("ops->request() failed: %d\n", ret); + return ret; + } + + return 0; +} + +int mbox_get_by_name(struct udevice *dev, const char *name, + struct mbox_chan *chan) +{ + int index; + + debug("%s(dev=%p, name=%s, chan=%p)\n", __func__, dev, name, chan); + + index = fdt_find_string(gd->fdt_blob, dev->of_offset, "mbox-names", + name); + if (index < 0) { + debug("fdt_find_string() failed: %d\n", index); + return index; + } + + return mbox_get_by_index(dev, index, chan); +} + +int mbox_free(struct mbox_chan *chan) +{ + struct mbox_ops *ops = mbox_dev_ops(chan->dev); + + debug("%s(chan=%p)\n", __func__, chan); + + return ops->free(chan); +} + +int mbox_send(struct mbox_chan *chan, const void *data) +{ + struct mbox_ops *ops = mbox_dev_ops(chan->dev); + + debug("%s(chan=%p, data=%p)\n", __func__, chan, data); + + return ops->send(chan, data); +} + +int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us) +{ + struct mbox_ops *ops = mbox_dev_ops(chan->dev); + ulong start_time; + int ret; + + debug("%s(chan=%p, data=%p, timeout_us=%ld)\n", __func__, chan, data, + timeout_us); + + start_time = timer_get_us(); + /* + * Account for partial us ticks, but if timeout_us is 0, ensure we + * still don't wait at all. + */ + if (timeout_us) + timeout_us++; + + for (;;) { + ret = ops->recv(chan, data); + if (ret != -ENODATA) + return ret; + if ((timer_get_us() - start_time) >= timeout_us) + return -ETIMEDOUT; + } +} + +UCLASS_DRIVER(mailbox) = { + .id = UCLASS_MAILBOX, + .name = "mailbox", +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index f9ff45e010f..0777cbe27ee 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -44,6 +44,7 @@ enum uclass_id { UCLASS_KEYBOARD, /* Keyboard input device */ UCLASS_LED, /* Light-emitting diode (LED) */ UCLASS_LPC, /* x86 'low pin count' interface */ + UCLASS_MAILBOX, /* Mailbox controller */ UCLASS_MASS_STORAGE, /* Mass storage device */ UCLASS_MISC, /* Miscellaneous device */ UCLASS_MMC, /* SD / MMC card or chip */ diff --git a/include/mailbox_client.h b/include/mailbox_client.h new file mode 100644 index 00000000000..8345ea0bf1f --- /dev/null +++ b/include/mailbox_client.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _MAILBOX_CLIENT_H +#define _MAILBOX_CLIENT_H + +/** + * A mailbox is a hardware mechanism for transferring small fixed-size messages + * and/or notifications between the CPU on which U-Boot runs and some other + * device such as an auxiliary CPU running firmware or a hardware module. + * + * Data transfer is optional; a mailbox may consist solely of a notification + * mechanism. When data transfer is implemented, it is via HW registers or + * FIFOs, rather than via RAM-based buffers. The mailbox API generally + * implements any communication protocol enforced solely by hardware, and + * leaves any higher-level protocols to other layers. + * + * A mailbox channel is a bi-directional mechanism that can send a message or + * notification to a single specific remote entity, and receive messages or + * notifications from that entity. The size, content, and format of such + * messages is defined by the mailbox implementation, or the remote entity with + * which it communicates; there is no general standard at this API level. + * + * A driver that implements UCLASS_MAILBOX is a mailbox provider. A provider + * will often implement multiple separate mailbox channels, since the hardware + * it manages often has this capability. mailbox_uclass.h describes the + * interface which mailbox providers must implement. + * + * Mailbox consumers/clients generate and send, or receive and process, + * messages. This header file describes the API used by clients. + */ + +struct udevice; + +/** + * struct mbox_chan - A handle to a single mailbox channel. + * + * Clients provide storage for channels. The content of the channel structure + * is managed solely by the mailbox API and mailbox drivers. A mailbox channel + * is initialized by "get"ing the mailbox. The channel struct is passed to all + * other mailbox APIs to identify which mailbox to operate upon. + * + * @dev: The device which implements the mailbox. + * @id: The mailbox channel ID within the provider. + * + * Currently, the mailbox API assumes that a single integer ID is enough to + * identify and configure any mailbox channel for any mailbox provider. If this + * assumption becomes invalid in the future, the struct could be expanded to + * either (a) add more fields to allow mailbox providers to store additional + * information, or (b) replace the id field with an opaque pointer, which the + * provider would dynamically allocated during its .of_xlate op, and process + * during is .request op. This may require the addition of an extra op to clean + * up the allocation. + */ +struct mbox_chan { + struct udevice *dev; + /* + * Written by of_xlate. We assume a single id is enough for now. In the + * future, we might add more fields here. + */ + unsigned long id; +}; + +/** + * mbox_get_by_index - Get/request a mailbox by integer index + * + * This looks up and requests a mailbox channel. The index is relative to the + * client device; each device is assumed to have n mailbox channels associated + * with it somehow, and this function finds and requests one of them. The + * mapping of client device channel indices to provider channels may be via + * device-tree properties, board-provided mapping tables, or some other + * mechanism. + * + * @dev: The client device. + * @index: The index of the mailbox channel to request, within the + * client's list of channels. + * @chan A pointer to a channel object to initialize. + * @return 0 if OK, or a negative error code. + */ +int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan); + +/** + * mbox_get_by_name - Get/request a mailbox by name + * + * This looks up and requests a mailbox channel. The name is relative to the + * client device; each device is assumed to have n mailbox channels associated + * with it somehow, and this function finds and requests one of them. The + * mapping of client device channel names to provider channels may be via + * device-tree properties, board-provided mapping tables, or some other + * mechanism. + * + * @dev: The client device. + * @name: The name of the mailbox channel to request, within the client's + * list of channels. + * @chan A pointer to a channel object to initialize. + * @return 0 if OK, or a negative error code. + */ +int mbox_get_by_name(struct udevice *dev, const char *name, + struct mbox_chan *chan); + +/** + * mbox_free - Free a previously requested mailbox channel. + * + * @chan: A channel object that was previously successfully requested by + * calling mbox_get_by_*(). + * @return 0 if OK, or a negative error code. + */ +int mbox_free(struct mbox_chan *chan); + +/** + * mbox_send - Send a message over a mailbox channel + * + * This function will send a message to the remote entity. It may return before + * the remote entity has received and/or processed the message. + * + * @chan: A channel object that was previously successfully requested by + * calling mbox_get_by_*(). + * @data: A pointer to the message to transfer. The format and size of + * the memory region pointed at by @data is determined by the + * mailbox provider. Providers that solely transfer notifications + * will ignore this parameter. + * @return 0 if OK, or a negative error code. + */ +int mbox_send(struct mbox_chan *chan, const void *data); + +/** + * mbox_recv - Receive any available message from a mailbox channel + * + * This function will wait (up to the specified @timeout_us) for a message to + * be sent by the remote entity, and write the content of any such message + * into a caller-provided buffer. + * + * @chan: A channel object that was previously successfully requested by + * calling mbox_get_by_*(). + * @data: A pointer to the buffer to receive the message. The format and + * size of the memory region pointed at by @data is determined by + * the mailbox provider. Providers that solely transfer + * notifications will ignore this parameter. + * @timeout_us: The maximum time to wait for a message to be available, in + * micro-seconds. A value of 0 does not wait at all. + * @return 0 if OK, -ENODATA if no message was available, or a negative error + * code. + */ +int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us); + +#endif diff --git a/include/mailbox_uclass.h b/include/mailbox_uclass.h new file mode 100644 index 00000000000..6a2994c34ce --- /dev/null +++ b/include/mailbox_uclass.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _MAILBOX_UCLASS_H +#define _MAILBOX_UCLASS_H + +/* See mailbox_client.h for background documentation. */ + +#include + +struct udevice; + +/** + * struct mbox_ops - The functions that a mailbox driver must implement. + */ +struct mbox_ops { + /** + * of_xlate - Translate a client's device-tree (OF) mailbox specifier. + * + * The mailbox core calls this function as the first step in + * implementing a client's mbox_get_by_*() call. + * + * If this function pointer is set to NULL, the mailbox core will use + * a default implementation, which assumes #mbox-cells = <1>, and that + * the DT cell contains a simple integer channel ID. + * + * At present, the mailbox API solely supports device-tree. If this + * changes, other xxx_xlate() functions may be added to support those + * other mechanisms. + * + * @chan: The channel to hold the translation result. + * @args: The mailbox specifier values from device tree. + * @return 0 if OK, or a negative error code. + */ + int (*of_xlate)(struct mbox_chan *chan, + struct fdtdec_phandle_args *args); + /** + * request - Request a translated channel. + * + * The mailbox core calls this function as the second step in + * implementing a client's mbox_get_by_*() call, following a successful + * xxx_xlate() call. + * + * @chan: The channel to request; this has been filled in by a + * previoux xxx_xlate() function call. + * @return 0 if OK, or a negative error code. + */ + int (*request)(struct mbox_chan *chan); + /** + * free - Free a previously requested channel. + * + * This is the implementation of the client mbox_free() API. + * + * @chan: The channel to free. + * @return 0 if OK, or a negative error code. + */ + int (*free)(struct mbox_chan *chan); + /** + * send - Send a message over a mailbox channel + * + * @chan: The channel to send to the message to. + * @data: A pointer to the message to send. + * @return 0 if OK, or a negative error code. + */ + int (*send)(struct mbox_chan *chan, const void *data); + /** + * recv - Receive any available message from the channel. + * + * This function does not block. If not message is immediately + * available, the function should return an error. + * + * @chan: The channel to receive to the message from. + * @data: A pointer to the buffer to hold the received message. + * @return 0 if OK, -ENODATA if no message was available, or a negative + * error code. + */ + int (*recv)(struct mbox_chan *chan, void *data); +}; + +#endif -- cgit v1.3.1 From d0375f3cc55ce740836f9ba6fe081ed0fdc19a3c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 7 Aug 2015 07:42:22 -0600 Subject: arm: rpi: Define CONFIG_TFTP_TSIZE to show tftp size info This shows a proper progress display and the total amount of data transferred. Enable it for Raspberry Pi. Signed-off-by: Simon Glass Acked-by: Stephen Warren --- include/configs/rpi.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/rpi.h b/include/configs/rpi.h index af58182e7b0..9ef5eae304e 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -106,6 +106,7 @@ #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_TFTP_TSIZE #define CONFIG_MISC_INIT_R #define CONFIG_USB_KEYBOARD #define CONFIG_SYS_USB_EVENT_POLL -- cgit v1.3.1 From e98dd20ccec30311dddd165f945c7ce0dedef6db Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 14 May 2016 14:02:55 -0600 Subject: mmc: Drop mmc_register() This function is no longer used. Signed-off-by: Simon Glass --- drivers/mmc/mmc.c | 9 --------- include/mmc.h | 1 - 2 files changed, 10 deletions(-) (limited to 'include') diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 74b3d68f871..1ddeff4ace7 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1531,15 +1531,6 @@ static int mmc_send_if_cond(struct mmc *mmc) return 0; } -/* not used any more */ -int __deprecated mmc_register(struct mmc *mmc) -{ -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - printf("%s is deprecated! use mmc_create() instead.\n", __func__); -#endif - return -1; -} - #ifdef CONFIG_BLK int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg) { diff --git a/include/mmc.h b/include/mmc.h index a5c6573ddd6..056296e908c 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -411,7 +411,6 @@ enum mmc_hwpart_conf_mode { MMC_HWPART_CONF_COMPLETE, }; -int mmc_register(struct mmc *mmc); struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); /** -- cgit v1.3.1 From 9cf7b1a74c8c17145e39d34893cce763e098efd2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 14 May 2016 14:02:56 -0600 Subject: mmc: Drop dead mmc code for non-generic MMC All boards that use MMC define CONFIG_GENERIC_MMC now, so we can drop this old code. Signed-off-by: Simon Glass --- cmd/mmc.c | 62 ----------------------------------------------------------- include/mmc.h | 4 ---- 2 files changed, 66 deletions(-) (limited to 'include') diff --git a/cmd/mmc.c b/cmd/mmc.c index eb4a547a970..b2761e934bd 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -11,66 +11,6 @@ #include static int curr_device = -1; -#ifndef CONFIG_GENERIC_MMC -int do_mmc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int dev; - - if (argc < 2) - return CMD_RET_USAGE; - - if (strcmp(argv[1], "init") == 0) { - if (argc == 2) { - if (curr_device < 0) - dev = 1; - else - dev = curr_device; - } else if (argc == 3) { - dev = (int)simple_strtoul(argv[2], NULL, 10); - } else { - return CMD_RET_USAGE; - } - - if (mmc_legacy_init(dev) != 0) { - puts("No MMC card found\n"); - return 1; - } - - curr_device = dev; - printf("mmc%d is available\n", curr_device); - } else if (strcmp(argv[1], "device") == 0) { - if (argc == 2) { - if (curr_device < 0) { - puts("No MMC device available\n"); - return 1; - } - } else if (argc == 3) { - dev = (int)simple_strtoul(argv[2], NULL, 10); - -#ifdef CONFIG_SYS_MMC_SET_DEV - if (mmc_set_dev(dev) != 0) - return 1; -#endif - curr_device = dev; - } else { - return CMD_RET_USAGE; - } - - printf("mmc%d is current device\n", curr_device); - } else { - return CMD_RET_USAGE; - } - - return 0; -} - -U_BOOT_CMD( - mmc, 3, 1, do_mmc, - "MMC sub-system", - "init [dev] - init MMC sub system\n" - "mmc device [dev] - show or set current device" -); -#else /* !CONFIG_GENERIC_MMC */ static void print_mmcinfo(struct mmc *mmc) { @@ -881,5 +821,3 @@ U_BOOT_CMD( "display MMC info", "- display info of the current MMC device" ); - -#endif /* !CONFIG_GENERIC_MMC */ diff --git a/include/mmc.h b/include/mmc.h index 056296e908c..7fdfc324fea 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -491,16 +491,12 @@ int mmc_start_init(struct mmc *mmc); */ void mmc_set_preinit(struct mmc *mmc, int preinit); -#ifdef CONFIG_GENERIC_MMC #ifdef CONFIG_MMC_SPI #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) #else #define mmc_host_is_spi(mmc) 0 #endif struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); -#else -int mmc_legacy_init(int verbose); -#endif void board_mmc_power_init(void); int board_mmc_init(bd_t *bis); -- cgit v1.3.1 From 0efe1bcf5c2ce89d7c2467550e2823d7f95733e0 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Fri, 6 May 2016 21:01:01 +0200 Subject: efi_loader: Add network access support We can now successfully boot EFI applications from disk, but users may want to also run them from a PXE setup. This patch implements rudimentary network support, allowing a payload to send and receive network packets. With this patch, I was able to successfully run grub2 with network access inside of QEMU's -M xlnx-ep108. Signed-off-by: Alexander Graf --- cmd/bootefi.c | 7 ++ include/efi_api.h | 119 +++++++++++++++++++ include/efi_loader.h | 7 ++ include/net.h | 2 +- lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_net.c | 291 +++++++++++++++++++++++++++++++++++++++++++++++ net/bootp.c | 2 + net/net.c | 4 +- net/tftp.c | 2 + 9 files changed, 432 insertions(+), 3 deletions(-) create mode 100644 lib/efi_loader/efi_net.c (limited to 'include') diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 7f552fc0d4d..d3a23318702 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -197,6 +197,13 @@ static unsigned long do_bootefi_exec(void *efi, void *fdt) #ifdef CONFIG_LCD efi_gop_register(); #endif +#ifdef CONFIG_NET + void *nethandle = loaded_image_info.device_handle; + efi_net_register(&nethandle); + + if (!memcmp(bootefi_device_path[0].str, "N\0e\0t", 6)) + loaded_image_info.device_handle = nethandle; +#endif /* Call our payload! */ #ifdef DEBUG_EFI diff --git a/include/efi_api.h b/include/efi_api.h index 51d7586e634..20035d72727 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -412,4 +412,123 @@ struct efi_gop struct efi_gop_mode *mode; }; +#define EFI_SIMPLE_NETWORK_GUID \ + EFI_GUID(0xa19832b9, 0xac25, 0x11d3, \ + 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d) + +struct efi_mac_address { + char mac_addr[32]; +}; + +struct efi_ip_address { + u8 ip_addr[16]; +}; + +enum efi_simple_network_state { + EFI_NETWORK_STOPPED, + EFI_NETWORK_STARTED, + EFI_NETWORK_INITIALIZED, +}; + +struct efi_simple_network_mode { + enum efi_simple_network_state state; + u32 hwaddr_size; + u32 media_header_size; + u32 max_packet_size; + u32 nvram_size; + u32 nvram_access_size; + u32 receive_filter_mask; + u32 receive_filter_setting; + u32 max_mcast_filter_count; + u32 mcast_filter_count; + struct efi_mac_address mcast_filter[16]; + struct efi_mac_address current_address; + struct efi_mac_address broadcast_address; + struct efi_mac_address permanent_address; + u8 if_type; + u8 mac_changeable; + u8 multitx_supported; + u8 media_present_supported; + u8 media_present; +}; + +#define EFI_SIMPLE_NETWORK_RECEIVE_UNICAST 0x01, +#define EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST 0x02, +#define EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST 0x04, +#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS 0x08, +#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST 0x10, + +struct efi_simple_network +{ + u64 revision; + efi_status_t (EFIAPI *start)(struct efi_simple_network *this); + efi_status_t (EFIAPI *stop)(struct efi_simple_network *this); + efi_status_t (EFIAPI *initialize)(struct efi_simple_network *this, + ulong extra_rx, ulong extra_tx); + efi_status_t (EFIAPI *reset)(struct efi_simple_network *this, + int extended_verification); + efi_status_t (EFIAPI *shutdown)(struct efi_simple_network *this); + efi_status_t (EFIAPI *receive_filters)(struct efi_simple_network *this, + u32 enable, u32 disable, int reset_mcast_filter, + ulong mcast_filter_count, + struct efi_mac_address *mcast_filter); + efi_status_t (EFIAPI *station_address)(struct efi_simple_network *this, + int reset, struct efi_mac_address *new_mac); + efi_status_t (EFIAPI *statistics)(struct efi_simple_network *this, + int reset, ulong *stat_size, void *stat_table); + efi_status_t (EFIAPI *mcastiptomac)(struct efi_simple_network *this, + int ipv6, struct efi_ip_address *ip, + struct efi_mac_address *mac); + efi_status_t (EFIAPI *nvdata)(struct efi_simple_network *this, + int read_write, ulong offset, ulong buffer_size, + char *buffer); + efi_status_t (EFIAPI *get_status)(struct efi_simple_network *this, + u32 *int_status, void **txbuf); + efi_status_t (EFIAPI *transmit)(struct efi_simple_network *this, + ulong header_size, ulong buffer_size, void *buffer, + struct efi_mac_address *src_addr, + struct efi_mac_address *dest_addr, u16 *protocol); + efi_status_t (EFIAPI *receive)(struct efi_simple_network *this, + ulong *header_size, ulong *buffer_size, void *buffer, + struct efi_mac_address *src_addr, + struct efi_mac_address *dest_addr, u16 *protocol); + void (EFIAPI *waitforpacket)(void); + struct efi_simple_network_mode *mode; +}; + +#define EFI_PXE_GUID \ + EFI_GUID(0x03c4e603, 0xac28, 0x11d3, \ + 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d) + +struct efi_pxe_packet { + u8 packet[1472]; +}; + +struct efi_pxe_mode +{ + u8 unused[52]; + struct efi_pxe_packet dhcp_discover; + struct efi_pxe_packet dhcp_ack; + struct efi_pxe_packet proxy_offer; + struct efi_pxe_packet pxe_discover; + struct efi_pxe_packet pxe_reply; +}; + +struct efi_pxe { + u64 rev; + void (EFIAPI *start)(void); + void (EFIAPI *stop)(void); + void (EFIAPI *dhcp)(void); + void (EFIAPI *discover)(void); + void (EFIAPI *mftp)(void); + void (EFIAPI *udpwrite)(void); + void (EFIAPI *udpread)(void); + void (EFIAPI *setipfilter)(void); + void (EFIAPI *arp)(void); + void (EFIAPI *setparams)(void); + void (EFIAPI *setstationip)(void); + void (EFIAPI *setpackets)(void); + struct efi_pxe_mode *mode; +}; + #endif diff --git a/include/efi_loader.h b/include/efi_loader.h index 88b8149b147..8005454af36 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -91,6 +91,12 @@ extern struct list_head efi_obj_list; int efi_disk_register(void); /* Called by bootefi to make GOP (graphical) interface available */ int efi_gop_register(void); +/* Called by bootefi to make the network interface available */ +int efi_net_register(void **handle); + +/* Called by networking code to memorize the dhcp ack package */ +void efi_net_set_dhcp_ack(void *pkt, int len); + /* * Stub implementation for a protocol opener that just returns the handle as * interface @@ -157,5 +163,6 @@ static inline void ascii2unicode(u16 *unicode, char *ascii) static inline void efi_restore_gd(void) { } static inline void efi_set_bootdev(const char *dev, const char *devnr, const char *path) { } +static inline void efi_net_set_dhcp_ack(void *pkt, int len) { } #endif diff --git a/include/net.h b/include/net.h index 05800c4422e..5ee5929beb8 100644 --- a/include/net.h +++ b/include/net.h @@ -269,7 +269,7 @@ int eth_getenv_enetaddr_by_index(const char *base_name, int index, int eth_init(void); /* Initialize the device */ int eth_send(void *packet, int length); /* Send a packet */ -#ifdef CONFIG_API +#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER) int eth_receive(void *packet, int length); /* Receive a packet*/ extern void (*push_packet)(void *packet, int length); #endif diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 83e31f6d1f6..2a3849e31b9 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -11,3 +11,4 @@ obj-y += efi_image_loader.o efi_boottime.o efi_runtime.o efi_console.o obj-y += efi_memory.o obj-$(CONFIG_LCD) += efi_gop.o obj-$(CONFIG_PARTITIONS) += efi_disk.o +obj-$(CONFIG_NET) += efi_net.o diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c new file mode 100644 index 00000000000..dd3b48570d8 --- /dev/null +++ b/lib/efi_loader/efi_net.c @@ -0,0 +1,291 @@ +/* + * EFI application network access support + * + * Copyright (c) 2016 Alexander Graf + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_GUID; +static const efi_guid_t efi_pxe_guid = EFI_PXE_GUID; +static struct efi_pxe_packet *dhcp_ack; +static bool new_rx_packet; +static void *new_tx_packet; + +struct efi_net_obj { + /* Generic EFI object parent class data */ + struct efi_object parent; + /* EFI Interface callback struct for network */ + struct efi_simple_network net; + struct efi_simple_network_mode net_mode; + /* Device path to the network adapter */ + struct efi_device_path_file_path dp[2]; + /* PXE struct to transmit dhcp data */ + struct efi_pxe pxe; + struct efi_pxe_mode pxe_mode; +}; + +static efi_status_t EFIAPI efi_net_start(struct efi_simple_network *this) +{ + EFI_ENTRY("%p", this); + + return EFI_EXIT(EFI_SUCCESS); +} + +static efi_status_t EFIAPI efi_net_stop(struct efi_simple_network *this) +{ + EFI_ENTRY("%p", this); + + return EFI_EXIT(EFI_SUCCESS); +} + +static efi_status_t EFIAPI efi_net_initialize(struct efi_simple_network *this, + ulong extra_rx, ulong extra_tx) +{ + EFI_ENTRY("%p, %lx, %lx", this, extra_rx, extra_tx); + + eth_init(); + + return EFI_EXIT(EFI_SUCCESS); +} + +static efi_status_t EFIAPI efi_net_reset(struct efi_simple_network *this, + int extended_verification) +{ + EFI_ENTRY("%p, %x", this, extended_verification); + + return EFI_EXIT(EFI_SUCCESS); +} + +static efi_status_t EFIAPI efi_net_shutdown(struct efi_simple_network *this) +{ + EFI_ENTRY("%p", this); + + return EFI_EXIT(EFI_SUCCESS); +} + +static efi_status_t EFIAPI efi_net_receive_filters( + struct efi_simple_network *this, u32 enable, u32 disable, + int reset_mcast_filter, ulong mcast_filter_count, + struct efi_mac_address *mcast_filter) +{ + EFI_ENTRY("%p, %x, %x, %x, %lx, %p", this, enable, disable, + reset_mcast_filter, mcast_filter_count, mcast_filter); + + /* XXX Do we care? */ + + return EFI_EXIT(EFI_SUCCESS); +} + +static efi_status_t EFIAPI efi_net_station_address( + struct efi_simple_network *this, int reset, + struct efi_mac_address *new_mac) +{ + EFI_ENTRY("%p, %x, %p", this, reset, new_mac); + + return EFI_EXIT(EFI_INVALID_PARAMETER); +} + +static efi_status_t EFIAPI efi_net_statistics(struct efi_simple_network *this, + int reset, ulong *stat_size, + void *stat_table) +{ + EFI_ENTRY("%p, %x, %p, %p", this, reset, stat_size, stat_table); + + return EFI_EXIT(EFI_INVALID_PARAMETER); +} + +static efi_status_t EFIAPI efi_net_mcastiptomac(struct efi_simple_network *this, + int ipv6, + struct efi_ip_address *ip, + struct efi_mac_address *mac) +{ + EFI_ENTRY("%p, %x, %p, %p", this, ipv6, ip, mac); + + return EFI_EXIT(EFI_INVALID_PARAMETER); +} + +static efi_status_t EFIAPI efi_net_nvdata(struct efi_simple_network *this, + int read_write, ulong offset, + ulong buffer_size, char *buffer) +{ + EFI_ENTRY("%p, %x, %lx, %lx, %p", this, read_write, offset, buffer_size, + buffer); + + return EFI_EXIT(EFI_INVALID_PARAMETER); +} + +static efi_status_t EFIAPI efi_net_get_status(struct efi_simple_network *this, + u32 *int_status, void **txbuf) +{ + EFI_ENTRY("%p, %p, %p", this, int_status, txbuf); + + /* We send packets synchronously, so nothing is outstanding */ + if (int_status) + *int_status = 0; + if (txbuf) + *txbuf = new_tx_packet; + + new_tx_packet = NULL; + + return EFI_EXIT(EFI_SUCCESS); +} + +static efi_status_t EFIAPI efi_net_transmit(struct efi_simple_network *this, + ulong header_size, ulong buffer_size, void *buffer, + struct efi_mac_address *src_addr, + struct efi_mac_address *dest_addr, u16 *protocol) +{ + EFI_ENTRY("%p, %lx, %lx, %p, %p, %p, %p", this, header_size, + buffer_size, buffer, src_addr, dest_addr, protocol); + + if (header_size) { + /* We would need to create the header if header_size != 0 */ + return EFI_EXIT(EFI_INVALID_PARAMETER); + } + + net_send_packet(buffer, buffer_size); + new_tx_packet = buffer; + + return EFI_EXIT(EFI_SUCCESS); +} + +static void efi_net_push(void *pkt, int len) +{ + new_rx_packet = true; +} + +static efi_status_t EFIAPI efi_net_receive(struct efi_simple_network *this, + ulong *header_size, ulong *buffer_size, void *buffer, + struct efi_mac_address *src_addr, + struct efi_mac_address *dest_addr, u16 *protocol) +{ + EFI_ENTRY("%p, %p, %p, %p, %p, %p, %p", this, header_size, + buffer_size, buffer, src_addr, dest_addr, protocol); + + push_packet = efi_net_push; + eth_rx(); + push_packet = NULL; + + if (!new_rx_packet) + return EFI_EXIT(EFI_NOT_READY); + + if (*buffer_size < net_rx_packet_len) { + /* Packet doesn't fit, try again with bigger buf */ + *buffer_size = net_rx_packet_len; + return EFI_EXIT(EFI_BUFFER_TOO_SMALL); + } + + memcpy(buffer, net_rx_packet, net_rx_packet_len); + *buffer_size = net_rx_packet_len; + new_rx_packet = false; + + return EFI_EXIT(EFI_SUCCESS); +} + +static efi_status_t efi_net_open_dp(void *handle, efi_guid_t *protocol, + void **protocol_interface, void *agent_handle, + void *controller_handle, uint32_t attributes) +{ + struct efi_simple_network *net = handle; + struct efi_net_obj *netobj = container_of(net, struct efi_net_obj, net); + + *protocol_interface = netobj->dp; + + return EFI_SUCCESS; +} + +static efi_status_t efi_net_open_pxe(void *handle, efi_guid_t *protocol, + void **protocol_interface, void *agent_handle, + void *controller_handle, uint32_t attributes) +{ + struct efi_simple_network *net = handle; + struct efi_net_obj *netobj = container_of(net, struct efi_net_obj, net); + + *protocol_interface = &netobj->pxe; + + return EFI_SUCCESS; +} + +void efi_net_set_dhcp_ack(void *pkt, int len) +{ + int maxsize = sizeof(*dhcp_ack); + + if (!dhcp_ack) + dhcp_ack = malloc(maxsize); + + memcpy(dhcp_ack, pkt, min(len, maxsize)); +} + +/* This gets called from do_bootefi_exec(). */ +int efi_net_register(void **handle) +{ + struct efi_net_obj *netobj; + struct efi_device_path_file_path dp_net = { + .dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE, + .dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH, + .dp.length = sizeof(dp_net), + .str = { 'N', 'e', 't' }, + }; + struct efi_device_path_file_path dp_end = { + .dp.type = DEVICE_PATH_TYPE_END, + .dp.sub_type = DEVICE_PATH_SUB_TYPE_END, + .dp.length = sizeof(dp_end), + }; + + if (!eth_get_dev()) { + /* No eth device active, don't expose any */ + return 0; + } + + /* We only expose the "active" eth device, so one is enough */ + netobj = calloc(1, sizeof(*netobj)); + + /* Fill in object data */ + netobj->parent.protocols[0].guid = &efi_net_guid; + netobj->parent.protocols[0].open = efi_return_handle; + netobj->parent.protocols[1].guid = &efi_guid_device_path; + netobj->parent.protocols[1].open = efi_net_open_dp; + netobj->parent.protocols[2].guid = &efi_pxe_guid; + netobj->parent.protocols[2].open = efi_net_open_pxe; + netobj->parent.handle = &netobj->net; + netobj->net.start = efi_net_start; + netobj->net.stop = efi_net_stop; + netobj->net.initialize = efi_net_initialize; + netobj->net.reset = efi_net_reset; + netobj->net.shutdown = efi_net_shutdown; + netobj->net.receive_filters = efi_net_receive_filters; + netobj->net.station_address = efi_net_station_address; + netobj->net.statistics = efi_net_statistics; + netobj->net.mcastiptomac = efi_net_mcastiptomac; + netobj->net.nvdata = efi_net_nvdata; + netobj->net.get_status = efi_net_get_status; + netobj->net.transmit = efi_net_transmit; + netobj->net.receive = efi_net_receive; + netobj->net.mode = &netobj->net_mode; + netobj->net_mode.state = EFI_NETWORK_STARTED; + netobj->dp[0] = dp_net; + netobj->dp[1] = dp_end; + memcpy(netobj->net_mode.current_address.mac_addr, eth_get_ethaddr(), 6); + netobj->net_mode.max_packet_size = PKTSIZE; + + netobj->pxe.mode = &netobj->pxe_mode; + if (dhcp_ack) + netobj->pxe_mode.dhcp_ack = *dhcp_ack; + + /* Hook net up to the device list */ + list_add_tail(&netobj->parent.link, &efi_obj_list); + + if (handle) + *handle = &netobj->net; + + return 0; +} diff --git a/net/bootp.c b/net/bootp.c index d7852dbb447..d91b3076b35 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include "bootp.h" @@ -1025,6 +1026,7 @@ static void dhcp_handler(uchar *pkt, unsigned dest, struct in_addr sip, strlen(CONFIG_SYS_BOOTFILE_PREFIX)) == 0) { #endif /* CONFIG_SYS_BOOTFILE_PREFIX */ dhcp_packet_process_options(bp); + efi_net_set_dhcp_ack(pkt, len); debug("TRANSITIONING TO REQUESTING STATE\n"); dhcp_state = REQUESTING; diff --git a/net/net.c b/net/net.c index fba111edfba..1e1d23dafa5 100644 --- a/net/net.c +++ b/net/net.c @@ -146,7 +146,7 @@ static unsigned net_ip_id; /* Ethernet bcast address */ const u8 net_bcast_ethaddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; const u8 net_null_ethaddr[6]; -#ifdef CONFIG_API +#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER) void (*push_packet)(void *, int len) = 0; #endif /* Network loop state */ @@ -1054,7 +1054,7 @@ void net_process_received_packet(uchar *in_packet, int len) if (len < ETHER_HDR_SIZE) return; -#ifdef CONFIG_API +#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER) if (push_packet) { (*push_packet)(in_packet, len); return; diff --git a/net/tftp.c b/net/tftp.c index f2889fe4c9b..ced45ec1f1f 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -804,6 +805,7 @@ void tftp_start(enum proto_t protocol) printf("Load address: 0x%lx\n", load_addr); puts("Loading: *\b"); tftp_state = STATE_SEND_RRQ; + efi_set_bootdev("Net", "", tftp_filename); } time_start = get_timer(0); -- cgit v1.3.1 From 0dac6b4e850cdd934f9b04cecc79fc395127ab29 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Fri, 6 May 2016 21:01:03 +0200 Subject: net: Move the VCI and client arch values to Kconfig We have a bunch of boards that define their vendor class identifier and client archs in the board files or in the distro config. Move everything to the generic Kconfig options. We're missing the distinction between i386 and x86_64, as I couldn't find any config variable that would tell us the difference. Is that really important to people? I guess not, so I left it out. Signed-off-by: Alexander Graf Reviewed-by: Tom Rini --- configs/ls2080a_emu_defconfig | 1 + configs/ls2080a_simu_defconfig | 1 + configs/thunderx_88xx_defconfig | 1 + configs/vexpress_aemv8a_dram_defconfig | 1 + configs/vexpress_aemv8a_juno_defconfig | 1 + configs/vexpress_aemv8a_semi_defconfig | 1 + configs/vexpress_ca15_tc2_defconfig | 1 + configs/vexpress_ca5x2_defconfig | 1 + configs/vexpress_ca9x4_defconfig | 1 + include/config_distro_defaults.h | 21 --------------------- include/configs/ls2080a_emu.h | 1 - include/configs/ls2080a_simu.h | 1 - include/configs/thunderx_88xx.h | 2 -- include/configs/vexpress_aemv8a.h | 2 -- include/configs/vexpress_ca15_tc2.h | 1 - include/configs/vexpress_ca5x2.h | 1 - include/configs/vexpress_ca9x4.h | 1 - net/Kconfig | 12 ++++++++++++ 18 files changed, 21 insertions(+), 30 deletions(-) (limited to 'include') diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig index f9b4eacb643..30a63818c3e 100644 --- a/configs/ls2080a_emu_defconfig +++ b/configs/ls2080a_emu_defconfig @@ -25,3 +25,4 @@ CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_BOOTP_VCI_STRING="U-Boot.LS2080A-EMU" diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig index 728fa255496..a095b8ac484 100644 --- a/configs/ls2080a_simu_defconfig +++ b/configs/ls2080a_simu_defconfig @@ -28,3 +28,4 @@ CONFIG_CMD_FAT=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_BOOTP_VCI_STRING="U-Boot.LS2080A-SIMU" diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig index b7078e03906..cb33f601bb6 100644 --- a/configs/thunderx_88xx_defconfig +++ b/configs/thunderx_88xx_defconfig @@ -22,3 +22,4 @@ CONFIG_DEBUG_UART_BASE=0x87e024000000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_REGEX=y +CONFIG_BOOTP_VCI_STRING="Diagnostics" diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig index 989f06880ec..c0708b288e2 100644 --- a/configs/vexpress_aemv8a_dram_defconfig +++ b/configs/vexpress_aemv8a_dram_defconfig @@ -24,3 +24,4 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y CONFIG_DM=y CONFIG_OF_LIBFDT=y +CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a" diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index c70851fc4c1..5af9f582333 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -24,3 +24,4 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y CONFIG_DM=y CONFIG_OF_LIBFDT=y +CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a" diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index b0a2f6710ae..379dff24991 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -24,3 +24,4 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y CONFIG_DM=y CONFIG_OF_LIBFDT=y +CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a" diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig index 2f141dda06c..c39faaa67a9 100644 --- a/configs/vexpress_ca15_tc2_defconfig +++ b/configs/vexpress_ca15_tc2_defconfig @@ -24,3 +24,4 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_LIBFDT=y +CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca15x2_tc2" diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig index c495ee589c3..e71d45ed055 100644 --- a/configs/vexpress_ca5x2_defconfig +++ b/configs/vexpress_ca5x2_defconfig @@ -24,3 +24,4 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_LIBFDT=y +CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca5x2" diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index fcd6e26db5f..20100a30758 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -24,3 +24,4 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_LIBFDT=y +CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca9x4" diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h index 766a212b970..dfc2cbc0223 100644 --- a/include/config_distro_defaults.h +++ b/include/config_distro_defaults.h @@ -20,27 +20,6 @@ #define CONFIG_BOOTP_PXE #define CONFIG_BOOTP_SUBNETMASK -#if defined(__arm__) || defined(__aarch64__) -#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 -#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) -#if !defined(CONFIG_BOOTP_VCI_STRING) -#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7" -#endif -#elif defined(__aarch64__) -#if !defined(CONFIG_BOOTP_VCI_STRING) -#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv8" -#endif -#else -#if !defined(CONFIG_BOOTP_VCI_STRING) -#define CONFIG_BOOTP_VCI_STRING "U-Boot.arm" -#endif -#endif -#elif defined(__i386__) -#define CONFIG_BOOTP_PXE_CLIENTARCH 0x0 -#elif defined(__x86_64__) -#define CONFIG_BOOTP_PXE_CLIENTARCH 0x9 -#endif - #ifdef CONFIG_ARM64 #define CONFIG_CMD_BOOTI #endif diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h index f4ace856b87..16e37bff4fe 100644 --- a/include/configs/ls2080a_emu.h +++ b/include/configs/ls2080a_emu.h @@ -10,7 +10,6 @@ #include "ls2080a_common.h" #define CONFIG_IDENT_STRING " LS2080A-EMU" -#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-EMU" #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h index bc0d678bf4f..7563aafbc62 100644 --- a/include/configs/ls2080a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -10,7 +10,6 @@ #include "ls2080a_common.h" #define CONFIG_IDENT_STRING " LS2080A-SIMU" -#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-SIMU" #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 7c35d8cd468..e43a7fdf3cf 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -17,7 +17,6 @@ #define CONFIG_IDENT_STRING \ " for Cavium Thunder CN88XX ARM v8 Multi-Core" -#define CONFIG_BOOTP_VCI_STRING "Diagnostics" #define MEM_BASE 0x00500000 @@ -62,7 +61,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_PXE -#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR (MEM_BASE) diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 1b5fc2ee821..6a3758216fd 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -23,7 +23,6 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_IDENT_STRING " vexpress_aemv8a" -#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv8.vexpress_aemv8a" /* Link Definitions */ #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ @@ -146,7 +145,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_PXE -#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h index 883e58e6602..b509a9cfd4e 100644 --- a/include/configs/vexpress_ca15_tc2.h +++ b/include/configs/vexpress_ca15_tc2.h @@ -12,7 +12,6 @@ #define __VEXPRESS_CA15X2_TC2_h #define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP -#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7.vexpress_ca15x2_tc2" #include "vexpress_common.h" #define CONFIG_SYSFLAGS_ADDR 0x1c010030 diff --git a/include/configs/vexpress_ca5x2.h b/include/configs/vexpress_ca5x2.h index 43850272a6b..20b92dc8884 100644 --- a/include/configs/vexpress_ca5x2.h +++ b/include/configs/vexpress_ca5x2.h @@ -12,7 +12,6 @@ #define __VEXPRESS_CA5X2_h #define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP -#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7.vexpress_ca5x2" #include "vexpress_common.h" #endif /* __VEXPRESS_CA5X2_h */ diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h index 99be50a5bd8..993398ccc69 100644 --- a/include/configs/vexpress_ca9x4.h +++ b/include/configs/vexpress_ca9x4.h @@ -12,7 +12,6 @@ #define __VEXPRESS_CA9X4_H #define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP -#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7.vexpress_ca9x4" #include "vexpress_common.h" #endif /* VEXPRESS_CA9X4_H */ diff --git a/net/Kconfig b/net/Kconfig index a44a783cae2..64fd0f94bf4 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -32,4 +32,16 @@ config NET_TFTP_VARS If unset, timeout and maximum are hard-defined as 1 second and 10 timouts per TFTP transfer. +config BOOTP_PXE_CLIENTARCH + hex + default 0x100 if ARM + default 0 if X86 + +config BOOTP_VCI_STRING + string + default "U-Boot.armv7" if CPU_V7 || CPU_V7M + default "U-Boot.armv8" if ARM64 + default "U-Boot.arm" if ARM + default "U-Boot" + endif # if NET -- cgit v1.3.1 From 3c2d75269cb4c94c445be2f77adcbca4add70893 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 14 May 2016 14:03:02 -0600 Subject: rockchip: Drop SPL GPIO support for rk3288 This is not currently used and saves a little over 1KB of SPL image size. Signed-off-by: Simon Glass --- include/configs/rk3288_common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 8a813972905..9d50d834db4 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -69,7 +69,6 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_PINCTRL_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_RAM_SUPPORT #define CONFIG_SPL_DRIVERS_MISC_SUPPORT -- cgit v1.3.1 From 487d756f78629f5e9465c7ace2c14ef51401bc3b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 14 May 2016 14:03:05 -0600 Subject: dm: efi: Update for CONFIG_BLK This code does not currently build with driver model enabled for block devices. Update it to correct this. Signed-off-by: Simon Glass Reviewed-by: Alexander Graf --- include/efi_loader.h | 2 +- lib/efi_loader/efi_disk.c | 61 +++++++++++++++++++++++++++++++++++------------ 2 files changed, 47 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index 88b8149b147..44a950f4842 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -134,7 +134,7 @@ uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type, int efi_memory_init(void); /* Convert strings from normal C strings to uEFI strings */ -static inline void ascii2unicode(u16 *unicode, char *ascii) +static inline void ascii2unicode(u16 *unicode, const char *ascii) { while (*ascii) *(unicode++) = *(ascii++); diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index 075fd340145..3095bcfa2bf 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -96,9 +97,9 @@ static efi_status_t EFIAPI efi_disk_rw_blocks(struct efi_block_io *this, return EFI_EXIT(EFI_DEVICE_ERROR); if (direction == EFI_DISK_READ) - n = desc->block_read(desc, lba, blocks, buffer); + n = blk_dread(desc, lba, blocks, buffer); else - n = desc->block_write(desc, lba, blocks, buffer); + n = blk_dwrite(desc, lba, blocks, buffer); /* We don't do interrupts, so check for timers cooperatively */ efi_timer_check(); @@ -142,8 +143,8 @@ static const struct efi_block_io block_io_disk_template = { .flush_blocks = &efi_disk_flush_blocks, }; -static void efi_disk_add_dev(char *name, - const struct blk_driver *cur_drvr, +static void efi_disk_add_dev(const char *name, + const char *if_typename, const struct blk_desc *desc, int dev_index, lbaint_t offset) @@ -161,7 +162,7 @@ static void efi_disk_add_dev(char *name, diskobj->parent.protocols[1].open = efi_disk_open_dp; diskobj->parent.handle = diskobj; diskobj->ops = block_io_disk_template; - diskobj->ifname = cur_drvr->if_typename; + diskobj->ifname = if_typename; diskobj->dev_index = dev_index; diskobj->offset = offset; @@ -190,7 +191,7 @@ static void efi_disk_add_dev(char *name, } static int efi_disk_create_eltorito(struct blk_desc *desc, - const struct blk_driver *cur_drvr, + const char *if_typename, int diskid) { int disks = 0; @@ -203,9 +204,10 @@ static int efi_disk_create_eltorito(struct blk_desc *desc, return 0; while (!part_get_info(desc, part, &info)) { - snprintf(devname, sizeof(devname), "%s%d:%d", - cur_drvr->if_typename, diskid, part); - efi_disk_add_dev(devname, cur_drvr, desc, diskid, info.start); + snprintf(devname, sizeof(devname), "%s%d:%d", if_typename, + diskid, part); + efi_disk_add_dev(devname, if_typename, desc, diskid, + info.start); part++; disks++; } @@ -219,21 +221,49 @@ static int efi_disk_create_eltorito(struct blk_desc *desc, * EFI payload, we scan through all of the potentially available ones and * store them in our object pool. * + * TODO(sjg@chromium.org): Actually with CONFIG_BLK, U-Boot does have this. + * Consider converting the code to look up devices as needed. The EFI device + * could be a child of the UCLASS_BLK block device, perhaps. + * * This gets called from do_bootefi_exec(). */ int efi_disk_register(void) { - const struct blk_driver *cur_drvr; - int i, if_type; int disks = 0; +#ifdef CONFIG_BLK + struct udevice *dev; + + for (uclass_first_device(UCLASS_BLK, &dev); + dev; + uclass_next_device(&dev)) { + struct blk_desc *desc = dev_get_uclass_platdata(dev); + const char *if_typename = dev->driver->name; + + printf("Scanning disk %s...\n", dev->name); + efi_disk_add_dev(dev->name, if_typename, desc, desc->devnum, 0); + disks++; + + /* + * El Torito images show up as block devices in an EFI world, + * so let's create them here + */ + disks += efi_disk_create_eltorito(desc, if_typename, + desc->devnum); + } +#else + int i, if_type; /* Search for all available disk devices */ for (if_type = 0; if_type < IF_TYPE_COUNT; if_type++) { + const struct blk_driver *cur_drvr; + const char *if_typename; + cur_drvr = blk_driver_lookup_type(if_type); if (!cur_drvr) continue; - printf("Scanning disks on %s...\n", cur_drvr->if_typename); + if_typename = cur_drvr->if_typename; + printf("Scanning disks on %s...\n", if_typename); for (i = 0; i < 4; i++) { struct blk_desc *desc; char devname[32] = { 0 }; /* dp->str is u16[32] long */ @@ -245,17 +275,18 @@ int efi_disk_register(void) continue; snprintf(devname, sizeof(devname), "%s%d", - cur_drvr->if_typename, i); - efi_disk_add_dev(devname, cur_drvr, desc, i, 0); + if_typename, i); + efi_disk_add_dev(devname, if_typename, desc, i, 0); disks++; /* * El Torito images show up as block devices * in an EFI world, so let's create them here */ - disks += efi_disk_create_eltorito(desc, cur_drvr, i); + disks += efi_disk_create_eltorito(desc, if_typename, i); } } +#endif printf("Found %d disks\n", disks); return 0; -- cgit v1.3.1 From 5e6ff810c3bfeec2e81cc1117a2c1514416d947d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 14 May 2016 14:03:07 -0600 Subject: dm: mmc: dwmmc: Support CONFIG_BLK Add support for using driver model for block devices in this driver. Signed-off-by: Simon Glass --- drivers/mmc/dw_mmc.c | 42 ++++++++++++++++++++++++++++-------------- include/dwmmc.h | 7 ++++++- 2 files changed, 34 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 7329f40d345..74a2663c8bf 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -454,27 +454,40 @@ static const struct mmc_ops dwmci_ops = { .init = dwmci_init, }; -int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) +void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, + uint caps, u32 max_clk, u32 min_clk) { - host->cfg.name = host->name; - host->cfg.ops = &dwmci_ops; - host->cfg.f_min = min_clk; - host->cfg.f_max = max_clk; + cfg->name = name; + cfg->ops = &dwmci_ops; + cfg->f_min = min_clk; + cfg->f_max = max_clk; - host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - host->cfg.host_caps = host->caps; + cfg->host_caps = caps; - if (host->buswidth == 8) { - host->cfg.host_caps |= MMC_MODE_8BIT; - host->cfg.host_caps &= ~MMC_MODE_4BIT; + if (buswidth == 8) { + cfg->host_caps |= MMC_MODE_8BIT; + cfg->host_caps &= ~MMC_MODE_4BIT; } else { - host->cfg.host_caps |= MMC_MODE_4BIT; - host->cfg.host_caps &= ~MMC_MODE_8BIT; + cfg->host_caps |= MMC_MODE_4BIT; + cfg->host_caps &= ~MMC_MODE_8BIT; } - host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; + cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; + + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; +} - host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; +#ifdef CONFIG_BLK +int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) +{ + return mmc_bind(dev, mmc, cfg); +} +#else +int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) +{ + dwmci_setup_cfg(&host->cfg, host->name, host->buswidth, host->caps, + max_clk, min_clk); host->mmc = mmc_create(&host->cfg, host); if (host->mmc == NULL) @@ -482,3 +495,4 @@ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) return 0; } +#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index 05b0817fe1e..335af51fdf4 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -180,8 +180,9 @@ struct dwmci_host { * @freq: Frequency the host is trying to achieve */ unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq); - +#ifndef CONFIG_BLK struct mmc_config cfg; +#endif /* use fifo mode to read and write data */ bool fifo_mode; @@ -223,5 +224,9 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg) return readb(host->ioaddr + reg); } +void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, + uint caps, u32 max_clk, u32 min_clk); +int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); + int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); #endif /* __DWMMC_HW_H */ -- cgit v1.3.1 From fa96f37ec5835aa685f7beb0af4fef12e9001027 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Fri, 6 May 2016 21:01:04 +0200 Subject: net: Fix client identifiers for ARM There are client identifiers specifically reserved for ARM U-Boot according to http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml#processor-architecture. So let's actually make use of them rather than the bogus 0x100 that we emitted so far. Signed-off-by: Alexander Graf Reviewed-by: Tom Rini [trini: Drop the Xilinx define to 0x100 as it's not the correct value to use]. Signed-off-by: Tom Rini --- include/configs/xilinx_zynqmp.h | 1 - net/Kconfig | 3 ++- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index b2fa164f652..ffb6b34d57c 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -80,7 +80,6 @@ #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_PXE #define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 /* Diff from config_distro_defaults.h */ #define CONFIG_SUPPORT_RAW_INITRD diff --git a/net/Kconfig b/net/Kconfig index 64fd0f94bf4..414c5497c75 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -34,7 +34,8 @@ config NET_TFTP_VARS config BOOTP_PXE_CLIENTARCH hex - default 0x100 if ARM + default 0x16 if ARM64 + default 0x15 if ARM default 0 if X86 config BOOTP_VCI_STRING -- cgit v1.3.1 From 20898ea9340a4fd1631a4057b8de011b9f166255 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Fri, 6 May 2016 21:01:07 +0200 Subject: distro: Add efi pxe boot code Now that we can expose network functionality to EFI applications, the logical next step is to load them via pxe to execute them as well. This patch adds the necessary bits to the distro script to automatically load and execute EFI payloads. It identifies the dhcp client as a uEFI capable PXE client, hoping the server returns a tftp path to a workable EFI binary that we can then execute. To enable boards that don't come with a working device tree preloaded, this patch also adds support to load a device tree from the /dtb directory on the remote tftp server. Signed-off-by: Alexander Graf Reviewed-by: Tom Rini --- include/config_distro_bootcmd.h | 47 ++++++++++++++++++++++++++++++++++++++++- net/bootp.c | 13 ++++++++++-- 2 files changed, 57 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 5a8d7f27086..4db6faa7bb8 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -230,13 +230,58 @@ #endif #if defined(CONFIG_CMD_DHCP) +#if defined(CONFIG_EFI_LOADER) +#if defined(CONFIG_ARM64) +#define BOOTENV_EFI_PXE_ARCH "0xb" +#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00011:UNDI:003000" +#elif defined(CONFIG_ARM) +#define BOOTENV_EFI_PXE_ARCH "0xa" +#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00010:UNDI:003000" +#elif defined(CONFIG_X86) +/* Always assume we're running 64bit */ +#define BOOTENV_EFI_PXE_ARCH "0x7" +#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00007:UNDI:003000" +#else +#error Please specify an EFI client identifier +#endif + +/* + * Ask the dhcp server for an EFI binary. If we get one, check for a + * device tree in the same folder. Then boot everything. If the file was + * not an EFI binary, we just return from the bootefi command and continue. + */ +#define BOOTENV_EFI_RUN_DHCP \ + "setenv efi_fdtfile ${fdtfile}; " \ + BOOTENV_EFI_SET_FDTFILE_FALLBACK \ + "setenv efi_old_vci ${bootp_vci};" \ + "setenv efi_old_arch ${bootp_arch};" \ + "setenv bootp_vci " BOOTENV_EFI_PXE_VCI ";" \ + "setenv bootp_arch " BOOTENV_EFI_PXE_ARCH ";" \ + "if dhcp ${kernel_addr_r}; then " \ + "tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};" \ + "if fdt addr ${fdt_addr_r}; then " \ + "bootefi ${kernel_addr_r} ${fdt_addr_r}; " \ + "else " \ + "bootefi ${kernel_addr_r} ${fdtcontroladdr};" \ + "fi;" \ + "fi;" \ + "setenv bootp_vci ${efi_old_vci};" \ + "setenv bootp_arch ${efi_old_arch};" \ + "setenv efi_fdtfile;" \ + "setenv efi_old_arch;" \ + "setenv efi_old_vci;" +#else +#define BOOTENV_EFI_RUN_DHCP +#endif #define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \ "bootcmd_dhcp=" \ BOOTENV_RUN_NET_USB_START \ BOOTENV_RUN_NET_PCI_ENUM \ "if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \ "source ${scriptaddr}; " \ - "fi\0" + "fi;" \ + BOOTENV_EFI_RUN_DHCP \ + "\0" #define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \ "dhcp " #else diff --git a/net/bootp.c b/net/bootp.c index d718e35b63e..85dc524df4f 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -413,12 +413,21 @@ static void bootp_timeout_handler(void) static u8 *add_vci(u8 *e) { + char *vci = NULL; + char *env_vci = getenv("bootp_vci"); + #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING) - put_vci(e, CONFIG_SPL_NET_VCI_STRING); + vci = CONFIG_SPL_NET_VCI_STRING; #elif defined(CONFIG_BOOTP_VCI_STRING) - put_vci(e, CONFIG_BOOTP_VCI_STRING); + vci = CONFIG_BOOTP_VCI_STRING; #endif + if (env_vci) + vci = env_vci; + + if (vci) + put_vci(e, vci); + return e; } -- cgit v1.3.1 From bfcef28ae4cf04e7c1fd3aea1d60a17bd046f153 Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Sun, 8 May 2016 08:30:16 +0200 Subject: arm: add initial support for Amlogic Meson and ODROID-C2 This adds platform code for the Amlogic Meson GXBaby (S905) SoC and a board definition for ODROID-C2. This initial submission only supports UART and Ethernet (through the existing Designware driver). DTS files are the ones submitted to Linux arm-soc for 4.7 [1]. [1] https://patchwork.ozlabs.org/patch/603583/ Signed-off-by: Beniamino Galvani Reviewed-by: Simon Glass --- arch/arm/Kconfig | 9 ++ arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/meson-gxbb-odroidc2.dts | 69 +++++++++++++ arch/arm/dts/meson-gxbb.dtsi | 178 +++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-meson/gxbb.h | 52 ++++++++++ arch/arm/mach-meson/Kconfig | 31 ++++++ arch/arm/mach-meson/Makefile | 7 ++ arch/arm/mach-meson/board.c | 66 ++++++++++++ board/hardkernel/odroid-c2/Kconfig | 12 +++ board/hardkernel/odroid-c2/MAINTAINERS | 6 ++ board/hardkernel/odroid-c2/Makefile | 7 ++ board/hardkernel/odroid-c2/README | 60 +++++++++++ board/hardkernel/odroid-c2/odroid-c2.c | 51 ++++++++++ configs/odroid-c2_defconfig | 23 +++++ drivers/serial/Kconfig | 15 +++ drivers/serial/Makefile | 1 + drivers/serial/serial_meson.c | 162 ++++++++++++++++++++++++++++++ include/configs/odroid-c2.h | 51 ++++++++++ 19 files changed, 803 insertions(+) create mode 100644 arch/arm/dts/meson-gxbb-odroidc2.dts create mode 100644 arch/arm/dts/meson-gxbb.dtsi create mode 100644 arch/arm/include/asm/arch-meson/gxbb.h create mode 100644 arch/arm/mach-meson/Kconfig create mode 100644 arch/arm/mach-meson/Makefile create mode 100644 arch/arm/mach-meson/board.c create mode 100644 board/hardkernel/odroid-c2/Kconfig create mode 100644 board/hardkernel/odroid-c2/MAINTAINERS create mode 100644 board/hardkernel/odroid-c2/Makefile create mode 100644 board/hardkernel/odroid-c2/README create mode 100644 board/hardkernel/odroid-c2/odroid-c2.c create mode 100644 configs/odroid-c2_defconfig create mode 100644 drivers/serial/serial_meson.c create mode 100644 include/configs/odroid-c2.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5fd20b97360..7e45642f917 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -456,6 +456,13 @@ config ARCH_KEYSTONE select SUPPORT_SPL select CMD_POWEROFF +config ARCH_MESON + bool "Amlogic Meson" + help + Support for the Meson SoC family developed by Amlogic Inc., + targeted at media players and tablet computers. We currently + support the S905 (GXBaby) 64-bit SoC. + config ARCH_MX7 bool "Freescale MX7" select CPU_V7 @@ -792,6 +799,8 @@ source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/cpu/armv7/rmobile/Kconfig" +source "arch/arm/mach-meson/Kconfig" + source "arch/arm/mach-rockchip/Kconfig" source "arch/arm/mach-s5pc1xx/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index d51634584bf..ecd1887fe59 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -50,6 +50,7 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_KEYSTONE) += keystone # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD machine-$(CONFIG_KIRKWOOD) += kirkwood +machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index bd68698e967..751bbd139cb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -26,6 +26,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-jerry.dtb \ rk3288-rock2-square.dtb \ rk3036-sdk.dtb +dtb-$(CONFIG_ARCH_MESON) += \ + meson-gxbb-odroidc2.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts new file mode 100644 index 00000000000..653c2fa785c --- /dev/null +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2016 Andreas Färber + * Copyright (c) 2016 BayLibre, Inc. + * Author: Kevin Hilman + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-gxbb.dtsi" + +/ { + compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; + model = "Hardkernel ODROID-C2"; + + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&uart_AO { + status = "okay"; +}; diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi new file mode 100644 index 00000000000..832815d8046 --- /dev/null +++ b/arch/arm/dts/meson-gxbb.dtsi @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + compatible = "amlogic,meson-gxbb"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cbus: cbus@c1100000 { + compatible = "simple-bus"; + reg = <0x0 0xc1100000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; + + uart_A: serial@84c0 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x084c0 0x0 0x14>; + interrupts = ; + clocks = <&xtal>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@c4301000 { + compatible = "arm,gic-400"; + reg = <0x0 0xc4301000 0 0x1000>, + <0x0 0xc4302000 0 0x2000>, + <0x0 0xc4304000 0 0x2000>, + <0x0 0xc4306000 0 0x2000>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + aobus: aobus@c8100000 { + compatible = "simple-bus"; + reg = <0x0 0xc8100000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; + + uart_AO: serial@4c0 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x004c0 0x0 0x14>; + interrupts = ; + clocks = <&xtal>; + status = "disabled"; + }; + }; + + apb: apb@d0000000 { + compatible = "simple-bus"; + reg = <0x0 0xd0000000 0x0 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h new file mode 100644 index 00000000000..f90f632dafe --- /dev/null +++ b/arch/arm/include/asm/arch-meson/gxbb.h @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2016 - Beniamino Galvani + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __GXBB_H__ +#define __GXBB_H__ + +#define GXBB_PERIPHS_BASE 0xc8834400 +#define GXBB_HIU_BASE 0xc883c000 +#define GXBB_ETH_BASE 0xc9410000 + +/* Peripherals registers */ +#define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2)) + +/* GPIO registers 0 to 6 */ +#define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) +#define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0) +#define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1) +#define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2) + +/* Pinmux registers 0 to 12 */ +#define GXBB_PINMUX(n) GXBB_PERIPHS_ADDR(0x2c + (n)) + +#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50) +#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51) + +#define GXBB_ETH_REG_0_PHY_INTF BIT(0) +#define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) +#define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) +#define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10) +#define GXBB_ETH_REG_0_CLK_EN BIT(12) + +/* HIU registers */ +#define GXBB_HIU_ADDR(off) (GXBB_HIU_BASE + ((off) << 2)) + +#define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40) + +/* Ethernet memory power domain */ +#define GXBB_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) + +/* Clock gates */ +#define GXBB_GCLK_MPEG_0 GXBB_HIU_ADDR(0x50) +#define GXBB_GCLK_MPEG_1 GXBB_HIU_ADDR(0x51) +#define GXBB_GCLK_MPEG_2 GXBB_HIU_ADDR(0x52) +#define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53) +#define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54) + +#define GXBB_GCLK_MPEG_1_ETH BIT(3) + +#endif /* __GXBB_H__ */ diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig new file mode 100644 index 00000000000..77d3cfec596 --- /dev/null +++ b/arch/arm/mach-meson/Kconfig @@ -0,0 +1,31 @@ +if ARCH_MESON + +config MESON_GXBB + bool "Support Meson GXBaby" + select ARM64 + select DM + select DM_SERIAL + help + The Amlogic Meson GXBaby (S905) is an ARM SoC with a + quad-core Cortex-A53 CPU and a Mali-450 GPU. + +if MESON_GXBB + +config TARGET_ODROID_C2 + bool "ODROID-C2" + help + ODROID-C2 is a single board computer based on Meson GXBaby + with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD + slot, eMMC, IR receiver and a 40-pin GPIO header. + +endif + +config SYS_SOC + default "meson" + +config SYS_MALLOC_F_LEN + default 0x1000 + +source "board/hardkernel/odroid-c2/Kconfig" + +endif diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile new file mode 100644 index 00000000000..44e3d63f844 --- /dev/null +++ b/arch/arm/mach-meson/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2016 Beniamino Galvani +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += board.o diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c new file mode 100644 index 00000000000..782f86c63ec --- /dev/null +++ b/arch/arm/mach-meson/board.c @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2016 Beniamino Galvani + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + const fdt64_t *val; + int offset; + int len; + + offset = fdt_path_offset(gd->fdt_blob, "/memory"); + if (offset < 0) + return -EINVAL; + + val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); + if (len < sizeof(*val) * 2) + return -EINVAL; + + /* Use unaligned access since cache is still disabled */ + gd->ram_size = get_unaligned_be64(&val[1]); + + return 0; +} + +void dram_init_banksize(void) +{ + /* Reserve first 16 MiB of RAM for firmware */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024); + gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024); +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(true); +} + +static struct mm_region gxbb_mem_map[] = { + { + .base = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .base = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = gxbb_mem_map; diff --git a/board/hardkernel/odroid-c2/Kconfig b/board/hardkernel/odroid-c2/Kconfig new file mode 100644 index 00000000000..687d9c6d280 --- /dev/null +++ b/board/hardkernel/odroid-c2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_C2 + +config SYS_BOARD + default "odroid-c2" + +config SYS_VENDOR + default "hardkernel" + +config SYS_CONFIG_NAME + default "odroid-c2" + +endif diff --git a/board/hardkernel/odroid-c2/MAINTAINERS b/board/hardkernel/odroid-c2/MAINTAINERS new file mode 100644 index 00000000000..23ae1e7cbc7 --- /dev/null +++ b/board/hardkernel/odroid-c2/MAINTAINERS @@ -0,0 +1,6 @@ +ODROID-C2 +M: Beniamino Galvani +S: Maintained +F: board/hardkernel/odroid-c2/ +F: include/configs/odroid-c2.h +F: configs/odroid-c2_defconfig diff --git a/board/hardkernel/odroid-c2/Makefile b/board/hardkernel/odroid-c2/Makefile new file mode 100644 index 00000000000..571044b66a3 --- /dev/null +++ b/board/hardkernel/odroid-c2/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Beniamino Galvani +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := odroid-c2.o diff --git a/board/hardkernel/odroid-c2/README b/board/hardkernel/odroid-c2/README new file mode 100644 index 00000000000..d6d266a5cee --- /dev/null +++ b/board/hardkernel/odroid-c2/README @@ -0,0 +1,60 @@ +U-Boot for ODROID-C2 +==================== + +ODROID-C2 is a single board computer manufactured by Hardkernel +Co. Ltd with the following specifications: + + - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - Gigabit Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 4 x USB 2.0 Host, 1 x USB OTG + - eMMC, microSD + - Infrared receiver + +Schematics are available on the manufacturer website. + +Currently the u-boot port supports the following devices: + - serial + - Ethernet + +u-boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make odroid-c2_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > DIR=odroid-c2 + > git clone --depth 1 \ + https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \ + $DIR + > $DIR/fip/fip_create --bl30 $DIR/fip/gxb/bl30.bin \ + --bl301 $DIR/fip/gxb/bl301.bin \ + --bl31 $DIR/fip/gxb/bl31.bin \ + --bl33 u-boot.bin \ + $DIR/fip.bin + > $DIR/fip/fip_create --dump $DIR/fip.bin + > cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin + > $DIR/fip/gxb/aml_encrypt_gxb --bootsig \ + --input $DIR/boot_new.bin \ + --output $DIR/u-boot.img + > dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96 + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > BL1=$DIR/sd_fuse/bl1.bin.hardkernel + > dd if=$BL1 of=$DEV conv=fsync bs=1 count=442 + > dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1 + > dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97 diff --git a/board/hardkernel/odroid-c2/odroid-c2.c b/board/hardkernel/odroid-c2/odroid-c2.c new file mode 100644 index 00000000000..c258d4f0b80 --- /dev/null +++ b/board/hardkernel/odroid-c2/odroid-c2.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2016 Beniamino Galvani + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int board_init(void) +{ + return 0; +} + +static const struct eth_pdata gxbb_eth_pdata = { + .iobase = GXBB_ETH_BASE, + .phy_interface = PHY_INTERFACE_MODE_RGMII, +}; + +U_BOOT_DEVICE(meson_eth) = { + .name = "eth_designware", + .platdata = &gxbb_eth_pdata, +}; + +int misc_init_r(void) +{ + /* Select Ethernet function */ + setbits_le32(GXBB_PINMUX(6), 0x3fff); + + /* Set RGMII mode */ + setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF | + GXBB_ETH_REG_0_TX_PHASE(1) | + GXBB_ETH_REG_0_TX_RATIO(4) | + GXBB_ETH_REG_0_PHY_CLK_EN | + GXBB_ETH_REG_0_CLK_EN); + + /* Enable power and clock gate */ + setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); + clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); + + /* Reset PHY on GPIOZ_14 */ + clrbits_le32(GXBB_GPIO_EN(3), BIT(14)); + clrbits_le32(GXBB_GPIO_OUT(3), BIT(14)); + mdelay(10); + setbits_le32(GXBB_GPIO_OUT(3), BIT(14)); + + return 0; +} diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig new file mode 100644 index 00000000000..a771b20f5fb --- /dev/null +++ b/configs/odroid-c2_defconfig @@ -0,0 +1,23 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_MESON_GXBB=y +CONFIG_TARGET_ODROID_C2=y +CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2" +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_BASE=0xc81004c0 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 2497ae90a09..0e3890391b2 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -121,6 +121,14 @@ config DEBUG_UART_S5P will need to provide parameters to make this work. The driver will be available until the real driver-model serial is running. +config DEBUG_UART_MESON + bool "Amlogic Meson" + depends on MESON_SERIAL + help + Select this to enable a debug UART using the serial_meson driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver-model serial is running. + config DEBUG_UART_UARTLITE bool "Xilinx Uartlite" help @@ -338,6 +346,13 @@ config XILINX_UARTLITE If you have a Xilinx based board and want to use the uartlite serial ports, say Y to this option. If unsure, say N. +config MESON_SERIAL + bool "Support for Amlogic Meson UART" + depends on DM_SERIAL && ARCH_MESON + help + If you have an Amlogic Meson based board and want to use the on-chip + serial ports, say Y to this option. If unsure, say N. + config MSM_SERIAL bool "Qualcomm on-chip UART" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 9def128e890..e1e28ded30a 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P) += serial_s5p.o obj-$(CONFIG_MXC_UART) += serial_mxc.o obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o +obj-$(CONFIG_MESON_SERIAL) += serial_meson.o obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c new file mode 100644 index 00000000000..1b494265ce6 --- /dev/null +++ b/drivers/serial/serial_meson.c @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2016 Beniamino Galvani + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct meson_uart { + u32 wfifo; + u32 rfifo; + u32 control; + u32 status; + u32 misc; +}; + +struct meson_serial_platdata { + struct meson_uart *reg; +}; + +/* AML_UART_STATUS bits */ +#define AML_UART_PARITY_ERR BIT(16) +#define AML_UART_FRAME_ERR BIT(17) +#define AML_UART_TX_FIFO_WERR BIT(18) +#define AML_UART_RX_EMPTY BIT(20) +#define AML_UART_TX_FULL BIT(21) +#define AML_UART_TX_EMPTY BIT(22) +#define AML_UART_XMIT_BUSY BIT(25) +#define AML_UART_ERR (AML_UART_PARITY_ERR | \ + AML_UART_FRAME_ERR | \ + AML_UART_TX_FIFO_WERR) + +/* AML_UART_CONTROL bits */ +#define AML_UART_TX_EN BIT(12) +#define AML_UART_RX_EN BIT(13) +#define AML_UART_TX_RST BIT(22) +#define AML_UART_RX_RST BIT(23) +#define AML_UART_CLR_ERR BIT(24) + +static void meson_serial_init(struct meson_uart *uart) +{ + u32 val; + + val = readl(&uart->control); + val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR); + writel(val, &uart->control); + val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR); + writel(val, &uart->control); + val |= (AML_UART_RX_EN | AML_UART_TX_EN); + writel(val, &uart->control); +} + +static int meson_serial_probe(struct udevice *dev) +{ + struct meson_serial_platdata *plat = dev->platdata; + struct meson_uart *const uart = plat->reg; + + meson_serial_init(uart); + + return 0; +} + +static int meson_serial_getc(struct udevice *dev) +{ + struct meson_serial_platdata *plat = dev->platdata; + struct meson_uart *const uart = plat->reg; + + if (readl(&uart->status) & AML_UART_RX_EMPTY) + return -EAGAIN; + + return readl(&uart->rfifo) & 0xff; +} + +static int meson_serial_putc(struct udevice *dev, const char ch) +{ + struct meson_serial_platdata *plat = dev->platdata; + struct meson_uart *const uart = plat->reg; + + if (readl(&uart->status) & AML_UART_TX_FULL) + return -EAGAIN; + + writel(ch, &uart->wfifo); + + return 0; +} + +static int meson_serial_pending(struct udevice *dev, bool input) +{ + struct meson_serial_platdata *plat = dev->platdata; + struct meson_uart *const uart = plat->reg; + uint32_t status = readl(&uart->status); + + if (input) + return !(status & AML_UART_RX_EMPTY); + else + return !(status & AML_UART_TX_FULL); +} + +static int meson_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct meson_serial_platdata *plat = dev->platdata; + fdt_addr_t addr; + + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->reg = (struct meson_uart *)addr; + + return 0; +} + +static const struct dm_serial_ops meson_serial_ops = { + .putc = meson_serial_putc, + .pending = meson_serial_pending, + .getc = meson_serial_getc, +}; + +static const struct udevice_id meson_serial_ids[] = { + { .compatible = "amlogic,meson-uart" }, + { } +}; + +U_BOOT_DRIVER(serial_meson) = { + .name = "serial_meson", + .id = UCLASS_SERIAL, + .of_match = meson_serial_ids, + .probe = meson_serial_probe, + .ops = &meson_serial_ops, + .flags = DM_FLAG_PRE_RELOC, + .ofdata_to_platdata = meson_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct meson_serial_platdata), +}; + +#ifdef CONFIG_DEBUG_UART_MESON + +#include + +static inline void _debug_uart_init(void) +{ +} + +static inline void _debug_uart_putc(int ch) +{ + struct meson_uart *regs = (struct meson_uart *)CONFIG_DEBUG_UART_BASE; + + while (readl(®s->status) & AML_UART_TX_FULL) + ; + + writel(ch, ®s->wfifo); +} + +DEBUG_UART_FUNCS + +#endif diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h new file mode 100644 index 00000000000..37a5671ccb5 --- /dev/null +++ b/include/configs/odroid-c2.h @@ -0,0 +1,51 @@ +/* + * Configuration for ODROID-C2 + * (C) Copyright 2016 Beniamino Galvani + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_CPU_ARMV8 +#define CONFIG_REMAKE_ELF +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_MISC_INIT_R + +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_TEXT_BASE 0x01000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x20000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xc4301000 +#define GICC_BASE 0xc4302000 + +#define CONFIG_IDENT_STRING " odroid-c2" + +/* Serial setup */ +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_CMD_ENV + +/* Monitor Command Prompt */ +/* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING + +#include + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 51735ae0ea2f5d67c0f7cc4d1f938f36955e1fe7 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 11 May 2016 18:25:48 +0200 Subject: efi_loader: Add bounce buffer support Some hardware that is supported by U-Boot can not handle DMA above 32bits. For these systems, we need to come up with a way to expose the disk interface in a safe way. This patch implements EFI specific bounce buffers. For non-EFI cases, this apparently was no issue so far, since we can just define our environment variables conveniently. Signed-off-by: Alexander Graf --- include/efi_loader.h | 5 ++++ lib/efi_loader/Kconfig | 9 ++++++ lib/efi_loader/efi_disk.c | 70 +++++++++++++++++++++++++++++++++++++++------ lib/efi_loader/efi_memory.c | 16 +++++++++++ 4 files changed, 91 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index 8005454af36..b1ca4ba26b6 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -139,6 +139,11 @@ uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type, /* Called by board init to initialize the EFI memory map */ int efi_memory_init(void); +#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER +extern void *efi_bounce_buffer; +#define EFI_LOADER_BOUNCE_BUFFER_SIZE (64 * 1024 * 1024) +#endif + /* Convert strings from normal C strings to uEFI strings */ static inline void ascii2unicode(u16 *unicode, char *ascii) { diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 14c99ec9cf9..37a0dd60a5e 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -7,3 +7,12 @@ config EFI_LOADER on top of U-Boot. If this option is enabled, U-Boot will expose EFI interfaces to a loaded EFI application, enabling it to reuse U-Boot's device drivers. + +config EFI_LOADER_BOUNCE_BUFFER + bool "EFI Applications use bounce buffers for DMA operations" + depends on EFI_LOADER && ARM64 + default n + help + Some hardware does not support DMA to full 64bit addresses. For this + hardware we can create a bounce buffer so that payloads don't have to + worry about platform details. diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index 075fd340145..c7d4515321e 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -76,9 +76,6 @@ static efi_status_t EFIAPI efi_disk_rw_blocks(struct efi_block_io *this, int blocks; unsigned long n; - EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba, - buffer_size, buffer); - diskobj = container_of(this, struct efi_disk_obj, ops); if (!(desc = blk_get_dev(diskobj->ifname, diskobj->dev_index))) return EFI_EXIT(EFI_DEVICE_ERROR); @@ -95,10 +92,11 @@ static efi_status_t EFIAPI efi_disk_rw_blocks(struct efi_block_io *this, if (buffer_size & (blksz - 1)) return EFI_EXIT(EFI_DEVICE_ERROR); - if (direction == EFI_DISK_READ) + if (direction == EFI_DISK_READ) { n = desc->block_read(desc, lba, blocks, buffer); - else + } else { n = desc->block_write(desc, lba, blocks, buffer); + } /* We don't do interrupts, so check for timers cooperatively */ efi_timer_check(); @@ -116,16 +114,70 @@ static efi_status_t efi_disk_read_blocks(struct efi_block_io *this, u32 media_id, u64 lba, unsigned long buffer_size, void *buffer) { - return efi_disk_rw_blocks(this, media_id, lba, buffer_size, buffer, - EFI_DISK_READ); + void *real_buffer = buffer; + efi_status_t r; + +#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER + if (buffer_size > EFI_LOADER_BOUNCE_BUFFER_SIZE) { + r = efi_disk_read_blocks(this, media_id, lba, + EFI_LOADER_BOUNCE_BUFFER_SIZE, buffer); + if (r != EFI_SUCCESS) + return r; + return efi_disk_read_blocks(this, media_id, lba + + EFI_LOADER_BOUNCE_BUFFER_SIZE / this->media->block_size, + buffer_size - EFI_LOADER_BOUNCE_BUFFER_SIZE, + buffer + EFI_LOADER_BOUNCE_BUFFER_SIZE); + } + + real_buffer = efi_bounce_buffer; +#endif + + EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba, + buffer_size, buffer); + + r = efi_disk_rw_blocks(this, media_id, lba, buffer_size, real_buffer, + EFI_DISK_READ); + + /* Copy from bounce buffer to real buffer if necessary */ + if ((r == EFI_SUCCESS) && (real_buffer != buffer)) + memcpy(buffer, real_buffer, buffer_size); + + return EFI_EXIT(r); } static efi_status_t efi_disk_write_blocks(struct efi_block_io *this, u32 media_id, u64 lba, unsigned long buffer_size, void *buffer) { - return efi_disk_rw_blocks(this, media_id, lba, buffer_size, buffer, - EFI_DISK_WRITE); + void *real_buffer = buffer; + efi_status_t r; + +#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER + if (buffer_size > EFI_LOADER_BOUNCE_BUFFER_SIZE) { + r = efi_disk_write_blocks(this, media_id, lba, + EFI_LOADER_BOUNCE_BUFFER_SIZE, buffer); + if (r != EFI_SUCCESS) + return r; + return efi_disk_write_blocks(this, media_id, lba + + EFI_LOADER_BOUNCE_BUFFER_SIZE / this->media->block_size, + buffer_size - EFI_LOADER_BOUNCE_BUFFER_SIZE, + buffer + EFI_LOADER_BOUNCE_BUFFER_SIZE); + } + + real_buffer = efi_bounce_buffer; +#endif + + EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba, + buffer_size, buffer); + + /* Populate bounce buffer if necessary */ + if (real_buffer != buffer) + memcpy(real_buffer, buffer, buffer_size); + + r = efi_disk_rw_blocks(this, media_id, lba, buffer_size, real_buffer, + EFI_DISK_WRITE); + + return EFI_EXIT(r); } static efi_status_t EFIAPI efi_disk_flush_blocks(struct efi_block_io *this) diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 71a3d192696..9e669f51026 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -27,6 +27,10 @@ struct efi_mem_list { /* This list contains all memory map items */ LIST_HEAD(efi_mem); +#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER +void *efi_bounce_buffer; +#endif + /* * Sorts the memory list from highest address to lowest address * @@ -349,5 +353,17 @@ int efi_memory_init(void) efi_add_memory_map(runtime_start, runtime_pages, EFI_RUNTIME_SERVICES_CODE, false); +#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER + /* Request a 32bit 64MB bounce buffer region */ + uint64_t efi_bounce_buffer_addr = 0xffffffff; + + if (efi_allocate_pages(1, EFI_LOADER_DATA, + (64 * 1024 * 1024) >> EFI_PAGE_SHIFT, + &efi_bounce_buffer_addr) != EFI_SUCCESS) + return -1; + + efi_bounce_buffer = (void*)(uintptr_t)efi_bounce_buffer_addr; +#endif + return 0; } -- cgit v1.3.1 From feee28f7d744fec50f61b4d46d3dfac165316fbc Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 14 May 2016 18:49:26 -0600 Subject: openrisc: Drop the arch-specific board init It is well past the deadline for conversion to generic board init. Remove the old code. Stefan, can you test this please and perhaps send a follow-up patch if needed? Signed-off-by: Simon Glass --- arch/openrisc/lib/Makefile | 1 - arch/openrisc/lib/board.c | 140 ------------------------------------- include/configs/openrisc-generic.h | 1 + 3 files changed, 1 insertion(+), 141 deletions(-) delete mode 100644 arch/openrisc/lib/board.c (limited to 'include') diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile index dfa72d915fd..3a2f6ec2437 100644 --- a/arch/openrisc/lib/Makefile +++ b/arch/openrisc/lib/Makefile @@ -5,6 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += board.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += timer.o diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c deleted file mode 100644 index b7fbd2f1253..00000000000 --- a/arch/openrisc/lib/board.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2011 - * Julius Baxter, julius@opencores.org - * - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_STATUS_LED -#include -#endif -#ifdef CONFIG_CMD_NAND -#include /* cannot even include nand.h if it isnt configured */ -#endif - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ - -extern int cache_init(void); - -/* - * Initialization sequence - */ -static int (* const init_sequence[])(void) = { - cache_init, - timer_init, /* initialize timer */ - env_init, - serial_init, - console_init_f, - display_options, - checkcpu, - checkboard, -}; - - -/***********************************************************************/ -void board_init(void) -{ - bd_t *bd; - int i; - - gd = (gd_t *)CONFIG_SYS_GBL_DATA_ADDR; - - memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE); - - gd->bd = (bd_t *)(gd+1); /* At end of global data */ - gd->baudrate = CONFIG_BAUDRATE; - gd->cpu_clk = CONFIG_SYS_CLK_FREQ; - - bd = gd->bd; - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; -#ifndef CONFIG_SYS_NO_FLASH - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; -#endif -#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE) - bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; - bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; -#endif - - for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { - WATCHDOG_RESET(); - if (init_sequence[i]()) - hang(); - } - - WATCHDOG_RESET(); - - /* The Malloc area is immediately below the monitor copy in RAM */ - mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); - -#ifndef CONFIG_SYS_NO_FLASH - WATCHDOG_RESET(); - bd->bi_flashsize = flash_init(); -#endif - -#ifdef CONFIG_CMD_NAND - puts("NAND: "); - nand_init(); -#endif - -#ifdef CONFIG_GENERIC_MMC - puts("MMC: "); - mmc_initialize(bd); -#endif - - WATCHDOG_RESET(); - env_relocate(); - - WATCHDOG_RESET(); - stdio_init(); - jumptable_init(); - console_init_r(); - - WATCHDOG_RESET(); - interrupt_init(); - -#if defined(CONFIG_BOARD_LATE_INIT) - board_late_init(); -#endif - -#if defined(CONFIG_CMD_NET) - puts("NET: "); - eth_initialize(); -#endif - - /* main_loop */ - for (;;) { - WATCHDOG_RESET(); - main_loop(); - } -} diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h index dfb8d3a3892..14e44b0156d 100644 --- a/include/configs/openrisc-generic.h +++ b/include/configs/openrisc-generic.h @@ -10,6 +10,7 @@ /* * BOARD/CPU */ +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_CLK_FREQ 50000000 #define CONFIG_SYS_RESET_ADDR 0x00000100 -- cgit v1.3.1 From 9be2e790eb28cbb30fb16a939cb95f82ad73efe5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 14 May 2016 18:49:35 -0600 Subject: Drop use of CONFIG_SYS_GENERIC_BOARD in U-Boot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This option is always enabled and is about to be removed. Drop references to it. Signed-off-by: Simon Glass Reviewed-by: Andreas Bießmann --- common/Makefile | 4 ++-- common/main.c | 6 ------ include/watchdog.h | 3 +-- 3 files changed, 3 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/common/Makefile b/common/Makefile index 0562d5cea46..1557a044de5 100644 --- a/common/Makefile +++ b/common/Makefile @@ -26,8 +26,8 @@ obj-y += bootretry.o endif # boards -obj-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o -obj-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o +obj-y += board_f.o +obj-y += board_r.o obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o diff --git a/common/main.c b/common/main.c index 42bbb507332..2116a9e0a2e 100644 --- a/common/main.c +++ b/common/main.c @@ -47,12 +47,6 @@ void main_loop(void) bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop"); -#ifndef CONFIG_SYS_GENERIC_BOARD - puts("Warning: Your board does not use generic board. Please read\n"); - puts("doc/README.generic-board and take action. Boards not\n"); - puts("upgraded by the late 2014 may break or be removed.\n"); -#endif - #ifdef CONFIG_VERSION_VARIABLE setenv("ver", version_string); /* set version variable */ #endif /* CONFIG_VERSION_VARIABLE */ diff --git a/include/watchdog.h b/include/watchdog.h index 9273fa1e809..174c894e499 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -21,8 +21,7 @@ int init_func_watchdog_reset(void); #endif -#if defined(CONFIG_SYS_GENERIC_BOARD) && \ - (defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)) +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) #define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init, #define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset, #else -- cgit v1.3.1 From 4c794525d5c662e6b18afe69835da6662c046e08 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 14 May 2016 18:49:36 -0600 Subject: Drop references to CONFIG_SYS_GENERIC_BOARD in config files This option is no longer used so need not be enabled. Signed-off-by: Simon Glass --- arch/sh/include/asm/config.h | 2 -- include/configs/gr_cpci_ax2000.h | 1 - include/configs/gr_ep2s60.h | 1 - include/configs/gr_xc3s_1500.h | 1 - include/configs/grsim.h | 1 - include/configs/grsim_leon2.h | 1 - include/configs/openrisc-generic.h | 2 -- 7 files changed, 9 deletions(-) (limited to 'include') diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h index dd1329eef46..cd297347894 100644 --- a/arch/sh/include/asm/config.h +++ b/arch/sh/include/asm/config.h @@ -7,6 +7,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_GENERIC_BOARD - #endif diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h index f3361d02552..e6b7953c929 100644 --- a/include/configs/gr_cpci_ax2000.h +++ b/include/configs/gr_cpci_ax2000.h @@ -14,7 +14,6 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO /* diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h index 94eb7acd77a..956c0e27bda 100644 --- a/include/configs/gr_ep2s60.h +++ b/include/configs/gr_ep2s60.h @@ -15,7 +15,6 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO /* diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h index dcb72c92a14..908d545070f 100644 --- a/include/configs/gr_xc3s_1500.h +++ b/include/configs/gr_xc3s_1500.h @@ -13,7 +13,6 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO /* diff --git a/include/configs/grsim.h b/include/configs/grsim.h index 3e81f0d70d2..6a889015a36 100644 --- a/include/configs/grsim.h +++ b/include/configs/grsim.h @@ -13,7 +13,6 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO /* diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h index ab1e11d1ae3..0ebded6bd28 100644 --- a/include/configs/grsim_leon2.h +++ b/include/configs/grsim_leon2.h @@ -12,7 +12,6 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO /* diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h index 14e44b0156d..913256a02bd 100644 --- a/include/configs/openrisc-generic.h +++ b/include/configs/openrisc-generic.h @@ -10,8 +10,6 @@ /* * BOARD/CPU */ -#define CONFIG_SYS_GENERIC_BOARD - #define CONFIG_SYS_CLK_FREQ 50000000 #define CONFIG_SYS_RESET_ADDR 0x00000100 -- cgit v1.3.1 From 6384726d2dd941411bfb3253f37f61eb1afa1c21 Mon Sep 17 00:00:00 2001 From: Madan Srinivas Date: Thu, 19 May 2016 19:10:43 -0500 Subject: arm: Kconfig: Add support for AM43xx SoC specific Kconfig Adding support for AM43xx secure devices require the addition of some SOC specific config options like the amount of memory used by public ROM and the address of the entry point of u-boot or SPL, as seen by the ROM code, for the image to be built correctly. This mandates the addition of am AM43xx CONFIG option and the ARM Kconfig file has been modified to source this SOC Kconfig file. Moving the TARGET_AM43XX_EVM config option to the SOC KConfig and out of the arch/arm/Kconfig. Updating defconfigs to add the CONFIG_AM43XX=y statement and removing the #define CONFIG_AM43XX from the header file. Signed-off-by: Madan Srinivas Signed-off-by: Daniel Allred Tested-by: Andreas Dannenberg Reviewed-by: Tom Rini --- arch/arm/Kconfig | 19 +++++++++++++------ arch/arm/cpu/armv7/am33xx/Kconfig | 13 +++++++++++++ configs/am437x_gp_evm_defconfig | 1 + configs/am437x_sk_evm_defconfig | 1 + configs/am43xx_evm_defconfig | 1 + configs/am43xx_evm_ethboot_defconfig | 1 + configs/am43xx_evm_qspiboot_defconfig | 1 + configs/am43xx_evm_usbhost_boot_defconfig | 1 + include/configs/am43xx_evm.h | 2 -- 9 files changed, 32 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7e45642f917..2f1b300a8ec 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -381,12 +381,6 @@ config TARGET_AM335X_SL50 select DM select DM_SERIAL -config TARGET_AM43XX_EVM - bool "Support am43xx_evm" - select CPU_V7 - select SUPPORT_SPL - select TI_I2C_BOARD_DETECT - config TARGET_BAV335X bool "Support bav335x" select CPU_V7 @@ -514,6 +508,17 @@ config OMAP54XX select CPU_V7 select SUPPORT_SPL +config AM43XX + bool "AM43XX SoC" + select CPU_V7 + select SUPPORT_SPL + help + Support for AM43xx SOC from Texas Instruments. + The AM43xx high performance SOC features a Cortex-A9 + ARM core, a quad core PRU-ICSS for industrial Ethernet + protocols, dual camera support, optional 3D graphics + and an optional customer programmable secure boot. + config RMOBILE bool "Renesas ARM SoCs" select CPU_V7 @@ -795,6 +800,8 @@ source "arch/arm/cpu/armv7/omap4/Kconfig" source "arch/arm/cpu/armv7/omap5/Kconfig" +source "arch/arm/cpu/armv7/am33xx/Kconfig" + source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/cpu/armv7/rmobile/Kconfig" diff --git a/arch/arm/cpu/armv7/am33xx/Kconfig b/arch/arm/cpu/armv7/am33xx/Kconfig index 39759cd522f..dc51e9b6978 100644 --- a/arch/arm/cpu/armv7/am33xx/Kconfig +++ b/arch/arm/cpu/armv7/am33xx/Kconfig @@ -1,3 +1,15 @@ +if AM43XX +config TARGET_AM43XX_EVM + bool "Support am43xx_evm" + select TI_I2C_BOARD_DETECT + help + This option specifies support for the AM43xx + GP and HS EVM development platforms.The AM437x + GP EVM is a standalone test, development, and + evaluation module system that enables developers + to write software and develop hardware around + an AM43xx processor subsystem. + config ISW_ENTRY_ADDR hex "Address in memory or XIP flash of bootloader entry point" help @@ -25,3 +37,4 @@ config PUB_ROM_DATA_SIZE image, this area is no longer used, and can be reclaimed for run time use by the boot image. default 0x8400 +endif diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig index ef4c248dead..e98412a5095 100644 --- a/configs/am437x_gp_evm_defconfig +++ b/configs/am437x_gp_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_AM43XX=y CONFIG_TARGET_AM43XX_EVM=y CONFIG_DM_SERIAL=y CONFIG_DM_GPIO=y diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig index 8c1e09aca1a..b6653310cf6 100644 --- a/configs/am437x_sk_evm_defconfig +++ b/configs/am437x_sk_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_AM43XX=y CONFIG_TARGET_AM43XX_EVM=y CONFIG_DM_SERIAL=y CONFIG_DM_SPI=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 4911b615b50..12d3fb78b35 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_AM43XX=y CONFIG_TARGET_AM43XX_EVM=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND" diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig index ee4716dd1c9..33fb552fc55 100644 --- a/configs/am43xx_evm_ethboot_defconfig +++ b/configs/am43xx_evm_ethboot_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_AM43XX=y CONFIG_TARGET_AM43XX_EVM=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_ETH_SUPPORT" diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index 4d182318ded..4bc75e71177 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_AM43XX=y CONFIG_TARGET_AM43XX_EVM=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT" CONFIG_HUSH_PARSER=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index c3364193488..32a07edccfb 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_AM43XX=y CONFIG_TARGET_AM43XX_EVM=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT" diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 5b49988db78..a35541bca91 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_AM43XX_EVM_H #define __CONFIG_AM43XX_EVM_H -#define CONFIG_AM43XX - #define CONFIG_BOARD_LATE_INIT #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_CACHELINE_SIZE 32 -- cgit v1.3.1 From 9aac7d0ec96923a39f8d234f82b82bec5c13f183 Mon Sep 17 00:00:00 2001 From: Madan Srinivas Date: Thu, 19 May 2016 19:10:47 -0500 Subject: ti: AM43xx: Use CONFIG options from SOC Kconfig Updates configs/am43xx_evm.h to use CONFIG options from SOC specific Kconfig file for various calculations. On AM43x devices, the address of SPL entry point depends on the device type, i.e. whether it is secure or non-secure. Further, for non-secure devices, the SPL entry point is different between USB HOST boot mode, other "memory" boot modes (MMC, NAND) and "peripheral" boot modes (UART, USB) To add to the complexity, on secure devices, in addition to the above differences, the SPL entry point can change because of the space occupied by other components (other than u-boot or spl) that go into a secure boot image. To prevent the user from having to modify source files every time any component of the secure image changes, the value of CONFIG_SPL_TEXT_BASE has been set using a Kconfig option that is supplied in the am43xx_*_defconfig files Using the CONFIG options also enables us to do away with some compile time flags that were used to specify CONFIG_SPL_TEXT_BASE for different boot modes. On QSPI devices, the same problem described above occurs w.r.t. the address of the u-boot entry point in flash, when booting secure devices. To handle this, CONFIG_SYS_TEXT_BASE is also setup via a Kconfig option and the defconfig files. Signed-off-by: Madan Srinivas Signed-off-by: Daniel Allred Reviewed-by: Lokesh Vutla Tested-by: Andreas Dannenberg Reviewed-by: Tom Rini --- configs/am43xx_evm_qspiboot_defconfig | 1 + configs/am43xx_evm_usbhost_boot_defconfig | 1 + include/configs/am43xx_evm.h | 19 +++++++------------ 3 files changed, 9 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index 4bc75e71177..5f90e2bef1c 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_AM43XX=y CONFIG_TARGET_AM43XX_EVM=y +CONFIG_ISW_ENTRY_ADDR=0x30000000 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 32a07edccfb..1f731146500 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_AM43XX=y CONFIG_TARGET_AM43XX_EVM=y CONFIG_SPL=y +CONFIG_ISW_ENTRY_ADDR=0x40300350 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index a35541bca91..8a48a9aa37b 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -37,17 +37,10 @@ #define CONFIG_POWER_TPS62362 /* SPL defines. */ -#ifdef CONFIG_SPL_USB_HOST_SUPPORT -/* - * For USB host boot, ROM uses DMA for copying MLO from USB storage - * and ARM internal ram is not accessible for DMA, so SPL text base - * should be in OCMC ram - */ -#define CONFIG_SPL_TEXT_BASE 0x40300350 -#else -#define CONFIG_SPL_TEXT_BASE 0x402F4000 -#endif -#define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */ +#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR +#define CONFIG_SPL_MAX_SIZE (NON_SECURE_SRAM_END - \ + CONFIG_PUB_ROM_DATA_SIZE - \ + CONFIG_SPL_TEXT_BASE) #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ (128 << 20)) #define CONFIG_SPL_POWER_SUPPORT @@ -190,7 +183,9 @@ #endif #ifdef CONFIG_QSPI_BOOT -#define CONFIG_SYS_TEXT_BASE 0x30000000 +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE CONFIG_ISW_ENTRY_ADDR +#endif #undef CONFIG_ENV_IS_IN_FAT #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_SYS_REDUNDAND_ENVIRONMENT -- cgit v1.3.1 From a5051b727eaf098a18cf0e77f2cd8e61b71c888a Mon Sep 17 00:00:00 2001 From: Madan Srinivas Date: Thu, 19 May 2016 19:10:48 -0500 Subject: ti: AM43xx: board: Detect AM43xx HS EVM Adds code to detect AM43xx HS EVMS - the string in the I2C EEPROM for HS EVMs differs from GP EVMs. Adds code to for evm detection, regardless of whether the evm is for GP or HS parts, and updates board init to use that. Modifies findfdt command to pick up am437x-gp-evm.dtb for the HS EVMs also, as the boards are similar except for some security specific changes around power supply and enclosure protection. Signed-off-by: Madan Srinivas Signed-off-by: Daniel Allred Signed-off-by: Andreas Dannenberg Reviewed-by: Lokesh Vutla Reviewed-by: Tom Rini --- board/ti/am43xx/board.c | 4 ++-- board/ti/am43xx/board.h | 14 ++++++++++++-- board/ti/am43xx/mux.c | 2 +- include/configs/am43xx_evm.h | 2 ++ 4 files changed, 17 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index d208d2fa891..724710763d6 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -341,7 +341,7 @@ const struct dpll_params *get_dpll_ddr_params(void) if (board_is_eposevm()) return &epos_evm_dpll_ddr[ind]; - else if (board_is_gpevm() || board_is_sk()) + else if (board_is_evm() || board_is_sk()) return &gp_evm_dpll_ddr; else if (board_is_idk()) return &idk_dpll_ddr; @@ -553,7 +553,7 @@ void sdram_init(void) enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz_beta, 0); - } else if (board_is_gpevm()) { + } else if (board_is_evm()) { enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz, 0); diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 2cf7a7751d4..3f93d137270 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -37,14 +37,24 @@ static inline int board_is_idk(void) return board_ti_is("AM43_IDK"); } +static inline int board_is_hsevm(void) +{ + return board_ti_is("AM43XXHS"); +} + +static inline int board_is_evm(void) +{ + return board_is_gpevm() || board_is_hsevm(); +} + static inline int board_is_evm_14_or_later(void) { - return (board_is_gpevm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0); + return board_is_evm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0; } static inline int board_is_evm_12_or_later(void) { - return (board_is_gpevm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0); + return board_is_evm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0; } void enable_uart0_pin_mux(void); diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index e03b1bcfaaa..f26b21e8695 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -126,7 +126,7 @@ void enable_board_pin_mux(void) configure_module_pin_mux(i2c0_pin_mux); configure_module_pin_mux(mdio_pin_mux); - if (board_is_gpevm()) { + if (board_is_evm()) { configure_module_pin_mux(gpio5_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); #if defined(CONFIG_NAND) diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 8a48a9aa37b..a54303df5c8 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -289,6 +289,8 @@ "setenv fdtfile am43x-epos-evm.dtb; fi; " \ "if test $board_name = AM43__GP; then " \ "setenv fdtfile am437x-gp-evm.dtb; fi; " \ + "if test $board_name = AM43XXHS; then " \ + "setenv fdtfile am437x-gp-evm.dtb; fi; " \ "if test $board_name = AM43__SK; then " \ "setenv fdtfile am437x-sk-evm.dtb; fi; " \ "if test $board_name = AM43_IDK; then " \ -- cgit v1.3.1 From b9b8403f4934c3236a6c8f515c6672e4714236f9 Mon Sep 17 00:00:00 2001 From: Daniel Allred Date: Thu, 19 May 2016 19:10:50 -0500 Subject: ti_omap5_common: Update SPL start address on secure parts Updated the CONFIG_SPL_TEXT_BASE to support secure parts (moving the start address past secure reserved memory and the size of the security certificate that precedes the boot image on secure devices). Updated the related CONFIG_SPL_MAX_SIZE to properly reflect the internal memory actually available on the various device flavors (Common minimum internal RAM guaranteed for various flavors of DRA7xx/AM57xx is 512KB). Signed-off-by: Daniel Allred Signed-off-by: Madan Srinivas Reviewed-by: Tom Rini --- include/configs/ti_omap5_common.h | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 2135af0db73..5c5a12d493c 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -130,13 +130,35 @@ /* * SPL related defines. The Public RAM memory map the ROM defines the - * area between 0x40300000 and 0x4031E000 as a download area for OMAP5 - * (dra7xx is larger, but we do not need to be larger at this time). We - * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and + * area between 0x40300000 and 0x4031E000 as a download area for OMAP5. + * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000. + * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and * print some information. */ -#define CONFIG_SPL_TEXT_BASE 0x40300000 -#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE) +#ifdef CONFIG_TI_SECURE_DEVICE +/* + * For memory booting on HS parts, the first 4KB of the internal RAM is + * reserved for secure world use and the flash loader image is + * preceded by a secure certificate. The SPL will therefore run in internal + * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)). + */ +#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000 +#define CONFIG_SPL_TEXT_BASE 0x40301350 +#else +/* + * For all booting on GP parts, the flash loader image is + * downloaded into internal RAM at address 0x40300000. + */ +#define CONFIG_SPL_TEXT_BASE 0x40300000 +#endif + +/* DRA7xx/AM57xx have 512K of SRAM, OMAP5 only 128K */ +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#define TI_ROM_BOOT_LOAD_END 0x4037E000 +#else +#define TI_ROM_BOOT_LOAD_END 0x4031E000 +#endif +#define CONFIG_SPL_MAX_SIZE (TI_ROM_BOOT_LOAD_END - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_DISPLAY_PRINT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ -- cgit v1.3.1 From eafd5410af2ade58f25da707edaba85e44999621 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 24 May 2016 10:34:38 +0530 Subject: spl: Allow to load a FIT containing U-Boot from FS This provides a way to load a FIT containing U-Boot and a selection of device tree files from a File system. Making sure that all the reads and writes are aligned to their respective needs. Tested-by: Michal Simek Reviewed-by: Simon Glass Reviewed-by: Tom Rini Signed-off-by: Lokesh Vutla [trini: Make this still apply with Michal's alignment change for 'fit'] Signed-off-by: Tom Rini --- common/spl/spl_fit.c | 72 ++++++++++++++++++++++++++++++++++++++++++---------- common/spl/spl_mmc.c | 1 + include/spl.h | 12 +++++++++ 3 files changed, 71 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 79cc06ed0b5..fb69f1d1685 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -87,6 +87,42 @@ static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp) return -ENOENT; } +static int get_aligned_image_offset(struct spl_load_info *info, int offset) +{ + /* + * If it is a FS read, get the first address before offset which is + * aligned to ARCH_DMA_MINALIGN. If it is raw read return the + * block number to which offset belongs. + */ + if (info->filename) + return offset & ~(ARCH_DMA_MINALIGN - 1); + + return offset / info->bl_len; +} + +static int get_aligned_image_overhead(struct spl_load_info *info, int offset) +{ + /* + * If it is a FS read, get the difference between the offset and + * the first address before offset which is aligned to + * ARCH_DMA_MINALIGN. If it is raw read return the offset within the + * block. + */ + if (info->filename) + return offset & (ARCH_DMA_MINALIGN - 1); + + return offset % info->bl_len; +} + +static int get_aligned_image_size(struct spl_load_info *info, int data_size, + int offset) +{ + if (info->filename) + return data_size + get_aligned_image_overhead(info, offset); + + return (data_size + info->bl_len - 1) / info->bl_len; +} + int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit) { int sectors; @@ -96,7 +132,7 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit) void *load_ptr; int fdt_offset, fdt_len; int data_offset, data_size; - int base_offset; + int base_offset, align_len = ARCH_DMA_MINALIGN - 1; int src_sector; void *dst; @@ -124,7 +160,7 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit) */ fit = (void *)(CONFIG_SYS_TEXT_BASE - size - info->bl_len); fit = (void *)ALIGN((ulong)fit, 8); - sectors = (size + info->bl_len - 1) / info->bl_len; + sectors = get_aligned_image_size(info, size, 0); count = info->read(info, sector, sectors, fit); debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n", sector, sectors, fit, count); @@ -157,19 +193,23 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit) * byte will be at 'load'. This may mean we need to load it starting * before then, since we can only read whole blocks. */ - sectors = (data_size + info->bl_len - 1) / info->bl_len; data_offset += base_offset; + sectors = get_aligned_image_size(info, data_size, data_offset); load_ptr = (void *)load; debug("U-Boot size %x, data %p\n", data_size, load_ptr); - dst = load_ptr - (data_offset % info->bl_len); + dst = load_ptr; /* Read the image */ - src_sector = sector + data_offset / info->bl_len; - debug("image: data_offset=%x, dst=%p, src_sector=%x, sectors=%x\n", - data_offset, dst, src_sector, sectors); + src_sector = sector + get_aligned_image_offset(info, data_offset); + debug("Aligned image read: dst=%p, src_sector=%x, sectors=%x\n", + dst, src_sector, sectors); count = info->read(info, src_sector, sectors, dst); if (count != sectors) return -EIO; + debug("image: dst=%p, data_offset=%x, size=%x\n", dst, data_offset, + data_size); + memcpy(dst, dst + get_aligned_image_overhead(info, data_offset), + data_size); /* Figure out which device tree the board wants to use */ fdt_len = spl_fit_select_fdt(fit, images, &fdt_offset); @@ -179,14 +219,15 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit) /* * Read the device tree and place it after the image. There may be * some extra data before it since we can only read entire blocks. + * And also align the destination address to ARCH_DMA_MINALIGN. */ - dst = load_ptr + data_size; + dst = (void *)((load + data_size + align_len) & ~align_len); fdt_offset += base_offset; - sectors = (fdt_len + info->bl_len - 1) / info->bl_len; - count = info->read(info, sector + fdt_offset / info->bl_len, sectors, - dst); - debug("fit read %x sectors to %x, dst %p, data_offset %x\n", - sectors, spl_image.load_addr, dst, fdt_offset); + sectors = get_aligned_image_size(info, fdt_len, fdt_offset); + src_sector = sector + get_aligned_image_offset(info, fdt_offset); + count = info->read(info, src_sector, sectors, dst); + debug("Aligned fdt read: dst %p, src_sector = %x, sectors %x\n", + dst, src_sector, sectors); if (count != sectors) return -EIO; @@ -195,7 +236,10 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit) * After this we will have the U-Boot image and its device tree ready * for us to start. */ - memcpy(dst, dst + fdt_offset % info->bl_len, fdt_len); + debug("fdt: dst=%p, data_offset=%x, size=%x\n", dst, fdt_offset, + fdt_len); + memcpy(load_ptr + data_size, + dst + get_aligned_image_overhead(info, fdt_offset), fdt_len); return 0; } diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 5676acdde3f..d8058d63999 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -77,6 +77,7 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector) debug("Found FIT\n"); load.dev = mmc; load.priv = NULL; + load.filename = NULL; load.bl_len = mmc->read_bl_len; load.read = h_spl_load_read; ret = spl_load_simple_fit(&load, sector, header); diff --git a/include/spl.h b/include/spl.h index 335b76a1b15..0ae160547d1 100644 --- a/include/spl.h +++ b/include/spl.h @@ -35,16 +35,28 @@ struct spl_image_info { * @dev: Pointer to the device, e.g. struct mmc * * @priv: Private data for the device * @bl_len: Block length for reading in bytes + * @filename: Name of the fit image file. * @read: Function to call to read from the device */ struct spl_load_info { void *dev; void *priv; int bl_len; + const char *filename; ulong (*read)(struct spl_load_info *load, ulong sector, ulong count, void *buf); }; +/** + * spl_load_simple_fit() - Loads a fit image from a device. + * @info: Structure containing the information required to load data. + * @sector: Sector number where FIT image is located in the device + * @fdt: Pointer to the copied FIT header. + * + * Reads the FIT image @sector in the device. Loads u-boot image to + * specified load address and copies the dtb to end of u-boot image. + * Returns 0 on success. + */ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fdt); #define SPL_COPY_PAYLOAD_ONLY 1 -- cgit v1.3.1 From e35eb0391a2c77848a422b1b02ee29bc7f0a3e6d Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 13 May 2016 13:08:56 +1200 Subject: Remove unused BOOTFLAG definitions This follows on from commit d98b052 ("powerpc: Cleanup BOOTFLAG_* references") and commit fc3d297 ("Drop bogus BOOTFLAG_* definitions"). Remove the definitions that have crept in since. Signed-off-by: Chris Packham --- include/configs/P1010RDB.h | 8 -------- include/configs/ac14xx.h | 8 -------- 2 files changed, 16 deletions(-) (limited to 'include') diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f398b37f5b9..4d0855567a0 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -821,14 +821,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - /* * For booting Linux, the board info and command line data * have to be in the first 64 MB of memory, since this is diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h index bcf69422350..f0b5b3e1883 100644 --- a/include/configs/ac14xx.h +++ b/include/configs/ac14xx.h @@ -449,14 +449,6 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 -#define BOOTFLAG_WARM 0x02 - #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif -- cgit v1.3.1 From 7dd12830482bd145861578e37b39735abefdaa8f Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 16 May 2016 11:11:17 +0530 Subject: ARM: dts: AM43x-EPOS Initial Support Add initial DTS support for AM43-EPOS evm. Reviewed-by: Tom Rini Signed-off-by: Lokesh Vutla --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/am43x-epos-evm.dts | 806 ++++++++++++++++++++++ board/ti/am43xx/board.c | 2 + configs/am43xx_evm_defconfig | 2 +- include/dt-bindings/pinctrl/am43xx.h | 6 + include/dt-bindings/sound/tlv320aic31xx-micbias.h | 8 + 6 files changed, 825 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/am43x-epos-evm.dts create mode 100644 include/dt-bindings/sound/tlv320aic31xx-micbias.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 751bbd139cb..5884d8df95e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -92,7 +92,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zc1751-xm016-dc2.dtb \ zynqmp-zc1751-xm019-dc5.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb -dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb +dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ + am43x-epos-evm.dtb dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ diff --git a/arch/arm/dts/am43x-epos-evm.dts b/arch/arm/dts/am43x-epos-evm.dts new file mode 100644 index 00000000000..fa4d1e3f320 --- /dev/null +++ b/arch/arm/dts/am43x-epos-evm.dts @@ -0,0 +1,806 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* AM43x EPOS EVM */ + +/dts-v1/; + +#include "am4372.dtsi" +#include +#include +#include +#include + +/ { + model = "TI AM43x EPOS EVM"; + compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43"; + + aliases { + display0 = &lcd0; + }; + + chosen { + stdout-path = &uart0; + tick-timer = &timer2; + }; + + vmmcsd_fixed: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + lcd0: display { + compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; + label = "lcd"; + + panel-timing { + clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <210>; + hback-porch = <16>; + hsync-len = <30>; + vback-porch = <10>; + vfront-porch = <22>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + matrix_keypad: matrix_keypad@0 { + compatible = "gpio-matrix-keypad"; + debounce-delay-ms = <5>; + col-scan-delay-us = <2>; + + row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ + &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ + &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ + &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ + + col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ + &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ + &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ + &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ + + linux,keymap = <0x00000201 /* P1 */ + 0x01000204 /* P4 */ + 0x02000207 /* P7 */ + 0x0300020a /* NUMERIC_STAR */ + 0x00010202 /* P2 */ + 0x01010205 /* P5 */ + 0x02010208 /* P8 */ + 0x03010200 /* P0 */ + 0x00020203 /* P3 */ + 0x01020206 /* P6 */ + 0x02020209 /* P9 */ + 0x0302020b /* NUMERIC_POUND */ + 0x00030067 /* UP */ + 0x0103006a /* RIGHT */ + 0x0203006c /* DOWN */ + 0x03030069>; /* LEFT */ + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + sound0: sound@0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM43-EPOS-EVM"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker"; + simple-audio-card,routing = + "MIC1LP", "Microphone Jack", + "MIC1RP", "Microphone Jack", + "MIC1LP", "MICBIAS", + "MIC1RP", "MICBIAS", + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Speaker", "SPL", + "Speaker", "SPR"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-frequency = <12000000>; + }; + + sound0_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3111>; + system-clock-frequency = <12000000>; + }; + }; +}; + +&am43xx_pinmux { + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ + AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ + AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + nand_flash_x8: nand_flash_x8 { + pinctrl-single,pins = < + AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ + AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ + AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; + + ecap0_pins: backlight_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ + AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ + >; + }; + + spi0_pins: pinmux_spi0_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ + AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ + AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ + AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + >; + }; + + spi1_pins: pinmux_spi1_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ + AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ + AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ + AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + qspi1_default: qspi1_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) + AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) + AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) + AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) + AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) + AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + + pixcir_ts_pins: pixcir_ts_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ + >; + }; + + hdq_pins: pinmux_hdq_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ + >; + }; + + dss_pins: dss_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ + AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ + AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ + AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ + AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ + AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ + AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ + AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ + >; + }; + + display_mux_pins: display_mux_pins { + pinctrl-single,pins = < + /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ + AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + vpfe1_pins_default: vpfe1_pins_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ + AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ + AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ + AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ + AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ + AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ + AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ + AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ + AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ + AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ + AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ + AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ + AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ + >; + }; + + vpfe1_pins_sleep: vpfe1_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + >; + }; + + mcasp1_pins: mcasp1_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ + AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ + AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */ + AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */ + >; + }; + + mcasp1_sleep_pins: mcasp1_sleep_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <16>; + phy-mode = "rmii"; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rmii"; +}; + +&phy_sel { + rmii-clock-ext; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + + tps65218: tps65218@24 { + reg = <0x24>; + compatible = "ti,tps65218"; + interrupts = ; /* NMIn */ + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + compatible = "ti,tps65218-dcdc1"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + compatible = "ti,tps65218-dcdc2"; + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + compatible = "ti,tps65218-dcdc3"; + regulator-name = "vdcdc3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc4: regulator-dcdc4 { + compatible = "ti,tps65218-dcdc4"; + regulator-name = "vdcdc4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,tps65218-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + + at24@50 { + compatible = "at24,24c256"; + pagesize = <64>; + reg = <0x50>; + }; + + pixcir_ts@5c { + compatible = "pixcir,pixcir_tangoc"; + pinctrl-names = "default"; + pinctrl-0 = <&pixcir_ts_pins>; + reg = <0x5c>; + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_EDGE_FALLING>; + + attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; + + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + }; + + tlv320aic3111: tlv320aic3111@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3111"; + reg = <0x18>; + status = "okay"; + + ai31xx-micbias-vg = ; + + /* Regulators */ + HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ + SPRVDD-supply = <&vbat>; /* vbat */ + SPLVDD-supply = <&vbat>; /* vbat */ + AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ + IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ + DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&display_mux_pins>; + status = "okay"; + + p1 { + /* + * SelLCDorHDMI selects between display and audio paths: + * Low: HDMI display with audio via HDMI + * High: LCD display with analog audio via aic3111 codec + */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SelLCDorHDMI"; + }; +}; + +&gpio3 { + status = "okay"; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ + pinctrl-names = "default"; + pinctrl-0 = <&nand_flash_x8>; + ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; /* cs-on-ns */ + gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ + gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ + gpmc,we-on-ns = <0>; /* cs-on-ns */ + gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ + gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ + gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ + gpmc,access-ns = <30>; /* tCEA + 4*/ + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x00040000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00040000 0x00040000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00080000 0x00040000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x000C0000 0x00040000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00100000 0x00080000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x00180000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x00280000 0x00040000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x002C0000 0x00040000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00300000 0x00700000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x1f600000>; + }; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&tscadc { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; +}; + +&usb2_phy1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; +}; + +&qspi { + status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ + pinctrl-names = "default"; + pinctrl-0 = <&qspi1_default>; + + spi-max-frequency = <48000000>; + m25p80@0 { + compatible = "mx66l51235l"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpol; + spi-cpha; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first 512KiB + * for a valid file to boot(XIP). + */ + partition@0 { + label = "QSPI.U_BOOT"; + reg = <0x00000000 0x000080000>; + }; + partition@1 { + label = "QSPI.U_BOOT.backup"; + reg = <0x00080000 0x00080000>; + }; + partition@2 { + label = "QSPI.U-BOOT-SPL_OS"; + reg = <0x00100000 0x00010000>; + }; + partition@3 { + label = "QSPI.U_BOOT_ENV"; + reg = <0x00110000 0x00010000>; + }; + partition@4 { + label = "QSPI.U-BOOT-ENV.backup"; + reg = <0x00120000 0x00010000>; + }; + partition@5 { + label = "QSPI.KERNEL"; + reg = <0x00130000 0x0800000>; + }; + partition@6 { + label = "QSPI.FILESYSTEM"; + reg = <0x00930000 0x36D0000>; + }; + }; +}; + +&hdq { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdq_pins>; +}; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_pins>; + + port { + dpi_out: endpoint@0 { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&vpfe1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&vpfe1_pins_default>; + pinctrl-1 = <&vpfe1_pins_sleep>; + + port { + vpfe1_ep: endpoint { + /* remote-endpoint = <&sensor>; add once we have it */ + ti,am437x-vpfe-interface = <0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; +}; + +&mcasp1 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_sleep_pins>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&synctimer_32kclk { + assigned-clocks = <&mux_synctimer32k_ck>; + assigned-clock-parents = <&clkdiv32k_ick>; +}; diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 34f5d0610bd..c0d5335681b 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -854,6 +854,8 @@ int board_fit_config_name_match(const char *name) return 0; else if (board_is_sk() && !strcmp(name, "am437x-sk-evm")) return 0; + else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm")) + return 0; else return -1; } diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 1f88e6806d1..57f70ab3ae3 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm" +CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm" CONFIG_DM=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h index 720368782ed..292c2ebf58d 100644 --- a/include/dt-bindings/pinctrl/am43xx.h +++ b/include/dt-bindings/pinctrl/am43xx.h @@ -30,4 +30,10 @@ #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (INPUT_EN) +/* + * Macro to allow using the absolute physical address instead of the + * padconf registers instead of the offset from padconf base. + */ +#define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val) + #endif diff --git a/include/dt-bindings/sound/tlv320aic31xx-micbias.h b/include/dt-bindings/sound/tlv320aic31xx-micbias.h new file mode 100644 index 00000000000..f5cb772ab9c --- /dev/null +++ b/include/dt-bindings/sound/tlv320aic31xx-micbias.h @@ -0,0 +1,8 @@ +#ifndef __DT_TLV320AIC31XX_MICBIAS_H +#define __DT_TLV320AIC31XX_MICBIAS_H + +#define MICBIAS_2_0V 1 +#define MICBIAS_2_5V 2 +#define MICBIAS_AVDDV 3 + +#endif /* __DT_TLV320AIC31XX_MICBIAS_H */ -- cgit v1.3.1 From 3819ea70635d15595df5bc2d0b1cc81245b1e1cf Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 16 May 2016 11:24:28 +0530 Subject: ARM: dts: AM335x-evmsk: Add initial support Add initial DTS support for AM335x-evm sk. Reviewed-by: Tom Rini Signed-off-by: Lokesh Vutla --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/am335x-evmsk.dts | 720 +++++++++++++++++++++++++++++++++++++ board/ti/am335x/board.c | 2 + configs/am335x_evm_defconfig | 2 +- include/dt-bindings/pinctrl/omap.h | 37 ++ 5 files changed, 762 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/am335x-evmsk.dts (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5d2910d5a7e..587d22077cd 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -91,7 +91,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ zynqmp-zc1751-xm019-dc5.dtb -dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb +dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb \ + am335x-evmsk.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am43x-epos-evm.dtb \ am437x-idk-evm.dtb diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts new file mode 100644 index 00000000000..b3e9b61baeb --- /dev/null +++ b/arch/arm/dts/am335x-evmsk.dts @@ -0,0 +1,720 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * AM335x Starter Kit + * http://www.ti.com/tool/tmdssk3358 + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include +#include + +/ { + model = "TI AM335x EVM-SK"; + compatible = "ti,am335x-evmsk", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer2; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + lis3_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "lis3_reg"; + regulator-boot-on; + }; + + wl12xx_vmmc: fixedregulator@2 { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 29 0>; + startup-delay-us = <70000>; + enable-active-high; + }; + + vtt_fixed: fixedregulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + led@1 { + label = "evmsk:green:usr0"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@2 { + label = "evmsk:green:usr1"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@3 { + label = "evmsk:green:mmc0"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@4 { + label = "evmsk:green:heartbeat"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + gpio_buttons: gpio_buttons@0 { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + switch@1 { + label = "button0"; + linux,code = <0x100>; + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + }; + + switch@2 { + label = "button1"; + linux,code = <0x101>; + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + }; + + switch@3 { + label = "button2"; + linux,code = <0x102>; + gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + switch@4 { + label = "button3"; + linux,code = <0x103>; + gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 58 61 66 75 90 125 170 255>; + default-brightness-level = <8>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM335x-EVMSK"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24000000>; + }; + }; + + panel { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_pins_default>; + pinctrl-1 = <&lcd_pins_sleep>; + status = "okay"; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + display-timings { + 480x272 { + hactive = <480>; + vactive = <272>; + hback-porch = <43>; + hfront-porch = <8>; + hsync-len = <4>; + vback-porch = <12>; + vfront-porch = <4>; + vsync-len = <10>; + clock-frequency = <9000000>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; + + lcd_pins_default: lcd_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ + AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ + AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ + AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ + AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ + AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ + AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ + AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + + lcd_pins_sleep: lcd_pins_sleep { + pinctrl-single,pins = < + AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */ + AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */ + AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */ + AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */ + AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */ + AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */ + AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */ + AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */ + AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + + + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ + AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ + AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ + AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ + >; + }; + + gpio_keys_s0: gpio_keys_s0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ + AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ + AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ + AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + ecap2_pins: backlight_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x99c, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + + /* Slave 2 */ + AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value*/ + AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + mcasp1_pins: mcasp1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + >; + }; + + mcasp1_pins_sleep: mcasp1_pins_sleep { + pinctrl-single,pins = < + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + >; + }; + + wl12xx_gpio: pinmux_wl12xx_gpio { + pinctrl-single,pins = < + AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; + + lis331dlh: lis331dlh@18 { + compatible = "st,lis331dlh", "st,lis3lv02d"; + reg = <0x18>; + Vdd-supply = <&lis3_reg>; + Vdd_IO-supply = <&lis3_reg>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <10>; + st,click-thresh-y = <10>; + st,click-thresh-z = <10>; + st,irq1-click; + st,irq2-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <120>; + st,min-limit-y = <120>; + st,min-limit-z = <140>; + st,max-limit-x = <550>; + st,max-limit-y = <550>; + st,max-limit-z = <750>; + }; + + tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + AVDD-supply = <&vaux2_reg>; + IOVDD-supply = <&vaux2_reg>; + DRVDD-supply = <&vaux2_reg>; + DVDD-supply = <&vbat>; + }; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +&epwmss2 { + status = "okay"; + + ecap2: ecap@48304100 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>; + }; +}; + +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac = <1>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rgmii-txid"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rgmii-txid"; + dual_emac_res_vlan = <2>; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&gpio0 { + ti,no-reset-on-init; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&wl12xx_vmmc>; + ti,non-removable; + bus-width = <4>; + cap-power-off-card; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */ + ref-clock-frequency = <38400000>; + }; +}; + +&mcasp1 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_pins_sleep>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x00 0x11 0x22 0x33>; + }; +}; + +&lcdc { + status = "okay"; +}; diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index a3d1e2b8a45..89b12a57daa 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -642,6 +642,8 @@ int board_fit_config_name_match(const char *name) return 0; else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack")) return 0; + else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk")) + return 0; else return -1; } diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 3e68744a0cb..a2794c28708 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -48,4 +48,4 @@ CONFIG_RSA=y CONFIG_FIT=y CONFIG_SPL_OF_LIBFDT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack" +CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk" diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h index 1dd7636a696..672a1369aff 100644 --- a/include/dt-bindings/pinctrl/omap.h +++ b/include/dt-bindings/pinctrl/omap.h @@ -53,5 +53,42 @@ #define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) #define PIN_OFF_WAKEUPENABLE WAKEUP_EN +/* + * Macros to allow using the absolute physical address instead of the + * padconf registers instead of the offset from padconf base. + */ +#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) + +#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) +#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) +#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) +#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) +#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) +#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) +#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) +#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) +#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) + +/* + * Macros to allow using the offset from the padconf physical address + * instead of the offset from padconf base. + */ +#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset)) + +#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) +#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) + +/* + * Define some commonly used pins configured by the boards. + * Note that some boards use alternative pins, so check + * the schematics before using these. + */ +#define OMAP3_UART1_RX 0x152 +#define OMAP3_UART2_RX 0x14a +#define OMAP3_UART3_RX 0x16e +#define OMAP4_UART2_RX 0xdc +#define OMAP4_UART3_RX 0x104 +#define OMAP4_UART4_RX 0x11c + #endif -- cgit v1.3.1 From 61bb825cd9edddc44c5a0c8897d400f213ce9e10 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 16 May 2016 11:32:49 +0530 Subject: configs: am335x_evm: Switch to env on FAT SD by default Re-org env sections so that we can fall back to env is in FAT on SD card, for broader board compatibility Signed-off-by: Tom Rini Signed-off-by: Lokesh Vutla --- include/configs/am335x_evm.h | 40 +++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 16935a105a1..dfd00de6e26 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -249,11 +249,6 @@ "8m(NAND.kernel)," \ "-(NAND.file-system)" #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 -#undef CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x001c0000 -#define CONFIG_ENV_OFFSET_REDUND 0x001e0000 -#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE /* NAND: SPL related configs */ #ifdef CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_AM33XX_BCH @@ -415,7 +410,6 @@ "128k(u-boot-env2),3464k(kernel)," \ "-(rootfs)" #elif defined(CONFIG_EMMC_BOOT) -#undef CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SYS_MMC_ENV_DEV 1 @@ -423,6 +417,27 @@ #define CONFIG_ENV_OFFSET 0x0 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#elif defined(CONFIG_NOR_BOOT) +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */ +#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */ +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \ + "512k(u-boot)," \ + "128k(u-boot-env1)," \ + "128k(u-boot-env2)," \ + "4m(kernel),-(rootfs)" +#elif defined(CONFIG_ENV_IS_IN_NAND) +#define CONFIG_ENV_OFFSET 0x001c0000 +#define CONFIG_ENV_OFFSET_REDUND 0x001e0000 +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#elif !defined(CONFIG_ENV_IS_NOWHERE) +/* Not NAND, SPI, NOR or eMMC env, so put ENV in a file on FAT */ +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" #endif /* SPI flash. */ @@ -458,19 +473,6 @@ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FLASH_SIZE 0x01000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -/* Reduce SPL size by removing unlikey targets */ -#ifdef CONFIG_NOR_BOOT -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */ -#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */ -#define MTDIDS_DEFAULT "nor0=physmap-flash.0" -#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \ - "512k(u-boot)," \ - "128k(u-boot-env1)," \ - "128k(u-boot-env2)," \ - "4m(kernel),-(rootfs)" -#endif #endif /* NOR support */ #endif /* ! __CONFIG_AM335X_EVM_H */ -- cgit v1.3.1 From 97f3a178b2a3d5a7767cb6cb15ba9c40ba804ebb Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 16 May 2016 11:47:26 +0530 Subject: board: AM335x-ICEv2: Add cpsw support In order to enable cpsw on AM335x ICEv2 board, the following needs to be done: 1)There are few on board jumper settings which gives a choice between cpsw and PRUSS, that needs to be properly selected[1]. Even after selecting this, there are few GPIOs which control these muxes that needs to be held high. 2) The clock to PHY is provided by a PLL-based clock synthesizer[2] connected via I2C. This needs to properly programmed and locked for PHY operation. And PHY needs to be reset before before being used, which is also held by a GPIO. 3) RMII mode needs to be selected. [1] http://www.ti.com/lit/zip/tidr336 [2] http://www.ti.com/lit/ds/symlink/cdce913.pdf Reviewed-by: Tom Rini Acked-by: Mugunthan V N Signed-off-by: Lokesh Vutla --- board/ti/am335x/board.c | 87 ++++++++++++++++++++++++++++++++++++++++---- include/configs/am335x_evm.h | 5 +++ 2 files changed, 85 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 51c43587c3b..8f4769206d9 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -37,8 +38,13 @@ DECLARE_GLOBAL_DATA_PTR; /* GPIO that controls power to DDR on EVM-SK */ -#define GPIO_DDR_VTT_EN 7 -#define ICE_GPIO_DDR_VTT_EN 18 +#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) +#define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7) +#define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18) +#define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4) +#define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10) +#define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7) +#define GPIO_PHY_RESET GPIO_TO_PIN(2, 5) #if defined(CONFIG_SPL_BUILD) || \ (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH)) @@ -474,6 +480,49 @@ void sdram_init(void) } #endif +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void request_and_set_gpio(int gpio, char *name) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret < 0) { + printf("%s: Unable to request %s\n", __func__, name); + return; + } + + ret = gpio_direction_output(gpio, 0); + if (ret < 0) { + printf("%s: Unable to set %s as output\n", __func__, name); + goto err_free_gpio; + } + + gpio_set_value(gpio, 1); + + return; + +err_free_gpio: + gpio_free(gpio); +} + +#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N); + +/** + * RMII mode on ICEv2 board needs 50MHz clock. Given the clock + * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle + * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to + * give 50MHz output for Eth0 and 1. + */ +static struct clk_synth cdce913_data = { + .id = 0x81, + .capacitor = 0x90, + .mux = 0x6d, + .pdiv2 = 0x2, + .pdiv3 = 0x2, +}; +#endif + /* * Basic board specific setup. Pinmux has been handled already. */ @@ -487,6 +536,23 @@ int board_init(void) #if defined(CONFIG_NOR) || defined(CONFIG_NAND) gpmc_init(); #endif +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) + int rv; + + if (board_is_icev2()) { + REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL); + REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL); + REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL); + REQUEST_AND_SET_GPIO(GPIO_PHY_RESET); + + rv = setup_clock_synthesizer(&cdce913_data); + if (rv) { + printf("Clock synthesizer setup failed %d\n", rv); + return rv; + } + } +#endif + return 0; } @@ -554,6 +620,12 @@ static struct cpsw_platform_data cpsw_data = { }; #endif +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\ + defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) + /* * This function will: * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr @@ -565,11 +637,6 @@ static struct cpsw_platform_data cpsw_data = { * Build in only these cases to avoid warnings about unused variables * when we build an SPL that has neither option but full U-Boot will. */ -#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ - && defined(CONFIG_SPL_BUILD)) || \ - ((defined(CONFIG_DRIVER_TI_CPSW) || \ - defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \ - !defined(CONFIG_SPL_BUILD)) int board_eth_init(bd_t *bis) { int rv, n = 0; @@ -620,6 +687,12 @@ int board_eth_init(bd_t *bis) writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; + } else if (board_is_icev2()) { + writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; + cpsw_slaves[0].phy_addr = 1; + cpsw_slaves[1].phy_addr = 3; } else { writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index dfd00de6e26..7c7f197cab7 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -475,4 +475,9 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #endif /* NOR support */ +#ifdef CONFIG_DRIVER_TI_CPSW +#define CONFIG_CLOCK_SYNTHESIZER +#define CLK_SYNTHESIZER_I2C_ADDR 0x65 +#endif + #endif /* ! __CONFIG_AM335X_EVM_H */ -- cgit v1.3.1 From 426af3848fdd383e0cb141142b3f0d9a7edb334e Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 16 May 2016 11:47:27 +0530 Subject: config: env: Set AM335x-ICEv2 board specific env Populate the right dtb file and console for AM335x-ICEv2 board. Reviewed-by: Tom Rini Signed-off-by: Lokesh Vutla --- include/configs/am335x_evm.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 7c7f197cab7..ba4c215463f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -91,6 +91,7 @@ #define CONFIG_BOOTCOMMAND \ "run findfdt; " \ + "run init_console; " \ "run envboot; " \ "run distro_bootcmd" @@ -169,8 +170,16 @@ "setenv fdtfile am335x-evm.dtb; fi; " \ "if test $board_name = A335X_SK; then " \ "setenv fdtfile am335x-evmsk.dtb; fi; " \ + "if test $board_name = A335_ICE; then " \ + "setenv fdtfile am335x-icev2.dtb; fi; " \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ + "init_console=" \ + "if test $board_name = A335_ICE; then "\ + "setenv console ttyO3,115200n8;" \ + "else " \ + "setenv console ttyO0,115200n8;" \ + "fi;\0" \ NANDARGS \ NETARGS \ DFUARGS \ -- cgit v1.3.1 From 3d16389c909657a5fd1017e771ce5acf8aed6189 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 16 May 2016 11:47:29 +0530 Subject: board: am335x: Allow to choose serial device dynamically Different AM335x based platforms have different serial consoles. As serial console is Kconfig option a separate defconfig has to be created for each platform. So pass the serial device dynamically. Signed-off-by: Lokesh Vutla --- board/ti/am335x/board.c | 11 +++++++++++ include/serial.h | 4 ++++ 2 files changed, 15 insertions(+) (limited to 'include') diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index ff52314bf59..56f4984f479 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -59,6 +60,16 @@ static inline int __maybe_unused read_eeprom(void) return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR); } +#ifndef CONFIG_DM_SERIAL +struct serial_device *default_serial_console(void) +{ + if (board_is_icev2()) + return &eserial4_device; + else + return &eserial1_device; +} +#endif + #ifndef CONFIG_SKIP_LOWLEVEL_INIT static const struct ddr_data ddr2_data = { .datardsratio0 = MT47H128M16RT25E_RD_DQS, diff --git a/include/serial.h b/include/serial.h index e490f9a0cf5..47332c53406 100644 --- a/include/serial.h +++ b/include/serial.h @@ -40,6 +40,10 @@ extern struct serial_device serial1_device; extern struct serial_device eserial1_device; extern struct serial_device eserial2_device; +extern struct serial_device eserial3_device; +extern struct serial_device eserial4_device; +extern struct serial_device eserial5_device; +extern struct serial_device eserial6_device; extern void serial_register(struct serial_device *); extern void serial_initialize(void); -- cgit v1.3.1 From 56adbb38727320375b2f695bd04600d766d8a1b3 Mon Sep 17 00:00:00 2001 From: "Robert P. J. Day" Date: Sat, 21 May 2016 05:06:31 -0400 Subject: image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro. In order for CONFIG_IS_ENABLED(FOO) to work we need to move the changes that CONFIG_FIT_DISABLE_SHA256 makes to be prior to the evaluation by CONFIG_IS_ENABLED(foo) Signed-off-by: Robert P. J. Day [trini: Move CONFIG_FIT_DISABLE_SHA256 parts to fix build breakage] Signed-off-by: Tom Rini --- include/image.h | 69 ++++++++++----------------------------------------------- 1 file changed, 12 insertions(+), 57 deletions(-) (limited to 'include') diff --git a/include/image.h b/include/image.h index a8f6bd16f69..80a445408c2 100644 --- a/include/image.h +++ b/include/image.h @@ -52,19 +52,15 @@ struct lmb; #include #include #include +# ifdef CONFIG_FIT_DISABLE_SHA256 +# undef CONFIG_SHA256 +# undef IMAGE_ENABLE_SHA256 +# endif # ifdef CONFIG_SPL_BUILD -# ifdef CONFIG_SPL_CRC32_SUPPORT -# define IMAGE_ENABLE_CRC32 1 -# endif -# ifdef CONFIG_SPL_MD5_SUPPORT -# define IMAGE_ENABLE_MD5 1 -# endif -# ifdef CONFIG_SPL_SHA1_SUPPORT -# define IMAGE_ENABLE_SHA1 1 -# endif -# ifdef CONFIG_SPL_SHA256_SUPPORT -# define IMAGE_ENABLE_SHA256 1 -# endif +# define IMAGE_ENABLE_CRC32 CONFIG_IS_ENABLED(SPL_CRC32_SUPPORT) +# define IMAGE_ENABLE_MD5 CONFIG_IS_ENABLED(SPL_MD5_SUPPORT) +# define IMAGE_ENABLE_SHA1 CONFIG_IS_ENABLED(SPL_SHA1_SUPPORT) +# define IMAGE_ENABLE_SHA256 CONFIG_IS_ENABLED(SPL_SHA256_SUPPORT) # else # define CONFIG_CRC32 /* FIT images need CRC32 support */ # define CONFIG_MD5 /* and MD5 */ @@ -75,53 +71,12 @@ struct lmb; # define IMAGE_ENABLE_SHA1 1 # define IMAGE_ENABLE_SHA256 1 # endif - -#ifdef CONFIG_FIT_DISABLE_SHA256 -#undef CONFIG_SHA256 -#undef IMAGE_ENABLE_SHA256 -#endif - -#ifndef IMAGE_ENABLE_CRC32 -#define IMAGE_ENABLE_CRC32 0 -#endif - -#ifndef IMAGE_ENABLE_MD5 -#define IMAGE_ENABLE_MD5 0 -#endif - -#ifndef IMAGE_ENABLE_SHA1 -#define IMAGE_ENABLE_SHA1 0 -#endif - -#ifndef IMAGE_ENABLE_SHA256 -#define IMAGE_ENABLE_SHA256 0 -#endif - #endif /* IMAGE_ENABLE_FIT */ -#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH -# define IMAGE_ENABLE_RAMDISK_HIGH 1 -#else -# define IMAGE_ENABLE_RAMDISK_HIGH 0 -#endif - -#ifdef CONFIG_SYS_BOOT_GET_CMDLINE -# define IMAGE_BOOT_GET_CMDLINE 1 -#else -# define IMAGE_BOOT_GET_CMDLINE 0 -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -# define IMAGE_OF_BOARD_SETUP 1 -#else -# define IMAGE_OF_BOARD_SETUP 0 -#endif - -#ifdef CONFIG_OF_SYSTEM_SETUP -# define IMAGE_OF_SYSTEM_SETUP 1 -#else -# define IMAGE_OF_SYSTEM_SETUP 0 -#endif +#define IMAGE_ENABLE_RAMDISK_HIGH CONFIG_IS_ENABLED(SYS_BOOT_RAMDISK_HIGH) +#define IMAGE_BOOT_GET_CMDLINE CONFIG_IS_ENABLED(SYS_BOOT_GET_CMDLINE) +#define IMAGE_OF_BOARD_SETUP CONFIG_IS_ENABLED(OF_BOARD_SETUP) +#define IMAGE_OF_SYSTEM_SETUP CONFIG_IS_ENABLED(OF_SYSTEM_SETUP) /* * Operating System Codes -- cgit v1.3.1 From f7c32e8ece7fefd950382a7522aff9939a218b91 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 27 Apr 2016 09:10:42 +0200 Subject: arm: spear: x600: Add support for Micrel KSZ9031 PHY As the old ethernet PHY is not available any more, the x600 board has been redesigned with the Micrel KSZ9031 PHY. This patch adds support to autodetect the PHY and configure the Micrel PHY correctly. Signed-off-by: Stefan Roese --- board/spear/x600/x600.c | 80 ++++++++++++++++++++++++++++++++++++------------- include/configs/x600.h | 2 ++ 2 files changed, 61 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c index b8edfcd071f..f8e9fddb0fb 100644 --- a/board/spear/x600/x600.c +++ b/board/spear/x600/x600.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -69,27 +70,64 @@ void board_nand_init(void) int board_phy_config(struct phy_device *phydev) { - /* Extended PHY control 1, select GMII */ - phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); - - /* Software reset necessary after GMII mode selction */ - phy_reset(phydev); - - /* Enable extended page register access */ - phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); - - /* 17e: Enhanced LED behavior, needs to be written twice */ - phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); - phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); - - /* 16e: Enhanced LED method select */ - phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); - - /* Disable extended page register access */ - phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); - - /* Enable clock output pin */ - phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); + unsigned short id1, id2; + + /* check whether KSZ9031 or AR8035 has to be configured */ + id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); + id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); + + if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) { + /* PHY configuration for Micrel KSZ9031 */ + printf("PHY KSZ9031 detected - "); + + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); + + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* tx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x03FF); + } else { + /* PHY configuration for Vitesse VSC8641 */ + printf("PHY VSC8641 detected - "); + + /* Extended PHY control 1, select GMII */ + phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); + + /* Software reset necessary after GMII mode selction */ + phy_reset(phydev); + + /* Enable extended page register access */ + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); + + /* 17e: Enhanced LED behavior, needs to be written twice */ + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); + + /* 16e: Enhanced LED method select */ + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); + + /* Disable extended page register access */ + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); + + /* Enable clock output pin */ + phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); + } if (phydev->drv->config) phydev->drv->config(phydev); diff --git a/include/configs/x600.h b/include/configs/x600.h index 5fdd2bee049..07c8abe2a79 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -80,6 +80,8 @@ #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 #define CONFIG_SPEAR_GPIO -- cgit v1.3.1 From 0f832b9cdcbe8a024b53c585622d70129652d20b Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Thu, 26 May 2016 14:49:36 +0100 Subject: malta: Allow MIPS64 builds Both real Malta boards & emulators that mimic Malta (eg. QEMU) can support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards, which enables the user to make use of the whole 64 bit address space. Signed-off-by: Paul Burton --- arch/mips/Kconfig | 3 +++ board/imgtec/malta/Kconfig | 3 ++- board/imgtec/malta/lowlevel_init.S | 13 +++++++------ include/configs/malta.h | 18 +++++++++++++----- 4 files changed, 25 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 53363e38fe4..abaeaf0330b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -33,6 +33,9 @@ config TARGET_MALTA select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SUPPORTS_CPU_MIPS32_R6 + select SUPPORTS_CPU_MIPS64_R1 + select SUPPORTS_CPU_MIPS64_R2 + select SUPPORTS_CPU_MIPS64_R6 select SWAP_IO_SPACE select MIPS_L1_CACHE_SHIFT_6 diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig index 2bb8e8be16e..98eb4d16c71 100644 --- a/board/imgtec/malta/Kconfig +++ b/board/imgtec/malta/Kconfig @@ -10,6 +10,7 @@ config SYS_CONFIG_NAME default "malta" config SYS_TEXT_BASE - default 0xbe000000 + default 0xbe000000 if 32BIT + default 0xffffffffbe000000 if 64BIT endif diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S index 534db1d8324..3d48cdc1f47 100644 --- a/board/imgtec/malta/lowlevel_init.S +++ b/board/imgtec/malta/lowlevel_init.S @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -34,7 +35,7 @@ lowlevel_init: mtc0 t0, CP0_CONFIG, 2 /* detect the core card */ - li t0, KSEG1ADDR(MALTA_REVISION) + PTR_LI t0, CKSEG1ADDR(MALTA_REVISION) lw t0, 0(t0) srl t0, t0, MALTA_REVISION_CORID_SHF andi t0, t0, (MALTA_REVISION_CORID_MSK >> \ @@ -68,12 +69,12 @@ lowlevel_init: */ _gt64120: /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - li t1, KSEG1ADDR(GT_DEF_BASE) + PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE) li t0, CPU_TO_GT32(0xdf000000) sw t0, GT_ISD_OFS(t1) /* setup MEM-to-PCI0 mapping */ - li t1, KSEG1ADDR(MALTA_GT_BASE) + PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE) /* setup PCI0 io window to 0x18000000-0x181fffff */ li t0, CPU_TO_GT32(0xc0000000) @@ -100,7 +101,7 @@ _gt64120: */ _msc01: /* setup peripheral bus controller clock divide */ - li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE) + PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE) li t1, 0x1 << MSC01_PBC_CLKCFG_SHF sw t1, MSC01_PBC_CLKCFG_OFS(t0) @@ -122,7 +123,7 @@ _msc01: sw t1, MSC01_PBC_CS0CFG_OFS(t0) /* setup basic address decode */ - li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE) + PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE) li t1, 0x0 li t2, -CONFIG_SYS_MEM_SIZE sw t1, MSC01_BIU_MCBAS1L_OFS(t0) @@ -157,7 +158,7 @@ _msc01: sw t2, MSC01_BIU_IP3MSK2L_OFS(t0) /* setup PCI memory */ - li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE) + PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE) li t1, MALTA_MSC01_PCIMEM_BASE li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK li t3, MALTA_MSC01_PCIMEM_MAP diff --git a/include/configs/malta.h b/include/configs/malta.h index a36967848c5..fc4baba7d7e 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -39,14 +39,18 @@ */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ +#ifdef CONFIG_64BIT +# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +#else +# define CONFIG_SYS_SDRAM_BASE 0x80000000 +#endif #define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024) #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80800000 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000) +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x00800000) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) @@ -69,7 +73,11 @@ /* * Flash configuration */ -#define CONFIG_SYS_FLASH_BASE 0xbe000000 +#ifdef CONFIG_64BIT +# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000 +#else +# define CONFIG_SYS_FLASH_BASE 0xbe000000 +#endif #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 128 #define CONFIG_SYS_FLASH_CFI -- cgit v1.3.1 From ace3be4f15875d74344336b9754c14274f940969 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 27 May 2016 14:28:04 +0100 Subject: MIPS: Move cache sizes to Kconfig Move details of the L1 cache line sizes & total sizes into Kconfig, defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is introduced to allow platforms to select auto-detection of cache sizes, and it defaults to being enabled if none of the cache sizes are set by the configuration (ie. sizes are all the default 0), and code is adjusted to #ifdef on that rather than on the definition of the sizes (which will always be defined even if 0). Signed-off-by: Paul Burton --- arch/mips/Kconfig | 28 ++++++++++++++++++++++++++++ arch/mips/lib/cache.c | 2 +- arch/mips/lib/cache_init.S | 6 +++--- board/dbau1x00/Kconfig | 9 +++++++++ board/micronas/vct/Kconfig | 9 +++++++++ board/pb1x00/Kconfig | 9 +++++++++ board/qca/ap121/Kconfig | 9 +++++++++ board/qca/ap143/Kconfig | 9 +++++++++ board/qemu-mips/Kconfig | 9 +++++++++ board/tplink/wdr4300/Kconfig | 9 +++++++++ include/configs/ap121.h | 5 ----- include/configs/ap143.h | 5 ----- include/configs/dbau1x00.h | 7 ------- include/configs/pb1x00.h | 6 ------ include/configs/qemu-mips.h | 7 ------- include/configs/qemu-mips64.h | 7 ------- include/configs/tplink_wdr4300.h | 5 ----- include/configs/vct.h | 7 ------- 18 files changed, 95 insertions(+), 53 deletions(-) (limited to 'include') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a9294527df7..a79224e525e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -246,6 +246,34 @@ config SWAP_IO_SPACE config SYS_MIPS_CACHE_INIT_RAM_LOAD bool +config SYS_DCACHE_SIZE + int + default 0 + help + The total size of the L1 Dcache, if known at compile time. + +config SYS_ICACHE_SIZE + int + default 0 + help + The total size of the L1 ICache, if known at compile time. + +config SYS_CACHELINE_SIZE + int + default 0 + help + The size of L1 cache lines, if known at compile time. + +config SYS_CACHE_SIZE_AUTO + def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ + SYS_CACHELINE_SIZE = 0 + help + Select this (or let it be auto-selected by not defining any cache + sizes) in order to allow U-Boot to automatically detect the sizes + of caches at runtime. This has a small cost in code size & runtime + so if you know the cache configuration for your system at compile + time it would be beneficial to configure it. + config MIPS_L1_CACHE_SHIFT_4 bool diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 7482005b679..fbaafee8cde 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -9,7 +9,7 @@ #include #include -#ifdef CONFIG_SYS_CACHELINE_SIZE +#ifndef CONFIG_SYS_CACHE_SIZE_AUTO static inline unsigned long icache_line_size(void) { diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 08b7c3af525..4bb9a17e749 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -99,14 +99,14 @@ * */ LEAF(mips_cache_reset) -#ifdef CONFIG_SYS_ICACHE_SIZE +#ifndef CONFIG_SYS_CACHE_SIZE_AUTO li t2, CONFIG_SYS_ICACHE_SIZE li t8, CONFIG_SYS_CACHELINE_SIZE #else l1_info t2, t8, MIPS_CONF1_IA_SHF #endif -#ifdef CONFIG_SYS_DCACHE_SIZE +#ifndef CONFIG_SYS_CACHE_SIZE_AUTO li t3, CONFIG_SYS_DCACHE_SIZE li t9, CONFIG_SYS_CACHELINE_SIZE #else @@ -116,7 +116,7 @@ LEAF(mips_cache_reset) #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* Determine the largest L1 cache size */ -#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE) +#ifndef CONFIG_SYS_CACHE_SIZE_AUTO #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE li v0, CONFIG_SYS_ICACHE_SIZE #else diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig index 342ec59cb73..1715a289755 100644 --- a/board/dbau1x00/Kconfig +++ b/board/dbau1x00/Kconfig @@ -12,6 +12,15 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0xbfc00000 +config SYS_DCACHE_SIZE + default 16384 + +config SYS_ICACHE_SIZE + default 16384 + +config SYS_CACHELINE_SIZE + default 32 + menu "dbau1x00 board options" choice diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig index 535a77b2a32..5bb6f03f30f 100644 --- a/board/micronas/vct/Kconfig +++ b/board/micronas/vct/Kconfig @@ -12,6 +12,15 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0x87000000 +config SYS_DCACHE_SIZE + default 16384 + +config SYS_ICACHE_SIZE + default 16384 + +config SYS_CACHELINE_SIZE + default 32 + menu "vct board options" choice diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig index 236a4108bfc..27b2ef000b0 100644 --- a/board/pb1x00/Kconfig +++ b/board/pb1x00/Kconfig @@ -12,4 +12,13 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0x83800000 +config SYS_DCACHE_SIZE + default 16384 + +config SYS_ICACHE_SIZE + default 16384 + +config SYS_CACHELINE_SIZE + default 32 + endif diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig index c3ecc8f62ff..f28ea1cd44f 100644 --- a/board/qca/ap121/Kconfig +++ b/board/qca/ap121/Kconfig @@ -12,4 +12,13 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0x9f000000 +config SYS_DCACHE_SIZE + default 32768 + +config SYS_ICACHE_SIZE + default 65536 + +config SYS_CACHELINE_SIZE + default 32 + endif diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig index 5ea5d6fbb02..ff02236d5d8 100644 --- a/board/qca/ap143/Kconfig +++ b/board/qca/ap143/Kconfig @@ -12,4 +12,13 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0x9f000000 +config SYS_DCACHE_SIZE + default 32768 + +config SYS_ICACHE_SIZE + default 65536 + +config SYS_CACHELINE_SIZE + default 32 + endif diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig index 3de1f44a3da..66957e7a57a 100644 --- a/board/qemu-mips/Kconfig +++ b/board/qemu-mips/Kconfig @@ -11,4 +11,13 @@ config SYS_TEXT_BASE default 0xbfc00000 if 32BIT default 0xffffffffbfc00000 if 64BIT +config SYS_DCACHE_SIZE + default 16384 + +config SYS_ICACHE_SIZE + default 16384 + +config SYS_CACHELINE_SIZE + default 32 + endif diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig index 65785bdb9c7..ded7f9b1798 100644 --- a/board/tplink/wdr4300/Kconfig +++ b/board/tplink/wdr4300/Kconfig @@ -15,4 +15,13 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0xa1000000 +config SYS_DCACHE_SIZE + default 32768 + +config SYS_ICACHE_SIZE + default 65536 + +config SYS_CACHELINE_SIZE + default 32 + endif diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 6f69f31503c..f069d501302 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -15,11 +15,6 @@ #define CONFIG_SYS_MHZ 200 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 0x8000 -#define CONFIG_SYS_ICACHE_SIZE 0x10000 -#define CONFIG_SYS_CACHELINE_SIZE 32 - #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MALLOC_LEN 0x40000 diff --git a/include/configs/ap143.h b/include/configs/ap143.h index f907c02af92..e45f743936d 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -15,11 +15,6 @@ #define CONFIG_SYS_MHZ 325 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 0x8000 -#define CONFIG_SYS_ICACHE_SIZE 0x10000 -#define CONFIG_SYS_CACHELINE_SIZE 32 - #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MALLOC_LEN 0x40000 diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index 68d9e36b19c..68ff02509b5 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -202,11 +202,4 @@ #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 #endif /* CONFIG_DBAU1550 */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 - #endif /* __CONFIG_H */ diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 869768add05..b907419a598 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -144,12 +144,6 @@ #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 #endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 /* * BOOTP options diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 246ee0173a7..f58fc4c3779 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -132,11 +132,4 @@ #define CONFIG_LZMA -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 - #endif /* __CONFIG_H */ diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index 60a3a71fbdc..2190d162007 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -132,11 +132,4 @@ #define CONFIG_LZMA -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 - #endif /* __CONFIG_H */ diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 09a69fec09d..6273711b1d0 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -15,11 +15,6 @@ #define CONFIG_SYS_MHZ 280 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 0x8000 -#define CONFIG_SYS_ICACHE_SIZE 0x10000 -#define CONFIG_SYS_CACHELINE_SIZE 32 - #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MALLOC_LEN 0x40000 diff --git a/include/configs/vct.h b/include/configs/vct.h index 68eb0893948..cc5e3546b08 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -203,13 +203,6 @@ #define CONFIG_ENV_SIZE (128 << 10) /* erase size */ #endif /* CONFIG_VCT_ONENAND */ -/* - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 - /* * I2C/EEPROM */ -- cgit v1.3.1 From 372286217f050bfd57695001d59f618c52822f40 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 27 May 2016 14:28:05 +0100 Subject: MIPS: Split I & D cache line size config Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck --- arch/mips/Kconfig | 12 +++++++++--- arch/mips/include/asm/cache.h | 7 +++++++ arch/mips/lib/cache.c | 22 +++++++--------------- arch/mips/lib/cache_init.S | 4 ++-- board/dbau1x00/Kconfig | 5 ++++- board/micronas/vct/Kconfig | 5 ++++- board/pb1x00/Kconfig | 5 ++++- board/qca/ap121/Kconfig | 5 ++++- board/qca/ap143/Kconfig | 5 ++++- board/qemu-mips/Kconfig | 5 ++++- board/tplink/wdr4300/Kconfig | 5 ++++- include/configs/pic32mzdask.h | 1 - 12 files changed, 53 insertions(+), 28 deletions(-) (limited to 'include') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a79224e525e..5c30ae981df 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -252,21 +252,27 @@ config SYS_DCACHE_SIZE help The total size of the L1 Dcache, if known at compile time. +config SYS_DCACHE_LINE_SIZE + hex + default 0 + help + The size of L1 Dcache lines, if known at compile time. + config SYS_ICACHE_SIZE int default 0 help The total size of the L1 ICache, if known at compile time. -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE int default 0 help - The size of L1 cache lines, if known at compile time. + The size of L1 Icache lines, if known at compile time. config SYS_CACHE_SIZE_AUTO def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ - SYS_CACHELINE_SIZE = 0 + SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 help Select this (or let it be auto-selected by not defining any cache sizes) in order to allow U-Boot to automatically detect the sizes diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 806bd26ba98..0cea581e5d8 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -12,4 +12,11 @@ #define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) +/* + * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for + * DMA buffer alignment. Satisfy those drivers by providing it as a synonym + * of ARCH_DMA_MINALIGN for now. + */ +#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN + #endif /* __MIPS_CACHE_H__ */ diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index fbaafee8cde..19a42ff8316 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -9,23 +9,13 @@ #include #include -#ifndef CONFIG_SYS_CACHE_SIZE_AUTO - static inline unsigned long icache_line_size(void) { - return CONFIG_SYS_CACHELINE_SIZE; -} - -static inline unsigned long dcache_line_size(void) -{ - return CONFIG_SYS_CACHELINE_SIZE; -} + unsigned long conf1, il; -#else /* !CONFIG_SYS_CACHELINE_SIZE */ + if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO)) + return CONFIG_SYS_ICACHE_LINE_SIZE; -static inline unsigned long icache_line_size(void) -{ - unsigned long conf1, il; conf1 = read_c0_config1(); il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF; if (!il) @@ -36,6 +26,10 @@ static inline unsigned long icache_line_size(void) static inline unsigned long dcache_line_size(void) { unsigned long conf1, dl; + + if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO)) + return CONFIG_SYS_DCACHE_LINE_SIZE; + conf1 = read_c0_config1(); dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF; if (!dl) @@ -43,8 +37,6 @@ static inline unsigned long dcache_line_size(void) return 2 << dl; } -#endif /* !CONFIG_SYS_CACHELINE_SIZE */ - void flush_cache(ulong start_addr, ulong size) { unsigned long ilsize = icache_line_size(); diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 4bb9a17e749..bc8ab27b58d 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -101,14 +101,14 @@ LEAF(mips_cache_reset) #ifndef CONFIG_SYS_CACHE_SIZE_AUTO li t2, CONFIG_SYS_ICACHE_SIZE - li t8, CONFIG_SYS_CACHELINE_SIZE + li t8, CONFIG_SYS_ICACHE_LINE_SIZE #else l1_info t2, t8, MIPS_CONF1_IA_SHF #endif #ifndef CONFIG_SYS_CACHE_SIZE_AUTO li t3, CONFIG_SYS_DCACHE_SIZE - li t9, CONFIG_SYS_CACHELINE_SIZE + li t9, CONFIG_SYS_DCACHE_LINE_SIZE #else l1_info t3, t9, MIPS_CONF1_DA_SHF #endif diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig index 1715a289755..448176d8ba8 100644 --- a/board/dbau1x00/Kconfig +++ b/board/dbau1x00/Kconfig @@ -15,10 +15,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 16384 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 16384 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 menu "dbau1x00 board options" diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig index 5bb6f03f30f..df7c0296c7d 100644 --- a/board/micronas/vct/Kconfig +++ b/board/micronas/vct/Kconfig @@ -15,10 +15,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 16384 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 16384 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 menu "vct board options" diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig index 27b2ef000b0..ef8905d46a5 100644 --- a/board/pb1x00/Kconfig +++ b/board/pb1x00/Kconfig @@ -15,10 +15,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 16384 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 16384 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 endif diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig index f28ea1cd44f..4fd6a7167a5 100644 --- a/board/qca/ap121/Kconfig +++ b/board/qca/ap121/Kconfig @@ -15,10 +15,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 32768 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 65536 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 endif diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig index ff02236d5d8..74c632a03e7 100644 --- a/board/qca/ap143/Kconfig +++ b/board/qca/ap143/Kconfig @@ -15,10 +15,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 32768 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 65536 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 endif diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig index 66957e7a57a..e696a12192b 100644 --- a/board/qemu-mips/Kconfig +++ b/board/qemu-mips/Kconfig @@ -14,10 +14,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 16384 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 16384 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 endif diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig index ded7f9b1798..67a0228773b 100644 --- a/board/tplink/wdr4300/Kconfig +++ b/board/tplink/wdr4300/Kconfig @@ -18,10 +18,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 32768 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 65536 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 endif diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index fb2e41fd92e..319e3b5111e 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -100,7 +100,6 @@ * USB Configuration */ #define CONFIG_USB_MUSB_PIO_ONLY -#define CONFIG_SYS_CACHELINE_SIZE 16 /*----------------------------------------------------------------------- * File System Configuration -- cgit v1.3.1 From ad5b48abfe7729d7e0eefcea8693d879af9915b7 Mon Sep 17 00:00:00 2001 From: Wills Wang Date: Mon, 30 May 2016 22:54:52 +0800 Subject: mips: ath79: Use 8MB flash profile for mtd partition by default Change bootm flash address and mtd partition table for 8MB flash profile. Signed-off-by: Wills Wang --- include/configs/ap121.h | 4 ++-- include/configs/ap143.h | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/ap121.h b/include/configs/ap121.h index f069d501302..b01031c8bbe 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -40,13 +40,13 @@ "rootfstype=squashfs" #define CONFIG_BOOTCOMMAND "sf probe;" \ "mtdparts default;" \ - "bootm 0x9f300000" + "bootm 0x9f650000" #define CONFIG_LZMA #define MTDIDS_DEFAULT "nor0=spi-flash.0" #define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \ "256k(u-boot),64k(u-boot-env)," \ - "2752k(rootfs),896k(uImage)," \ + "6144k(rootfs),1600k(uImage)," \ "64k(NVRAM),64k(ART)" #define CONFIG_ENV_SPI_MAX_HZ 25000000 diff --git a/include/configs/ap143.h b/include/configs/ap143.h index e45f743936d..0fa73a79a59 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -44,14 +44,14 @@ "rootfstype=squashfs" #define CONFIG_BOOTCOMMAND "sf probe;" \ "mtdparts default;" \ - "bootm 0x9f300000" + "bootm 0x9f680000" #define CONFIG_LZMA #define MTDIDS_DEFAULT "nor0=spi-flash.0" #define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \ "256k(u-boot),64k(u-boot-env)," \ - "2752k(rootfs),896k(uImage)," \ - "64k(NVRAM),64k(ART)" + "6336k(rootfs),1472k(uImage)," \ + "64k(ART)" #define CONFIG_ENV_SPI_MAX_HZ 25000000 #define CONFIG_ENV_IS_IN_SPI_FLASH -- cgit v1.3.1 From 6f41751f4683aaf310b31b29c26e3da5f478dc07 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 31 May 2016 20:41:54 +0900 Subject: Revert "image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro." This reverts commit 56adbb38727320375b2f695bd04600d766d8a1b3. Since commit 56adbb387273 ("image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro."), I found my boards fail to boot Linux because the commit changed the logic of macros it touched. Now, IMAGE_ENABLE_RAMDISK_HIGH and IMAGE_BOOT_GET_CMDLINE are 0 for all the boards. As you can see in include/linux/kconfig.h, CONFIG_IS_ENABLE() (and IS_ENABLED() as well) can only take a macro that is either defined as 1 or undefined. This is met for boolean options defined in Kconfig. On the other hand, CONFIG_SYS_BOOT_RAMDISK_HIGH and CONFIG_SYS_BOOT_GET_CMDLINE are defined without any value in arch/*/include/asm/config.h . This kind of clean-up is welcome, but the options should be moved to Kconfig beforehand. Moreover, CONFIG_IS_ENABLED(SPL_CRC32_SUPPORT) looks weird. It should be either CONFIG_IS_ENABLED(CRC32_SUPPORT) or IS_ENABLED(CONFIG_SPL_CRC32_SUPPORT). But, I see no define for CONFIG_SPL_CRC32_SUPPORT anywhere. Likewise for the other three. The logic of IMAGE_OF_BOARD_SETUP and IMAGE_OF_SYSTEM_SETUP were also changed for SPL. This can be a problem for boards defining CONFIG_SPL_OF_LIBFDT. I guess it should have been changed to IS_ENABLED(CONFIG_OF_BOARD_SETUP). In the first place, if we replace the references in C code, the macros IMAGE_* will go away. if (IS_ENABLED(CONFIG_OF_BOARD_SETUP) { ... } Signed-off-by: Masahiro Yamada --- include/image.h | 69 +++++++++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 57 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/image.h b/include/image.h index 80a445408c2..a8f6bd16f69 100644 --- a/include/image.h +++ b/include/image.h @@ -52,15 +52,19 @@ struct lmb; #include #include #include -# ifdef CONFIG_FIT_DISABLE_SHA256 -# undef CONFIG_SHA256 -# undef IMAGE_ENABLE_SHA256 -# endif # ifdef CONFIG_SPL_BUILD -# define IMAGE_ENABLE_CRC32 CONFIG_IS_ENABLED(SPL_CRC32_SUPPORT) -# define IMAGE_ENABLE_MD5 CONFIG_IS_ENABLED(SPL_MD5_SUPPORT) -# define IMAGE_ENABLE_SHA1 CONFIG_IS_ENABLED(SPL_SHA1_SUPPORT) -# define IMAGE_ENABLE_SHA256 CONFIG_IS_ENABLED(SPL_SHA256_SUPPORT) +# ifdef CONFIG_SPL_CRC32_SUPPORT +# define IMAGE_ENABLE_CRC32 1 +# endif +# ifdef CONFIG_SPL_MD5_SUPPORT +# define IMAGE_ENABLE_MD5 1 +# endif +# ifdef CONFIG_SPL_SHA1_SUPPORT +# define IMAGE_ENABLE_SHA1 1 +# endif +# ifdef CONFIG_SPL_SHA256_SUPPORT +# define IMAGE_ENABLE_SHA256 1 +# endif # else # define CONFIG_CRC32 /* FIT images need CRC32 support */ # define CONFIG_MD5 /* and MD5 */ @@ -71,12 +75,53 @@ struct lmb; # define IMAGE_ENABLE_SHA1 1 # define IMAGE_ENABLE_SHA256 1 # endif + +#ifdef CONFIG_FIT_DISABLE_SHA256 +#undef CONFIG_SHA256 +#undef IMAGE_ENABLE_SHA256 +#endif + +#ifndef IMAGE_ENABLE_CRC32 +#define IMAGE_ENABLE_CRC32 0 +#endif + +#ifndef IMAGE_ENABLE_MD5 +#define IMAGE_ENABLE_MD5 0 +#endif + +#ifndef IMAGE_ENABLE_SHA1 +#define IMAGE_ENABLE_SHA1 0 +#endif + +#ifndef IMAGE_ENABLE_SHA256 +#define IMAGE_ENABLE_SHA256 0 +#endif + #endif /* IMAGE_ENABLE_FIT */ -#define IMAGE_ENABLE_RAMDISK_HIGH CONFIG_IS_ENABLED(SYS_BOOT_RAMDISK_HIGH) -#define IMAGE_BOOT_GET_CMDLINE CONFIG_IS_ENABLED(SYS_BOOT_GET_CMDLINE) -#define IMAGE_OF_BOARD_SETUP CONFIG_IS_ENABLED(OF_BOARD_SETUP) -#define IMAGE_OF_SYSTEM_SETUP CONFIG_IS_ENABLED(OF_SYSTEM_SETUP) +#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH +# define IMAGE_ENABLE_RAMDISK_HIGH 1 +#else +# define IMAGE_ENABLE_RAMDISK_HIGH 0 +#endif + +#ifdef CONFIG_SYS_BOOT_GET_CMDLINE +# define IMAGE_BOOT_GET_CMDLINE 1 +#else +# define IMAGE_BOOT_GET_CMDLINE 0 +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +# define IMAGE_OF_BOARD_SETUP 1 +#else +# define IMAGE_OF_BOARD_SETUP 0 +#endif + +#ifdef CONFIG_OF_SYSTEM_SETUP +# define IMAGE_OF_SYSTEM_SETUP 1 +#else +# define IMAGE_OF_SYSTEM_SETUP 0 +#endif /* * Operating System Codes -- cgit v1.3.1 From e6bf0ca0e2ef8d87d754f788be1b9b5d58c01860 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 12 May 2016 12:07:40 -0600 Subject: ARM: tegra: fix naming in GPIO DT binding header According to the Tegra TRM, GPIOs are aggregated into /ports/ of 8 GPIOs, not into /banks/. Fix to correctly reflect this naming convention. While this seems like silly churn, it will become slightly more important once we introduce the GPIO binding for upcoming Tegra chips. This mirrors an identical commit in the Linux kernel. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- include/dt-bindings/gpio/tegra-gpio.h | 68 +++++++++++++++++------------------ 1 file changed, 34 insertions(+), 34 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h index 197dc28b676..a1c09e88e80 100644 --- a/include/dt-bindings/gpio/tegra-gpio.h +++ b/include/dt-bindings/gpio/tegra-gpio.h @@ -12,40 +12,40 @@ #include -#define TEGRA_GPIO_BANK_ID_A 0 -#define TEGRA_GPIO_BANK_ID_B 1 -#define TEGRA_GPIO_BANK_ID_C 2 -#define TEGRA_GPIO_BANK_ID_D 3 -#define TEGRA_GPIO_BANK_ID_E 4 -#define TEGRA_GPIO_BANK_ID_F 5 -#define TEGRA_GPIO_BANK_ID_G 6 -#define TEGRA_GPIO_BANK_ID_H 7 -#define TEGRA_GPIO_BANK_ID_I 8 -#define TEGRA_GPIO_BANK_ID_J 9 -#define TEGRA_GPIO_BANK_ID_K 10 -#define TEGRA_GPIO_BANK_ID_L 11 -#define TEGRA_GPIO_BANK_ID_M 12 -#define TEGRA_GPIO_BANK_ID_N 13 -#define TEGRA_GPIO_BANK_ID_O 14 -#define TEGRA_GPIO_BANK_ID_P 15 -#define TEGRA_GPIO_BANK_ID_Q 16 -#define TEGRA_GPIO_BANK_ID_R 17 -#define TEGRA_GPIO_BANK_ID_S 18 -#define TEGRA_GPIO_BANK_ID_T 19 -#define TEGRA_GPIO_BANK_ID_U 20 -#define TEGRA_GPIO_BANK_ID_V 21 -#define TEGRA_GPIO_BANK_ID_W 22 -#define TEGRA_GPIO_BANK_ID_X 23 -#define TEGRA_GPIO_BANK_ID_Y 24 -#define TEGRA_GPIO_BANK_ID_Z 25 -#define TEGRA_GPIO_BANK_ID_AA 26 -#define TEGRA_GPIO_BANK_ID_BB 27 -#define TEGRA_GPIO_BANK_ID_CC 28 -#define TEGRA_GPIO_BANK_ID_DD 29 -#define TEGRA_GPIO_BANK_ID_EE 30 -#define TEGRA_GPIO_BANK_ID_FF 31 +#define TEGRA_GPIO_PORT_A 0 +#define TEGRA_GPIO_PORT_B 1 +#define TEGRA_GPIO_PORT_C 2 +#define TEGRA_GPIO_PORT_D 3 +#define TEGRA_GPIO_PORT_E 4 +#define TEGRA_GPIO_PORT_F 5 +#define TEGRA_GPIO_PORT_G 6 +#define TEGRA_GPIO_PORT_H 7 +#define TEGRA_GPIO_PORT_I 8 +#define TEGRA_GPIO_PORT_J 9 +#define TEGRA_GPIO_PORT_K 10 +#define TEGRA_GPIO_PORT_L 11 +#define TEGRA_GPIO_PORT_M 12 +#define TEGRA_GPIO_PORT_N 13 +#define TEGRA_GPIO_PORT_O 14 +#define TEGRA_GPIO_PORT_P 15 +#define TEGRA_GPIO_PORT_Q 16 +#define TEGRA_GPIO_PORT_R 17 +#define TEGRA_GPIO_PORT_S 18 +#define TEGRA_GPIO_PORT_T 19 +#define TEGRA_GPIO_PORT_U 20 +#define TEGRA_GPIO_PORT_V 21 +#define TEGRA_GPIO_PORT_W 22 +#define TEGRA_GPIO_PORT_X 23 +#define TEGRA_GPIO_PORT_Y 24 +#define TEGRA_GPIO_PORT_Z 25 +#define TEGRA_GPIO_PORT_AA 26 +#define TEGRA_GPIO_PORT_BB 27 +#define TEGRA_GPIO_PORT_CC 28 +#define TEGRA_GPIO_PORT_DD 29 +#define TEGRA_GPIO_PORT_EE 30 +#define TEGRA_GPIO_PORT_FF 31 -#define TEGRA_GPIO(bank, offset) \ - ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset) +#define TEGRA_GPIO(port, offset) \ + ((TEGRA_GPIO_PORT_##port * 8) + offset) #endif -- cgit v1.3.1 From 601800be22a37cc518e023adc8e32ad15f00a2c6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 12 May 2016 12:07:41 -0600 Subject: ARM: tegra: convert CONFIG_TEGRA_GPIO to Kconfig Future chips will contain different GPIO HW. This change will enable future SoC support to select the appropriate GPIO driver for their HW, in a future-looking fashion, using Kconfig. TEGRA_GPIO is not simply selected by TEGRA_COMMON (even though all current Tegra chips used this GPIO HW) to simplify the later addition of support for Tegra SoCs that use different GPIO HW. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/mach-tegra/Kconfig | 2 ++ drivers/gpio/Kconfig | 7 +++++++ include/configs/tegra-common.h | 1 - 3 files changed, 9 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index ba6983f3dfd..616a1c3cf34 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -22,6 +22,7 @@ config TEGRA_ARMV7_COMMON select SPL select SUPPORT_SPL select TEGRA_COMMON + select TEGRA_GPIO config TEGRA_ARMV8_COMMON bool "Tegra 64-bit common options" @@ -50,6 +51,7 @@ config TEGRA124 config TEGRA210 bool "Tegra210 family" + select TEGRA_GPIO select TEGRA_ARMV8_COMMON endchoice diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 93a7e8c6c23..f7307442149 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -109,6 +109,13 @@ config SANDBOX_GPIO_COUNT of 'anonymous' GPIOs that do not belong to any device or bank. Select a suitable value depending on your needs. +config TEGRA_GPIO + bool "Tegra20..210 GPIO driver" + depends on DM_GPIO + help + Support for the GPIO controller contained in NVIDIA Tegra20 through + Tegra210. + config GPIO_UNIPHIER bool "UniPhier GPIO" depends on ARCH_UNIPHIER diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 92d4dd8e519..7b0940a7f20 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -111,7 +111,6 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_TEGRA_GPIO #define CONFIG_CMD_ENTERRCM /* Defines for SPL */ -- cgit v1.3.1 From 074a1fdd27953aacb59346c83baaf443335ea04e Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 25 May 2016 14:38:51 -0600 Subject: gpio: add Tegra186 GPIO driver Tegra186's GPIO controller register layout is significantly different from previous chips, so add a new driver for it. In fact, there are two different GPIO controllers in Tegra186 that share a similar register layout, but very different port mapping. This driver covers both. The DT binding is already present in the Linux kernel (in linux-next via the Tegra tree so far). Signed-off-by: Stephen Warren Reviewed-by: Simon Glass # v1 Signed-off-by: Tom Warren --- .../gpio/nvidia,tegra186-gpio.txt | 161 ++++++++++++ drivers/gpio/Kconfig | 8 + drivers/gpio/Makefile | 1 + drivers/gpio/rk_gpio.c | 1 - drivers/gpio/tegra186_gpio.c | 288 +++++++++++++++++++++ drivers/gpio/tegra186_gpio_priv.h | 61 +++++ include/dt-bindings/gpio/tegra186-gpio.h | 60 +++++ 7 files changed, 579 insertions(+), 1 deletion(-) create mode 100644 doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt create mode 100644 drivers/gpio/tegra186_gpio.c create mode 100644 drivers/gpio/tegra186_gpio_priv.h create mode 100644 include/dt-bindings/gpio/tegra186-gpio.h (limited to 'include') diff --git a/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt b/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt new file mode 100644 index 00000000000..c82a2e221bc --- /dev/null +++ b/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt @@ -0,0 +1,161 @@ +NVIDIA Tegra186 GPIO controllers + +Tegra186 contains two GPIO controllers; a main controller and an "AON" +controller. This binding document applies to both controllers. The register +layouts for the controllers share many similarities, but also some significant +differences. Hence, this document describes closely related but different +bindings and compatible values. + +The Tegra186 GPIO controller allows software to set the IO direction of, and +read/write the value of, numerous GPIO signals. Routing of GPIO signals to +package balls is under the control of a separate pin controller HW block. Two +major sets of registers exist: + +a) Security registers, which allow configuration of allowed access to the GPIO +register set. These registers exist in a single contiguous block of physical +address space. The size of this block, and the security features available, +varies between the different GPIO controllers. + +Access to this set of registers is not necessary in all circumstances. Code +that wishes to configure access to the GPIO registers needs access to these +registers to do so. Code which simply wishes to read or write GPIO data does not +need access to these registers. + +b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO +controllers, these registers are exposed via multiple "physical aliases" in +address space, each of which access the same underlying state. See the hardware +documentation for rationale. Any particular GPIO client is expected to access +just one of these physical aliases. + +Tegra HW documentation describes a unified naming convention for all GPIOs +implemented by the SoC. Each GPIO is assigned to a port, and a port may control +a number of GPIOs. Thus, each GPIO is named according to an alphabetical port +name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6, +or GPIO_PCC3. + +The number of ports implemented by each GPIO controller varies. The number of +implemented GPIOs within each port varies. GPIO registers within a controller +are grouped and laid out according to the port they affect. + +The mapping from port name to the GPIO controller that implements that port, and +the mapping from port name to register offset within a controller, are both +extremely non-linear. The header file +describes the port-level mapping. In that file, the naming convention for ports +matches the HW documentation. The values chosen for the names are alphabetically +sorted within a particular controller. Drivers need to map between the DT GPIO +IDs and HW register offsets using a lookup table. + +Each GPIO controller can generate a number of interrupt signals. Each signal +represents the aggregate status for all GPIOs within a set of ports. Thus, the +number of interrupt signals generated by a controller varies as a rough function +of the number of ports it implements. Note that the HW documentation refers to +both the overall controller HW module and the sets-of-ports as "controllers". + +Each GPIO controller in fact generates multiple interrupts signals for each set +of ports. Each GPIO may be configured to feed into a specific one of the +interrupt signals generated by a set-of-ports. The intent is for each generated +signal to be routed to a different CPU, thus allowing different CPUs to each +handle subsets of the interrupts within a port. The status of each of these +per-port-set signals is reported via a separate register. Thus, a driver needs +to know which status register to observe. This binding currently defines no +configuration mechanism for this. By default, drivers should use register +GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could +define a property to configure this. + +Required properties: +- compatible + Array of strings. + One of: + - "nvidia,tegra186-gpio". + - "nvidia,tegra186-gpio-aon". +- reg-names + Array of strings. + Contains a list of names for the register spaces described by the reg + property. May contain the following entries, in any order: + - "gpio": Mandatory. GPIO control registers. This may cover either: + a) The single physical alias that this OS should use. + b) All physical aliases that exist in the controller. This is + appropriate when the OS is responsible for managing assignment of + the physical aliases. + - "security": Optional. Security configuration registers. + Users of this binding MUST look up entries in the reg property by name, + using this reg-names property to do so. +- reg + Array of (physical base address, length) tuples. + Must contain one entry per entry in the reg-names property, in a matching + order. +- interrupts + Array of interrupt specifiers. + The interrupt outputs from the HW block, one per set of ports, in the + order the HW manual describes them. The number of entries required varies + depending on compatible value: + - "nvidia,tegra186-gpio": 6 entries. + - "nvidia,tegra186-gpio-aon": 1 entry. +- gpio-controller + Boolean. + Marks the device node as a GPIO controller/provider. +- #gpio-cells + Single-cell integer. + Must be <2>. + Indicates how many cells are used in a consumer's GPIO specifier. + In the specifier: + - The first cell is the pin number. + See . + - The second cell contains flags: + - Bit 0 specifies polarity + - 0: Active-high (normal). + - 1: Active-low (inverted). +- interrupt-controller + Boolean. + Marks the device node as an interrupt controller/provider. +- #interrupt-cells + Single-cell integer. + Must be <2>. + Indicates how many cells are used in a consumer's interrupt specifier. + In the specifier: + - The first cell is the GPIO number. + See . + - The second cell is contains flags: + - Bits [3:0] indicate trigger type and level: + - 1: Low-to-high edge triggered. + - 2: High-to-low edge triggered. + - 4: Active high level-sensitive. + - 8: Active low level-sensitive. + Valid combinations are 1, 2, 3, 4, 8. + +Example: + +#include + +gpio@2200000 { + compatible = "nvidia,tegra186-gpio"; + reg-names = "security", "gpio"; + reg = + <0x0 0x2200000 0x0 0x10000>, + <0x0 0x2210000 0x0 0x10000>; + interrupts = + <0 47 IRQ_TYPE_LEVEL_HIGH>, + <0 50 IRQ_TYPE_LEVEL_HIGH>, + <0 53 IRQ_TYPE_LEVEL_HIGH>, + <0 56 IRQ_TYPE_LEVEL_HIGH>, + <0 59 IRQ_TYPE_LEVEL_HIGH>, + <0 180 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +}; + +gpio@c2f0000 { + compatible = "nvidia,tegra186-gpio-aon"; + reg-names = "security", "gpio"; + reg = + <0x0 0xc2f0000 0x0 0x1000>, + <0x0 0xc2f1000 0x0 0x1000>; + interrupts = + <0 60 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +}; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f7307442149..32219ed4788 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -116,6 +116,14 @@ config TEGRA_GPIO Support for the GPIO controller contained in NVIDIA Tegra20 through Tegra210. +config TEGRA186_GPIO + bool "Tegra186 GPIO driver" + depends on DM_GPIO + help + Support for the GPIO controller contained in NVIDIA Tegra186. This + covers both the "main" and "AON" controller instances, even though + they have slightly different register layout. + config GPIO_UNIPHIER bool "UniPhier GPIO" depends on ARCH_UNIPHIER diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index ddec1ef8dee..3c4310176d1 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_S5P) += s5p_gpio.o obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o +obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o obj-$(CONFIG_ALTERA_PIO) += altera_pio.o diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index fefe3ca2035..64abcbaa0ac 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/drivers/gpio/tegra186_gpio.c b/drivers/gpio/tegra186_gpio.c new file mode 100644 index 00000000000..1c681514db9 --- /dev/null +++ b/drivers/gpio/tegra186_gpio.c @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2010-2016, NVIDIA CORPORATION. + * (based on tegra_gpio.c) + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "tegra186_gpio_priv.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct tegra186_gpio_port_data { + const char *name; + uint32_t offset; +}; + +struct tegra186_gpio_ctlr_data { + const struct tegra186_gpio_port_data *ports; + uint32_t port_count; +}; + +struct tegra186_gpio_platdata { + const char *name; + uint32_t *regs; +}; + +static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg, + uint32_t gpio) +{ + struct tegra186_gpio_platdata *plat = dev->platdata; + uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4; + + return &(plat->regs[index]); +} + +static int tegra186_gpio_set_out(struct udevice *dev, unsigned offset, + bool output) +{ + uint32_t *reg; + uint32_t rval; + + reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_CONTROL, offset); + rval = readl(reg); + if (output) + rval &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; + else + rval |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; + writel(rval, reg); + + reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset); + rval = readl(reg); + if (output) + rval |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; + else + rval &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; + rval |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; + writel(rval, reg); + + return 0; +} + +static int tegra186_gpio_set_val(struct udevice *dev, unsigned offset, bool val) +{ + uint32_t *reg; + uint32_t rval; + + reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE, offset); + rval = readl(reg); + if (val) + rval |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; + else + rval &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; + writel(rval, reg); + + return 0; +} + +static int tegra186_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + return tegra186_gpio_set_out(dev, offset, false); +} + +static int tegra186_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + int ret; + + ret = tegra186_gpio_set_val(dev, offset, value != 0); + if (ret) + return ret; + return tegra186_gpio_set_out(dev, offset, true); +} + +static int tegra186_gpio_get_value(struct udevice *dev, unsigned offset) +{ + uint32_t *reg; + uint32_t rval; + + reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset); + rval = readl(reg); + + if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT) + reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE, + offset); + else + reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_INPUT, offset); + + rval = readl(reg); + return !!rval; +} + +static int tegra186_gpio_set_value(struct udevice *dev, unsigned offset, + int value) +{ + return tegra186_gpio_set_val(dev, offset, value != 0); +} + +static int tegra186_gpio_get_function(struct udevice *dev, unsigned offset) +{ + uint32_t *reg; + uint32_t rval; + + reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset); + rval = readl(reg); + if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + +static int tegra186_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct fdtdec_phandle_args *args) +{ + int gpio, port, ret; + + gpio = args->args[0]; + port = gpio / TEGRA186_GPIO_PER_GPIO_COUNT; + ret = device_get_child(dev, port, &desc->dev); + if (ret) + return ret; + desc->offset = gpio % TEGRA186_GPIO_PER_GPIO_COUNT; + desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; + + return 0; +} + +static const struct dm_gpio_ops tegra186_gpio_ops = { + .direction_input = tegra186_gpio_direction_input, + .direction_output = tegra186_gpio_direction_output, + .get_value = tegra186_gpio_get_value, + .set_value = tegra186_gpio_set_value, + .get_function = tegra186_gpio_get_function, + .xlate = tegra186_gpio_xlate, +}; + +/** + * We have a top-level GPIO device with no actual GPIOs. It has a child device + * for each port within the controller. + */ +static int tegra186_gpio_bind(struct udevice *parent) +{ + struct tegra186_gpio_platdata *parent_plat = parent->platdata; + struct tegra186_gpio_ctlr_data *ctlr_data = + (struct tegra186_gpio_ctlr_data *)dev_get_driver_data(parent); + uint32_t *regs; + int port, ret; + + /* If this is a child device, there is nothing to do here */ + if (parent_plat) + return 0; + + regs = (uint32_t *)dev_get_addr_name(parent, "gpio"); + if (regs == (uint32_t *)FDT_ADDR_T_NONE) + return -ENODEV; + + for (port = 0; port < ctlr_data->port_count; port++) { + struct tegra186_gpio_platdata *plat; + struct udevice *dev; + + plat = calloc(1, sizeof(*plat)); + if (!plat) + return -ENOMEM; + plat->name = ctlr_data->ports[port].name; + plat->regs = &(regs[ctlr_data->ports[port].offset / 4]); + + ret = device_bind(parent, parent->driver, plat->name, plat, + -1, &dev); + if (ret) + return ret; + dev->of_offset = parent->of_offset; + } + + return 0; +} + +static int tegra186_gpio_probe(struct udevice *dev) +{ + struct tegra186_gpio_platdata *plat = dev->platdata; + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + /* Only child devices have ports */ + if (!plat) + return 0; + + uc_priv->gpio_count = TEGRA186_GPIO_PER_GPIO_COUNT; + uc_priv->bank_name = plat->name; + + return 0; +} + +static const struct tegra186_gpio_port_data tegra186_gpio_main_ports[] = { + {"A", 0x2000}, + {"B", 0x3000}, + {"C", 0x3200}, + {"D", 0x3400}, + {"E", 0x2200}, + {"F", 0x2400}, + {"G", 0x4200}, + {"H", 0x1000}, + {"I", 0x0800}, + {"J", 0x5000}, + {"K", 0x5200}, + {"L", 0x1200}, + {"M", 0x5600}, + {"N", 0x0000}, + {"O", 0x0200}, + {"P", 0x4000}, + {"Q", 0x0400}, + {"R", 0x0a00}, + {"T", 0x0600}, + {"X", 0x1400}, + {"Y", 0x1600}, + {"BB", 0x2600}, + {"CC", 0x5400}, +}; + +static const struct tegra186_gpio_ctlr_data tegra186_gpio_main_data = { + .ports = tegra186_gpio_main_ports, + .port_count = ARRAY_SIZE(tegra186_gpio_main_ports), +}; + +static const struct tegra186_gpio_port_data tegra186_gpio_aon_ports[] = { + {"S", 0x0200}, + {"U", 0x0400}, + {"V", 0x0800}, + {"W", 0x0a00}, + {"Z", 0x0e00}, + {"AA", 0x0c00}, + {"EE", 0x0600}, + {"FF", 0x0000}, +}; + +static const struct tegra186_gpio_ctlr_data tegra186_gpio_aon_data = { + .ports = tegra186_gpio_aon_ports, + .port_count = ARRAY_SIZE(tegra186_gpio_aon_ports), +}; + +static const struct udevice_id tegra186_gpio_ids[] = { + { + .compatible = "nvidia,tegra186-gpio", + .data = (ulong)&tegra186_gpio_main_data, + }, + { + .compatible = "nvidia,tegra186-gpio-aon", + .data = (ulong)&tegra186_gpio_aon_data, + }, + { } +}; + +U_BOOT_DRIVER(tegra186_gpio) = { + .name = "tegra186_gpio", + .id = UCLASS_GPIO, + .of_match = tegra186_gpio_ids, + .bind = tegra186_gpio_bind, + .probe = tegra186_gpio_probe, + .ops = &tegra186_gpio_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/gpio/tegra186_gpio_priv.h b/drivers/gpio/tegra186_gpio_priv.h new file mode 100644 index 00000000000..9e85a4343b2 --- /dev/null +++ b/drivers/gpio/tegra186_gpio_priv.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _TEGRA186_GPIO_PRIV_H_ +#define _TEGRA186_GPIO_PRIV_H_ + +/* + * For each GPIO, there are a set of registers than affect it, all packed + * back-to-back. + */ +#define TEGRA186_GPIO_ENABLE_CONFIG 0x00 +#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) +#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) +#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SHIFT 2 +#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK 3 +#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE 0 +#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL 1 +#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE 2 +#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE 3 +#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL_HIGH_RISING BIT(4) +#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE_ENABLE BIT(5) +#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT_ENABLE BIT(6) +#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMPING_ENABLE BIT(7) + +#define TEGRA186_GPIO_DEBOUNCE_THRESHOLD 0x04 + +#define TEGRA186_GPIO_INPUT 0x08 + +#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c +#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) + +#define TEGRA186_GPIO_OUTPUT_VALUE 0x10 +#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH 1 + +#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 + +/* + * 8 GPIOs are packed into a port. Their registers appear back-to-back in the + * port's address space. + */ +#define TEGRA186_GPIO_PER_GPIO_STRIDE 0x20 +#define TEGRA186_GPIO_PER_GPIO_COUNT 8 + +/* + * Per-port registers are packed immediately following all of a port's + * per-GPIO registers. + */ +#define TEGRA186_GPIO_INTERRUPT_STATUS_G 0x100 +#define TEGRA186_GPIO_INTERRUPT_STATUS_G_STRIDE 4 +#define TEGRA186_GPIO_INTERRUPT_STATUS_G_COUNT 8 + +/* + * The registers for multiple ports are packed together back-to-back to form + * the overall controller. + */ +#define TEGRA186_GPIO_PER_PORT_STRIDE 0x200 + +#endif diff --git a/include/dt-bindings/gpio/tegra186-gpio.h b/include/dt-bindings/gpio/tegra186-gpio.h new file mode 100644 index 00000000000..7e6fb95da14 --- /dev/null +++ b/include/dt-bindings/gpio/tegra186-gpio.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + * + * This header provides constants for binding nvidia,tegra186-gpio*. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H + +#include + +/* GPIOs implemented by main GPIO controller */ +#define TEGRA_MAIN_GPIO_PORT_A 0 +#define TEGRA_MAIN_GPIO_PORT_B 1 +#define TEGRA_MAIN_GPIO_PORT_C 2 +#define TEGRA_MAIN_GPIO_PORT_D 3 +#define TEGRA_MAIN_GPIO_PORT_E 4 +#define TEGRA_MAIN_GPIO_PORT_F 5 +#define TEGRA_MAIN_GPIO_PORT_G 6 +#define TEGRA_MAIN_GPIO_PORT_H 7 +#define TEGRA_MAIN_GPIO_PORT_I 8 +#define TEGRA_MAIN_GPIO_PORT_J 9 +#define TEGRA_MAIN_GPIO_PORT_K 10 +#define TEGRA_MAIN_GPIO_PORT_L 11 +#define TEGRA_MAIN_GPIO_PORT_M 12 +#define TEGRA_MAIN_GPIO_PORT_N 13 +#define TEGRA_MAIN_GPIO_PORT_O 14 +#define TEGRA_MAIN_GPIO_PORT_P 15 +#define TEGRA_MAIN_GPIO_PORT_Q 16 +#define TEGRA_MAIN_GPIO_PORT_R 17 +#define TEGRA_MAIN_GPIO_PORT_T 18 +#define TEGRA_MAIN_GPIO_PORT_X 19 +#define TEGRA_MAIN_GPIO_PORT_Y 20 +#define TEGRA_MAIN_GPIO_PORT_BB 21 +#define TEGRA_MAIN_GPIO_PORT_CC 22 + +#define TEGRA_MAIN_GPIO(port, offset) \ + ((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset) + +/* GPIOs implemented by AON GPIO controller */ +#define TEGRA_AON_GPIO_PORT_S 0 +#define TEGRA_AON_GPIO_PORT_U 1 +#define TEGRA_AON_GPIO_PORT_V 2 +#define TEGRA_AON_GPIO_PORT_W 3 +#define TEGRA_AON_GPIO_PORT_Z 4 +#define TEGRA_AON_GPIO_PORT_AA 5 +#define TEGRA_AON_GPIO_PORT_EE 6 +#define TEGRA_AON_GPIO_PORT_FF 7 + +#define TEGRA_AON_GPIO(port, offset) \ + ((TEGRA_AON_GPIO_PORT_##port * 8) + offset) + +#endif -- cgit v1.3.1 From 39f633320c569a5d975d2d051ff2683db27bd021 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 12 May 2016 12:11:23 -0600 Subject: mmc: tegra: add basic Tegra186 support Tegra186's MMC controller needs to be explicitly identified. Add another compatible value for it. Tegra186 will use an entirely different clock/reset control mechanism to existing chips, and will use standard clock/reset APIs rather than the existing Tegra-specific custom APIs. The driver support for that isn't ready yet, so simply disable all clock/reset usage if compiling for Tegra186. This must happen at compile time rather than run-time since the custom APIs won't even be compiled in on Tegra186. In the long term, the plan would be to convert the existing custom APIs to standard APIs and get rid of the ifdefs completely. The system's main eMMC will work without any clock/reset support, since the firmware will have already initialized the controller in order to load U-Boot. Hence the driver is useful even in this apparently crippled state. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/tegra_mmc.h | 2 ++ drivers/mmc/tegra_mmc.c | 32 ++++++++++++++++++++++++++++- include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 4 files changed, 35 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index a20bdaa6187..75e56c4ea78 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -134,7 +134,9 @@ struct mmc_host { int id; /* device id/number, 0-3 */ int enabled; /* 1 to enable, 0 to disable */ int width; /* Bus Width, 1, 4 or 8 */ +#ifndef CONFIG_TEGRA186 enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ +#endif struct gpio_desc cd_gpio; /* Change Detect GPIO */ struct gpio_desc pwr_gpio; /* Power GPIO */ struct gpio_desc wp_gpio; /* Write Protect GPIO */ diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index 573819a01e2..c9d9432e5e8 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -11,8 +11,10 @@ #include #include #include +#ifndef CONFIG_TEGRA186 #include #include +#endif #include #include #include @@ -357,8 +359,12 @@ static void mmc_change_clock(struct mmc_host *host, uint clock) */ if (clock == 0) goto out; +#ifndef CONFIG_TEGRA186 clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock, &div); +#else + div = (20000000 + clock - 1) / clock; +#endif debug("div = %d\n", div); writew(0, &host->reg->clkcon); @@ -543,7 +549,9 @@ static int do_mmc_init(int dev_index, bool removable) gpio_get_number(&host->cd_gpio)); host->clock = 0; +#ifndef CONFIG_TEGRA186 clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000); +#endif if (dm_gpio_is_valid(&host->pwr_gpio)) dm_gpio_set_value(&host->pwr_gpio, 1); @@ -568,7 +576,11 @@ static int do_mmc_init(int dev_index, bool removable) * (actually 52MHz) */ host->cfg.f_min = 375000; +#ifndef CONFIG_TEGRA186 host->cfg.f_max = 48000000; +#else + host->cfg.f_max = 375000; +#endif host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; @@ -600,11 +612,13 @@ static int mmc_get_config(const void *blob, int node, struct mmc_host *host, return -FDT_ERR_NOTFOUND; } +#ifndef CONFIG_TEGRA186 host->mmc_id = clock_decode_periph_id(blob, node); if (host->mmc_id == PERIPH_ID_NONE) { debug("%s: could not decode periph id\n", __func__); return -FDT_ERR_NOTFOUND; } +#endif /* * NOTE: mmc->bus_width is determined by mmc.c dynamically. @@ -624,7 +638,13 @@ static int mmc_get_config(const void *blob, int node, struct mmc_host *host, *removablep = !fdtdec_get_bool(blob, node, "non-removable"); debug("%s: found controller at %p, width = %d, periph_id = %d\n", - __func__, host->reg, host->width, host->mmc_id); + __func__, host->reg, host->width, +#ifndef CONFIG_TEGRA186 + host->mmc_id +#else + -1 +#endif + ); return 0; } @@ -668,6 +688,16 @@ void tegra_mmc_init(void) const void *blob = gd->fdt_blob; debug("%s entry\n", __func__); + /* See if any Tegra186 MMC controllers are present */ + count = fdtdec_find_aliases_for_id(blob, "sdhci", + COMPAT_NVIDIA_TEGRA186_SDMMC, node_list, + CONFIG_SYS_MMC_MAX_DEVICE); + debug("%s: count of Tegra186 sdhci nodes is %d\n", __func__, count); + if (process_nodes(blob, node_list, count)) { + printf("%s: Error processing T186 mmc node(s)!\n", __func__); + return; + } + /* See if any Tegra210 MMC controllers are present */ count = fdtdec_find_aliases_for_id(blob, "sdhci", COMPAT_NVIDIA_TEGRA210_SDMMC, node_list, diff --git a/include/fdtdec.h b/include/fdtdec.h index 37d482aba72..54e3d8139fe 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -123,6 +123,7 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */ COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ + COMPAT_NVIDIA_TEGRA186_SDMMC, /* Tegra186 SDMMC controller */ COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */ COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 70acc29c924..ab002e9fa3e 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -30,6 +30,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"), COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"), COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"), + COMPAT(NVIDIA_TEGRA186_SDMMC, "nvidia,tegra186-sdhci"), COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"), COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"), COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"), -- cgit v1.3.1 From c7ba99c8c18a606b95a89366bc4fd94a8295772f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 12 May 2016 13:32:55 -0600 Subject: ARM: tegra: add core Tegra186 support This adds the bare minimum code to support Tegra186, with UART and eMMC working. The empty gpio.h is required because includes it. A future cleanup round may be able to solve this for all Tegra generations at once. mach-tegra/Makefile is adjusted not to compile anything for Tegra186, but instead to defer everything to mach-tegra/tegra186/Makefile. This allows the SoC code to pick-and-choose which of the C files in the "common" mach-tegra/ directory to compile in based on the SoC's needs. Most of the code is not valid for Tegra186, and this approach removes the need for mach-tegra/Makefile to contain many SoC-specific ifdefs. This approach may be applied to all other Tegra SoCs in a future cleanup round. board186.c is introduced to replace board.c and board2.c. These files currently contain a slew of SoC- and board-specific code that is not valid for Tegra186. This approach avoids adding yet more ifdefs to those files. A future cleanup round may refactor most of board*.c into board-/ SoC-specific functions files thus allowing the top-level functions like board_init_early_f to be shared again. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/dts/tegra186.dtsi | 56 +++++++++++++++++++++++ arch/arm/include/asm/arch-tegra186/gpio.h | 10 +++++ arch/arm/include/asm/arch-tegra186/tegra.h | 16 +++++++ arch/arm/mach-tegra/Kconfig | 6 +++ arch/arm/mach-tegra/Makefile | 3 ++ arch/arm/mach-tegra/board186.c | 55 +++++++++++++++++++++++ arch/arm/mach-tegra/tegra186/Kconfig | 15 +++++++ arch/arm/mach-tegra/tegra186/Makefile | 8 ++++ include/configs/tegra186-common.h | 71 ++++++++++++++++++++++++++++++ 9 files changed, 240 insertions(+) create mode 100644 arch/arm/dts/tegra186.dtsi create mode 100644 arch/arm/include/asm/arch-tegra186/gpio.h create mode 100644 arch/arm/include/asm/arch-tegra186/tegra.h create mode 100644 arch/arm/mach-tegra/board186.c create mode 100644 arch/arm/mach-tegra/tegra186/Kconfig create mode 100644 arch/arm/mach-tegra/tegra186/Makefile create mode 100644 include/configs/tegra186-common.h (limited to 'include') diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi new file mode 100644 index 00000000000..18b6a266434 --- /dev/null +++ b/arch/arm/dts/tegra186.dtsi @@ -0,0 +1,56 @@ +#include "skeleton.dtsi" +#include +#include + +/ { + compatible = "nvidia,tegra186"; + #address-cells = <2>; + #size-cells = <2>; + + gpio@2200000 { + compatible = "nvidia,tegra186-gpio"; + reg-names = "security", "gpio"; + reg = + <0x0 0x2200000 0x0 0x10000>, + <0x0 0x2210000 0x0 0x10000>; + interrupts = + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + uarta: serial@3100000 { + compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x03100000 0x0 0x10000>; + reg-shift = <2>; + status = "disabled"; + }; + + sdhci@3460000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x0 0x03460000 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + gpio@c2f0000 { + compatible = "nvidia,tegra186-gpio-aon"; + reg-names = "security", "gpio"; + reg = + <0x0 0xc2f0000 0x0 0x1000>, + <0x0 0xc2f1000 0x0 0x1000>; + interrupts = + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/arch/arm/include/asm/arch-tegra186/gpio.h b/arch/arm/include/asm/arch-tegra186/gpio.h new file mode 100644 index 00000000000..aaecfc7ea6c --- /dev/null +++ b/arch/arm/include/asm/arch-tegra186/gpio.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _TEGRA186_GPIO_H_ +#define _TEGRA186_GPIO_H_ + +#endif diff --git a/arch/arm/include/asm/arch-tegra186/tegra.h b/arch/arm/include/asm/arch-tegra186/tegra.h new file mode 100644 index 00000000000..8031f23873e --- /dev/null +++ b/arch/arm/include/asm/arch-tegra186/tegra.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2013-2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _TEGRA186_TEGRA_H_ +#define _TEGRA186_TEGRA_H_ + +#define GICD_BASE 0x03881000 /* Generic Int Cntrlr Distrib */ +#define GICC_BASE 0x03882000 /* Generic Int Cntrlr CPU I/F */ +#define NV_PA_SDRAM_BASE 0x80000000 + +#include + +#endif diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 616a1c3cf34..b18a12e3420 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -54,6 +54,11 @@ config TEGRA210 select TEGRA_GPIO select TEGRA_ARMV8_COMMON +config TEGRA186 + bool "Tegra186 family" + select TEGRA186_GPIO + select TEGRA_ARMV8_COMMON + endchoice config TEGRA_DISCONNECT_UDC_ON_BOOT @@ -77,5 +82,6 @@ source "arch/arm/mach-tegra/tegra30/Kconfig" source "arch/arm/mach-tegra/tegra114/Kconfig" source "arch/arm/mach-tegra/tegra124/Kconfig" source "arch/arm/mach-tegra/tegra210/Kconfig" +source "arch/arm/mach-tegra/tegra186/Kconfig" endif diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index b2dbc6999c7..12ee1cd7495 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -7,6 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifndef CONFIG_TEGRA186 ifdef CONFIG_SPL_BUILD obj-y += spl.o obj-y += cpu.o @@ -30,9 +31,11 @@ obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o endif +endif obj-$(CONFIG_TEGRA20) += tegra20/ obj-$(CONFIG_TEGRA30) += tegra30/ obj-$(CONFIG_TEGRA114) += tegra114/ obj-$(CONFIG_TEGRA124) += tegra124/ +obj-$(CONFIG_TEGRA186) += tegra186/ obj-$(CONFIG_TEGRA210) += tegra210/ diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c new file mode 100644 index 00000000000..f4b6152a793 --- /dev/null +++ b/arch/arm/mach-tegra/board186.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = (1.5 * 1024 * 1024 * 1024); + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} + +void pad_init_mmc(struct mmc_host *host) +{ +} + +int board_mmc_init(bd_t *bd) +{ + tegra_mmc_init(); + + return 0; +} + +int ft_system_setup(void *blob, bd_t *bd) +{ + return 0; +} diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig new file mode 100644 index 00000000000..124d8e58359 --- /dev/null +++ b/arch/arm/mach-tegra/tegra186/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +if TEGRA186 + +choice + prompt "Tegra186 board select" + +endchoice + +config SYS_SOC + default "tegra186" + +endif diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile new file mode 100644 index 00000000000..ce4610d8f80 --- /dev/null +++ b/arch/arm/mach-tegra/tegra186/Makefile @@ -0,0 +1,8 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +obj-y += ../arm64-mmu.o +obj-y += ../board186.o +obj-y += ../lowlevel_init.o +obj-$(CONFIG_DISPLAY_CPUINFO) += ../sys_info.o diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h new file mode 100644 index 00000000000..aa7b9d038a7 --- /dev/null +++ b/include/configs/tegra186-common.h @@ -0,0 +1,71 @@ +/* + * Copyright 2013-2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _TEGRA186_COMMON_H_ +#define _TEGRA186_COMMON_H_ + +#include "tegra-common.h" + +/* Cortex-A57 uses a cache line size of 64 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_STACKBASE 0x82800000 /* 40MB */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ + +#define CONFIG_SYS_TEXT_BASE 0x80080000 + +/* Generic Interrupt Controller */ +#define CONFIG_GICV2 + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define CONFIG_LOADADDR 0x80080000 +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdt_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x82100000\0" + +/* Defines for SPL */ +#define CONFIG_SPL_TEXT_BASE 0x80108000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 +#define CONFIG_SPL_STACK 0x800ffffc + +#endif -- cgit v1.3.1 From 10a03382f0f8e774e58df7143e1a8ea52903ae1f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 12 May 2016 13:32:56 -0600 Subject: ARM: tegra: add p2771-0000 board support P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO expansion headers. Currently, due to U-Boot's level of support for Tegra186, the only features supported by U-Boot are the console UART and the on-board eMMC. Additional features will be added over time. U-Boot has so far been tested by replacing the kernel image on the device with a U-Boot binary. It is anticipated that U-Boot will eventually replace the CCPLEX bootloader binary, as on previous chips. This hasn't yet been tested. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra186-p2771-0000.dts | 25 +++++++++++++++++++++++++ arch/arm/mach-tegra/tegra186/Kconfig | 10 ++++++++++ board/nvidia/p2771-0000/Kconfig | 16 ++++++++++++++++ board/nvidia/p2771-0000/MAINTAINERS | 6 ++++++ board/nvidia/p2771-0000/Makefile | 5 +++++ board/nvidia/p2771-0000/p2771-0000.c | 7 +++++++ configs/p2771-0000_defconfig | 31 +++++++++++++++++++++++++++++++ include/configs/p2771-0000.h | 33 +++++++++++++++++++++++++++++++++ 9 files changed, 134 insertions(+) create mode 100644 arch/arm/dts/tegra186-p2771-0000.dts create mode 100644 board/nvidia/p2771-0000/Kconfig create mode 100644 board/nvidia/p2771-0000/MAINTAINERS create mode 100644 board/nvidia/p2771-0000/Makefile create mode 100644 board/nvidia/p2771-0000/p2771-0000.c create mode 100644 configs/p2771-0000_defconfig create mode 100644 include/configs/p2771-0000.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 92c7545bb5a..818d24eb69b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -47,6 +47,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ tegra124-venice2.dtb \ + tegra186-p2771-0000.dtb \ tegra210-e2220-1170.dtb \ tegra210-p2371-0000.dtb \ tegra210-p2371-2180.dtb \ diff --git a/arch/arm/dts/tegra186-p2771-0000.dts b/arch/arm/dts/tegra186-p2771-0000.dts new file mode 100644 index 00000000000..5f29ee45019 --- /dev/null +++ b/arch/arm/dts/tegra186-p2771-0000.dts @@ -0,0 +1,25 @@ +/dts-v1/; + +#include "tegra186.dtsi" + +/ { + model = "NVIDIA P2771-0000"; + compatible = "nvidia,p2771-0000", "nvidia,tegra186"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + sdhci0 = "/sdhci@3460000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0x60000000>; + }; + + sdhci@3460000 { + status = "okay"; + bus-width = <8>; + }; +}; diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig index 124d8e58359..97cf23f31f8 100644 --- a/arch/arm/mach-tegra/tegra186/Kconfig +++ b/arch/arm/mach-tegra/tegra186/Kconfig @@ -7,9 +7,19 @@ if TEGRA186 choice prompt "Tegra186 board select" +config TARGET_P2771_0000 + bool "NVIDIA Tegra186 P2771-0000 board" + help + P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The + combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB + micro-B port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO + expansion headers. + endchoice config SYS_SOC default "tegra186" +source "board/nvidia/p2771-0000/Kconfig" + endif diff --git a/board/nvidia/p2771-0000/Kconfig b/board/nvidia/p2771-0000/Kconfig new file mode 100644 index 00000000000..1b1116f0209 --- /dev/null +++ b/board/nvidia/p2771-0000/Kconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +if TARGET_P2771_0000 + +config SYS_BOARD + default "p2771-0000" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "p2771-0000" + +endif diff --git a/board/nvidia/p2771-0000/MAINTAINERS b/board/nvidia/p2771-0000/MAINTAINERS new file mode 100644 index 00000000000..4fc4ebd5e07 --- /dev/null +++ b/board/nvidia/p2771-0000/MAINTAINERS @@ -0,0 +1,6 @@ +P2771-0000 BOARD +M: Stephen Warren +S: Maintained +F: board/nvidia/p2771-0000/ +F: include/configs/p2771-0000.h +F: configs/p2771-0000_defconfig diff --git a/board/nvidia/p2771-0000/Makefile b/board/nvidia/p2771-0000/Makefile new file mode 100644 index 00000000000..b28a47d9078 --- /dev/null +++ b/board/nvidia/p2771-0000/Makefile @@ -0,0 +1,5 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +obj-y += p2771-0000.o diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c new file mode 100644 index 00000000000..4ba8ebc0dce --- /dev/null +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include diff --git a/configs/p2771-0000_defconfig b/configs/p2771-0000_defconfig new file mode 100644 index 00000000000..9f2c418f9fe --- /dev/null +++ b/configs/p2771-0000_defconfig @@ -0,0 +1,31 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA186=y +CONFIG_TARGET_P2771_0000=y +CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Tegra186 (P2771-0000) # " +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h new file mode 100644 index 00000000000..257283f3b93 --- /dev/null +++ b/include/configs/p2771-0000.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2013-2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _P2771_0000_H +#define _P2771_0000_H + +#include + +#include "tegra186-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +#include "tegra-common-post.h" + +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 + +#endif -- cgit v1.3.1 From 569a191a864cee66e3d0763179e8688499de0377 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 Dec 2015 18:09:52 +0100 Subject: arm: socfpga: Add samtec VIN|ING board Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See --- V2: Update the defconfig as per Tom's request --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 113 +++++ arch/arm/mach-socfpga/Kconfig | 7 + board/samtec/vining_fpga/MAINTAINERS | 5 + board/samtec/vining_fpga/Makefile | 9 + board/samtec/vining_fpga/qts/iocsr_config.h | 660 ++++++++++++++++++++++++++ board/samtec/vining_fpga/qts/pinmux_config.h | 219 +++++++++ board/samtec/vining_fpga/qts/pll_config.h | 91 ++++ board/samtec/vining_fpga/qts/sdram_config.h | 341 +++++++++++++ board/samtec/vining_fpga/socfpga.c | 100 ++++ configs/socfpga_vining_fpga_defconfig | 55 +++ include/configs/socfpga_vining_fpga.h | 231 +++++++++ 12 files changed, 1833 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/socfpga_cyclone5_vining_fpga.dts create mode 100644 board/samtec/vining_fpga/MAINTAINERS create mode 100644 board/samtec/vining_fpga/Makefile create mode 100644 board/samtec/vining_fpga/qts/iocsr_config.h create mode 100644 board/samtec/vining_fpga/qts/pinmux_config.h create mode 100644 board/samtec/vining_fpga/qts/pll_config.h create mode 100644 board/samtec/vining_fpga/qts/sdram_config.h create mode 100644 board/samtec/vining_fpga/socfpga.c create mode 100644 configs/socfpga_vining_fpga_defconfig create mode 100644 include/configs/socfpga_vining_fpga.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 92c7545bb5a..e76f56b22eb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -107,7 +107,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_de0_nano_soc.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ - socfpga_cyclone5_sr1500.dtb + socfpga_cyclone5_sr1500.dtb \ + socfpga_cyclone5_vining_fpga.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts new file mode 100644 index 00000000000..f168e4ff996 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2015 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "samtec VIN|ING FPGA"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + ethernet0 = &gmac1; + udc0 = &usb0; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rtc: rtc@68 { + compatible = "stm,m41t82"; + reg = <0x68>; + }; +}; + +&qspi { + status = "okay"; + u-boot,dm-pre-reloc; + + flash0: n25q128@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128", "spi-flash"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; + + flash1: n25q00@1 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00", "spi-flash"; + reg = <1>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index dea4ce569f7..1484607754b 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -35,6 +35,10 @@ config TARGET_SOCFPGA_EBV_SOCRATES bool "EBV SoCrates (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_SAMTEC_VINING_FPGA + bool "samtec VIN|ING FPGA (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + config TARGET_SOCFPGA_TERASIC_DE0_NANO bool "Terasic DE0-Nano-Atlas (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -53,12 +57,14 @@ config SYS_BOARD default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 + default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "denx" if TARGET_SOCFPGA_DENX_MCVEVK default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES + default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT @@ -73,5 +79,6 @@ config SYS_CONFIG_NAME default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 + default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA endif diff --git a/board/samtec/vining_fpga/MAINTAINERS b/board/samtec/vining_fpga/MAINTAINERS new file mode 100644 index 00000000000..c2002fe3cef --- /dev/null +++ b/board/samtec/vining_fpga/MAINTAINERS @@ -0,0 +1,5 @@ +VINING FPGA BOARD +M: Marek Vasut +S: Maintained +F: include/configs/socfpga_vining_fpga.h +F: configs/socfpga_vining_fpga_defconfig diff --git a/board/samtec/vining_fpga/Makefile b/board/samtec/vining_fpga/Makefile new file mode 100644 index 00000000000..86f9b78cad7 --- /dev/null +++ b/board/samtec/vining_fpga/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010, Thomas Chou +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga.o diff --git a/board/samtec/vining_fpga/qts/iocsr_config.h b/board/samtec/vining_fpga/qts/iocsr_config.h new file mode 100644 index 00000000000..fe5cb61a62d --- /dev/null +++ b/board/samtec/vining_fpga/qts/iocsr_config.h @@ -0,0 +1,660 @@ +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00000000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00000000, + 0x300C0000, + 0x000000C0, + 0x00000000, + 0x00000000, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00601806, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x300C0300, + 0x300C0000, + 0x0FF00000, + 0x00000000, + 0x000300C0, + 0x00008000, + 0x18060180, + 0x18060000, + 0x00000000, + 0x00000000, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x00000030, + 0x00000000, + 0x0300C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, + 0x0000C030, + 0x00000000, + 0x03000000, + 0x0000000C, + 0x00C0300C, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680A28, + 0x41034051, + 0x12481A00, + 0x80A280D0, + 0x34051406, + 0x01A02490, + 0x080D0000, + 0x51406802, + 0x02490340, + 0xD000001A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680208, + 0x49034051, + 0x12481A02, + 0x80A280D0, + 0x34030C06, + 0x01A00040, + 0x280D0002, + 0x5140680A, + 0x02490340, + 0xD012481A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0x8A28A3D5, + 0xF6D1451E, + 0x034AD348, + 0x821A0000, + 0x0000D000, + 0x05140680, + 0xD569A47A, + 0x1E8A28A3, + 0x48F6D145, + 0x00035292, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0x8A28A3D5, + 0xF4D1451E, + 0x034AD348, + 0x821A0186, + 0x0000D000, + 0x00000680, + 0xD569A47A, + 0x1EF228A3, + 0x48F4D145, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x0C864000, + 0x59647A03, + 0xCB2CA3DD, + 0xF6D9651E, + 0x034AD348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDD59647A, + 0x1E8A28A3, + 0x48F6D965, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F16080, + 0x1A041404, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0xF228A3D5, + 0xF4D1451E, + 0x03529248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1E8A28A3, + 0x48F6D145, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/qts/pinmux_config.h b/board/samtec/vining_fpga/qts/pinmux_config.h new file mode 100644 index 00000000000..968036587d6 --- /dev/null +++ b/board/samtec/vining_fpga/qts/pinmux_config.h @@ -0,0 +1,219 @@ +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 2, /* FLASHIO0 */ + 2, /* FLASHIO1 */ + 2, /* FLASHIO2 */ + 2, /* FLASHIO3 */ + 2, /* FLASHIO4 */ + 2, /* FLASHIO5 */ + 2, /* FLASHIO6 */ + 2, /* FLASHIO7 */ + 2, /* FLASHIO8 */ + 2, /* FLASHIO9 */ + 2, /* FLASHIO10 */ + 2, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 3, /* GENERALIO9 */ + 3, /* GENERALIO10 */ + 3, /* GENERALIO11 */ + 3, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 2, /* GENERALIO15 */ + 2, /* GENERALIO16 */ + 0, /* GENERALIO17 */ + 0, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 2, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 1, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 1, /* SPIS1USEFPGA */ + 1, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/qts/pll_config.h b/board/samtec/vining_fpga/qts/pll_config.h new file mode 100644 index 00000000000..c8a6e961fdf --- /dev/null +++ b/board/samtec/vining_fpga/qts/pll_config.h @@ -0,0 +1,91 @@ +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 488281 +#define CONFIG_HPS_CLK_SDMMC_HZ 1953125 +#define CONFIG_HPS_CLK_QSPI_HZ 400000000 +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 +#define CONFIG_HPS_CLK_CAN0_HZ 12500000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/qts/sdram_config.h b/board/samtec/vining_fpga/qts/sdram_config.h new file mode 100644 index 00000000000..74cb405601d --- /dev/null +++ b/board/samtec/vining_fpga/qts/sdram_config.h @@ -0,0 +1,341 @@ +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 7 +#define CALIB_VFIFO_OFFSET 5 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 99 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 99 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080421, + 0x10080520, + 0x10090046, + 0x100a0088, + 0x100b0000, + 0x10380400, + 0x10080441, + 0x100804c0, + 0x100a0026, + 0x10090110, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/socfpga.c b/board/samtec/vining_fpga/socfpga.c new file mode 100644 index 00000000000..f3a92b5e645 --- /dev/null +++ b/board/samtec/vining_fpga/socfpga.c @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ +int board_late_init(void) +{ + const unsigned int phy_nrst_gpio = 0; + const unsigned int usb_nrst_gpio = 35; + int ret; + + status_led_set(1, STATUS_LED_ON); + status_led_set(2, STATUS_LED_ON); + + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio"); + if (!ret) + gpio_direction_output(phy_nrst_gpio, 1); + else + printf("Cannot remove PHY from reset!\n"); + + ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio"); + if (!ret) + gpio_direction_output(usb_nrst_gpio, 1); + else + printf("Cannot remove USB from reset!\n"); + + mdelay(50); + + return 0; +} + +#ifndef CONFIG_SPL_BUILD +int misc_init_r(void) +{ + uchar data[128]; + char str[32]; + u32 serial; + int ret; + + /* EEPROM is at bus 0. */ + ret = i2c_set_bus_num(0); + if (ret) { + puts("Cannot select EEPROM I2C bus.\n"); + return 0; + } + + /* EEPROM is at address 0x50. */ + ret = eeprom_read(0x50, 0, data, sizeof(data)); + if (ret) { + puts("Cannot read I2C EEPROM.\n"); + return 0; + } + + /* Check EEPROM signature. */ + if (!(data[0] == 0xa5 && data[1] == 0x5a)) { + puts("Invalid I2C EEPROM signature.\n"); + setenv("unit_serial", "invalid"); + setenv("unit_ident", "VINing-xxxx-STD"); + setenv("hostname", "vining-invalid"); + return 0; + } + + /* If 'unit_serial' is already set, do nothing. */ + if (!getenv("unit_serial")) { + /* This field is Big Endian ! */ + serial = (data[0x54] << 24) | (data[0x55] << 16) | + (data[0x56] << 8) | (data[0x57] << 0); + memset(str, 0, sizeof(str)); + sprintf(str, "%07i", serial); + setenv("unit_serial", str); + } + + if (!getenv("unit_ident")) { + memset(str, 0, sizeof(str)); + memcpy(str, &data[0x2e], 18); + setenv("unit_ident", str); + } + + /* Set ethernet address from EEPROM. */ + if (!getenv("ethaddr") && is_valid_ethaddr(&data[0x62])) + eth_setenv_enetaddr("ethaddr", &data[0x62]); + + return 0; +} +#endif diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig new file mode 100644 index 00000000000..f8bb9a640bc --- /dev/null +++ b/configs/socfpga_vining_fpga_defconfig @@ -0,0 +1,55 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_DM=y +CONFIG_DM_GPIO=y +CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y +CONFIG_SPL_STACK_R_ADDR=0x00800000 +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga" +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_FIT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="samtec" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h new file mode 100644 index 00000000000..1ccde1a76fe --- /dev/null +++ b/include/configs/socfpga_vining_fpga.h @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2015 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_SAMTEC_VINING_FPGA_H__ +#define __CONFIG_SAMTEC_VINING_FPGA_H__ + +#include + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_LED + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */ + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTFILE "openwrt-socfpga-socfpga_cyclone5_vining_fpga-fit-uImage.itb" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTCOMMAND "run selboot" +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* I2C EEPROM */ +#ifdef CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 0 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 +#endif + +/* + * Status LEDs: + * 0 ... Top Green + * 1 ... Top Red + * 2 ... Bottom Green + * 3 ... Bottom Red + */ +#define CONFIG_STATUS_LED +#define CONFIG_GPIO_LED +#define CONFIG_BOARD_SPECIFIC_LED +#define STATUS_LED_BIT 48 +#define STATUS_LED_STATE STATUS_LED_OFF +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BIT1 53 +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BIT2 54 +#define STATUS_LED_STATE2 STATUS_LED_OFF +#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BIT3 65 +#define STATUS_LED_STATE3 STATUS_LED_OFF +#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2) + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_BOOTP_SEND_HOSTNAME +/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#endif + +/* Extra Environment */ +#define CONFIG_HOSTNAME socfpga_vining_fpga + +/* + * Active LOW GPIO buttons: + * A: GPIO 77 ... the button between USB B and ethernet + * B: GPIO 78 ... the button between USB A ports + * + * The logic: + * if button B is not pressed, boot normal Linux system immediatelly + * if button B is pressed, wait $bootdelay and boot recovery system + */ +#define CONFIG_PREBOOT \ + "setenv hostname vining-${unit_serial} ; " \ + "setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; " \ + "if gpio input 78 ; then " \ + "setenv bootdelay 10 ; " \ + "setenv boottype rcvr ; " \ + "else " \ + "setenv bootdelay 5 ; " \ + "setenv boottype norm ; " \ + "fi" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "consdev=ttyS0\0" \ + "baudrate=115200\0" \ + "bootscript=boot.scr\0" \ + "ubimtdnr=5\0" \ + "ubimtd=rootfs\0" \ + "ubipart=ubi0:rootfs\0" \ + "ubisfcs=1\0" /* Default is flash at CS#1 */ \ + "netdev=eth0\0" \ + "hostname=vining_fpga\0" \ + "kernel_addr_r=0x10000000\0" \ + "mtdparts_0=ff705000.spi.0:" \ + "1m(u-boot)," \ + "64k(env1)," \ + "64k(env2)," \ + "256k(samtec1)," \ + "256k(samtec2)," \ + "-(rcvrfs)\0" /* Recovery */ \ + "mtdparts_1=ff705000.spi.1:" \ + "32m(rootfs)," \ + "-(userfs)\0" \ + "update_filename=u-boot-with-spl-dtb.sfp\0" \ + "update_qspi_offset=0x0\0" \ + "update_qspi=" /* Update the QSPI firmware */ \ + "if sf probe ; then " \ + "if tftp ${update_filename} ; then " \ + "sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \ + "fi ; " \ + "fi\0" \ + "fpga_filename=output_file.rbf\0" \ + "load_fpga=" /* Load FPGA bitstream */ \ + "if tftp ${fpga_filename} ; then " \ + "fpga load 0 $loadaddr $filesize ; " \ + "bridge enable ; " \ + "fi\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "addmtd=" \ + "setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; " \ + "setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \ + "addargs=run addcons addmtd addmisc\0" \ + "ubiload=" \ + "ubi part ${ubimtd} ; ubifsmount ${ubipart} ; " \ + "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ + "netload=" \ + "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ + "miscargs=nohlt panic=1\0" \ + "ubiargs=" \ + "setenv bootargs ubi.mtd=${ubimtdnr} " \ + "root=${ubipart} rootfstype=ubifs\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ + "ubi_sfsel=" \ + "if test \"${boottype}\" = \"rcvr\" ; then " \ + "setenv ubisfcs 0 ; " \ + "setenv ubimtd rcvrfs ; " \ + "setenv ubimtdnr 5 ; " \ + "setenv mtdparts mtdparts=${mtdparts_0} ; " \ + "setenv mtdids nor0=ff705000.spi.0 ; " \ + "setenv ubipart ubi0:rootfs ; " \ + "else " \ + "setenv ubisfcs 1 ; " \ + "setenv ubimtd rootfs ; " \ + "setenv ubimtdnr 6 ; " \ + "setenv mtdparts mtdparts=${mtdparts_1} ; " \ + "setenv mtdids nor0=ff705000.spi.1 ; " \ + "setenv ubipart ubi0:rootfs ; " \ + "fi ; " \ + "sf probe 0:${ubisfcs}\0" \ + "ubi_ubi=" \ + "run ubi_sfsel ubiload ubiargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "ubi_nfs=" \ + "run ubiload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_ubi=" \ + "run netload ubiargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_nfs=" \ + "run netload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "selboot=" /* Select from where to boot. */ \ + "if test \"${bootmode}\" = \"qspi\" ; then " \ + "led all off ; " \ + "if test \"${boottype}\" = \"rcvr\" ; then " \ + "echo \"Booting recovery system\" ; " \ + "led 3 on ; " /* Bottom RED */ \ + "fi ; " \ + "led 1 on ; " /* Top RED */ \ + "run ubi_ubi ; " \ + "else echo \"Unsupported boot mode: \"${bootmode} ; " \ + "fi\0" \ + +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_MTD_UBI_FASTMAP +#define CONFIG_RBTREE +#define CONFIG_LZO +#define MTDPARTS_DEFAULT \ + "mtdparts=ff705000.spi.0:" \ + "1m(u-boot)," \ + "64k(env1)," \ + "64k(env2)," \ + "256k(samtec1)," \ + "256k(samtec2)," \ + "-(rcvrfs);" /* Recovery */ \ + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_OFFSET_REDUND \ + (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) + +#define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_LATE_INIT + +/* Enable DFU to SF and RAM */ +#define CONFIG_DFU_RAM +#define CONFIG_DFU_SF + +/* Support changing the prompt string */ +#define CONFIG_CMDLINE_PS_SUPPORT + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_SAMTEC_VINING_FPGA_H__ */ -- cgit v1.3.1 From 5bb4050df36f016de106c0ab129319795acabc06 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 30 May 2016 17:09:48 +0200 Subject: arm: socfpga: Enable tiny printf and simple malloc in SPL Enable both features to reduce the SPL size by 6 kiB. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Pavel Machek Cc: Stefan Roese --- configs/socfpga_arria5_defconfig | 2 ++ configs/socfpga_cyclone5_defconfig | 2 ++ configs/socfpga_de0_nano_soc_defconfig | 2 ++ configs/socfpga_mcvevk_defconfig | 2 ++ configs/socfpga_sockit_defconfig | 2 ++ configs/socfpga_socrates_defconfig | 2 ++ configs/socfpga_sr1500_defconfig | 2 ++ configs/socfpga_vining_fpga_defconfig | 2 ++ include/configs/socfpga_common.h | 3 --- 9 files changed, 16 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index a662e72cc7a..ec40ec72dca 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index b2933f778a0..8e5c527ac2f 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index f197b6d2b00..034a2153610 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 6624f9e07d0..133a6eba2af 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index c6414f8be53..8b1bcfcee61 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index b47a5602b80..56284a1c0a7 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index aab44989736..d66f7c605ed 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_SR1500=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index f8bb9a640bc..6ce4defca43 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f6577668a1d..aee4012c306 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -324,9 +324,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_RAM_DEVICE #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SPL_MAX_SIZE (64 * 1024) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT -- cgit v1.3.1 From 77cd5368cee8b6a5684877e1bf4d544bf271ef08 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 1 Jun 2016 13:24:58 +0200 Subject: arm: socfpga: Add missing ',' in CONFIG_BOOTARGS Somehow the sr1500 is missing this comma in the CONFIG_BOOTARGS definition. This patch adds it to. Signed-off-by: Stefan Roese Reported-by: Pavel Machek Cc: Pavel Machek Cc: Marek Vasut --- include/configs/socfpga_sr1500.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index efa9e428cee..c097f47edd4 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -22,7 +22,7 @@ /* Booting Linux */ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- cgit v1.3.1 From d31e9c575f24f4b7f5f382ccae70d7a86bbc379d Mon Sep 17 00:00:00 2001 From: Sylvain Lesne Date: Wed, 1 Jun 2016 11:14:54 +0200 Subject: arm: socfpga: improve raw MMC SPL boot Before this patch, when booting from MMC (no filesystem), the SPL loaded U-Boot from a fixed offset. It will now load U-Boot from an offset of 256kB (which is 4 times the padded SPL image) in the third partition. This behaviour is similar to what the vendor SPL (based on U-Boot 2013.01) does, and allows to directly 'dd' the u-boot-with-spl.sfp file to the A2 partition. Signed-off-by: Sylvain Lesne --- include/configs/socfpga_common.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index aee4012c306..1f8b7b3b80e 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -346,9 +346,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" #define CONFIG_SPL_LIBDISK_SUPPORT #else -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* offset 512 sect (256k) */ +#define CONFIG_SPL_LIBDISK_SUPPORT #endif #endif -- cgit v1.3.1 From 35016e39fe545420260ec487859aaaeb80bf3be0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 1 Jun 2016 00:00:02 +0200 Subject: mips: wdr4300: Move the CONFIG_USE_PRIVATE_LIBGCC to Kconfig This fixes the last remaining libgcc warning, where the symbol was defined twice. Signed-off-by: Marek Vasut Cc: Simon Glass Cc: Tom Rini Reviewed-by: Tom Rini --- configs/tplink_wdr4300_defconfig | 1 + include/configs/tplink_wdr4300.h | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig index b1af2f6f35f..3eec4c2db94 100644 --- a/configs/tplink_wdr4300_defconfig +++ b/configs/tplink_wdr4300_defconfig @@ -1,6 +1,7 @@ CONFIG_MIPS=y CONFIG_ARCH_ATH79=y CONFIG_BOARD_TPLINK_WDR4300=y +CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SYS_NS16550=y CONFIG_DM_SERIAL=y diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 6273711b1d0..abe1da2bd68 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -78,8 +78,6 @@ #define CONFIG_SYS_MEMTEST_END 0x83f00000 #define CONFIG_CMD_MEMTEST -#define CONFIG_USE_PRIVATE_LIBGCC - #define CONFIG_CMD_MII #define CONFIG_PHY_GIGE -- cgit v1.3.1 From b7f2bbfff6dcc2d5989bb1d20500c431f7927daf Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 3 Jun 2016 18:41:31 +0530 Subject: armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson Signed-off-by: Makarand Pawagi Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 43 ++++++ .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 11 ++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 + arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c | 74 ++++++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 + arch/arm/include/asm/arch-fsl-layerscape/config.h | 29 ++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 1 + .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 + .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 + .../include/asm/arch-fsl-layerscape/ns_access.h | 10 ++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + include/fsl_mmdc.h | 160 +++++++++++++++++++++ include/linux/usb/xhci-fsl.h | 6 +- 14 files changed, 347 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c create mode 100644 include/fsl_mmdc.h (limited to 'include') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 5f86ef90d24..eb2cbc3f7e2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -28,3 +28,7 @@ endif ifneq ($(CONFIG_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o endif + +ifneq ($(CONFIG_LS1012A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o +endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index a4130cee50c..8eee016f11c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -2,6 +2,7 @@ SoC overview 1. LS1043A 2. LS2080A + 3. LS1012A LS1043A --------- @@ -84,3 +85,45 @@ The LS2080A SoC includes the following function and features: - QorIQ platform's trust architecture 3.0 - Service processor (SP) provides pre-boot initialization and secure-boot capabilities + +LS1012A +-------- +The LS1012A features an advanced 64-bit ARM v8 Cortex- +A53 processor, with 32 KB of parity protected L1-I cache, +32 KB of ECC protected L1-D cache, as well as 256 KB of +ECC protected L2 cache. + +The LS1012A SoC includes the following function and features: + - One 64-bit ARM v8 Cortex-A53 core with the following capabilities: + - ARM v8 cryptography extensions + - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports + 16-/8-bit operation (no ECC support) + - ARM core-link CCI-400 cache coherent interconnect + - Packet Forwarding Engine (PFE) + - Cryptography acceleration (SEC) + - Ethernet interfaces supported by PFE: + - One Configurable x3 SerDes: + Two Serdes PLLs supported for usage by any SerDes data lane + Support for up to 6 GBaud operation + - High-speed peripheral interfaces: + - One PCI Express Gen2 controller, supporting x1 operation + - One serial ATA (SATA Gen 3.0) controller + - One USB 3.0/2.0 controller with integrated PHY + - One USB 2.0 controller with ULPI interface. . + - Additional peripheral interfaces: + - One quad serial peripheral interface (QuadSPI) controller + - One serial peripheral interface (SPI) controller + - Two enhanced secure digital host controllers + - Two I2C controllers + - One 16550 compliant DUART (two UART interfaces) + - Two general purpose IOs (GPIO) + - Two FlexTimers + - Five synchronous audio interfaces (SAI) + - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading + - Single-source clocking solution enabling generation of core, platform, + DDR, SerDes, and USB clocks from a single external crystal and internal + crystaloscillator + - Thermal monitor unit (TMU) with +/- 3C accuracy + - Two WatchDog timers + - ARM generic timer + - QorIQ platform's trust architecture 2.1 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 4fc31862278..3a77b21d0ab 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -59,12 +59,18 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_ddrbus = sysclk; #endif +#ifdef CONFIG_LS1012A + sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; +#else sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK; +#endif for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff; @@ -83,6 +89,11 @@ void get_sys_info(struct sys_info *sys_info) freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } +#ifdef CONFIG_LS1012A + sys_info->freq_systembus = sys_info->freq_ddrbus / 2; + sys_info->freq_ddrbus *= 2; +#endif + #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index d743ffe6b55..5af6b73bc9e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -183,6 +183,7 @@ ENTRY(lowlevel_init) ret ENDPROC(lowlevel_init) +#ifdef CONFIG_FSL_LSCH3 hnf_pstate_poll: /* x0 has the desired status, return 0 for success, 1 for timeout * clobber x1, x2, x3, x4, x6, x7 @@ -260,6 +261,7 @@ ENTRY(__asm_flush_l3_cache) mov lr, x29 ret ENDPROC(__asm_flush_l3_cache) +#endif #ifdef CONFIG_MP /* Keep literals not used by the secondary boot code outside it */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c new file mode 100644 index 00000000000..ff0903cebc9 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c @@ -0,0 +1,74 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + {0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} }, + {0x0008, {NONE, NONE, NONE, SATA1} }, + {0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} }, + {0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} }, + {0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} }, + {0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} }, + {0x9508, {TX_CLK, PCIE1, NONE, SATA1} }, + {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} }, + {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 0ae61d6d3ab..dd633f36905 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -12,8 +12,10 @@ #include #include #include +#ifdef CONFIG_SYS_FSL_DDR #include #include +#endif #ifdef CONFIG_CHAIN_OF_TRUST #include #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index fbdaa52c329..44fe0c00953 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -14,8 +14,11 @@ #else #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ #endif + +#ifndef CONFIG_LS1012A #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#endif /* * Reserve secure memory @@ -200,6 +203,32 @@ #define CONFIG_SYS_FSL_ERRATUM_A009942 #define CONFIG_SYS_FSL_ERRATUM_A009660 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 +#elif defined(CONFIG_LS1012A) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 +#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ + +#define GICD_BASE 0x01401000 +#define GICC_BASE 0x01402000 + +#define CONFIG_SYS_FSL_CCSR_GUR_BE +#define CONFIG_SYS_FSL_CCSR_SCFG_BE +#define CONFIG_SYS_FSL_ESDHC_BE +#define CONFIG_SYS_FSL_WDOG_BE +#define CONFIG_SYS_FSL_DSPI_BE +#define CONFIG_SYS_FSL_QSPI_BE +#define CONFIG_SYS_FSL_PEX_LUT_BE + +#define SRDS_MAX_LANES 4 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" +#define CONFIG_SYS_FSL_SEC_BE #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 702b9faabd9..1cebe2fbb01 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1043, LS1043, 4), CPU_TYPE_ENTRY(LS1023, LS1023, 2), CPU_TYPE_ENTRY(LS2040, LS2040, 4), + CPU_TYPE_ENTRY(LS1012, LS1012, 1), }; #ifndef CONFIG_SYS_DCACHE_OFF diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index c4fb7c9a475..487cba80803 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -134,6 +134,7 @@ enum srds_prtcl { SGMII_2500_FM2_DTSEC6, SGMII_2500_FM2_DTSEC9, SGMII_2500_FM2_DTSEC10, + TX_CLK, SERDES_PRCTL_COUNT }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 57b99d4084e..e98e055d9f1 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -60,7 +60,11 @@ #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL /* LUT registers */ +#ifdef CONFIG_LS1012A +#define PCIE_LUT_BASE 0xC0000 +#else #define PCIE_LUT_BASE 0x10000 +#endif #define PCIE_LUT_LCTRL0 0x7F8 #define PCIE_LUT_DBG 0x7FC diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h index a3ccdb03c7f..db76066c807 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -69,7 +69,12 @@ enum csu_cslx_ind { CSU_CSLX_IIC4 = 77, CSU_CSLX_WDT4, CSU_CSLX_WDT3, + CSU_CSLX_ESDHC2 = 80, CSU_CSLX_WDT5 = 81, + CSU_CSLX_SAI2, + CSU_CSLX_SAI1, + CSU_CSLX_SAI4, + CSU_CSLX_SAI3, CSU_CSLX_FTM2 = 86, CSU_CSLX_FTM1, CSU_CSLX_FTM4, @@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = { {CSU_CSLX_IIC4, CSU_ALL_RW}, {CSU_CSLX_WDT4, CSU_ALL_RW}, {CSU_CSLX_WDT3, CSU_ALL_RW}, + {CSU_CSLX_ESDHC2, CSU_ALL_RW}, {CSU_CSLX_WDT5, CSU_ALL_RW}, + {CSU_CSLX_SAI2, CSU_ALL_RW}, + {CSU_CSLX_SAI1, CSU_ALL_RW}, + {CSU_CSLX_SAI4, CSU_ALL_RW}, + {CSU_CSLX_SAI3, CSU_ALL_RW}, {CSU_CSLX_FTM2, CSU_ALL_RW}, {CSU_CSLX_FTM1, CSU_ALL_RW}, {CSU_CSLX_FTM4, CSU_ALL_RW}, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 831d81764ec..02ecc6257e1 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -41,6 +41,7 @@ struct cpu_type { { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} #define SVR_WO_E 0xFFFFFE +#define SVR_LS1012 0x870400 #define SVR_LS1043 0x879200 #define SVR_LS1023 0x879208 #define SVR_LS2045 0x870120 diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h new file mode 100644 index 00000000000..281a8198632 --- /dev/null +++ b/include/fsl_mmdc.h @@ -0,0 +1,160 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef FSL_MMDC_H +#define FSL_MMDC_H + +#define CONFIG_SYS_MMDC_CORE_ODT_TIMING 0x12554000 +#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0 0xbabf7954 +#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64 +#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db + +#define CONFIG_SYS_MMDC_CORE_MISC 0x00000680 +#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800 +#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000 +#define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a + +#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY 0x00bf1023 + +#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION 0x0000007f + +#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL 0xa1390003 + +#define FORCE_ZQ_AUTO_CALIBRATION (0x1 << 16) + +/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */ +#define WR_LVL_HW_EN 0x00000001 + +/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */ +#define MPR_COMPARE_EN 0x00000001 + +#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG 0x40404040 + +/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */ +#define AUTO_RD_DQS_GATING_CALIBRATION_EN 0x10000000 + +/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */ +#define AUTO_RD_CALIBRATION_EN 0x00000010 + +#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL 0x00030035 + +#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067 + +#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x103e8000 + +#define START_REFRESH 0x00000001 + +/* MMDC Core Special Command Register (MDSCR) */ +#define CMD_ADDR_MSB_MR_OP(x) (x << 24) + +#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16) + +#define DISABLE_CFG_REQ 0x0 +#define CONFIGURATION_REQ (0x1 << 15) +#define WL_EN (0x1 << 9) + +#define CMD_NORMAL (0x0 << 4) +#define CMD_PRECHARGE (0x1 << 4) +#define CMD_AUTO_REFRESH (0x2 << 4) +#define CMD_LOAD_MODE_REG (0x3 << 4) +#define CMD_ZQ_CALIBRATION (0x4 << 4) +#define CMD_PRECHARGE_BANK_OPEN (0x5 << 4) +#define CMD_MRR (0x6 << 4) + +#define CMD_BANK_ADDR_0 0x0 +#define CMD_BANK_ADDR_1 0x1 +#define CMD_BANK_ADDR_2 0x2 +#define CMD_BANK_ADDR_3 0x3 +#define CMD_BANK_ADDR_4 0x4 +#define CMD_BANK_ADDR_5 0x5 +#define CMD_BANK_ADDR_6 0x6 +#define CMD_BANK_ADDR_7 0x7 + +/* MMDC Registers */ +struct mmdc_p_regs { + u32 mdctl; + u32 mdpdc; + u32 mdotc; + u32 mdcfg0; + u32 mdcfg1; + u32 mdcfg2; + u32 mdmisc; + u32 mdscr; + u32 mdref; + u32 res1[2]; + u32 mdrwd; + u32 mdor; + u32 mdmrr; + u32 mdcfg3lp; + u32 mdmr4; + u32 mdasp; + u32 res2[239]; + u32 maarcr; + u32 mapsr; + u32 maexidr0; + u32 maexidr1; + u32 madpcr0; + u32 madpcr1; + u32 madpsr0; + u32 madpsr1; + u32 madpsr2; + u32 madpsr3; + u32 madpsr4; + u32 madpsr5; + u32 masbs0; + u32 masbs1; + u32 res3[2]; + u32 magenp; + u32 res4[239]; + u32 mpzqhwctrl; + u32 mpzqswctrl; + u32 mpwlgcr; + u32 mpwldectrl0; + u32 mpwldectrl1; + u32 mpwldlst; + u32 mpodtctrl; + u32 mprddqby0dl; + u32 mprddqby1dl; + u32 mprddqby2dl; + u32 mprddqby3dl; + u32 res5[4]; + u32 mpdgctrl0; + u32 mpdgctrl1; + u32 mpdgdlst0; + u32 mprddlctl; + u32 mprddlst; + u32 mpwrdlctl; + u32 mpwrdlst; + u32 mpsdctrl; + u32 mpzqlp2ctl; + u32 mprddlhwctl; + u32 mpwrdlhwctl; + u32 mprddlhwst0; + u32 mprddlhwst1; + u32 mpwrdlhwst0; + u32 mpwrdlhwst1; + u32 mpwlhwerr; + u32 mpdghwst0; + u32 mpdghwst1; + u32 mpdghwst2; + u32 mpdghwst3; + u32 mppdcmpr1; + u32 mppdcmpr2; + u32 mpswdar0; + u32 mpswdrdr0; + u32 mpswdrdr1; + u32 mpswdrdr2; + u32 mpswdrdr3; + u32 mpswdrdr4; + u32 mpswdrdr5; + u32 mpswdrdr6; + u32 mpswdrdr7; + u32 mpmur0; + u32 mpwrcadl; + u32 mpdccr; +}; + +#endif /* FSL_MMDC_H */ diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index c5e42e69fe2..253eddf1590 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -59,10 +59,14 @@ struct fsl_xhci { #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_LS1043A) +#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR +#elif defined(CONFIG_LS1012A) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 +#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 #endif #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ -- cgit v1.3.1 From 9d044fcb8c4558d7ec28089375d2de565bfd2619 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 3 Jun 2016 18:41:34 +0530 Subject: armv8: ls1012a: Add support of ls1012aqds board QorIQ LS1012A Development System (LS1012AQDS) is a high-performance development platform, with a complete debugging environment. The LS1012AQDS board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Calvin Johnson Signed-off-by: Pratiyush Mohan Srivastava Signed-off-by: Abhimanyu Saini Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/arm/Kconfig | 10 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/fsl-ls1012a-qds.dts | 14 ++ arch/arm/dts/fsl-ls1012a-qds.dtsi | 123 ++++++++++++++ arch/arm/dts/fsl-ls1012a.dtsi | 119 +++++++++++++ board/freescale/ls1012aqds/Kconfig | 15 ++ board/freescale/ls1012aqds/MAINTAINERS | 6 + board/freescale/ls1012aqds/Makefile | 7 + board/freescale/ls1012aqds/README | 59 +++++++ board/freescale/ls1012aqds/ls1012aqds.c | 234 ++++++++++++++++++++++++++ board/freescale/ls1012aqds/ls1012aqds_qixis.h | 35 ++++ configs/ls1012aqds_qspi_defconfig | 32 ++++ include/configs/ls1012a_common.h | 145 ++++++++++++++++ include/configs/ls1012aqds.h | 191 +++++++++++++++++++++ 14 files changed, 992 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dts create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dtsi create mode 100644 arch/arm/dts/fsl-ls1012a.dtsi create mode 100644 board/freescale/ls1012aqds/Kconfig create mode 100644 board/freescale/ls1012aqds/MAINTAINERS create mode 100644 board/freescale/ls1012aqds/Makefile create mode 100644 board/freescale/ls1012aqds/README create mode 100644 board/freescale/ls1012aqds/ls1012aqds.c create mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h create mode 100644 configs/ls1012aqds_qspi_defconfig create mode 100644 include/configs/ls1012a_common.h create mode 100644 include/configs/ls1012aqds.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7a77b6a0370..30fc32a853f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -696,6 +696,15 @@ config TARGET_HIKEY Support for HiKey 96boards platform. It features a HI6220 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM. +config TARGET_LS1012AQDS + bool "Support ls1012aqds" + select ARM64 + help + Support for Freescale LS1012AQDS platform. + The LS1012A Development System (QDS) is a high-performance + development platform that supports the QorIQ LS1012A + Layerscape Architecture processor. + config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -852,6 +861,7 @@ source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/ls1043ardb/Kconfig" +source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/mx23evk/Kconfig" source "board/freescale/mx25pdk/Kconfig" source "board/freescale/mx28evk/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 92c7545bb5a..47ec7a28ec5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -120,7 +120,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-rdb.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ - fsl-ls1043a-rdb.dtb + fsl-ls1043a-rdb.dtb \ + fsl-ls1012a-qds.dtb dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts new file mode 100644 index 00000000000..76db36ca39f --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-qds.dts @@ -0,0 +1,14 @@ +/* + * Copyright 2016 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1012a-qds.dtsi" + +/ { + chosen { + stdout-path = &duart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi new file mode 100644 index 00000000000..dde71346266 --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi @@ -0,0 +1,123 @@ +/* + * Copyright 2016 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "fsl-ls1012a.dtsi" + +/ { + model = "LS1012A QDS Board"; + aliases { + spi0 = &qspi; + spi1 = &dspi0; + }; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <1000000>; /* input clock */ + }; + + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3500000>; + reg = <1>; + }; + + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3500000>; + reg = <2>; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fl128s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "philips,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + /* IRQ10_B */ + interrupts = <0 150 0x4>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + eeprom@56 { + compatible = "at24,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "at24,24c512"; + reg = <0x57>; + }; + + adt7461a@4c { + compatible = "adt7461a"; + reg = <0x4c>; + }; + }; + }; +}; + +&duart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi new file mode 100644 index 00000000000..546a87a0a5b --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -0,0 +1,119 @@ +/* + * Copyright 2016 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton64.dtsi" + +/ { + compatible = "fsl,ls1012a"; + interrupt-parent = <&gic>; + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; + }; + + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + gic: interrupt-controller@1400000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0 0x1000>, /* GICD */ + <0x0 0x1402000 0 0x2000>, /* GICC */ + <0x0 0x1404000 0 0x2000>, /* GICH */ + <0x0 0x1406000 0 0x2000>; /* GICV */ + interrupts = <1 9 0xf08>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clockgen: clocking@1ee1000 { + compatible = "fsl,ls1012a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 64 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <6>; + big-endian; + status = "disabled"; + }; + + + i2c0: i2c@2180000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <0 56 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c1: i2c@2190000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = <0 57 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + duart0: serial@21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0500 0x0 0x100>; + interrupts = <0 54 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart1: serial@21c0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0600 0x0 0x100>; + interrupts = <0 54 0x4>; + clocks = <&clockgen 4 0>; + }; + + qspi: quadspi@1550000 { + compatible = "fsl,vf610-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1550000 0x0 0x10000>, + <0x0 0x40000000 0x0 0x4000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + num-cs = <2>; + big-endian; + status = "disabled"; + }; + + }; +}; diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig new file mode 100644 index 00000000000..1257ec8d06e --- /dev/null +++ b/board/freescale/ls1012aqds/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1012AQDS + +config SYS_BOARD + default "ls1012aqds" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012aqds" + +endif diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS new file mode 100644 index 00000000000..27c4affd30b --- /dev/null +++ b/board/freescale/ls1012aqds/MAINTAINERS @@ -0,0 +1,6 @@ +LS1012AQDS BOARD +M: Prabhakar Kushwaha +S: Maintained +F: board/freescale/ls1012aqds/ +F: include/configs/ls1012aqds.h +F: configs/ls1012aqds_qspi_defconfig diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile new file mode 100644 index 00000000000..0b813f97848 --- /dev/null +++ b/board/freescale/ls1012aqds/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012aqds.o diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README new file mode 100644 index 00000000000..dee4b302c14 --- /dev/null +++ b/board/freescale/ls1012aqds/README @@ -0,0 +1,59 @@ +Overview +-------- +QorIQ LS1012A Development System (LS1012AQDS) is a high-performance +development platform, with a complete debugging environment. +The LS1012AQDS board supports the QorIQ LS1012A processor and is +optimized to support the high-bandwidth DDR3L memory and +a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A +SoC overview. + +LS1012AQDS board Overview +----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - SATA 3.0 + - DDR Controller + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s + - QSPI Controller + - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select + signals to QSPI NOR flash memory (2 virtual banks) and the QSPI + emulator + - USB 3.0 + - One USB 3.0 controller with integrated PHY + - One high-speed USB 3.0 port + - USB 2.0 + - One USB 2.0 controller with ULPI interface + - Two enhanced secure digital host controllers: + - SDHC1 controller can be connected to onboard SDHC connector + - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices + - 2 I2C controllers + - One SATA onboard connectors + - UART + - 5 SAI + - One SAI port with audio codec SGTL5000: + • Provides MIC bias + • Provides headphone and line output + - One SAI port terminated at 2x6 header + - Three SAI Tx/Rx ports terminated at 2x3 headers + - ARM JTAG support + +Booting Options +--------------- +a) QSPI Flash Emu Boot +b) QSPI Flash 1 +c) QSPI Flash 2 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c new file mode 100644 index 00000000000..71eea82a035 --- /dev/null +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -0,0 +1,234 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "ls1012aqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) +{ + int timeout = 1000; + + out_be32(ptr, value); + + while (in_be32(ptr) & bits) { + udelay(100); + timeout--; + } + if (timeout <= 0) + puts("Error: wait for clear timeout.\n"); +} + +int checkboard(void) +{ + char buf[64]; + u8 sw; + + sw = QIXIS_READ(arch); + printf("Board Arch: V%d, ", sw >> 4); + printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); + + sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); + + if (sw & QIXIS_LBMAP_ALTBANK) + printf("flash: 2\n"); + else + printf("flash: 1\n"); + + printf("FPGA: v%d (%s), build %d", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + return 0; +} + +void mmdc_init(void) +{ + struct mmdc_p_regs *mmdc = + (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; + + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + /* configure timing parms */ + out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); + out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); + out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); + out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); + + /* other parms */ + out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); + out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); + out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); + out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); + + /* out of reset delays */ + out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); + + /* physical parms */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); + out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); + + /* Enable MMDC */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); + + /* dram init sequence: update MRs */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | + CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); + + /* dram init sequence: ZQCL */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, + CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, + FORCE_ZQ_AUTO_CALIBRATION); + + /* Calibrations now: wr lvl */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | + CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); + set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); + + mdelay(1); + + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + mdelay(1); + + /* Calibrations now: Read DQS gating calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); + set_wait_for_bits_clear(&mmdc->mpdgctrl0, + AUTO_RD_DQS_GATING_CALIBRATION_EN, + AUTO_RD_DQS_GATING_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* Calibrations now: Read calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + set_wait_for_bits_clear(&mmdc->mprddlhwctl, + AUTO_RD_CALIBRATION_EN, + AUTO_RD_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* PD, SR */ + out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); + out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); + + /* refresh scheme */ + set_wait_for_bits_clear(&mmdc->mdref, + CONFIG_SYS_MMDC_CORE_REFRESH_CTL, + START_REFRESH); + + /* disable CON_REQ */ + out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); +} + +int dram_init(void) +{ + mmdc_init(); + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + u8 mux_sdhc_cd = 0x80; + + i2c_set_bus_num(0); + + i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); + return 0; +} +#endif + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *) + CONFIG_SYS_CCI400_ADDR; + + /* Set CCI-400 control override register to enable barrier + * transaction */ + out_le32(&cci->ctrl_ord, + CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} +#endif diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h new file mode 100644 index 00000000000..584f604aa86 --- /dev/null +++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h @@ -0,0 +1,35 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1043AQDS_QIXIS_H__ +#define __LS1043AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1043AQDS */ + +/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +/* BRDCFG2 - SD clock*/ +#define QIXIS_SDCLK1_100 0x0 +#define QIXIS_SDCLK1_125 0x1 +#define QIXIS_SDCLK1_165 0x2 +#define QIXIS_SDCLK1_100_SP 0x3 + +#endif diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig new file mode 100644 index 00000000000..2bc178c761b --- /dev/null +++ b/configs/ls1012aqds_qspi_defconfig @@ -0,0 +1,32 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012AQDS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h new file mode 100644 index 00000000000..ccd94ec952c --- /dev/null +++ b/include/configs/ls1012a_common.h @@ -0,0 +1,145 @@ +/* + * Copyright 2016 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1012A_COMMON_H +#define __LS1012A_COMMON_H + +#define CONFIG_FSL_LAYERSCAPE +#define CONFIG_FSL_LSCH2 +#define CONFIG_LS1012A +#define CONFIG_GICV2 + +#define CONFIG_SYS_HAS_SERDES + +#include +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SUPPORT_RAW_INITRD + +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#define CONFIG_SYS_TEXT_BASE 0x40100000 + +#define CONFIG_SYS_FSL_CLK +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 125000000 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F 1 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */ + +/* CSU */ +#define CONFIG_LAYERSCAPE_NS_ACCESS + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/*SPI device */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 1000000 +#define CONFIG_ENV_SPI_MODE 0x03 +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_FSL_SPI_INTERFACE +#define CONFIG_SF_DATAFLASH + +#define CONFIG_FSL_QSPI +#define QSPI0_AMBA_BASE 0x40000000 +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_BAR + +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x40000 /* 256KB */ +#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 +#endif + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* Command line configuration */ +#define CONFIG_CMD_ENV +#undef CONFIG_CMD_IMLS + +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#define CONFIG_DISPLAY_CPUINFO + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "initrd_high=0xffffffff\0" \ + "verify=no\0" \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0xa00000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "console=ttyAMA0,38400n8\0" + +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ + "earlycon=uart8250,mmio,0x21c0500" +#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ + "$kernel_start $kernel_size && "\ + "bootm $kernel_load" +#define CONFIG_BOOTDELAY 10 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_PANIC_HANG +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#include + +#endif /* __LS1012A_COMMON_H */ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h new file mode 100644 index 00000000000..2d84095e94a --- /dev/null +++ b/include/configs/ls1012aqds.h @@ -0,0 +1,191 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1012AQDS_H__ +#define __LS1012AQDS_H__ + +#include "ls1012a_common.h" + + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + +#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000 +#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000 + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_BRDCFG_REG 0x04 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0xf7 +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x08 +#define QIXIS_RST_CTL_RESET 0x41 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#endif + +/* + * I2C bus multiplexer + */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ +#define I2C_RETIMER_ADDR 0x18 +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_CH7301 0xC +#define I2C_MUX_CH5 0xD +#define I2C_MUX_CH7 0xF + +#define I2C_MUX_CH_VOL_MONITOR 0xa + +/* +* RTC configuration +*/ +#define RTC +#define CONFIG_RTC_PCF8563 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CONFIG_CMD_DATE + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +/* DSPI */ +#define CONFIG_FSL_DSPI1 +#define CONFIG_DEFAULT_SPI_BUS 1 + +#define CONFIG_CMD_SPI +#define MMAP_DSPI DSPI1_BASE_ADDR + +#define CONFIG_SYS_DSPI_CTAR0 1 + +#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ + DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(0)) +#define CONFIG_SPI_FLASH_SST /* cs1 */ + +#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ + DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(0)) +#define CONFIG_SPI_FLASH_STMICRO /* cs2 */ + +#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ + DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(0)) +#define CONFIG_SPI_FLASH_EON /* cs3 */ + +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_CS 0 + +/* +* USB +*/ +/* EHCI Support - disbaled by default */ +/*#define CONFIG_HAS_FSL_DR_USB*/ + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif + +/*XHCI Support - enabled by default*/ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#endif + +/* MMC */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION +#endif + +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA AHCI_BASE_ADDR + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" + +#define CONFIG_SYS_PCI_64BIT + +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ + +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */ + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI + +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +#define CONFIG_MISC_INIT_R + +#endif /* __LS1012AQDS_H__ */ -- cgit v1.3.1 From 3b6e3898c2c68fa8340794c8abf5d47859069f98 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 3 Jun 2016 18:41:35 +0530 Subject: armv8: ls1012a: Add support of ls1012ardb board QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Calvin Johnson Signed-off-by: Pratiyush Mohan Srivastava Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/arm/Kconfig | 10 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/fsl-ls1012a-rdb.dts | 16 +++ arch/arm/dts/fsl-ls1012a-rdb.dtsi | 39 ++++++ board/freescale/ls1012ardb/Kconfig | 15 +++ board/freescale/ls1012ardb/MAINTAINERS | 6 + board/freescale/ls1012ardb/Makefile | 7 + board/freescale/ls1012ardb/README | 54 ++++++++ board/freescale/ls1012ardb/ls1012ardb.c | 224 ++++++++++++++++++++++++++++++++ configs/ls1012ardb_qspi_defconfig | 32 +++++ include/configs/ls1012ardb.h | 107 +++++++++++++++ 11 files changed, 512 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dts create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dtsi create mode 100644 board/freescale/ls1012ardb/Kconfig create mode 100644 board/freescale/ls1012ardb/MAINTAINERS create mode 100644 board/freescale/ls1012ardb/Makefile create mode 100644 board/freescale/ls1012ardb/README create mode 100644 board/freescale/ls1012ardb/ls1012ardb.c create mode 100644 configs/ls1012ardb_qspi_defconfig create mode 100644 include/configs/ls1012ardb.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 30fc32a853f..9be8c2b8c99 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -705,6 +705,15 @@ config TARGET_LS1012AQDS development platform that supports the QorIQ LS1012A Layerscape Architecture processor. +config TARGET_LS1012ARDB + bool "Support ls1012ardb" + select ARM64 + help + Support for Freescale LS1012ARDB platform. + The LS1012A Reference design board (RDB) is a high-performance + development platform that supports the QorIQ LS1012A + Layerscape Architecture processor. + config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -862,6 +871,7 @@ source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/ls1012aqds/Kconfig" +source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/mx23evk/Kconfig" source "board/freescale/mx25pdk/Kconfig" source "board/freescale/mx28evk/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 47ec7a28ec5..f021699ebf9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -121,7 +121,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ - fsl-ls1012a-qds.dtb + fsl-ls1012a-qds.dtb \ + fsl-ls1012a-rdb.dtb dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts new file mode 100644 index 00000000000..f683812c30a --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-rdb.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1012A family SoC. + * + * Copyright 2016, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1012a-rdb.dtsi" + +/ { + chosen { + stdout-path = &duart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi new file mode 100644 index 00000000000..bf407aeb94c --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi @@ -0,0 +1,39 @@ +/* + * Device Tree Include file for Freescale Layerscape-1012A family SoC. + * + * Copyright 2016, Freescale Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/include/ "fsl-ls1012a.dtsi" + +/ { + model = "LS1012A RDB Board"; + aliases { + spi0 = &qspi; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fl128s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&duart0 { + status = "okay"; +}; diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig new file mode 100644 index 00000000000..3f67c2841f5 --- /dev/null +++ b/board/freescale/ls1012ardb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1012ARDB + +config SYS_BOARD + default "ls1012ardb" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012ardb" + +endif diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS new file mode 100644 index 00000000000..79a2a7dd247 --- /dev/null +++ b/board/freescale/ls1012ardb/MAINTAINERS @@ -0,0 +1,6 @@ +LS1012ARDB BOARD +M: Prabhakar Kushwaha +S: Maintained +F: board/freescale/ls1012ardb/ +F: include/configs/ls1012ardb.h +F: configs/ls1012ardb_qspi_defconfig diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile new file mode 100644 index 00000000000..05fa9d9c5b2 --- /dev/null +++ b/board/freescale/ls1012ardb/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012ardb.o diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README new file mode 100644 index 00000000000..453b4329155 --- /dev/null +++ b/board/freescale/ls1012ardb/README @@ -0,0 +1,54 @@ +Overview +-------- +QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance +development platform, with a complete debugging environment. +The LS1012ARDB board supports the QorIQ LS1012A processor and is +optimized to support the high-bandwidth DDR3L memory and +a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. + +LS1012ARDB board Overview +----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - SATA 3.0 + - DDR Controller + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s + -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select + signals to + - QSPI NOR flash memory (2 virtual banks) + - the QSPI emulator.s + - USB 3.0 + - one high-speed USB 2.0/3.0 port. + - Two enhanced secure digital host controllers: + - SDHC1 controller can be connected to onboard SDHC connector + - SDHC2 controller: Three dual 1:4 mux/demux devices, + 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC, + SDIO WiFi, SPI, and Ardiuno shield + - 2 I2C controllers + - One SATA onboard connectors + - UART + - The LS1012A processor consists of two UART controllers, + out of which only UART1 is used on RDB. + - ARM JTAG support + +Booting Options +--------------- +a) QSPI Flash Emu Boot +b) QSPI Flash 1 +c) QSPI Flash 2 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c new file mode 100644 index 00000000000..f69768d24e9 --- /dev/null +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -0,0 +1,224 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) +{ + int timeout = 1000; + + out_be32(ptr, value); + + while (in_be32(ptr) & bits) { + udelay(100); + timeout--; + } + if (timeout <= 0) + puts("Error: wait for clear timeout.\n"); +} + +int checkboard(void) +{ + u8 in1; + + puts("Board: LS1012ARDB "); + + /* Initialize i2c early for Serial flash bank information */ + i2c_set_bus_num(0); + + if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) { + printf("Error reading i2c boot information!\n"); + return 0; /* Don't want to hang() on this error */ + } + + puts("Version"); + if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A) + puts(": RevA"); + else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B) + puts(": RevB"); + else + puts(": unknown"); + + printf(", boot from QSPI"); + if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU) + puts(": emu\n"); + else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1) + puts(": bank1\n"); + else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2) + puts(": bank2\n"); + else + puts("unknown\n"); + + return 0; +} + +void mmdc_init(void) +{ + struct mmdc_p_regs *mmdc = + (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; + + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + /* configure timing parms */ + out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); + out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); + out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); + out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); + + /* other parms */ + out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); + out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); + out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); + out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); + + /* out of reset delays */ + out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); + + /* physical parms */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); + out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); + + /* Enable MMDC */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); + + /* dram init sequence: update MRs */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | + CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); + + /* dram init sequence: ZQCL */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, + CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, + FORCE_ZQ_AUTO_CALIBRATION); + + /* Calibrations now: wr lvl */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | + CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); + set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); + + mdelay(1); + + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + mdelay(1); + + /* Calibrations now: Read DQS gating calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); + set_wait_for_bits_clear(&mmdc->mpdgctrl0, + AUTO_RD_DQS_GATING_CALIBRATION_EN, + AUTO_RD_DQS_GATING_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* Calibrations now: Read calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + set_wait_for_bits_clear(&mmdc->mprddlhwctl, + AUTO_RD_CALIBRATION_EN, + AUTO_RD_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* PD, SR */ + out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); + out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); + + /* refresh scheme */ + set_wait_for_bits_clear(&mmdc->mdref, + CONFIG_SYS_MMDC_CORE_REFRESH_CTL, + START_REFRESH); + + /* disable CON_REQ */ + out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); +} + +int dram_init(void) +{ + mmdc_init(); + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + /* + * Set CCI-400 control override register to enable barrier + * transaction + */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig new file mode 100644 index 00000000000..456eebd1592 --- /dev/null +++ b/configs/ls1012ardb_qspi_defconfig @@ -0,0 +1,32 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012ARDB=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h new file mode 100644 index 00000000000..f63c66a8d99 --- /dev/null +++ b/include/configs/ls1012ardb.h @@ -0,0 +1,107 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1012ARDB_H__ +#define __LS1012ARDB_H__ + +#include "ls1012a_common.h" + + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + +#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000 +#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000 + +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +/* +* USB +*/ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#endif + +/* + * I2C IO expander + */ + +#define I2C_MUX_IO1_ADDR 0x24 +#define __SW_BOOT_MASK 0xFC +#define __SW_BOOT_EMU 0x10 +#define __SW_BOOT_BANK1 0x00 +#define __SW_BOOT_BANK2 0x01 +#define __SW_REV_MASK 0x07 +#define __SW_REV_A 0xF8 +#define __SW_REV_B 0xF0 + +/* MMC */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION +#endif + +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA AHCI_BASE_ADDR + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" + +#define CONFIG_SYS_PCI_64BIT + +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ + +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */ + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI + +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +#endif /* __LS1012ARDB_H__ */ -- cgit v1.3.1 From ff78aa2ba19cda755b01818fb3caf2aca9236865 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 3 Jun 2016 18:41:36 +0530 Subject: armv8: ls1012a: Add support of ls1012afrdm board QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development platform, with a complete debugging environment. The LS1012AFRDM board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Shengzhou Liu Signed-off-by: Calvin Johnson Signed-off-by: Pratiyush Mohan Srivastava Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/arm/Kconfig | 10 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/fsl-ls1012a-frdm.dts | 16 +++ arch/arm/dts/fsl-ls1012a-frdm.dtsi | 37 ++++++ board/freescale/ls1012afrdm/Kconfig | 15 +++ board/freescale/ls1012afrdm/MAINTAINERS | 6 + board/freescale/ls1012afrdm/Makefile | 7 ++ board/freescale/ls1012afrdm/README | 58 +++++++++ board/freescale/ls1012afrdm/ls1012afrdm.c | 192 ++++++++++++++++++++++++++++++ configs/ls1012afrdm_qspi_defconfig | 29 +++++ include/configs/ls1012afrdm.h | 44 +++++++ 11 files changed, 416 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dts create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dtsi create mode 100644 board/freescale/ls1012afrdm/Kconfig create mode 100644 board/freescale/ls1012afrdm/MAINTAINERS create mode 100644 board/freescale/ls1012afrdm/Makefile create mode 100644 board/freescale/ls1012afrdm/README create mode 100644 board/freescale/ls1012afrdm/ls1012afrdm.c create mode 100644 configs/ls1012afrdm_qspi_defconfig create mode 100644 include/configs/ls1012afrdm.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9be8c2b8c99..71169b2520f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -714,6 +714,15 @@ config TARGET_LS1012ARDB development platform that supports the QorIQ LS1012A Layerscape Architecture processor. +config TARGET_LS1012AFRDM + bool "Support ls1012afrdm" + select ARM64 + help + Support for Freescale LS1012AFRDM platform. + The LS1012A Freedom board (FRDM) is a high-performance + development platform that supports the QorIQ LS1012A + Layerscape Architecture processor. + config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -872,6 +881,7 @@ source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" +source "board/freescale/ls1012afrdm/Kconfig" source "board/freescale/mx23evk/Kconfig" source "board/freescale/mx25pdk/Kconfig" source "board/freescale/mx28evk/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f021699ebf9..e8ad6c60c2f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -122,7 +122,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ fsl-ls1012a-qds.dtb \ - fsl-ls1012a-rdb.dtb + fsl-ls1012a-rdb.dtb \ + fsl-ls1012a-frdm.dtb dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts new file mode 100644 index 00000000000..983e599b9bb --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-frdm.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1012A family SoC. + * + * Copyright 2016, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1012a-frdm.dtsi" + +/ { + chosen { + stdout-path = &duart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi new file mode 100644 index 00000000000..25dcdd2929a --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi @@ -0,0 +1,37 @@ +/* + * Device Tree file for Freescale Layerscape-1012A family SoC. + * + * Copyright 2016, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "fsl-ls1012a.dtsi" + +/ { + model = "LS1012A FREEDOM Board"; + aliases { + spi0 = &qspi; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fl128s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&duart0 { + status = "okay"; +}; diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig new file mode 100644 index 00000000000..a34521cf795 --- /dev/null +++ b/board/freescale/ls1012afrdm/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1012AFRDM + +config SYS_BOARD + default "ls1012afrdm" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012afrdm" + +endif diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS new file mode 100644 index 00000000000..842f86f8619 --- /dev/null +++ b/board/freescale/ls1012afrdm/MAINTAINERS @@ -0,0 +1,6 @@ +LS1012AFRDM BOARD +M: Prabhakar Kushwaha +S: Maintained +F: board/freescale/ls1012afrdm/ +F: include/configs/ls1012afrdm.h +F: configs/ls1012afrdm_qspi_defconfig diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile new file mode 100644 index 00000000000..dbfa2cea383 --- /dev/null +++ b/board/freescale/ls1012afrdm/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012afrdm.o diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README new file mode 100644 index 00000000000..181c4615a87 --- /dev/null +++ b/board/freescale/ls1012afrdm/README @@ -0,0 +1,58 @@ +Overview +-------- +QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development +platform, with a complete debugging environment. The LS1012AFRDM board +supports the QorIQ LS1012A processor and is optimized to support the +high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. + + LS1012AFRDM board Overview + ----------------------- + - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s + - 2 SGMII 1G PHYs + - DDR Controller + - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s + operating at 1.35 V + - QSPI + - Onboard 512 Mbit QSPI flash memory running at speed up + to 108/54 MHz + - One high-speed USB 2.0/3.0 port, one USB 2.0 port + - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a + Micro-AB connector. + - USB 2.0 port is a debug port (CMSIS DAP) and is configured + as a Micro-AB device. + - I2C controller + - One I2C bus with connectivity to Arduino headers + - UART + - UART (Console): UART1 (Without flow control) for console + - ARM JTAG support + - ARM Cortex® 10-pin JTAG connector for LS1012A + - CMSIS DAP through K20 microcontroller + - SAI Audio interface + - One SAI port, SAI 2 with full duplex support + - Clocks + - 25 MHz crystal for LS1012A + - 8 MHz Crystal for K20 + - 24 MHz for SC16IS740IPW SPI to Dual UART bridge + - Power Supplies + - 5 V input supply from USB + - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and + other board interfaces + +Booting Options +--------------- +QSPI Flash 1 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c new file mode 100644 index 00000000000..a94a458f53d --- /dev/null +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -0,0 +1,192 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) +{ + int timeout = 1000; + + out_be32(ptr, value); + + while (in_be32(ptr) & bits) { + udelay(100); + timeout--; + } + if (timeout <= 0) + puts("Error: wait for clear timeout.\n"); +} + +int checkboard(void) +{ + puts("Board: LS1012AFRDM "); + + return 0; +} + +void mmdc_init(void) +{ + struct mmdc_p_regs *mmdc = + (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; + + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + /* configure timing parms */ + out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); + out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); + out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); + out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); + + /* other parms */ + out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); + out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); + out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); + out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); + + /* out of reset delays */ + out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); + + /* physical parms */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); + out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); + + /* Enable MMDC */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); + + /* dram init sequence: update MRs */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | + CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); + + /* dram init sequence: ZQCL */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, + CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, + FORCE_ZQ_AUTO_CALIBRATION); + + /* Calibrations now: wr lvl */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | + CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); + set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); + + mdelay(1); + + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + mdelay(1); + + /* Calibrations now: Read DQS gating calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); + set_wait_for_bits_clear(&mmdc->mpdgctrl0, + AUTO_RD_DQS_GATING_CALIBRATION_EN, + AUTO_RD_DQS_GATING_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* Calibrations now: Read calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + set_wait_for_bits_clear(&mmdc->mprddlhwctl, + AUTO_RD_CALIBRATION_EN, + AUTO_RD_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* PD, SR */ + out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); + out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); + + /* refresh scheme */ + set_wait_for_bits_clear(&mmdc->mdref, + CONFIG_SYS_MMDC_CORE_REFRESH_CTL, + START_REFRESH); + + /* disable CON_REQ */ + out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); +} + +int dram_init(void) +{ + mmdc_init(); + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + /* + * Set CCI-400 control override register to enable barrier + * transaction + */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig new file mode 100644 index 00000000000..349758b84c9 --- /dev/null +++ b/configs/ls1012afrdm_qspi_defconfig @@ -0,0 +1,29 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012AFRDM=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_SYS_NS16550=y diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h new file mode 100644 index 00000000000..3e7c430c646 --- /dev/null +++ b/include/configs/ls1012afrdm.h @@ -0,0 +1,44 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1012ARDB_H__ +#define __LS1012ARDB_H__ + +#include "ls1012a_common.h" + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x04180000 +#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x84180000 + +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +/* +* USB +*/ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#endif + +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +#endif /* __LS1012ARDB_H__ */ -- cgit v1.3.1 From 4835c737ff8ca65aa2bf206dcddd6407f4bc40cf Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 12 May 2016 08:57:13 +0200 Subject: usb: dwc3: Correct datatype of base to unsigned long Correct type of varibale base to unsigned long as keeping it as int causes usb failures if MSB of the base address is set. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- include/dwc3-uboot.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h index 09ff8a74d66..7af2ad11e4e 100644 --- a/include/dwc3-uboot.h +++ b/include/dwc3-uboot.h @@ -13,7 +13,7 @@ #include struct dwc3_device { - int base; + unsigned long base; enum usb_dr_mode dr_mode; u32 maximum_speed; unsigned tx_fifo_resize:1; -- cgit v1.3.1 From 0ff27eb25f027602261fd009b1cf588f7918f02c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 4 Jun 2016 07:35:02 +0900 Subject: configs: blackfin: move CONFIG_USB to defconfig These Blackfin boards are the last ones that define CONFIG_USB in their headers. Signed-off-by: Masahiro Yamada --- configs/bf526-ezbrd_defconfig | 1 + configs/bf527-ezkit-v2_defconfig | 1 + configs/bf527-ezkit_defconfig | 1 + configs/bf548-ezkit_defconfig | 1 + include/configs/bf526-ezbrd.h | 1 - include/configs/bf527-ezkit.h | 1 - include/configs/bf548-ezkit.h | 1 - 7 files changed, 4 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/configs/bf526-ezbrd_defconfig b/configs/bf526-ezbrd_defconfig index 85c2a6be194..ea4f8e4bafd 100644 --- a/configs/bf526-ezbrd_defconfig +++ b/configs/bf526-ezbrd_defconfig @@ -17,3 +17,4 @@ CONFIG_CMD_FAT=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y +CONFIG_USB=y diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig index ff797f8786d..faac28d39cd 100644 --- a/configs/bf527-ezkit-v2_defconfig +++ b/configs/bf527-ezkit-v2_defconfig @@ -17,4 +17,5 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_USB=y CONFIG_LIB_RAND=y diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig index eff2a1263ef..d69b14622e0 100644 --- a/configs/bf527-ezkit_defconfig +++ b/configs/bf527-ezkit_defconfig @@ -17,3 +17,4 @@ CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_NET_TFTP_VARS is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_USB=y diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig index 6d398ac57d6..e4fa1364518 100644 --- a/configs/bf548-ezkit_defconfig +++ b/configs/bf548-ezkit_defconfig @@ -16,5 +16,6 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_USB=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y CONFIG_LIB_RAND=y diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index 74c3464c4dc..cf8ef8af753 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -125,7 +125,6 @@ * USB Settings */ #if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) -#define CONFIG_USB #define CONFIG_USB_MUSB_HCD #define CONFIG_USB_BLACKFIN #define CONFIG_USB_STORAGE diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index e2684735a79..c958a942ec0 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -128,7 +128,6 @@ * USB Settings */ #if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) -#define CONFIG_USB #define CONFIG_USB_MUSB_HCD #define CONFIG_USB_BLACKFIN #define CONFIG_USB_STORAGE diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index 6830e4d7c99..be28ea33ad9 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -151,7 +151,6 @@ * USB Settings */ #if !defined(__ADSPBF544__) -#define CONFIG_USB #define CONFIG_USB_MUSB_HCD #define CONFIG_USB_BLACKFIN #define CONFIG_USB_STORAGE -- cgit v1.3.1 From 0a8cc1a3a4206d556da784a0e98598190dfe5408 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 4 Jun 2016 07:35:03 +0900 Subject: usb: move CONFIG_USB_XHCI to Kconfig with renaming Move CONFIG_USB_XHCI to defconfig files for all boards, renaming it into CONFIG_USB_XHCI_HCD. As commented in the help of "config USB_XHCI" entry, this has been a TODO for a long time; now CONFIG_USB_XHCI_HCD and CONFIG_USB_XHCI have been unified in favor of the former. Note: Some boards define CONFIG_USB_XHCI in their headers without CONFIG_USB, which does not meet the "depends on" in Kconfig. I added CONFIG_USB=y for those boards when converting. Otherwise, they would fail to build. Signed-off-by: Masahiro Yamada --- common/usb.c | 2 +- configs/am437x_hs_evm_defconfig | 1 + configs/am43xx_evm_defconfig | 1 + configs/am43xx_evm_ethboot_defconfig | 1 + configs/am43xx_evm_qspiboot_defconfig | 1 + configs/am43xx_evm_usbhost_boot_defconfig | 1 + configs/am57xx_evm_defconfig | 2 ++ configs/am57xx_evm_nodt_defconfig | 2 ++ configs/am57xx_hs_evm_defconfig | 2 ++ configs/cm_t43_defconfig | 2 ++ configs/dra72_hs_evm_defconfig | 1 + configs/dra74_hs_evm_defconfig | 1 + configs/dra7xx_evm_defconfig | 1 + configs/k2e_evm_defconfig | 2 ++ configs/k2g_evm_defconfig | 2 ++ configs/k2hk_evm_defconfig | 2 ++ configs/k2l_evm_defconfig | 2 ++ configs/ls1021aqds_ddr4_nor_defconfig | 2 ++ configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 2 ++ configs/ls1021aqds_nand_defconfig | 2 ++ configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 ++ configs/ls1021aqds_nor_defconfig | 2 ++ configs/ls1021aqds_nor_lpuart_defconfig | 2 ++ configs/ls1021aqds_qspi_defconfig | 2 ++ configs/ls1021aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1021aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_nor_defconfig | 2 ++ configs/ls1021atwr_nor_lpuart_defconfig | 2 ++ configs/ls1021atwr_qspi_defconfig | 2 ++ configs/ls1021atwr_sdcard_ifc_defconfig | 2 ++ configs/ls1021atwr_sdcard_qspi_defconfig | 2 ++ configs/ls1043aqds_defconfig | 2 ++ configs/ls1043aqds_lpuart_defconfig | 2 ++ configs/ls1043aqds_nand_defconfig | 2 ++ configs/ls1043aqds_nor_ddr3_defconfig | 2 ++ configs/ls1043aqds_qspi_defconfig | 2 ++ configs/ls1043aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1043aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1043ardb_SECURE_BOOT_defconfig | 2 ++ configs/ls1043ardb_defconfig | 2 ++ configs/ls1043ardb_nand_defconfig | 2 ++ configs/ls1043ardb_sdcard_defconfig | 2 ++ configs/ls2080aqds_SECURE_BOOT_defconfig | 2 ++ configs/ls2080aqds_defconfig | 2 ++ configs/ls2080aqds_nand_defconfig | 2 ++ configs/ls2080ardb_SECURE_BOOT_defconfig | 2 ++ configs/ls2080ardb_defconfig | 2 ++ configs/ls2080ardb_nand_defconfig | 2 ++ configs/odroid-xu3_defconfig | 1 + configs/peach-pi_defconfig | 1 + configs/peach-pit_defconfig | 1 + configs/smdk5420_defconfig | 1 + configs/xilinx_zynqmp_ep_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 + configs/xilinx_zynqmp_zcu102_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 + drivers/usb/host/Kconfig | 6 ------ drivers/usb/host/Makefile | 2 +- include/configs/am43xx_evm.h | 1 - include/configs/am57xx_evm.h | 1 - include/configs/cm_t43.h | 1 - include/configs/dra7xx_evm.h | 1 - include/configs/ds414.h | 3 +-- include/configs/exynos5420-common.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - include/configs/ls1043aqds.h | 1 - include/configs/ls1043ardb.h | 1 - include/configs/ls2080aqds.h | 1 - include/configs/ls2080ardb.h | 1 - include/configs/smdk5420.h | 1 - include/configs/ti_armv7_keystone2.h | 1 - include/configs/xilinx_zynqmp.h | 1 - 75 files changed, 100 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/common/usb.c b/common/usb.c index 8d9efe516b7..b3ba487890a 100644 --- a/common/usb.c +++ b/common/usb.c @@ -1182,7 +1182,7 @@ int usb_new_device(struct usb_device *dev) * with the device. So a get_descriptor will fail before any * of that is done for XHCI unlike EHCI. */ -#ifdef CONFIG_USB_XHCI +#ifdef CONFIG_USB_XHCI_HCD do_read = false; #endif err = usb_setup_device(dev, do_read, dev->parent); diff --git a/configs/am437x_hs_evm_defconfig b/configs/am437x_hs_evm_defconfig index c4accb6da17..a7d4041d4f7 100644 --- a/configs/am437x_hs_evm_defconfig +++ b/configs/am437x_hs_evm_defconfig @@ -42,6 +42,7 @@ CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 3955612f4cf..e8a3d753e38 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -42,6 +42,7 @@ CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig index 33fb552fc55..2a85a34a756 100644 --- a/configs/am43xx_evm_ethboot_defconfig +++ b/configs/am43xx_evm_ethboot_defconfig @@ -29,6 +29,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index 5f90e2bef1c..b4f1228f534 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -29,6 +29,7 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 72f4ad854f8..e88a9e30569 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -40,6 +40,7 @@ CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index cccdc10dacc..815811fb319 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -33,3 +33,5 @@ CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig index 47d103beefd..373aa9e64aa 100644 --- a/configs/am57xx_evm_nodt_defconfig +++ b/configs/am57xx_evm_nodt_defconfig @@ -22,4 +22,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_OF_LIBFDT=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 60525cdf504..aa3d6273bd6 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -34,3 +34,5 @@ CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index c926a3a4bbf..a8ffea71713 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -37,4 +37,6 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_OF_LIBFDT=y diff --git a/configs/dra72_hs_evm_defconfig b/configs/dra72_hs_evm_defconfig index 01f985e397f..767e067df21 100644 --- a/configs/dra72_hs_evm_defconfig +++ b/configs/dra72_hs_evm_defconfig @@ -44,6 +44,7 @@ CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/dra74_hs_evm_defconfig b/configs/dra74_hs_evm_defconfig index 1b30ad4d9a8..e05efe07c63 100644 --- a/configs/dra74_hs_evm_defconfig +++ b/configs/dra74_hs_evm_defconfig @@ -43,6 +43,7 @@ CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 288f8b34de2..9ee579c08f8 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -42,6 +42,7 @@ CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 044a9bf5b6e..b1d40184d2d 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -32,3 +32,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_ETH=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index d0b45ce3f8a..2c7167e2014 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -32,3 +32,5 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_ETH=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 3975e804e53..410de640f0b 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -32,3 +32,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_ETH=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 844dd57163f..91d7a04c137 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -32,3 +32,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_ETH=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 04ded544d81..92f77966018 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -27,3 +27,5 @@ CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index 7915200ca18..338dbf457cd 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -27,3 +27,5 @@ CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_FSL_LPUART=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 9002a014fec..b3edd0a1e7b 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -21,6 +21,8 @@ CONFIG_CMD_FAT=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_OF_LIBFDT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 30c2ca5576d..499feceb23b 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -22,6 +22,8 @@ CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_RSA=y CONFIG_OF_LIBFDT=y CONFIG_FIT=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index a30153aa3a7..cf4f79d290f 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -26,3 +26,5 @@ CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 217cf88a1ff..5ad90829830 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -27,3 +27,5 @@ CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_FSL_LPUART=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 15b0b0d686e..33484ede65b 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -33,3 +33,5 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index ef42d3d99c4..09927184a1a 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -25,3 +25,5 @@ CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 69f5b612aaa..abb32877c8d 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -32,3 +32,5 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 1c0ae06c4bf..f3a9e35930d 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -22,6 +22,8 @@ CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_RSA=y CONFIG_OF_LIBFDT=y CONFIG_FIT=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 10cc576e7c7..be686312822 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -26,3 +26,5 @@ CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index f56f93117a4..ec165b11484 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -27,3 +27,5 @@ CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_FSL_LPUART=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index bc419fbda2f..c0a79673f6f 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -34,3 +34,5 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index e27758b62df..1900c1a0a08 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_FAT=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_OF_LIBFDT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 01856d4363f..272dabdbc46 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -34,3 +34,5 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 346faf46a03..fa4270ae2d2 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -25,3 +25,5 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 2c6ac35c4fd..2a845b602bd 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -26,3 +26,5 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_FSL_LPUART=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index cc8d8fa51fb..20dc98bcb3f 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -26,3 +26,5 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 7d0646c1bd6..829ed3209e8 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -24,3 +24,5 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 8ea14164ab0..b6b98e3df16 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -26,3 +26,5 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 7e5949d98dd..40ae837ac98 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -26,3 +26,5 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 609fd636e45..8228d22da43 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -27,3 +27,5 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index cacee2f7489..9e4ab65e607 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -21,4 +21,6 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_RSA=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 49d0740fae4..37a67b9dabe 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -21,3 +21,5 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index d240cde39ef..e847312dcd0 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -22,3 +22,5 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index f85368541e8..e8a516b30b3 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -22,3 +22,5 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 04a84abc3bf..14619fbb11b 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -29,5 +29,7 @@ CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 3b6504b7acc..2ca0117472a 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -29,4 +29,6 @@ CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 130231346bd..2af3687cc8b 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -22,5 +22,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_OF_LIBFDT=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index f974d8832c3..76a9c3d1c42 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -29,5 +29,7 @@ CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index 0168dbb0d55..82d14be93f2 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -29,4 +29,6 @@ CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 718a651b962..17f0f6d5781 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -22,5 +22,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_OF_LIBFDT=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 8995cc2f6be..e78f973a5af 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -36,6 +36,7 @@ CONFIG_PMIC_S2MPS11=y CONFIG_DM_REGULATOR=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_PHY_SAMSUNG=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index c8c74c03013..9a815d03eca 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -55,6 +55,7 @@ CONFIG_EXYNOS_SPI=y CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_TPM=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index c5fbf8c8225..5bea9379469 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -55,6 +55,7 @@ CONFIG_EXYNOS_SPI=y CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_TPM=y diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig index 40de7c149c1..ad599fccabd 100644 --- a/configs/smdk5420_defconfig +++ b/configs/smdk5420_defconfig @@ -36,4 +36,5 @@ CONFIG_DM_REGULATOR=y CONFIG_EXYNOS_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_VIDEO_BRIDGE=y diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index f342ed293c7..2a5b2d9554c 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -56,6 +56,7 @@ CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=25000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_GADGET=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 5d641a57bd5..457393a30f3 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -49,6 +49,7 @@ CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_ULPI_VIEWPORT=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 77e6180143f..fe415cd6759 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -41,6 +41,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_ULPI_VIEWPORT=y diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig index b370bc1835a..6b76dbcefb9 100644 --- a/configs/xilinx_zynqmp_zcu102_defconfig +++ b/configs/xilinx_zynqmp_zcu102_defconfig @@ -47,6 +47,7 @@ CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_ULPI_VIEWPORT=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 97644528898..1a3fb21bee5 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -47,6 +47,7 @@ CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_ULPI_VIEWPORT=y diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index d2363c80671..8a6f732894e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -9,12 +9,6 @@ config USB_XHCI_HCD The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 "SuperSpeed" host controller hardware. -config USB_XHCI - bool - default USB_XHCI_HCD - ---help--- - TODO: rename after most boards switch to Kconfig - if USB_XHCI_HCD config USB_XHCI_UNIPHIER diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 507519ea72c..620d114795a 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -54,7 +54,7 @@ obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci -obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o +obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index a54303df5c8..170d069647e 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -99,7 +99,6 @@ #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD) #define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 #define CONFIG_USB_HOST -#define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_STORAGE diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index d53b0fdd89c..6a3d8e5aef9 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -65,7 +65,6 @@ /* USB xHCI HOST */ #define CONFIG_USB_HOST #define CONFIG_USB_XHCI_DWC3 -#define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index c2dbd31803a..51eac933928 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -61,7 +61,6 @@ /* USB support */ #define CONFIG_USB_HOST -#define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_STORAGE diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 8a0cd66cd0f..0571dc0e990 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -211,7 +211,6 @@ /* USB xHCI HOST */ #define CONFIG_USB_HOST -#define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_STORAGE diff --git a/include/configs/ds414.h b/include/configs/ds414.h index 64c546cc82e..23373cdb58a 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -71,12 +71,11 @@ * - USB init fails, controller does not respond in time */ #if 0 #undef CONFIG_DM_USB -#define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_PCI #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif -#if !defined(CONFIG_USB_XHCI) +#if !defined(CONFIG_USB_XHCI_HCD) #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MARVELL #define CONFIG_EHCI_IS_TDI diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index cd86e066685..16153eb5952 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -48,7 +48,6 @@ */ #define CONFIG_CORE_COUNT 0x8 -#define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS #endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index f605ca62803..ac322404c3e 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -451,7 +451,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_XHCI_DWC3 -#define CONFIG_USB_XHCI #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 32d2acc0cda..c38d680abeb 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -58,7 +58,6 @@ #ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_XHCI_DWC3 -#define CONFIG_USB_XHCI #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index af1f73dbaa8..103bb2ebb99 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -388,7 +388,6 @@ unsigned long get_board_ddr_clk(void); /* USB */ #define CONFIG_HAS_FSL_XHCI_USB #ifdef CONFIG_HAS_FSL_XHCI_USB -#define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index aca8d95c153..0a716370b68 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -278,7 +278,6 @@ /* USB */ #define CONFIG_HAS_FSL_XHCI_USB #ifdef CONFIG_HAS_FSL_XHCI_USB -#define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 4b27114863d..743473fec84 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -383,7 +383,6 @@ unsigned long get_board_ddr_clk(void); * USB */ #define CONFIG_HAS_FSL_XHCI_USB -#define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 3baca643d58..1fe4138a445 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -316,7 +316,6 @@ unsigned long get_board_sys_clk(void); * USB */ #define CONFIG_HAS_FSL_XHCI_USB -#define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 9cf886c0664..c15acec89d0 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -31,7 +31,6 @@ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" /* USB */ -#define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS /* DRAM Memory Banks */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 2c9028c7355..2292eb2e325 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -191,7 +191,6 @@ "-(ubifs)" /* USB Configuration */ -#define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_XHCI_KEYSTONE #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index ffb6b34d57c..b0e0c22be63 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -118,7 +118,6 @@ #if defined(CONFIG_ZYNQMP_USB) #define CONFIG_USB_XHCI_DWC3 -#define CONFIG_USB_XHCI #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE -- cgit v1.3.1 From 10db7500369ea000af4c4c5b039b7946c2865ae9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 4 Jun 2016 07:35:04 +0900 Subject: usb: move CONFIG_USB_XHCI_DWC3 to Kconfig Create an entry for "config USB_XHCI_DWC3" in Kconfig and switch over to it for all boards. Signed-off-by: Masahiro Yamada --- configs/am437x_hs_evm_defconfig | 1 + configs/am43xx_evm_defconfig | 1 + configs/am43xx_evm_ethboot_defconfig | 1 + configs/am43xx_evm_qspiboot_defconfig | 1 + configs/am43xx_evm_usbhost_boot_defconfig | 1 + configs/am57xx_evm_defconfig | 1 + configs/am57xx_evm_nodt_defconfig | 1 + configs/am57xx_hs_evm_defconfig | 1 + configs/cm_t43_defconfig | 1 + configs/dra72_hs_evm_defconfig | 1 + configs/dra74_hs_evm_defconfig | 1 + configs/dra7xx_evm_defconfig | 1 + configs/k2e_evm_defconfig | 1 + configs/k2g_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_defconfig | 1 + configs/ls1043aqds_lpuart_defconfig | 1 + configs/ls1043aqds_nand_defconfig | 1 + configs/ls1043aqds_nor_ddr3_defconfig | 1 + configs/ls1043aqds_qspi_defconfig | 1 + configs/ls1043aqds_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_sdcard_qspi_defconfig | 1 + configs/ls1043ardb_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_defconfig | 1 + configs/ls1043ardb_nand_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 1 + configs/ls2080aqds_SECURE_BOOT_defconfig | 1 + configs/ls2080aqds_defconfig | 1 + configs/ls2080aqds_nand_defconfig | 1 + configs/ls2080ardb_SECURE_BOOT_defconfig | 1 + configs/ls2080ardb_defconfig | 1 + configs/ls2080ardb_nand_defconfig | 1 + configs/odroid-xu3_defconfig | 1 + configs/peach-pi_defconfig | 1 + configs/peach-pit_defconfig | 1 + configs/smdk5420_defconfig | 1 + configs/xilinx_zynqmp_ep_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 + configs/xilinx_zynqmp_zcu102_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 + drivers/usb/host/Kconfig | 6 ++++++ include/configs/am43xx_evm.h | 1 - include/configs/am57xx_evm.h | 1 - include/configs/cm_t43.h | 1 - include/configs/dra7xx_evm.h | 1 - include/configs/exynos5-common.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - include/configs/ls1043aqds.h | 1 - include/configs/ls1043ardb.h | 1 - include/configs/ls2080aqds.h | 1 - include/configs/ls2080ardb.h | 1 - include/configs/ti_armv7_keystone2.h | 1 - include/configs/xilinx_zynqmp.h | 1 - 71 files changed, 63 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/configs/am437x_hs_evm_defconfig b/configs/am437x_hs_evm_defconfig index a7d4041d4f7..3cd39eb65d4 100644 --- a/configs/am437x_hs_evm_defconfig +++ b/configs/am437x_hs_evm_defconfig @@ -43,6 +43,7 @@ CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index e8a3d753e38..cb3de11808a 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -43,6 +43,7 @@ CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig index 2a85a34a756..3b958d79b83 100644 --- a/configs/am43xx_evm_ethboot_defconfig +++ b/configs/am43xx_evm_ethboot_defconfig @@ -30,6 +30,7 @@ CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index b4f1228f534..52643325513 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -30,6 +30,7 @@ CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index e88a9e30569..34c875e5e84 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -41,6 +41,7 @@ CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 815811fb319..6743b846772 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -35,3 +35,4 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig index 373aa9e64aa..1cf82d293ed 100644 --- a/configs/am57xx_evm_nodt_defconfig +++ b/configs/am57xx_evm_nodt_defconfig @@ -24,4 +24,5 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_OF_LIBFDT=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index aa3d6273bd6..c109939fdac 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -36,3 +36,4 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index a8ffea71713..b80ca0da4ef 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -39,4 +39,5 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_OF_LIBFDT=y diff --git a/configs/dra72_hs_evm_defconfig b/configs/dra72_hs_evm_defconfig index 767e067df21..1a4082cbbc9 100644 --- a/configs/dra72_hs_evm_defconfig +++ b/configs/dra72_hs_evm_defconfig @@ -45,6 +45,7 @@ CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/dra74_hs_evm_defconfig b/configs/dra74_hs_evm_defconfig index e05efe07c63..edcdca08996 100644 --- a/configs/dra74_hs_evm_defconfig +++ b/configs/dra74_hs_evm_defconfig @@ -44,6 +44,7 @@ CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 9ee579c08f8..756af63c1fa 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -43,6 +43,7 @@ CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index b1d40184d2d..9fcdfe9b9fa 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -34,3 +34,4 @@ CONFIG_DM_ETH=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 2c7167e2014..8efa58c8c43 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -34,3 +34,4 @@ CONFIG_REMOTEPROC_TI_POWER=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 410de640f0b..278eaf32fd8 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -34,3 +34,4 @@ CONFIG_DM_ETH=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 91d7a04c137..8417e0ab075 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -34,3 +34,4 @@ CONFIG_DM_ETH=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 92f77966018..efaa7a9fd1c 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -29,3 +29,4 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index 338dbf457cd..9fa5cb95262 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -29,3 +29,4 @@ CONFIG_E1000=y CONFIG_FSL_LPUART=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index b3edd0a1e7b..24b7a15bfd5 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -23,6 +23,7 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_OF_LIBFDT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 499feceb23b..5d2b57d489d 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -24,6 +24,7 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_OF_LIBFDT=y CONFIG_FIT=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index cf4f79d290f..426a4bec039 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -28,3 +28,4 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 5ad90829830..4f5c1e8200b 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -29,3 +29,4 @@ CONFIG_E1000=y CONFIG_FSL_LPUART=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 33484ede65b..6a791c0a9c5 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -35,3 +35,4 @@ CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 09927184a1a..33e5c0cec3c 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -27,3 +27,4 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index abb32877c8d..45f0f734c5c 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -34,3 +34,4 @@ CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index f3a9e35930d..16243ee4ff3 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -24,6 +24,7 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_OF_LIBFDT=y CONFIG_FIT=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index be686312822..315834032be 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -28,3 +28,4 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index ec165b11484..bbeb4bf1d50 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -29,3 +29,4 @@ CONFIG_E1000=y CONFIG_FSL_LPUART=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index c0a79673f6f..6910c4e8501 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -36,3 +36,4 @@ CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 1900c1a0a08..f59ad74f16b 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -22,6 +22,7 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_OF_LIBFDT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 272dabdbc46..90f810adfae 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -36,3 +36,4 @@ CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index fa4270ae2d2..1fbfd38d3f9 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -27,3 +27,4 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 2a845b602bd..6b628d3c838 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -28,3 +28,4 @@ CONFIG_SPI_FLASH=y CONFIG_FSL_LPUART=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 20dc98bcb3f..90f870afa0f 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -28,3 +28,4 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 829ed3209e8..813c269509f 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -26,3 +26,4 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index b6b98e3df16..e665ba44952 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -28,3 +28,4 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 40ae837ac98..03a263a5eed 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -28,3 +28,4 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 8228d22da43..0062f5c50ac 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -29,3 +29,4 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 9e4ab65e607..bace827cb7b 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -23,4 +23,5 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 37a67b9dabe..48a89ab5f78 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -23,3 +23,4 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index e847312dcd0..627a90dc6e2 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -24,3 +24,4 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index e8a516b30b3..c676a91c0f9 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -24,3 +24,4 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 14619fbb11b..49a4a26295b 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -31,5 +31,6 @@ CONFIG_SYS_NS16550=y CONFIG_FSL_DSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 2ca0117472a..c3053452ae3 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -31,4 +31,5 @@ CONFIG_SYS_NS16550=y CONFIG_FSL_DSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 2af3687cc8b..8a6dd14b657 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -24,5 +24,6 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_OF_LIBFDT=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 76a9c3d1c42..a2d88ccb905 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -31,5 +31,6 @@ CONFIG_SYS_NS16550=y CONFIG_FSL_DSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index 82d14be93f2..dc2b872176a 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -31,4 +31,5 @@ CONFIG_SYS_NS16550=y CONFIG_FSL_DSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 17f0f6d5781..dbba8abae9a 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -24,5 +24,6 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_OF_LIBFDT=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index e78f973a5af..49cfa8c02ad 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -37,6 +37,7 @@ CONFIG_DM_REGULATOR=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_PHY_SAMSUNG=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index 9a815d03eca..3c403ba8da7 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -56,6 +56,7 @@ CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_TPM=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index 5bea9379469..bfa361498cb 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -56,6 +56,7 @@ CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_TPM=y diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig index ad599fccabd..3bda611f767 100644 --- a/configs/smdk5420_defconfig +++ b/configs/smdk5420_defconfig @@ -37,4 +37,5 @@ CONFIG_EXYNOS_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_VIDEO_BRIDGE=y diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 2a5b2d9554c..ad94d56cb72 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -57,6 +57,7 @@ CONFIG_DEBUG_UART_CLOCK=25000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_GADGET=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 457393a30f3..ad1566d3321 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -50,6 +50,7 @@ CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_ULPI_VIEWPORT=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index fe415cd6759..3aa80cbe978 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -42,6 +42,7 @@ CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_ULPI_VIEWPORT=y diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig index 6b76dbcefb9..a216f118546 100644 --- a/configs/xilinx_zynqmp_zcu102_defconfig +++ b/configs/xilinx_zynqmp_zcu102_defconfig @@ -48,6 +48,7 @@ CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_ULPI_VIEWPORT=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 1a3fb21bee5..514176dafc3 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -48,6 +48,7 @@ CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_ULPI_VIEWPORT=y diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 8a6f732894e..89580cc31f7 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -18,6 +18,12 @@ config USB_XHCI_UNIPHIER ---help--- Enables support for the on-chip xHCI controller on UniPhier SoCs. +config USB_XHCI_DWC3 + bool "DesignWare USB3 DRD Core Support" + help + Say Y or if your system has a Dual Role SuperSpeed + USB controller based on the DesignWare USB3 IP Core. + endif config USB_OHCI_GENERIC diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 170d069647e..361704bfd47 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -99,7 +99,6 @@ #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD) #define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 #define CONFIG_USB_HOST -#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 6a3d8e5aef9..2db199db33b 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -64,7 +64,6 @@ /* USB xHCI HOST */ #define CONFIG_USB_HOST -#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 51eac933928..50765408db7 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -62,7 +62,6 @@ /* USB support */ #define CONFIG_USB_HOST #define CONFIG_USB_XHCI_OMAP -#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_OMAP_USB_PHY diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 0571dc0e990..0d51aeb8690 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -211,7 +211,6 @@ /* USB xHCI HOST */ #define CONFIG_USB_HOST -#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index b2ff4dd9277..e614a7f5a69 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -157,7 +157,6 @@ /* USB */ #define CONFIG_USB_STORAGE -#define CONFIG_USB_XHCI_DWC3 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index ac322404c3e..1edf798e32d 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -450,7 +450,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL -#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index c38d680abeb..30f5655dcb8 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -57,7 +57,6 @@ #ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL -#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 103bb2ebb99..a19eaee5a9b 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -389,7 +389,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_HAS_FSL_XHCI_USB #ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL -#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 0a716370b68..94ddfb17976 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -279,7 +279,6 @@ #define CONFIG_HAS_FSL_XHCI_USB #ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL -#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 743473fec84..b44066c4073 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -384,7 +384,6 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL -#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 1fe4138a445..86a49a5cd8e 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -317,7 +317,6 @@ unsigned long get_board_sys_clk(void); */ #define CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL -#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 2292eb2e325..707106ffab8 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -191,7 +191,6 @@ "-(ubifs)" /* USB Configuration */ -#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_XHCI_KEYSTONE #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index b0e0c22be63..8a1142bd423 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -117,7 +117,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x8000000 #if defined(CONFIG_ZYNQMP_USB) -#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE -- cgit v1.3.1 From ea7d1eec66898b233ac49f8a60391b96afa25477 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 30 May 2016 13:57:53 -0500 Subject: mtd: nand: Remove docg4 driver and palmtreo680 flashing tool Commit ad4f54ea86b ("arm: Remove palmtreo680 board") removed the only user of the docg4 driver and the palmtreo680 image flashing tool. This patch removes them. Signed-off-by: Scott Wood Cc: Mike Dunn Cc: Simon Glass --- drivers/mtd/nand/Makefile | 2 - drivers/mtd/nand/docg4.c | 1030 -------------------------------------- drivers/mtd/nand/docg4_spl.c | 219 -------- include/linux/mtd/docg4.h | 132 ----- tools/palmtreo680/flash_u-boot.c | 177 ------- 5 files changed, 1560 deletions(-) delete mode 100644 drivers/mtd/nand/docg4.c delete mode 100644 drivers/mtd/nand/docg4_spl.c delete mode 100644 include/linux/mtd/docg4.h delete mode 100644 tools/palmtreo680/flash_u-boot.c (limited to 'include') diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index aea6a93b283..837d397bdaf 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -13,7 +13,6 @@ endif obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o -obj-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o @@ -67,7 +66,6 @@ obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o obj-$(CONFIG_NAND_PLAT) += nand_plat.o -obj-$(CONFIG_NAND_DOCG4) += docg4.o else # minimal SPL drivers diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c deleted file mode 100644 index c1c1ff876a7..00000000000 --- a/drivers/mtd/nand/docg4.c +++ /dev/null @@ -1,1030 +0,0 @@ -/* - * drivers/mtd/nand/docg4.c - * - * Copyright (C) 2013 Mike Dunn - * - * SPDX-License-Identifier: GPL-2.0+ - * - * mtd nand driver for M-Systems DiskOnChip G4 - * - * Tested on the Palm Treo 680. The G4 is also present on Toshiba Portege, Asus - * P526, some HTC smartphones (Wizard, Prophet, ...), O2 XDA Zinc, maybe others. - * Should work on these as well. Let me know! - * - * TODO: - * - * Mechanism for management of password-protected areas - * - * Hamming ecc when reading oob only - * - * According to the M-Sys documentation, this device is also available in a - * "dual-die" configuration having a 256MB capacity, but no mechanism for - * detecting this variant is documented. Currently this driver assumes 128MB - * capacity. - * - * Support for multiple cascaded devices ("floors"). Not sure which gadgets - * contain multiple G4s in a cascaded configuration, if any. - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * The device has a nop register which M-Sys claims is for the purpose of - * inserting precise delays. But beware; at least some operations fail if the - * nop writes are replaced with a generic delay! - */ -static inline void write_nop(void __iomem *docptr) -{ - writew(0, docptr + DOC_NOP); -} - - -static int poll_status(void __iomem *docptr) -{ - /* - * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL - * register. Operations known to take a long time (e.g., block erase) - * should sleep for a while before calling this. - */ - - uint8_t flash_status; - - /* hardware quirk requires reading twice initially */ - flash_status = readb(docptr + DOC_FLASHCONTROL); - - do { - flash_status = readb(docptr + DOC_FLASHCONTROL); - } while (!(flash_status & DOC_CTRL_FLASHREADY)); - - return 0; -} - -static void write_addr(void __iomem *docptr, uint32_t docg4_addr) -{ - /* write the four address bytes packed in docg4_addr to the device */ - - writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS); - docg4_addr >>= 8; - writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS); - docg4_addr >>= 8; - writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS); - docg4_addr >>= 8; - writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS); -} - -/* - * This is a module parameter in the linux kernel version of this driver. It is - * hard-coded to 'off' for u-boot. This driver uses oob to mark bad blocks. - * This can be problematic when dealing with data not intended for the mtd/nand - * subsystem. For example, on boards that boot from the docg4 and use the IPL - * to load an spl + u-boot image, the blocks containing the image will be - * reported as "bad" because the oob of the first page of each block contains a - * magic number that the IPL looks for, which causes the badblock scan to - * erroneously add them to the bad block table. To erase such a block, use - * u-boot's 'nand scrub'. scrub is safe for the docg4. The device does have a - * factory bad block table, but it is read-only, and is used in conjunction with - * oob bad block markers that are written by mtd/nand when a block is deemed to - * be bad. To read data from "bad" blocks, use 'read.raw'. Unfortunately, - * read.raw does not use ecc, which would still work fine on such misidentified - * bad blocks. TODO: u-boot nand utilities need the ability to ignore bad - * blocks. - */ -static const int ignore_badblocks; /* remains false */ - -struct docg4_priv { - int status; - struct { - unsigned int command; - int column; - int page; - } last_command; - uint8_t oob_buf[16]; - uint8_t ecc_buf[7]; - int oob_page; - struct bch_control *bch; -}; -/* - * Oob bytes 0 - 6 are available to the user. - * Byte 7 is hamming ecc for first 7 bytes. Bytes 8 - 14 are hw-generated ecc. - * Byte 15 (the last) is used by the driver as a "page written" flag. - */ -static struct nand_ecclayout docg4_oobinfo = { - .eccbytes = 9, - .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, - .oobavail = 7, - .oobfree = { {0, 7} } -}; - -static void reset(void __iomem *docptr) -{ - /* full device reset */ - - writew(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN, docptr + DOC_ASICMODE); - writew(~(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN), - docptr + DOC_ASICMODECONFIRM); - write_nop(docptr); - - writew(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN, - docptr + DOC_ASICMODE); - writew(~(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN), - docptr + DOC_ASICMODECONFIRM); - - writew(DOC_ECCCONF1_ECC_ENABLE, docptr + DOC_ECCCONF1); - - poll_status(docptr); -} - -static void docg4_select_chip(struct mtd_info *mtd, int chip) -{ - /* - * Select among multiple cascaded chips ("floors"). Multiple floors are - * not yet supported, so the only valid non-negative value is 0. - */ - void __iomem *docptr = CONFIG_SYS_NAND_BASE; - - if (chip < 0) - return; /* deselected */ - - if (chip > 0) - printf("multiple floors currently unsupported\n"); - - writew(0, docptr + DOC_DEVICESELECT); -} - -static void read_hw_ecc(void __iomem *docptr, uint8_t *ecc_buf) -{ - /* read the 7 hw-generated ecc bytes */ - - int i; - for (i = 0; i < 7; i++) { /* hw quirk; read twice */ - ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i)); - ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i)); - } -} - -static int correct_data(struct mtd_info *mtd, uint8_t *buf, int page) -{ - /* - * Called after a page read when hardware reports bitflips. - * Up to four bitflips can be corrected. - */ - - struct nand_chip *nand = mtd->priv; - struct docg4_priv *doc = nand->priv; - void __iomem *docptr = CONFIG_SYS_NAND_BASE; - int i, numerrs; - unsigned int errpos[4]; - const uint8_t blank_read_hwecc[8] = { - 0xcf, 0x72, 0xfc, 0x1b, 0xa9, 0xc7, 0xb9, 0 }; - - read_hw_ecc(docptr, doc->ecc_buf); /* read 7 hw-generated ecc bytes */ - - /* check if read error is due to a blank page */ - if (!memcmp(doc->ecc_buf, blank_read_hwecc, 7)) - return 0; /* yes */ - - /* skip additional check of "written flag" if ignore_badblocks */ - if (!ignore_badblocks) { - /* - * If the hw ecc bytes are not those of a blank page, there's - * still a chance that the page is blank, but was read with - * errors. Check the "written flag" in last oob byte, which - * is set to zero when a page is written. If more than half - * the bits are set, assume a blank page. Unfortunately, the - * bit flips(s) are not reported in stats. - */ - - if (doc->oob_buf[15]) { - int bit, numsetbits = 0; - unsigned long written_flag = doc->oob_buf[15]; - - for (bit = 0; bit < 8; bit++) { - if (written_flag & 0x01) - numsetbits++; - written_flag >>= 1; - } - if (numsetbits > 4) { /* assume blank */ - printf("errors in blank page at offset %08x\n", - page * DOCG4_PAGE_SIZE); - return 0; - } - } - } - - /* - * The hardware ecc unit produces oob_ecc ^ calc_ecc. The kernel's bch - * algorithm is used to decode this. However the hw operates on page - * data in a bit order that is the reverse of that of the bch alg, - * requiring that the bits be reversed on the result. Thanks to Ivan - * Djelic for his analysis! - */ - for (i = 0; i < 7; i++) - doc->ecc_buf[i] = bitrev8(doc->ecc_buf[i]); - - numerrs = decode_bch(doc->bch, NULL, DOCG4_USERDATA_LEN, NULL, - doc->ecc_buf, NULL, errpos); - - if (numerrs == -EBADMSG) { - printf("uncorrectable errors at offset %08x\n", - page * DOCG4_PAGE_SIZE); - return -EBADMSG; - } - - BUG_ON(numerrs < 0); /* -EINVAL, or anything other than -EBADMSG */ - - /* undo last step in BCH alg (modulo mirroring not needed) */ - for (i = 0; i < numerrs; i++) - errpos[i] = (errpos[i] & ~7)|(7-(errpos[i] & 7)); - - /* fix the errors */ - for (i = 0; i < numerrs; i++) { - /* ignore if error within oob ecc bytes */ - if (errpos[i] > DOCG4_USERDATA_LEN * 8) - continue; - - /* if error within oob area preceeding ecc bytes... */ - if (errpos[i] > DOCG4_PAGE_SIZE * 8) - __change_bit(errpos[i] - DOCG4_PAGE_SIZE * 8, - (unsigned long *)doc->oob_buf); - - else /* error in page data */ - __change_bit(errpos[i], (unsigned long *)buf); - } - - printf("%d error(s) corrected at offset %08x\n", - numerrs, page * DOCG4_PAGE_SIZE); - - return numerrs; -} - -static int read_progstatus(struct docg4_priv *doc, void __iomem *docptr) -{ - /* - * This apparently checks the status of programming. Done after an - * erasure, and after page data is written. On error, the status is - * saved, to be later retrieved by the nand infrastructure code. - */ - - /* status is read from the I/O reg */ - uint16_t status1 = readw(docptr + DOC_IOSPACE_DATA); - uint16_t status2 = readw(docptr + DOC_IOSPACE_DATA); - uint16_t status3 = readw(docptr + DOCG4_MYSTERY_REG); - - MTDDEBUG(MTD_DEBUG_LEVEL3, "docg4: %s: %02x %02x %02x\n", - __func__, status1, status2, status3); - - if (status1 != DOCG4_PROGSTATUS_GOOD || - status2 != DOCG4_PROGSTATUS_GOOD_2 || - status3 != DOCG4_PROGSTATUS_GOOD_2) { - doc->status = NAND_STATUS_FAIL; - printf("read_progstatus failed: %02x, %02x, %02x\n", - status1, status2, status3); - return -EIO; - } - return 0; -} - -static int pageprog(struct mtd_info *mtd) -{ - /* - * Final step in writing a page. Writes the contents of its - * internal buffer out to the flash array, or some such. - */ - - struct nand_chip *nand = mtd->priv; - struct docg4_priv *doc = nand->priv; - void __iomem *docptr = CONFIG_SYS_NAND_BASE; - int retval = 0; - - MTDDEBUG(MTD_DEBUG_LEVEL3, "docg4: %s\n", __func__); - - writew(DOCG4_SEQ_PAGEPROG, docptr + DOC_FLASHSEQUENCE); - writew(DOC_CMD_PROG_CYCLE2, docptr + DOC_FLASHCOMMAND); - write_nop(docptr); - write_nop(docptr); - - /* Just busy-wait; usleep_range() slows things down noticeably. */ - poll_status(docptr); - - writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE); - writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND); - writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - - retval = read_progstatus(doc, docptr); - writew(0, docptr + DOC_DATAEND); - write_nop(docptr); - poll_status(docptr); - write_nop(docptr); - - return retval; -} - -static void sequence_reset(void __iomem *docptr) -{ - /* common starting sequence for all operations */ - - writew(DOC_CTRL_UNKNOWN | DOC_CTRL_CE, docptr + DOC_FLASHCONTROL); - writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE); - writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND); - write_nop(docptr); - write_nop(docptr); - poll_status(docptr); - write_nop(docptr); -} - -static void read_page_prologue(void __iomem *docptr, uint32_t docg4_addr) -{ - /* first step in reading a page */ - - sequence_reset(docptr); - - writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE); - writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND); - write_nop(docptr); - - write_addr(docptr, docg4_addr); - - write_nop(docptr); - writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND); - write_nop(docptr); - write_nop(docptr); - - poll_status(docptr); -} - -static void write_page_prologue(void __iomem *docptr, uint32_t docg4_addr) -{ - /* first step in writing a page */ - - sequence_reset(docptr); - writew(DOCG4_SEQ_PAGEWRITE, docptr + DOC_FLASHSEQUENCE); - writew(DOCG4_CMD_PAGEWRITE, docptr + DOC_FLASHCOMMAND); - write_nop(docptr); - write_addr(docptr, docg4_addr); - write_nop(docptr); - write_nop(docptr); - poll_status(docptr); -} - -static uint32_t mtd_to_docg4_address(int page, int column) -{ - /* - * Convert mtd address to format used by the device, 32 bit packed. - * - * Some notes on G4 addressing... The M-Sys documentation on this device - * claims that pages are 2K in length, and indeed, the format of the - * address used by the device reflects that. But within each page are - * four 512 byte "sub-pages", each with its own oob data that is - * read/written immediately after the 512 bytes of page data. This oob - * data contains the ecc bytes for the preceeding 512 bytes. - * - * Rather than tell the mtd nand infrastructure that page size is 2k, - * with four sub-pages each, we engage in a little subterfuge and tell - * the infrastructure code that pages are 512 bytes in size. This is - * done because during the course of reverse-engineering the device, I - * never observed an instance where an entire 2K "page" was read or - * written as a unit. Each "sub-page" is always addressed individually, - * its data read/written, and ecc handled before the next "sub-page" is - * addressed. - * - * This requires us to convert addresses passed by the mtd nand - * infrastructure code to those used by the device. - * - * The address that is written to the device consists of four bytes: the - * first two are the 2k page number, and the second is the index into - * the page. The index is in terms of 16-bit half-words and includes - * the preceeding oob data, so e.g., the index into the second - * "sub-page" is 0x108, and the full device address of the start of mtd - * page 0x201 is 0x00800108. - */ - int g4_page = page / 4; /* device's 2K page */ - int g4_index = (page % 4) * 0x108 + column/2; /* offset into page */ - return (g4_page << 16) | g4_index; /* pack */ -} - -static void docg4_command(struct mtd_info *mtd, unsigned command, int column, - int page_addr) -{ - /* handle standard nand commands */ - - struct nand_chip *nand = mtd->priv; - struct docg4_priv *doc = nand->priv; - uint32_t g4_addr = mtd_to_docg4_address(page_addr, column); - - MTDDEBUG(MTD_DEBUG_LEVEL3, "%s %x, page_addr=%x, column=%x\n", - __func__, command, page_addr, column); - - /* - * Save the command and its arguments. This enables emulation of - * standard flash devices, and also some optimizations. - */ - doc->last_command.command = command; - doc->last_command.column = column; - doc->last_command.page = page_addr; - - switch (command) { - case NAND_CMD_RESET: - reset(CONFIG_SYS_NAND_BASE); - break; - - case NAND_CMD_READ0: - read_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr); - break; - - case NAND_CMD_STATUS: - /* next call to read_byte() will expect a status */ - break; - - case NAND_CMD_SEQIN: - write_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr); - - /* hack for deferred write of oob bytes */ - if (doc->oob_page == page_addr) - memcpy(nand->oob_poi, doc->oob_buf, 16); - break; - - case NAND_CMD_PAGEPROG: - pageprog(mtd); - break; - - /* we don't expect these, based on review of nand_base.c */ - case NAND_CMD_READOOB: - case NAND_CMD_READID: - case NAND_CMD_ERASE1: - case NAND_CMD_ERASE2: - printf("docg4_command: unexpected nand command 0x%x\n", - command); - break; - } -} - -static void docg4_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) -{ - int i; - struct nand_chip *nand = mtd->priv; - uint16_t *p = (uint16_t *)buf; - len >>= 1; - - for (i = 0; i < len; i++) - p[i] = readw(nand->IO_ADDR_R); -} - -static int docg4_read_oob(struct mtd_info *mtd, struct nand_chip *nand, - int page) -{ - struct docg4_priv *doc = nand->priv; - void __iomem *docptr = CONFIG_SYS_NAND_BASE; - uint16_t status; - - MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: page %x\n", __func__, page); - - /* - * Oob bytes are read as part of a normal page read. If the previous - * nand command was a read of the page whose oob is now being read, just - * copy the oob bytes that we saved in a local buffer and avoid a - * separate oob read. - */ - if (doc->last_command.command == NAND_CMD_READ0 && - doc->last_command.page == page) { - memcpy(nand->oob_poi, doc->oob_buf, 16); - return 0; - } - - /* - * Separate read of oob data only. - */ - docg4_command(mtd, NAND_CMD_READ0, nand->ecc.size, page); - - writew(DOC_ECCCONF0_READ_MODE | DOCG4_OOB_SIZE, docptr + DOC_ECCCONF0); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - - /* the 1st byte from the I/O reg is a status; the rest is oob data */ - status = readw(docptr + DOC_IOSPACE_DATA); - if (status & DOCG4_READ_ERROR) { - printf("docg4_read_oob failed: status = 0x%02x\n", status); - return -EIO; - } - - MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: status = 0x%x\n", __func__, status); - - docg4_read_buf(mtd, nand->oob_poi, 16); - - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - writew(0, docptr + DOC_DATAEND); - write_nop(docptr); - - return 0; -} - -static int docg4_write_oob(struct mtd_info *mtd, struct nand_chip *nand, - int page) -{ - /* - * Writing oob-only is not really supported, because MLC nand must write - * oob bytes at the same time as page data. Nonetheless, we save the - * oob buffer contents here, and then write it along with the page data - * if the same page is subsequently written. This allows user space - * utilities that write the oob data prior to the page data to work - * (e.g., nandwrite). The disdvantage is that, if the intention was to - * write oob only, the operation is quietly ignored. Also, oob can get - * corrupted if two concurrent processes are running nandwrite. - */ - - /* note that bytes 7..14 are hw generated hamming/ecc and overwritten */ - struct docg4_priv *doc = nand->priv; - doc->oob_page = page; - memcpy(doc->oob_buf, nand->oob_poi, 16); - return 0; -} - -static int docg4_block_neverbad(struct mtd_info *mtd, loff_t ofs, int getchip) -{ - /* only called when module_param ignore_badblocks is set */ - return 0; -} - -static void docg4_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - int i; - struct nand_chip *nand = mtd->priv; - uint16_t *p = (uint16_t *)buf; - len >>= 1; - - for (i = 0; i < len; i++) - writew(p[i], nand->IO_ADDR_W); -} - -static int write_page(struct mtd_info *mtd, struct nand_chip *nand, - const uint8_t *buf, int use_ecc) -{ - void __iomem *docptr = CONFIG_SYS_NAND_BASE; - uint8_t ecc_buf[8]; - - writew(DOC_ECCCONF0_ECC_ENABLE | - DOC_ECCCONF0_UNKNOWN | - DOCG4_BCH_SIZE, - docptr + DOC_ECCCONF0); - write_nop(docptr); - - /* write the page data */ - docg4_write_buf16(mtd, buf, DOCG4_PAGE_SIZE); - - /* oob bytes 0 through 5 are written to I/O reg */ - docg4_write_buf16(mtd, nand->oob_poi, 6); - - /* oob byte 6 written to a separate reg */ - writew(nand->oob_poi[6], docptr + DOCG4_OOB_6_7); - - write_nop(docptr); - write_nop(docptr); - - /* write hw-generated ecc bytes to oob */ - if (likely(use_ecc)) { - /* oob byte 7 is hamming code */ - uint8_t hamming = readb(docptr + DOC_HAMMINGPARITY); - hamming = readb(docptr + DOC_HAMMINGPARITY); /* 2nd read */ - writew(hamming, docptr + DOCG4_OOB_6_7); - write_nop(docptr); - - /* read the 7 bch bytes from ecc regs */ - read_hw_ecc(docptr, ecc_buf); - ecc_buf[7] = 0; /* clear the "page written" flag */ - } - - /* write user-supplied bytes to oob */ - else { - writew(nand->oob_poi[7], docptr + DOCG4_OOB_6_7); - write_nop(docptr); - memcpy(ecc_buf, &nand->oob_poi[8], 8); - } - - docg4_write_buf16(mtd, ecc_buf, 8); - write_nop(docptr); - write_nop(docptr); - writew(0, docptr + DOC_DATAEND); - write_nop(docptr); - - return 0; -} - -static int docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand, - const uint8_t *buf, int oob_required) -{ - return write_page(mtd, nand, buf, 0); -} - -static int docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand, - const uint8_t *buf, int oob_required) -{ - return write_page(mtd, nand, buf, 1); -} - -static int read_page(struct mtd_info *mtd, struct nand_chip *nand, - uint8_t *buf, int page, int use_ecc) -{ - struct docg4_priv *doc = nand->priv; - void __iomem *docptr = CONFIG_SYS_NAND_BASE; - uint16_t status, edc_err, *buf16; - - writew(DOC_ECCCONF0_READ_MODE | - DOC_ECCCONF0_ECC_ENABLE | - DOC_ECCCONF0_UNKNOWN | - DOCG4_BCH_SIZE, - docptr + DOC_ECCCONF0); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - - /* the 1st byte from the I/O reg is a status; the rest is page data */ - status = readw(docptr + DOC_IOSPACE_DATA); - if (status & DOCG4_READ_ERROR) { - printf("docg4_read_page: bad status: 0x%02x\n", status); - writew(0, docptr + DOC_DATAEND); - return -EIO; - } - - docg4_read_buf(mtd, buf, DOCG4_PAGE_SIZE); /* read the page data */ - - /* first 14 oob bytes read from I/O reg */ - docg4_read_buf(mtd, nand->oob_poi, 14); - - /* last 2 read from another reg */ - buf16 = (uint16_t *)(nand->oob_poi + 14); - *buf16 = readw(docptr + DOCG4_MYSTERY_REG); - - /* - * Diskonchips read oob immediately after a page read. Mtd - * infrastructure issues a separate command for reading oob after the - * page is read. So we save the oob bytes in a local buffer and just - * copy it if the next command reads oob from the same page. - */ - memcpy(doc->oob_buf, nand->oob_poi, 16); - - write_nop(docptr); - - if (likely(use_ecc)) { - /* read the register that tells us if bitflip(s) detected */ - edc_err = readw(docptr + DOC_ECCCONF1); - edc_err = readw(docptr + DOC_ECCCONF1); - - /* If bitflips are reported, attempt to correct with ecc */ - if (edc_err & DOC_ECCCONF1_BCH_SYNDROM_ERR) { - int bits_corrected = correct_data(mtd, buf, page); - if (bits_corrected == -EBADMSG) - mtd->ecc_stats.failed++; - else - mtd->ecc_stats.corrected += bits_corrected; - } - } - - writew(0, docptr + DOC_DATAEND); - return 0; -} - - -static int docg4_read_page_raw(struct mtd_info *mtd, struct nand_chip *nand, - uint8_t *buf, int oob_required, int page) -{ - return read_page(mtd, nand, buf, page, 0); -} - -static int docg4_read_page(struct mtd_info *mtd, struct nand_chip *nand, - uint8_t *buf, int oob_required, int page) -{ - return read_page(mtd, nand, buf, page, 1); -} - -static int docg4_erase_block(struct mtd_info *mtd, int page) -{ - struct nand_chip *nand = mtd->priv; - struct docg4_priv *doc = nand->priv; - void __iomem *docptr = CONFIG_SYS_NAND_BASE; - uint16_t g4_page; - - MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: page %04x\n", __func__, page); - - sequence_reset(docptr); - - writew(DOCG4_SEQ_BLOCKERASE, docptr + DOC_FLASHSEQUENCE); - writew(DOC_CMD_PROG_BLOCK_ADDR, docptr + DOC_FLASHCOMMAND); - write_nop(docptr); - - /* only 2 bytes of address are written to specify erase block */ - g4_page = (uint16_t)(page / 4); /* to g4's 2k page addressing */ - writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS); - g4_page >>= 8; - writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS); - write_nop(docptr); - - /* start the erasure */ - writew(DOC_CMD_ERASECYCLE2, docptr + DOC_FLASHCOMMAND); - write_nop(docptr); - write_nop(docptr); - - poll_status(docptr); - writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE); - writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND); - writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - - read_progstatus(doc, docptr); - - writew(0, docptr + DOC_DATAEND); - write_nop(docptr); - poll_status(docptr); - write_nop(docptr); - - return nand->waitfunc(mtd, nand); -} - -static int read_factory_bbt(struct mtd_info *mtd) -{ - /* - * The device contains a read-only factory bad block table. Read it and - * update the memory-based bbt accordingly. - */ - - struct nand_chip *nand = mtd->priv; - uint32_t g4_addr = mtd_to_docg4_address(DOCG4_FACTORY_BBT_PAGE, 0); - uint8_t *buf; - int i, block, status; - - buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL); - if (buf == NULL) - return -ENOMEM; - - read_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr); - status = docg4_read_page(mtd, nand, buf, 0, DOCG4_FACTORY_BBT_PAGE); - if (status) - goto exit; - - /* - * If no memory-based bbt was created, exit. This will happen if module - * parameter ignore_badblocks is set. Then why even call this function? - * For an unknown reason, block erase always fails if it's the first - * operation after device power-up. The above read ensures it never is. - * Ugly, I know. - */ - if (nand->bbt == NULL) /* no memory-based bbt */ - goto exit; - - /* - * Parse factory bbt and update memory-based bbt. Factory bbt format is - * simple: one bit per block, block numbers increase left to right (msb - * to lsb). Bit clear means bad block. - */ - for (i = block = 0; block < DOCG4_NUMBLOCKS; block += 8, i++) { - int bitnum; - uint8_t mask; - for (bitnum = 0, mask = 0x80; - bitnum < 8; bitnum++, mask >>= 1) { - if (!(buf[i] & mask)) { - int badblock = block + bitnum; - nand->bbt[badblock / 4] |= - 0x03 << ((badblock % 4) * 2); - mtd->ecc_stats.badblocks++; - printf("factory-marked bad block: %d\n", - badblock); - } - } - } - exit: - kfree(buf); - return status; -} - -static int docg4_block_markbad(struct mtd_info *mtd, loff_t ofs) -{ - /* - * Mark a block as bad. Bad blocks are marked in the oob area of the - * first page of the block. The default scan_bbt() in the nand - * infrastructure code works fine for building the memory-based bbt - * during initialization, as does the nand infrastructure function that - * checks if a block is bad by reading the bbt. This function replaces - * the nand default because writes to oob-only are not supported. - */ - - int ret, i; - uint8_t *buf; - struct nand_chip *nand = mtd->priv; - struct nand_bbt_descr *bbtd = nand->badblock_pattern; - int block = (int)(ofs >> nand->bbt_erase_shift); - int page = (int)(ofs >> nand->page_shift); - uint32_t g4_addr = mtd_to_docg4_address(page, 0); - - MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: %08llx\n", __func__, ofs); - - if (unlikely(ofs & (DOCG4_BLOCK_SIZE - 1))) - printf("%s: ofs %llx not start of block!\n", - __func__, ofs); - - /* allocate blank buffer for page data */ - buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL); - if (buf == NULL) - return -ENOMEM; - - /* update bbt in memory */ - nand->bbt[block / 4] |= 0x01 << ((block & 0x03) * 2); - - /* write bit-wise negation of pattern to oob buffer */ - memset(nand->oob_poi, 0xff, mtd->oobsize); - for (i = 0; i < bbtd->len; i++) - nand->oob_poi[bbtd->offs + i] = ~bbtd->pattern[i]; - - /* write first page of block */ - write_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr); - docg4_write_page(mtd, nand, buf, 1); - ret = pageprog(mtd); - if (!ret) - mtd->ecc_stats.badblocks++; - - kfree(buf); - - return ret; -} - -static uint8_t docg4_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *nand = mtd->priv; - struct docg4_priv *doc = nand->priv; - - MTDDEBUG(MTD_DEBUG_LEVEL3, "%s\n", __func__); - - if (doc->last_command.command == NAND_CMD_STATUS) { - int status; - - /* - * Previous nand command was status request, so nand - * infrastructure code expects to read the status here. If an - * error occurred in a previous operation, report it. - */ - doc->last_command.command = 0; - - if (doc->status) { - status = doc->status; - doc->status = 0; - } - - /* why is NAND_STATUS_WP inverse logic?? */ - else - status = NAND_STATUS_WP | NAND_STATUS_READY; - - return status; - } - - printf("unexpectd call to read_byte()\n"); - - return 0; -} - -static int docg4_wait(struct mtd_info *mtd, struct nand_chip *nand) -{ - struct docg4_priv *doc = nand->priv; - int status = NAND_STATUS_WP; /* inverse logic?? */ - MTDDEBUG(MTD_DEBUG_LEVEL3, "%s...\n", __func__); - - /* report any previously unreported error */ - if (doc->status) { - status |= doc->status; - doc->status = 0; - return status; - } - - status |= poll_status(CONFIG_SYS_NAND_BASE); - return status; -} - -int docg4_nand_init(struct mtd_info *mtd, struct nand_chip *nand, int devnum) -{ - uint16_t id1, id2; - struct docg4_priv *docg4; - int retval; - - docg4 = kzalloc(sizeof(*docg4), GFP_KERNEL); - if (!docg4) - return -1; - - mtd->priv = nand; - nand->priv = docg4; - - /* These must be initialized here because the docg4 is non-standard - * and doesn't produce an id that the nand code can use to look up - * these values (nand_scan_ident() not called). - */ - mtd->size = DOCG4_CHIP_SIZE; - mtd->name = "Msys_Diskonchip_G4"; - mtd->writesize = DOCG4_PAGE_SIZE; - mtd->erasesize = DOCG4_BLOCK_SIZE; - mtd->oobsize = DOCG4_OOB_SIZE; - - nand->IO_ADDR_R = - (void __iomem *)CONFIG_SYS_NAND_BASE + DOC_IOSPACE_DATA; - nand->IO_ADDR_W = nand->IO_ADDR_R; - nand->chipsize = DOCG4_CHIP_SIZE; - nand->chip_shift = DOCG4_CHIP_SHIFT; - nand->bbt_erase_shift = DOCG4_ERASE_SHIFT; - nand->phys_erase_shift = DOCG4_ERASE_SHIFT; - nand->chip_delay = 20; - nand->page_shift = DOCG4_PAGE_SHIFT; - nand->pagemask = 0x3ffff; - nand->badblockpos = NAND_LARGE_BADBLOCK_POS; - nand->badblockbits = 8; - nand->ecc.layout = &docg4_oobinfo; - nand->ecc.mode = NAND_ECC_HW_SYNDROME; - nand->ecc.size = DOCG4_PAGE_SIZE; - nand->ecc.prepad = 8; - nand->ecc.bytes = 8; - nand->ecc.strength = DOCG4_T; - nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE; - nand->controller = &nand->hwcontrol; - - /* methods */ - nand->cmdfunc = docg4_command; - nand->waitfunc = docg4_wait; - nand->select_chip = docg4_select_chip; - nand->read_byte = docg4_read_byte; - nand->block_markbad = docg4_block_markbad; - nand->read_buf = docg4_read_buf; - nand->write_buf = docg4_write_buf16; - nand->scan_bbt = nand_default_bbt; - nand->erase = docg4_erase_block; - nand->ecc.read_page = docg4_read_page; - nand->ecc.write_page = docg4_write_page; - nand->ecc.read_page_raw = docg4_read_page_raw; - nand->ecc.write_page_raw = docg4_write_page_raw; - nand->ecc.read_oob = docg4_read_oob; - nand->ecc.write_oob = docg4_write_oob; - - /* - * The way the nand infrastructure code is written, a memory-based bbt - * is not created if NAND_SKIP_BBTSCAN is set. With no memory bbt, - * nand->block_bad() is used. So when ignoring bad blocks, we skip the - * scan and define a dummy block_bad() which always returns 0. - */ - if (ignore_badblocks) { - nand->options |= NAND_SKIP_BBTSCAN; - nand->block_bad = docg4_block_neverbad; - } - - reset(CONFIG_SYS_NAND_BASE); - - /* check for presence of g4 chip by reading id registers */ - id1 = readw(CONFIG_SYS_NAND_BASE + DOC_CHIPID); - id1 = readw(CONFIG_SYS_NAND_BASE + DOCG4_MYSTERY_REG); - id2 = readw(CONFIG_SYS_NAND_BASE + DOC_CHIPID_INV); - id2 = readw(CONFIG_SYS_NAND_BASE + DOCG4_MYSTERY_REG); - if (id1 != DOCG4_IDREG1_VALUE || id2 != DOCG4_IDREG2_VALUE) - return -1; - - /* initialize bch algorithm */ - docg4->bch = init_bch(DOCG4_M, DOCG4_T, DOCG4_PRIMITIVE_POLY); - if (docg4->bch == NULL) - return -1; - - retval = nand_scan_tail(mtd); - if (retval) - return -1; - - /* - * Scan for bad blocks and create bbt here, then add the factory-marked - * bad blocks to the bbt. - */ - nand->scan_bbt(mtd); - nand->options |= NAND_BBT_SCANNED; - retval = read_factory_bbt(mtd); - if (retval) - return -1; - - retval = nand_register(devnum); - if (retval) - return -1; - - return 0; -} diff --git a/drivers/mtd/nand/docg4_spl.c b/drivers/mtd/nand/docg4_spl.c deleted file mode 100644 index 351b75a090e..00000000000 --- a/drivers/mtd/nand/docg4_spl.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * SPL driver for Diskonchip G4 nand flash - * - * Copyright (C) 2013 Mike Dunn - * - * SPDX-License-Identifier: GPL-2.0+ - * - * This driver basically mimics the load functionality of a typical IPL (initial - * program loader) resident in the 2k NOR-like region of the docg4 that is - * mapped to the reset vector. It allows the u-boot SPL to continue loading if - * the IPL loads a fixed number of flash blocks that is insufficient to contain - * the entire u-boot image. In this case, a concatenated spl + u-boot image is - * written at the flash offset from which the IPL loads an image, and when the - * IPL jumps to the SPL, the SPL resumes loading where the IPL left off. See - * the palmtreo680 for an example. - * - * This driver assumes that the data was written to the flash using the device's - * "reliable" mode, and also assumes that each 512 byte page is stored - * redundantly in the subsequent page. This storage format is likely to be used - * by all boards that boot from the docg4. The format compensates for the lack - * of ecc in the IPL. - * - * Reliable mode reduces the capacity of a block by half, and the redundant - * pages reduce it by half again. As a result, the normal 256k capacity of a - * block is reduced to 64k for the purposes of the IPL/SPL. - */ - -#include -#include - -/* forward declarations */ -static inline void write_nop(void __iomem *docptr); -static int poll_status(void __iomem *docptr); -static void write_addr(void __iomem *docptr, uint32_t docg4_addr); -static void address_sequence(unsigned int g4_page, unsigned int g4_index, - void __iomem *docptr); -static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr); - -int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) -{ - void *load_addr = dst; - uint32_t flash_offset = offs; - const unsigned int block_count = - (size + DOCG4_BLOCK_CAPACITY_SPL - 1) - / DOCG4_BLOCK_CAPACITY_SPL; - int i; - - for (i = 0; i < block_count; i++) { - int ret = docg4_load_block_reliable(flash_offset, load_addr); - if (ret) - return ret; - load_addr += DOCG4_BLOCK_CAPACITY_SPL; - flash_offset += DOCG4_BLOCK_SIZE; - } - return 0; -} - -static inline void write_nop(void __iomem *docptr) -{ - writew(0, docptr + DOC_NOP); -} - -static int poll_status(void __iomem *docptr) -{ - /* - * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL - * register. Operations known to take a long time (e.g., block erase) - * should sleep for a while before calling this. - */ - - uint8_t flash_status; - - /* hardware quirk requires reading twice initially */ - flash_status = readb(docptr + DOC_FLASHCONTROL); - - do { - flash_status = readb(docptr + DOC_FLASHCONTROL); - } while (!(flash_status & DOC_CTRL_FLASHREADY)); - - return 0; -} - -static void write_addr(void __iomem *docptr, uint32_t docg4_addr) -{ - /* write the four address bytes packed in docg4_addr to the device */ - - writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS); - docg4_addr >>= 8; - writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS); - docg4_addr >>= 8; - writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS); - docg4_addr >>= 8; - writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS); -} - -static void address_sequence(unsigned int g4_page, unsigned int g4_index, - void __iomem *docptr) -{ - writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE); - writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND); - write_nop(docptr); - write_addr(docptr, ((uint32_t)g4_page << 16) | g4_index); - write_nop(docptr); -} - -static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr) -{ - void __iomem *docptr = (void *)CONFIG_SYS_NAND_BASE; - unsigned int g4_page = flash_offset >> 11; /* 2k page */ - const unsigned int last_g4_page = g4_page + 0x80; /* last in block */ - int g4_index = 0; - uint16_t flash_status; - uint16_t *buf; - - /* flash_offset must be aligned to the start of a block */ - if (flash_offset & 0x3ffff) - return -1; - - writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE); - writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND); - write_nop(docptr); - write_nop(docptr); - poll_status(docptr); - write_nop(docptr); - writew(0x45, docptr + DOC_FLASHSEQUENCE); - writew(0xa3, docptr + DOC_FLASHCOMMAND); - write_nop(docptr); - writew(0x22, docptr + DOC_FLASHCOMMAND); - write_nop(docptr); - - /* read 1st 4 oob bytes of first subpage of block */ - address_sequence(g4_page, 0x0100, docptr); /* index at oob */ - write_nop(docptr); - flash_status = readw(docptr + DOC_FLASHCONTROL); - flash_status = readw(docptr + DOC_FLASHCONTROL); - if (flash_status & 0x06) /* sequence or protection errors */ - return -1; - writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND); - write_nop(docptr); - write_nop(docptr); - poll_status(docptr); - writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - - /* - * Here we read the first four oob bytes of the first page of the block. - * The IPL on the palmtreo680 requires that this contain a 32 bit magic - * number, or the load aborts. We'll ignore it. - */ - readw(docptr + 0x103c); /* hw quirk; 1st read discarded */ - readw(docptr + 0x103c); /* lower 16 bits of magic number */ - readw(docptr + DOCG4_MYSTERY_REG); /* upper 16 bits of magic number */ - writew(0, docptr + DOC_DATAEND); - write_nop(docptr); - write_nop(docptr); - - /* load contents of block to memory */ - buf = (uint16_t *)dest_addr; - do { - int i; - - address_sequence(g4_page, g4_index, docptr); - writew(DOCG4_CMD_READ2, - docptr + DOC_FLASHCOMMAND); - write_nop(docptr); - write_nop(docptr); - poll_status(docptr); - writew(DOC_ECCCONF0_READ_MODE | - DOC_ECCCONF0_ECC_ENABLE | - DOCG4_BCH_SIZE, - docptr + DOC_ECCCONF0); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - write_nop(docptr); - - /* read the 512 bytes of page data, 2 bytes at a time */ - readw(docptr + 0x103c); /* hw quirk */ - for (i = 0; i < 256; i++) - *buf++ = readw(docptr + 0x103c); - - /* read oob, but discard it */ - for (i = 0; i < 7; i++) - readw(docptr + 0x103c); - readw(docptr + DOCG4_OOB_6_7); - readw(docptr + DOCG4_OOB_6_7); - - writew(0, docptr + DOC_DATAEND); - write_nop(docptr); - write_nop(docptr); - - if (!(g4_index & 0x100)) { - /* not redundant subpage read; check for ecc error */ - write_nop(docptr); - flash_status = readw(docptr + DOC_ECCCONF1); - flash_status = readw(docptr + DOC_ECCCONF1); - if (flash_status & 0x80) { /* ecc error */ - g4_index += 0x108; /* read redundant subpage */ - buf -= 256; /* back up ram ptr */ - continue; - } else /* no ecc error */ - g4_index += 0x210; /* skip redundant subpage */ - } else /* redundant page was just read; skip ecc error check */ - g4_index += 0x108; - - if (g4_index == 0x420) { /* finished with 2k page */ - g4_index = 0; - g4_page += 2; /* odd-numbered 2k pages skipped */ - } - - } while (g4_page != last_g4_page); /* while still on same block */ - - return 0; -} diff --git a/include/linux/mtd/docg4.h b/include/linux/mtd/docg4.h deleted file mode 100644 index 741fc0db46e..00000000000 --- a/include/linux/mtd/docg4.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (C) 2013 Mike Dunn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __DOCG4_H__ -#define __DOCG4_H__ - -#include -#include - -extern int docg4_nand_init(struct mtd_info *mtd, - struct nand_chip *nand, int devnum); - -/* SPL-related definitions */ -#define DOCG4_IPL_LOAD_BLOCK_COUNT 2 /* number of blocks that IPL loads */ -#define DOCG4_BLOCK_CAPACITY_SPL 0x10000 /* reliable mode; redundant pages */ - -#define DOC_IOSPACE_DATA 0x0800 - -/* register offsets */ -#define DOC_CHIPID 0x1000 -#define DOC_DEVICESELECT 0x100a -#define DOC_ASICMODE 0x100c -#define DOC_DATAEND 0x101e -#define DOC_NOP 0x103e - -#define DOC_FLASHSEQUENCE 0x1032 -#define DOC_FLASHCOMMAND 0x1034 -#define DOC_FLASHADDRESS 0x1036 -#define DOC_FLASHCONTROL 0x1038 -#define DOC_ECCCONF0 0x1040 -#define DOC_ECCCONF1 0x1042 -#define DOC_HAMMINGPARITY 0x1046 -#define DOC_BCH_SYNDROM(idx) (0x1048 + idx) - -#define DOC_ASICMODECONFIRM 0x1072 -#define DOC_CHIPID_INV 0x1074 -#define DOC_POWERMODE 0x107c - -#define DOCG4_MYSTERY_REG 0x1050 - -/* apparently used only to write oob bytes 6 and 7 */ -#define DOCG4_OOB_6_7 0x1052 - -/* DOC_FLASHSEQUENCE register commands */ -#define DOC_SEQ_RESET 0x00 -#define DOCG4_SEQ_PAGE_READ 0x03 -#define DOCG4_SEQ_FLUSH 0x29 -#define DOCG4_SEQ_PAGEWRITE 0x16 -#define DOCG4_SEQ_PAGEPROG 0x1e -#define DOCG4_SEQ_BLOCKERASE 0x24 - -/* DOC_FLASHCOMMAND register commands */ -#define DOCG4_CMD_PAGE_READ 0x00 -#define DOC_CMD_ERASECYCLE2 0xd0 -#define DOCG4_CMD_FLUSH 0x70 -#define DOCG4_CMD_READ2 0x30 -#define DOC_CMD_PROG_BLOCK_ADDR 0x60 -#define DOCG4_CMD_PAGEWRITE 0x80 -#define DOC_CMD_PROG_CYCLE2 0x10 -#define DOC_CMD_RESET 0xff - -/* DOC_POWERMODE register bits */ -#define DOC_POWERDOWN_READY 0x80 - -/* DOC_FLASHCONTROL register bits */ -#define DOC_CTRL_CE 0x10 -#define DOC_CTRL_UNKNOWN 0x40 -#define DOC_CTRL_FLASHREADY 0x01 - -/* DOC_ECCCONF0 register bits */ -#define DOC_ECCCONF0_READ_MODE 0x8000 -#define DOC_ECCCONF0_UNKNOWN 0x2000 -#define DOC_ECCCONF0_ECC_ENABLE 0x1000 -#define DOC_ECCCONF0_DATA_BYTES_MASK 0x07ff - -/* DOC_ECCCONF1 register bits */ -#define DOC_ECCCONF1_BCH_SYNDROM_ERR 0x80 -#define DOC_ECCCONF1_ECC_ENABLE 0x07 -#define DOC_ECCCONF1_PAGE_IS_WRITTEN 0x20 - -/* DOC_ASICMODE register bits */ -#define DOC_ASICMODE_RESET 0x00 -#define DOC_ASICMODE_NORMAL 0x01 -#define DOC_ASICMODE_POWERDOWN 0x02 -#define DOC_ASICMODE_MDWREN 0x04 -#define DOC_ASICMODE_BDETCT_RESET 0x08 -#define DOC_ASICMODE_RSTIN_RESET 0x10 -#define DOC_ASICMODE_RAM_WE 0x20 - -/* good status values read after read/write/erase operations */ -#define DOCG4_PROGSTATUS_GOOD 0x51 -#define DOCG4_PROGSTATUS_GOOD_2 0xe0 - -/* - * On read operations (page and oob-only), the first byte read from I/O reg is a - * status. On error, it reads 0x73; otherwise, it reads either 0x71 (first read - * after reset only) or 0x51, so bit 1 is presumed to be an error indicator. - */ -#define DOCG4_READ_ERROR 0x02 /* bit 1 indicates read error */ - -/* anatomy of the device */ -#define DOCG4_CHIP_SIZE 0x8000000 -#define DOCG4_PAGE_SIZE 0x200 -#define DOCG4_PAGES_PER_BLOCK 0x200 -#define DOCG4_BLOCK_SIZE (DOCG4_PAGES_PER_BLOCK * DOCG4_PAGE_SIZE) -#define DOCG4_NUMBLOCKS (DOCG4_CHIP_SIZE / DOCG4_BLOCK_SIZE) -#define DOCG4_OOB_SIZE 0x10 -#define DOCG4_CHIP_SHIFT 27 /* log_2(DOCG4_CHIP_SIZE) */ -#define DOCG4_PAGE_SHIFT 9 /* log_2(DOCG4_PAGE_SIZE) */ -#define DOCG4_ERASE_SHIFT 18 /* log_2(DOCG4_BLOCK_SIZE) */ - -/* all but the last byte is included in ecc calculation */ -#define DOCG4_BCH_SIZE (DOCG4_PAGE_SIZE + DOCG4_OOB_SIZE - 1) - -#define DOCG4_USERDATA_LEN 520 /* 512 byte page plus 8 oob avail to user */ - -/* expected values from the ID registers */ -#define DOCG4_IDREG1_VALUE 0x0400 -#define DOCG4_IDREG2_VALUE 0xfbff - -/* primitive polynomial used to build the Galois field used by hw ecc gen */ -#define DOCG4_PRIMITIVE_POLY 0x4443 - -#define DOCG4_M 14 /* Galois field is of order 2^14 */ -#define DOCG4_T 4 /* BCH alg corrects up to 4 bit errors */ - -#define DOCG4_FACTORY_BBT_PAGE 16 /* page where read-only factory bbt lives */ - -#endif /* __DOCG4_H__ */ diff --git a/tools/palmtreo680/flash_u-boot.c b/tools/palmtreo680/flash_u-boot.c deleted file mode 100644 index 832d3fef7b8..00000000000 --- a/tools/palmtreo680/flash_u-boot.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (C) 2013 Mike Dunn - * - * This file is released under the terms of GPL v2 and any later version. - * See the file COPYING in the root directory of the source tree for details. - * - * - * This is a userspace Linux utility that, when run on the Treo 680, will - * program u-boot to flash. The docg4 driver *must* be loaded with the - * reliable_mode and ignore_badblocks parameters enabled: - * - * modprobe docg4 ignore_badblocks=1 reliable_mode=1 - * - * This utility writes the concatenated spl + u-boot image to the start of the - * mtd device in the format expected by the IPL/SPL. The image file and mtd - * device node are passed to the utility as arguments. The blocks must have - * been erased beforehand. - * - * When you compile this, note that it links to libmtd from mtd-utils, so ensure - * that your include and lib paths include this. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "libmtd.h" - -#define RELIABLE_BLOCKSIZE 0x10000 /* block capacity in reliable mode */ -#define STANDARD_BLOCKSIZE 0x40000 /* block capacity in normal mode */ -#define PAGESIZE 512 -#define PAGES_PER_BLOCK 512 -#define OOBSIZE 7 /* available to user (16 total) */ - -uint8_t ff_oob[OOBSIZE] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - -/* this is the magic number the IPL looks for (ASCII "BIPO") */ -uint8_t page0_oob[OOBSIZE] = {'B', 'I', 'P', 'O', 0xff, 0xff, 0xff}; - -int main(int argc, char * const argv[]) -{ - int devfd, datafd, num_blocks, block; - off_t file_size; - libmtd_t mtd_desc; - struct mtd_dev_info devinfo; - uint8_t *blockbuf; - char response[8]; - - if (argc != 3) { - printf("usage: %s \n", argv[0]); - return -EINVAL; - } - - mtd_desc = libmtd_open(); - if (mtd_desc == NULL) { - int errsv = errno; - fprintf(stderr, "can't initialize libmtd\n"); - return -errsv; - } - - /* open the spl image file and mtd device */ - datafd = open(argv[1], O_RDONLY); - if (datafd == -1) { - int errsv = errno; - perror(argv[1]); - return -errsv; - } - devfd = open(argv[2], O_WRONLY); - if (devfd == -1) { - int errsv = errno; - perror(argv[2]); - return -errsv; - } - if (mtd_get_dev_info(mtd_desc, argv[2], &devinfo) < 0) { - int errsv = errno; - perror(argv[2]); - return -errsv; - } - - /* determine the number of blocks needed by the image */ - file_size = lseek(datafd, 0, SEEK_END); - if (file_size == (off_t)-1) { - int errsv = errno; - perror("lseek"); - return -errsv; - } - num_blocks = (file_size + RELIABLE_BLOCKSIZE - 1) / RELIABLE_BLOCKSIZE; - file_size = lseek(datafd, 0, SEEK_SET); - if (file_size == (off_t)-1) { - int errsv = errno; - perror("lseek"); - return -errsv; - } - printf("The mtd partition contains %d blocks\n", devinfo.eb_cnt); - printf("U-Boot will occupy %d blocks\n", num_blocks); - if (num_blocks > devinfo.eb_cnt) { - fprintf(stderr, "Insufficient blocks on partition\n"); - return -EINVAL; - } - - printf("IMPORTANT: These blocks must be in an erased state!\n"); - printf("Do you want to proceed?\n"); - scanf("%s", response); - if ((response[0] != 'y') && (response[0] != 'Y')) { - printf("Exiting\n"); - close(devfd); - close(datafd); - return 0; - } - - blockbuf = calloc(RELIABLE_BLOCKSIZE, 1); - if (blockbuf == NULL) { - int errsv = errno; - perror("calloc"); - return -errsv; - } - - for (block = 0; block < num_blocks; block++) { - int ofs, page; - uint8_t *pagebuf = blockbuf, *buf = blockbuf; - uint8_t *oobbuf = page0_oob; /* magic num in oob of 1st page */ - size_t len = RELIABLE_BLOCKSIZE; - int ret; - - /* read data for one block from file */ - while (len) { - ssize_t read_ret = read(datafd, buf, len); - if (read_ret == -1) { - int errsv = errno; - if (errno == EINTR) - continue; - perror("read"); - return -errsv; - } else if (read_ret == 0) { - break; /* EOF */ - } - len -= read_ret; - buf += read_ret; - } - - printf("Block %d: writing\r", block + 1); - fflush(stdout); - - for (page = 0, ofs = 0; - page < PAGES_PER_BLOCK; - page++, ofs += PAGESIZE) { - if (page & 0x04) /* Odd-numbered 2k page */ - continue; /* skipped in reliable mode */ - - ret = mtd_write(mtd_desc, &devinfo, devfd, block, ofs, - pagebuf, PAGESIZE, oobbuf, OOBSIZE, - MTD_OPS_PLACE_OOB); - if (ret) { - fprintf(stderr, - "\nmtd_write returned %d on block %d, ofs %x\n", - ret, block + 1, ofs); - return -EIO; - } - oobbuf = ff_oob; /* oob for subsequent pages */ - - if (page & 0x01) /* odd-numbered subpage */ - pagebuf += PAGESIZE; - } - } - - printf("\nDone\n"); - - close(devfd); - close(datafd); - free(blockbuf); - return 0; -} -- cgit v1.3.1 From 151c06ec61d74b77cf27d6d622bab6370c949c66 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 30 May 2016 13:57:54 -0500 Subject: mtd: nand: Remove nand_info_t typedef This typedef serves no purpose other than causing confusion with struct nand_chip. Signed-off-by: Scott Wood --- cmd/bootm.c | 30 +++---- cmd/jffs2.c | 6 +- cmd/nand.c | 161 ++++++++++++++++++----------------- common/env_nand.c | 6 +- common/fb_nand.c | 32 +++---- drivers/dfu/dfu_nand.c | 20 ++--- drivers/mtd/nand/am335x_spl_bch.c | 2 +- drivers/mtd/nand/atmel_nand.c | 2 +- drivers/mtd/nand/mxs_nand_spl.c | 2 +- drivers/mtd/nand/nand.c | 2 +- drivers/mtd/nand/nand_spl_simple.c | 2 +- drivers/mtd/nand/nand_util.c | 170 ++++++++++++++++++------------------- fs/jffs2/jffs2_nand_1pass.c | 24 +++--- fs/yaffs2/yaffs_uboot_glue.c | 2 +- include/nand.h | 39 ++++----- 15 files changed, 251 insertions(+), 249 deletions(-) (limited to 'include') diff --git a/cmd/bootm.c b/cmd/bootm.c index ee3b460adb0..24f1054f34b 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -372,8 +372,8 @@ next_bank: ; #endif #if defined(CONFIG_CMD_IMLS_NAND) -static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev, loff_t off, - size_t len) +static int nand_imls_legacyimage(struct mtd_info *mtd, int nand_dev, + loff_t off, size_t len) { void *imgdata; int ret; @@ -386,8 +386,7 @@ static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev, loff_t off, return -ENOMEM; } - ret = nand_read_skip_bad(nand, off, &len, - imgdata); + ret = nand_read_skip_bad(mtd, off, &len, imgdata); if (ret < 0 && ret != -EUCLEAN) { free(imgdata); return ret; @@ -413,8 +412,8 @@ static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev, loff_t off, return 0; } -static int nand_imls_fitimage(nand_info_t *nand, int nand_dev, loff_t off, - size_t len) +static int nand_imls_fitimage(struct mtd_info *mtd, int nand_dev, loff_t off, + size_t len) { void *imgdata; int ret; @@ -427,8 +426,7 @@ static int nand_imls_fitimage(nand_info_t *nand, int nand_dev, loff_t off, return -ENOMEM; } - ret = nand_read_skip_bad(nand, off, &len, - imgdata); + ret = nand_read_skip_bad(mtd, off, &len, imgdata); if (ret < 0 && ret != -EUCLEAN) { free(imgdata); return ret; @@ -449,7 +447,7 @@ static int nand_imls_fitimage(nand_info_t *nand, int nand_dev, loff_t off, static int do_imls_nand(void) { - nand_info_t *nand; + struct mtd_info *mtd; int nand_dev = nand_curr_device; size_t len; loff_t off; @@ -463,20 +461,20 @@ static int do_imls_nand(void) printf("\n"); for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) { - nand = &nand_info[nand_dev]; - if (!nand->name || !nand->size) + mtd = &nand_info[nand_dev]; + if (!mtd->name || !mtd->size) continue; - for (off = 0; off < nand->size; off += nand->erasesize) { + for (off = 0; off < mtd->size; off += mtd->erasesize) { const image_header_t *header; int ret; - if (nand_block_isbad(nand, off)) + if (nand_block_isbad(mtd, off)) continue; len = sizeof(buffer); - ret = nand_read(nand, off, &len, (u8 *)buffer); + ret = nand_read(mtd, off, &len, (u8 *)buffer); if (ret < 0 && ret != -EUCLEAN) { printf("NAND read error %d at offset %08llX\n", ret, off); @@ -489,13 +487,13 @@ static int do_imls_nand(void) header = (const image_header_t *)buffer; len = image_get_image_size(header); - nand_imls_legacyimage(nand, nand_dev, off, len); + nand_imls_legacyimage(mtd, nand_dev, off, len); break; #endif #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: len = fit_get_size(buffer); - nand_imls_fitimage(nand, nand_dev, off, len); + nand_imls_fitimage(mtd, nand_dev, off, len); break; #endif } diff --git a/cmd/jffs2.c b/cmd/jffs2.c index 0b2eefa1954..e4eaa48c1f5 100644 --- a/cmd/jffs2.c +++ b/cmd/jffs2.c @@ -242,11 +242,11 @@ static int mtd_id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *d static inline u32 get_part_sector_size_nand(struct mtdids *id) { #if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND) - nand_info_t *nand; + struct mtd_info *mtd; - nand = &nand_info[id->num]; + mtd = &nand_info[id->num]; - return nand->erasesize; + return mtd->erasesize; #else BUG(); return 0; diff --git a/cmd/nand.c b/cmd/nand.c index a6b67e29f1c..0439607d682 100644 --- a/cmd/nand.c +++ b/cmd/nand.c @@ -38,7 +38,8 @@ int find_dev_and_part(const char *id, struct mtd_device **dev, u8 *part_num, struct part_info **part); #endif -static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat) +static int nand_dump(struct mtd_info *mtd, ulong off, int only_oob, + int repeat) { int i; u_char *datbuf, *oobbuf, *p; @@ -46,32 +47,32 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat) int ret = 0; if (repeat) - off = last + nand->writesize; + off = last + mtd->writesize; last = off; - datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize); + datbuf = memalign(ARCH_DMA_MINALIGN, mtd->writesize); if (!datbuf) { puts("No memory for page buffer\n"); return 1; } - oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize); + oobbuf = memalign(ARCH_DMA_MINALIGN, mtd->oobsize); if (!oobbuf) { puts("No memory for page buffer\n"); ret = 1; goto free_dat; } - off &= ~(nand->writesize - 1); + off &= ~(mtd->writesize - 1); loff_t addr = (loff_t) off; struct mtd_oob_ops ops; memset(&ops, 0, sizeof(ops)); ops.datbuf = datbuf; ops.oobbuf = oobbuf; - ops.len = nand->writesize; - ops.ooblen = nand->oobsize; + ops.len = mtd->writesize; + ops.ooblen = mtd->oobsize; ops.mode = MTD_OPS_RAW; - i = mtd_read_oob(nand, addr, &ops); + i = mtd_read_oob(mtd, addr, &ops); if (i < 0) { printf("Error (%d) reading page %08lx\n", i, off); ret = 1; @@ -80,7 +81,7 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat) printf("Page %08lx dump:\n", off); if (!only_oob) { - i = nand->writesize >> 4; + i = mtd->writesize >> 4; p = datbuf; while (i--) { @@ -94,7 +95,7 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat) } puts("OOB:\n"); - i = nand->oobsize >> 3; + i = mtd->oobsize >> 3; p = oobbuf; while (i--) { printf("\t%02x %02x %02x %02x %02x %02x %02x %02x\n", @@ -152,32 +153,32 @@ static void print_status(ulong start, ulong end, ulong erasesize, int status) ((status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : "")); } -static void do_nand_status(nand_info_t *nand) +static void do_nand_status(struct mtd_info *mtd) { ulong block_start = 0; ulong off; int last_status = -1; - struct nand_chip *nand_chip = nand->priv; + struct nand_chip *nand_chip = mtd->priv; /* check the WP bit */ - nand_chip->cmdfunc(nand, NAND_CMD_STATUS, -1, -1); + nand_chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); printf("device is %swrite protected\n", - (nand_chip->read_byte(nand) & 0x80 ? - "NOT " : "")); + (nand_chip->read_byte(mtd) & 0x80 ? + "NOT " : "")); - for (off = 0; off < nand->size; off += nand->erasesize) { - int s = nand_get_lock_status(nand, off); + for (off = 0; off < mtd->size; off += mtd->erasesize) { + int s = nand_get_lock_status(mtd, off); /* print message only if status has changed */ if (s != last_status && off != 0) { - print_status(block_start, off, nand->erasesize, + print_status(block_start, off, mtd->erasesize, last_status); block_start = off; } last_status = s; } /* Print the last block info */ - print_status(block_start, off, nand->erasesize, last_status); + print_status(block_start, off, mtd->erasesize, last_status); } #endif @@ -188,10 +189,10 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[]) { int ret; uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)]; - nand_info_t *nand = &nand_info[0]; + struct mtd_info *mtd = &nand_info[0]; char *cmd = argv[1]; - if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !nand->name) { + if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !mtd->name) { puts("no devices available\n"); return 1; } @@ -199,7 +200,7 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[]) set_dev(0); if (!strcmp(cmd, "get")) { - ret = get_nand_env_oob(nand, &nand_env_oob_offset); + ret = get_nand_env_oob(mtd, &nand_env_oob_offset); if (ret) return 1; @@ -229,15 +230,15 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[]) return 1; } - if (nand->oobavail < ENV_OFFSET_SIZE) { + if (mtd->oobavail < ENV_OFFSET_SIZE) { printf("Insufficient available OOB bytes:\n" "%d OOB bytes available but %d required for " "env.oob support\n", - nand->oobavail, ENV_OFFSET_SIZE); + mtd->oobavail, ENV_OFFSET_SIZE); return 1; } - if ((addr & (nand->erasesize - 1)) != 0) { + if ((addr & (mtd->erasesize - 1)) != 0) { printf("Environment offset must be block-aligned\n"); return 1; } @@ -249,15 +250,15 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[]) ops.oobbuf = (void *) oob_buf; oob_buf[0] = ENV_OOB_MARKER; - oob_buf[1] = addr / nand->erasesize; + oob_buf[1] = addr / mtd->erasesize; - ret = nand->write_oob(nand, ENV_OFFSET_SIZE, &ops); + ret = mtd->write_oob(mtd, ENV_OFFSET_SIZE, &ops); if (ret) { printf("Error writing OOB block 0\n"); return ret; } - ret = get_nand_env_oob(nand, &nand_env_oob_offset); + ret = get_nand_env_oob(mtd, &nand_env_oob_offset); if (ret) { printf("Error reading env offset in OOB\n"); return ret; @@ -283,29 +284,29 @@ usage: static void nand_print_and_set_info(int idx) { - nand_info_t *nand = &nand_info[idx]; - struct nand_chip *chip = nand->priv; + struct mtd_info *mtd = &nand_info[idx]; + struct nand_chip *chip = mtd->priv; printf("Device %d: ", idx); if (chip->numchips > 1) printf("%dx ", chip->numchips); printf("%s, sector size %u KiB\n", - nand->name, nand->erasesize >> 10); - printf(" Page size %8d b\n", nand->writesize); - printf(" OOB size %8d b\n", nand->oobsize); - printf(" Erase size %8d b\n", nand->erasesize); + mtd->name, mtd->erasesize >> 10); + printf(" Page size %8d b\n", mtd->writesize); + printf(" OOB size %8d b\n", mtd->oobsize); + printf(" Erase size %8d b\n", mtd->erasesize); printf(" subpagesize %8d b\n", chip->subpagesize); printf(" options 0x%8x\n", chip->options); printf(" bbt options 0x%8x\n", chip->bbt_options); /* Set geometry info */ - setenv_hex("nand_writesize", nand->writesize); - setenv_hex("nand_oobsize", nand->oobsize); - setenv_hex("nand_erasesize", nand->erasesize); + setenv_hex("nand_writesize", mtd->writesize); + setenv_hex("nand_oobsize", mtd->oobsize); + setenv_hex("nand_erasesize", mtd->erasesize); } -static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count, - int read) +static int raw_access(struct mtd_info *mtd, ulong addr, loff_t off, + ulong count, int read) { int ret = 0; @@ -313,18 +314,18 @@ static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count, /* Raw access */ mtd_oob_ops_t ops = { .datbuf = (u8 *)addr, - .oobbuf = ((u8 *)addr) + nand->writesize, - .len = nand->writesize, - .ooblen = nand->oobsize, + .oobbuf = ((u8 *)addr) + mtd->writesize, + .len = mtd->writesize, + .ooblen = mtd->oobsize, .mode = MTD_OPS_RAW }; if (read) { - ret = mtd_read_oob(nand, off, &ops); + ret = mtd_read_oob(mtd, off, &ops); } else { - ret = mtd_write_oob(nand, off, &ops); + ret = mtd_write_oob(mtd, off, &ops); if (!ret) - ret = nand_verify_page_oob(nand, &ops, off); + ret = nand_verify_page_oob(mtd, &ops, off); } if (ret) { @@ -333,8 +334,8 @@ static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count, break; } - addr += nand->writesize + nand->oobsize; - off += nand->writesize; + addr += mtd->writesize + mtd->oobsize; + off += mtd->writesize; } return ret; @@ -348,18 +349,18 @@ static void adjust_size_for_badblocks(loff_t *size, loff_t offset, int dev) /* We grab the nand info object here fresh because this is usually * called after arg_off_size() which can change the value of dev. */ - nand_info_t *nand = &nand_info[dev]; + struct mtd_info *mtd = &nand_info[dev]; loff_t maxoffset = offset + *size; int badblocks = 0; /* count badblocks in NAND from offset to offset + size */ - for (; offset < maxoffset; offset += nand->erasesize) { - if (nand_block_isbad(nand, offset)) + for (; offset < maxoffset; offset += mtd->erasesize) { + if (nand_block_isbad(mtd, offset)) badblocks++; } /* adjust size if any bad blocks found */ if (badblocks) { - *size -= badblocks * nand->erasesize; + *size -= badblocks * mtd->erasesize; printf("size adjusted to 0x%llx (%d bad blocks)\n", (unsigned long long)*size, badblocks); } @@ -371,7 +372,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ulong addr; loff_t off, size, maxsize; char *cmd, *s; - nand_info_t *nand; + struct mtd_info *mtd; #ifdef CONFIG_SYS_NAND_QUIET int quiet = CONFIG_SYS_NAND_QUIET; #else @@ -437,12 +438,12 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("\nno devices available\n"); return 1; } - nand = &nand_info[dev]; + mtd = &nand_info[dev]; if (strcmp(cmd, "bad") == 0) { printf("\nDevice %d bad blocks:\n", dev); - for (off = 0; off < nand->size; off += nand->erasesize) - if (nand_block_isbad(nand, off)) + for (off = 0; off < mtd->size; off += mtd->erasesize) + if (nand_block_isbad(mtd, off)) printf(" %08llx\n", (unsigned long long)off); return 0; } @@ -502,7 +503,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (set_dev(dev)) return 1; - nand = &nand_info[dev]; + mtd = &nand_info[dev]; memset(&opts, 0, sizeof(opts)); opts.offset = off; @@ -524,7 +525,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } } } - ret = nand_erase_opts(nand, &opts); + ret = nand_erase_opts(mtd, &opts); printf("%s\n", ret ? "ERROR" : "OK"); return ret == 0 ? 0 : 1; @@ -535,7 +536,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) goto usage; off = (int)simple_strtoul(argv[2], NULL, 16); - ret = nand_dump(nand, off, !strcmp(&cmd[4], ".oob"), repeat); + ret = nand_dump(mtd, off, !strcmp(&cmd[4], ".oob"), repeat); return ret == 0 ? 1 : 0; } @@ -567,19 +568,19 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (set_dev(dev)) return 1; - nand = &nand_info[dev]; + mtd = &nand_info[dev]; if (argc > 4 && !str2long(argv[4], &pagecount)) { printf("'%s' is not a number\n", argv[4]); return 1; } - if (pagecount * nand->writesize > size) { + if (pagecount * mtd->writesize > size) { puts("Size exceeds partition or device limit\n"); return -1; } - rwsize = pagecount * (nand->writesize + nand->oobsize); + rwsize = pagecount * (mtd->writesize + mtd->oobsize); } else { if (mtd_arg_off_size(argc - 3, argv + 3, &dev, &off, &size, &maxsize, @@ -596,16 +597,16 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) rwsize = size; } - nand = &nand_info[dev]; + mtd = &nand_info[dev]; if (!s || !strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i")) { if (read) - ret = nand_read_skip_bad(nand, off, &rwsize, + ret = nand_read_skip_bad(mtd, off, &rwsize, NULL, maxsize, (u_char *)addr); else - ret = nand_write_skip_bad(nand, off, &rwsize, + ret = nand_write_skip_bad(mtd, off, &rwsize, NULL, maxsize, (u_char *)addr, WITH_WR_VERIFY); @@ -615,7 +616,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("Unknown nand command suffix '%s'\n", s); return 1; } - ret = nand_write_skip_bad(nand, off, &rwsize, NULL, + ret = nand_write_skip_bad(mtd, off, &rwsize, NULL, maxsize, (u_char *)addr, WITH_DROP_FFS | WITH_WR_VERIFY); #endif @@ -628,11 +629,11 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) }; if (read) - ret = mtd_read_oob(nand, off, &ops); + ret = mtd_read_oob(mtd, off, &ops); else - ret = mtd_write_oob(nand, off, &ops); + ret = mtd_write_oob(mtd, off, &ops); } else if (raw) { - ret = raw_access(nand, addr, off, pagecount, read); + ret = raw_access(mtd, addr, off, pagecount, read); } else { printf("Unknown nand command suffix '%s'.\n", s); return 1; @@ -655,8 +656,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } printf("\nNAND torture: device %d offset 0x%llx size 0x%x\n", - dev, off, nand->erasesize); - ret = nand_torture(nand, off); + dev, off, mtd->erasesize); + ret = nand_torture(mtd, off); printf(" %s\n", ret ? "Failed" : "Passed"); return ret == 0 ? 0 : 1; @@ -673,7 +674,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) while (argc > 0) { addr = simple_strtoul(*argv, NULL, 16); - if (mtd_block_markbad(nand, addr)) { + if (mtd_block_markbad(mtd, addr)) { printf("block 0x%08lx NOT marked " "as bad! ERROR %d\n", addr, ret); @@ -705,9 +706,9 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) status = 1; } if (status) { - do_nand_status(nand); + do_nand_status(mtd); } else { - if (!nand_lock(nand, tight)) { + if (!nand_lock(mtd, tight)) { puts("NAND flash successfully locked\n"); } else { puts("Error locking NAND flash\n"); @@ -801,7 +802,7 @@ U_BOOT_CMD( "NAND sub-system", nand_help_text ); -static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, +static int nand_load_image(cmd_tbl_t *cmdtp, struct mtd_info *mtd, ulong offset, ulong addr, char *cmd) { int r; @@ -822,11 +823,11 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, return 1; } - printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset); + printf("\nLoading from %s, offset 0x%lx\n", mtd->name, offset); - cnt = nand->writesize; - r = nand_read_skip_bad(nand, offset, &cnt, NULL, nand->size, - (u_char *)addr); + cnt = mtd->writesize; + r = nand_read_skip_bad(mtd, offset, &cnt, NULL, mtd->size, + (u_char *)addr); if (r) { puts("** Read error\n"); bootstage_error(BOOTSTAGE_ID_NAND_HDR_READ); @@ -860,8 +861,8 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, } bootstage_mark(BOOTSTAGE_ID_NAND_TYPE); - r = nand_read_skip_bad(nand, offset, &cnt, NULL, nand->size, - (u_char *)addr); + r = nand_read_skip_bad(mtd, offset, &cnt, NULL, mtd->size, + (u_char *)addr); if (r) { puts("** Read error\n"); bootstage_error(BOOTSTAGE_ID_NAND_READ); diff --git a/common/env_nand.c b/common/env_nand.c index b32eeac9d76..0debc2c1926 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -276,7 +276,7 @@ static int readenv(size_t offset, u_char *buf) #endif /* #if defined(CONFIG_SPL_BUILD) */ #ifdef CONFIG_ENV_OFFSET_OOB -int get_nand_env_oob(nand_info_t *nand, unsigned long *result) +int get_nand_env_oob(struct mtd_info *mtd, unsigned long *result) { struct mtd_oob_ops ops; uint32_t oob_buf[ENV_OFFSET_SIZE / sizeof(uint32_t)]; @@ -288,14 +288,14 @@ int get_nand_env_oob(nand_info_t *nand, unsigned long *result) ops.ooblen = ENV_OFFSET_SIZE; ops.oobbuf = (void *)oob_buf; - ret = nand->read_oob(nand, ENV_OFFSET_SIZE, &ops); + ret = mtd->read_oob(mtd, ENV_OFFSET_SIZE, &ops); if (ret) { printf("error reading OOB block 0\n"); return ret; } if (oob_buf[0] == ENV_OOB_MARKER) { - *result = oob_buf[1] * nand->erasesize; + *result = oob_buf[1] * mtd->erasesize; } else if (oob_buf[0] == ENV_OOB_MARKER_OLD) { *result = oob_buf[1]; } else { diff --git a/common/fb_nand.c b/common/fb_nand.c index 9ca8602a73e..c770effd799 100644 --- a/common/fb_nand.c +++ b/common/fb_nand.c @@ -19,7 +19,7 @@ static char *response_str; struct fb_nand_sparse { - nand_info_t *nand; + struct mtd_info *nand; struct part_info *part; }; @@ -34,7 +34,7 @@ __weak int board_fastboot_write_partition_setup(char *name) } static int fb_nand_lookup(const char *partname, char *response, - nand_info_t **nand, + struct mtd_info **nand, struct part_info **part) { struct mtd_device *dev; @@ -62,12 +62,12 @@ static int fb_nand_lookup(const char *partname, char *response, return -EINVAL; } - *nand = &nand_info[dev->id->num]; + *mtd = &nand_info[dev->id->num]; return 0; } -static int _fb_nand_erase(nand_info_t *nand, struct part_info *part) +static int _fb_nand_erase(struct mtd_info *mtd, struct part_info *part) { nand_erase_options_t opts; int ret; @@ -80,7 +80,7 @@ static int _fb_nand_erase(nand_info_t *nand, struct part_info *part) printf("Erasing blocks 0x%llx to 0x%llx\n", part->offset, part->offset + part->size); - ret = nand_erase_opts(nand, &opts); + ret = nand_erase_opts(mtd, &opts); if (ret) return ret; @@ -90,7 +90,7 @@ static int _fb_nand_erase(nand_info_t *nand, struct part_info *part) return 0; } -static int _fb_nand_write(nand_info_t *nand, struct part_info *part, +static int _fb_nand_write(struct mtd_info *mtd, struct part_info *part, void *buffer, unsigned int offset, unsigned int length, size_t *written) { @@ -100,7 +100,7 @@ static int _fb_nand_write(nand_info_t *nand, struct part_info *part, flags |= WITH_DROP_FFS; #endif - return nand_write_skip_bad(nand, offset, &length, written, + return nand_write_skip_bad(mtd, offset, &length, written, part->size - (offset - part->offset), buffer, flags); } @@ -131,13 +131,13 @@ void fb_nand_flash_write(const char *partname, unsigned int session_id, char *response) { struct part_info *part; - nand_info_t *nand = NULL; + struct mtd_info *mtd = NULL; int ret; /* initialize the response buffer */ response_str = response; - ret = fb_nand_lookup(partname, response, &nand, &part); + ret = fb_nand_lookup(partname, response, &mtd, &part); if (ret) { error("invalid NAND device"); fastboot_fail(response_str, "invalid NAND device"); @@ -152,10 +152,10 @@ void fb_nand_flash_write(const char *partname, unsigned int session_id, struct fb_nand_sparse sparse_priv; sparse_storage_t sparse; - sparse_priv.nand = nand; + sparse_priv.nand = mtd; sparse_priv.part = part; - sparse.block_sz = nand->writesize; + sparse.block_sz = mtd->writesize; sparse.start = part->offset / sparse.block_sz; sparse.size = part->size / sparse.block_sz; sparse.name = part->name; @@ -167,7 +167,7 @@ void fb_nand_flash_write(const char *partname, unsigned int session_id, printf("Flashing raw image at offset 0x%llx\n", part->offset); - ret = _fb_nand_write(nand, part, download_buffer, part->offset, + ret = _fb_nand_write(mtd, part, download_buffer, part->offset, download_bytes, NULL); printf("........ wrote %u bytes to '%s'\n", @@ -185,13 +185,13 @@ void fb_nand_flash_write(const char *partname, unsigned int session_id, void fb_nand_erase(const char *partname, char *response) { struct part_info *part; - nand_info_t *nand = NULL; + struct mtd_info *mtd = NULL; int ret; /* initialize the response buffer */ response_str = response; - ret = fb_nand_lookup(partname, response, &nand, &part); + ret = fb_nand_lookup(partname, response, &mtd, &part); if (ret) { error("invalid NAND device"); fastboot_fail(response_str, "invalid NAND device"); @@ -202,9 +202,9 @@ void fb_nand_erase(const char *partname, char *response) if (ret) return; - ret = _fb_nand_erase(nand, part); + ret = _fb_nand_erase(mtd, part); if (ret) { - error("failed erasing from device %s", nand->name); + error("failed erasing from device %s", mtd->name); fastboot_fail(response_str, "failed erasing from device"); return; } diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c index a9754922e8d..4652541aeff 100644 --- a/drivers/dfu/dfu_nand.c +++ b/drivers/dfu/dfu_nand.c @@ -25,7 +25,7 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu, loff_t start, lim; size_t count, actual; int ret; - nand_info_t *nand; + struct mtd_info *mtd; /* if buf == NULL return total size of the area */ if (buf == NULL) { @@ -44,11 +44,11 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu, return -1; } - nand = &nand_info[nand_curr_device]; + mtd = &nand_info[nand_curr_device]; if (op == DFU_OP_READ) { - ret = nand_read_skip_bad(nand, start, &count, &actual, - lim, buf); + ret = nand_read_skip_bad(mtd, start, &count, &actual, + lim, buf); } else { nand_erase_options_t opts; @@ -59,12 +59,12 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu, opts.quiet = 1; opts.lim = lim; /* first erase */ - ret = nand_erase_opts(nand, &opts); + ret = nand_erase_opts(mtd, &opts); if (ret) return ret; /* then write */ - ret = nand_write_skip_bad(nand, start, &count, &actual, - lim, buf, WITH_WR_VERIFY); + ret = nand_write_skip_bad(mtd, start, &count, &actual, + lim, buf, WITH_WR_VERIFY); } if (ret != 0) { @@ -142,7 +142,7 @@ static int dfu_flush_medium_nand(struct dfu_entity *dfu) /* in case of ubi partition, erase rest of the partition */ if (dfu->data.nand.ubi) { - nand_info_t *nand; + struct mtd_info *mtd; nand_erase_options_t opts; if (nand_curr_device < 0 || @@ -152,14 +152,14 @@ static int dfu_flush_medium_nand(struct dfu_entity *dfu) return -1; } - nand = &nand_info[nand_curr_device]; + mtd = &nand_info[nand_curr_device]; memset(&opts, 0, sizeof(opts)); opts.offset = dfu->data.nand.start + dfu->offset + dfu->bad_skip; opts.length = dfu->data.nand.start + dfu->data.nand.size - opts.offset; - ret = nand_erase_opts(nand, &opts); + ret = nand_erase_opts(mtd, &opts); if (ret != 0) printf("Failure erase: %d\n", ret); } diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c index 31c78258b98..b8f68c0ea92 100644 --- a/drivers/mtd/nand/am335x_spl_bch.c +++ b/drivers/mtd/nand/am335x_spl_bch.c @@ -16,7 +16,7 @@ #include static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; -nand_info_t nand_info[1]; +struct mtd_info nand_info[1]; static struct nand_chip nand_chip; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 7cc1de03134..e6b3fe8b2b1 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1238,7 +1238,7 @@ static int at91_nand_ready(struct mtd_info *mtd) #ifdef CONFIG_SPL_BUILD /* The following code is for SPL */ -static nand_info_t mtd; +static struct mtd_info mtd; static struct nand_chip nand_chip; static int nand_command(int block, int page, uint32_t offs, u8 cmd) diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c index 0e7c364a220..4d691d1a32c 100644 --- a/drivers/mtd/nand/mxs_nand_spl.c +++ b/drivers/mtd/nand/mxs_nand_spl.c @@ -8,7 +8,7 @@ #include #include -static nand_info_t mtd; +static struct mtd_info mtd; static struct nand_chip nand_chip; static void mxs_nand_command(struct mtd_info *mtd, unsigned int command, diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index 8f0a9210ec3..46f2654102c 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; int nand_curr_device = -1; -nand_info_t nand_info[CONFIG_SYS_MAX_NAND_DEVICE]; +struct mtd_info nand_info[CONFIG_SYS_MAX_NAND_DEVICE]; #ifndef CONFIG_SYS_NAND_SELF_INIT static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c index e69f66226da..b3978e97556 100644 --- a/drivers/mtd/nand/nand_spl_simple.c +++ b/drivers/mtd/nand/nand_spl_simple.c @@ -11,7 +11,7 @@ #include static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; -static nand_info_t mtd; +static struct mtd_info mtd; static struct nand_chip nand_chip; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 71285b66694..90bf798ac00 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -42,25 +42,26 @@ typedef struct mtd_info mtd_info_t; * nand_erase_opts: - erase NAND flash with support for various options * (jffs2 formatting) * - * @param meminfo NAND device to erase + * @param mtd nand mtd instance to erase * @param opts options, @see struct nand_erase_options * @return 0 in case of success * * This code is ported from flash_eraseall.c from Linux mtd utils by * Arcom Control System Ltd. */ -int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) +int nand_erase_opts(struct mtd_info *mtd, + const nand_erase_options_t *opts) { struct jffs2_unknown_node cleanmarker; erase_info_t erase; unsigned long erase_length, erased_length; /* in blocks */ int result; int percent_complete = -1; - const char *mtd_device = meminfo->name; + const char *mtd_device = mtd->name; struct mtd_oob_ops oob_opts; - struct nand_chip *chip = meminfo->priv; + struct nand_chip *chip = mtd->priv; - if ((opts->offset & (meminfo->erasesize - 1)) != 0) { + if ((opts->offset & (mtd->erasesize - 1)) != 0) { printf("Attempt to erase non block-aligned data\n"); return -1; } @@ -68,11 +69,11 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) memset(&erase, 0, sizeof(erase)); memset(&oob_opts, 0, sizeof(oob_opts)); - erase.mtd = meminfo; - erase.len = meminfo->erasesize; + erase.mtd = mtd; + erase.len = mtd->erasesize; erase.addr = opts->offset; - erase_length = lldiv(opts->length + meminfo->erasesize - 1, - meminfo->erasesize); + erase_length = lldiv(opts->length + mtd->erasesize - 1, + mtd->erasesize); cleanmarker.magic = cpu_to_je16(JFFS2_MAGIC_BITMASK); cleanmarker.nodetype = cpu_to_je16(JFFS2_NODETYPE_CLEANMARKER); @@ -97,7 +98,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) for (erased_length = 0; erased_length < erase_length; - erase.addr += meminfo->erasesize) { + erase.addr += mtd->erasesize) { WATCHDOG_RESET(); @@ -106,7 +107,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) return -EFBIG; } if (!opts->scrub) { - int ret = mtd_block_isbad(meminfo, erase.addr); + int ret = mtd_block_isbad(mtd, erase.addr); if (ret > 0) { if (!opts->quiet) printf("\rSkipping bad block at " @@ -129,7 +130,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) erased_length++; - result = mtd_erase(meminfo, &erase); + result = mtd_erase(mtd, &erase); if (result != 0) { printf("\n%s: MTD Erase failure: %d\n", mtd_device, result); @@ -145,9 +146,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) ops.ooboffs = 0; ops.mode = MTD_OPS_AUTO_OOB; - result = mtd_write_oob(meminfo, - erase.addr, - &ops); + result = mtd_write_oob(mtd, erase.addr, &ops); if (result != 0) { printf("\n%s: MTD writeoob failure: %d\n", mtd_device, result); @@ -303,7 +302,7 @@ int nand_get_lock_status(struct mtd_info *mtd, loff_t offset) * @param mtd nand mtd instance * @param start start byte address * @param length number of bytes to unlock (must be a multiple of - * page size nand->writesize) + * page size mtd->writesize) * @param allexcept if set, unlock everything not selected * * @return 0 on success, -1 in case of error @@ -399,7 +398,7 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length, * Check if there are any bad blocks, and whether length including bad * blocks fits into device * - * @param nand NAND device + * @param mtd nand mtd instance * @param offset offset in flash * @param length image length * @param used length of flash needed for the requested length @@ -407,8 +406,8 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length, * 1 if the image fits, but there are bad blocks * -1 if the image does not fit */ -static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length, - size_t *used) +static int check_skip_len(struct mtd_info *mtd, loff_t offset, size_t length, + size_t *used) { size_t len_excl_bad = 0; int ret = 0; @@ -417,14 +416,14 @@ static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length, size_t block_len, block_off; loff_t block_start; - if (offset >= nand->size) + if (offset >= mtd->size) return -1; - block_start = offset & ~(loff_t)(nand->erasesize - 1); - block_off = offset & (nand->erasesize - 1); - block_len = nand->erasesize - block_off; + block_start = offset & ~(loff_t)(mtd->erasesize - 1); + block_off = offset & (mtd->erasesize - 1); + block_len = mtd->erasesize - block_off; - if (!nand_block_isbad(nand, block_start)) + if (!nand_block_isbad(mtd, block_start)) len_excl_bad += block_len; else ret = 1; @@ -441,7 +440,7 @@ static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length, } #ifdef CONFIG_CMD_NAND_TRIMFFS -static size_t drop_ffs(const nand_info_t *nand, const u_char *buf, +static size_t drop_ffs(const struct mtd_info *mtd, const u_char *buf, const size_t *len) { size_t l = *len; @@ -453,8 +452,8 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf, /* The resulting length must be aligned to the minimum flash I/O size */ l = i + 1; - l = (l + nand->writesize - 1) / nand->writesize; - l *= nand->writesize; + l = (l + mtd->writesize - 1) / mtd->writesize; + l *= mtd->writesize; /* * since the input length may be unaligned, prevent access past the end @@ -471,16 +470,17 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf, * Reads page of NAND and verifies the contents and OOB against the * values in ops. * - * @param nand NAND device + * @param mtd nand mtd instance * @param ops MTD operations, including data to verify * @param ofs offset in flash * @return 0 in case of success */ -int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs) +int nand_verify_page_oob(struct mtd_info *mtd, struct mtd_oob_ops *ops, + loff_t ofs) { int rval; struct mtd_oob_ops vops; - size_t verlen = nand->writesize + nand->oobsize; + size_t verlen = mtd->writesize + mtd->oobsize; memcpy(&vops, ops, sizeof(vops)); @@ -489,9 +489,9 @@ int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs) if (!vops.datbuf) return -ENOMEM; - vops.oobbuf = vops.datbuf + nand->writesize; + vops.oobbuf = vops.datbuf + mtd->writesize; - rval = mtd_read_oob(nand, ofs, &vops); + rval = mtd_read_oob(mtd, ofs, &vops); if (!rval) rval = memcmp(ops->datbuf, vops.datbuf, vops.len); if (!rval) @@ -510,17 +510,17 @@ int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs) * the contents of a buffer. The offset into the NAND must be * page-aligned, and the function doesn't handle skipping bad blocks. * - * @param nand NAND device + * @param mtd nand mtd instance * @param ofs offset in flash * @param len buffer length * @param buf buffer to read from * @return 0 in case of success */ -int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf) +int nand_verify(struct mtd_info *mtd, loff_t ofs, size_t len, u_char *buf) { int rval = 0; size_t verofs; - size_t verlen = nand->writesize; + size_t verlen = mtd->writesize; uint8_t *verbuf = memalign(ARCH_DMA_MINALIGN, verlen); if (!verbuf) @@ -529,8 +529,8 @@ int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf) /* Read the NAND back in page-size groups to limit malloc size */ for (verofs = ofs; verofs < ofs + len; verofs += verlen, buf += verlen) { - verlen = min(nand->writesize, (uint32_t)(ofs + len - verofs)); - rval = nand_read(nand, verofs, &verlen, verbuf); + verlen = min(mtd->writesize, (uint32_t)(ofs + len - verofs)); + rval = nand_read(mtd, verofs, &verlen, verbuf); if (!rval || (rval == -EUCLEAN)) rval = memcmp(buf, verbuf, verlen); @@ -558,7 +558,7 @@ int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf) * beyond the limit we are passed, length is set to 0 and actual is set * to the required length. * - * @param nand NAND device + * @param mtd nand mtd instance * @param offset offset in flash * @param length buffer length * @param actual set to size required to write length worth of @@ -569,8 +569,8 @@ int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf) * @param flags flags modifying the behaviour of the write to NAND * @return 0 in case of success */ -int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, - size_t *actual, loff_t lim, u_char *buffer, int flags) +int nand_write_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length, + size_t *actual, loff_t lim, u_char *buffer, int flags) { int rval = 0, blocksize; size_t left_to_write = *length; @@ -581,7 +581,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, if (actual) *actual = 0; - blocksize = nand->erasesize; + blocksize = mtd->erasesize; /* * nand_write() handles unaligned, partial page writes. @@ -594,13 +594,13 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, * you should only start a block skipping access at a * partition boundary). So don't try to handle that. */ - if ((offset & (nand->writesize - 1)) != 0) { + if ((offset & (mtd->writesize - 1)) != 0) { printf("Attempt to write non page-aligned data\n"); *length = 0; return -EINVAL; } - need_skip = check_skip_len(nand, offset, *length, &used_for_write); + need_skip = check_skip_len(mtd, offset, *length, &used_for_write); if (actual) *actual = used_for_write; @@ -618,10 +618,10 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, } if (!need_skip && !(flags & WITH_DROP_FFS)) { - rval = nand_write(nand, offset, length, buffer); + rval = nand_write(mtd, offset, length, buffer); if ((flags & WITH_WR_VERIFY) && !rval) - rval = nand_verify(nand, offset, *length, buffer); + rval = nand_verify(mtd, offset, *length, buffer); if (rval == 0) return 0; @@ -633,15 +633,15 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, } while (left_to_write > 0) { - size_t block_offset = offset & (nand->erasesize - 1); + size_t block_offset = offset & (mtd->erasesize - 1); size_t write_size, truncated_write_size; WATCHDOG_RESET(); - if (nand_block_isbad(nand, offset & ~(nand->erasesize - 1))) { + if (nand_block_isbad(mtd, offset & ~(mtd->erasesize - 1))) { printf("Skip bad block 0x%08llx\n", - offset & ~(nand->erasesize - 1)); - offset += nand->erasesize - block_offset; + offset & ~(mtd->erasesize - 1)); + offset += mtd->erasesize - block_offset; continue; } @@ -653,15 +653,15 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, truncated_write_size = write_size; #ifdef CONFIG_CMD_NAND_TRIMFFS if (flags & WITH_DROP_FFS) - truncated_write_size = drop_ffs(nand, p_buffer, + truncated_write_size = drop_ffs(mtd, p_buffer, &write_size); #endif - rval = nand_write(nand, offset, &truncated_write_size, + rval = nand_write(mtd, offset, &truncated_write_size, p_buffer); if ((flags & WITH_WR_VERIFY) && !rval) - rval = nand_verify(nand, offset, + rval = nand_verify(mtd, offset, truncated_write_size, p_buffer); offset += write_size; @@ -693,7 +693,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, * the limit we are passed, length is set to 0 and actual is set to the * required length. * - * @param nand NAND device + * @param mtd nand mtd instance * @param offset offset in flash * @param length buffer length, on return holds number of read bytes * @param actual set to size required to read length worth of buffer or 0 @@ -703,8 +703,8 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, * @param buffer buffer to write to * @return 0 in case of success */ -int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, - size_t *actual, loff_t lim, u_char *buffer) +int nand_read_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length, + size_t *actual, loff_t lim, u_char *buffer) { int rval; size_t left_to_read = *length; @@ -712,7 +712,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, u_char *p_buffer = buffer; int need_skip; - if ((offset & (nand->writesize - 1)) != 0) { + if ((offset & (mtd->writesize - 1)) != 0) { printf("Attempt to read non page-aligned data\n"); *length = 0; if (actual) @@ -720,7 +720,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, return -EINVAL; } - need_skip = check_skip_len(nand, offset, *length, &used_for_read); + need_skip = check_skip_len(mtd, offset, *length, &used_for_read); if (actual) *actual = used_for_read; @@ -738,7 +738,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, } if (!need_skip) { - rval = nand_read(nand, offset, length, buffer); + rval = nand_read(mtd, offset, length, buffer); if (!rval || rval == -EUCLEAN) return 0; @@ -749,24 +749,24 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, } while (left_to_read > 0) { - size_t block_offset = offset & (nand->erasesize - 1); + size_t block_offset = offset & (mtd->erasesize - 1); size_t read_length; WATCHDOG_RESET(); - if (nand_block_isbad(nand, offset & ~(nand->erasesize - 1))) { + if (nand_block_isbad(mtd, offset & ~(mtd->erasesize - 1))) { printf("Skipping bad block 0x%08llx\n", - offset & ~(nand->erasesize - 1)); - offset += nand->erasesize - block_offset; + offset & ~(mtd->erasesize - 1)); + offset += mtd->erasesize - block_offset; continue; } - if (left_to_read < (nand->erasesize - block_offset)) + if (left_to_read < (mtd->erasesize - block_offset)) read_length = left_to_read; else - read_length = nand->erasesize - block_offset; + read_length = mtd->erasesize - block_offset; - rval = nand_read(nand, offset, &read_length, p_buffer); + rval = nand_read(mtd, offset, &read_length, p_buffer); if (rval && rval != -EUCLEAN) { printf("NAND read from offset %llx failed %d\n", offset, rval); @@ -812,57 +812,57 @@ static int check_pattern(const u_char *buf, u_char patt, int size) * This is useful to determine if a block that caused a write error is still * good or should be marked as bad. * - * @param nand NAND device + * @param mtd nand mtd instance * @param offset offset in flash * @return 0 if the block is still good */ -int nand_torture(nand_info_t *nand, loff_t offset) +int nand_torture(struct mtd_info *mtd, loff_t offset) { u_char patterns[] = {0xa5, 0x5a, 0x00}; struct erase_info instr = { .mtd = nand, .addr = offset, - .len = nand->erasesize, + .len = mtd->erasesize, }; size_t retlen; int err, ret = -1, i, patt_count; u_char *buf; - if ((offset & (nand->erasesize - 1)) != 0) { + if ((offset & (mtd->erasesize - 1)) != 0) { puts("Attempt to torture a block at a non block-aligned offset\n"); return -EINVAL; } - if (offset + nand->erasesize > nand->size) { + if (offset + mtd->erasesize > mtd->size) { puts("Attempt to torture a block outside the flash area\n"); return -EINVAL; } patt_count = ARRAY_SIZE(patterns); - buf = malloc_cache_aligned(nand->erasesize); + buf = malloc_cache_aligned(mtd->erasesize); if (buf == NULL) { puts("Out of memory for erase block buffer\n"); return -ENOMEM; } for (i = 0; i < patt_count; i++) { - err = nand->erase(nand, &instr); + err = mtd->erase(mtd, &instr); if (err) { printf("%s: erase() failed for block at 0x%llx: %d\n", - nand->name, instr.addr, err); + mtd->name, instr.addr, err); goto out; } /* Make sure the block contains only 0xff bytes */ - err = nand->read(nand, offset, nand->erasesize, &retlen, buf); - if ((err && err != -EUCLEAN) || retlen != nand->erasesize) { + err = mtd->read(mtd, offset, mtd->erasesize, &retlen, buf); + if ((err && err != -EUCLEAN) || retlen != mtd->erasesize) { printf("%s: read() failed for block at 0x%llx: %d\n", - nand->name, instr.addr, err); + mtd->name, instr.addr, err); goto out; } - err = check_pattern(buf, 0xff, nand->erasesize); + err = check_pattern(buf, 0xff, mtd->erasesize); if (!err) { printf("Erased block at 0x%llx, but a non-0xff byte was found\n", offset); @@ -871,22 +871,22 @@ int nand_torture(nand_info_t *nand, loff_t offset) } /* Write a pattern and check it */ - memset(buf, patterns[i], nand->erasesize); - err = nand->write(nand, offset, nand->erasesize, &retlen, buf); - if (err || retlen != nand->erasesize) { + memset(buf, patterns[i], mtd->erasesize); + err = mtd->write(mtd, offset, mtd->erasesize, &retlen, buf); + if (err || retlen != mtd->erasesize) { printf("%s: write() failed for block at 0x%llx: %d\n", - nand->name, instr.addr, err); + mtd->name, instr.addr, err); goto out; } - err = nand->read(nand, offset, nand->erasesize, &retlen, buf); - if ((err && err != -EUCLEAN) || retlen != nand->erasesize) { + err = mtd->read(mtd, offset, mtd->erasesize, &retlen, buf); + if ((err && err != -EUCLEAN) || retlen != mtd->erasesize) { printf("%s: read() failed for block at 0x%llx: %d\n", - nand->name, instr.addr, err); + mtd->name, instr.addr, err); goto out; } - err = check_pattern(buf, patterns[i], nand->erasesize); + err = check_pattern(buf, patterns[i], mtd->erasesize); if (!err) { printf("Pattern 0x%.2x checking failed for block at " "0x%llx\n", patterns[i], offset); diff --git a/fs/jffs2/jffs2_nand_1pass.c b/fs/jffs2/jffs2_nand_1pass.c index 740f787dd23..9b7af09fe39 100644 --- a/fs/jffs2/jffs2_nand_1pass.c +++ b/fs/jffs2/jffs2_nand_1pass.c @@ -23,7 +23,7 @@ # define DEBUGF(fmt,args...) #endif -static nand_info_t *nand; +static struct mtd_info *mtd; /* Compression names */ static char *compr_names[] = { @@ -304,7 +304,7 @@ jffs2_1pass_read_inode(struct b_lists *pL, u32 ino, char *dest, len = sizeof(struct jffs2_raw_inode); if (dest) len += jNode->csize; - nand_read(nand, jNode->offset, &len, inode); + nand_read(mtd, jNode->offset, &len, inode); /* ignore data behind latest known EOF */ if (inode->offset > totalSize) continue; @@ -450,7 +450,7 @@ dump_inode(struct b_lists *pL, struct b_dirent *d, struct b_inode *i) if(!d || !i) return -1; len = d->nsize; - nand_read(nand, d->offset + sizeof(struct jffs2_raw_dirent), + nand_read(mtd, d->offset + sizeof(struct jffs2_raw_dirent), &len, &fname); fname[d->nsize] = '\0'; @@ -592,7 +592,9 @@ jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino) for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) { if (jNode->ino == jDirFoundIno) { size_t len = jNode->csize; - nand_read(nand, jNode->offset + sizeof(struct jffs2_raw_inode), &len, &tmp); + nand_read(mtd, + jNode->offset + sizeof(struct jffs2_raw_inode), + &len, &tmp); tmp[jNode->csize] = '\0'; break; } @@ -760,14 +762,14 @@ dump_dirents(struct b_lists *pL) #endif static int -jffs2_fill_scan_buf(nand_info_t *nand, unsigned char *buf, +jffs2_fill_scan_buf(struct mtd_info *mtd, unsigned char *buf, unsigned ofs, unsigned len) { int ret; unsigned olen; olen = len; - ret = nand_read(nand, ofs, &olen, buf); + ret = nand_read(mtd, ofs, &olen, buf); if (ret) { printf("nand_read(0x%x bytes from 0x%x) returned %d\n", len, ofs, ret); return ret; @@ -794,7 +796,7 @@ jffs2_1pass_build_lists(struct part_info * part) u32 counterN = 0; struct mtdids *id = part->dev->id; - nand = nand_info + id->num; + mtd = nand_info + id->num; /* if we are building a list we need to refresh the cache. */ jffs_init_1pass_list(part); @@ -802,7 +804,7 @@ jffs2_1pass_build_lists(struct part_info * part) pL->partOffset = part->offset; puts ("Scanning JFFS2 FS: "); - sectorsize = nand->erasesize; + sectorsize = mtd->erasesize; nr_blocks = part->size / sectorsize; buf = malloc(sectorsize); if (!buf) @@ -813,10 +815,10 @@ jffs2_1pass_build_lists(struct part_info * part) offset = part->offset + i * sectorsize; - if (nand_block_isbad(nand, offset)) + if (nand_block_isbad(mtd, offset)) continue; - if (jffs2_fill_scan_buf(nand, buf, offset, EMPTY_SCAN_SIZE)) + if (jffs2_fill_scan_buf(mtd, buf, offset, EMPTY_SCAN_SIZE)) return 0; ofs = 0; @@ -826,7 +828,7 @@ jffs2_1pass_build_lists(struct part_info * part) if (ofs == EMPTY_SCAN_SIZE) continue; - if (jffs2_fill_scan_buf(nand, buf + EMPTY_SCAN_SIZE, offset + EMPTY_SCAN_SIZE, sectorsize - EMPTY_SCAN_SIZE)) + if (jffs2_fill_scan_buf(mtd, buf + EMPTY_SCAN_SIZE, offset + EMPTY_SCAN_SIZE, sectorsize - EMPTY_SCAN_SIZE)) return 0; offset += ofs; diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c index 50000a135b5..5e9902519a7 100644 --- a/fs/yaffs2/yaffs_uboot_glue.c +++ b/fs/yaffs2/yaffs_uboot_glue.c @@ -141,7 +141,7 @@ static const char *yaffs_error_str(void) } } -extern nand_info_t nand_info[]; +extern struct mtd_info nand_info[]; void cmd_yaffs_tracemask(unsigned set, unsigned mask) { diff --git a/include/nand.h b/include/nand.h index 7cbbbd327a6..eb2d76dbc64 100644 --- a/include/nand.h +++ b/include/nand.h @@ -40,27 +40,27 @@ int nand_register(int devnum); extern int board_nand_init(struct nand_chip *nand); #endif -typedef struct mtd_info nand_info_t; - extern int nand_curr_device; -extern nand_info_t nand_info[]; +extern struct mtd_info nand_info[]; -static inline int nand_read(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf) +static inline int nand_read(struct mtd_info *info, loff_t ofs, size_t *len, + u_char *buf) { return mtd_read(info, ofs, *len, (size_t *)len, buf); } -static inline int nand_write(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf) +static inline int nand_write(struct mtd_info *info, loff_t ofs, size_t *len, + u_char *buf) { return mtd_write(info, ofs, *len, (size_t *)len, buf); } -static inline int nand_block_isbad(nand_info_t *info, loff_t ofs) +static inline int nand_block_isbad(struct mtd_info *info, loff_t ofs) { return mtd_block_isbad(info, ofs); } -static inline int nand_erase(nand_info_t *info, loff_t off, size_t size) +static inline int nand_erase(struct mtd_info *info, loff_t off, size_t size) { struct erase_info instr; @@ -96,27 +96,28 @@ struct nand_erase_options { typedef struct nand_erase_options nand_erase_options_t; -int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, +int nand_read_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length, size_t *actual, loff_t lim, u_char *buffer); #define WITH_DROP_FFS (1 << 0) /* drop trailing all-0xff pages */ #define WITH_WR_VERIFY (1 << 1) /* verify data was written correctly */ -int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, +int nand_write_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length, size_t *actual, loff_t lim, u_char *buffer, int flags); -int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); -int nand_torture(nand_info_t *nand, loff_t offset); -int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, - loff_t ofs); -int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf); +int nand_erase_opts(struct mtd_info *mtd, + const nand_erase_options_t *opts); +int nand_torture(struct mtd_info *mtd, loff_t offset); +int nand_verify_page_oob(struct mtd_info *mtd, struct mtd_oob_ops *ops, + loff_t ofs); +int nand_verify(struct mtd_info *mtd, loff_t ofs, size_t len, u_char *buf); #define NAND_LOCK_STATUS_TIGHT 0x01 #define NAND_LOCK_STATUS_UNLOCK 0x04 -int nand_lock(nand_info_t *meminfo, int tight); -int nand_unlock(nand_info_t *meminfo, loff_t start, size_t length, - int allexcept); -int nand_get_lock_status(nand_info_t *meminfo, loff_t offset); +int nand_lock(struct mtd_info *mtd, int tight); +int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length, + int allexcept); +int nand_get_lock_status(struct mtd_info *mtd, loff_t offset); int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst); void nand_deselect(void); @@ -135,6 +136,6 @@ __attribute__((noreturn)) void nand_boot(void); #define ENV_OOB_MARKER_OLD 0x30564e45 /*"ENV0" in little-endian -- offset is stored as byte number */ #define ENV_OFFSET_SIZE 8 -int get_nand_env_oob(nand_info_t *nand, unsigned long *result); +int get_nand_env_oob(struct mtd_info *mtd, unsigned long *result); #endif int spl_nand_erase_one(int block, int page); -- cgit v1.3.1 From b616d9b0a708eb90eb474e1b6ec6dfe4c48a1678 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 30 May 2016 13:57:55 -0500 Subject: nand: Embed mtd_info in struct nand_chip nand_info[] is now an array of pointers, with the actual mtd_info instance embedded in struct nand_chip. This is in preparation for syncing the NAND code with Linux 4.6, which makes the same change to struct nand_chip. It's in a separate commit due to the large amount of changes required to accommodate the change to nand_info[]. Signed-off-by: Scott Wood --- board/BuR/common/common.c | 2 +- board/atmel/at91sam9261ek/at91sam9261ek.c | 2 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 2 +- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 2 +- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 2 +- board/atmel/at91sam9rlek/at91sam9rlek.c | 2 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 2 +- board/atmel/sama5d3xek/sama5d3xek.c | 2 +- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 2 +- board/atmel/sama5d4ek/sama5d4ek.c | 2 +- board/ronetix/pm9261/pm9261.c | 2 +- board/ronetix/pm9263/pm9263.c | 2 +- cmd/bootm.c | 2 +- cmd/jffs2.c | 4 +- cmd/nand.c | 42 ++++++------ common/env_nand.c | 18 +++--- common/fb_nand.c | 2 +- common/splash_source.c | 4 +- doc/README.nand | 15 ++--- drivers/dfu/dfu_nand.c | 8 +-- drivers/mtd/nand/am335x_spl_bch.c | 54 ++++++++-------- drivers/mtd/nand/arasan_nfc.c | 4 +- drivers/mtd/nand/atmel_nand.c | 77 +++++++++++----------- drivers/mtd/nand/denali.c | 4 +- drivers/mtd/nand/fsl_elbc_nand.c | 5 +- drivers/mtd/nand/fsl_ifc_nand.c | 5 +- drivers/mtd/nand/fsmc_nand.c | 10 ++- drivers/mtd/nand/lpc32xx_nand_mlc.c | 10 ++- drivers/mtd/nand/mpc5121_nfc.c | 3 +- drivers/mtd/nand/mxc_nand.c | 2 +- drivers/mtd/nand/mxs_nand_spl.c | 33 +++++----- drivers/mtd/nand/nand.c | 27 +++++--- drivers/mtd/nand/nand_spl_simple.c | 85 +++++++++++++------------ drivers/mtd/nand/omap_gpmc.c | 4 +- drivers/mtd/nand/pxa3xx_nand.c | 10 +-- drivers/mtd/nand/tegra_nand.c | 4 +- drivers/mtd/nand/vf610_nfc.c | 5 +- drivers/net/fm/fm.c | 2 +- drivers/net/phy/cortina.c | 4 +- fs/jffs2/jffs2_1pass.c | 2 +- fs/jffs2/jffs2_nand_1pass.c | 2 +- fs/yaffs2/yaffs_uboot_glue.c | 8 +-- include/linux/mtd/nand.h | 1 + include/nand.h | 6 +- 44 files changed, 247 insertions(+), 239 deletions(-) (limited to 'include') diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index ce4acc13e0e..e947e54c39f 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -259,7 +259,7 @@ static int load_devicetree(void) } #ifdef CONFIG_NAND dtbsize = 0x20000; - rc = nand_read_skip_bad(&nand_info[0], 0x40000, (size_t *)&dtbsize, + rc = nand_read_skip_bad(nand_info[0], 0x40000, (size_t *)&dtbsize, NULL, 0x20000, (u_char *)dtbaddr); #else char *dtbname = getenv("dtb"); diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 7b7cd2c4262..6398bcbc9ea 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -212,7 +212,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20 ); diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index af68e103900..04e5812db3d 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -191,7 +191,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; #ifndef CONFIG_SYS_NO_FLASH flash_size = 0; for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 4c6431266fb..68719168659 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -272,7 +272,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20 ); diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index d3555bbdf69..fc4f50d2192 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -124,7 +124,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index 9ef2864bb13..994f2460788 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -151,7 +151,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20 ); diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index c14df303b22..b0d440d728a 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -196,7 +196,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index e8ee612036d..fa90270b866 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -207,7 +207,7 @@ void lcd_show_board_info(void) nand_size = 0; #ifdef CONFIG_NAND_ATMEL for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; #endif lcd_printf("%ld MB SDRAM, %lld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index f4eef9609fe..23ec2744684 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -191,7 +191,7 @@ void lcd_show_board_info(void) nand_size = 0; #ifdef CONFIG_NAND_ATMEL for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; #endif lcd_printf("%ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index aee621789e9..72bad230871 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -187,7 +187,7 @@ void lcd_show_board_info(void) nand_size = 0; #ifdef CONFIG_NAND_ATMEL for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; #endif lcd_printf("%ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 3cc01cb6870..e2cb94ee13b 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -194,7 +194,7 @@ void lcd_show_board_info(void) nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; flash_size = 0; for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 276ff80943e..e9f9b67b77d 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -293,7 +293,7 @@ void lcd_show_board_info(void) nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; flash_size = 0; for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) diff --git a/cmd/bootm.c b/cmd/bootm.c index 24f1054f34b..f5e91f40a9b 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -461,7 +461,7 @@ static int do_imls_nand(void) printf("\n"); for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) { - mtd = &nand_info[nand_dev]; + mtd = nand_info[nand_dev]; if (!mtd->name || !mtd->size) continue; diff --git a/cmd/jffs2.c b/cmd/jffs2.c index e4eaa48c1f5..f00d53a6c83 100644 --- a/cmd/jffs2.c +++ b/cmd/jffs2.c @@ -167,7 +167,7 @@ static int mtd_device_validate(u8 type, u8 num, u32 *size) } else if (type == MTD_DEV_TYPE_NAND) { #if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND) if (num < CONFIG_SYS_MAX_NAND_DEVICE) { - *size = nand_info[num].size; + *size = nand_info[num]->size; return 0; } @@ -244,7 +244,7 @@ static inline u32 get_part_sector_size_nand(struct mtdids *id) #if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND) struct mtd_info *mtd; - mtd = &nand_info[id->num]; + mtd = nand_info[id->num]; return mtd->erasesize; #else diff --git a/cmd/nand.c b/cmd/nand.c index 0439607d682..f1d5a1161d1 100644 --- a/cmd/nand.c +++ b/cmd/nand.c @@ -116,7 +116,7 @@ free_dat: static int set_dev(int dev) { if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE || - !nand_info[dev].name) { + !nand_info[dev]->name) { puts("No such device\n"); return -1; } @@ -124,12 +124,12 @@ static int set_dev(int dev) if (nand_curr_device == dev) return 0; - printf("Device %d: %s", dev, nand_info[dev].name); + printf("Device %d: %s", dev, nand_info[dev]->name); puts("... is now current device\n"); nand_curr_device = dev; #ifdef CONFIG_SYS_NAND_SELECT_DEVICE - board_nand_select_device(nand_info[dev].priv, dev); + board_nand_select_device(nand_info[dev]->priv, dev); #endif return 0; @@ -189,7 +189,7 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[]) { int ret; uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)]; - struct mtd_info *mtd = &nand_info[0]; + struct mtd_info *mtd = nand_info[0]; char *cmd = argv[1]; if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !mtd->name) { @@ -216,7 +216,7 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[]) /* We don't care about size, or maxsize. */ if (mtd_arg_off(argv[2], &idx, &addr, &maxsize, &maxsize, - MTD_DEV_TYPE_NAND, nand_info[idx].size)) { + MTD_DEV_TYPE_NAND, nand_info[idx]->size)) { puts("Offset or partition name expected\n"); return 1; } @@ -284,7 +284,7 @@ usage: static void nand_print_and_set_info(int idx) { - struct mtd_info *mtd = &nand_info[idx]; + struct mtd_info *mtd = nand_info[idx]; struct nand_chip *chip = mtd->priv; printf("Device %d: ", idx); @@ -349,7 +349,7 @@ static void adjust_size_for_badblocks(loff_t *size, loff_t offset, int dev) /* We grab the nand info object here fresh because this is usually * called after arg_off_size() which can change the value of dev. */ - struct mtd_info *mtd = &nand_info[dev]; + struct mtd_info *mtd = nand_info[dev]; loff_t maxoffset = offset + *size; int badblocks = 0; @@ -399,7 +399,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) putc('\n'); for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) { - if (nand_info[i].name) + if (nand_info[i]->name) nand_print_and_set_info(i); } return 0; @@ -434,11 +434,11 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * for another device is to be used. */ if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE || - !nand_info[dev].name) { + !nand_info[dev]->name) { puts("\nno devices available\n"); return 1; } - mtd = &nand_info[dev]; + mtd = nand_info[dev]; if (strcmp(cmd, "bad") == 0) { printf("\nDevice %d bad blocks:\n", dev); @@ -497,13 +497,13 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* skip first two or three arguments, look for offset and size */ if (mtd_arg_off_size(argc - o, argv + o, &dev, &off, &size, &maxsize, MTD_DEV_TYPE_NAND, - nand_info[dev].size) != 0) + nand_info[dev]->size) != 0) return 1; if (set_dev(dev)) return 1; - mtd = &nand_info[dev]; + mtd = nand_info[dev]; memset(&opts, 0, sizeof(opts)); opts.offset = off; @@ -562,13 +562,13 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (mtd_arg_off(argv[3], &dev, &off, &size, &maxsize, MTD_DEV_TYPE_NAND, - nand_info[dev].size)) + nand_info[dev]->size)) return 1; if (set_dev(dev)) return 1; - mtd = &nand_info[dev]; + mtd = nand_info[dev]; if (argc > 4 && !str2long(argv[4], &pagecount)) { printf("'%s' is not a number\n", argv[4]); @@ -585,7 +585,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (mtd_arg_off_size(argc - 3, argv + 3, &dev, &off, &size, &maxsize, MTD_DEV_TYPE_NAND, - nand_info[dev].size) != 0) + nand_info[dev]->size) != 0) return 1; if (set_dev(dev)) @@ -597,7 +597,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) rwsize = size; } - mtd = &nand_info[dev]; + mtd = nand_info[dev]; if (!s || !strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i")) { @@ -728,13 +728,13 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (mtd_arg_off_size(argc - 2, argv + 2, &dev, &off, &size, &maxsize, MTD_DEV_TYPE_NAND, - nand_info[dev].size) < 0) + nand_info[dev]->size) < 0) return 1; if (set_dev(dev)) return 1; - if (!nand_unlock(&nand_info[dev], off, size, allexcept)) { + if (!nand_unlock(nand_info[dev], off, size, allexcept)) { puts("NAND flash successfully unlocked\n"); } else { puts("Error unlocking NAND flash, " @@ -915,7 +915,7 @@ static int do_nandboot(cmd_tbl_t *cmdtp, int flag, int argc, addr = simple_strtoul(argv[1], NULL, 16); else addr = CONFIG_SYS_LOAD_ADDR; - return nand_load_image(cmdtp, &nand_info[dev->id->num], + return nand_load_image(cmdtp, nand_info[dev->id->num], part->offset, addr, argv[0]); } } @@ -958,14 +958,14 @@ usage: idx = simple_strtoul(boot_device, NULL, 16); - if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx].name) { + if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx]->name) { printf("\n** Device %d not available\n", idx); bootstage_error(BOOTSTAGE_ID_NAND_AVAILABLE); return 1; } bootstage_mark(BOOTSTAGE_ID_NAND_AVAILABLE); - return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]); + return nand_load_image(cmdtp, nand_info[idx], offset, addr, argv[0]); } U_BOOT_CMD(nboot, 4, 1, do_nandboot, diff --git a/common/env_nand.c b/common/env_nand.c index 0debc2c1926..fc99a5e3fc0 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -132,15 +132,15 @@ static int writeenv(size_t offset, u_char *buf) size_t blocksize, len; u_char *char_ptr; - blocksize = nand_info[0].erasesize; + blocksize = nand_info[0]->erasesize; len = min(blocksize, (size_t)CONFIG_ENV_SIZE); while (amount_saved < CONFIG_ENV_SIZE && offset < end) { - if (nand_block_isbad(&nand_info[0], offset)) { + if (nand_block_isbad(nand_info[0], offset)) { offset += blocksize; } else { char_ptr = &buf[amount_saved]; - if (nand_write(&nand_info[0], offset, &len, char_ptr)) + if (nand_write(nand_info[0], offset, &len, char_ptr)) return 1; offset += blocksize; @@ -164,7 +164,7 @@ static int erase_and_write_env(const struct env_location *location, int ret = 0; printf("Erasing %s...\n", location->name); - if (nand_erase_opts(&nand_info[0], &location->erase_opts)) + if (nand_erase_opts(nand_info[0], &location->erase_opts)) return 1; printf("Writing to %s... ", location->name); @@ -247,20 +247,20 @@ static int readenv(size_t offset, u_char *buf) size_t blocksize, len; u_char *char_ptr; - blocksize = nand_info[0].erasesize; + blocksize = nand_info[0]->erasesize; if (!blocksize) return 1; len = min(blocksize, (size_t)CONFIG_ENV_SIZE); while (amount_loaded < CONFIG_ENV_SIZE && offset < end) { - if (nand_block_isbad(&nand_info[0], offset)) { + if (nand_block_isbad(nand_info[0], offset)) { offset += blocksize; } else { char_ptr = &buf[amount_loaded]; - if (nand_read_skip_bad(&nand_info[0], offset, + if (nand_read_skip_bad(nand_info[0], offset, &len, NULL, - nand_info[0].size, char_ptr)) + nand_info[0]->size, char_ptr)) return 1; offset += blocksize; @@ -387,7 +387,7 @@ void env_relocate_spec(void) ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE); #if defined(CONFIG_ENV_OFFSET_OOB) - ret = get_nand_env_oob(&nand_info[0], &nand_env_oob_offset); + ret = get_nand_env_oob(nand_info[0], &nand_env_oob_offset); /* * If unable to read environment offset from NAND OOB then fall through * to the normal environment reading code below diff --git a/common/fb_nand.c b/common/fb_nand.c index c770effd799..e55ea3872fd 100644 --- a/common/fb_nand.c +++ b/common/fb_nand.c @@ -62,7 +62,7 @@ static int fb_nand_lookup(const char *partname, char *response, return -EINVAL; } - *mtd = &nand_info[dev->id->num]; + *mtd = nand_info[dev->id->num]; return 0; } diff --git a/common/splash_source.c b/common/splash_source.c index a09dd4b46eb..f86a78a4363 100644 --- a/common/splash_source.c +++ b/common/splash_source.c @@ -45,9 +45,9 @@ static int splash_sf_read_raw(u32 bmp_load_addr, int offset, size_t read_size) #ifdef CONFIG_CMD_NAND static int splash_nand_read_raw(u32 bmp_load_addr, int offset, size_t read_size) { - return nand_read_skip_bad(&nand_info[nand_curr_device], offset, + return nand_read_skip_bad(nand_info[nand_curr_device], offset, &read_size, NULL, - nand_info[nand_curr_device].size, + nand_info[nand_curr_device]->size, (u_char *)bmp_load_addr); } #else diff --git a/doc/README.nand b/doc/README.nand index 545d88ca689..96ffc489408 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -136,15 +136,8 @@ Configuration Options: Example of new init to be added to the end of an existing driver init: - /* - * devnum is the device number to be used in nand commands - * and in mtd->name. Must be less than - * CONFIG_SYS_NAND_MAX_DEVICE. - */ - mtd = &nand_info[devnum]; - /* chip is struct nand_chip, and is now provided by the driver. */ - mtd->priv = &chip; + mtd = &chip.mtd; /* * Fill in appropriate values if this driver uses these fields, @@ -165,7 +158,11 @@ Configuration Options: if (nand_scan_tail(mtd)) error out - if (nand_register(devnum)) + /* + * devnum is the device number to be used in nand commands + * and in mtd->name. Must be less than CONFIG_SYS_NAND_MAX_DEVICE. + */ + if (nand_register(devnum, mtd)) error out In addition to providing more flexibility to the driver, it reduces diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c index 4652541aeff..ab782bead42 100644 --- a/drivers/dfu/dfu_nand.c +++ b/drivers/dfu/dfu_nand.c @@ -39,12 +39,12 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu, if (nand_curr_device < 0 || nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || - !nand_info[nand_curr_device].name) { + !nand_info[nand_curr_device]->name) { printf("%s: invalid nand device\n", __func__); return -1; } - mtd = &nand_info[nand_curr_device]; + mtd = nand_info[nand_curr_device]; if (op == DFU_OP_READ) { ret = nand_read_skip_bad(mtd, start, &count, &actual, @@ -147,12 +147,12 @@ static int dfu_flush_medium_nand(struct dfu_entity *dfu) if (nand_curr_device < 0 || nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || - !nand_info[nand_curr_device].name) { + !nand_info[nand_curr_device]->name) { printf("%s: invalid nand device\n", __func__); return -1; } - mtd = &nand_info[nand_curr_device]; + mtd = nand_info[nand_curr_device]; memset(&opts, 0, sizeof(opts)); opts.offset = dfu->data.nand.start + dfu->offset + diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c index b8f68c0ea92..b280f87ccbc 100644 --- a/drivers/mtd/nand/am335x_spl_bch.c +++ b/drivers/mtd/nand/am335x_spl_bch.c @@ -16,7 +16,7 @@ #include static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; -struct mtd_info nand_info[1]; +static struct mtd_info *mtd; static struct nand_chip nand_chip; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ @@ -30,12 +30,12 @@ static struct nand_chip nand_chip; static int nand_command(int block, int page, uint32_t offs, u8 cmd) { - struct nand_chip *this = nand_info[0].priv; + struct nand_chip *this = mtd->priv; int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; - while (!this->dev_ready(&nand_info[0])) + while (!this->dev_ready(mtd)) ; /* Emulate NAND_CMD_READOOB */ @@ -45,11 +45,11 @@ static int nand_command(int block, int page, uint32_t offs, } /* Begin command latch cycle */ - hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); if (cmd == NAND_CMD_RESET) { - hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); - while (!this->dev_ready(&nand_info[0])) + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + while (!this->dev_ready(mtd)) ; return 0; } @@ -60,39 +60,39 @@ static int nand_command(int block, int page, uint32_t offs, /* Set ALE and clear CLE to start address cycle */ /* Column address */ - hwctrl(&nand_info[0], offs & 0xff, + hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ - hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ + hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ /* Row address */ if (cmd != NAND_CMD_RNDOUT) { - hwctrl(&nand_info[0], (page_addr & 0xff), + hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ - hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff), + hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE); /* A[27:20] */ #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE /* One more address cycle for devices > 128MiB */ - hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f, + hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE); /* A[31:28] */ #endif } - hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); if (cmd == NAND_CMD_READ0) { /* Latch in address */ - hwctrl(&nand_info[0], NAND_CMD_READSTART, + hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); - hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); /* * Wait a while for the data to be ready */ - while (!this->dev_ready(&nand_info[0])) + while (!this->dev_ready(mtd)) ; } else if (cmd == NAND_CMD_RNDOUT) { - hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE | + hwctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); - hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); } return 0; @@ -100,7 +100,7 @@ static int nand_command(int block, int page, uint32_t offs, static int nand_is_bad_block(int block) { - struct nand_chip *this = nand_info[0].priv; + struct nand_chip *this = mtd->priv; nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); @@ -121,7 +121,7 @@ static int nand_is_bad_block(int block) static int nand_read_page(int block, int page, void *dst) { - struct nand_chip *this = nand_info[0].priv; + struct nand_chip *this = mtd->priv; u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; @@ -137,15 +137,15 @@ static int nand_read_page(int block, int page, void *dst) nand_command(block, page, 0, NAND_CMD_READ0); for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - this->ecc.hwctl(&nand_info[0], NAND_ECC_READ); + this->ecc.hwctl(mtd, NAND_ECC_READ); nand_command(block, page, data_pos, NAND_CMD_RNDOUT); - this->read_buf(&nand_info[0], p, eccsize); + this->read_buf(mtd, p, eccsize); nand_command(block, page, oob_pos, NAND_CMD_RNDOUT); - this->read_buf(&nand_info[0], oob, eccbytes); - this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]); + this->read_buf(mtd, oob, eccbytes); + this->ecc.calculate(mtd, p, &ecc_calc[i]); data_pos += eccsize; oob_pos += eccbytes; @@ -164,7 +164,7 @@ static int nand_read_page(int block, int page, void *dst) * from correct_data(). We just hope that all possible errors * are corrected by this routine. */ - this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]); + this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); } return 0; @@ -223,13 +223,13 @@ void nand_init(void) /* * Init board specific nand support */ - nand_info[0].priv = &nand_chip; + mtd = &nand_chip.mtd; nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; board_nand_init(&nand_chip); if (nand_chip.select_chip) - nand_chip.select_chip(&nand_info[0], 0); + nand_chip.select_chip(mtd, 0); /* NAND chip may require reset after power-on */ nand_command(0, 0, 0, NAND_CMD_RESET); @@ -239,5 +239,5 @@ void nand_init(void) void nand_deselect(void) { if (nand_chip.select_chip) - nand_chip.select_chip(&nand_info[0], -1); + nand_chip.select_chip(mtd, -1); } diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c index caa7982d7e0..8f0ae4cb419 100644 --- a/drivers/mtd/nand/arasan_nfc.c +++ b/drivers/mtd/nand/arasan_nfc.c @@ -1101,7 +1101,7 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum) } nand->nand_base = arasan_nand_base; - mtd = &nand_info[0]; + mtd = &nand_chip->mtd; nand_chip->priv = nand; mtd->priv = nand_chip; @@ -1134,7 +1134,7 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum) goto fail; } - if (nand_register(devnum)) { + if (nand_register(devnum, mtd)) { printf("Nand Register Fail\n"); goto fail; } diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index e6b3fe8b2b1..9c2cb443440 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1238,17 +1238,17 @@ static int at91_nand_ready(struct mtd_info *mtd) #ifdef CONFIG_SPL_BUILD /* The following code is for SPL */ -static struct mtd_info mtd; +static struct mtd_info *mtd; static struct nand_chip nand_chip; static int nand_command(int block, int page, uint32_t offs, u8 cmd) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = mtd->priv; int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; - while (!this->dev_ready(&mtd)) + while (!this->dev_ready(mtd)) ; if (cmd == NAND_CMD_READOOB) { @@ -1256,24 +1256,24 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) cmd = NAND_CMD_READ0; } - hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) offs >>= 1; - hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE); - hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); - hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); - hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE); + hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE); + hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); + hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); + hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE); #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE - hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE); + hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE); #endif - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); - hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); - while (!this->dev_ready(&mtd)) + while (!this->dev_ready(mtd)) ; return 0; @@ -1281,7 +1281,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) static int nand_is_bad_block(int block) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = mtd->priv; nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); @@ -1304,7 +1304,7 @@ static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; static int nand_read_page(int block, int page, void *dst) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = mtd->priv; u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; @@ -1317,11 +1317,11 @@ static int nand_read_page(int block, int page, void *dst) for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { if (this->ecc.mode != NAND_ECC_SOFT) - this->ecc.hwctl(&mtd, NAND_ECC_READ); - this->read_buf(&mtd, p, eccsize); - this->ecc.calculate(&mtd, p, &ecc_calc[i]); + this->ecc.hwctl(mtd, NAND_ECC_READ); + this->read_buf(mtd, p, eccsize); + this->ecc.calculate(mtd, p, &ecc_calc[i]); } - this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); + this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); for (i = 0; i < ECCTOTAL; i++) ecc_code[i] = oob_data[nand_ecc_pos[i]]; @@ -1330,35 +1330,35 @@ static int nand_read_page(int block, int page, void *dst) p = dst; for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) - this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]); + this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); return 0; } int spl_nand_erase_one(int block, int page) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = mtd->priv; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; int page_addr; if (nand_chip.select_chip) - nand_chip.select_chip(&mtd, 0); + nand_chip.select_chip(mtd, 0); page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; - hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE); /* Row address */ - hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE); - hwctrl(&mtd, ((page_addr >> 8) & 0xff), + hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE); + hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE); #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE /* One more address cycle for devices > 128MiB */ - hwctrl(&mtd, (page_addr >> 16) & 0x0f, + hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE | NAND_CTRL_CHANGE); #endif - hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE); - while (!this->dev_ready(&mtd)) + while (!this->dev_ready(mtd)) ; nand_deselect(); @@ -1368,10 +1368,10 @@ int spl_nand_erase_one(int block, int page) #else static int nand_read_page(int block, int page, void *dst) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = mtd->priv; nand_command(block, page, 0, NAND_CMD_READ0); - atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page); + atmel_nand_pmecc_read_page(mtd, this, dst, 0, page); return 0; } @@ -1438,7 +1438,7 @@ int board_nand_init(struct nand_chip *nand) #ifdef CONFIG_ATMEL_NAND_HWECC #ifdef CONFIG_ATMEL_NAND_HW_PMECC - ret = atmel_pmecc_nand_init_params(nand, &mtd); + ret = atmel_pmecc_nand_init_params(nand, mtd); #endif #endif @@ -1447,9 +1447,10 @@ int board_nand_init(struct nand_chip *nand) void nand_init(void) { - mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE; - mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE; - mtd.priv = &nand_chip; + mtd = &nand_chip.mtd; + mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE; + mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE; + mtd->priv = &nand_chip; nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE; nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; board_nand_init(&nand_chip); @@ -1462,13 +1463,13 @@ void nand_init(void) #endif if (nand_chip.select_chip) - nand_chip.select_chip(&mtd, 0); + nand_chip.select_chip(mtd, 0); } void nand_deselect(void) { if (nand_chip.select_chip) - nand_chip.select_chip(&mtd, -1); + nand_chip.select_chip(mtd, -1); } #else @@ -1482,8 +1483,8 @@ static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST; int atmel_nand_chip_init(int devnum, ulong base_addr) { int ret; - struct mtd_info *mtd = &nand_info[devnum]; struct nand_chip *nand = &nand_chip[devnum]; + struct mtd_info *mtd = &nand->mtd; mtd->priv = nand; nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr; @@ -1521,7 +1522,7 @@ int atmel_nand_chip_init(int devnum, ulong base_addr) ret = nand_scan_tail(mtd); if (!ret) - nand_register(devnum); + nand_register(devnum, mtd); return ret; } diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 5894fcc4a8e..13d10aeaa83 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1263,7 +1263,7 @@ static int denali_init(struct denali_nand_info *denali) goto fail; } - ret = nand_register(0); + ret = nand_register(0, denali->mtd); fail: return ret; @@ -1282,7 +1282,7 @@ static int __board_nand_init(void) * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c * still provides a "struct mtd_info nand_info" instance. */ - denali->mtd = &nand_info[0]; + denali->mtd = &denali->nand.mtd; /* * In the future, these base addresses should be taken from diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index d457d53574a..523aee32a86 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -656,7 +656,7 @@ static void fsl_elbc_ctrl_init(void) static int fsl_elbc_chip_init(int devnum, u8 *addr) { - struct mtd_info *mtd = &nand_info[devnum]; + struct mtd_info *mtd; struct nand_chip *nand; struct fsl_elbc_mtd *priv; uint32_t br = 0, or = 0; @@ -697,6 +697,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) } nand = &priv->chip; + mtd = &nand->mtd; mtd->priv = nand; elbc_ctrl->chips[priv->bank] = priv; @@ -787,7 +788,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) if (ret) return ret; - ret = nand_register(devnum); + ret = nand_register(devnum, mtd); if (ret) return ret; diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 975b0d46131..d5fd3ee957c 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -880,7 +880,7 @@ static int fsl_ifc_sram_init(uint32_t ver) static int fsl_ifc_chip_init(int devnum, u8 *addr) { - struct mtd_info *mtd = &nand_info[devnum]; + struct mtd_info *mtd; struct nand_chip *nand; struct fsl_ifc_mtd *priv; struct nand_ecclayout *layout; @@ -925,6 +925,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) } nand = &priv->chip; + mtd = &nand->mtd; mtd->priv = nand; ifc_ctrl->chips[priv->bank] = priv; @@ -1044,7 +1045,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) if (ret) return ret; - ret = nand_register(devnum); + ret = nand_register(devnum, mtd); if (ret) return ret; return 0; diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c index e0e9e1ebd03..0b8b56ffa14 100644 --- a/drivers/mtd/nand/fsmc_nand.c +++ b/drivers/mtd/nand/fsmc_nand.c @@ -409,7 +409,7 @@ int fsmc_nand_switch_ecc(uint32_t eccstrength) * Nomadik SoC is currently supporting this fsmc_nand_switch_ecc() * function, as it doesn't need to switch to a different ECC layout. */ - mtd = &nand_info[nand_curr_device]; + mtd = nand_info[nand_curr_device]; nand = mtd->priv; /* Setup the ecc configurations again */ @@ -443,7 +443,6 @@ int fsmc_nand_init(struct nand_chip *nand) { static int chip_nr; struct mtd_info *mtd; - int i; u32 peripid2 = readl(&fsmc_regs_p->peripid2); fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) & @@ -480,7 +479,7 @@ int fsmc_nand_init(struct nand_chip *nand) (void __iomem *)CONFIG_SYS_NAND_BASE; nand->badblockbits = 7; - mtd = &nand_info[chip_nr++]; + mtd = &nand->mtd; mtd->priv = nand; switch (fsmc_version) { @@ -514,9 +513,8 @@ int fsmc_nand_init(struct nand_chip *nand) if (nand_scan_tail(mtd)) return -ENXIO; - for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - if (nand_register(i)) - return -ENXIO; + if (nand_register(chip_nr++, mtd)) + return -ENXIO; return 0; } diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c b/drivers/mtd/nand/lpc32xx_nand_mlc.c index 8156fe9613e..236b0becd79 100644 --- a/drivers/mtd/nand/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c @@ -539,13 +539,11 @@ static struct nand_chip lpc32xx_chip; void board_nand_init(void) { - /* we have only one device anyway */ - struct mtd_info *mtd = &nand_info[0]; - /* chip is struct nand_chip, and is now provided by the driver. */ - mtd->priv = &lpc32xx_chip; - /* to store return status in case we need to print it */ + struct mtd_info *mtd = &lpc32xx_chip.mtd; int ret; + mtd->priv = &lpc32xx_chip; + /* Set all BOARDSPECIFIC (actually core-specific) fields */ lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff; @@ -597,7 +595,7 @@ void board_nand_init(void) } /* chip is good, register it */ - ret = nand_register(0); + ret = nand_register(0, mtd); if (ret) error("nand_register returned %i", ret); } diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c index e621c3665e5..d8361304526 100644 --- a/drivers/mtd/nand/mpc5121_nfc.c +++ b/drivers/mtd/nand/mpc5121_nfc.c @@ -549,7 +549,6 @@ int board_nand_init(struct nand_chip *chip) int resettime = 0; int retval = 0; int rev; - static int chip_nr = 0; /* * Check SoC revision. This driver supports only NFC @@ -568,7 +567,7 @@ int board_nand_init(struct nand_chip *chip) return -ENOMEM; } - mtd = &nand_info[chip_nr++]; + mtd = &chip->mtd; mtd->priv = chip; chip->priv = prv; diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index f12b07e7adc..5e7b9cf9de9 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1164,7 +1164,7 @@ int board_nand_init(struct nand_chip *this) #endif /* structures must be linked */ - mtd = &host->mtd; + mtd = &this->mtd; mtd->priv = this; host->nand = this; diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c index 4d691d1a32c..0b3a604cf98 100644 --- a/drivers/mtd/nand/mxs_nand_spl.c +++ b/drivers/mtd/nand/mxs_nand_spl.c @@ -8,7 +8,7 @@ #include #include -static struct mtd_info mtd; +static struct mtd_info *mtd; static struct nand_chip nand_chip; static void mxs_nand_command(struct mtd_info *mtd, unsigned int command, @@ -147,14 +147,15 @@ static int mxs_nand_init(void) /* init mxs nand driver */ board_nand_init(&nand_chip); - mtd.priv = &nand_chip; + mtd = &nand_chip.mtd; + mtd->priv = &nand_chip; /* set mtd functions */ nand_chip.cmdfunc = mxs_nand_command; nand_chip.numchips = 1; /* identify flash device */ puts("NAND : "); - if (mxs_flash_ident(&mtd)) { + if (mxs_flash_ident(mtd)) { printf("Failed to identify\n"); return -1; } @@ -162,12 +163,12 @@ static int mxs_nand_init(void) /* allocate and initialize buffers */ nand_chip.buffers = memalign(ARCH_DMA_MINALIGN, sizeof(*nand_chip.buffers)); - nand_chip.oob_poi = nand_chip.buffers->databuf + mtd.writesize; + nand_chip.oob_poi = nand_chip.buffers->databuf + mtd->writesize; /* setup flash layout (does not scan as we override that) */ - mtd.size = nand_chip.chipsize; - nand_chip.scan_bbt(&mtd); + mtd->size = nand_chip.chipsize; + nand_chip.scan_bbt(mtd); - printf("%llu MiB\n", (mtd.size / (1024 * 1024))); + printf("%llu MiB\n", (mtd->size / (1024 * 1024))); return 0; } @@ -180,20 +181,20 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) if (mxs_nand_init()) return -ENODEV; - chip = mtd.priv; + chip = mtd->priv; page = offs >> chip->page_shift; - nand_page_per_block = mtd.erasesize / mtd.writesize; + nand_page_per_block = mtd->erasesize / mtd->writesize; debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page); - size = roundup(size, mtd.writesize); + size = roundup(size, mtd->writesize); while (sz < size) { - if (mxs_read_page_ecc(&mtd, buf, page) < 0) + if (mxs_read_page_ecc(mtd, buf, page) < 0) return -1; - sz += mtd.writesize; - offs += mtd.writesize; + sz += mtd->writesize; + offs += mtd->writesize; page++; - buf += mtd.writesize; + buf += mtd->writesize; /* * Check if we have crossed a block boundary, and if so @@ -204,10 +205,10 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) * Yes, new block. See if this block is good. If not, * loop until we find a good block. */ - while (is_badblock(&mtd, offs, 1)) { + while (is_badblock(mtd, offs, 1)) { page = page + nand_page_per_block; /* Check i we've reached the end of flash. */ - if (page >= mtd.size >> chip->page_shift) + if (page >= mtd->size >> chip->page_shift) return -ENOMEM; } } diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index 46f2654102c..ddd8249d59a 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; int nand_curr_device = -1; -struct mtd_info nand_info[CONFIG_SYS_MAX_NAND_DEVICE]; +struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE]; #ifndef CONFIG_SYS_NAND_SELF_INIT static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; @@ -30,15 +30,25 @@ static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8]; static unsigned long total_nand_size; /* in kiB */ -/* Register an initialized NAND mtd device with the U-Boot NAND command. */ -int nand_register(int devnum) +int nand_mtd_to_devnum(struct mtd_info *mtd) { - struct mtd_info *mtd; + int i; + for (i = 0; i < ARRAY_SIZE(nand_info); i++) { + if (mtd && nand_info[i] == mtd) + return i; + } + + return -ENODEV; +} + +/* Register an initialized NAND mtd device with the U-Boot NAND command. */ +int nand_register(int devnum, struct mtd_info *mtd) +{ if (devnum >= CONFIG_SYS_MAX_NAND_DEVICE) return -EINVAL; - mtd = &nand_info[devnum]; + nand_info[devnum] = mtd; sprintf(dev_name[devnum], "nand%d", devnum); mtd->name = dev_name[devnum]; @@ -62,8 +72,8 @@ int nand_register(int devnum) #ifndef CONFIG_SYS_NAND_SELF_INIT static void nand_init_chip(int i) { - struct mtd_info *mtd = &nand_info[i]; struct nand_chip *nand = &nand_chip[i]; + struct mtd_info *mtd = &nand->mtd; ulong base_addr = base_address[i]; int maxchips = CONFIG_SYS_NAND_MAX_CHIPS; @@ -79,7 +89,7 @@ static void nand_init_chip(int i) if (nand_scan(mtd, maxchips)) return; - nand_register(i); + nand_register(i, mtd); } #endif @@ -100,6 +110,7 @@ void nand_init(void) /* * Select the chip in the board/cpu specific driver */ - board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device); + board_nand_select_device(nand_info[nand_curr_device]->priv, + nand_curr_device); #endif } diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c index b3978e97556..bc6a09a1b5b 100644 --- a/drivers/mtd/nand/nand_spl_simple.c +++ b/drivers/mtd/nand/nand_spl_simple.c @@ -11,7 +11,7 @@ #include static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; -static struct mtd_info mtd; +static struct mtd_info *mtd; static struct nand_chip nand_chip; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ @@ -26,32 +26,32 @@ static struct nand_chip nand_chip; static int nand_command(int block, int page, uint32_t offs, u8 cmd) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = mtd->priv(); int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; - while (!this->dev_ready(&mtd)) + while (!this->dev_ready(mtd)) ; /* Begin command latch cycle */ - this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); /* Set ALE and clear CLE to start address cycle */ /* Column address */ - this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE); - this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */ - this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff, + this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE); + this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */ + this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff, NAND_CTRL_ALE); /* A[24:17] */ #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE /* One more address cycle for devices > 32MiB */ - this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f, + this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE); /* A[28:25] */ #endif /* Latch in address */ - this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); /* * Wait a while for the data to be ready */ - while (!this->dev_ready(&mtd)) + while (!this->dev_ready(mtd)) ; return 0; @@ -63,12 +63,12 @@ static int nand_command(int block, int page, uint32_t offs, static int nand_command(int block, int page, uint32_t offs, u8 cmd) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = mtd->priv; int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; - while (!this->dev_ready(&mtd)) + while (!this->dev_ready(mtd)) ; /* Emulate NAND_CMD_READOOB */ @@ -82,30 +82,30 @@ static int nand_command(int block, int page, uint32_t offs, offs >>= 1; /* Begin command latch cycle */ - hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); /* Set ALE and clear CLE to start address cycle */ /* Column address */ - hwctrl(&mtd, offs & 0xff, - NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ - hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ + hwctrl(mtd, offs & 0xff, + NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ + hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ /* Row address */ - hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ - hwctrl(&mtd, ((page_addr >> 8) & 0xff), - NAND_CTRL_ALE); /* A[27:20] */ + hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ + hwctrl(mtd, ((page_addr >> 8) & 0xff), + NAND_CTRL_ALE); /* A[27:20] */ #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE /* One more address cycle for devices > 128MiB */ - hwctrl(&mtd, (page_addr >> 16) & 0x0f, + hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE); /* A[31:28] */ #endif /* Latch in address */ - hwctrl(&mtd, NAND_CMD_READSTART, - NAND_CTRL_CLE | NAND_CTRL_CHANGE); - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + hwctrl(mtd, NAND_CMD_READSTART, + NAND_CTRL_CLE | NAND_CTRL_CHANGE); + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); /* * Wait a while for the data to be ready */ - while (!this->dev_ready(&mtd)) + while (!this->dev_ready(mtd)) ; return 0; @@ -114,7 +114,7 @@ static int nand_command(int block, int page, uint32_t offs, static int nand_is_bad_block(int block) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = mtd->priv; u_char bb_data[2]; nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, @@ -124,11 +124,11 @@ static int nand_is_bad_block(int block) * Read one byte (or two if it's a 16 bit chip). */ if (this->options & NAND_BUSWIDTH_16) { - this->read_buf(&mtd, bb_data, 2); + this->read_buf(mtd, bb_data, 2); if (bb_data[0] != 0xff || bb_data[1] != 0xff) return 1; } else { - this->read_buf(&mtd, bb_data, 1); + this->read_buf(mtd, bb_data, 1); if (bb_data[0] != 0xff) return 1; } @@ -139,7 +139,7 @@ static int nand_is_bad_block(int block) #if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST) static int nand_read_page(int block, int page, uchar *dst) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = mtd->priv; u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; @@ -150,7 +150,7 @@ static int nand_read_page(int block, int page, uchar *dst) uint8_t *p = dst; nand_command(block, page, 0, NAND_CMD_READOOB); - this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); + this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); nand_command(block, page, 0, NAND_CMD_READ0); /* Pick the ECC bytes out of the oob data */ @@ -159,10 +159,10 @@ static int nand_read_page(int block, int page, uchar *dst) for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - this->ecc.hwctl(&mtd, NAND_ECC_READ); - this->read_buf(&mtd, p, eccsize); - this->ecc.calculate(&mtd, p, &ecc_calc[i]); - this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]); + this->ecc.hwctl(mtd, NAND_ECC_READ); + this->read_buf(mtd, p, eccsize); + this->ecc.calculate(mtd, p, &ecc_calc[i]); + this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); } return 0; @@ -170,7 +170,7 @@ static int nand_read_page(int block, int page, uchar *dst) #else static int nand_read_page(int block, int page, void *dst) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = mtd->priv; u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; @@ -184,11 +184,11 @@ static int nand_read_page(int block, int page, void *dst) for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { if (this->ecc.mode != NAND_ECC_SOFT) - this->ecc.hwctl(&mtd, NAND_ECC_READ); - this->read_buf(&mtd, p, eccsize); - this->ecc.calculate(&mtd, p, &ecc_calc[i]); + this->ecc.hwctl(mtd, NAND_ECC_READ); + this->read_buf(mtd, p, eccsize); + this->ecc.calculate(mtd, p, &ecc_calc[i]); } - this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); + this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); /* Pick the ECC bytes out of the oob data */ for (i = 0; i < ECCTOTAL; i++) @@ -202,7 +202,7 @@ static int nand_read_page(int block, int page, void *dst) * from correct_data(). We just hope that all possible errors * are corrected by this routine. */ - this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]); + this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); } return 0; @@ -249,7 +249,8 @@ void nand_init(void) /* * Init board specific nand support */ - mtd.priv = &nand_chip; + mtd = &nand_chip.mtd; + mtd->priv = &nand_chip; nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; board_nand_init(&nand_chip); @@ -262,12 +263,12 @@ void nand_init(void) #endif if (nand_chip.select_chip) - nand_chip.select_chip(&mtd, 0); + nand_chip.select_chip(mtd, 0); } /* Unselect after operation */ void nand_deselect(void) { if (nand_chip.select_chip) - nand_chip.select_chip(&mtd, -1); + nand_chip.select_chip(mtd, -1); } diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 6a45d28a72d..f2ee90ee611 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -898,12 +898,12 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) if (nand_curr_device < 0 || nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || - !nand_info[nand_curr_device].name) { + !nand_info[nand_curr_device]->name) { printf("nand: error: no NAND devices found\n"); return -ENODEV; } - mtd = &nand_info[nand_curr_device]; + mtd = nand_info[nand_curr_device]; nand = mtd->priv; nand->options |= NAND_OWN_BUFFERS; nand->options &= ~NAND_SUBPAGE_READ; diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index d529467ebc8..125dbe7fd30 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -1477,9 +1477,9 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info) info->variant = pxa3xx_nand_get_variant(); for (cs = 0; cs < pdata->num_cs; cs++) { - mtd = &nand_info[cs]; chip = (struct nand_chip *) ((u8 *)&info[1] + sizeof(*host) * cs); + mtd = &chip->mtd; host = (struct pxa3xx_nand_host *)chip; info->host[cs] = host; host->mtd = mtd; @@ -1573,8 +1573,10 @@ static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info) continue; } - if (!ret) - probe_success = 1; + if (nand_register(cs, mtd)) + continue; + + probe_success = 1; } if (!probe_success) @@ -1601,6 +1603,4 @@ void board_nand_init(void) ret = pxa3xx_nand_probe(info); if (ret) return; - - nand_register(0); } diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c index a77db7b65df..b20fb1e10d9 100644 --- a/drivers/mtd/nand/tegra_nand.c +++ b/drivers/mtd/nand/tegra_nand.c @@ -976,7 +976,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum) dm_gpio_set_value(&config->wp_gpio, 1); - our_mtd = &nand_info[devnum]; + our_mtd = &nand->mtd; our_mtd->priv = nand; ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL); if (ret) @@ -989,7 +989,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum) if (ret) return ret; - ret = nand_register(devnum); + ret = nand_register(devnum, our_mtd); if (ret) return ret; diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c index 1faec5e1f23..3be8b02ccb7 100644 --- a/drivers/mtd/nand/vf610_nfc.c +++ b/drivers/mtd/nand/vf610_nfc.c @@ -630,7 +630,7 @@ struct vf610_nfc_config { static int vf610_nfc_nand_init(int devnum, void __iomem *addr) { - struct mtd_info *mtd = &nand_info[devnum]; + struct mtd_info *mtd; struct nand_chip *chip; struct vf610_nfc *nfc; int err = 0; @@ -653,6 +653,7 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) chip = &nfc->chip; nfc->regs = addr; + mtd = &chip->mtd; mtd->priv = chip; chip->priv = nfc; @@ -753,7 +754,7 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) if (err) return err; - err = nand_register(devnum); + err = nand_register(devnum, mtd); if (err) return err; diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index e2a8ed39198..00cdfd47b86 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -360,7 +360,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); - rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR, + rc = nand_read(nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR, &fw_length, (u_char *)addr); if (rc == -EUCLEAN) { printf("NAND read of FMAN firmware at offset 0x%x failed %d\n", diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index f975fd82091..fd130d5b820 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -139,8 +139,8 @@ void cs4340_upload_firmware(struct phy_device *phydev) size_t fw_length = CONFIG_CORTINA_FW_LENGTH; addr = malloc(CONFIG_CORTINA_FW_LENGTH); - ret = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR, - &fw_length, (u_char *)addr); + ret = nand_read(nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR, + &fw_length, (u_char *)addr); if (ret == -EUCLEAN) { printf("NAND read of Cortina firmware at 0x%x failed %d\n", CONFIG_CORTINA_FW_ADDR, ret); diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index ba038b11224..f771e94f91e 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -195,7 +195,7 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf) } retlen = NAND_CACHE_SIZE; - if (nand_read(&nand_info[id->num], nand_cache_off, + if (nand_read(nand_info[id->num], nand_cache_off, &retlen, nand_cache) != 0 || retlen != NAND_CACHE_SIZE) { printf("read_nand_cached: error reading nand off %#x size %d bytes\n", diff --git a/fs/jffs2/jffs2_nand_1pass.c b/fs/jffs2/jffs2_nand_1pass.c index 9b7af09fe39..d94c48f534b 100644 --- a/fs/jffs2/jffs2_nand_1pass.c +++ b/fs/jffs2/jffs2_nand_1pass.c @@ -796,7 +796,7 @@ jffs2_1pass_build_lists(struct part_info * part) u32 counterN = 0; struct mtdids *id = part->dev->id; - mtd = nand_info + id->num; + mtd = nand_info[id->num]; /* if we are building a list we need to refresh the cache. */ jffs_init_1pass_list(part); diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c index 5e9902519a7..6d8687148da 100644 --- a/fs/yaffs2/yaffs_uboot_glue.c +++ b/fs/yaffs2/yaffs_uboot_glue.c @@ -141,8 +141,6 @@ static const char *yaffs_error_str(void) } } -extern struct mtd_info nand_info[]; - void cmd_yaffs_tracemask(unsigned set, unsigned mask) { if (set) @@ -171,7 +169,7 @@ void cmd_yaffs_devconfig(char *_mp, int flash_dev, dev = calloc(1, sizeof(*dev)); mp = strdup(_mp); - mtd = &nand_info[flash_dev]; + mtd = nand_info[flash_dev]; if (!dev || !mp) { /* Alloc error */ @@ -260,9 +258,7 @@ void cmd_yaffs_dev_ls(void) dev = yaffs_next_dev(); if (!dev) return; - flash_dev = - ((unsigned) dev->driver_context - (unsigned) nand_info)/ - sizeof(nand_info[0]); + flash_dev = nand_mtd_to_devnum(dev->driver_context); printf("%-10s %5d 0x%05x 0x%05x %s", dev->param.name, flash_dev, dev->param.start_block, dev->param.end_block, diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 23072fdfc3c..fe8ac9da29d 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -659,6 +659,7 @@ struct nand_buffers { */ struct nand_chip { + struct mtd_info mtd; void __iomem *IO_ADDR_R; void __iomem *IO_ADDR_W; diff --git a/include/nand.h b/include/nand.h index eb2d76dbc64..a4f0f9253d8 100644 --- a/include/nand.h +++ b/include/nand.h @@ -33,15 +33,17 @@ extern void nand_init(void); #include #include +int nand_mtd_to_devnum(struct mtd_info *mtd); + #ifdef CONFIG_SYS_NAND_SELF_INIT void board_nand_init(void); -int nand_register(int devnum); +int nand_register(int devnum, struct mtd_info *mtd); #else extern int board_nand_init(struct nand_chip *nand); #endif extern int nand_curr_device; -extern struct mtd_info nand_info[]; +extern struct mtd_info *nand_info[]; static inline int nand_read(struct mtd_info *info, loff_t ofs, size_t *len, u_char *buf) -- cgit v1.3.1 From 17cb4b8f327eb983cef7c510fcf77f1635a00e48 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 30 May 2016 13:57:56 -0500 Subject: mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_data These functions are part of the Linux 4.6 sync. They are being added before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood --- board/esd/common/esd405ep_nand.c | 2 +- board/freescale/m5329evb/nand.c | 2 +- board/freescale/m5373evb/nand.c | 2 +- board/socrates/nand.c | 6 ++-- board/xes/common/actl_nand.c | 2 +- cmd/nand.c | 4 +-- drivers/mtd/nand/am335x_spl_bch.c | 6 ++-- drivers/mtd/nand/arasan_nfc.c | 19 +++++----- drivers/mtd/nand/atmel_nand.c | 55 ++++++++++++++-------------- drivers/mtd/nand/davinci_nand.c | 8 ++--- drivers/mtd/nand/denali.c | 4 +-- drivers/mtd/nand/fsl_elbc_nand.c | 33 +++++++++-------- drivers/mtd/nand/fsl_ifc_nand.c | 43 +++++++++++----------- drivers/mtd/nand/fsl_upm.c | 22 ++++++------ drivers/mtd/nand/fsmc_nand.c | 7 ++-- drivers/mtd/nand/kb9202_nand.c | 2 +- drivers/mtd/nand/kirkwood_nand.c | 2 +- drivers/mtd/nand/lpc32xx_nand_mlc.c | 2 -- drivers/mtd/nand/lpc32xx_nand_slc.c | 2 +- drivers/mtd/nand/mpc5121_nfc.c | 27 +++++++------- drivers/mtd/nand/mxc_nand.c | 51 +++++++++++++------------- drivers/mtd/nand/mxs_nand.c | 46 ++++++++++++------------ drivers/mtd/nand/mxs_nand_spl.c | 11 +++--- drivers/mtd/nand/nand.c | 5 ++- drivers/mtd/nand/nand_base.c | 72 ++++++++++++++++++------------------- drivers/mtd/nand/nand_bbt.c | 32 ++++++++--------- drivers/mtd/nand/nand_bch.c | 4 +-- drivers/mtd/nand/nand_plat.c | 4 +-- drivers/mtd/nand/nand_spl_simple.c | 11 +++--- drivers/mtd/nand/nand_util.c | 8 ++--- drivers/mtd/nand/ndfc.c | 14 ++++---- drivers/mtd/nand/omap_gpmc.c | 40 ++++++++++----------- drivers/mtd/nand/pxa3xx_nand.c | 34 ++++++++++-------- drivers/mtd/nand/s3c2410_nand.c | 4 +-- drivers/mtd/nand/tegra_nand.c | 29 ++++++++------- drivers/mtd/nand/vf610_nfc.c | 8 ++--- fs/yaffs2/yaffs_uboot_glue.c | 2 +- include/linux/mtd/nand.h | 20 +++++++++++ 38 files changed, 328 insertions(+), 317 deletions(-) (limited to 'include') diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c index f46936ca366..51ac10c8c0a 100644 --- a/board/esd/common/esd405ep_nand.c +++ b/board/esd/common/esd405ep_nand.c @@ -16,7 +16,7 @@ */ static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); if (ctrl & NAND_CTRL_CHANGE) { if ( ctrl & NAND_CLE ) out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE); diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index 8d88bc03c01..88496812bf8 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { - struct nand_chip *this = mtdinfo->priv; + struct nand_chip *this = mtd_to_nand(mtdinfo); volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; if (ctrl & NAND_CTRL_CHANGE) { diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c index 92cef2a97db..a96a59991f5 100644 --- a/board/freescale/m5373evb/nand.c +++ b/board/freescale/m5373evb/nand.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { - struct nand_chip *this = mtdinfo->priv; + struct nand_chip *this = mtd_to_nand(mtdinfo); volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; if (ctrl & NAND_CTRL_CHANGE) { diff --git a/board/socrates/nand.c b/board/socrates/nand.c index 15e6ea69446..a67d812c813 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -48,7 +48,7 @@ static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte) static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) { int i; - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); for (i = 0; i < len; i++) { out_be32(this->IO_ADDR_W, @@ -88,7 +88,7 @@ static u16 sc_nand_read_word(struct mtd_info *mtd) static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) { int i; - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int val; val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ; @@ -105,7 +105,7 @@ static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) */ static int sc_nand_device_ready(struct mtd_info *mtdinfo) { - struct nand_chip *this = mtdinfo->priv; + struct nand_chip *this = mtd_to_nand(mtdinfo); if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY) return 0; /* busy */ diff --git a/board/xes/common/actl_nand.c b/board/xes/common/actl_nand.c index bf896fe0cea..d1f3668bcbb 100644 --- a/board/xes/common/actl_nand.c +++ b/board/xes/common/actl_nand.c @@ -16,7 +16,7 @@ */ static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); ulong IO_ADDR_W; if (ctrl & NAND_CTRL_CHANGE) { diff --git a/cmd/nand.c b/cmd/nand.c index f1d5a1161d1..583a18f341a 100644 --- a/cmd/nand.c +++ b/cmd/nand.c @@ -159,7 +159,7 @@ static void do_nand_status(struct mtd_info *mtd) ulong off; int last_status = -1; - struct nand_chip *nand_chip = mtd->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); /* check the WP bit */ nand_chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); printf("device is %swrite protected\n", @@ -285,7 +285,7 @@ usage: static void nand_print_and_set_info(int idx) { struct mtd_info *mtd = nand_info[idx]; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); printf("Device %d: ", idx); if (chip->numchips > 1) diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c index b280f87ccbc..f8770e0ad8e 100644 --- a/drivers/mtd/nand/am335x_spl_bch.c +++ b/drivers/mtd/nand/am335x_spl_bch.c @@ -30,7 +30,7 @@ static struct nand_chip nand_chip; static int nand_command(int block, int page, uint32_t offs, u8 cmd) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; @@ -100,7 +100,7 @@ static int nand_command(int block, int page, uint32_t offs, static int nand_is_bad_block(int block) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); @@ -121,7 +121,7 @@ static int nand_is_bad_block(int block) static int nand_read_page(int block, int page, void *dst) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c index 8f0ae4cb419..6f3b71e0563 100644 --- a/drivers/mtd/nand/arasan_nfc.c +++ b/drivers/mtd/nand/arasan_nfc.c @@ -230,7 +230,7 @@ static void arasan_nand_enable_ecc(void) static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd) { u8 addrcycles; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); switch (curr_cmd->addr_cycles) { case NAND_ADDR_CYCL_NONE: @@ -264,7 +264,7 @@ static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd) static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); u32 reg_val, i, pktsize, pktnum; u32 *bufptr = (u32 *)buf; u32 timeout; @@ -441,7 +441,7 @@ static int arasan_nand_write_page_hwecc(struct mtd_info *mtd, u32 size = mtd->writesize; u32 rdcount = 0; u8 column_addr_cycles; - struct arasan_nand_info *nand = chip->priv; + struct arasan_nand_info *nand = nand_get_controller_data(chip); if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K) pktsize = ARASAN_NAND_PKTSIZE_1K; @@ -944,7 +944,7 @@ static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size) static u8 arasan_nand_read_byte(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); u32 size; u8 val; struct nand_onfi_params *p; @@ -976,8 +976,8 @@ static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command, int column, int page_addr) { u32 i, ret = 0; - struct nand_chip *chip = mtd->priv; - struct arasan_nand_info *nand = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct arasan_nand_info *nand = nand_get_controller_data(chip); curr_cmd = NULL; writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, @@ -1033,7 +1033,7 @@ static int arasan_nand_ecc_init(struct mtd_info *mtd) { int found = -1; u32 regval, eccpos_start, i; - struct nand_chip *nand_chip = mtd->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); nand_chip->ecc.mode = NAND_ECC_HW; nand_chip->ecc.hwctl = NULL; @@ -1101,9 +1101,8 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum) } nand->nand_base = arasan_nand_base; - mtd = &nand_chip->mtd; - nand_chip->priv = nand; - mtd->priv = nand_chip; + mtd = nand_to_mtd(nand_chip); + nand_set_controller_data(nand_chip, nand); /* Set the driver entry points for MTD */ nand_chip->cmdfunc = arasan_nand_cmd_function; diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 9c2cb443440..b1adff0e806 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -160,8 +160,8 @@ static int pmecc_data_alloc(struct atmel_nand_host *host) static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector) { - struct nand_chip *nand_chip = mtd->priv; - struct atmel_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct atmel_nand_host *host = nand_get_controller_data(nand_chip); int i; uint32_t value; @@ -177,8 +177,8 @@ static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector) static void pmecc_substitute(struct mtd_info *mtd) { - struct nand_chip *nand_chip = mtd->priv; - struct atmel_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct atmel_nand_host *host = nand_get_controller_data(nand_chip); int16_t __iomem *alpha_to = host->pmecc_alpha_to; int16_t __iomem *index_of = host->pmecc_index_of; int16_t *partial_syn = host->pmecc_partial_syn; @@ -227,8 +227,8 @@ static void pmecc_substitute(struct mtd_info *mtd) */ static void pmecc_get_sigma(struct mtd_info *mtd) { - struct nand_chip *nand_chip = mtd->priv; - struct atmel_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct atmel_nand_host *host = nand_get_controller_data(nand_chip); int16_t *lmu = host->pmecc_lmu; int16_t *si = host->pmecc_si; @@ -383,8 +383,8 @@ static void pmecc_get_sigma(struct mtd_info *mtd) static int pmecc_err_location(struct mtd_info *mtd) { - struct nand_chip *nand_chip = mtd->priv; - struct atmel_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct atmel_nand_host *host = nand_get_controller_data(nand_chip); const int cap = host->pmecc_corr_cap; const int num = 2 * cap + 1; int sector_size = host->pmecc_sector_size; @@ -437,8 +437,8 @@ static int pmecc_err_location(struct mtd_info *mtd) static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc, int sector_num, int extra_bytes, int err_nbr) { - struct nand_chip *nand_chip = mtd->priv; - struct atmel_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct atmel_nand_host *host = nand_get_controller_data(nand_chip); int i = 0; int byte_pos, bit_pos, sector_size, pos; uint32_t tmp; @@ -483,8 +483,8 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc, static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf, u8 *ecc) { - struct nand_chip *nand_chip = mtd->priv; - struct atmel_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct atmel_nand_host *host = nand_get_controller_data(nand_chip); int i, err_nbr, eccbytes; uint8_t *buf_pos; @@ -529,7 +529,7 @@ normal_check: static int atmel_nand_pmecc_read_page(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { - struct atmel_nand_host *host = chip->priv; + struct atmel_nand_host *host = nand_get_controller_data(chip); int eccsize = chip->ecc.size; uint8_t *oob = chip->oob_poi; uint32_t *eccpos = chip->ecc.layout->eccpos; @@ -571,7 +571,7 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required) { - struct atmel_nand_host *host = chip->priv; + struct atmel_nand_host *host = nand_get_controller_data(chip); uint32_t *eccpos = chip->ecc.layout->eccpos; int i, j; int timeout = PMECC_MAX_TIMEOUT_US; @@ -615,8 +615,8 @@ out: static void atmel_pmecc_core_init(struct mtd_info *mtd) { - struct nand_chip *nand_chip = mtd->priv; - struct atmel_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct atmel_nand_host *host = nand_get_controller_data(nand_chip); uint32_t val = 0; struct nand_ecclayout *ecc_layout; @@ -808,7 +808,8 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, struct atmel_nand_host *host; int cap, sector_size; - host = nand->priv = &pmecc_host; + host = &pmecc_host; + nand_set_controller_data(nand, host); nand->ecc.mode = NAND_ECC_HW; nand->ecc.calculate = NULL; @@ -1080,7 +1081,7 @@ static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *isnull) { - struct nand_chip *nand_chip = mtd->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); unsigned int ecc_status; unsigned int ecc_word, ecc_bit; @@ -1207,7 +1208,7 @@ int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd) static void at91_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); if (ctrl & NAND_CTRL_CHANGE) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; @@ -1243,7 +1244,7 @@ static struct nand_chip nand_chip; static int nand_command(int block, int page, uint32_t offs, u8 cmd) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; @@ -1281,7 +1282,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) static int nand_is_bad_block(int block) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); @@ -1304,7 +1305,7 @@ static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; static int nand_read_page(int block, int page, void *dst) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; @@ -1337,7 +1338,7 @@ static int nand_read_page(int block, int page, void *dst) int spl_nand_erase_one(int block, int page) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; int page_addr; @@ -1368,7 +1369,7 @@ int spl_nand_erase_one(int block, int page) #else static int nand_read_page(int block, int page, void *dst) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); nand_command(block, page, 0, NAND_CMD_READ0); atmel_nand_pmecc_read_page(mtd, this, dst, 0, page); @@ -1407,7 +1408,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) int at91_nand_wait_ready(struct mtd_info *mtd) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); udelay(this->chip_delay); @@ -1450,7 +1451,6 @@ void nand_init(void) mtd = &nand_chip.mtd; mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE; mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE; - mtd->priv = &nand_chip; nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE; nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; board_nand_init(&nand_chip); @@ -1484,9 +1484,8 @@ int atmel_nand_chip_init(int devnum, ulong base_addr) { int ret; struct nand_chip *nand = &nand_chip[devnum]; - struct mtd_info *mtd = &nand->mtd; + struct mtd_info *mtd = nand_to_mtd(nand); - mtd->priv = nand; nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr; #ifdef CONFIG_NAND_ECC_BCH diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index a3970745c95..5e0c7bf503f 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -54,7 +54,7 @@ */ static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); const u32 *nand = chip->IO_ADDR_R; /* Make sure that buf is 32 bit aligned */ @@ -99,7 +99,7 @@ static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); const u32 *nand = chip->IO_ADDR_W; /* Make sure that buf is 32 bit aligned */ @@ -144,7 +144,7 @@ static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf, static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; if (ctrl & NAND_CTRL_CHANGE) { @@ -223,7 +223,7 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16); u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) | diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 13d10aeaa83..d9bcd721f09 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -48,7 +48,8 @@ static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; * this macro allows us to convert from an MTD structure to our own * device context (denali) structure. */ -#define mtd_to_denali(m) container_of(m->priv, struct denali_nand_info, nand) +#define mtd_to_denali(m) \ + container_of(mtd_to_nand(m), struct denali_nand_info, nand) /* * These constants are defined by the driver to enable common driver @@ -1179,7 +1180,6 @@ static int denali_init(struct denali_nand_info *denali) denali->mtd->name = "denali-nand"; denali->mtd->owner = THIS_MODULE; - denali->mtd->priv = &denali->nand; /* register the driver with the NAND core subsystem */ denali->nand.select_chip = denali_select_chip; diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 523aee32a86..aafff67a5fb 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -154,8 +154,8 @@ static struct nand_bbt_descr bbt_mirror_descr = { */ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) { - struct nand_chip *chip = mtd->priv; - struct fsl_elbc_mtd *priv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); struct fsl_elbc_ctrl *ctrl = priv->ctrl; fsl_lbc_t *lbc = ctrl->regs; int buf_num; @@ -194,8 +194,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) */ static int fsl_elbc_run_command(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; - struct fsl_elbc_mtd *priv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); struct fsl_elbc_ctrl *ctrl = priv->ctrl; fsl_lbc_t *lbc = ctrl->regs; u32 timeo = (CONFIG_SYS_HZ * 10) / 1000; @@ -246,7 +246,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd) static void fsl_elbc_do_read(struct nand_chip *chip, int oob) { - struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); struct fsl_elbc_ctrl *ctrl = priv->ctrl; fsl_lbc_t *lbc = ctrl->regs; @@ -279,8 +279,8 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob) static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column, int page_addr) { - struct nand_chip *chip = mtd->priv; - struct fsl_elbc_mtd *priv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); struct fsl_elbc_ctrl *ctrl = priv->ctrl; fsl_lbc_t *lbc = ctrl->regs; @@ -489,8 +489,8 @@ static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip) */ static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) { - struct nand_chip *chip = mtd->priv; - struct fsl_elbc_mtd *priv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); struct fsl_elbc_ctrl *ctrl = priv->ctrl; unsigned int bufsize = mtd->writesize + mtd->oobsize; @@ -526,8 +526,8 @@ static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) */ static u8 fsl_elbc_read_byte(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; - struct fsl_elbc_mtd *priv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); struct fsl_elbc_ctrl *ctrl = priv->ctrl; /* If there are still bytes in the FCM, then use the next byte. */ @@ -543,8 +543,8 @@ static u8 fsl_elbc_read_byte(struct mtd_info *mtd) */ static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) { - struct nand_chip *chip = mtd->priv; - struct fsl_elbc_mtd *priv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); struct fsl_elbc_ctrl *ctrl = priv->ctrl; int avail; @@ -566,7 +566,7 @@ static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) */ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip) { - struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); struct fsl_elbc_ctrl *ctrl = priv->ctrl; fsl_lbc_t *lbc = ctrl->regs; @@ -697,8 +697,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) } nand = &priv->chip; - mtd = &nand->mtd; - mtd->priv = nand; + mtd = nand_to_mtd(nand); elbc_ctrl->chips[priv->bank] = priv; @@ -720,7 +719,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) nand->bbt_options = NAND_BBT_USE_FLASH; nand->controller = &elbc_ctrl->controller; - nand->priv = priv; + nand_set_controller_data(nand, priv); nand->ecc.read_page = fsl_elbc_read_page; nand->ecc.write_page = fsl_elbc_write_page; diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index d5fd3ee957c..f28602e14fb 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -222,8 +222,8 @@ static struct nand_bbt_descr bbt_mirror_descr = { */ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) { - struct nand_chip *chip = mtd->priv; - struct fsl_ifc_mtd *priv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); struct fsl_ifc_ctrl *ctrl = priv->ctrl; struct fsl_ifc_runtime *ifc = ctrl->regs.rregs; int buf_num; @@ -247,8 +247,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, unsigned int bufnum) { - struct nand_chip *chip = mtd->priv; - struct fsl_ifc_mtd *priv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2); u32 __iomem *main = (u32 *)addr; u8 __iomem *oob = addr + mtd->writesize; @@ -286,8 +286,8 @@ static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, */ static int fsl_ifc_run_command(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; - struct fsl_ifc_mtd *priv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); struct fsl_ifc_ctrl *ctrl = priv->ctrl; struct fsl_ifc_runtime *ifc = ctrl->regs.rregs; u32 timeo = (CONFIG_SYS_HZ * 10) / 1000; @@ -367,7 +367,7 @@ static void fsl_ifc_do_read(struct nand_chip *chip, int oob, struct mtd_info *mtd) { - struct fsl_ifc_mtd *priv = chip->priv; + struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); struct fsl_ifc_ctrl *ctrl = priv->ctrl; struct fsl_ifc_runtime *ifc = ctrl->regs.rregs; @@ -404,8 +404,8 @@ static void fsl_ifc_do_read(struct nand_chip *chip, static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column, int page_addr) { - struct nand_chip *chip = mtd->priv; - struct fsl_ifc_mtd *priv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); struct fsl_ifc_ctrl *ctrl = priv->ctrl; struct fsl_ifc_runtime *ifc = ctrl->regs.rregs; @@ -607,8 +607,8 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, */ static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) { - struct nand_chip *chip = mtd->priv; - struct fsl_ifc_mtd *priv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); struct fsl_ifc_ctrl *ctrl = priv->ctrl; unsigned int bufsize = mtd->writesize + mtd->oobsize; @@ -635,8 +635,8 @@ static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) */ static u8 fsl_ifc_read_byte(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; - struct fsl_ifc_mtd *priv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); struct fsl_ifc_ctrl *ctrl = priv->ctrl; unsigned int offset; @@ -659,8 +659,8 @@ static u8 fsl_ifc_read_byte(struct mtd_info *mtd) */ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; - struct fsl_ifc_mtd *priv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); struct fsl_ifc_ctrl *ctrl = priv->ctrl; uint16_t data; @@ -683,8 +683,8 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) */ static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len) { - struct nand_chip *chip = mtd->priv; - struct fsl_ifc_mtd *priv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); struct fsl_ifc_ctrl *ctrl = priv->ctrl; int avail; @@ -706,7 +706,7 @@ static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len) */ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) { - struct fsl_ifc_mtd *priv = chip->priv; + struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); struct fsl_ifc_ctrl *ctrl = priv->ctrl; struct fsl_ifc_runtime *ifc = ctrl->regs.rregs; u32 nand_fsr; @@ -739,7 +739,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { - struct fsl_ifc_mtd *priv = chip->priv; + struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); struct fsl_ifc_ctrl *ctrl = priv->ctrl; fsl_ifc_read_buf(mtd, buf, mtd->writesize); @@ -925,8 +925,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) } nand = &priv->chip; - mtd = &nand->mtd; - mtd->priv = nand; + mtd = nand_to_mtd(nand); ifc_ctrl->chips[priv->bank] = priv; @@ -955,7 +954,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) } nand->controller = &ifc_ctrl->controller; - nand->priv = priv; + nand_set_controller_data(nand, priv); nand->ecc.read_page = fsl_ifc_read_page; nand->ecc.write_page = fsl_ifc_write_page; diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c index 5426c321141..d2b388197bd 100644 --- a/drivers/mtd/nand/fsl_upm.c +++ b/drivers/mtd/nand/fsl_upm.c @@ -64,8 +64,8 @@ static void fun_wait(struct fsl_upm_nand *fun) #if CONFIG_SYS_NAND_MAX_CHIPS > 1 static void fun_select_chip(struct mtd_info *mtd, int chip_nr) { - struct nand_chip *chip = mtd->priv; - struct fsl_upm_nand *fun = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_upm_nand *fun = nand_get_controller_data(chip); if (chip_nr >= 0) { fun->chip_nr = chip_nr; @@ -79,8 +79,8 @@ static void fun_select_chip(struct mtd_info *mtd, int chip_nr) static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - struct nand_chip *chip = mtd->priv; - struct fsl_upm_nand *fun = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_upm_nand *fun = nand_get_controller_data(chip); void __iomem *io_addr; u32 mar; @@ -123,7 +123,7 @@ static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) static u8 upm_nand_read_byte(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); return in_8(chip->IO_ADDR_R); } @@ -131,8 +131,8 @@ static u8 upm_nand_read_byte(struct mtd_info *mtd) static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) { int i; - struct nand_chip *chip = mtd->priv; - struct fsl_upm_nand *fun = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_upm_nand *fun = nand_get_controller_data(chip); for (i = 0; i < len; i++) { out_8(chip->IO_ADDR_W, buf[i]); @@ -147,7 +147,7 @@ static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) { int i; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); for (i = 0; i < len; i++) buf[i] = in_8(chip->IO_ADDR_R); @@ -155,8 +155,8 @@ static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) static int nand_dev_ready(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; - struct fsl_upm_nand *fun = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct fsl_upm_nand *fun = nand_get_controller_data(chip); return fun->dev_ready(fun->chip_nr); } @@ -168,7 +168,7 @@ int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) fun->last_ctrl = NAND_CLE; - chip->priv = fun; + nand_set_controller_data(chip, fun); chip->chip_delay = fun->chip_delay; chip->ecc.mode = NAND_ECC_SOFT; chip->cmd_ctrl = fun_cmd_ctrl; diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c index 0b8b56ffa14..a1f2cbae331 100644 --- a/drivers/mtd/nand/fsmc_nand.c +++ b/drivers/mtd/nand/fsmc_nand.c @@ -165,7 +165,7 @@ static int count_written_bits(uint8_t *buff, int size, int max_bits) static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); ulong IO_ADDR_W; if (ctrl & NAND_CTRL_CHANGE) { @@ -410,7 +410,7 @@ int fsmc_nand_switch_ecc(uint32_t eccstrength) * function, as it doesn't need to switch to a different ECC layout. */ mtd = nand_info[nand_curr_device]; - nand = mtd->priv; + nand = mtd_to_nand(mtd); /* Setup the ecc configurations again */ if (eccstrength == 1) { @@ -479,8 +479,7 @@ int fsmc_nand_init(struct nand_chip *nand) (void __iomem *)CONFIG_SYS_NAND_BASE; nand->badblockbits = 7; - mtd = &nand->mtd; - mtd->priv = nand; + mtd = nand_to_mtd(nand); switch (fsmc_version) { case FSMC_VER8: diff --git a/drivers/mtd/nand/kb9202_nand.c b/drivers/mtd/nand/kb9202_nand.c index 22c56254079..e978cf8c824 100644 --- a/drivers/mtd/nand/kb9202_nand.c +++ b/drivers/mtd/nand/kb9202_nand.c @@ -35,7 +35,7 @@ */ static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); if (ctrl & NAND_CTRL_CHANGE) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c index d734113f640..d0a68bdcb9c 100644 --- a/drivers/mtd/nand/kirkwood_nand.c +++ b/drivers/mtd/nand/kirkwood_nand.c @@ -33,7 +33,7 @@ static u32 nand_mpp_backup[9] = { 0 }; static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - struct nand_chip *nc = mtd->priv; + struct nand_chip *nc = mtd_to_nand(mtd); u32 offs; if (cmd == NAND_CMD_NONE) diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c b/drivers/mtd/nand/lpc32xx_nand_mlc.c index 236b0becd79..94752089189 100644 --- a/drivers/mtd/nand/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c @@ -542,8 +542,6 @@ void board_nand_init(void) struct mtd_info *mtd = &lpc32xx_chip.mtd; int ret; - mtd->priv = &lpc32xx_chip; - /* Set all BOARDSPECIFIC (actually core-specific) fields */ lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff; diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c index 4e1be36654c..89b48cbed01 100644 --- a/drivers/mtd/nand/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/lpc32xx_nand_slc.c @@ -291,7 +291,7 @@ static void lpc32xx_nand_dma_configure(struct nand_chip *chip, static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf, int len, int read) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); u32 config; int ret; diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c index d8361304526..362d3932856 100644 --- a/drivers/mtd/nand/mpc5121_nfc.c +++ b/drivers/mtd/nand/mpc5121_nfc.c @@ -117,8 +117,8 @@ static void mpc5121_nfc_done(struct mtd_info *mtd); /* Read NFC register */ static inline u16 nfc_read(struct mtd_info *mtd, uint reg) { - struct nand_chip *chip = mtd->priv; - struct mpc5121_nfc_prv *prv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); return in_be16(prv->regs + reg); } @@ -126,8 +126,8 @@ static inline u16 nfc_read(struct mtd_info *mtd, uint reg) /* Write NFC register */ static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val) { - struct nand_chip *chip = mtd->priv; - struct mpc5121_nfc_prv *prv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); out_be16(prv->regs + reg, val); } @@ -211,7 +211,7 @@ static void mpc5121_nfc_done(struct mtd_info *mtd) /* Do address cycle(s) */ static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); u32 pagemask = chip->pagemask; if (column != -1) { @@ -283,8 +283,8 @@ static int mpc5121_nfc_dev_ready(struct mtd_info *mtd) static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command, int column, int page) { - struct nand_chip *chip = mtd->priv; - struct mpc5121_nfc_prv *prv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); prv->column = (column >= 0) ? column : 0; prv->spareonly = 0; @@ -357,8 +357,8 @@ static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command, static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset, u8 * buffer, uint size, int wr) { - struct nand_chip *nand = mtd->priv; - struct mpc5121_nfc_prv *prv = nand->priv; + struct nand_chip *nand = mtd_to_nand(mtd); + struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand); uint o, s, sbsize, blksize; /* @@ -410,8 +410,8 @@ static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset, static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char * buf, int len, int wr) { - struct nand_chip *chip = mtd->priv; - struct mpc5121_nfc_prv *prv = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); uint c = prv->column; uint l; @@ -489,7 +489,7 @@ static u16 mpc5121_nfc_read_word(struct mtd_info *mtd) static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd) { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); uint rcw_pagesize = 0; uint rcw_sparesize = 0; uint rcw_width; @@ -568,8 +568,7 @@ int board_nand_init(struct nand_chip *chip) } mtd = &chip->mtd; - mtd->priv = chip; - chip->priv = prv; + nand_set_controller_data(chip, prv); /* Read NFC configuration from Reset Config Word */ retval = mpc5121_nfc_read_hw_config(mtd); diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 5e7b9cf9de9..f935055afd6 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -351,8 +351,8 @@ static int mxc_nand_dev_ready(struct mtd_info *mtd) static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on) { - struct nand_chip *nand_chip = mtd->priv; - struct mxc_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct mxc_nand_host *host = nand_get_controller_data(nand_chip); #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) uint16_t tmp = readnfc(&host->regs->config1); @@ -386,7 +386,7 @@ static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, int page) { - struct mxc_nand_host *host = chip->priv; + struct mxc_nand_host *host = nand_get_controller_data(chip); uint8_t *buf = chip->oob_poi; int length = mtd->oobsize; int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; @@ -441,7 +441,7 @@ static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd, int oob_required, int page) { - struct mxc_nand_host *host = chip->priv; + struct mxc_nand_host *host = nand_get_controller_data(chip); int eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; @@ -486,7 +486,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd, int oob_required, int page) { - struct mxc_nand_host *host = chip->priv; + struct mxc_nand_host *host = nand_get_controller_data(chip); int n, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; @@ -550,7 +550,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd, static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, int page) { - struct mxc_nand_host *host = chip->priv; + struct mxc_nand_host *host = nand_get_controller_data(chip); int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; int length = mtd->oobsize; int i, len, status, steps = chip->ecc.steps; @@ -578,7 +578,7 @@ static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd, const uint8_t *buf, int oob_required) { - struct mxc_nand_host *host = chip->priv; + struct mxc_nand_host *host = nand_get_controller_data(chip); int eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; @@ -618,7 +618,7 @@ static int mxc_nand_write_page_syndrome(struct mtd_info *mtd, const uint8_t *buf, int oob_required) { - struct mxc_nand_host *host = chip->priv; + struct mxc_nand_host *host = nand_get_controller_data(chip); int i, n, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; @@ -661,8 +661,8 @@ static int mxc_nand_write_page_syndrome(struct mtd_info *mtd, static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) { - struct nand_chip *nand_chip = mtd->priv; - struct mxc_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct mxc_nand_host *host = nand_get_controller_data(nand_chip); uint32_t ecc_status = readl(&host->regs->ecc_status_result); int subpages = mtd->writesize / nand_chip->subpagesize; int pg2blk_shift = nand_chip->phys_erase_shift - @@ -700,8 +700,8 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) { - struct nand_chip *nand_chip = mtd->priv; - struct mxc_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct mxc_nand_host *host = nand_get_controller_data(nand_chip); /* * 1-Bit errors are automatically corrected in HW. No need for @@ -729,8 +729,8 @@ static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, static u_char mxc_nand_read_byte(struct mtd_info *mtd) { - struct nand_chip *nand_chip = mtd->priv; - struct mxc_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct mxc_nand_host *host = nand_get_controller_data(nand_chip); uint8_t ret = 0; uint16_t col; uint16_t __iomem *main_buf = @@ -769,8 +769,8 @@ static u_char mxc_nand_read_byte(struct mtd_info *mtd) static uint16_t mxc_nand_read_word(struct mtd_info *mtd) { - struct nand_chip *nand_chip = mtd->priv; - struct mxc_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct mxc_nand_host *host = nand_get_controller_data(nand_chip); uint16_t col, ret; uint16_t __iomem *p; @@ -821,8 +821,8 @@ static uint16_t mxc_nand_read_word(struct mtd_info *mtd) static void mxc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) { - struct nand_chip *nand_chip = mtd->priv; - struct mxc_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct mxc_nand_host *host = nand_get_controller_data(nand_chip); int n, col, i = 0; MTDDEBUG(MTD_DEBUG_LEVEL3, @@ -895,8 +895,8 @@ static void mxc_nand_write_buf(struct mtd_info *mtd, */ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) { - struct nand_chip *nand_chip = mtd->priv; - struct mxc_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct mxc_nand_host *host = nand_get_controller_data(nand_chip); int n, col, i = 0; MTDDEBUG(MTD_DEBUG_LEVEL3, @@ -955,8 +955,8 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) */ static void mxc_nand_select_chip(struct mtd_info *mtd, int chip) { - struct nand_chip *nand_chip = mtd->priv; - struct mxc_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct mxc_nand_host *host = nand_get_controller_data(nand_chip); switch (chip) { case -1: @@ -982,8 +982,8 @@ static void mxc_nand_select_chip(struct mtd_info *mtd, int chip) void mxc_nand_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) { - struct nand_chip *nand_chip = mtd->priv; - struct mxc_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct mxc_nand_host *host = nand_get_controller_data(nand_chip); MTDDEBUG(MTD_DEBUG_LEVEL3, "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", @@ -1165,13 +1165,12 @@ int board_nand_init(struct nand_chip *this) /* structures must be linked */ mtd = &this->mtd; - mtd->priv = this; host->nand = this; /* 5 us command delay time */ this->chip_delay = 5; - this->priv = host; + nand_set_controller_data(this, host); this->dev_ready = mxc_nand_dev_ready; this->cmdfunc = mxc_nand_command; this->select_chip = mxc_nand_select_chip; diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index b5bbd889ffc..7053ff26304 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -264,8 +264,8 @@ static int mxs_nand_wait_for_bch_complete(void) */ static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) { - struct nand_chip *nand = mtd->priv; - struct mxs_nand_info *nand_info = nand->priv; + struct nand_chip *nand = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(nand); struct mxs_dma_desc *d; uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; int ret; @@ -343,8 +343,8 @@ static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) */ static int mxs_nand_device_ready(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; - struct mxs_nand_info *nand_info = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(chip); struct mxs_gpmi_regs *gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE; uint32_t tmp; @@ -360,8 +360,8 @@ static int mxs_nand_device_ready(struct mtd_info *mtd) */ static void mxs_nand_select_chip(struct mtd_info *mtd, int chip) { - struct nand_chip *nand = mtd->priv; - struct mxs_nand_info *nand_info = nand->priv; + struct nand_chip *nand = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(nand); nand_info->cur_chip = chip; } @@ -410,8 +410,8 @@ static void mxs_nand_swap_block_mark(struct mtd_info *mtd, */ static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length) { - struct nand_chip *nand = mtd->priv; - struct mxs_nand_info *nand_info = nand->priv; + struct nand_chip *nand = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(nand); struct mxs_dma_desc *d; uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; int ret; @@ -494,8 +494,8 @@ rtn: static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int length) { - struct nand_chip *nand = mtd->priv; - struct mxs_nand_info *nand_info = nand->priv; + struct nand_chip *nand = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(nand); struct mxs_dma_desc *d; uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; int ret; @@ -559,7 +559,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, uint8_t *buf, int oob_required, int page) { - struct mxs_nand_info *nand_info = nand->priv; + struct mxs_nand_info *nand_info = nand_get_controller_data(nand); struct mxs_dma_desc *d; uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; uint32_t corrected = 0, failed = 0; @@ -709,7 +709,7 @@ static int mxs_nand_ecc_write_page(struct mtd_info *mtd, struct nand_chip *nand, const uint8_t *buf, int oob_required) { - struct mxs_nand_info *nand_info = nand->priv; + struct mxs_nand_info *nand_info = nand_get_controller_data(nand); struct mxs_dma_desc *d; uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; int ret; @@ -775,8 +775,8 @@ rtn: static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) { - struct nand_chip *chip = mtd->priv; - struct mxs_nand_info *nand_info = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(chip); int ret; if (ops->mode == MTD_OPS_RAW) @@ -800,8 +800,8 @@ static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from, static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) { - struct nand_chip *chip = mtd->priv; - struct mxs_nand_info *nand_info = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(chip); int ret; if (ops->mode == MTD_OPS_RAW) @@ -824,8 +824,8 @@ static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to, */ static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs) { - struct nand_chip *chip = mtd->priv; - struct mxs_nand_info *nand_info = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(chip); int ret; nand_info->marking_block_bad = 1; @@ -884,7 +884,7 @@ static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs) static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand, int page) { - struct mxs_nand_info *nand_info = nand->priv; + struct mxs_nand_info *nand_info = nand_get_controller_data(nand); /* * First, fill in the OOB buffer. If we're doing a raw read, we need to @@ -919,7 +919,7 @@ static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand, static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand, int page) { - struct mxs_nand_info *nand_info = nand->priv; + struct mxs_nand_info *nand_info = nand_get_controller_data(nand); uint8_t block_mark = 0; /* @@ -982,8 +982,8 @@ static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) */ static int mxs_nand_scan_bbt(struct mtd_info *mtd) { - struct nand_chip *nand = mtd->priv; - struct mxs_nand_info *nand_info = nand->priv; + struct nand_chip *nand = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(nand); struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; uint32_t tmp; @@ -1175,7 +1175,7 @@ int board_nand_init(struct nand_chip *nand) memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout)); - nand->priv = nand_info; + nand_set_controller_data(nand, nand_info); nand->options |= NAND_NO_SUBPAGE_WRITE; nand->cmd_ctrl = mxs_nand_cmd_ctrl; diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c index 0b3a604cf98..a8a3084d033 100644 --- a/drivers/mtd/nand/mxs_nand_spl.c +++ b/drivers/mtd/nand/mxs_nand_spl.c @@ -14,7 +14,7 @@ static struct nand_chip nand_chip; static void mxs_nand_command(struct mtd_info *mtd, unsigned int command, int column, int page_addr) { - register struct nand_chip *chip = mtd->priv; + register struct nand_chip *chip = mtd_to_nand(mtd); u32 timeo, time_start; /* write out the command to the device */ @@ -51,7 +51,7 @@ static void mxs_nand_command(struct mtd_info *mtd, unsigned int command, static int mxs_flash_ident(struct mtd_info *mtd) { - register struct nand_chip *chip = mtd->priv; + register struct nand_chip *chip = mtd_to_nand(mtd); int i; u8 mfg_id, dev_id; u8 id_data[8]; @@ -111,7 +111,7 @@ static int mxs_flash_ident(struct mtd_info *mtd) static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page) { - register struct nand_chip *chip = mtd->priv; + register struct nand_chip *chip = mtd_to_nand(mtd); int ret; chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page); @@ -125,7 +125,7 @@ static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page) static int is_badblock(struct mtd_info *mtd, loff_t offs, int allowbbt) { - register struct nand_chip *chip = mtd->priv; + register struct nand_chip *chip = mtd_to_nand(mtd); unsigned int block = offs >> chip->phys_erase_shift; unsigned int page = offs >> chip->page_shift; @@ -148,7 +148,6 @@ static int mxs_nand_init(void) /* init mxs nand driver */ board_nand_init(&nand_chip); mtd = &nand_chip.mtd; - mtd->priv = &nand_chip; /* set mtd functions */ nand_chip.cmdfunc = mxs_nand_command; nand_chip.numchips = 1; @@ -181,7 +180,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) if (mxs_nand_init()) return -ENODEV; - chip = mtd->priv; + chip = mtd_to_nand(mtd); page = offs >> chip->page_shift; nand_page_per_block = mtd->erasesize / mtd->writesize; diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index ddd8249d59a..f4493168539 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -73,14 +73,13 @@ int nand_register(int devnum, struct mtd_info *mtd) static void nand_init_chip(int i) { struct nand_chip *nand = &nand_chip[i]; - struct mtd_info *mtd = &nand->mtd; + struct mtd_info *mtd = nand_to_mtd(nand); ulong base_addr = base_address[i]; int maxchips = CONFIG_SYS_NAND_MAX_CHIPS; if (maxchips < 1) maxchips = 1; - mtd->priv = nand; nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr; if (board_nand_init(nand)) @@ -110,7 +109,7 @@ void nand_init(void) /* * Select the chip in the board/cpu specific driver */ - board_nand_select_device(nand_info[nand_curr_device]->priv, + board_nand_select_device(mtd_to_nand(nand_info[nand_curr_device]), nand_curr_device); #endif } diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 9e8fc1ffe24..92f581edd94 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -105,7 +105,7 @@ DEFINE_LED_TRIGGER(nand_led_trigger); static int check_offs_len(struct mtd_info *mtd, loff_t ofs, uint64_t len) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); int ret = 0; /* Start address must align on block boundary */ @@ -131,7 +131,7 @@ static int check_offs_len(struct mtd_info *mtd, */ static void nand_release_device(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); /* De-select the NAND device */ chip->select_chip(mtd, -1); @@ -145,7 +145,7 @@ static void nand_release_device(struct mtd_info *mtd) */ uint8_t nand_read_byte(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); return readb(chip->IO_ADDR_R); } @@ -158,7 +158,7 @@ uint8_t nand_read_byte(struct mtd_info *mtd) */ static uint8_t nand_read_byte16(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); } @@ -170,7 +170,7 @@ static uint8_t nand_read_byte16(struct mtd_info *mtd) */ static u16 nand_read_word(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); return readw(chip->IO_ADDR_R); } @@ -183,7 +183,7 @@ static u16 nand_read_word(struct mtd_info *mtd) */ static void nand_select_chip(struct mtd_info *mtd, int chipnr) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); switch (chipnr) { case -1: @@ -206,7 +206,7 @@ static void nand_select_chip(struct mtd_info *mtd, int chipnr) */ static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); chip->write_buf(mtd, &byte, 1); } @@ -220,7 +220,7 @@ static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) */ static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); uint16_t word = byte; /* @@ -287,7 +287,7 @@ static void iowrite16_rep(void *addr, void *buf, int len) */ void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); iowrite8_rep(chip->IO_ADDR_W, buf, len); } @@ -302,7 +302,7 @@ void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) */ void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); ioread8_rep(chip->IO_ADDR_R, buf, len); } @@ -317,7 +317,7 @@ void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) */ void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); u16 *p = (u16 *) buf; iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); @@ -333,7 +333,7 @@ void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) */ void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); u16 *p = (u16 *) buf; ioread16_rep(chip->IO_ADDR_R, p, len >> 1); @@ -350,7 +350,7 @@ void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) { int page, chipnr, res = 0, i = 0; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); u16 bad; if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) @@ -410,7 +410,7 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) */ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); struct mtd_oob_ops ops; uint8_t buf[2] = { 0, 0 }; int ret = 0, res, i = 0; @@ -460,7 +460,7 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) */ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); int res, ret = 0; if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { @@ -501,7 +501,7 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) */ static int nand_check_wp(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); /* Broken xD cards report WP despite being writable */ if (chip->options & NAND_BROKEN_XD) @@ -521,7 +521,7 @@ static int nand_check_wp(struct mtd_info *mtd) */ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); if (!chip->bbt) return 0; @@ -542,7 +542,7 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); if (!(chip->options & NAND_SKIP_BBTSCAN) && !(chip->options & NAND_BBT_SCANNED)) { @@ -560,7 +560,7 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, /* Wait for the ready pin, after a command. The timeout is caught later. */ void nand_wait_ready(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); u32 timeo = (CONFIG_SYS_HZ * 20) / 1000; u32 time_start; @@ -583,7 +583,7 @@ EXPORT_SYMBOL_GPL(nand_wait_ready); */ static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo) { - register struct nand_chip *chip = mtd->priv; + register struct nand_chip *chip = mtd_to_nand(mtd); u32 time_start; timeo = (CONFIG_SYS_HZ * timeo) / 1000; @@ -608,7 +608,7 @@ static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo) static void nand_command(struct mtd_info *mtd, unsigned int command, int column, int page_addr) { - register struct nand_chip *chip = mtd->priv; + register struct nand_chip *chip = mtd_to_nand(mtd); int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; /* Write out the command to the device */ @@ -711,7 +711,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, static void nand_command_lp(struct mtd_info *mtd, unsigned int command, int column, int page_addr) { - register struct nand_chip *chip = mtd->priv; + register struct nand_chip *chip = mtd_to_nand(mtd); /* Emulate NAND_CMD_READOOB */ if (command == NAND_CMD_READOOB) { @@ -835,7 +835,7 @@ static void panic_nand_get_device(struct nand_chip *chip, static int nand_get_device(struct mtd_info *mtd, int new_state) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); chip->state = new_state; return 0; } @@ -1332,7 +1332,7 @@ static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, */ static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); pr_debug("setting READ RETRY mode %d\n", retry_mode); @@ -1357,7 +1357,7 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) { int chipnr, page, realpage, col, bytes, aligned, oob_required; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); int ret = 0; uint32_t readlen = ops->len; uint32_t oobreadlen = ops->ooblen; @@ -1700,7 +1700,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) { int page, realpage, chipnr; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); struct mtd_ecc_stats stats; int readlen = ops->ooblen; int len; @@ -2139,7 +2139,7 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, struct mtd_oob_ops *ops) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); /* * Initialise to all 0xFF, to avoid the possibility of left over OOB @@ -2199,7 +2199,7 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) { int chipnr, realpage, page, blockmask, column; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); uint32_t writelen = ops->len; uint32_t oobwritelen = ops->ooblen; @@ -2328,7 +2328,7 @@ err_out: static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const uint8_t *buf) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); struct mtd_oob_ops ops; int ret; @@ -2388,7 +2388,7 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) { int chipnr, page, status, len; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); pr_debug("%s: to = 0x%08x, len = %i\n", __func__, (unsigned int)to, (int)ops->ooblen); @@ -2513,7 +2513,7 @@ out: */ static int single_erase(struct mtd_info *mtd, int page) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); /* Send commands to erase a block */ chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); @@ -2545,7 +2545,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, int allowbbt) { int page, status, pages_per_block, ret, chipnr; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); loff_t len; pr_debug("%s: start = 0x%012llx, len = %llu\n", @@ -2908,7 +2908,7 @@ ext_out: static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, @@ -3616,7 +3616,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, struct nand_flash_dev *table) { int i, nand_maf_id, nand_dev_id; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); struct nand_flash_dev *type; /* Set the default functions */ @@ -3680,7 +3680,7 @@ EXPORT_SYMBOL(nand_scan_ident); */ static bool nand_ecc_strength_good(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); struct nand_ecc_ctrl *ecc = &chip->ecc; int corr, ds_corr; @@ -3709,7 +3709,7 @@ static bool nand_ecc_strength_good(struct mtd_info *mtd) int nand_scan_tail(struct mtd_info *mtd) { int i; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); struct nand_ecc_ctrl *ecc = &chip->ecc; struct nand_buffers *nbuf; diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 00f28a41571..152f3bc78ef 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -173,7 +173,7 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num, struct nand_bbt_descr *td, int offs) { int res, ret = 0, i, j, act = 0; - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); size_t retlen, len, totlen; loff_t from; int bits = td->options & NAND_BBT_NRBITS_MSK; @@ -264,7 +264,7 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num, */ static int read_abs_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, int chip) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int res = 0, i; if (td->options & NAND_BBT_PERCHIP) { @@ -389,7 +389,7 @@ static u32 bbt_get_ver_offs(struct mtd_info *mtd, struct nand_bbt_descr *td) static void read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, struct nand_bbt_descr *md) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); /* Read the primary version, if available */ if (td->options & NAND_BBT_VERSION) { @@ -455,7 +455,7 @@ static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd, static int create_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd, int chip) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int i, numblocks, numpages; int startblock; loff_t from; @@ -524,7 +524,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, */ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int i, chips; int startblock, block, dir; int scanlen = mtd->writesize + mtd->oobsize; @@ -619,7 +619,7 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, struct nand_bbt_descr *md, int chipsel) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); struct erase_info einfo; int i, res, chip = 0; int bits, startblock, dir, page, offs, numblocks, sft, sftmsk; @@ -820,7 +820,7 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, */ static inline int nand_memory_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); return create_bbt(mtd, this->buffers->databuf, bd, -1); } @@ -839,7 +839,7 @@ static inline int nand_memory_bbt(struct mtd_info *mtd, struct nand_bbt_descr *b static int check_create(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd) { int i, chips, writeops, create, chipsel, res, res2; - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); struct nand_bbt_descr *td = this->bbt_td; struct nand_bbt_descr *md = this->bbt_md; struct nand_bbt_descr *rd, *rd2; @@ -963,7 +963,7 @@ static int check_create(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_desc */ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int i, j, chips, block, nrblocks, update; uint8_t oldval; @@ -1023,7 +1023,7 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) */ static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); u32 pattern_len; u32 bits; u32 table_size; @@ -1075,7 +1075,7 @@ static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd) */ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int len, res = 0; uint8_t *buf; struct nand_bbt_descr *td = this->bbt_td; @@ -1143,7 +1143,7 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) */ static int nand_update_bbt(struct mtd_info *mtd, loff_t offs) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int len, res = 0; int chip, chipsel; uint8_t *buf; @@ -1277,7 +1277,7 @@ static int nand_create_badblock_pattern(struct nand_chip *this) */ int nand_default_bbt(struct mtd_info *mtd) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int ret; /* Is a flash based bad block table requested? */ @@ -1313,7 +1313,7 @@ int nand_default_bbt(struct mtd_info *mtd) */ int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int block; block = (int)(offs >> this->bbt_erase_shift); @@ -1328,7 +1328,7 @@ int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs) */ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int block, res; block = (int)(offs >> this->bbt_erase_shift); @@ -1355,7 +1355,7 @@ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) */ int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int block, ret = 0; block = (int)(offs >> this->bbt_erase_shift); diff --git a/drivers/mtd/nand/nand_bch.c b/drivers/mtd/nand/nand_bch.c index 35d2140dabc..d7f6ce0acfd 100644 --- a/drivers/mtd/nand/nand_bch.c +++ b/drivers/mtd/nand/nand_bch.c @@ -41,7 +41,7 @@ struct nand_bch_control { int nand_bch_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf, unsigned char *code) { - const struct nand_chip *chip = mtd->priv; + const struct nand_chip *chip = mtd_to_nand(mtd); struct nand_bch_control *nbc = chip->ecc.priv; unsigned int i; @@ -67,7 +67,7 @@ int nand_bch_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf, int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf, unsigned char *read_ecc, unsigned char *calc_ecc) { - const struct nand_chip *chip = mtd->priv; + const struct nand_chip *chip = mtd_to_nand(mtd); struct nand_bch_control *nbc = chip->ecc.priv; unsigned int *errloc = nbc->errloc; int i, count; diff --git a/drivers/mtd/nand/nand_plat.c b/drivers/mtd/nand/nand_plat.c index 37a0206ad65..335c3e34714 100644 --- a/drivers/mtd/nand/nand_plat.c +++ b/drivers/mtd/nand/nand_plat.c @@ -25,7 +25,7 @@ static void plat_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); if (cmd == NAND_CMD_NONE) return; @@ -39,7 +39,7 @@ static void plat_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) #ifdef NAND_PLAT_DEV_READY static int plat_dev_ready(struct mtd_info *mtd) { - return NAND_PLAT_DEV_READY((struct nand_chip *)mtd->priv); + return NAND_PLAT_DEV_READY((struct nand_chip *)mtd_to_nand(mtd)); } #else # define plat_dev_ready NULL diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c index bc6a09a1b5b..b023e00313b 100644 --- a/drivers/mtd/nand/nand_spl_simple.c +++ b/drivers/mtd/nand/nand_spl_simple.c @@ -26,7 +26,7 @@ static struct nand_chip nand_chip; static int nand_command(int block, int page, uint32_t offs, u8 cmd) { - struct nand_chip *this = mtd->priv(); + struct nand_chip *this = mtd_to_nand(mtd); int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; while (!this->dev_ready(mtd)) @@ -63,7 +63,7 @@ static int nand_command(int block, int page, uint32_t offs, static int nand_command(int block, int page, uint32_t offs, u8 cmd) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; @@ -114,7 +114,7 @@ static int nand_command(int block, int page, uint32_t offs, static int nand_is_bad_block(int block) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); u_char bb_data[2]; nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, @@ -139,7 +139,7 @@ static int nand_is_bad_block(int block) #if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST) static int nand_read_page(int block, int page, uchar *dst) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; @@ -170,7 +170,7 @@ static int nand_read_page(int block, int page, uchar *dst) #else static int nand_read_page(int block, int page, void *dst) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; @@ -250,7 +250,6 @@ void nand_init(void) * Init board specific nand support */ mtd = &nand_chip.mtd; - mtd->priv = &nand_chip; nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; board_nand_init(&nand_chip); diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 90bf798ac00..9b61087e862 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -59,7 +59,7 @@ int nand_erase_opts(struct mtd_info *mtd, int percent_complete = -1; const char *mtd_device = mtd->name; struct mtd_oob_ops oob_opts; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); if ((opts->offset & (mtd->erasesize - 1)) != 0) { printf("Attempt to erase non block-aligned data\n"); @@ -217,7 +217,7 @@ int nand_lock(struct mtd_info *mtd, int tight) { int ret = 0; int status; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); /* select the NAND device */ chip->select_chip(mtd, 0); @@ -267,7 +267,7 @@ int nand_get_lock_status(struct mtd_info *mtd, loff_t offset) int ret = 0; int chipnr; int page; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); /* select the NAND device */ chipnr = (int)(offset >> chip->chip_shift); @@ -314,7 +314,7 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length, int chipnr; int status; int page; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); debug("nand_unlock%s: start: %08llx, length: %zd!\n", allexcept ? " (allexcept)" : "", start, length); diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 8a68cb0a67a..ee353c768b8 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -37,7 +37,7 @@ static int ndfc_cs[NDFC_MAX_BANKS]; static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; if (cmd == NAND_CMD_NONE) @@ -51,7 +51,7 @@ static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) static int ndfc_dev_ready(struct mtd_info *mtdinfo) { - struct nand_chip *this = mtdinfo->priv; + struct nand_chip *this = mtd_to_nand(mtdinfo); ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY); @@ -59,7 +59,7 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo) static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode) { - struct nand_chip *this = mtdinfo->priv; + struct nand_chip *this = mtd_to_nand(mtdinfo); ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; u32 ccr; @@ -71,7 +71,7 @@ static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode) static int ndfc_calculate_ecc(struct mtd_info *mtdinfo, const u_char *dat, u_char *ecc_code) { - struct nand_chip *this = mtdinfo->priv; + struct nand_chip *this = mtd_to_nand(mtdinfo); ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; u32 ecc; u8 *p = (u8 *)&ecc; @@ -96,7 +96,7 @@ static int ndfc_calculate_ecc(struct mtd_info *mtdinfo, */ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) { - struct nand_chip *this = mtdinfo->priv; + struct nand_chip *this = mtd_to_nand(mtdinfo); ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; uint32_t *p = (uint32_t *) buf; @@ -110,7 +110,7 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) */ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { - struct nand_chip *this = mtdinfo->priv; + struct nand_chip *this = mtd_to_nand(mtdinfo); ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; uint32_t *p = (uint32_t *) buf; @@ -124,7 +124,7 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len static uint8_t ndfc_read_byte(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT return (uint8_t) readw(chip->IO_ADDR_R); diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index f2ee90ee611..cac9eea2c1e 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -58,8 +58,8 @@ static struct omap_nand_info omap_nand_info[GPMC_MAX_CS]; static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, uint32_t ctrl) { - register struct nand_chip *this = mtd->priv; - struct omap_nand_info *info = this->priv; + register struct nand_chip *this = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(this); int cs = info->cs; /* @@ -85,8 +85,8 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, /* Check wait pin as dev ready indicator */ static int omap_dev_ready(struct mtd_info *mtd) { - register struct nand_chip *this = mtd->priv; - struct omap_nand_info *info = this->priv; + register struct nand_chip *this = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(this); return gpmc_cfg->status & (1 << (8 + info->ws)); } @@ -177,8 +177,8 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, __maybe_unused static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) { - struct nand_chip *nand = mtd->priv; - struct omap_nand_info *info = nand->priv; + struct nand_chip *nand = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(nand); unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0; unsigned int ecc_algo = 0; unsigned int bch_type = 0; @@ -262,8 +262,8 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code) { - struct nand_chip *chip = mtd->priv; - struct omap_nand_info *info = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(chip); uint32_t *ptr, val = 0; int8_t i = 0, j; @@ -392,7 +392,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le { int ret; uint32_t cnt; - struct omap_nand_info *info = chip->priv; + struct omap_nand_info *info = nand_get_controller_data(chip); ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs); if (ret < 0) @@ -417,7 +417,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); if (chip->options & NAND_BUSWIDTH_16) nand_read_buf16(mtd, buf, len); @@ -429,7 +429,7 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) { int ret; uint32_t head, tail; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); /* * If the destination buffer is unaligned, start with reading @@ -491,8 +491,8 @@ static void omap_reverse_list(u8 *list, unsigned int length) static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc) { - struct nand_chip *chip = mtd->priv; - struct omap_nand_info *info = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(chip); struct nand_ecc_ctrl *ecc = &chip->ecc; uint32_t error_count = 0, error_max; uint32_t error_loc[ELM_MAX_ERROR_COUNT]; @@ -652,8 +652,8 @@ static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data, int i, count; /* cannot correct more than 8 errors */ unsigned int errloc[8]; - struct nand_chip *chip = mtd->priv; - struct omap_nand_info *info = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(chip); count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc, NULL, errloc); @@ -691,8 +691,8 @@ static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data, */ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; - struct omap_nand_info *info = chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(chip); if (info->control) { free_bch(info->control); @@ -710,7 +710,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) */ static int omap_select_ecc_scheme(struct nand_chip *nand, enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) { - struct omap_nand_info *info = nand->priv; + struct omap_nand_info *info = nand_get_controller_data(nand); struct nand_ecclayout *ecclayout = &omap_ecclayout; int eccsteps = pagesize / SECTOR_BYTES; int i; @@ -904,7 +904,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) } mtd = nand_info[nand_curr_device]; - nand = mtd->priv; + nand = mtd_to_nand(mtd); nand->options |= NAND_OWN_BUFFERS; nand->options &= ~NAND_SUBPAGE_READ; /* Setup the ecc configurations again */ @@ -994,7 +994,7 @@ int board_nand_init(struct nand_chip *nand) omap_nand_info[cs].control = NULL; omap_nand_info[cs].cs = cs; omap_nand_info[cs].ws = wscfg[cs]; - nand->priv = &omap_nand_info[cs]; + nand_set_controller_data(nand, &omap_nand_info[cs]); nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; nand->chip_delay = 100; diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 125dbe7fd30..03bf0468f14 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -900,7 +900,8 @@ static int prepare_set_command(struct pxa3xx_nand_info *info, int command, static void nand_cmdfunc(struct mtd_info *mtd, unsigned command, int column, int page_addr) { - struct pxa3xx_nand_host *host = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct pxa3xx_nand_host *host = nand_get_controller_data(chip); struct pxa3xx_nand_info *info = host->info_data; int exec_cmd; @@ -960,7 +961,8 @@ static void nand_cmdfunc_extended(struct mtd_info *mtd, const unsigned command, int column, int page_addr) { - struct pxa3xx_nand_host *host = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct pxa3xx_nand_host *host = nand_get_controller_data(chip); struct pxa3xx_nand_info *info = host->info_data; int exec_cmd, ext_cmd_type; @@ -1091,7 +1093,7 @@ static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { - struct pxa3xx_nand_host *host = mtd->priv; + struct pxa3xx_nand_host *host = nand_get_controller_data(chip); struct pxa3xx_nand_info *info = host->info_data; chip->read_buf(mtd, buf, mtd->writesize); @@ -1117,7 +1119,8 @@ static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd) { - struct pxa3xx_nand_host *host = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct pxa3xx_nand_host *host = nand_get_controller_data(chip); struct pxa3xx_nand_info *info = host->info_data; char retval = 0xFF; @@ -1130,7 +1133,8 @@ static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd) static u16 pxa3xx_nand_read_word(struct mtd_info *mtd) { - struct pxa3xx_nand_host *host = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct pxa3xx_nand_host *host = nand_get_controller_data(chip); struct pxa3xx_nand_info *info = host->info_data; u16 retval = 0xFFFF; @@ -1143,7 +1147,8 @@ static u16 pxa3xx_nand_read_word(struct mtd_info *mtd) static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { - struct pxa3xx_nand_host *host = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct pxa3xx_nand_host *host = nand_get_controller_data(chip); struct pxa3xx_nand_info *info = host->info_data; int real_len = min_t(size_t, len, info->buf_count - info->buf_start); @@ -1154,7 +1159,8 @@ static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) static void pxa3xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) { - struct pxa3xx_nand_host *host = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct pxa3xx_nand_host *host = nand_get_controller_data(chip); struct pxa3xx_nand_info *info = host->info_data; int real_len = min_t(size_t, len, info->buf_count - info->buf_start); @@ -1169,7 +1175,8 @@ static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip) static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) { - struct pxa3xx_nand_host *host = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct pxa3xx_nand_host *host = nand_get_controller_data(chip); struct pxa3xx_nand_info *info = host->info_data; if (info->need_wait) { @@ -1210,7 +1217,7 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info) { struct pxa3xx_nand_host *host = info->host[info->cs]; struct mtd_info *mtd = host->mtd; - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0; info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0; @@ -1262,7 +1269,7 @@ static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host) int ret; mtd = info->host[info->cs]->mtd; - chip = mtd->priv; + chip = mtd_to_nand(mtd); /* configure default flash values */ info->reg_ndcr = 0x0; /* enable all interrupts */ @@ -1354,10 +1361,10 @@ static int pxa_ecc_init(struct pxa3xx_nand_info *info, static int pxa3xx_nand_scan(struct mtd_info *mtd) { - struct pxa3xx_nand_host *host = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct pxa3xx_nand_host *host = nand_get_controller_data(chip); struct pxa3xx_nand_info *info = host->info_data; struct pxa3xx_nand_platform_data *pdata = info->pdata; - struct nand_chip *chip = mtd->priv; int ret; uint16_t ecc_strength, ecc_step; @@ -1479,14 +1486,13 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info) for (cs = 0; cs < pdata->num_cs; cs++) { chip = (struct nand_chip *) ((u8 *)&info[1] + sizeof(*host) * cs); - mtd = &chip->mtd; + mtd = nand_to_mtd(chip); host = (struct pxa3xx_nand_host *)chip; info->host[cs] = host; host->mtd = mtd; host->cs = cs; host->info_data = info; host->read_id_bytes = 4; - mtd->priv = host; mtd->owner = THIS_MODULE; chip->ecc.read_page = pxa3xx_nand_read_page_hwecc; diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index b3a2a60bb26..2a0da6e3987 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -31,7 +31,7 @@ static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) { int i; - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); for (i = 0; i < len; i++) buf[i] = readb(this->IO_ADDR_R); @@ -40,7 +40,7 @@ static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) static void s3c24x0_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl); diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c index b20fb1e10d9..3eae4cbee20 100644 --- a/drivers/mtd/nand/tegra_nand.c +++ b/drivers/mtd/nand/tegra_nand.c @@ -143,10 +143,10 @@ static int nand_waitfor_cmd_completion(struct nand_ctlr *reg) */ static uint8_t read_byte(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); struct nand_drv *info; - info = (struct nand_drv *)chip->priv; + info = (struct nand_drv *)nand_get_controller_data(chip); writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID, &info->reg->command); @@ -169,8 +169,8 @@ static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { int i, s; unsigned int reg; - struct nand_chip *chip = mtd->priv; - struct nand_drv *info = (struct nand_drv *)chip->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip); for (i = 0; i < len; i += 4) { s = (len - i) > 4 ? 4 : len - i; @@ -194,11 +194,11 @@ static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len) */ static int nand_dev_ready(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); int reg_val; struct nand_drv *info; - info = (struct nand_drv *)chip->priv; + info = (struct nand_drv *)nand_get_controller_data(chip); reg_val = readl(&info->reg->status); if (reg_val & STATUS_RBSY0) @@ -245,10 +245,10 @@ static void nand_clear_interrupt_status(struct nand_ctlr *reg) static void nand_command(struct mtd_info *mtd, unsigned int command, int column, int page_addr) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); struct nand_drv *info; - info = (struct nand_drv *)chip->priv; + info = (struct nand_drv *)nand_get_controller_data(chip); /* * Write out the command to the device. @@ -512,7 +512,7 @@ static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip, return -EINVAL; } - info = (struct nand_drv *)chip->priv; + info = (struct nand_drv *)nand_get_controller_data(chip); config = &info->config; if (set_bus_width_page_size(config, ®_val)) return -EINVAL; @@ -662,7 +662,7 @@ static int nand_write_page_hwecc(struct mtd_info *mtd, int page; struct nand_drv *info; - info = (struct nand_drv *)chip->priv; + info = (struct nand_drv *)nand_get_controller_data(chip); page = (readl(&info->reg->addr_reg1) >> 16) | (readl(&info->reg->addr_reg2) << 16); @@ -702,7 +702,7 @@ static int nand_write_page_raw(struct mtd_info *mtd, int page; struct nand_drv *info; - info = (struct nand_drv *)chip->priv; + info = (struct nand_drv *)nand_get_controller_data(chip); page = (readl(&info->reg->addr_reg1) >> 16) | (readl(&info->reg->addr_reg2) << 16); @@ -734,7 +734,7 @@ static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip, if (((int)chip->oob_poi) & 0x03) return -EINVAL; - info = (struct nand_drv *)chip->priv; + info = (struct nand_drv *)nand_get_controller_data(chip); if (set_bus_width_page_size(&info->config, ®_val)) return -EINVAL; @@ -963,7 +963,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum) nand->ecc.strength = 1; nand->select_chip = nand_select_chip; nand->dev_ready = nand_dev_ready; - nand->priv = &nand_ctrl; + nand_set_controller_data(nand, &nand_ctrl); /* Disable subpage writes as we do not provide ecc->hwctl */ nand->options |= NAND_NO_SUBPAGE_WRITE; @@ -976,8 +976,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum) dm_gpio_set_value(&config->wp_gpio, 1); - our_mtd = &nand->mtd; - our_mtd->priv = nand; + our_mtd = nand_to_mtd(nand); ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL); if (ret) return ret; diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c index 3be8b02ccb7..a4d5a6205f3 100644 --- a/drivers/mtd/nand/vf610_nfc.c +++ b/drivers/mtd/nand/vf610_nfc.c @@ -155,8 +155,7 @@ struct vf610_nfc { enum vf610_nfc_alt_buf alt_buf; }; -#define mtd_to_nfc(_mtd) \ - (struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv +#define mtd_to_nfc(_mtd) nand_get_controller_data(mtd_to_nand(_mtd)) #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES) #define ECC_HW_MODE ECC_45_BYTE @@ -653,9 +652,8 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) chip = &nfc->chip; nfc->regs = addr; - mtd = &chip->mtd; - mtd->priv = chip; - chip->priv = nfc; + mtd = nand_to_mtd(chip); + nand_set_controller_data(chip, nfc); if (cfg.width == 16) chip->options |= NAND_BUSWIDTH_16; diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c index 6d8687148da..25aa6d15647 100644 --- a/fs/yaffs2/yaffs_uboot_glue.c +++ b/fs/yaffs2/yaffs_uboot_glue.c @@ -190,7 +190,7 @@ void cmd_yaffs_devconfig(char *_mp, int flash_dev, goto err; } - chip = mtd->priv; + chip = mtd_to_nand(mtd); /* Check for any conflicts */ yaffs_dev_rewind(); diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index fe8ac9da29d..e1df66b6257 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -740,6 +740,26 @@ struct nand_chip { void *priv; }; +static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) +{ + return container_of(mtd, struct nand_chip, mtd); +} + +static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) +{ + return &chip->mtd; +} + +static inline void *nand_get_controller_data(struct nand_chip *chip) +{ + return chip->priv; +} + +static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) +{ + chip->priv = priv; +} + /* * NAND Flash Manufacturer ID Codes */ -- cgit v1.3.1 From 81c772521ff26054a3fe75efa87d8daeae83e9b4 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 30 May 2016 13:57:57 -0500 Subject: mtd: nand: Add page argument to write_page() etc. This change is part of the Linux 4.6 sync. It is being done before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood --- drivers/mtd/nand/arasan_nfc.c | 3 ++- drivers/mtd/nand/atmel_nand.c | 2 +- drivers/mtd/nand/davinci_nand.c | 11 +++++++---- drivers/mtd/nand/denali.c | 6 ++++-- drivers/mtd/nand/fsl_elbc_nand.c | 5 +++-- drivers/mtd/nand/fsl_ifc_nand.c | 2 +- drivers/mtd/nand/lpc32xx_nand_mlc.c | 6 ++++-- drivers/mtd/nand/lpc32xx_nand_slc.c | 3 ++- drivers/mtd/nand/mxc_nand.c | 4 ++-- drivers/mtd/nand/mxs_nand.c | 2 +- drivers/mtd/nand/nand_base.c | 31 +++++++++++++++++++++---------- drivers/mtd/nand/pxa3xx_nand.c | 3 ++- drivers/mtd/nand/tegra_nand.c | 21 ++++----------------- drivers/mtd/nand/vf610_nfc.c | 2 +- include/linux/mtd/nand.h | 6 +++--- 15 files changed, 58 insertions(+), 49 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c index 6f3b71e0563..320cbaa859a 100644 --- a/drivers/mtd/nand/arasan_nfc.c +++ b/drivers/mtd/nand/arasan_nfc.c @@ -433,7 +433,8 @@ static void arasan_nand_fill_tx(const u8 *buf, int len) } static int arasan_nand_write_page_hwecc(struct mtd_info *mtd, - struct nand_chip *chip, const u8 *buf, int oob_required) + struct nand_chip *chip, const u8 *buf, int oob_required, + int page) { u32 reg_val, i, pktsize, pktnum; const u32 *bufptr = (const u32 *)buf; diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index b1adff0e806..a81b96d2813 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -569,7 +569,7 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd, static int atmel_nand_pmecc_write_page(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, - int oob_required) + int oob_required, int page) { struct atmel_nand_host *host = nand_get_controller_data(chip); uint32_t *eccpos = chip->ecc.layout->eccpos; diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 5e0c7bf503f..be9d666b682 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -380,10 +380,13 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip, chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); - if (unlikely(raw)) - status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required); - else - status = chip->ecc.write_page(mtd, chip, buf, oob_required); + if (unlikely(raw)) { + status = chip->ecc.write_page_raw(mtd, chip, buf, + oob_required, page); + } else { + status = chip->ecc.write_page(mtd, chip, buf, + oob_required, page); + } if (status < 0) { ret = status; diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index d9bcd721f09..3ae75451bea 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -866,7 +866,8 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip, * by write_page above. */ static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required) + const uint8_t *buf, int oob_required, + int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); @@ -890,7 +891,8 @@ static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, * write_page() function above. */ static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required) + const uint8_t *buf, int oob_required, + int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index aafff67a5fb..f621f141223 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -611,7 +611,8 @@ static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip, * waitfunc. */ static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required) + const uint8_t *buf, int oob_required, + int page) { fsl_elbc_write_buf(mtd, buf, mtd->writesize); fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize); @@ -626,7 +627,7 @@ static struct fsl_elbc_ctrl *elbc_ctrl; */ static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t offset, uint32_t data_len, - const uint8_t *buf, int oob_required) + const uint8_t *buf, int oob_required, int page) { fsl_elbc_write_buf(mtd, buf, mtd->writesize); fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize); diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index f28602e14fb..7001cbd62d0 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -755,7 +755,7 @@ static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip, * waitfunc. */ static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required) + const uint8_t *buf, int oob_required, int page) { fsl_ifc_write_buf(mtd, buf, mtd->writesize); fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize); diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c b/drivers/mtd/nand/lpc32xx_nand_mlc.c index 94752089189..42620298196 100644 --- a/drivers/mtd/nand/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c @@ -378,7 +378,8 @@ static int lpc32xx_read_oob(struct mtd_info *mtd, struct nand_chip *chip, */ static int lpc32xx_write_page_hwecc(struct mtd_info *mtd, - struct nand_chip *chip, const uint8_t *buf, int oob_required) + struct nand_chip *chip, const uint8_t *buf, int oob_required, + int page) { unsigned int i, status, timeout; struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi; @@ -435,7 +436,8 @@ static int lpc32xx_write_page_hwecc(struct mtd_info *mtd, */ static int lpc32xx_write_page_raw(struct mtd_info *mtd, - struct nand_chip *chip, const uint8_t *buf, int oob_required) + struct nand_chip *chip, const uint8_t *buf, int oob_required, + int page) { unsigned int i; struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi; diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c index 89b48cbed01..daa1e7a501d 100644 --- a/drivers/mtd/nand/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/lpc32xx_nand_slc.c @@ -486,7 +486,8 @@ static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, /* Reuse the logic from "nand_write_page_hwecc()" */ static int lpc32xx_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required) + const uint8_t *buf, int oob_required, + int page) { int i; uint8_t *ecc_calc = chip->buffers->ecccalc; diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index f935055afd6..d4e14b590a2 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -576,7 +576,7 @@ static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd, static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, - int oob_required) + int oob_required, int page) { struct mxc_nand_host *host = nand_get_controller_data(chip); int eccsize = chip->ecc.size; @@ -616,7 +616,7 @@ static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd, static int mxc_nand_write_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, - int oob_required) + int oob_required, int page) { struct mxc_nand_host *host = nand_get_controller_data(chip); int i, n, eccsize = chip->ecc.size; diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index 7053ff26304..5291330b911 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -707,7 +707,7 @@ rtn: */ static int mxs_nand_ecc_write_page(struct mtd_info *mtd, struct nand_chip *nand, const uint8_t *buf, - int oob_required) + int oob_required, int page) { struct mxs_nand_info *nand_info = nand_get_controller_data(nand); struct mxs_dma_desc *d; diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 92f581edd94..62e70a72aa6 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1840,11 +1840,13 @@ out: * @chip: nand chip info structure * @buf: data buffer * @oob_required: must write chip->oob_poi to OOB + * @page: page number to write * * Not for syndrome calculating ECC controllers, which use a special oob layout. */ static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required) + const uint8_t *buf, int oob_required, + int page) { chip->write_buf(mtd, buf, mtd->writesize); if (oob_required) @@ -1864,7 +1866,8 @@ static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, */ static int nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required) + const uint8_t *buf, int oob_required, + int page) { int eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; @@ -1901,9 +1904,11 @@ static int nand_write_page_raw_syndrome(struct mtd_info *mtd, * @chip: nand chip info structure * @buf: data buffer * @oob_required: must write chip->oob_poi to OOB + * @page: page number to write */ static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required) + const uint8_t *buf, int oob_required, + int page) { int i, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; @@ -1919,7 +1924,7 @@ static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, for (i = 0; i < chip->ecc.total; i++) chip->oob_poi[eccpos[i]] = ecc_calc[i]; - return chip->ecc.write_page_raw(mtd, chip, buf, 1); + return chip->ecc.write_page_raw(mtd, chip, buf, 1, page); } /** @@ -1928,9 +1933,11 @@ static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, * @chip: nand chip info structure * @buf: data buffer * @oob_required: must write chip->oob_poi to OOB + * @page: page number to write */ static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required) + const uint8_t *buf, int oob_required, + int page) { int i, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; @@ -1962,11 +1969,12 @@ static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, * @data_len: data length * @buf: data buffer * @oob_required: must write chip->oob_poi to OOB + * @page: page number to write */ static int nand_write_subpage_hwecc(struct mtd_info *mtd, struct nand_chip *chip, uint32_t offset, uint32_t data_len, const uint8_t *buf, - int oob_required) + int oob_required, int page) { uint8_t *oob_buf = chip->oob_poi; uint8_t *ecc_calc = chip->buffers->ecccalc; @@ -2027,7 +2035,8 @@ static int nand_write_subpage_hwecc(struct mtd_info *mtd, */ static int nand_write_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required) + const uint8_t *buf, int oob_required, + int page) { int i, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; @@ -2091,12 +2100,13 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, if (unlikely(raw)) status = chip->ecc.write_page_raw(mtd, chip, buf, - oob_required); + oob_required, page); else if (subpage) status = chip->ecc.write_subpage(mtd, chip, offset, data_len, - buf, oob_required); + buf, oob_required, page); else - status = chip->ecc.write_page(mtd, chip, buf, oob_required); + status = chip->ecc.write_page(mtd, chip, buf, oob_required, + page); if (status < 0) return status; @@ -2135,6 +2145,7 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, * @oob: oob data buffer * @len: oob data write length * @ops: oob ops structure + * @page: page number to write */ static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, struct mtd_oob_ops *ops) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 03bf0468f14..d3ac5391f15 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -1081,7 +1081,8 @@ static void nand_cmdfunc_extended(struct mtd_info *mtd, } static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd, - struct nand_chip *chip, const uint8_t *buf, int oob_required) + struct nand_chip *chip, const uint8_t *buf, int oob_required, + int page) { chip->write_buf(mtd, buf, mtd->writesize); chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c index 3eae4cbee20..2032f658129 100644 --- a/drivers/mtd/nand/tegra_nand.c +++ b/drivers/mtd/nand/tegra_nand.c @@ -657,16 +657,9 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, * @param buf data buffer */ static int nand_write_page_hwecc(struct mtd_info *mtd, - struct nand_chip *chip, const uint8_t *buf, int oob_required) + struct nand_chip *chip, const uint8_t *buf, int oob_required, + int page) { - int page; - struct nand_drv *info; - - info = (struct nand_drv *)nand_get_controller_data(chip); - - page = (readl(&info->reg->addr_reg1) >> 16) | - (readl(&info->reg->addr_reg2) << 16); - nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1); return 0; } @@ -697,15 +690,9 @@ static int nand_read_page_raw(struct mtd_info *mtd, * @param buf data buffer */ static int nand_write_page_raw(struct mtd_info *mtd, - struct nand_chip *chip, const uint8_t *buf, int oob_required) + struct nand_chip *chip, const uint8_t *buf, + int oob_required, int page) { - int page; - struct nand_drv *info; - - info = (struct nand_drv *)nand_get_controller_data(chip); - page = (readl(&info->reg->addr_reg1) >> 16) | - (readl(&info->reg->addr_reg2) << 16); - nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1); return 0; } diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c index a4d5a6205f3..dfbefc6bb90 100644 --- a/drivers/mtd/nand/vf610_nfc.c +++ b/drivers/mtd/nand/vf610_nfc.c @@ -607,7 +607,7 @@ static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, * ECC will be calculated automatically */ static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required) + const uint8_t *buf, int oob_required, int page) { struct vf610_nfc *nfc = mtd_to_nfc(mtd); diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index e1df66b6257..34945fda702 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -519,16 +519,16 @@ struct nand_ecc_ctrl { int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required); + const uint8_t *buf, int oob_required, int page); int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, uint32_t offs, uint32_t len, uint8_t *buf, int page); int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, uint32_t offset, uint32_t data_len, - const uint8_t *data_buf, int oob_required); + const uint8_t *data_buf, int oob_required, int page); int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required); + const uint8_t *buf, int oob_required, int page); int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, int page); int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, -- cgit v1.3.1 From ceee07b65875bb01bef55cba06940ef7afc1afba Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 30 May 2016 13:57:58 -0500 Subject: mtd: nand: Sync with Linux v4.6 Updates the NAND code to match Linux v4.6. The previous sync was from Linux v4.1 in commit d3963721d93fafa. Note that none of the individual NAND drivers tracked Linux closely enough to be synced themselves, other than manually applying a few cross-tree changes. Signed-off-by: Scott Wood Tested-by: Heiko Schocher --- drivers/mtd/nand/atmel_nand.c | 6 +- drivers/mtd/nand/davinci_nand.c | 6 +- drivers/mtd/nand/denali.c | 39 +++-- drivers/mtd/nand/denali.h | 1 - drivers/mtd/nand/denali_spl.c | 2 +- drivers/mtd/nand/mpc5121_nfc.c | 1 - drivers/mtd/nand/mxc_nand.c | 5 +- drivers/mtd/nand/mxc_nand_spl.c | 2 +- drivers/mtd/nand/mxs_nand.c | 2 +- drivers/mtd/nand/nand_base.c | 329 ++++++++++++++++++++++++++++------------ drivers/mtd/nand/nand_bbt.c | 30 ++-- drivers/mtd/nand/nand_bch.c | 29 ++-- drivers/mtd/nand/nand_ids.c | 10 +- drivers/mtd/nand/ndfc.c | 2 +- drivers/mtd/nand/omap_gpmc.c | 2 +- drivers/mtd/nand/s3c2410_nand.c | 2 +- drivers/mtd/nand/vf610_nfc.c | 1 - include/linux/mtd/mtd.h | 5 + include/linux/mtd/nand.h | 65 +++++--- include/linux/mtd/nand_bch.h | 10 +- 20 files changed, 347 insertions(+), 202 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index a81b96d2813..75e830724c7 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -513,7 +513,7 @@ normal_check: if (err_nbr == -1) { dev_err(host->dev, "PMECC: Too many errors\n"); mtd->ecc_stats.failed++; - return -EIO; + return -EBADMSG; } else { pmecc_correct_data(mtd, buf_pos, ecc, i, host->pmecc_bytes_per_sector, err_nbr); @@ -562,7 +562,7 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd, stat = pmecc_readl(host->pmecc, isr); if (stat != 0) if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0) - return -EIO; + return -EBADMSG; return 0; } @@ -1112,7 +1112,7 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, * We can't correct so many errors */ dev_warn(host->dev, "atmel_nand : multiple errors detected." " Unable to correct.\n"); - return -EIO; + return -EBADMSG; } /* if there's a single bit error : we can correct it */ diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index be9d666b682..48a8ca78e75 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -243,7 +243,7 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, "%d\n", find_byte, find_bit); return 1; } else { - return -1; + return -EBADMSG; } } else if (!(diff & (diff - 1))) { /* Single bit ECC error in the ECC itself, @@ -254,7 +254,7 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, } else { /* Uncorrectable error */ MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); - return -1; + return -EBADMSG; } } return 0; @@ -701,7 +701,7 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, return 0; } else if (iserror == ECC_STATE_TOO_MANY_ERRS) { val = __raw_readl(&davinci_emif_regs->nanderrval1); - return -1; + return -EBADMSG; } numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16) diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 3ae75451bea..601e744a08a 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -48,8 +48,10 @@ static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; * this macro allows us to convert from an MTD structure to our own * device context (denali) structure. */ -#define mtd_to_denali(m) \ - container_of(mtd_to_nand(m), struct denali_nand_info, nand) +static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) +{ + return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); +} /* * These constants are defined by the driver to enable common driver @@ -866,8 +868,7 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip, * by write_page above. */ static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required, - int page) + const uint8_t *buf, int oob_required, int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); @@ -891,8 +892,8 @@ static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, * write_page() function above. */ static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required, - int page) + const uint8_t *buf, int oob_required, + int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); @@ -991,7 +992,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, debug(" ECC error cause by erased block\n"); /* false alarm, return the 0xFF */ } else { - return -EIO; + return -EBADMSG; } } memcpy(buf, denali->buf.dma_buf, mtd->writesize); @@ -1176,12 +1177,13 @@ static struct nand_ecclayout nand_oob; static int denali_init(struct denali_nand_info *denali) { + struct mtd_info *mtd = nand_to_mtd(&denali->nand); int ret; denali_hw_init(denali); - denali->mtd->name = "denali-nand"; - denali->mtd->owner = THIS_MODULE; + mtd->name = "denali-nand"; + mtd->owner = THIS_MODULE; /* register the driver with the NAND core subsystem */ denali->nand.select_chip = denali_select_chip; @@ -1195,7 +1197,7 @@ static int denali_init(struct denali_nand_info *denali) * this is the first stage in a two step process to register * with the nand subsystem */ - if (nand_scan_ident(denali->mtd, denali->max_banks, NULL)) { + if (nand_scan_ident(mtd, denali->max_banks, NULL)) { ret = -ENXIO; goto fail; } @@ -1241,13 +1243,13 @@ static int denali_init(struct denali_nand_info *denali) nand_oob.eccbytes = denali->nand.ecc.bytes; denali->nand.ecc.layout = &nand_oob; - writel(denali->mtd->erasesize / denali->mtd->writesize, + writel(mtd->erasesize / mtd->writesize, denali->flash_reg + PAGES_PER_BLOCK); writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0, denali->flash_reg + DEVICE_WIDTH); - writel(denali->mtd->writesize, + writel(mtd->writesize, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); - writel(denali->mtd->oobsize, + writel(mtd->oobsize, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0) writel(1, denali->flash_reg + DEVICES_CONNECTED); @@ -1260,12 +1262,12 @@ static int denali_init(struct denali_nand_info *denali) denali->nand.ecc.read_oob = denali_read_oob; denali->nand.ecc.write_oob = denali_write_oob; - if (nand_scan_tail(denali->mtd)) { + if (nand_scan_tail(mtd)) { ret = -ENXIO; goto fail; } - ret = nand_register(0, denali->mtd); + ret = nand_register(0, mtd); fail: return ret; @@ -1279,13 +1281,6 @@ static int __board_nand_init(void) if (!denali) return -ENOMEM; - /* - * If CONFIG_SYS_NAND_SELF_INIT is defined, each driver is responsible - * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c - * still provides a "struct mtd_info nand_info" instance. - */ - denali->mtd = &denali->nand.mtd; - /* * In the future, these base addresses should be taken from * Device Tree or platform data. diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index db1457a680e..0e098bddf11 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -436,7 +436,6 @@ struct nand_buf { #define DT 3 struct denali_nand_info { - struct mtd_info *mtd; struct nand_chip nand; int flash_bank; /* currently selected chip */ int status; diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c index 15874135408..c6930325307 100644 --- a/drivers/mtd/nand/denali_spl.c +++ b/drivers/mtd/nand/denali_spl.c @@ -41,7 +41,7 @@ static int wait_for_irq(uint32_t irq_mask) if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) { debug("Uncorrected ECC detected\n"); - return -EIO; + return -EBADMSG; } if (intr_status & irq_mask) diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c index 362d3932856..8a8775c4c5b 100644 --- a/drivers/mtd/nand/mpc5121_nfc.c +++ b/drivers/mtd/nand/mpc5121_nfc.c @@ -100,7 +100,6 @@ #define NFC_WPC_UNLOCK (1 << 2) struct mpc5121_nfc_prv { - struct mtd_info mtd; struct nand_chip chip; int irq; void __iomem *regs; diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index d4e14b590a2..7221d0ba0d7 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -19,7 +19,6 @@ #define DRIVER_NAME "mxc_nand" struct mxc_nand_host { - struct mtd_info mtd; struct nand_chip *nand; struct mxc_nand_regs __iomem *regs; @@ -681,7 +680,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, mtd->writesize / nand_chip->subpagesize - subpages); } - return -1; + return -EBADMSG; } ecc_status >>= 4; subpages--; @@ -713,7 +712,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { MTDDEBUG(MTD_DEBUG_LEVEL0, "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); - return -1; + return -EBADMSG; } return 0; diff --git a/drivers/mtd/nand/mxc_nand_spl.c b/drivers/mtd/nand/mxc_nand_spl.c index 6ac2c96eeb6..841fb5bd963 100644 --- a/drivers/mtd/nand/mxc_nand_spl.c +++ b/drivers/mtd/nand/mxc_nand_spl.c @@ -232,7 +232,7 @@ static int nfc_read_page(unsigned int page_address, unsigned char *buf) nfc_nand_read_page(page_address); if (nfc_nand_check_ecc()) - return -1; + return -EBADMSG; src = (u32 *)&nfc->main_area[0][0]; dst = (u32 *)buf; diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index 5291330b911..7be1f86bc2b 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -961,7 +961,7 @@ static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand, * Thus, this function is only called when we want *all* blocks to look good, * so it *always* return success. */ -static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) +static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs) { return 0; } diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 62e70a72aa6..74c563c4955 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1,6 +1,4 @@ /* - * drivers/mtd/nand.c - * * Overview: * This is the generic MTD driver for NAND flash devices. It should be * capable of working with almost all NAND chips currently available. @@ -45,8 +43,6 @@ #include #include -static bool is_module_text_address(unsigned long addr) {return 0;} - /* Define default oob placement schemes for large and small page devices */ static struct nand_ecclayout nand_oob_8 = { .eccbytes = 3, @@ -343,13 +339,12 @@ void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) * nand_block_bad - [DEFAULT] Read bad block marker from the chip * @mtd: MTD device structure * @ofs: offset from device start - * @getchip: 0, if the chip is already selected * * Check, if the block is bad. */ -static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) +static int nand_block_bad(struct mtd_info *mtd, loff_t ofs) { - int page, chipnr, res = 0, i = 0; + int page, res = 0, i = 0; struct nand_chip *chip = mtd_to_nand(mtd); u16 bad; @@ -358,15 +353,6 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) page = (int)(ofs >> chip->page_shift) & chip->pagemask; - if (getchip) { - chipnr = (int)(ofs >> chip->chip_shift); - - nand_get_device(mtd, FL_READING); - - /* Select the NAND device */ - chip->select_chip(mtd, chipnr); - } - do { if (chip->options & NAND_BUSWIDTH_16) { chip->cmdfunc(mtd, NAND_CMD_READOOB, @@ -391,11 +377,6 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) i++; } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); - if (getchip) { - chip->select_chip(mtd, -1); - nand_release_device(mtd); - } - return res; } @@ -533,14 +514,12 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) * nand_block_checkbad - [GENERIC] Check if a block is marked bad * @mtd: MTD device structure * @ofs: offset from device start - * @getchip: 0, if the chip is already selected * @allowbbt: 1, if its allowed to access the bbt area * * Check, if the block is bad. Either by reading the bad block table or * calling of the scan function. */ -static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, - int allowbbt) +static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) { struct nand_chip *chip = mtd_to_nand(mtd); @@ -551,17 +530,22 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, } if (!chip->bbt) - return chip->block_bad(mtd, ofs, getchip); + return chip->block_bad(mtd, ofs); /* Return info from the table */ return nand_isbad_bbt(mtd, ofs, allowbbt); } -/* Wait for the ready pin, after a command. The timeout is caught later. */ +/** + * nand_wait_ready - [GENERIC] Wait for the ready pin after commands. + * @mtd: MTD device structure + * + * Wait for the ready pin after a command, and warn if a timeout occurs. + */ void nand_wait_ready(struct mtd_info *mtd) { struct nand_chip *chip = mtd_to_nand(mtd); - u32 timeo = (CONFIG_SYS_HZ * 20) / 1000; + u32 timeo = (CONFIG_SYS_HZ * 400) / 1000; u32 time_start; time_start = get_timer(0); @@ -571,6 +555,9 @@ void nand_wait_ready(struct mtd_info *mtd) if (chip->dev_ready(mtd)) break; } + + if (!chip->dev_ready(mtd)) + pr_warn("timeout while waiting for chip to become ready\n"); } EXPORT_SYMBOL_GPL(nand_wait_ready); @@ -871,15 +858,13 @@ static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, * @mtd: MTD device structure * @chip: NAND chip structure * - * Wait for command done. This applies to erase and program only. Erase can - * take up to 400ms and program up to 20ms according to general NAND and - * SmartMedia specs. + * Wait for command done. This applies to erase and program only. */ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) { - int status, state = chip->state; - unsigned long timeo = (state == FL_ERASING ? 400 : 20); + int status; + unsigned long timeo = 400; led_trigger_event(nand_led_trigger, LED_FULL); @@ -912,6 +897,135 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) return status; } +#define BITS_PER_BYTE 8 + +/** + * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data + * @buf: buffer to test + * @len: buffer length + * @bitflips_threshold: maximum number of bitflips + * + * Check if a buffer contains only 0xff, which means the underlying region + * has been erased and is ready to be programmed. + * The bitflips_threshold specify the maximum number of bitflips before + * considering the region is not erased. + * Note: The logic of this function has been extracted from the memweight + * implementation, except that nand_check_erased_buf function exit before + * testing the whole buffer if the number of bitflips exceed the + * bitflips_threshold value. + * + * Returns a positive number of bitflips less than or equal to + * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the + * threshold. + */ +static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold) +{ + const unsigned char *bitmap = buf; + int bitflips = 0; + int weight; + + for (; len && ((uintptr_t)bitmap) % sizeof(long); + len--, bitmap++) { + weight = hweight8(*bitmap); + bitflips += BITS_PER_BYTE - weight; + if (unlikely(bitflips > bitflips_threshold)) + return -EBADMSG; + } + + for (; len >= 4; len -= 4, bitmap += 4) { + weight = hweight32(*((u32 *)bitmap)); + bitflips += 32 - weight; + if (unlikely(bitflips > bitflips_threshold)) + return -EBADMSG; + } + + for (; len > 0; len--, bitmap++) { + weight = hweight8(*bitmap); + bitflips += BITS_PER_BYTE - weight; + if (unlikely(bitflips > bitflips_threshold)) + return -EBADMSG; + } + + return bitflips; +} + +/** + * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only + * 0xff data + * @data: data buffer to test + * @datalen: data length + * @ecc: ECC buffer + * @ecclen: ECC length + * @extraoob: extra OOB buffer + * @extraooblen: extra OOB length + * @bitflips_threshold: maximum number of bitflips + * + * Check if a data buffer and its associated ECC and OOB data contains only + * 0xff pattern, which means the underlying region has been erased and is + * ready to be programmed. + * The bitflips_threshold specify the maximum number of bitflips before + * considering the region as not erased. + * + * Note: + * 1/ ECC algorithms are working on pre-defined block sizes which are usually + * different from the NAND page size. When fixing bitflips, ECC engines will + * report the number of errors per chunk, and the NAND core infrastructure + * expect you to return the maximum number of bitflips for the whole page. + * This is why you should always use this function on a single chunk and + * not on the whole page. After checking each chunk you should update your + * max_bitflips value accordingly. + * 2/ When checking for bitflips in erased pages you should not only check + * the payload data but also their associated ECC data, because a user might + * have programmed almost all bits to 1 but a few. In this case, we + * shouldn't consider the chunk as erased, and checking ECC bytes prevent + * this case. + * 3/ The extraoob argument is optional, and should be used if some of your OOB + * data are protected by the ECC engine. + * It could also be used if you support subpages and want to attach some + * extra OOB data to an ECC chunk. + * + * Returns a positive number of bitflips less than or equal to + * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the + * threshold. In case of success, the passed buffers are filled with 0xff. + */ +int nand_check_erased_ecc_chunk(void *data, int datalen, + void *ecc, int ecclen, + void *extraoob, int extraooblen, + int bitflips_threshold) +{ + int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0; + + data_bitflips = nand_check_erased_buf(data, datalen, + bitflips_threshold); + if (data_bitflips < 0) + return data_bitflips; + + bitflips_threshold -= data_bitflips; + + ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); + if (ecc_bitflips < 0) + return ecc_bitflips; + + bitflips_threshold -= ecc_bitflips; + + extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen, + bitflips_threshold); + if (extraoob_bitflips < 0) + return extraoob_bitflips; + + if (data_bitflips) + memset(data, 0xff, datalen); + + if (ecc_bitflips) + memset(ecc, 0xff, ecclen); + + if (extraoob_bitflips) + memset(extraoob, 0xff, extraooblen); + + return data_bitflips + ecc_bitflips + extraoob_bitflips; +} +EXPORT_SYMBOL(nand_check_erased_ecc_chunk); + /** * nand_read_page_raw - [INTERN] read raw page data without ecc * @mtd: mtd info structure @@ -1103,6 +1217,16 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); + if (stat == -EBADMSG && + (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { + /* check for empty pages with bitflips */ + stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, + &chip->buffers->ecccode[i], + chip->ecc.bytes, + NULL, 0, + chip->ecc.strength); + } + if (stat < 0) { mtd->ecc_stats.failed++; } else { @@ -1152,6 +1276,15 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, int stat; stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); + if (stat == -EBADMSG && + (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { + /* check for empty pages with bitflips */ + stat = nand_check_erased_ecc_chunk(p, eccsize, + &ecc_code[i], eccbytes, + NULL, 0, + chip->ecc.strength); + } + if (stat < 0) { mtd->ecc_stats.failed++; } else { @@ -1204,6 +1337,15 @@ static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, chip->ecc.calculate(mtd, p, &ecc_calc[i]); stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); + if (stat == -EBADMSG && + (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { + /* check for empty pages with bitflips */ + stat = nand_check_erased_ecc_chunk(p, eccsize, + &ecc_code[i], eccbytes, + NULL, 0, + chip->ecc.strength); + } + if (stat < 0) { mtd->ecc_stats.failed++; } else { @@ -1231,6 +1373,7 @@ static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, int i, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; int eccsteps = chip->ecc.steps; + int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; uint8_t *p = buf; uint8_t *oob = chip->oob_poi; unsigned int max_bitflips = 0; @@ -1250,19 +1393,29 @@ static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, chip->read_buf(mtd, oob, eccbytes); stat = chip->ecc.correct(mtd, p, oob, NULL); - if (stat < 0) { - mtd->ecc_stats.failed++; - } else { - mtd->ecc_stats.corrected += stat; - max_bitflips = max_t(unsigned int, max_bitflips, stat); - } - oob += eccbytes; if (chip->ecc.postpad) { chip->read_buf(mtd, oob, chip->ecc.postpad); oob += chip->ecc.postpad; } + + if (stat == -EBADMSG && + (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { + /* check for empty pages with bitflips */ + stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, + oob - eccpadbytes, + eccpadbytes, + NULL, 0, + chip->ecc.strength); + } + + if (stat < 0) { + mtd->ecc_stats.failed++; + } else { + mtd->ecc_stats.corrected += stat; + max_bitflips = max_t(unsigned int, max_bitflips, stat); + } } /* Calculate remaining oob bytes */ @@ -1361,8 +1514,7 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, int ret = 0; uint32_t readlen = ops->len; uint32_t oobreadlen = ops->ooblen; - uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? - mtd->oobavail : mtd->oobsize; + uint32_t max_oobsize = mtd_oobavail(mtd, ops); uint8_t *bufpoi, *oob, *buf; int use_bufpoi; @@ -1712,10 +1864,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, stats = mtd->ecc_stats; - if (ops->mode == MTD_OPS_AUTO_OOB) - len = chip->ecc.layout->oobavail; - else - len = mtd->oobsize; + len = mtd_oobavail(mtd, ops); if (unlikely(ops->ooboffs >= len)) { pr_debug("%s: attempt to start read outside oob\n", @@ -1845,8 +1994,7 @@ out: * Not for syndrome calculating ECC controllers, which use a special oob layout. */ static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required, - int page) + const uint8_t *buf, int oob_required, int page) { chip->write_buf(mtd, buf, mtd->writesize); if (oob_required) @@ -1861,6 +2009,7 @@ static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, * @chip: nand chip info structure * @buf: data buffer * @oob_required: must write chip->oob_poi to OOB + * @page: page number to write * * We need a special oob layout and handling even when ECC isn't checked. */ @@ -1907,8 +2056,8 @@ static int nand_write_page_raw_syndrome(struct mtd_info *mtd, * @page: page number to write */ static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required, - int page) + const uint8_t *buf, int oob_required, + int page) { int i, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; @@ -2029,6 +2178,7 @@ static int nand_write_subpage_hwecc(struct mtd_info *mtd, * @chip: nand chip info structure * @buf: data buffer * @oob_required: must write chip->oob_poi to OOB + * @page: page number to write * * The hw generator calculates the error syndrome automatically. Therefore we * need a special oob layout and handling. @@ -2103,7 +2253,7 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, oob_required, page); else if (subpage) status = chip->ecc.write_subpage(mtd, chip, offset, data_len, - buf, oob_required, page); + buf, oob_required, page); else status = chip->ecc.write_page(mtd, chip, buf, oob_required, page); @@ -2145,7 +2295,6 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, * @oob: oob data buffer * @len: oob data write length * @ops: oob ops structure - * @page: page number to write */ static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, struct mtd_oob_ops *ops) @@ -2214,8 +2363,7 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, uint32_t writelen = ops->len; uint32_t oobwritelen = ops->ooblen; - uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? - mtd->oobavail : mtd->oobsize; + uint32_t oobmaxlen = mtd_oobavail(mtd, ops); uint8_t *oob = ops->oobbuf; uint8_t *buf = ops->datbuf; @@ -2404,10 +2552,7 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, pr_debug("%s: to = 0x%08x, len = %i\n", __func__, (unsigned int)to, (int)ops->ooblen); - if (ops->mode == MTD_OPS_AUTO_OOB) - len = chip->ecc.layout->oobavail; - else - len = mtd->oobsize; + len = mtd_oobavail(mtd, ops); /* Do not allow write past end of page */ if ((ops->ooboffs + ops->ooblen) > len) { @@ -2597,7 +2742,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, /* Check if we have a bad block, we do not erase bad blocks! */ if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) << - chip->page_shift, 0, allowbbt)) { + chip->page_shift, allowbbt)) { pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", __func__, page); instr->state = MTD_ERASE_FAILED; @@ -2684,7 +2829,20 @@ static void nand_sync(struct mtd_info *mtd) */ static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) { - return nand_block_checkbad(mtd, offs, 1, 0); + struct nand_chip *chip = mtd_to_nand(mtd); + int chipnr = (int)(offs >> chip->chip_shift); + int ret; + + /* Select the NAND device */ + nand_get_device(mtd, FL_READING); + chip->select_chip(mtd, chipnr); + + ret = nand_block_checkbad(mtd, offs, 0); + + chip->select_chip(mtd, -1); + nand_release_device(mtd); + + return ret; } /** @@ -2756,9 +2914,6 @@ static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, return -EINVAL; #endif - /* clear the sub feature parameters */ - memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN); - chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) *subfeature_param++ = chip->read_byte(mtd); @@ -3491,7 +3646,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (find_full_id_nand(mtd, chip, type, id_data, &busw)) goto ident_done; } else if (*dev_id == type->dev_id) { - break; + break; } } @@ -3514,10 +3669,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->chipsize = (uint64_t)type->chipsize << 20; - if (!type->pagesize && chip->init_size) { - /* Set the pagesize, oobsize, erasesize by the driver */ - busw = chip->init_size(mtd, chip, id_data); - } else if (!type->pagesize) { + if (!type->pagesize) { /* Decode parameters from extended ID */ nand_decode_ext_id(mtd, chip, id_data, &busw); } else { @@ -3621,7 +3773,6 @@ ident_done: * This is the first phase of the normal nand_scan() function. It reads the * flash ID and sets up MTD fields accordingly. * - * The mtd->owner field must be set to the module of the caller. */ int nand_scan_ident(struct mtd_info *mtd, int maxchips, struct nand_flash_dev *table) @@ -3797,7 +3948,7 @@ int nand_scan_tail(struct mtd_info *mtd) ecc->write_oob = nand_write_oob_std; if (!ecc->read_subpage) ecc->read_subpage = nand_read_subpage; - if (!ecc->write_subpage) + if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) ecc->write_subpage = nand_write_subpage_hwecc; case NAND_ECC_HW_SYNDROME: @@ -3875,10 +4026,8 @@ int nand_scan_tail(struct mtd_info *mtd) } /* See nand_bch_init() for details. */ - ecc->bytes = DIV_ROUND_UP( - ecc->strength * fls(8 * ecc->size), 8); - ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes, - &ecc->layout); + ecc->bytes = 0; + ecc->priv = nand_bch_init(mtd); if (!ecc->priv) { pr_warn("BCH ECC initialization failed!\n"); BUG(); @@ -3913,11 +4062,11 @@ int nand_scan_tail(struct mtd_info *mtd) * The number of bytes available for a client to place data into * the out of band area. */ - ecc->layout->oobavail = 0; - for (i = 0; ecc->layout->oobfree[i].length - && i < ARRAY_SIZE(ecc->layout->oobfree); i++) - ecc->layout->oobavail += ecc->layout->oobfree[i].length; - mtd->oobavail = ecc->layout->oobavail; + mtd->oobavail = 0; + if (ecc->layout) { + for (i = 0; ecc->layout->oobfree[i].length; i++) + mtd->oobavail += ecc->layout->oobfree[i].length; + } /* ECC sanity check: warn if it's too weak */ if (!nand_ecc_strength_good(mtd)) @@ -4002,18 +4151,6 @@ int nand_scan_tail(struct mtd_info *mtd) } EXPORT_SYMBOL(nand_scan_tail); -/* - * is_module_text_address() isn't exported, and it's mostly a pointless - * test if this is a module _anyway_ -- they'd have to try _really_ hard - * to call us from in-kernel code if the core NAND support is modular. - */ -#ifdef MODULE -#define caller_is_module() (1) -#else -#define caller_is_module() \ - is_module_text_address((unsigned long)__builtin_return_address(0)) -#endif - /** * nand_scan - [NAND Interface] Scan for the NAND device * @mtd: MTD device structure @@ -4021,19 +4158,12 @@ EXPORT_SYMBOL(nand_scan_tail); * * This fills out all the uninitialized function pointers with the defaults. * The flash ID is read and the mtd/chip structures are filled with the - * appropriate values. The mtd->owner field must be set to the module of the - * caller. + * appropriate values. */ int nand_scan(struct mtd_info *mtd, int maxchips) { int ret; - /* Many callers got this wrong, so check for it for a while... */ - if (!mtd->owner && caller_is_module()) { - pr_crit("%s called with NULL mtd->owner!\n", __func__); - BUG(); - } - ret = nand_scan_ident(mtd, maxchips, NULL); if (!ret) ret = nand_scan_tail(mtd); @@ -4041,9 +4171,6 @@ int nand_scan(struct mtd_info *mtd, int maxchips) } EXPORT_SYMBOL(nand_scan); -module_init(nand_base_init); -module_exit(nand_base_exit); - MODULE_LICENSE("GPL"); MODULE_AUTHOR("Steven J. Hill "); MODULE_AUTHOR("Thomas Gleixner "); diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 152f3bc78ef..74c4c9a3c80 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -1,6 +1,4 @@ /* - * drivers/mtd/nand_bbt.c - * * Overview: * Bad block table support for the NAND driver * @@ -65,7 +63,6 @@ #include #include #include -#include #include #include @@ -718,7 +715,7 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, /* Must we save the block contents? */ if (td->options & NAND_BBT_SAVECONTENT) { /* Make it block aligned */ - to &= ~((loff_t)((1 << this->bbt_erase_shift) - 1)); + to &= ~(((loff_t)1 << this->bbt_erase_shift) - 1); len = 1 << this->bbt_erase_shift; res = mtd_read(mtd, to, len, &retlen, buf); if (res < 0) { @@ -1073,15 +1070,15 @@ static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd) * The bad block table memory is allocated here. It must be freed by calling * the nand_free_bbt function. */ -int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) +static int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) { struct nand_chip *this = mtd_to_nand(mtd); - int len, res = 0; + int len, res; uint8_t *buf; struct nand_bbt_descr *td = this->bbt_td; struct nand_bbt_descr *md = this->bbt_md; - len = mtd->size >> (this->bbt_erase_shift + 2); + len = (mtd->size >> (this->bbt_erase_shift + 2)) ? : 1; /* * Allocate memory (2bit per block) and clear the memory bad block * table. @@ -1097,10 +1094,9 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) if (!td) { if ((res = nand_memory_bbt(mtd, bd))) { pr_err("nand_bbt: can't scan flash and build the RAM-based BBT\n"); - kfree(this->bbt); - this->bbt = NULL; + goto err; } - return res; + return 0; } verify_bbt_descr(mtd, td); verify_bbt_descr(mtd, md); @@ -1110,9 +1106,8 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) len += (len >> this->page_shift) * mtd->oobsize; buf = vmalloc(len); if (!buf) { - kfree(this->bbt); - this->bbt = NULL; - return -ENOMEM; + res = -ENOMEM; + goto err; } /* Is the bbt at a given page? */ @@ -1124,6 +1119,8 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) } res = check_create(mtd, buf, bd); + if (res) + goto err; /* Prevent the bbt regions from erasing / writing */ mark_bbt_region(mtd, td); @@ -1131,6 +1128,11 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) mark_bbt_region(mtd, md); vfree(buf); + return 0; + +err: + kfree(this->bbt); + this->bbt = NULL; return res; } @@ -1369,5 +1371,3 @@ int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs) return ret; } - -EXPORT_SYMBOL(nand_scan_bbt); diff --git a/drivers/mtd/nand/nand_bch.c b/drivers/mtd/nand/nand_bch.c index d7f6ce0acfd..c14520380e6 100644 --- a/drivers/mtd/nand/nand_bch.c +++ b/drivers/mtd/nand/nand_bch.c @@ -86,7 +86,7 @@ int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf, } } else if (count < 0) { printk(KERN_ERR "ecc unrecoverable error\n"); - count = -1; + count = -EBADMSG; } return count; } @@ -94,9 +94,6 @@ int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf, /** * nand_bch_init - [NAND Interface] Initialize NAND BCH error correction * @mtd: MTD block structure - * @eccsize: ecc block size in bytes - * @eccbytes: ecc length in bytes - * @ecclayout: output default layout * * Returns: * a pointer to a new NAND BCH control structure, or NULL upon failure @@ -110,14 +107,21 @@ int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf, * @eccsize = 512 (thus, m=13 is the smallest integer such that 2^m-1 > 512*8) * @eccbytes = 7 (7 bytes are required to store m*t = 13*4 = 52 bits) */ -struct nand_bch_control * -nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes, - struct nand_ecclayout **ecclayout) +struct nand_bch_control *nand_bch_init(struct mtd_info *mtd) { + struct nand_chip *nand = mtd_to_nand(mtd); unsigned int m, t, eccsteps, i; - struct nand_ecclayout *layout; + struct nand_ecclayout *layout = nand->ecc.layout; struct nand_bch_control *nbc = NULL; unsigned char *erased_page; + unsigned int eccsize = nand->ecc.size; + unsigned int eccbytes = nand->ecc.bytes; + unsigned int eccstrength = nand->ecc.strength; + + if (!eccbytes && eccstrength) { + eccbytes = DIV_ROUND_UP(eccstrength * fls(8 * eccsize), 8); + nand->ecc.bytes = eccbytes; + } if (!eccsize || !eccbytes) { printk(KERN_WARNING "ecc parameters not supplied\n"); @@ -145,7 +149,7 @@ nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes, eccsteps = mtd->writesize/eccsize; /* if no ecc placement scheme was provided, build one */ - if (!*ecclayout) { + if (!layout) { /* handle large page devices only */ if (mtd->oobsize < 64) { @@ -171,7 +175,7 @@ nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes, layout->oobfree[0].offset = 2; layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes; - *ecclayout = layout; + nand->ecc.layout = layout; } /* sanity checks */ @@ -179,7 +183,7 @@ nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes, printk(KERN_WARNING "eccsize %u is too large\n", eccsize); goto fail; } - if ((*ecclayout)->eccbytes != (eccsteps*eccbytes)) { + if (layout->eccbytes != (eccsteps*eccbytes)) { printk(KERN_WARNING "invalid ecc layout\n"); goto fail; } @@ -203,6 +207,9 @@ nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes, for (i = 0; i < eccbytes; i++) nbc->eccmask[i] ^= 0xff; + if (!eccstrength) + nand->ecc.strength = (eccbytes * 8) / fls(8 * eccsize); + return nbc; fail: nand_bch_free(nbc); diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index fdd00741dcb..561d2cd63bb 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -1,6 +1,4 @@ /* - * drivers/mtd/nandids.c - * * Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de) * * This program is free software; you can redistribute it and/or modify @@ -41,6 +39,10 @@ struct nand_flash_dev nand_flash_ids[] = { * listed by full ID. We list them first so that we can easily identify * the most specific match. */ + {"TC58NVG0S3E 1G 3.3V 8-bit", + { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} }, + SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), + 2 }, {"TC58NVG2S0F 4G 3.3V 8-bit", { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} }, SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) }, @@ -58,8 +60,8 @@ struct nand_flash_dev nand_flash_ids[] = { SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, {"H27UCG8T2ATR-BC 64G 3.3V 8-bit", { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, - SZ_8K, SZ_8K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K), - 4 }, + SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, + NAND_ECC_INFO(40, SZ_1K), 4 }, LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index ee353c768b8..0a9849e9bcd 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -1,6 +1,6 @@ /* * Overview: - * Platform independend driver for NDFC (NanD Flash Controller) + * Platform independent driver for NDFC (NanD Flash Controller) * integrated into IBM/AMCC PPC4xx cores * * (C) Copyright 2006-2009 diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index cac9eea2c1e..37c4341763d 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -163,7 +163,7 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, return 0; printf("Error: Bad compare! failed\n"); /* detected 2 bit error */ - return -1; + return -EBADMSG; } } return 0; diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index 2a0da6e3987..dd742a6351f 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -104,7 +104,7 @@ static int s3c24x0_nand_correct_data(struct mtd_info *mtd, u_char *dat, return 0; printf("s3c24x0_nand_correct_data: not implemented\n"); - return -1; + return -EBADMSG; } #endif diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c index dfbefc6bb90..f99bdaf94da 100644 --- a/drivers/mtd/nand/vf610_nfc.c +++ b/drivers/mtd/nand/vf610_nfc.c @@ -146,7 +146,6 @@ enum vf610_nfc_alt_buf { }; struct vf610_nfc { - struct mtd_info *mtd; struct nand_chip chip; void __iomem *regs; uint buf_offset; diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 9da77ec1441..cf20674549c 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -278,6 +278,11 @@ struct mtd_info { int usecount; }; +static inline int mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops) +{ + return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize; +} + int mtd_erase(struct mtd_info *mtd, struct erase_info *instr); #ifndef __UBOOT__ int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 34945fda702..b5a02c3382c 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -25,6 +25,8 @@ struct mtd_info; struct nand_flash_dev; +struct device_node; + /* Scan and identify a NAND device */ extern int nand_scan(struct mtd_info *mtd, int max_chips); /* @@ -144,6 +146,14 @@ typedef enum { /* Enable Hardware ECC before syndrome is read back from flash */ #define NAND_ECC_READSYN 2 +/* + * Enable generic NAND 'page erased' check. This check is only done when + * ecc.correct() returns -EBADMSG. + * Set this flag if your implementation does not fix bitflips in erased + * pages and you want to rely on the default implementation. + */ +#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) + /* Bit mask for flags passed to do_nand_read_ecc */ #define NAND_GET_DEVICE 0x80 @@ -179,6 +189,12 @@ typedef enum { /* Device supports subpage reads */ #define NAND_SUBPAGE_READ 0x00001000 +/* + * Some MLC NANDs need data scrambling to limit bitflips caused by repeated + * patterns. + */ +#define NAND_NEED_SCRAMBLING 0x00002000 + /* Options valid for Samsung large page devices */ #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG @@ -203,6 +219,11 @@ typedef enum { * before calling nand_scan_tail. */ #define NAND_BUSWIDTH_AUTO 0x00080000 +/* + * This option could be defined by controller drivers to protect against + * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers + */ +#define NAND_USE_BOUNCE_BUFFER 0x00100000 /* Options set by nand scan */ /* bbt has already been read */ @@ -292,15 +313,15 @@ struct nand_onfi_params { __le16 t_r; __le16 t_ccs; __le16 src_sync_timing_mode; - __le16 src_ssync_features; + u8 src_ssync_features; __le16 clk_pin_capacitance_typ; __le16 io_pin_capacitance_typ; __le16 input_pin_capacitance_typ; u8 input_pin_capacitance_max; u8 driver_strength_support; __le16 t_int_r; - __le16 t_ald; - u8 reserved4[7]; + __le16 t_adl; + u8 reserved4[8]; /* vendor */ __le16 vendor_revision; @@ -423,7 +444,7 @@ struct nand_jedec_params { __le16 input_pin_capacitance_typ; __le16 clk_pin_capacitance_typ; u8 driver_strength_support; - __le16 t_ald; + __le16 t_adl; u8 reserved4[36]; /* ECC and endurance block */ @@ -466,12 +487,19 @@ struct nand_hw_control { * @total: total number of ECC bytes per page * @prepad: padding information for syndrome based ECC generators * @postpad: padding information for syndrome based ECC generators + * @options: ECC specific options (see NAND_ECC_XXX flags defined above) * @layout: ECC layout control struct pointer * @priv: pointer to private ECC control data * @hwctl: function to control hardware ECC generator. Must only * be provided if an hardware ECC is available * @calculate: function for ECC calculation or readback from ECC hardware - * @correct: function for ECC correction, matching to ECC generator (sw/hw) + * @correct: function for ECC correction, matching to ECC generator (sw/hw). + * Should return a positive number representing the number of + * corrected bitflips, -EBADMSG if the number of bitflips exceed + * ECC strength, or any other error code if the error is not + * directly related to correction. + * If -EBADMSG is returned the input buffers should be left + * untouched. * @read_page_raw: function to read a raw page without ECC. This function * should hide the specific layout used by the ECC * controller and always return contiguous in-band and @@ -509,6 +537,7 @@ struct nand_ecc_ctrl { int strength; int prepad; int postpad; + unsigned int options; struct nand_ecclayout *layout; void *priv; void (*hwctl)(struct mtd_info *mtd, int mode); @@ -556,6 +585,7 @@ struct nand_buffers { /** * struct nand_chip - NAND Private Flash Chip Data + * @mtd: MTD device registered to the MTD framework * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the * flash device * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the @@ -571,10 +601,6 @@ struct nand_buffers { * @block_markbad: [REPLACEABLE] mark a block bad * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling * ALE/CLE/nCE. Also used to write command and address - * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting - * mtd->oobsize, mtd->writesize and so on. - * @id_data contains the 8 bytes values of NAND_CMD_READID. - * Return with the bus width. * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing * device ready/busy line. If set to NULL no access to * ready/busy is available and the ready/busy information @@ -669,11 +695,9 @@ struct nand_chip { void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); void (*select_chip)(struct mtd_info *mtd, int chip); - int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); + int (*block_bad)(struct mtd_info *mtd, loff_t ofs); int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); - int (*init_size)(struct mtd_info *mtd, struct nand_chip *this, - u8 *id_data); int (*dev_ready)(struct mtd_info *mtd); void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); @@ -873,7 +897,6 @@ struct nand_manufacturers { extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[]; -extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); extern int nand_default_bbt(struct mtd_info *mtd); extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); @@ -898,7 +921,6 @@ extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, * @chip_delay: R/B delay value in us * @options: Option flags, e.g. 16bit buswidth * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH - * @ecclayout: ECC layout info structure * @part_probe_types: NULL-terminated array of probe types */ struct platform_nand_chip { @@ -906,7 +928,6 @@ struct platform_nand_chip { int chip_offset; int nr_partitions; struct mtd_partition *partitions; - struct nand_ecclayout *ecclayout; int chip_delay; unsigned int options; unsigned int bbt_options; @@ -955,15 +976,6 @@ struct platform_nand_data { struct platform_nand_ctrl ctrl; }; -/* Some helpers to access the data structures */ -static inline -struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd->priv; - - return chip->priv; -} - #ifdef CONFIG_SYS_NAND_ONFI_DETECTION /* return the supported features. */ static inline int onfi_feature(struct nand_chip *chip) @@ -1081,4 +1093,9 @@ struct nand_sdr_timings { /* get timing characteristics from ONFI timing mode. */ const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); + +int nand_check_erased_ecc_chunk(void *data, int datalen, + void *ecc, int ecclen, + void *extraoob, int extraooblen, + int threshold); #endif /* __LINUX_MTD_NAND_H */ diff --git a/include/linux/mtd/nand_bch.h b/include/linux/mtd/nand_bch.h index d8754dd8c8e..8ea6b04cc3a 100644 --- a/include/linux/mtd/nand_bch.h +++ b/include/linux/mtd/nand_bch.h @@ -32,9 +32,7 @@ int nand_bch_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, /* * Initialize BCH encoder/decoder */ -struct nand_bch_control * -nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, - unsigned int eccbytes, struct nand_ecclayout **ecclayout); +struct nand_bch_control *nand_bch_init(struct mtd_info *mtd); /* * Release BCH encoder/decoder resources */ @@ -55,12 +53,10 @@ static inline int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf, unsigned char *read_ecc, unsigned char *calc_ecc) { - return -1; + return -ENOTSUPP; } -static inline struct nand_bch_control * -nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, - unsigned int eccbytes, struct nand_ecclayout **ecclayout) +static inline struct nand_bch_control *nand_bch_init(struct mtd_info *mtd) { return NULL; } -- cgit v1.3.1 From 53ecdfb92034ce836ec94ba33ba0d8d27ea3c16c Mon Sep 17 00:00:00 2001 From: "mario.six@gdsys.cc" Date: Wed, 25 May 2016 15:15:21 +0200 Subject: dm: gpio: Add methods for open drain setting Certain GPIO devices have the capability to switch their GPIOs into open-drain mode, that is, instead of actively driving the output (Push-pull output), the pin is connected to the collector (for a NPN transistor) or the drain (for a MOSFET) of a transistor, respectively. The pin then either forms an open circuit or a connection to ground, depending on the state of the transistor. This patch adds functions to the GPIO uclass to switch GPIOs to open-drain mode on devices that support it. Signed-off-by: Mario Six Reviewed-by: Simon Glass Reviewed-by: York Sun --- drivers/gpio/gpio-uclass.c | 32 ++++++++++++++++++++++++++++++++ include/asm-generic/gpio.h | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) (limited to 'include') diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 732b6c2afa1..4559739d619 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -367,6 +367,38 @@ int dm_gpio_set_value(const struct gpio_desc *desc, int value) return 0; } +int dm_gpio_get_open_drain(struct gpio_desc *desc) +{ + struct dm_gpio_ops *ops = gpio_get_ops(desc->dev); + int ret; + + ret = check_reserved(desc, "get_open_drain"); + if (ret) + return ret; + + if (ops->set_open_drain) + return ops->get_open_drain(desc->dev, desc->offset); + else + return -ENOSYS; +} + +int dm_gpio_set_open_drain(struct gpio_desc *desc, int value) +{ + struct dm_gpio_ops *ops = gpio_get_ops(desc->dev); + int ret; + + ret = check_reserved(desc, "set_open_drain"); + if (ret) + return ret; + + if (ops->set_open_drain) + ret = ops->set_open_drain(desc->dev, desc->offset, value); + else + return 0; /* feature not supported -> ignore setting */ + + return ret; +} + int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags) { struct udevice *dev = desc->dev; diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 2500c104500..4aa0004fab4 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -251,6 +251,8 @@ struct dm_gpio_ops { int value); int (*get_value)(struct udevice *dev, unsigned offset); int (*set_value)(struct udevice *dev, unsigned offset, int value); + int (*get_open_drain)(struct udevice *dev, unsigned offset); + int (*set_open_drain)(struct udevice *dev, unsigned offset, int value); /** * get_function() Get the GPIO function * @@ -549,6 +551,38 @@ int dm_gpio_get_value(const struct gpio_desc *desc); int dm_gpio_set_value(const struct gpio_desc *desc, int value); +/** + * dm_gpio_get_open_drain() - Check if open-drain-mode of a GPIO is active + * + * This checks if open-drain-mode for a GPIO is enabled or not. This method is + * optional. + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @return Value of open drain mode for GPIO (0 for inactive, 1 for active) or + * -ve on error + */ +int dm_gpio_get_open_drain(struct gpio_desc *desc); + +/** + * dm_gpio_set_open_drain() - Switch open-drain-mode of a GPIO on or off + * + * This enables or disables open-drain mode for a GPIO. This method is + * optional; if the driver does not support it, nothing happens when the method + * is called. + * + * In open-drain mode, instead of actively driving the output (Push-pull + * output), the GPIO's pin is connected to the collector (for a NPN transistor) + * or the drain (for a MOSFET) of a transistor, respectively. The pin then + * either forms an open circuit or a connection to ground, depending on the + * state of the transistor. + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @return 0 if OK, -ve on error + */ +int dm_gpio_set_open_drain(struct gpio_desc *desc, int value); + /** * dm_gpio_set_dir() - Set the direction for a GPIO * -- cgit v1.3.1 From 1630d5582c2b8be129bcd2d3a0db03bc3349dfab Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 27 May 2016 11:25:49 +0200 Subject: ARM64: zynqmp: Enable CMD_NAND via Kconfig Simplify board file by enabling CMD_NAND via Kconfig. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_ep_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 + include/configs/xilinx_zynqmp.h | 1 - 3 files changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index f342ed293c7..7879b4dd6c4 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_DFU=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 77e6180143f..2edd180c867 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_NAND=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_DFU=y diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index ffb6b34d57c..c2c6eab314d 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -105,7 +105,6 @@ #endif #ifdef CONFIG_NAND_ARASAN -# define CONFIG_CMD_NAND # define CONFIG_CMD_NAND_LOCK_UNLOCK # define CONFIG_SYS_MAX_NAND_DEVICE 1 # define CONFIG_SYS_NAND_SELF_INIT -- cgit v1.3.1 From a1a6af82e2c7be4ef34e38e2d01dd337e8b32903 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 30 May 2016 10:13:37 +0200 Subject: ARM64: zynqmp: Enable Vitesse and RealTek ethernet phys Phys are available on zc1751-dc4 that's why enable them. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index c2c6eab314d..455481dc534 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -189,6 +189,8 @@ # define CONFIG_PHY_NATSEMI # define CONFIG_PHY_TI # define CONFIG_PHY_GIGE +# define CONFIG_PHY_VITESSE +# define CONFIG_PHY_REALTEK # define PHY_ANEG_TIMEOUT 20000 #endif -- cgit v1.3.1 From 08ac386bb292d3be19f77e7d782574e72646ea1b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 May 2016 08:06:38 +0200 Subject: ARM64: zynqmp: Add support for zc1751-dc4 zc1751-dc4 contains four GEMs. Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 212 +++++++++++++++++++++++ configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 41 +++++ include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h | 24 +++ 4 files changed, 278 insertions(+) create mode 100644 arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts create mode 100644 configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig create mode 100644 include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e76f56b22eb..ed897cf52a6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -90,6 +90,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu102-revB.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ + zynqmp-zc1751-xm018-dc4.dtb \ zynqmp-zc1751-xm019-dc5.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb \ am335x-evmsk.dtb \ diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts new file mode 100644 index 00000000000..03f1ad7934c --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -0,0 +1,212 @@ +/* + * dts file for Xilinx ZynqMP zc1751-xm018-dc4 + * + * (C) Copyright 2015 - 2016, Xilinx, Inc. + * + * Michal Simek + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP zc1751-xm018-dc4"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + can0 = &can0; + can1 = &can1; + ethernet0 = &gem0; + ethernet1 = &gem1; + ethernet2 = &gem2; + ethernet3 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + spi0 = &qspi; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ + xlnx,overfetch; /* for testing purpose */ + xlnx,ratectrl = <0>; /* for testing purpose */ + xlnx,src-issue = <31>; +}; + +&fpd_dma_chan2 { + status = "okay"; + xlnx,ratectrl = <100>; /* for testing purpose */ + xlnx,src-issue = <4>; /* for testing purpose */ +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&lpd_dma_chan1 { + status = "okay"; +}; + +&lpd_dma_chan2 { + status = "okay"; +}; + +&lpd_dma_chan3 { + status = "okay"; +}; + +&lpd_dma_chan4 { + status = "okay"; +}; + +&lpd_dma_chan5 { + status = "okay"; +}; + +&lpd_dma_chan6 { + status = "okay"; +}; + +&lpd_dma_chan7 { + status = "okay"; +}; + +&lpd_dma_chan8 { + status = "okay"; +}; + +&xlnx_dp { + status = "okay"; +}; + +&xlnx_dpdma { + status = "okay"; +}; + +&gem0 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 90]; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy0>; + ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ + reg = <0>; + }; + ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ + reg = <7>; + }; + ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ + reg = <3>; + }; + ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ + reg = <8>; + }; +}; + +&gem1 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 91]; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy7>; +}; + +&gem2 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 92]; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy3>; +}; + +&gem3 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 93]; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy8>; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig new file mode 100644 index 00000000000..f7f3822d699 --- /dev/null +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -0,0 +1,41 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm018_dc4" +CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_DM_MMC=y +CONFIG_ZYNQ_SDHCI=y +CONFIG_DM_ETH=y +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y diff --git a/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h new file mode 100644 index 00000000000..fd2ec6a7751 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h @@ -0,0 +1,24 @@ +/* + * Configuration for Xilinx ZynqMP zc1751 XM018 DC4 + * + * (C) Copyright 2015 Xilinx, Inc. + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H +#define __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H + +#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm018 dc4" + +#define CONFIG_KERNEL_FDT_OFST_SIZE \ + "kernel_offset=0x400000\0" \ + "fdt_offset=0x2400000\0" \ + "kernel_size=0x2000000\0" \ + "fdt_size=0x80000\0" \ + "board=zc1751-dc4\0" + +#include + +#endif /* __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H */ -- cgit v1.3.1 From 340b0e3bb6e8808a7e683e030b3c5b5137715041 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 30 May 2016 16:06:54 +0200 Subject: env: Setup GD_FLG_ENV_DEFAULT flag when default environment are used Setup flag when default environment are used to be able to rewrite default distro boot variables based on SoC boot mode. Signed-off-by: Michal Simek Reviewed-by: Alexander Graf --- common/env_common.c | 1 + include/asm-generic/global_data.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/common/env_common.c b/common/env_common.c index af59c72e1fd..13db7dc3f75 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -123,6 +123,7 @@ void set_default_env(const char *s) error("Environment import failed: errno = %d\n", errno); gd->flags |= GD_FLG_ENV_READY; + gd->flags |= GD_FLG_ENV_DEFAULT; } diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index f2810a1bd75..0abcbe4c0b3 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -141,5 +141,6 @@ typedef struct global_data { #define GD_FLG_SPL_INIT 0x00400 /* spl_init() has been called */ #define GD_FLG_SKIP_RELOC 0x00800 /* Don't relocate */ #define GD_FLG_RECORD 0x01000 /* Record console */ +#define GD_FLG_ENV_DEFAULT 0x02000 /* Default variable flag */ #endif /* __ASM_GENERIC_GBL_DATA_H */ -- cgit v1.3.1 From 0d169b8cd70975f60920b077d6ed96623db97d33 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 1 Jun 2016 14:29:33 +0200 Subject: ARM64: zynqmp: Enable AHCI when CONFIG_SATA_CEVA is defined Simplify zcu102 board file by moving CONFIG_AHCI enabling to common file. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 3 ++- include/configs/xilinx_zynqmp_zcu102.h | 1 - 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 455481dc534..795d58646e1 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -211,7 +211,8 @@ # define CONFIG_SYS_EEPROM_SIZE (64 * 1024) #endif -#ifdef CONFIG_AHCI +#ifdef CONFIG_SATA_CEVA +#define CONFIG_AHCI #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h index 81079fe7d8b..09c4a51a2ec 100644 --- a/include/configs/xilinx_zynqmp_zcu102.h +++ b/include/configs/xilinx_zynqmp_zcu102.h @@ -41,7 +41,6 @@ #define CONFIG_CMD_PCA953X #define CONFIG_CMD_PCA953X_INFO -#define CONFIG_AHCI #define CONFIG_SATA_CEVA #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} -- cgit v1.3.1 From a8b6a156c0f7fb99502229e454bc9c3b38645280 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 1 Jun 2016 22:41:54 +0200 Subject: ARM64: zynqmp: Remove CONFIG_BOOTP_SERVERIP When the CONFIG_BOOTP_SERVERIP option is set, we ignore all dhcp values for the tftp server and use our own serverip and file name instead. This is usually not what we want and I doubt it's set for a good reason on ZynqMP. It definitely hurts if we want to support uEFI PXE boot on it. So just remove the option for now. Signed-off-by: Alexander Graf Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 795d58646e1..ac3de0ac811 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -76,7 +76,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_MAY_FAIL -#define CONFIG_BOOTP_SERVERIP #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_PXE #define CONFIG_BOOTP_SUBNETMASK -- cgit v1.3.1 From b72894f14da79cdcdab8007b079d922bd28e5ce7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 22 Apr 2016 14:28:54 +0200 Subject: ARM64: zynqmp: Add support for standard distro boot commands Nand and QSPI are not defined now but this will be extended. Based on selected bootmode boot_targets are rewritten. Patch also contains detection if variables are saved. If yes don't rewrite boot_targets variable. Also move variable setup to the end of file because SCSI needs to be defined before others macros are using it. Signed-off-by: Michal Simek Reviewed-by: Alexander Graf --- board/xilinx/zynqmp/zynqmp.c | 34 +++++++++++--- include/configs/xilinx_zynqmp.h | 59 ++++++++++++++++++------ include/configs/xilinx_zynqmp_ep.h | 7 --- include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h | 7 --- include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h | 7 --- include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h | 7 --- include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h | 7 --- include/configs/xilinx_zynqmp_zcu102.h | 7 --- 8 files changed, 71 insertions(+), 64 deletions(-) (limited to 'include') diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 4623cd49e9c..f15dc5d7152 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -214,6 +215,13 @@ int board_late_init(void) { u32 reg = 0; u8 bootmode; + const char *mode; + char *new_targets; + + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { + debug("Saved variables - Skipping\n"); + return 0; + } reg = readl(&crlapb_base->boot_mode); bootmode = reg & BOOT_MODES_MASK; @@ -222,37 +230,49 @@ int board_late_init(void) switch (bootmode) { case JTAG_MODE: puts("JTAG_MODE\n"); - setenv("modeboot", "jtagboot"); + mode = "pxe dhcp"; break; case QSPI_MODE_24BIT: case QSPI_MODE_32BIT: - setenv("modeboot", "qspiboot"); + mode = "qspi0"; puts("QSPI_MODE\n"); break; case EMMC_MODE: puts("EMMC_MODE\n"); - setenv("modeboot", "sdboot"); + mode = "mmc0"; break; case SD_MODE: puts("SD_MODE\n"); - setenv("modeboot", "sdboot"); + mode = "mmc0"; break; case SD_MODE1: puts("SD_MODE1\n"); #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) - setenv("sdbootdev", "1"); + mode = "mmc1"; +#else + mode = "mmc0"; #endif - setenv("modeboot", "sdboot"); break; case NAND_MODE: puts("NAND_MODE\n"); - setenv("modeboot", "nandboot"); + mode = "nand0"; break; default: + mode = ""; printf("Invalid Boot Mode:0x%x\n", bootmode); break; } + /* + * One terminating char + one byte for space between mode + * and default boot_targets + */ + new_targets = calloc(1, strlen(mode) + + strlen(getenv("boot_targets")) + 2); + + sprintf(new_targets, "%s %s", mode, getenv("boot_targets")); + setenv("boot_targets", new_targets); + return 0; } diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index ac3de0ac811..fc2e1f72d0c 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -146,21 +146,6 @@ # define DFU_ALT_INFO #endif -/* Initial environment variables */ -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr=0x80000\0" \ - "fdt_addr=0x7000000\0" \ - "fdt_high=0x10000000\0" \ - CONFIG_KERNEL_FDT_OFST_SIZE \ - "sdbootdev=0\0"\ - "sdboot=mmc dev $sdbootdev && mmcinfo && load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \ - "load mmc $sdbootdev:$partid $kernel_addr Image && " \ - "booti $kernel_addr - $fdt_addr\0" \ - DFU_ALT_INFO -#endif - -#define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 3 #define CONFIG_BOARD_LATE_INIT @@ -230,6 +215,50 @@ #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_CLOCKS +#define ENV_MEM_LAYOUT_SETTINGS \ + "fdt_high=10000000\0" \ + "initrd_high=10000000\0" \ + "fdt_addr_r=0x40000000\0" \ + "pxefile_addr_r=0x10000000\0" \ + "kernel_addr_r=0x18000000\0" \ + "scriptaddr=0x02000000\0" \ + "ramdisk_addr_r=0x02100000\0" \ + +#if defined(CONFIG_ZYNQ_SDHCI) +# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) +#else +# define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#if defined(CONFIG_SATA_CEVA) +# define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) +#else +# define BOOT_TARGET_DEVICES_SCSI(func) +#endif + +#if defined(CONFIG_ZYNQMP_USB) +# define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1) +#else +# define BOOT_TARGET_DEVICES_USB(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_DEVICES_SCSI(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +/* Initial environment variables */ +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV \ + DFU_ALT_INFO +#endif + #define CONFIG_SPL_TEXT_BASE 0xfffc0000 #define CONFIG_SPL_MAX_SIZE 0x20000 diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index 95063557137..c5bd5da43c5 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -22,13 +22,6 @@ #define COUNTER_FREQUENCY 4000000 -#define CONFIG_KERNEL_FDT_OFST_SIZE \ - "kernel_offset=0x400000\0" \ - "fdt_offset=0x2400000\0" \ - "kernel_size=0x2000000\0" \ - "fdt_size=0x80000\0" \ - "board=ep108\0" - #include #endif /* __CONFIG_ZYNQMP_EP_H */ diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h index 3c0ba883dbb..c9f443207d9 100644 --- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h +++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h @@ -17,13 +17,6 @@ #define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm015 dc1" -#define CONFIG_KERNEL_FDT_OFST_SIZE \ - "kernel_offset=0x400000\0" \ - "fdt_offset=0x2400000\0" \ - "kernel_size=0x2000000\0" \ - "fdt_size=0x80000\0" \ - "board=zc1751-dc1\0" - #include #endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */ diff --git a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h index 83ea624c51c..526d0bbe585 100644 --- a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h +++ b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h @@ -14,13 +14,6 @@ #define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm016 dc2" -#define CONFIG_KERNEL_FDT_OFST_SIZE \ - "kernel_offset=0x400000\0" \ - "fdt_offset=0x2400000\0" \ - "kernel_size=0x2000000\0" \ - "fdt_size=0x80000\0" \ - "board=zc1751-dc2\0" - #include #endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */ diff --git a/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h index fd2ec6a7751..65277a64c3c 100644 --- a/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h +++ b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h @@ -12,13 +12,6 @@ #define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm018 dc4" -#define CONFIG_KERNEL_FDT_OFST_SIZE \ - "kernel_offset=0x400000\0" \ - "fdt_offset=0x2400000\0" \ - "kernel_size=0x2000000\0" \ - "fdt_size=0x80000\0" \ - "board=zc1751-dc4\0" - #include #endif /* __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H */ diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h index 4f8f5c10536..76350d95795 100644 --- a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h +++ b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h @@ -15,13 +15,6 @@ #define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm019 dc5" -#define CONFIG_KERNEL_FDT_OFST_SIZE \ - "kernel_offset=0x400000\0" \ - "fdt_offset=0x2400000\0" \ - "kernel_size=0x2000000\0" \ - "fdt_size=0x80000\0" \ - "board=zc1751-dc5\0" - #include #endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */ diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h index 09c4a51a2ec..7ceab3230b8 100644 --- a/include/configs/xilinx_zynqmp_zcu102.h +++ b/include/configs/xilinx_zynqmp_zcu102.h @@ -53,13 +53,6 @@ #define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20 -#define CONFIG_KERNEL_FDT_OFST_SIZE \ - "kernel_offset=0x180000\0" \ - "fdt_offset=0x100000\0" \ - "kernel_size=0x1e00000\0" \ - "fdt_size=0x80000\0" \ - "board=zcu102\0" - #include #endif /* __CONFIG_ZYNQMP_ZCU102_H */ -- cgit v1.3.1 From 1d2541ba32c0ab144c9307edd4a76606ad528ce0 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Thu, 2 Jun 2016 09:05:41 +0200 Subject: strider: Support con-dp flavor There is a new strider console flavor with DisplayPort video. Signed-off-by: Dirk Eibach Reviewed-by: Tom Rini --- board/gdsys/common/Makefile | 1 + board/gdsys/mpc8308/strider.c | 37 ++++++++++++++++++++++ configs/strider_con_dp_defconfig | 20 ++++++++++++ include/configs/strider.h | 67 +++++++++++++++++++++++++++++++++++++--- include/gdsys_fpga.h | 2 +- 5 files changed, 121 insertions(+), 6 deletions(-) create mode 100644 configs/strider_con_dp_defconfig (limited to 'include') diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index ce230455c84..d4f0e705736 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o obj-$(CONFIG_STRIDER) += fanctrl.o obj-$(CONFIG_STRIDER_CON) += osd.o +obj-$(CONFIG_STRIDER_CON_DP) += osd.o diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c index eee582bb0f7..121977d315f 100644 --- a/board/gdsys/mpc8308/strider.c +++ b/board/gdsys/mpc8308/strider.c @@ -133,6 +133,9 @@ int last_stage_init(void) unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 }; #endif bool hw_type_cat = pca9698_get_value(0x20, 18); +#ifdef CONFIG_STRIDER_CON_DP + bool is_dh = pca9698_get_value(0x20, 25); +#endif bool ch0_sgmii2_present = false; /* Turn on Analog Devices ADV7611 */ @@ -140,6 +143,7 @@ int last_stage_init(void) /* Turn on Parade DP501 */ pca9698_direction_output(0x20, 10, 1); + pca9698_direction_output(0x20, 11, 1); ch0_sgmii2_present = !pca9698_get_value(0x20, 37); @@ -202,6 +206,14 @@ int last_stage_init(void) osd_probe(0); #endif +#ifdef CONFIG_STRIDER_CON_DP + if (ioep_fpga_has_osd(0)) { + osd_probe(0); + if (is_dh) + osd_probe(4); + } +#endif + #ifdef CONFIG_STRIDER_CPU ch7301_probe(0, false); dp501_probe(0, false); @@ -226,6 +238,13 @@ int last_stage_init(void) if (ioep_fpga_has_osd(k)) osd_probe(k); #endif +#ifdef CONFIG_STRIDER_CON_DP + if (ioep_fpga_has_osd(k)) { + osd_probe(k); + if (is_dh) + osd_probe(k + 4); + } +#endif #ifdef CONFIG_STRIDER_CPU if (!adv7611_probe(k)) printf(" Advantiv ADV7611 HDMI Receiver\n"); @@ -270,6 +289,24 @@ int fpga_gpio_get(unsigned int bus, int pin) return val & pin; } +#ifdef CONFIG_STRIDER_CON_DP +void fpga_control_set(unsigned int bus, int pin) +{ + u16 val; + + FPGA_GET_REG(bus, control, &val); + FPGA_SET_REG(bus, control, val | pin); +} + +void fpga_control_clear(unsigned int bus, int pin) +{ + u16 val; + + FPGA_GET_REG(bus, control, &val); + FPGA_SET_REG(bus, control, val & ~pin); +} +#endif + void mpc8308_init(void) { pca9698_direction_output(0x20, 26, 1); diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig new file mode 100644 index 00000000000..b7a16b7a381 --- /dev/null +++ b/configs/strider_con_dp_defconfig @@ -0,0 +1,20 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_STRIDER=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON_DP" +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/strider.h b/include/configs/strider.h index 5803b660bc3..20ffc0c61fd 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -22,6 +22,8 @@ #ifdef CONFIG_STRIDER_CPU #define CONFIG_IDENT_STRING " strider cpu 0.01" +#elif defined(CONFIG_STRIDER_CON_DP) +#define CONFIG_IDENT_STRING " strider con dp 0.01" #else #define CONFIG_IDENT_STRING " strider con 0.01" #endif @@ -225,15 +227,11 @@ /* * FLASH on the Local Bus */ -#if 1 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_FLASH_CFI_LEGACY #define CONFIG_SYS_FLASH_LEGACY_512Kx16 -#else -#define CONFIG_SYS_NO_FLASH -#endif #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ @@ -341,6 +339,22 @@ #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F +#ifdef CONFIG_STRIDER_CON_DP +#define CONFIG_SYS_I2C_IHS_DUAL +#define CONFIG_SYS_I2C_IHS_CH0_1 +#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH1_1 +#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH2_1 +#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH3_1 +#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F +#endif + /* * Software (bit-bang) I2C driver configuration */ @@ -357,7 +371,7 @@ #define I2C_SOFT_DECLARATIONS4 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F -#ifdef CONFIG_STRIDER_CON +#if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP) #define I2C_SOFT_DECLARATIONS5 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F @@ -371,12 +385,33 @@ #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F #endif +#ifdef CONFIG_STRIDER_CON_DP +#define I2C_SOFT_DECLARATIONS9 +#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F +#define I2C_SOFT_DECLARATIONS10 +#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F +#define I2C_SOFT_DECLARATIONS11 +#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F +#define I2C_SOFT_DECLARATIONS12 +#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F +#endif #ifdef CONFIG_STRIDER_CON #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} +#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ + {12, 0x4c} } +#elif defined(CONFIG_STRIDER_CON_DP) +#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} +#define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7} +#define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7} +#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ {12, 0x4c} } #else @@ -391,6 +426,8 @@ void fpga_gpio_set(unsigned int bus, int pin); void fpga_gpio_clear(unsigned int bus, int pin); int fpga_gpio_get(unsigned int bus, int pin); +void fpga_control_set(unsigned int bus, int pin); +void fpga_control_clear(unsigned int bus, int pin); #endif #ifdef CONFIG_STRIDER_CON @@ -398,12 +435,28 @@ int fpga_gpio_get(unsigned int bus, int pin); #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) +#elif defined(CONFIG_STRIDER_CON_DP) +#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) +#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) +#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) #else #define I2C_SDA_GPIO 0x0040 #define I2C_SCL_GPIO 0x0020 #define I2C_FPGA_IDX I2C_ADAP_HWNR #endif + +#ifdef CONFIG_STRIDER_CON_DP +#define I2C_ACTIVE \ + do { \ + if (I2C_ADAP_HWNR > 7) \ + fpga_control_set(I2C_FPGA_IDX, 0x0004); \ + else \ + fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ + } while (0) +#else #define I2C_ACTIVE { } +#endif + #define I2C_TRISTATE { } #define I2C_READ \ (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) @@ -436,6 +489,10 @@ int fpga_gpio_get(unsigned int bus, int pin); #define CONFIG_SYS_DP501_DIFFERENTIAL #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ +#ifdef CONFIG_STRIDER_CON_DP +#define CONFIG_SYS_OSD_DH +#endif + /* * General PCI * Addresses are mapped 1-1. diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index 3b8762df669..e1b9c646266 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -163,7 +163,7 @@ struct ihs_fpga { }; #endif -#ifdef CONFIG_HRCON +#if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP) struct ihs_fpga { u16 reflection_low; /* 0x0000 */ u16 versions; /* 0x0002 */ -- cgit v1.3.1 From 145510cc7651fa36f1e6ee2d3d8504b05e965b1a Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Thu, 2 Jun 2016 09:05:42 +0200 Subject: strider: Support cpu-dp flavor There is new strider cpu flavor with DisplayPort video. Signed-off-by: Dirk Eibach Reviewed-by: Tom Rini --- configs/strider_cpu_dp_defconfig | 20 ++++++++++++++++++++ include/configs/strider.h | 10 +++++++++- 2 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 configs/strider_cpu_dp_defconfig (limited to 'include') diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig new file mode 100644 index 00000000000..db75c0d2d61 --- /dev/null +++ b/configs/strider_cpu_dp_defconfig @@ -0,0 +1,20 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_STRIDER=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU,STRIDER_CPU_DP" +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/strider.h b/include/configs/strider.h index 20ffc0c61fd..90492f4fdb6 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -20,7 +20,9 @@ #define CONFIG_SYS_TEXT_BASE 0xFE000000 -#ifdef CONFIG_STRIDER_CPU +#ifdef CONFIG_STRIDER_CPU_DP +#define CONFIG_IDENT_STRING " strider cpu dp 0.01" +#elif defined(CONFIG_STRIDER_CPU) #define CONFIG_IDENT_STRING " strider cpu 0.01" #elif defined(CONFIG_STRIDER_CON_DP) #define CONFIG_IDENT_STRING " strider con dp 0.01" @@ -414,6 +416,12 @@ #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ {12, 0x4c} } +#elif defined(CONFIG_STRIDER_CPU_DP) +#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} +#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} +#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} +#define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \ + {8, 0x4c} } #else #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} -- cgit v1.3.1 From a86aeaf228da739bce6bc40927949efc33672050 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Fri, 20 May 2016 23:28:23 +0200 Subject: efi_loader: Add exit support Some times you may want to exit an EFI payload again, for example to default boot into a PXE installation and decide that you would rather want to boot from the local disk instead. This patch adds exit functionality to the EFI implementation, allowing EFI payloads to exit. Signed-off-by: Alexander Graf --- cmd/bootefi.c | 6 ++++++ include/efi_api.h | 10 ++++++++++ lib/efi_loader/efi_boottime.c | 21 ++++++++++++++++----- 3 files changed, 32 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/cmd/bootefi.c b/cmd/bootefi.c index d3a23318702..2a62dce702b 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -209,6 +209,12 @@ static unsigned long do_bootefi_exec(void *efi, void *fdt) #ifdef DEBUG_EFI printf("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry); #endif + + if (setjmp(&loaded_image_info.exit_jmp)) { + efi_status_t status = loaded_image_info.exit_status; + return status == EFI_SUCCESS ? 0 : -EINVAL; + } + return entry(&loaded_image_info, &systab); } diff --git a/include/efi_api.h b/include/efi_api.h index 20035d72727..f572b880798 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -17,6 +17,10 @@ #include +#ifdef CONFIG_EFI_LOADER +#include +#endif + /* Types and defines for EFI CreateEvent */ enum efi_event_type { EFI_TIMER_STOP = 0, @@ -239,6 +243,12 @@ struct efi_loaded_image { unsigned int image_code_type; unsigned int image_data_type; unsigned long unload; + + /* Below are efi loader private fields */ +#ifdef CONFIG_EFI_LOADER + efi_status_t exit_status; + struct jmp_buf_data exit_jmp; +#endif }; #define DEVICE_PATH_GUID \ diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 9daca50a72f..15a1b90d65a 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -458,19 +458,30 @@ static efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, efi_is_direct_boot = false; /* call the image! */ + if (setjmp(&info->exit_jmp)) { + /* We returned from the child image */ + return EFI_EXIT(info->exit_status); + } + entry(image_handle, &systab); /* Should usually never get here */ return EFI_EXIT(EFI_SUCCESS); } -static efi_status_t EFIAPI efi_exit(void *image_handle, long exit_status, - unsigned long exit_data_size, - uint16_t *exit_data) +static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle, + efi_status_t exit_status, unsigned long exit_data_size, + int16_t *exit_data) { + struct efi_loaded_image *loaded_image_info = (void*)image_handle; + EFI_ENTRY("%p, %ld, %ld, %p", image_handle, exit_status, exit_data_size, exit_data); - return EFI_EXIT(efi_unsupported(__func__)); + + loaded_image_info->exit_status = exit_status; + longjmp(&loaded_image_info->exit_jmp); + + panic("EFI application exited"); } static struct efi_object *efi_search_obj(void *handle) @@ -746,7 +757,7 @@ static const struct efi_boot_services efi_boot_services = { .install_configuration_table = efi_install_configuration_table, .load_image = efi_load_image, .start_image = efi_start_image, - .exit = (void*)efi_exit, + .exit = efi_exit, .unload_image = efi_unload_image, .exit_boot_services = efi_exit_boot_services, .get_next_monotonic_count = efi_get_next_monotonic_count, -- cgit v1.3.1 From edcef3ba1d2d5beb92fcd7df253e196e77ba174d Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Thu, 2 Jun 2016 11:38:27 +0200 Subject: efi_loader: Move to normal debug infrastructure We introduced special "DEBUG_EFI" defines when the efi loader support was new. After giving it a bit of thought, turns out we really didn't have to - the normal #define DEBUG infrastructure works well enough for efi loader as well. So this patch switches to the common debug() and #define DEBUG way of printing debug information. Signed-off-by: Alexander Graf --- cmd/bootefi.c | 4 +--- include/efi_loader.h | 10 +--------- lib/efi_loader/efi_boottime.c | 6 +----- lib/efi_loader/efi_disk.c | 11 ++++------- lib/efi_loader/efi_memory.c | 2 -- lib/efi_loader/efi_runtime.c | 14 +++----------- 6 files changed, 10 insertions(+), 37 deletions(-) (limited to 'include') diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 2a62dce702b..216906527fe 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -206,9 +206,7 @@ static unsigned long do_bootefi_exec(void *efi, void *fdt) #endif /* Call our payload! */ -#ifdef DEBUG_EFI - printf("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry); -#endif + debug("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry); if (setjmp(&loaded_image_info.exit_jmp)) { efi_status_t status = loaded_image_info.exit_status; diff --git a/include/efi_loader.h b/include/efi_loader.h index 3332d61cefc..97388350eb9 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -15,18 +15,10 @@ #include -/* #define DEBUG_EFI */ - -#ifdef DEBUG_EFI #define EFI_ENTRY(format, ...) do { \ efi_restore_gd(); \ - printf("EFI: Entry %s(" format ")\n", __func__, ##__VA_ARGS__); \ + debug("EFI: Entry %s(" format ")\n", __func__, ##__VA_ARGS__); \ } while(0) -#else -#define EFI_ENTRY(format, ...) do { \ - efi_restore_gd(); \ - } while(0) -#endif #define EFI_EXIT(ret) efi_exit_func(ret); diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 15a1b90d65a..be6f5e81124 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -6,8 +6,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -/* #define DEBUG_EFI */ - #include #include #include @@ -76,9 +74,7 @@ efi_status_t efi_exit_func(efi_status_t ret) static efi_status_t efi_unsupported(const char *funcname) { -#ifdef DEBUG_EFI - printf("EFI: App called into unimplemented function %s\n", funcname); -#endif + debug("EFI: App called into unimplemented function %s\n", funcname); return EFI_EXIT(EFI_UNSUPPORTED); } diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index f9ad6156b71..c434c92250a 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -84,10 +84,8 @@ static efi_status_t EFIAPI efi_disk_rw_blocks(struct efi_block_io *this, blocks = buffer_size / blksz; lba += diskobj->offset; -#ifdef DEBUG_EFI - printf("EFI: %s:%d blocks=%x lba=%"PRIx64" blksz=%x dir=%d\n", __func__, - __LINE__, blocks, lba, blksz, direction); -#endif + debug("EFI: %s:%d blocks=%x lba=%"PRIx64" blksz=%x dir=%d\n", __func__, + __LINE__, blocks, lba, blksz, direction); /* We only support full block access */ if (buffer_size & (blksz - 1)) @@ -101,9 +99,8 @@ static efi_status_t EFIAPI efi_disk_rw_blocks(struct efi_block_io *this, /* We don't do interrupts, so check for timers cooperatively */ efi_timer_check(); -#ifdef DEBUG_EFI - printf("EFI: %s:%d n=%lx blocks=%x\n", __func__, __LINE__, n, blocks); -#endif + debug("EFI: %s:%d n=%lx blocks=%x\n", __func__, __LINE__, n, blocks); + if (n != blocks) return EFI_EXIT(EFI_DEVICE_ERROR); diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 9e669f51026..ad713d0e8be 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -6,8 +6,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -/* #define DEBUG_EFI */ - #include #include #include diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index 11d01268d8c..99b5ef11c2e 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -165,9 +165,7 @@ static void efi_runtime_detach(ulong offset) ulong *p = efi_runtime_detach_list[i].ptr; ulong newaddr = patchto ? (patchto + patchoff) : 0; -#ifdef DEBUG_EFI - printf("%s: Setting %p to %lx\n", __func__, p, newaddr); -#endif + debug("%s: Setting %p to %lx\n", __func__, p, newaddr); *p = newaddr; } } @@ -182,10 +180,7 @@ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map) static ulong lastoff = CONFIG_SYS_TEXT_BASE; #endif -#ifdef DEBUG_EFI - printf("%s: Relocating to offset=%lx\n", __func__, offset); -#endif - + debug("%s: Relocating to offset=%lx\n", __func__, offset); for (; (ulong)rel < (ulong)&__efi_runtime_rel_stop; rel++) { ulong base = CONFIG_SYS_TEXT_BASE; ulong *p; @@ -212,10 +207,7 @@ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map) continue; } -#ifdef DEBUG_EFI - printf("%s: Setting %p to %lx\n", __func__, p, newaddr); -#endif - + debug("%s: Setting %p to %lx\n", __func__, p, newaddr); *p = newaddr; flush_dcache_range((ulong)p & ~(EFI_CACHELINE_SIZE - 1), ALIGN((ulong)&p[1], EFI_CACHELINE_SIZE)); -- cgit v1.3.1 From 5c2728ff0fb6ade135cc15c4849acac7db1d93d0 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 6 Jun 2016 11:18:42 +0530 Subject: configs: k2*_evm: Update fdt file names Now that all Keystone2 dts file names are changed in Linux kernel, reflect the same in evn variables inorder to find the right dtb file. Signed-off-by: Lokesh Vutla --- include/configs/k2e_evm.h | 2 +- include/configs/k2g_evm.h | 2 +- include/configs/k2hk_evm.h | 2 +- include/configs/k2l_evm.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 07f975bb37b..7eaab875f28 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -21,7 +21,7 @@ "addr_mon=0x0c140000\0" \ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ - "name_fdt=k2e-evm.dtb\0" \ + "name_fdt=keystone-k2e-evm.dtb\0" \ "name_mon=skern-k2e.bin\0" \ "name_ubi=k2e-evm-ubifs.ubi\0" \ "name_uboot=u-boot-spi-k2e-evm.gph\0" \ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index 3f985102683..f8bba6710db 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -26,7 +26,7 @@ "addr_mon=0x0c040000\0" \ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ - "name_fdt=k2g-evm.dtb\0" \ + "name_fdt=keystone-k2g-evm.dtb\0" \ "name_mon=skern-k2g.bin\0" \ "name_ubi=k2g-evm-ubifs.ubi\0" \ "name_uboot=u-boot-spi-k2g-evm.gph\0" \ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index a268a867364..0256f0e5678 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -21,7 +21,7 @@ "addr_mon=0x0c5f0000\0" \ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ - "name_fdt=k2hk-evm.dtb\0" \ + "name_fdt=keystone-k2hk-evm.dtb\0" \ "name_mon=skern-k2hk.bin\0" \ "name_ubi=k2hk-evm-ubifs.ubi\0" \ "name_uboot=u-boot-spi-k2hk-evm.gph\0" \ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index f366e6703d0..2322ab288d9 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -21,7 +21,7 @@ "addr_mon=0x0c140000\0" \ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0" \ - "name_fdt=k2l-evm.dtb\0" \ + "name_fdt=keystone-k2l-evm.dtb\0" \ "name_mon=skern-k2l.bin\0" \ "name_ubi=k2l-evm-ubifs.ubi\0" \ "name_uboot=u-boot-spi-k2l-evm.gph\0" \ -- cgit v1.3.1 From 25bab53ab26efdb9e2024477f896be65b6e7191e Mon Sep 17 00:00:00 2001 From: "Robert P. J. Day" Date: Mon, 30 May 2016 06:55:53 -0400 Subject: Remove unneeded remnants of bcopy(). Since bcopy() is no longer used, delete all remaining references to it. Signed-off-by: Robert P. J. Day --- arch/microblaze/include/asm/string.h | 2 -- arch/powerpc/lib/ppcstring.S | 7 ------- include/linux/string.h | 4 ---- lib/string.c | 24 ------------------------ 4 files changed, 37 deletions(-) (limited to 'include') diff --git a/arch/microblaze/include/asm/string.h b/arch/microblaze/include/asm/string.h index 724f5bdfa65..8f67ec785d4 100644 --- a/arch/microblaze/include/asm/string.h +++ b/arch/microblaze/include/asm/string.h @@ -17,13 +17,11 @@ #define __MICROBLAZE_STRING_H__ #if 0 -#define __HAVE_ARCH_BCOPY #define __HAVE_ARCH_MEMCPY #define __HAVE_ARCH_MEMSET #define __HAVE_ARCH_MEMMOVE extern void *memcpy (void *, const void *, __kernel_size_t); -extern void bcopy (const char *, char *, int); extern void *memset (void *, int, __kernel_size_t); extern void *memmove (void *, const void *, __kernel_size_t); #endif diff --git a/arch/powerpc/lib/ppcstring.S b/arch/powerpc/lib/ppcstring.S index 8152ac9b0f8..56bb3b824e7 100644 --- a/arch/powerpc/lib/ppcstring.S +++ b/arch/powerpc/lib/ppcstring.S @@ -92,13 +92,6 @@ memset: bdnz 8b blr - .globl bcopy -bcopy: - mr r6,r3 - mr r3,r4 - mr r4,r6 - b memcpy - .globl memmove memmove: cmplw 0,r3,r4 diff --git a/include/linux/string.h b/include/linux/string.h index c7047ba0bca..091ccab395b 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -20,10 +20,6 @@ extern __kernel_size_t strspn(const char *,const char *); */ #include -#ifndef __HAVE_ARCH_BCOPY -char *bcopy(const char *src, char *dest, int count); -#endif - #ifndef __HAVE_ARCH_STRCPY extern char * strcpy(char *,const char *); #endif diff --git a/lib/string.c b/lib/string.c index 87c9a408e62..67d5f6a4213 100644 --- a/lib/string.c +++ b/lib/string.c @@ -461,30 +461,6 @@ void * memset(void * s,int c,size_t count) } #endif -#ifndef __HAVE_ARCH_BCOPY -/** - * bcopy - Copy one area of memory to another - * @src: Where to copy from - * @dest: Where to copy to - * @count: The size of the area. - * - * Note that this is the same as memcpy(), with the arguments reversed. - * memcpy() is the standard, bcopy() is a legacy BSD function. - * - * You should not use this function to access IO space, use memcpy_toio() - * or memcpy_fromio() instead. - */ -char * bcopy(const char * src, char * dest, int count) -{ - char *tmp = dest; - - while (count--) - *tmp++ = *src++; - - return dest; -} -#endif - #ifndef __HAVE_ARCH_MEMCPY /** * memcpy - Copy one area of memory to another -- cgit v1.3.1 From 65eac4cc54921f9496061b0e0f0a7e159b42a3c6 Mon Sep 17 00:00:00 2001 From: "B, Ravi" Date: Fri, 3 Jun 2016 20:44:02 +0530 Subject: ti_armv7_common: env: Fix hard coded mmc device for uuid Avoid use of hard coded mmcdev value, use bootpart instead, so finduuid works based on bootpart set for a specific platform. Signed-off-by: Ravi Babu Reviewed-by: Tom Rini --- include/configs/ti_armv7_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 7db08813e49..ba7cf15242f 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -59,7 +59,7 @@ #define DEFAULT_MMC_TI_ARGS \ "mmcdev=0\0" \ "mmcrootfstype=ext4 rootwait\0" \ - "finduuid=part uuid mmc 0:2 uuid\0" \ + "finduuid=part uuid mmc ${bootpart} uuid\0" \ "args_mmc=run finduuid;setenv bootargs console=${console} " \ "${optargs} " \ "root=PARTUUID=${uuid} rw " \ -- cgit v1.3.1 From adb3928f152796e275f0535759796422d91f4709 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 4 Jun 2016 22:39:08 +0900 Subject: ARM: uniphier: support eMMC boot for PH1-LD11 and PH1-LD20 The Boot ROM on PH1-LD11/LD20 exports built-in APIs to load images from an eMMC device. They are useful to reduce the memory footprint of SPL, rather than compiling the whole MMC framework. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/boot-mode/Makefile | 4 + arch/arm/mach-uniphier/boot-mode/boot-mode.c | 25 +++++- arch/arm/mach-uniphier/boot-mode/spl_board.c | 128 +++++++++++++++++++++++++++ include/configs/uniphier.h | 4 +- 4 files changed, 157 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mach-uniphier/boot-mode/spl_board.c (limited to 'include') diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile index d7fefc5bbd0..a8980210b1c 100644 --- a/arch/arm/mach-uniphier/boot-mode/Makefile +++ b/arch/arm/mach-uniphier/boot-mode/Makefile @@ -14,4 +14,8 @@ obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-mode-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-mode-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-mode-ld20.o +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_BOARD_LOAD_IMAGE) += spl_board.o +else obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o +endif diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c index 4b744da2529..d34b9af9a18 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c @@ -51,11 +51,30 @@ u32 spl_boot_device_raw(void) u32 spl_boot_device(void) { - u32 ret; + u32 mode; - ret = spl_boot_device_raw(); + mode = spl_boot_device_raw(); - return ret == BOOT_DEVICE_USB ? BOOT_DEVICE_NOR : ret; + switch (uniphier_get_soc_type()) { +#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) + case SOC_UNIPHIER_PXS2: + case SOC_UNIPHIER_LD6B: + if (mode == BOOT_DEVICE_USB) + mode = BOOT_DEVICE_NOR; + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) + case SOC_UNIPHIER_LD11: + case SOC_UNIPHIER_LD20: + if (mode == BOOT_DEVICE_MMC1 || mode == BOOT_DEVICE_USB) + mode = BOOT_DEVICE_BOARD; + break; +#endif + default: + break; + } + + return mode; } u32 spl_boot_mode(void) diff --git a/arch/arm/mach-uniphier/boot-mode/spl_board.c b/arch/arm/mach-uniphier/boot-mode/spl_board.c new file mode 100644 index 00000000000..86292b6f59e --- /dev/null +++ b/arch/arm/mach-uniphier/boot-mode/spl_board.c @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include "../soc-info.h" + +void spl_board_announce_boot_device(void) +{ + printf("eMMC"); +} + +struct uniphier_romfunc_table { + void *mmc_send_cmd; + void *mmc_card_blockaddr; + void *mmc_switch_part; + void *mmc_load_image; +}; + +static const struct uniphier_romfunc_table uniphier_ld11_romfunc_table = { + .mmc_send_cmd = (void *)0x20d8, + .mmc_card_blockaddr = (void *)0x1b68, + .mmc_switch_part = (void *)0x1c38, + .mmc_load_image = (void *)0x2e48, +}; + +static const struct uniphier_romfunc_table uniphier_ld20_romfunc_table = { + .mmc_send_cmd = (void *)0x2130, + .mmc_card_blockaddr = (void *)0x1ba0, + .mmc_switch_part = (void *)0x1c70, + .mmc_load_image = (void *)0x2ef0, +}; + +int uniphier_rom_get_mmc_funcptr(int (**send_cmd)(u32, u32), + int (**card_blockaddr)(u32), + int (**switch_part)(int), + int (**load_image)(u32, uintptr_t, u32)) +{ + const struct uniphier_romfunc_table *table; + + switch (uniphier_get_soc_type()) { + case SOC_UNIPHIER_LD11: + table = &uniphier_ld11_romfunc_table; + break; + case SOC_UNIPHIER_LD20: + table = &uniphier_ld20_romfunc_table; + break; + default: + printf("unsupported SoC\n"); + return -EINVAL; + } + + *send_cmd = table->mmc_send_cmd; + *card_blockaddr = table->mmc_card_blockaddr; + *switch_part = table->mmc_switch_part; + *load_image = table->mmc_load_image; + + return 0; +} + +int spl_board_load_image(void) +{ + int (*send_cmd)(u32 cmd, u32 arg); + int (*card_blockaddr)(u32 rca); + int (*switch_part)(int part); + int (*load_image)(u32 dev_addr, uintptr_t load_addr, u32 block_cnt); + u32 dev_addr = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; + const u32 rca = 0x1000; /* RCA assigned by Boot ROM */ + int ret; + + ret = uniphier_rom_get_mmc_funcptr(&send_cmd, &card_blockaddr, + &switch_part, &load_image); + if (ret) + return ret; + + /* + * deselect card before SEND_CSD command. + * Do not check the return code. It fails, but it is OK. + */ + (*send_cmd)(0x071a0000, 0); /* CMD7 (arg=0) */ + + /* reset CMD Line */ + writeb(0x6, 0x5a00022f); + while (readb(0x5a00022f)) + cpu_relax(); + + ret = (*card_blockaddr)(rca); + if (ret) { + debug("card is block addressing\n"); + } else { + debug("card is byte addressing\n"); + dev_addr *= 512; + } + + ret = (*send_cmd)(0x071a0000, rca << 16); /* CMD7: select card again */ + if (ret) + printf("failed to select card\n"); + + ret = (*switch_part)(1); /* Switch to Boot Partition 1 */ + if (ret) + printf("failed to switch partition\n"); + + ret = (*load_image)(dev_addr, CONFIG_SYS_TEXT_BASE, 1); + if (ret) { + printf("failed to load image\n"); + return ret; + } + + ret = spl_parse_image_header((void *)CONFIG_SYS_TEXT_BASE); + if (ret) + return ret; + + ret = (*load_image)(dev_addr, spl_image.load_addr, + spl_image.size / 512); + if (ret) { + printf("failed to load image\n"); + return ret; + } + + return 0; +} diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 10fd8c21ea5..058ccd8d8e0 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -288,7 +288,9 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NOR_SUPPORT -#ifndef CONFIG_ARM64 +#ifdef CONFIG_ARM64 +#define CONFIG_SPL_BOARD_LOAD_IMAGE +#else #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #endif -- cgit v1.3.1 From f7e9402b54db4bed916c9adb2565d9713ca5bbfa Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 7 Jun 2016 21:03:46 +0900 Subject: ARM: uniphier: do not erase when updating U-Boot image in eMMC device Unlike NAND, eMMC can be re-written without erasing. Signed-off-by: Masahiro Yamada --- include/configs/uniphier.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 058ccd8d8e0..c826b200ba4 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -245,7 +245,6 @@ "tftpboot $tmp_addr u-boot.bin\0" \ "emmcupdate=mmcsetn &&" \ "mmc partconf $mmc_first_dev 0 1 1 &&" \ - "mmc erase 0 800 &&" \ "tftpboot u-boot-spl.bin &&" \ "mmc write $loadaddr 0 80 &&" \ "tftpboot u-boot.bin &&" \ -- cgit v1.3.1 From bb597c0eeb7ee2f6e983577d993c76a30dd3c2b4 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 7 Jun 2016 08:31:14 +0200 Subject: common: bootdelay: move CONFIG_BOOTDELAY into a Kconfig option move CONFIG_BOOTDELAY into a Kconfig option. Used for this purpose the moveconfig.py tool in tools. Signed-off-by: Heiko Schocher Reviewed-by: Tom Rini Acked-by: Viresh Kumar Acked-by: Igor Grinberg --- common/Kconfig | 9 ++++++ configs/A10-OLinuXino-Lime_defconfig | 1 - configs/A20-OLinuXino_MICRO_defconfig | 2 +- configs/A20-Olimex-SOM-EVB_defconfig | 2 +- configs/B4420QDS_NAND_defconfig | 1 + configs/B4420QDS_SPIFLASH_defconfig | 1 + configs/B4420QDS_defconfig | 1 + configs/B4860QDS_NAND_defconfig | 1 + configs/B4860QDS_SECURE_BOOT_defconfig | 1 + configs/B4860QDS_SPIFLASH_defconfig | 1 + configs/B4860QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/B4860QDS_defconfig | 1 + configs/BSC9131RDB_NAND_SYSCLK100_defconfig | 1 + configs/BSC9131RDB_NAND_defconfig | 1 + configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig | 1 + configs/BSC9131RDB_SPIFLASH_defconfig | 1 + configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig | 1 + configs/BSC9132QDS_NAND_DDRCLK100_defconfig | 1 + configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig | 1 + configs/BSC9132QDS_NAND_DDRCLK133_defconfig | 1 + configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig | 1 + configs/BSC9132QDS_NOR_DDRCLK100_defconfig | 1 + configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig | 1 + configs/BSC9132QDS_NOR_DDRCLK133_defconfig | 1 + .../BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig | 1 + configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig | 1 + .../BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig | 1 + configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig | 1 + .../BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig | 1 + configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig | 1 + .../BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig | 1 + configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig | 1 + configs/CHIP_defconfig | 2 +- configs/CPCI2DP_defconfig | 1 + configs/CPCI4052_defconfig | 1 + configs/Chuwi_V7_CW0825_defconfig | 1 - configs/Cubieboard_defconfig | 1 - configs/Cubietruck_plus_defconfig | 1 - configs/Cyrus_P5020_defconfig | 1 + configs/Cyrus_P5040_defconfig | 1 + configs/Hyundai_A7HD_defconfig | 1 - configs/Linksprite_pcDuino_defconfig | 1 - configs/M52277EVB_defconfig | 1 + configs/M52277EVB_stmicro_defconfig | 1 + configs/M5253DEMO_defconfig | 1 + configs/M5253EVBE_defconfig | 1 + configs/M5272C3_defconfig | 1 + configs/M5275EVB_defconfig | 1 + configs/M5282EVB_defconfig | 1 + configs/MIP405T_defconfig | 1 + configs/MIP405_defconfig | 1 + configs/MPC8308RDB_defconfig | 1 + configs/MPC8313ERDB_33_defconfig | 1 + configs/MPC8313ERDB_66_defconfig | 1 + configs/MPC8313ERDB_NAND_33_defconfig | 1 + configs/MPC8313ERDB_NAND_66_defconfig | 1 + configs/MPC8315ERDB_defconfig | 1 + configs/MPC8323ERDB_defconfig | 1 + configs/MPC832XEMDS_ATM_defconfig | 1 + configs/MPC832XEMDS_HOST_33_defconfig | 1 + configs/MPC832XEMDS_HOST_66_defconfig | 1 + configs/MPC832XEMDS_SLAVE_defconfig | 1 + configs/MPC832XEMDS_defconfig | 1 + configs/MPC8349EMDS_defconfig | 1 + configs/MPC8349ITXGP_defconfig | 1 + configs/MPC8349ITX_LOWBOOT_defconfig | 1 + configs/MPC8349ITX_defconfig | 1 + configs/MPC837XEMDS_HOST_defconfig | 1 + configs/MPC837XEMDS_defconfig | 1 + configs/MPC837XERDB_defconfig | 1 + configs/MPC8536DS_36BIT_defconfig | 1 + configs/MPC8536DS_SDCARD_defconfig | 1 + configs/MPC8536DS_SPIFLASH_defconfig | 1 + configs/MPC8536DS_defconfig | 1 + configs/MPC8540ADS_defconfig | 1 + configs/MPC8541CDS_defconfig | 1 + configs/MPC8541CDS_legacy_defconfig | 1 + configs/MPC8544DS_defconfig | 1 + configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/MPC8555CDS_defconfig | 1 + configs/MPC8555CDS_legacy_defconfig | 1 + configs/MPC8560ADS_defconfig | 1 + configs/MPC8568MDS_defconfig | 1 + configs/MPC8569MDS_ATM_defconfig | 1 + configs/MPC8569MDS_defconfig | 1 + configs/MPC8572DS_36BIT_defconfig | 1 + configs/MPC8572DS_defconfig | 1 + configs/MPC8610HPCD_defconfig | 1 + configs/MPC8641HPCN_36BIT_defconfig | 1 + configs/MPC8641HPCN_defconfig | 1 + configs/Marsboard_A10_defconfig | 1 - configs/Mele_A1000_defconfig | 1 - configs/Merrii_A80_Optimus_defconfig | 1 - configs/MigoR_defconfig | 1 + configs/Mini-X_defconfig | 1 - configs/MiniFAP_defconfig | 1 + configs/O2D300_defconfig | 1 + configs/O2DNT2_RAMBOOT_defconfig | 1 + configs/O2DNT2_defconfig | 1 + configs/O2D_defconfig | 1 + configs/O2I_defconfig | 1 + configs/O2MNT_O2M110_defconfig | 1 + configs/O2MNT_O2M112_defconfig | 1 + configs/O2MNT_O2M113_defconfig | 1 + configs/O2MNT_defconfig | 1 + configs/O3DNT_defconfig | 1 + configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 + .../P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_NAND_defconfig | 1 + configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_NOR_defconfig | 1 + configs/P1010RDB-PA_SDCARD_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 + .../P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_NAND_defconfig | 1 + configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_NOR_defconfig | 1 + configs/P1010RDB-PB_SDCARD_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_defconfig | 1 + configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020MBG-PC_36BIT_defconfig | 1 + configs/P1020MBG-PC_SDCARD_defconfig | 1 + configs/P1020MBG-PC_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 1 + configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 1 + configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig | 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020UTM-PC_36BIT_defconfig | 1 + configs/P1020UTM-PC_SDCARD_defconfig | 1 + configs/P1020UTM-PC_defconfig | 1 + configs/P1021RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1021RDB-PC_36BIT_defconfig | 1 + configs/P1021RDB-PC_NAND_defconfig | 1 + configs/P1021RDB-PC_SDCARD_defconfig | 1 + configs/P1021RDB-PC_SPIFLASH_defconfig | 1 + configs/P1021RDB-PC_defconfig | 1 + configs/P1022DS_36BIT_NAND_defconfig | 1 + configs/P1022DS_36BIT_SDCARD_defconfig | 1 + configs/P1022DS_36BIT_SPIFLASH_defconfig | 1 + configs/P1022DS_36BIT_defconfig | 1 + configs/P1022DS_NAND_defconfig | 1 + configs/P1022DS_SDCARD_defconfig | 1 + configs/P1022DS_SPIFLASH_defconfig | 1 + configs/P1022DS_defconfig | 1 + configs/P1024RDB_36BIT_defconfig | 1 + configs/P1024RDB_NAND_defconfig | 1 + configs/P1024RDB_SDCARD_defconfig | 1 + configs/P1024RDB_SPIFLASH_defconfig | 1 + configs/P1024RDB_defconfig | 1 + configs/P1025RDB_36BIT_defconfig | 1 + configs/P1025RDB_NAND_defconfig | 1 + configs/P1025RDB_SDCARD_defconfig | 1 + configs/P1025RDB_SPIFLASH_defconfig | 1 + configs/P1025RDB_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 1 + configs/P2020RDB-PC_SDCARD_defconfig | 1 + configs/P2020RDB-PC_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_defconfig | 1 + configs/P2041RDB_NAND_defconfig | 1 + configs/P2041RDB_SDCARD_defconfig | 1 + configs/P2041RDB_SECURE_BOOT_defconfig | 1 + configs/P2041RDB_SPIFLASH_defconfig | 1 + configs/P2041RDB_SRIO_PCIE_BOOT_defconfig | 1 + configs/P2041RDB_defconfig | 1 + configs/P3041DS_NAND_SECURE_BOOT_defconfig | 1 + configs/P3041DS_NAND_defconfig | 1 + configs/P3041DS_SDCARD_defconfig | 1 + configs/P3041DS_SECURE_BOOT_defconfig | 1 + configs/P3041DS_SPIFLASH_defconfig | 1 + configs/P3041DS_SRIO_PCIE_BOOT_defconfig | 1 + configs/P3041DS_defconfig | 1 + configs/P4080DS_SDCARD_defconfig | 1 + configs/P4080DS_SECURE_BOOT_defconfig | 1 + configs/P4080DS_SPIFLASH_defconfig | 1 + configs/P4080DS_SRIO_PCIE_BOOT_defconfig | 1 + configs/P4080DS_defconfig | 1 + configs/P5020DS_NAND_SECURE_BOOT_defconfig | 1 + configs/P5020DS_NAND_defconfig | 1 + configs/P5020DS_SDCARD_defconfig | 1 + configs/P5020DS_SECURE_BOOT_defconfig | 1 + configs/P5020DS_SPIFLASH_defconfig | 1 + configs/P5020DS_SRIO_PCIE_BOOT_defconfig | 1 + configs/P5020DS_defconfig | 1 + configs/P5040DS_NAND_SECURE_BOOT_defconfig | 1 + configs/P5040DS_NAND_defconfig | 1 + configs/P5040DS_SDCARD_defconfig | 1 + configs/P5040DS_SECURE_BOOT_defconfig | 1 + configs/P5040DS_SPIFLASH_defconfig | 1 + configs/P5040DS_defconfig | 1 + configs/PATI_defconfig | 1 + configs/PIP405_defconfig | 1 + configs/PLU405_defconfig | 1 + configs/PMC405DE_defconfig | 1 + configs/PMC440_defconfig | 1 + configs/T1023RDB_NAND_defconfig | 1 + configs/T1023RDB_SDCARD_defconfig | 1 + configs/T1023RDB_SECURE_BOOT_defconfig | 1 + configs/T1023RDB_SPIFLASH_defconfig | 1 + configs/T1023RDB_defconfig | 1 + configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 1 + configs/T1024QDS_DDR4_defconfig | 1 + configs/T1024QDS_NAND_defconfig | 1 + configs/T1024QDS_SDCARD_defconfig | 1 + configs/T1024QDS_SECURE_BOOT_defconfig | 1 + configs/T1024QDS_SPIFLASH_defconfig | 1 + configs/T1024QDS_defconfig | 1 + configs/T1024RDB_NAND_defconfig | 1 + configs/T1024RDB_SDCARD_defconfig | 1 + configs/T1024RDB_SECURE_BOOT_defconfig | 1 + configs/T1024RDB_SPIFLASH_defconfig | 1 + configs/T1024RDB_defconfig | 1 + configs/T1040D4RDB_NAND_defconfig | 1 + configs/T1040D4RDB_SDCARD_defconfig | 1 + configs/T1040D4RDB_SECURE_BOOT_defconfig | 1 + configs/T1040D4RDB_SPIFLASH_defconfig | 1 + configs/T1040D4RDB_defconfig | 1 + configs/T1040QDS_DDR4_defconfig | 1 + configs/T1040QDS_SECURE_BOOT_defconfig | 1 + configs/T1040QDS_defconfig | 1 + configs/T1040RDB_NAND_defconfig | 1 + configs/T1040RDB_SDCARD_defconfig | 1 + configs/T1040RDB_SECURE_BOOT_defconfig | 1 + configs/T1040RDB_SPIFLASH_defconfig | 1 + configs/T1040RDB_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 1 + configs/T1042D4RDB_SDCARD_defconfig | 1 + configs/T1042D4RDB_SECURE_BOOT_defconfig | 1 + configs/T1042D4RDB_SPIFLASH_defconfig | 1 + configs/T1042D4RDB_defconfig | 1 + configs/T1042RDB_PI_NAND_defconfig | 1 + configs/T1042RDB_PI_SDCARD_defconfig | 1 + configs/T1042RDB_PI_SPIFLASH_defconfig | 1 + configs/T1042RDB_PI_defconfig | 1 + configs/T1042RDB_SECURE_BOOT_defconfig | 1 + configs/T1042RDB_defconfig | 1 + configs/T2080QDS_NAND_defconfig | 1 + configs/T2080QDS_SDCARD_defconfig | 1 + configs/T2080QDS_SECURE_BOOT_defconfig | 1 + configs/T2080QDS_SPIFLASH_defconfig | 1 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/T2080QDS_defconfig | 1 + configs/T2080RDB_NAND_defconfig | 1 + configs/T2080RDB_SDCARD_defconfig | 1 + configs/T2080RDB_SECURE_BOOT_defconfig | 1 + configs/T2080RDB_SPIFLASH_defconfig | 1 + configs/T2080RDB_SRIO_PCIE_BOOT_defconfig | 1 + configs/T2080RDB_defconfig | 1 + configs/T2081QDS_NAND_defconfig | 1 + configs/T2081QDS_SDCARD_defconfig | 1 + configs/T2081QDS_SPIFLASH_defconfig | 1 + configs/T2081QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/T2081QDS_defconfig | 1 + configs/T4160QDS_NAND_defconfig | 1 + configs/T4160QDS_SDCARD_defconfig | 1 + configs/T4160QDS_SECURE_BOOT_defconfig | 1 + configs/T4160QDS_defconfig | 1 + configs/T4160RDB_defconfig | 1 + configs/T4240QDS_NAND_defconfig | 1 + configs/T4240QDS_SDCARD_defconfig | 1 + configs/T4240QDS_SECURE_BOOT_defconfig | 1 + configs/T4240QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/T4240QDS_defconfig | 1 + configs/T4240RDB_SDCARD_defconfig | 1 + configs/T4240RDB_defconfig | 1 + configs/TQM5200S_HIGHBOOT_defconfig | 1 + configs/TQM5200S_defconfig | 1 + configs/TQM5200_B_HIGHBOOT_defconfig | 1 + configs/TQM5200_B_defconfig | 1 + configs/TQM5200_STK100_defconfig | 1 + configs/TQM5200_defconfig | 1 + configs/TQM823L_LCD_defconfig | 1 + configs/TQM823L_defconfig | 1 + configs/TQM823M_defconfig | 1 + configs/TQM834x_defconfig | 1 + configs/TQM850L_defconfig | 1 + configs/TQM850M_defconfig | 1 + configs/TQM855L_defconfig | 1 + configs/TQM855M_defconfig | 1 + configs/TQM860L_defconfig | 1 + configs/TQM860M_defconfig | 1 + configs/TQM862L_defconfig | 1 + configs/TQM862M_defconfig | 1 + configs/TQM866M_defconfig | 1 + configs/TQM885D_defconfig | 1 + configs/TTTech_defconfig | 1 + configs/TWR-P1025_defconfig | 1 + configs/VCMA9_defconfig | 1 + configs/VOM405_defconfig | 1 + configs/a3m071_defconfig | 1 + configs/a4m2k_defconfig | 1 + configs/acadia_defconfig | 1 + configs/adp-ag101p_defconfig | 1 + configs/alt_defconfig | 1 + configs/am335x_evm_defconfig | 8 ++--- configs/am335x_evm_nor_defconfig | 1 - configs/am335x_evm_norboot_defconfig | 1 - configs/am335x_evm_spiboot_defconfig | 1 - configs/am335x_evm_usbspl_defconfig | 1 - configs/am335x_sl50_defconfig | 1 - configs/am3517_crane_defconfig | 1 + configs/am3517_evm_defconfig | 1 + configs/am437x_hs_evm_defconfig | 3 +- configs/am43xx_evm_ethboot_defconfig | 1 - configs/am43xx_evm_qspiboot_defconfig | 1 - configs/am43xx_evm_usbhost_boot_defconfig | 10 +++--- configs/am57xx_evm_defconfig | 2 +- configs/am57xx_hs_evm_defconfig | 2 +- configs/ap121_defconfig | 9 ++---- configs/ap143_defconfig | 3 +- configs/ap325rxa_defconfig | 1 + configs/ap_sh4a_4a_defconfig | 1 + configs/apalis_t30_defconfig | 1 - configs/apf27_defconfig | 1 + configs/arcangel4-be_defconfig | 1 + configs/arcangel4_defconfig | 1 + configs/arches_defconfig | 1 + configs/aria_defconfig | 1 + configs/armadillo-800eva_defconfig | 1 + configs/aspenite_defconfig | 1 + configs/at91rm9200ek_defconfig | 1 + configs/at91rm9200ek_ram_defconfig | 1 + configs/at91sam9260ek_dataflash_cs0_defconfig | 1 + configs/at91sam9260ek_dataflash_cs1_defconfig | 1 + configs/at91sam9260ek_nandflash_defconfig | 1 + configs/at91sam9261ek_dataflash_cs0_defconfig | 1 + configs/at91sam9261ek_dataflash_cs3_defconfig | 1 + configs/at91sam9261ek_nandflash_defconfig | 1 + configs/at91sam9263ek_dataflash_cs0_defconfig | 1 + configs/at91sam9263ek_dataflash_defconfig | 1 + configs/at91sam9263ek_nandflash_defconfig | 1 + configs/at91sam9263ek_norflash_boot_defconfig | 1 + configs/at91sam9263ek_norflash_defconfig | 1 + configs/at91sam9g10ek_dataflash_cs0_defconfig | 1 + configs/at91sam9g10ek_dataflash_cs3_defconfig | 1 + configs/at91sam9g10ek_nandflash_defconfig | 1 + configs/at91sam9g20ek_2mmc_defconfig | 1 + configs/at91sam9g20ek_2mmc_nandflash_defconfig | 1 + configs/at91sam9g20ek_dataflash_cs0_defconfig | 1 + configs/at91sam9g20ek_dataflash_cs1_defconfig | 1 + configs/at91sam9g20ek_nandflash_defconfig | 1 + configs/at91sam9m10g45ek_mmc_defconfig | 1 + configs/at91sam9m10g45ek_nandflash_defconfig | 1 + configs/at91sam9n12ek_mmc_defconfig | 1 + configs/at91sam9n12ek_nandflash_defconfig | 1 + configs/at91sam9n12ek_spiflash_defconfig | 1 + configs/at91sam9rlek_dataflash_defconfig | 1 + configs/at91sam9rlek_mmc_defconfig | 1 + configs/at91sam9rlek_nandflash_defconfig | 1 + configs/at91sam9x5ek_dataflash_defconfig | 1 + configs/at91sam9x5ek_mmc_defconfig | 1 + configs/at91sam9x5ek_nandflash_defconfig | 1 + configs/at91sam9x5ek_spiflash_defconfig | 1 + configs/at91sam9xeek_dataflash_cs0_defconfig | 1 + configs/at91sam9xeek_dataflash_cs1_defconfig | 1 + configs/at91sam9xeek_nandflash_defconfig | 1 + configs/axm_defconfig | 1 + configs/axs101_defconfig | 1 + configs/axs103_defconfig | 1 + configs/ba10_tv_box_defconfig | 1 - configs/bamboo_defconfig | 1 + configs/bcm28155_ap_defconfig | 2 +- configs/bcm28155_w1d_defconfig | 2 +- configs/beaver_defconfig | 1 - configs/bf525-ucr2_defconfig | 1 + configs/bf537-minotaur_defconfig | 1 + configs/bf537-srv1_defconfig | 1 + configs/bg0900_defconfig | 1 + configs/birdland_bav335a_defconfig | 1 - configs/birdland_bav335b_defconfig | 1 - configs/blackstamp_defconfig | 1 + configs/blackvme_defconfig | 1 + configs/bubinga_defconfig | 1 + configs/caddy2_defconfig | 1 + configs/cam5200_defconfig | 1 + configs/cam5200_niosflash_defconfig | 1 + configs/canmb_defconfig | 1 + configs/canyonlands_defconfig | 1 + configs/cardhu_defconfig | 1 - configs/charon_defconfig | 1 + configs/chromebook_jerry_defconfig | 1 - configs/clearfog_defconfig | 3 +- configs/cm5200_defconfig | 1 + configs/cm_t3517_defconfig | 1 + configs/cm_t35_defconfig | 1 + configs/cm_t54_defconfig | 1 + configs/cobra5272_defconfig | 1 + configs/colibri_t20_defconfig | 1 - configs/colibri_t30_defconfig | 1 - .../controlcenterd_36BIT_SDCARD_DEVELOP_defconfig | 1 + configs/controlcenterd_36BIT_SDCARD_defconfig | 1 + configs/corvus_defconfig | 1 + configs/d2net_v2_defconfig | 1 + configs/da850_am18xxevm_defconfig | 1 + configs/da850evm_defconfig | 1 + configs/da850evm_direct_nor_defconfig | 1 + configs/dalmore_defconfig | 1 - configs/db-88f6720_defconfig | 1 + configs/db-88f6820-gp_defconfig | 1 + configs/db-mv784mp-gp_defconfig | 1 + configs/dbau1000_defconfig | 1 - configs/dbau1100_defconfig | 1 - configs/dbau1500_defconfig | 1 - configs/dbau1550_defconfig | 1 - configs/dbau1550_el_defconfig | 1 - configs/devconcenter_defconfig | 1 + configs/dlvision-10g_defconfig | 1 + configs/dlvision_defconfig | 1 + configs/dns325_defconfig | 1 + configs/dockstar_defconfig | 1 + configs/dra7xx_evm_defconfig | 8 ++--- configs/dra7xx_hs_evm_defconfig | 10 +++--- configs/draco_defconfig | 1 + configs/dreamplug_defconfig | 1 + configs/ds414_defconfig | 1 + configs/dserve_dsrv9703c_defconfig | 1 - configs/ea20_defconfig | 1 + configs/eb_cpu5282_defconfig | 1 + configs/eb_cpu5282_internal_defconfig | 1 + configs/eco5pk_defconfig | 1 + configs/ecovec_defconfig | 1 + configs/edminiv2_defconfig | 1 + configs/espresso7420_defconfig | 3 +- configs/ethernut5_defconfig | 1 + configs/evb-rk3036_defconfig | 1 - configs/firefly-rk3288_defconfig | 1 - configs/flea3_defconfig | 1 + configs/fo300_defconfig | 1 + configs/gdppc440etx_defconfig | 1 + configs/glacier_defconfig | 1 + configs/glacier_ramboot_defconfig | 1 + configs/goflexhome_defconfig | 1 + configs/gose_defconfig | 1 + configs/gplugd_defconfig | 1 + configs/gr_cpci_ax2000_defconfig | 3 +- configs/gr_ep2s60_defconfig | 3 +- configs/gr_xc3s_1500_defconfig | 3 +- configs/grsim_defconfig | 3 +- configs/grsim_leon2_defconfig | 3 +- configs/guruplug_defconfig | 1 + configs/h8_homlet_v2_defconfig | 1 - configs/haleakala_defconfig | 1 + configs/harmony_defconfig | 1 - configs/hikey_defconfig | 3 +- configs/hrcon_defconfig | 1 + configs/hrcon_dh_defconfig | 1 + configs/iNet_3F_defconfig | 1 - configs/iNet_3W_defconfig | 1 - configs/ib62x0_defconfig | 1 + configs/icon_defconfig | 1 + configs/iconnect_defconfig | 1 + configs/imx31_phycore_defconfig | 1 + configs/imx31_phycore_eet_defconfig | 1 + configs/inet1_defconfig | 1 - configs/inet97fv2_defconfig | 1 - configs/inet9f_rev03_defconfig | 1 - configs/inetspace_v2_defconfig | 1 + configs/intip_defconfig | 1 + configs/io64_defconfig | 1 + configs/io_defconfig | 1 + configs/iocon_defconfig | 1 + configs/ipek01_defconfig | 1 + configs/jesurun_q5_defconfig | 1 - configs/jetson-tk1_defconfig | 1 - configs/jupiter_defconfig | 1 + configs/katmai_defconfig | 1 + configs/kilauea_defconfig | 1 + configs/koelsch_defconfig | 1 + configs/kylin-rk3036_defconfig | 1 - configs/kzm9g_defconfig | 1 + configs/lager_defconfig | 1 + configs/ls1012afrdm_qspi_defconfig | 3 +- configs/ls1012aqds_qspi_defconfig | 3 +- configs/ls1012ardb_qspi_defconfig | 3 +- configs/ls1021aqds_ddr4_nor_defconfig | 6 ++-- configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 6 ++-- configs/ls1021aqds_nand_defconfig | 5 +-- configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 5 +-- configs/ls1021aqds_nor_defconfig | 6 ++-- configs/ls1021aqds_nor_lpuart_defconfig | 6 ++-- configs/ls1021aqds_qspi_defconfig | 6 ++-- configs/ls1021aqds_sdcard_ifc_defconfig | 4 +-- configs/ls1021aqds_sdcard_qspi_defconfig | 4 +-- configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 5 +-- configs/ls1021atwr_nor_defconfig | 6 ++-- configs/ls1021atwr_nor_lpuart_defconfig | 6 ++-- configs/ls1021atwr_qspi_defconfig | 6 ++-- configs/ls1021atwr_sdcard_ifc_defconfig | 5 +-- configs/ls1021atwr_sdcard_qspi_defconfig | 6 ++-- configs/ls1043aqds_defconfig | 1 + configs/ls1043aqds_lpuart_defconfig | 1 + configs/ls1043aqds_nand_defconfig | 1 + configs/ls1043aqds_nor_ddr3_defconfig | 1 + configs/ls1043aqds_qspi_defconfig | 1 + configs/ls1043aqds_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_sdcard_qspi_defconfig | 1 + configs/ls1043ardb_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_defconfig | 1 + configs/ls1043ardb_nand_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 1 + configs/ls2080a_emu_defconfig | 2 +- configs/ls2080a_simu_defconfig | 2 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 1 + configs/ls2080aqds_defconfig | 1 + configs/ls2080aqds_nand_defconfig | 1 + configs/ls2080ardb_SECURE_BOOT_defconfig | 1 + configs/ls2080ardb_defconfig | 1 + configs/ls2080ardb_nand_defconfig | 1 + configs/lschlv2_defconfig | 1 + configs/lsxhl_defconfig | 1 + configs/luan_defconfig | 1 + configs/lwmon5_defconfig | 1 + configs/m28evk_defconfig | 1 + configs/m53evk_defconfig | 1 + configs/ma5d4evk_defconfig | 1 + configs/makalu_defconfig | 1 + configs/malta64_defconfig | 1 - configs/malta64el_defconfig | 1 - configs/malta_defconfig | 1 - configs/maltael_defconfig | 1 - configs/maxbcm_defconfig | 1 + configs/mcx_defconfig | 1 + configs/mecp5123_defconfig | 1 + configs/medcom-wide_defconfig | 1 - configs/meesc_dataflash_defconfig | 1 + configs/meesc_defconfig | 1 + configs/mk802_defconfig | 1 - configs/mk802ii_defconfig | 1 - configs/mpc5121ads_defconfig | 1 + configs/mpc5121ads_rev2_defconfig | 1 + configs/mpc8308_p1m_defconfig | 1 + configs/ms7722se_defconfig | 1 + configs/mt_ventoux_defconfig | 1 + configs/munices_defconfig | 1 + configs/mx23_olinuxino_defconfig | 1 + configs/mx31ads_defconfig | 1 + configs/mx53ard_defconfig | 1 + configs/mx53evk_defconfig | 1 + configs/mx53smd_defconfig | 1 + configs/nas220_defconfig | 1 + configs/neo_defconfig | 1 + configs/net2big_v2_defconfig | 1 + configs/netspace_lite_v2_defconfig | 1 + configs/netspace_max_v2_defconfig | 1 + configs/netspace_mini_v2_defconfig | 1 + configs/netspace_v2_defconfig | 1 + configs/nokia_rx51_defconfig | 1 + configs/nsa310s_defconfig | 1 + configs/nyan-big_defconfig | 1 - configs/odroid-xu3_defconfig | 1 - configs/omap3_evm_defconfig | 1 + configs/omap3_ha_defconfig | 1 + configs/omap3_logic_defconfig | 2 +- configs/omapl138_lcdk_defconfig | 1 + configs/openrd_base_defconfig | 1 + configs/openrd_client_defconfig | 1 + configs/openrd_ultimate_defconfig | 1 + configs/orangepi_2_defconfig | 2 -- configs/orangepi_one_defconfig | 2 -- configs/orangepi_pc_defconfig | 1 - configs/orangepi_plus_defconfig | 2 -- configs/p2771-0000_defconfig | 1 - configs/paz00_defconfig | 1 - configs/pb1000_defconfig | 1 - configs/pcm030_LOWBOOT_defconfig | 1 + configs/pcm030_defconfig | 1 + configs/pcm051_rev1_defconfig | 1 - configs/pcm051_rev3_defconfig | 1 - configs/pcm052_defconfig | 1 + configs/pdm360ng_defconfig | 1 + configs/pic32mzdask_defconfig | 2 +- configs/picosam9g45_defconfig | 1 + configs/pine64_plus_defconfig | 2 +- configs/plutux_defconfig | 1 - configs/pm9261_defconfig | 1 + configs/pm9263_defconfig | 1 + configs/pm9g45_defconfig | 1 + configs/pogo_e02_defconfig | 1 + configs/porter_defconfig | 1 + configs/pov_protab2_ips9_defconfig | 1 - configs/pxm2_defconfig | 1 + configs/qemu_mips64_defconfig | 2 +- configs/qemu_mips64el_defconfig | 2 +- configs/qemu_mips_defconfig | 2 +- configs/qemu_mipsel_defconfig | 2 +- configs/r0p7734_defconfig | 1 + configs/r7780mp_defconfig | 1 + configs/rainier_defconfig | 1 + configs/rainier_ramboot_defconfig | 1 + configs/rastaban_defconfig | 1 + configs/redwood_defconfig | 1 + configs/rock2_defconfig | 1 - configs/rsk7264_defconfig | 1 + configs/rsk7269_defconfig | 1 + configs/rut_defconfig | 1 + configs/sama5d2_ptc_nandflash_defconfig | 1 + configs/sama5d2_ptc_spiflash_defconfig | 1 + configs/sama5d2_xplained_mmc_defconfig | 3 +- configs/sama5d2_xplained_spiflash_defconfig | 3 +- configs/sama5d3_xplained_mmc_defconfig | 3 +- configs/sama5d3_xplained_nandflash_defconfig | 3 +- configs/sama5d3xek_mmc_defconfig | 3 +- configs/sama5d3xek_nandflash_defconfig | 3 +- configs/sama5d3xek_spiflash_defconfig | 3 +- configs/sama5d4_xplained_mmc_defconfig | 3 +- configs/sama5d4_xplained_nandflash_defconfig | 3 +- configs/sama5d4_xplained_spiflash_defconfig | 3 +- configs/sama5d4ek_mmc_defconfig | 3 +- configs/sama5d4ek_nandflash_defconfig | 3 +- configs/sama5d4ek_spiflash_defconfig | 3 +- configs/sandbox_defconfig | 8 ++--- configs/sansa_fuze_plus_defconfig | 1 + configs/sbc8349_PCI_33_defconfig | 1 + configs/sbc8349_PCI_66_defconfig | 1 + configs/sbc8349_defconfig | 1 + configs/sbc8548_PCI_33_PCIE_defconfig | 1 + configs/sbc8548_PCI_33_defconfig | 1 + configs/sbc8548_PCI_66_PCIE_defconfig | 1 + configs/sbc8548_PCI_66_defconfig | 1 + configs/sbc8548_defconfig | 1 + configs/sbc8641d_defconfig | 1 + configs/sc_sps_1_defconfig | 1 + configs/seaboard_defconfig | 1 - configs/sequoia_defconfig | 1 + configs/sequoia_ramboot_defconfig | 1 + configs/sh7752evb_defconfig | 1 + configs/sh7753evb_defconfig | 1 + configs/sh7757lcr_defconfig | 1 + configs/sh7785lcr_32bit_defconfig | 1 + configs/sh7785lcr_defconfig | 1 + configs/sheevaplug_defconfig | 1 + configs/silk_defconfig | 1 + configs/smartweb_defconfig | 1 + configs/smdk2410_defconfig | 1 + configs/smdkc100_defconfig | 1 + configs/smdkv310_defconfig | 1 - configs/snapper9260_defconfig | 1 + configs/snapper9g20_defconfig | 1 + configs/socfpga_arria5_defconfig | 3 +- configs/socfpga_cyclone5_defconfig | 3 +- configs/socfpga_de0_nano_soc_defconfig | 3 +- configs/socfpga_mcvevk_defconfig | 3 +- configs/socfpga_sockit_defconfig | 3 +- configs/socfpga_socrates_defconfig | 3 +- configs/socfpga_sr1500_defconfig | 3 +- configs/socfpga_vining_fpga_defconfig | 3 +- configs/stm32f429-discovery_defconfig | 1 + configs/stm32f746-disco_defconfig | 1 + configs/stout_defconfig | 1 + configs/strider_con_defconfig | 1 + configs/strider_con_dp_defconfig | 1 + configs/strider_cpu_defconfig | 1 + configs/strider_cpu_dp_defconfig | 1 + configs/stv0991_defconfig | 1 + configs/sunxi_Gemei_G9_defconfig | 1 - configs/sycamore_defconfig | 1 + configs/t3corp_defconfig | 1 + configs/tao3530_defconfig | 1 + configs/taurus_defconfig | 1 + configs/tb100_defconfig | 1 + configs/tec-ng_defconfig | 1 - configs/tec_defconfig | 1 - configs/theadorable_debug_defconfig | 1 + configs/theadorable_defconfig | 1 + configs/thuban_defconfig | 1 + configs/thunderx_88xx_defconfig | 2 +- configs/ti816x_evm_defconfig | 1 + configs/tplink_wdr4300_defconfig | 36 ++++++++++------------ configs/trimslice_defconfig | 1 - configs/twister_defconfig | 1 + configs/uniphier_ld11_defconfig | 1 + configs/uniphier_ld20_defconfig | 1 + configs/uniphier_ld4_sld8_defconfig | 1 + configs/uniphier_pro4_defconfig | 1 + configs/uniphier_pxs2_ld6b_defconfig | 1 + configs/uniphier_sld3_defconfig | 1 + configs/usb_a9263_dataflash_defconfig | 1 + configs/v38b_defconfig | 1 + configs/vct_platinum_defconfig | 2 +- configs/vct_platinum_onenand_defconfig | 2 +- configs/vct_platinum_onenand_small_defconfig | 2 +- configs/vct_platinum_small_defconfig | 2 +- configs/vct_platinumavc_defconfig | 2 +- configs/vct_platinumavc_onenand_defconfig | 2 +- configs/vct_platinumavc_onenand_small_defconfig | 2 +- configs/vct_platinumavc_small_defconfig | 2 +- configs/vct_premium_defconfig | 2 +- configs/vct_premium_onenand_defconfig | 2 +- configs/vct_premium_onenand_small_defconfig | 2 +- configs/vct_premium_small_defconfig | 2 +- configs/ve8313_defconfig | 1 + configs/venice2_defconfig | 1 - configs/ventana_defconfig | 1 - configs/vexpress_aemv8a_dram_defconfig | 1 - configs/vexpress_aemv8a_juno_defconfig | 1 - configs/vexpress_aemv8a_semi_defconfig | 1 - configs/vexpress_ca15_tc2_defconfig | 1 - configs/vexpress_ca5x2_defconfig | 1 - configs/vexpress_ca9x4_defconfig | 1 - configs/vf610twr_defconfig | 1 + configs/vf610twr_nand_defconfig | 1 + configs/vinco_defconfig | 1 + configs/vme8349_defconfig | 1 + configs/walnut_defconfig | 1 + configs/whistler_defconfig | 1 - configs/woodburn_defconfig | 1 + configs/woodburn_sd_defconfig | 1 + configs/work_92105_defconfig | 1 + configs/wtk_defconfig | 1 + configs/x600_defconfig | 1 + configs/xfi3_defconfig | 1 + configs/xilinx-ppc405-generic_defconfig | 1 + configs/xilinx-ppc440-generic_defconfig | 1 + configs/xilinx_zynqmp_ep_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 + configs/xilinx_zynqmp_zcu102_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 + configs/xpedite1000_defconfig | 1 + configs/xpedite517x_defconfig | 1 + configs/xpedite520x_defconfig | 1 + configs/xpedite537x_defconfig | 1 + configs/xpedite550x_defconfig | 1 + configs/yellowstone_defconfig | 1 + configs/yosemite_defconfig | 1 + configs/yucca_defconfig | 1 + configs/zmx25_defconfig | 1 + configs/zynq_microzed_defconfig | 1 + configs/zynq_picozed_defconfig | 1 + configs/zynq_zc702_defconfig | 1 + configs/zynq_zc706_defconfig | 1 + configs/zynq_zc770_xm010_defconfig | 1 + configs/zynq_zc770_xm011_defconfig | 1 + configs/zynq_zc770_xm012_defconfig | 1 + configs/zynq_zc770_xm013_defconfig | 1 + configs/zynq_zed_defconfig | 1 + configs/zynq_zybo_defconfig | 1 + include/config_distro_defaults.h | 1 - include/configs/B4860QDS.h | 1 - include/configs/BSC9131RDB.h | 1 - include/configs/BSC9132QDS.h | 1 - include/configs/C29XPCIE.h | 1 - include/configs/CPCI2DP.h | 1 - include/configs/CPCI4052.h | 1 - include/configs/M5208EVBE.h | 1 - include/configs/M52277EVB.h | 1 - include/configs/M5235EVB.h | 1 - include/configs/M5253DEMO.h | 1 - include/configs/M5253EVBE.h | 1 - include/configs/M5272C3.h | 1 - include/configs/M5275EVB.h | 1 - include/configs/M5282EVB.h | 1 - include/configs/M53017EVB.h | 1 - include/configs/M5329EVB.h | 1 - include/configs/M5373EVB.h | 1 - include/configs/M54418TWR.h | 1 - include/configs/M54451EVB.h | 1 - include/configs/M54455EVB.h | 1 - include/configs/M5475EVB.h | 1 - include/configs/M5485EVB.h | 1 - include/configs/MIP405.h | 1 - include/configs/MPC8308RDB.h | 1 - include/configs/MPC8313ERDB.h | 1 - include/configs/MPC8315ERDB.h | 1 - include/configs/MPC8323ERDB.h | 1 - include/configs/MPC832XEMDS.h | 1 - include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349ITX.h | 1 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 1 - include/configs/MPC8536DS.h | 1 - include/configs/MPC8540ADS.h | 1 - include/configs/MPC8541CDS.h | 1 - include/configs/MPC8544DS.h | 1 - include/configs/MPC8548CDS.h | 1 - include/configs/MPC8555CDS.h | 1 - include/configs/MPC8560ADS.h | 1 - include/configs/MPC8568MDS.h | 1 - include/configs/MPC8569MDS.h | 1 - include/configs/MPC8572DS.h | 1 - include/configs/MPC8610HPCD.h | 1 - include/configs/MPC8641HPCN.h | 1 - include/configs/MigoR.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/P1022DS.h | 1 - include/configs/P1023RDB.h | 1 - include/configs/P2041RDB.h | 1 - include/configs/PATI.h | 5 --- include/configs/PIP405.h | 1 - include/configs/PLU405.h | 1 - include/configs/PMC405DE.h | 1 - include/configs/PMC440.h | 1 - include/configs/T102xQDS.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T1040QDS.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240QDS.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/TQM5200.h | 1 - include/configs/TQM823L.h | 1 - include/configs/TQM823M.h | 1 - include/configs/TQM834x.h | 1 - include/configs/TQM850L.h | 1 - include/configs/TQM850M.h | 1 - include/configs/TQM855L.h | 1 - include/configs/TQM855M.h | 1 - include/configs/TQM860L.h | 1 - include/configs/TQM860M.h | 1 - include/configs/TQM862L.h | 1 - include/configs/TQM862M.h | 1 - include/configs/TQM866M.h | 1 - include/configs/TQM885D.h | 1 - include/configs/UCP1020.h | 3 -- include/configs/VCMA9.h | 1 - include/configs/VOM405.h | 1 - include/configs/a3m071.h | 1 - include/configs/a4m072.h | 1 - include/configs/ac14xx.h | 1 - include/configs/adp-ag101p.h | 1 - include/configs/am335x_sl50.h | 1 - include/configs/am3517_crane.h | 1 - include/configs/am3517_evm.h | 1 - include/configs/amcc-common.h | 1 - include/configs/amcore.h | 1 - include/configs/ap121.h | 1 - include/configs/ap143.h | 1 - include/configs/ap325rxa.h | 1 - include/configs/ap_sh4a_4a.h | 1 - include/configs/apf27.h | 1 - include/configs/apx4devkit.h | 1 - include/configs/arcangel4.h | 1 - include/configs/aria.h | 1 - include/configs/armadillo-800eva.h | 1 - include/configs/astro_mcf5373l.h | 13 -------- include/configs/at91-sama5_common.h | 1 - include/configs/at91rm9200ek.h | 1 - include/configs/at91sam9260ek.h | 1 - include/configs/at91sam9261ek.h | 1 - include/configs/at91sam9263ek.h | 1 - include/configs/at91sam9m10g45ek.h | 1 - include/configs/at91sam9n12ek.h | 1 - include/configs/at91sam9rlek.h | 1 - include/configs/at91sam9x5ek.h | 1 - include/configs/atngw100.h | 1 - include/configs/atngw100mkii.h | 1 - include/configs/atstk1002.h | 1 - include/configs/axs101.h | 1 - include/configs/bct-brettl2.h | 1 - include/configs/bf525-ucr2.h | 1 - include/configs/bf537-minotaur.h | 6 ---- include/configs/bf537-srv1.h | 9 ------ include/configs/bfin_adi_common.h | 2 -- include/configs/bg0900.h | 1 - include/configs/blackstamp.h | 1 - include/configs/blackvme.h | 1 - include/configs/br4.h | 1 - include/configs/calimain.h | 1 - include/configs/canmb.h | 1 - include/configs/cm5200.h | 1 - include/configs/cm_t35.h | 1 - include/configs/cm_t3517.h | 1 - include/configs/cm_t54.h | 2 -- include/configs/cobra5272.h | 1 - include/configs/colibri_pxa270.h | 1 - include/configs/colibri_vf.h | 1 - include/configs/controlcenterd.h | 2 -- include/configs/corenet_ds.h | 1 - include/configs/corvus.h | 1 - include/configs/cyrus.h | 1 - include/configs/da850evm.h | 1 - include/configs/dbau1x00.h | 1 - include/configs/devkit3250.h | 1 - include/configs/digsy_mtc.h | 1 - include/configs/draco.h | 2 -- include/configs/ea20.h | 1 - include/configs/eb_cpu5282.h | 1 - include/configs/eco5pk.h | 1 - include/configs/ecovec.h | 1 - include/configs/edb93xx.h | 1 - include/configs/edminiv2.h | 1 - include/configs/espt.h | 1 - include/configs/ethernut5.h | 1 - include/configs/flea3.h | 1 - include/configs/ge_bx50v3.h | 1 - include/configs/gr_cpci_ax2000.h | 1 - include/configs/gr_ep2s60.h | 1 - include/configs/gr_xc3s_1500.h | 1 - include/configs/grasshopper.h | 1 - include/configs/grsim.h | 1 - include/configs/grsim_leon2.h | 1 - include/configs/h2200.h | 1 - include/configs/hrcon.h | 1 - include/configs/ids8313.h | 1 - include/configs/imx27lite-common.h | 1 - include/configs/imx31_phycore.h | 1 - include/configs/inka4x0.h | 1 - include/configs/integratorap.h | 1 - include/configs/integratorcp.h | 1 - include/configs/ipam390.h | 1 - include/configs/ipek01.h | 1 - include/configs/jupiter.h | 1 - include/configs/km/keymile-common.h | 1 - include/configs/kwb.h | 1 - include/configs/kzm9g.h | 1 - include/configs/legoev3.h | 1 - include/configs/ls1012a_common.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - include/configs/ls1043a_common.h | 1 - include/configs/ls2080a_common.h | 1 - include/configs/lwmon5.h | 1 - include/configs/m28evk.h | 1 - include/configs/m53evk.h | 1 - include/configs/ma5d4evk.h | 1 - include/configs/manroland/common.h | 1 - include/configs/mcx.h | 1 - include/configs/mecp5123.h | 1 - include/configs/meesc.h | 1 - include/configs/microblaze-generic.h | 1 - include/configs/motionpro.h | 1 - include/configs/mpc5121ads.h | 1 - include/configs/mpc8308_p1m.h | 1 - include/configs/ms7722se.h | 1 - include/configs/ms7750se.h | 1 - include/configs/mt_ventoux.h | 1 - include/configs/munices.h | 1 - include/configs/mv-common.h | 1 - include/configs/mx23_olinuxino.h | 1 - include/configs/mx23evk.h | 1 - include/configs/mx25pdk.h | 1 - include/configs/mx28evk.h | 1 - include/configs/mx31ads.h | 1 - include/configs/mx31pdk.h | 1 - include/configs/mx35pdk.h | 1 - include/configs/mx51evk.h | 1 - include/configs/mx53ard.h | 1 - include/configs/mx53evk.h | 1 - include/configs/mx53loco.h | 1 - include/configs/mx53smd.h | 1 - include/configs/mx6_common.h | 1 - include/configs/mx7_common.h | 1 - include/configs/nokia_rx51.h | 1 - include/configs/o2dnt-common.h | 1 - include/configs/omap3_cairo.h | 2 -- include/configs/omap3_evm.h | 1 - include/configs/omap3_evm_quick_mmc.h | 1 - include/configs/omap3_evm_quick_nand.h | 1 - include/configs/omapl138_lcdk.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/p1_twr.h | 1 - include/configs/pb1x00.h | 1 - include/configs/pcm030.h | 1 - include/configs/pcm052.h | 1 - include/configs/pdm360ng.h | 1 - include/configs/pic32mzdask.h | 1 - include/configs/picosam9g45.h | 1 - include/configs/pm9261.h | 1 - include/configs/pm9263.h | 1 - include/configs/pm9g45.h | 1 - include/configs/pr1.h | 1 - include/configs/pxm2.h | 2 -- include/configs/qemu-mips.h | 1 - include/configs/qemu-mips64.h | 1 - include/configs/qemu-ppce500.h | 1 - include/configs/r0p7734.h | 1 - include/configs/r2dplus.h | 1 - include/configs/r7780mp.h | 1 - include/configs/rastaban.h | 2 -- include/configs/rcar-gen2-common.h | 1 - include/configs/redwood.h | 1 - include/configs/rpi.h | 1 - include/configs/rsk7264.h | 1 - include/configs/rsk7269.h | 1 - include/configs/rut.h | 2 -- include/configs/sansa_fuze_plus.h | 1 - include/configs/sbc8349.h | 1 - include/configs/sbc8548.h | 1 - include/configs/sbc8641d.h | 1 - include/configs/sc_sps_1.h | 1 - include/configs/sh7752evb.h | 1 - include/configs/sh7753evb.h | 1 - include/configs/sh7757lcr.h | 1 - include/configs/sh7763rdp.h | 1 - include/configs/sh7785lcr.h | 1 - include/configs/smartweb.h | 1 - include/configs/smdk2410.h | 1 - include/configs/smdkc100.h | 1 - include/configs/snapper9260.h | 1 - include/configs/socfpga_arria5_socdk.h | 1 - include/configs/socfpga_cyclone5_socdk.h | 1 - include/configs/socfpga_de0_nano_soc.h | 1 - include/configs/socfpga_mcvevk.h | 1 - include/configs/socfpga_sockit.h | 1 - include/configs/socfpga_socrates.h | 1 - include/configs/socfpga_sr1500.h | 1 - include/configs/socfpga_vining_fpga.h | 1 - include/configs/socrates.h | 1 - include/configs/spear-common.h | 6 ---- include/configs/stm32f429-discovery.h | 1 - include/configs/stm32f746-disco.h | 1 - include/configs/strider.h | 1 - include/configs/stv0991.h | 1 - include/configs/tao3530.h | 1 - include/configs/taurus.h | 1 - include/configs/tb100.h | 1 - include/configs/thuban.h | 2 -- include/configs/thunderx_88xx.h | 1 - include/configs/ti814x_evm.h | 1 - include/configs/ti816x_evm.h | 1 - include/configs/tplink_wdr4300.h | 1 - include/configs/tricorder.h | 1 - include/configs/ts4800.h | 1 - include/configs/tseries.h | 1 - include/configs/twister.h | 1 - include/configs/uniphier.h | 1 - include/configs/usb_a9263.h | 1 - include/configs/v38b.h | 1 - include/configs/vct.h | 1 - include/configs/ve8313.h | 1 - include/configs/vexpress_aemv8a.h | 3 -- include/configs/vexpress_common.h | 1 - include/configs/vf610twr.h | 1 - include/configs/vme8349.h | 1 - include/configs/warp7.h | 1 - include/configs/woodburn_common.h | 1 - include/configs/work_92105.h | 1 - include/configs/x600.h | 1 - include/configs/x86-common.h | 1 - include/configs/xfi3.h | 1 - include/configs/xilinx-ppc.h | 1 - include/configs/xilinx_zynqmp.h | 1 - include/configs/xpedite1000.h | 1 - include/configs/xpedite517x.h | 1 - include/configs/xpedite520x.h | 1 - include/configs/xpedite537x.h | 1 - include/configs/xpedite550x.h | 1 - include/configs/zipitz2.h | 1 - include/configs/zmx25.h | 1 - include/configs/zynq-common.h | 1 - 1074 files changed, 788 insertions(+), 590 deletions(-) (limited to 'include') diff --git a/common/Kconfig b/common/Kconfig index 067545d8a3e..4d17b101a1a 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -97,6 +97,15 @@ config BOOTSTAGE_STASH_SIZE endmenu +config BOOTDELAY + int "delay in seconds before automatically booting" + default 0 + help + Delay before automatically running bootcmd; + set to -1 to disable autoboot. + set to -2 to autoboot with no delay and not check for abort + (even when CONFIG_ZERO_BOOTDELAY_CHECK is defined). + config CONSOLE_RECORD bool "Console recording" help diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index 8cb7ac7bb11..378f7a19286 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=480 CONFIG_DRAM_EMR1=4 CONFIG_SYS_CLK_FREQ=912000000 diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index e4168fa3e30..f121cabeb16 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -14,6 +14,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_ETH_DESIGNWARE=y -CONFIG_USB_EHCI_HCD=y CONFIG_AXP_ALDO3_VOLT=2800 CONFIG_AXP_ALDO4_VOLT=2800 +CONFIG_USB_EHCI_HCD=y diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index 6430606f474..57609b384fe 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -17,6 +17,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)" # CONFIG_CMD_FPGA is not set CONFIG_RTL8211X_PHY_FORCE_MASTER=y CONFIG_ETH_DESIGNWARE=y -CONFIG_USB_EHCI_HCD=y CONFIG_AXP_ALDO3_VOLT=2800 CONFIG_AXP_ALDO4_VOLT=2800 +CONFIG_USB_EHCI_HCD=y diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig index 369afbb22a7..06d89af4b0b 100644 --- a/configs/B4420QDS_NAND_defconfig +++ b/configs/B4420QDS_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_SF=y diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig index 408e84e58f4..0e2d3f9908b 100644 --- a/configs/B4420QDS_SPIFLASH_defconfig +++ b/configs/B4420QDS_SPIFLASH_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_SF=y diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig index bab96cac606..36986b5fd8f 100644 --- a/configs/B4420QDS_defconfig +++ b/configs/B4420QDS_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_SF=y diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig index 10fe1d03616..6aea615f57c 100644 --- a/configs/B4860QDS_NAND_defconfig +++ b/configs/B4860QDS_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_SF=y diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig index 5e754ebee12..505e0148543 100644 --- a/configs/B4860QDS_SECURE_BOOT_defconfig +++ b/configs/B4860QDS_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_SF=y diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig index fca6f5aeb01..4696d6d37e3 100644 --- a/configs/B4860QDS_SPIFLASH_defconfig +++ b/configs/B4860QDS_SPIFLASH_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_SF=y diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig index e833e0c3915..dfbf2cb4d82 100644 --- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_GREPENV=y diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig index cd276383598..b6c45ea3365 100644 --- a/configs/B4860QDS_defconfig +++ b/configs/B4860QDS_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_SF=y diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig index cdfccbed432..85d4a85bdb1 100644 --- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig +++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig index 555e446a3bc..2937dc3cbbd 100644 --- a/configs/BSC9131RDB_NAND_defconfig +++ b/configs/BSC9131RDB_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig index 014916c0d47..fd33d142910 100644 --- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig +++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig index 941fe75f374..572de826dd4 100644 --- a/configs/BSC9131RDB_SPIFLASH_defconfig +++ b/configs/BSC9131RDB_SPIFLASH_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig index ae8271be584..523b7ada86b 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig index 502ba3c7ca1..f15c4a16db8 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig index d60c0c1bf84..6d685b6d48f 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig index 43fa804e3b7..7cdc2b2a782 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig index adc42c515a3..8fdc698aa3f 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig index d591a373fc1..c40b6fe31d4 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig index 034109eba4a..b5fc43376ac 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig index c804b4f1cd3..c4bbb5140b3 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig index 49609b7f5ca..456fb8dc626 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig index a64db9bb98d..867e433465f 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig index 0850d84da91..effdd33ef18 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig index 7d7ecd277db..3d863315440 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig index a46d8d77f08..0ac319cf249 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig index 3ef15fcef7e..25e5afa96fc 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig index 307813cc8f7..00fe70b9171 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig index aef5e7bdd91..f20f23102e8 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index 3e8c0a11881..19ae280dfbd 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -13,10 +13,10 @@ CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 +CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Allwinner Technology" CONFIG_G_DNL_VENDOR_NUM=0x1f3a CONFIG_G_DNL_PRODUCT_NUM=0x1010 -CONFIG_USB_EHCI_HCD=y diff --git a/configs/CPCI2DP_defconfig b/configs/CPCI2DP_defconfig index ea0775d5858..99e4ad007d1 100644 --- a/configs/CPCI2DP_defconfig +++ b/configs/CPCI2DP_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_CPCI2DP=y +CONFIG_BOOTDELAY=3 CONFIG_LOOPW=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/CPCI4052_defconfig b/configs/CPCI4052_defconfig index 25818bd3b44..d7c71c1a990 100644 --- a/configs/CPCI4052_defconfig +++ b/configs/CPCI4052_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_CPCI4052=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index 3257aaea789..4b9abea67b0 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_EMR1=4 CONFIG_USB0_VBUS_PIN="PB9" diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index c88411585f9..97bdcd64f20 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=480 CONFIG_MMC0_CD_PIN="PH1" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard" diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index 725652d6a73..f2c6fe7fd5e 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -4,7 +4,6 @@ CONFIG_MACH_SUN8I_A83T=y CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=15355 CONFIG_DRAM_ODT_EN=y -CONFIG_MMC0_CD_PIN="PF6" CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH11" diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig index 78e94ab7fa9..d53c6294831 100644 --- a/configs/Cyrus_P5020_defconfig +++ b/configs/Cyrus_P5020_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_GREPENV=y diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig index f03d738b527..a7c6307a83b 100644 --- a/configs/Cyrus_P5040_defconfig +++ b/configs/Cyrus_P5040_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_GREPENV=y diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index fef3685f2e7..77e496c25f1 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DRAM_EMR1=4 CONFIG_USB0_VBUS_PIN="PB09" CONFIG_USB0_VBUS_DET="PH5" diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index 9d8d3251e1b..94aab9dba8e 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino" diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig index 93e39b49430..36067000ef6 100644 --- a/configs/M52277EVB_defconfig +++ b/configs/M52277EVB_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M52277EVB=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="-> " CONFIG_CMD_SF=y CONFIG_CMD_SPI=y diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig index b63386d59a0..af463c3c7c2 100644 --- a/configs/M52277EVB_stmicro_defconfig +++ b/configs/M52277EVB_stmicro_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M52277EVB=y CONFIG_SYS_TEXT_BASE=0x43E00000 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT" +CONFIG_BOOTDELAY=3 CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_I2C=y diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index fc29e306acb..e758873c4d2 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M5253DEMO=y CONFIG_SYS_TEXT_BASE=0xFF800000 +CONFIG_BOOTDELAY=5 # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y diff --git a/configs/M5253EVBE_defconfig b/configs/M5253EVBE_defconfig index 15c22df7a56..17ded588876 100644 --- a/configs/M5253EVBE_defconfig +++ b/configs/M5253EVBE_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M5253EVBE=y CONFIG_SYS_TEXT_BASE=0xFFE00000 +CONFIG_BOOTDELAY=5 # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set CONFIG_CMD_CACHE=y diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index 585ea17d5d4..7638b18991b 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M5272C3=y CONFIG_SYS_TEXT_BASE=0xffe00000 +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index cd751181d1c..a7af3564baf 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M5275EVB=y CONFIG_SYS_TEXT_BASE=0xffe00000 +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index df12b3a8323..f415f7b5f4b 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M5282EVB=y CONFIG_SYS_TEXT_BASE=0xFFE00000 +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/MIP405T_defconfig b/configs/MIP405T_defconfig index 0d0c029d666..c9913ae3afa 100644 --- a/configs/MIP405T_defconfig +++ b/configs/MIP405T_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_MIP405=y CONFIG_SYS_EXTRA_OPTIONS="MIP405T" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/MIP405_defconfig b/configs/MIP405_defconfig index aa234993260..1d8e38ebc5e 100644 --- a/configs/MIP405_defconfig +++ b/configs/MIP405_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_MIP405=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 9e6f50b7199..4e25193cf64 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 978e23164bc..2fdffa9b439 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8313ERDB=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_GPIO=y diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index 35db54169c4..56538ccb942 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8313ERDB=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_GPIO=y diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index 63c6d7b2645..efabb9a1eb5 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_GPIO=y diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index a3d52940574..be0e2748673 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_GPIO=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index dfb41f0cee5..f2aef3332e1 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC8315ERDB=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index cf2f6557e82..5e5a2d0f988 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC8323ERDB=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index 0c85f409e41..72aacf31787 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index e9cf0c8d976..3e7390f84e4 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 92724311a6f..c65d3c94022 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index d8078847f54..5c95787e2a3 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index 8900665b5bf..4d7c52f054a 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 60561cfdd55..7ed79233b1d 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index fb7485cd90e..f1afcf853cf 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8349ITX=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> " CONFIG_CMD_I2C=y diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 65edb639256..5c9f7fc0766 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8349ITX=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="MPC8349E-mITX> " CONFIG_CMD_I2C=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index 358656e8e09..df08fe38df9 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8349ITX=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="MPC8349E-mITX> " CONFIG_CMD_I2C=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 0e09e77afe6..d8b5607093b 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC837XEMDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index f7ad159f0a5..c04c2560a80 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XEMDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 1b2c7870e8a..0d6e4b67911 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XERDB=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig index 40d1a3a2355..2ffc6474cf8 100644 --- a/configs/MPC8536DS_36BIT_defconfig +++ b/configs/MPC8536DS_36BIT_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8536DS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig index c6afe45adf1..5f4d51a6c70 100644 --- a/configs/MPC8536DS_SDCARD_defconfig +++ b/configs/MPC8536DS_SDCARD_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8536DS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig index eafa11c44ec..0fdc9de5e6c 100644 --- a/configs/MPC8536DS_SPIFLASH_defconfig +++ b/configs/MPC8536DS_SPIFLASH_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8536DS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig index 0ae81ef6182..13e06d655aa 100644 --- a/configs/MPC8536DS_defconfig +++ b/configs/MPC8536DS_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8536DS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/MPC8540ADS_defconfig b/configs/MPC8540ADS_defconfig index 401a86dbdfc..e3cb0d5e9ae 100644 --- a/configs/MPC8540ADS_defconfig +++ b/configs/MPC8540ADS_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8540ADS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_PING=y diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig index ddc3b5b8d33..1ea8800441b 100644 --- a/configs/MPC8541CDS_defconfig +++ b/configs/MPC8541CDS_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8541CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig index a340c8bb554..ae529d17255 100644 --- a/configs/MPC8541CDS_legacy_defconfig +++ b/configs/MPC8541CDS_legacy_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8541CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="LEGACY" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig index 06569e288b7..ecb05acbb62 100644 --- a/configs/MPC8544DS_defconfig +++ b/configs/MPC8544DS_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8544DS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index d038267d909..066eaf229b9 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8548CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index a42d991dbb8..ee400a38fdd 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8548CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 3a730f9af8c..b7334615f98 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8548CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="LEGACY" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig index 86db71c70a7..da42112fab4 100644 --- a/configs/MPC8555CDS_defconfig +++ b/configs/MPC8555CDS_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8555CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig index 485e9870a02..fb148912b9a 100644 --- a/configs/MPC8555CDS_legacy_defconfig +++ b/configs/MPC8555CDS_legacy_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8555CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="LEGACY" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y diff --git a/configs/MPC8560ADS_defconfig b/configs/MPC8560ADS_defconfig index 19407b347ca..67063c81da3 100644 --- a/configs/MPC8560ADS_defconfig +++ b/configs/MPC8560ADS_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8560ADS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_PING=y diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig index 5ec37124676..2e7dcebd07d 100644 --- a/configs/MPC8568MDS_defconfig +++ b/configs/MPC8568MDS_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8568MDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig index daacef75762..505a8536aa9 100644 --- a/configs/MPC8569MDS_ATM_defconfig +++ b/configs/MPC8569MDS_ATM_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8569MDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="ATM" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig index 26ab184b459..0f9cc2fb925 100644 --- a/configs/MPC8569MDS_defconfig +++ b/configs/MPC8569MDS_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8569MDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig index 1720d9e6fc1..8218ef688ff 100644 --- a/configs/MPC8572DS_36BIT_defconfig +++ b/configs/MPC8572DS_36BIT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig index 63cf745ce7a..6c65fbe7deb 100644 --- a/configs/MPC8572DS_defconfig +++ b/configs/MPC8572DS_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig index 6883249cb7e..10607e80dc8 100644 --- a/configs/MPC8610HPCD_defconfig +++ b/configs/MPC8610HPCD_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC86xx=y CONFIG_TARGET_MPC8610HPCD=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig index c85ddfe1c9c..b90e6ea359e 100644 --- a/configs/MPC8641HPCN_36BIT_defconfig +++ b/configs/MPC8641HPCN_36BIT_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8641HPCN=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PHYS_64BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig index d71369ece25..d8f74b31dcb 100644 --- a/configs/MPC8641HPCN_defconfig +++ b/configs/MPC8641HPCN_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC86xx=y CONFIG_TARGET_MPC8641HPCN=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index cef97946f95..d230a68c9f6 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index f076e30b557..64f2c74213f 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000" diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index 53e023a75fd..198fda95fea 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -5,7 +5,6 @@ CONFIG_DRAM_CLK=360 CONFIG_DRAM_ZQ=123 CONFIG_SYS_CLK_FREQ=1008000000 CONFIG_MMC0_CD_PIN="PH18" -# CONFIG_VIDEO is not set CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/MigoR_defconfig b/configs/MigoR_defconfig index 57b7db4d3b5..129403c34ab 100644 --- a/configs/MigoR_defconfig +++ b/configs/MigoR_defconfig @@ -1,5 +1,6 @@ CONFIG_SH=y CONFIG_TARGET_MIGOR=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index 53f9bfe9cb6..f96757e2637 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus" diff --git a/configs/MiniFAP_defconfig b/configs/MiniFAP_defconfig index bad6a39003b..39fdf6a93da 100644 --- a/configs/MiniFAP_defconfig +++ b/configs/MiniFAP_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="MINIFAP" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y diff --git a/configs/O2D300_defconfig b/configs/O2D300_defconfig index f7d7f00bf76..3b36d8fa34b 100644 --- a/configs/O2D300_defconfig +++ b/configs/O2D300_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_O2D300=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/O2DNT2_RAMBOOT_defconfig b/configs/O2DNT2_RAMBOOT_defconfig index 31e309fedbb..977da33c682 100644 --- a/configs/O2DNT2_RAMBOOT_defconfig +++ b/configs/O2DNT2_RAMBOOT_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_O2DNT2=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n" diff --git a/configs/O2DNT2_defconfig b/configs/O2DNT2_defconfig index eb65c22aead..32e475d5316 100644 --- a/configs/O2DNT2_defconfig +++ b/configs/O2DNT2_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_O2DNT2=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n" diff --git a/configs/O2D_defconfig b/configs/O2D_defconfig index 67a7757e7dc..22e83577bd7 100644 --- a/configs/O2D_defconfig +++ b/configs/O2D_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_O2D=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/O2I_defconfig b/configs/O2I_defconfig index 7a29872fa97..a1c2794c0d1 100644 --- a/configs/O2I_defconfig +++ b/configs/O2I_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_O2I=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/O2MNT_O2M110_defconfig b/configs/O2MNT_O2M110_defconfig index 4f35c2e8fce..f33496cfd1c 100644 --- a/configs/O2MNT_O2M110_defconfig +++ b/configs/O2MNT_O2M110_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_O2MNT=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M110\"" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/O2MNT_O2M112_defconfig b/configs/O2MNT_O2M112_defconfig index 77d18798dd9..04a8fdda4b6 100644 --- a/configs/O2MNT_O2M112_defconfig +++ b/configs/O2MNT_O2M112_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_O2MNT=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M112\"" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/O2MNT_O2M113_defconfig b/configs/O2MNT_O2M113_defconfig index 6d91a1153b8..2e4b8abe95d 100644 --- a/configs/O2MNT_O2M113_defconfig +++ b/configs/O2MNT_O2M113_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_O2MNT=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M113\"" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/O2MNT_defconfig b/configs/O2MNT_defconfig index e135f93b2d4..9176431e017 100644 --- a/configs/O2MNT_defconfig +++ b/configs/O2MNT_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_O2MNT=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/O3DNT_defconfig b/configs/O3DNT_defconfig index b6bc88e638e..55054ac757f 100644 --- a/configs/O3DNT_defconfig +++ b/configs/O3DNT_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_O3DNT=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig index af6a4be901d..5e05795cbb7 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 5ed93a169ac..5e12add6ceb 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig index 2c05f6e1812..b63475c634a 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 4dbff83c045..74168dabbd8 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index f421b224e8c..2e34a10a0a3 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig index f0a74fdba6e..d5bf9467c73 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 6bd7dcb6555..aa08a595c6d 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig index b8968a84573..a745bb94108 100644 --- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 551b9db1ea6..8ac7c115514 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig index 7d8ebfece15..808851a826b 100644 --- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 6fd23ac04b9..ca3ba080d3a 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 1f29b11e9ee..dff79c60c6d 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig index 6da92e415e3..800e7b9c230 100644 --- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index fa7cab84df5..e1be2ebba06 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig index 860bc6a6393..e8564f9f580 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 23d938bd30a..425344b5bbd 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig index 5bc446b585a..dce2a1a92eb 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 7b83294b1bb..883de6f423f 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 234645eef47..381caad7b4e 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig index 7adcca84e34..293a9455699 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index c455059c9aa..0c8ae441c9f 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig index 45f54f7a0da..880be23ad9b 100644 --- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 7d6de18ebe0..d6f4f58f1ff 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig index 629fbbb7da7..a8755533900 100644 --- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 8f44aee4799..3e966315f25 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 37ebca37631..5adfa4940d7 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig index 6d6edd1f4c4..be7f0e28f47 100644 --- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index d21afae47e9..f82850c8634 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig index a0e44718f87..bb278317762 100644 --- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig index d2095819f45..79a4282e04b 100644 --- a/configs/P1020MBG-PC_36BIT_defconfig +++ b/configs/P1020MBG-PC_36BIT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig index d07ed43aee6..9b6370d7943 100644 --- a/configs/P1020MBG-PC_SDCARD_defconfig +++ b/configs/P1020MBG-PC_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig index 0fe87d1c428..5c5eb5ed5a7 100644 --- a/configs/P1020MBG-PC_defconfig +++ b/configs/P1020MBG-PC_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020MBG" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 735c53f8cf5..1c98b5503f2 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 953552d68ae..e5bff617f30 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index ec94e061e5e..dda50fb590c 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 044e7393e16..b69370506a8 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 3bd72f07493..3d4a746e073 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index a9a659c6605..121ff7925aa 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index f01dbc3bb4a..9dde9c7d053 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 37e14da144c..8ee1fa46bf9 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 63faa06a460..a296fee4c6f 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 255b8e221a5..045216c9157 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 61a635ab77c..7ff3b741b17 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index f8e633aba84..32c504708aa 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig index d6775d913bc..6dfe1951976 100644 --- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig index 054e9fc76d9..98f928524a2 100644 --- a/configs/P1020UTM-PC_36BIT_defconfig +++ b/configs/P1020UTM-PC_36BIT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig index b0553ef3429..136e5ac820e 100644 --- a/configs/P1020UTM-PC_SDCARD_defconfig +++ b/configs/P1020UTM-PC_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig index 36f7366c5ef..42f28cdfb3a 100644 --- a/configs/P1020UTM-PC_defconfig +++ b/configs/P1020UTM-PC_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1020UTM" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig index b24f8ec995c..eeb232d7a25 100644 --- a/configs/P1021RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig index 8f618ae38e7..d2f83fa2b4e 100644 --- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig index 70e4d444192..09ba6eaecd0 100644 --- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig index e119befc39d..7652d29ad84 100644 --- a/configs/P1021RDB-PC_36BIT_defconfig +++ b/configs/P1021RDB-PC_36BIT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig index 772a3133b94..a49dfca4e0d 100644 --- a/configs/P1021RDB-PC_NAND_defconfig +++ b/configs/P1021RDB-PC_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig index 9206cc7b4a4..c2d23b82545 100644 --- a/configs/P1021RDB-PC_SDCARD_defconfig +++ b/configs/P1021RDB-PC_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig index 85c03aa92eb..facbf9efc70 100644 --- a/configs/P1021RDB-PC_SPIFLASH_defconfig +++ b/configs/P1021RDB-PC_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig index ae78a8e91dc..eebc69b7f63 100644 --- a/configs/P1021RDB-PC_defconfig +++ b/configs/P1021RDB-PC_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig index af98b8e57c7..352305d8df2 100644 --- a/configs/P1022DS_36BIT_NAND_defconfig +++ b/configs/P1022DS_36BIT_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig index 0ea0201a117..68a6c118389 100644 --- a/configs/P1022DS_36BIT_SDCARD_defconfig +++ b/configs/P1022DS_36BIT_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig index 40934494128..21300da4572 100644 --- a/configs/P1022DS_36BIT_SPIFLASH_defconfig +++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig index 24e86783095..c63abc3d6a0 100644 --- a/configs/P1022DS_36BIT_defconfig +++ b/configs/P1022DS_36BIT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig index cbc3d763910..6d90082236d 100644 --- a/configs/P1022DS_NAND_defconfig +++ b/configs/P1022DS_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig index 8c36f58b7f7..7643544694d 100644 --- a/configs/P1022DS_SDCARD_defconfig +++ b/configs/P1022DS_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig index 1c7b323229e..2e96cb2806a 100644 --- a/configs/P1022DS_SPIFLASH_defconfig +++ b/configs/P1022DS_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig index b5dee335e9e..679353e952a 100644 --- a/configs/P1022DS_defconfig +++ b/configs/P1022DS_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig index bcc0aede640..d3731a87d2a 100644 --- a/configs/P1024RDB_36BIT_defconfig +++ b/configs/P1024RDB_36BIT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig index dc747089a5c..2a53c57c121 100644 --- a/configs/P1024RDB_NAND_defconfig +++ b/configs/P1024RDB_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig index a59ddde3515..dc93a19d299 100644 --- a/configs/P1024RDB_SDCARD_defconfig +++ b/configs/P1024RDB_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig index 99935933913..b41e590b1cf 100644 --- a/configs/P1024RDB_SPIFLASH_defconfig +++ b/configs/P1024RDB_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig index 8f723c6ff27..5541bf98e18 100644 --- a/configs/P1024RDB_defconfig +++ b/configs/P1024RDB_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig index 5285f79adfe..98644861b5b 100644 --- a/configs/P1025RDB_36BIT_defconfig +++ b/configs/P1025RDB_36BIT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig index ec6038c5209..8a3b80497ac 100644 --- a/configs/P1025RDB_NAND_defconfig +++ b/configs/P1025RDB_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig index 6ba76fa69f0..eed18337cfb 100644 --- a/configs/P1025RDB_SDCARD_defconfig +++ b/configs/P1025RDB_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig index 86b9cd7d58d..89daf1cc884 100644 --- a/configs/P1025RDB_SPIFLASH_defconfig +++ b/configs/P1025RDB_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig index f7ce9b69de2..746e150b66a 100644 --- a/configs/P1025RDB_defconfig +++ b/configs/P1025RDB_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 21d98e3afab..2421a7371d5 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index ce42c822c70..fce023ba5bb 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index c8f86e2b587..a3162649cc9 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index a6a01e8fc8e..0bc2d1a2b5c 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 0f10e08bbcc..cf1ccbfe5e8 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 8649e520089..e8b6e2a3925 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 1764f2c01a0..bfbaea1b812 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index b9610e43899..82e7b4b2c2c 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index d4b1c557f0b..66f6ec4e3ef 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index a36e73193eb..59014580946 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig index 4d4051176d9..b7f3a0d4297 100644 --- a/configs/P2041RDB_SECURE_BOOT_defconfig +++ b/configs/P2041RDB_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index c2dbd98886c..7f07d2d9c69 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig index 3dbf5a31074..a767520644c 100644 --- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_GREPENV=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index aea98c63a4b..17e2ad5ee82 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig index d5b1c12add1..c2790b22d56 100644 --- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index dfe0e1754ea..1c863dee7c5 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index a8e21319a3e..028b9f077a8 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig index 13e2fed459c..d1b3f7001d2 100644 --- a/configs/P3041DS_SECURE_BOOT_defconfig +++ b/configs/P3041DS_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 901c373d403..acce0840a40 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig index f9285a8a693..d20defab5ee 100644 --- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_GREPENV=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index d648d975aa4..641f2635ab8 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index aaa97f74cc0..deba4696175 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig index 437e05a810a..68c910ee0fb 100644 --- a/configs/P4080DS_SECURE_BOOT_defconfig +++ b/configs/P4080DS_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index a3f0d853167..130e2f48482 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig index 7059c81aa41..b47fc08a4ae 100644 --- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_GREPENV=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index 752a6c63898..f9a7ed30156 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig index 2ecb0b864b4..ae9843c66e5 100644 --- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig index c26e72987fc..3edbee003d7 100644 --- a/configs/P5020DS_NAND_defconfig +++ b/configs/P5020DS_NAND_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig index acc617ece65..b7a2f1d5470 100644 --- a/configs/P5020DS_SDCARD_defconfig +++ b/configs/P5020DS_SDCARD_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig index 24d4f173661..9523a07ddc9 100644 --- a/configs/P5020DS_SECURE_BOOT_defconfig +++ b/configs/P5020DS_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig index 3e97ee0084d..93d92d312db 100644 --- a/configs/P5020DS_SPIFLASH_defconfig +++ b/configs/P5020DS_SPIFLASH_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig index f381326a582..b5906514f25 100644 --- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_GREPENV=y diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig index d7145aee5ac..8b8e5578214 100644 --- a/configs/P5020DS_defconfig +++ b/configs/P5020DS_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig index 0495c4de077..e45ed753f3e 100644 --- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index 9be5ff17486..73b2216c82e 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index 66751641fba..72923ca4e27 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig index 552d93a6451..21a7ba542f4 100644 --- a/configs/P5040DS_SECURE_BOOT_defconfig +++ b/configs/P5040DS_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 2caec57f126..0722667d00f 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index 07e67c893e2..9c3a2ce9d7d 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/PATI_defconfig b/configs/PATI_defconfig index ae957320e51..53fdfad6feb 100644 --- a/configs/PATI_defconfig +++ b/configs/PATI_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_5xx=y CONFIG_TARGET_PATI=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="pati=> " # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/PIP405_defconfig b/configs/PIP405_defconfig index fe887396da3..dee793b3e6c 100644 --- a/configs/PIP405_defconfig +++ b/configs/PIP405_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_PIP405=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/PLU405_defconfig b/configs/PLU405_defconfig index c1795a4ae5b..a0e84117051 100644 --- a/configs/PLU405_defconfig +++ b/configs/PLU405_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_PLU405=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/PMC405DE_defconfig b/configs/PMC405DE_defconfig index 8f60d87311b..cdb82d64486 100644 --- a/configs/PMC405DE_defconfig +++ b/configs/PMC405DE_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_PMC405DE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/PMC440_defconfig b/configs/PMC440_defconfig index 4d060ab6961..704cd36bce9 100644 --- a/configs/PMC440_defconfig +++ b/configs/PMC440_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_PMC440=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig index 9a916c96fad..32df4e58754 100644 --- a/configs/T1023RDB_NAND_defconfig +++ b/configs/T1023RDB_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_GREPENV=y diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig index 2c41d03d79e..069f5d36bcf 100644 --- a/configs/T1023RDB_SDCARD_defconfig +++ b/configs/T1023RDB_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_GREPENV=y diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig index e3cf48d835f..984e60b63af 100644 --- a/configs/T1023RDB_SECURE_BOOT_defconfig +++ b/configs/T1023RDB_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig index 5ce9ed991ed..109cade718f 100644 --- a/configs/T1023RDB_SPIFLASH_defconfig +++ b/configs/T1023RDB_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_GREPENV=y diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig index 44c9584655f..de0d50c241b 100644 --- a/configs/T1023RDB_defconfig +++ b/configs/T1023RDB_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig index 6c4505fcf7c..6253b052290 100644 --- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig index 0af7eab817b..71ff16606d1 100644 --- a/configs/T1024QDS_DDR4_defconfig +++ b/configs/T1024QDS_DDR4_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig index efdcbeb48c4..04204fb2b4e 100644 --- a/configs/T1024QDS_NAND_defconfig +++ b/configs/T1024QDS_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig index 12a03766fc9..80dd6df6e6b 100644 --- a/configs/T1024QDS_SDCARD_defconfig +++ b/configs/T1024QDS_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig index 84da5830ac4..21f7ed40a93 100644 --- a/configs/T1024QDS_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig index 03d009f4060..a8698537458 100644 --- a/configs/T1024QDS_SPIFLASH_defconfig +++ b/configs/T1024QDS_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig index a70963fbd33..c824674afa6 100644 --- a/configs/T1024QDS_defconfig +++ b/configs/T1024QDS_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index a012f3d80b7..ce0ba29f6cb 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index d7cce8b8a6f..21707f64a77 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig index ceae6cf1715..557897605db 100644 --- a/configs/T1024RDB_SECURE_BOOT_defconfig +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 1359aad17c8..6a9df4804de 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 7ffacd420c1..d54b83543de 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig index a07a59aed32..9295c61ca25 100644 --- a/configs/T1040D4RDB_NAND_defconfig +++ b/configs/T1040D4RDB_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig index e4c095e8d2d..de3aef0ea16 100644 --- a/configs/T1040D4RDB_SDCARD_defconfig +++ b/configs/T1040D4RDB_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig index a2c14953161..fe7b9d18e90 100644 --- a/configs/T1040D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig index 9a78aa9d77e..b762e1914c3 100644 --- a/configs/T1040D4RDB_SPIFLASH_defconfig +++ b/configs/T1040D4RDB_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig index f2415d9e352..4147f385aa8 100644 --- a/configs/T1040D4RDB_defconfig +++ b/configs/T1040D4RDB_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig index df9e295127d..11ff5f085ed 100644 --- a/configs/T1040QDS_DDR4_defconfig +++ b/configs/T1040QDS_DDR4_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig index 7f889c7ac0a..33c6772c8ce 100644 --- a/configs/T1040QDS_SECURE_BOOT_defconfig +++ b/configs/T1040QDS_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig index f93f0b9a1ef..fd512dbf9f2 100644 --- a/configs/T1040QDS_defconfig +++ b/configs/T1040QDS_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig index 023dc37d3d9..8f99f8fda85 100644 --- a/configs/T1040RDB_NAND_defconfig +++ b/configs/T1040RDB_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig index bacb060c20a..899339a70f6 100644 --- a/configs/T1040RDB_SDCARD_defconfig +++ b/configs/T1040RDB_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig index 9d6d9fb41ef..4e5682c5dc4 100644 --- a/configs/T1040RDB_SECURE_BOOT_defconfig +++ b/configs/T1040RDB_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig index b5a050cae1a..a20259556c0 100644 --- a/configs/T1040RDB_SPIFLASH_defconfig +++ b/configs/T1040RDB_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig index a50f1774870..e2a8321b5f7 100644 --- a/configs/T1040RDB_defconfig +++ b/configs/T1040RDB_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index f70d5ce27fb..17b6b83a96b 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 4f218130515..097bb8a9e02 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig index 07bdcf68009..fa0e2a63297 100644 --- a/configs/T1042D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index a49d32d987b..6dd0cdbb43e 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 23f83e67203..60fc267d2e5 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig index 1935dad2b58..106b2f05fd5 100644 --- a/configs/T1042RDB_PI_NAND_defconfig +++ b/configs/T1042RDB_PI_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig index f093e92b616..3dd11a5d288 100644 --- a/configs/T1042RDB_PI_SDCARD_defconfig +++ b/configs/T1042RDB_PI_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig index f7126e5856a..5af19870b3c 100644 --- a/configs/T1042RDB_PI_SPIFLASH_defconfig +++ b/configs/T1042RDB_PI_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig index f0aed08eb73..2c72833ee81 100644 --- a/configs/T1042RDB_PI_defconfig +++ b/configs/T1042RDB_PI_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig index 0057e22d7e4..c7777140a15 100644 --- a/configs/T1042RDB_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig index 8905b6c00c9..bb1bee7504f 100644 --- a/configs/T1042RDB_defconfig +++ b/configs/T1042RDB_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 2459eba3f7b..e4aec61e9dd 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index b937af4a83f..d314307bcfe 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 049819e4b77..5e5635807d0 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 86344776098..cf15e001d59 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 40c871e7c44..db6e7fb2a20 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_GREPENV=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 795a3f00282..d5f1de54a26 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index c6e07104d61..673655c1318 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 51caeeb60d9..32c0a571f85 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig index f4190af51b3..af64f230aa2 100644 --- a/configs/T2080RDB_SECURE_BOOT_defconfig +++ b/configs/T2080RDB_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 9d4821dafba..75a56d564a3 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig index 0a15e05f81d..b1cacf763d4 100644 --- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 955b394f9e1..1161f0820b1 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig index 0b0e1204e18..1e196a03b09 100644 --- a/configs/T2081QDS_NAND_defconfig +++ b/configs/T2081QDS_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig index bffca4001c4..85029cf4acf 100644 --- a/configs/T2081QDS_SDCARD_defconfig +++ b/configs/T2081QDS_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig index fc8f1f5035d..66350d0af79 100644 --- a/configs/T2081QDS_SPIFLASH_defconfig +++ b/configs/T2081QDS_SPIFLASH_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig index ed075eb390d..88702bccfec 100644 --- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_GREPENV=y diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig index 844fe106537..d8fadec534a 100644 --- a/configs/T2081QDS_defconfig +++ b/configs/T2081QDS_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig index 92b03913575..4e7dbe55fa4 100644 --- a/configs/T4160QDS_NAND_defconfig +++ b/configs/T4160QDS_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig index 2a30e11c2d6..d70417999f9 100644 --- a/configs/T4160QDS_SDCARD_defconfig +++ b/configs/T4160QDS_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig index 37aac2a7921..560fce8c851 100644 --- a/configs/T4160QDS_SECURE_BOOT_defconfig +++ b/configs/T4160QDS_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig index 3b13a343683..a9cd51cd64b 100644 --- a/configs/T4160QDS_defconfig +++ b/configs/T4160QDS_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig index 3523fe16db2..9adcc211838 100644 --- a/configs/T4160RDB_defconfig +++ b/configs/T4160RDB_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig index c2a16fd1f37..7ce7ff0da9b 100644 --- a/configs/T4240QDS_NAND_defconfig +++ b/configs/T4240QDS_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig index 3ec6c75c011..9fd17a9149b 100644 --- a/configs/T4240QDS_SDCARD_defconfig +++ b/configs/T4240QDS_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig index 18c8e676249..2d6b47f771c 100644 --- a/configs/T4240QDS_SECURE_BOOT_defconfig +++ b/configs/T4240QDS_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig index c590410997c..193d54c24d4 100644 --- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_GREPENV=y diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig index afb665dac81..4a241849d6c 100644 --- a/configs/T4240QDS_defconfig +++ b/configs/T4240QDS_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 85fd13b4e9e..27093ec3566 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 21e22be06ef..c14f9b8e6ce 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/TQM5200S_HIGHBOOT_defconfig b/configs/TQM5200S_HIGHBOOT_defconfig index 7adc71cc2bd..6a147034656 100644 --- a/configs/TQM5200S_HIGHBOOT_defconfig +++ b/configs/TQM5200S_HIGHBOOT_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y diff --git a/configs/TQM5200S_defconfig b/configs/TQM5200S_defconfig index f09895417ea..0d8f0969388 100644 --- a/configs/TQM5200S_defconfig +++ b/configs/TQM5200S_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y diff --git a/configs/TQM5200_B_HIGHBOOT_defconfig b/configs/TQM5200_B_HIGHBOOT_defconfig index 70eb3834f3a..9c310aa464f 100644 --- a/configs/TQM5200_B_HIGHBOOT_defconfig +++ b/configs/TQM5200_B_HIGHBOOT_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,SYS_TEXT_BASE=0xFFF00000" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y diff --git a/configs/TQM5200_B_defconfig b/configs/TQM5200_B_defconfig index 6734495f025..da88fcc8c34 100644 --- a/configs/TQM5200_B_defconfig +++ b/configs/TQM5200_B_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y diff --git a/configs/TQM5200_STK100_defconfig b/configs/TQM5200_STK100_defconfig index d0adb77b9d1..9926fd7a907 100644 --- a/configs/TQM5200_STK100_defconfig +++ b/configs/TQM5200_STK100_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="STK52XX_REV100" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y diff --git a/configs/TQM5200_defconfig b/configs/TQM5200_defconfig index 445636102ca..fe68631018f 100644 --- a/configs/TQM5200_defconfig +++ b/configs/TQM5200_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y diff --git a/configs/TQM823L_LCD_defconfig b/configs/TQM823L_LCD_defconfig index 9bf21f57424..38f511967c6 100644 --- a/configs/TQM823L_LCD_defconfig +++ b/configs/TQM823L_LCD_defconfig @@ -3,6 +3,7 @@ CONFIG_8xx=y CONFIG_TARGET_TQM823L=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="LCD,NEC_NL6448BC20" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/TQM823L_defconfig b/configs/TQM823L_defconfig index 9f3218b7836..3bc293410ac 100644 --- a/configs/TQM823L_defconfig +++ b/configs/TQM823L_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM823L=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/TQM823M_defconfig b/configs/TQM823M_defconfig index 9a0ba9d0df9..9d40a1ff6bf 100644 --- a/configs/TQM823M_defconfig +++ b/configs/TQM823M_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM823M=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index 00dd80d7461..b56d780bb46 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC83xx=y CONFIG_TARGET_TQM834X=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/TQM850L_defconfig b/configs/TQM850L_defconfig index 088ed6d22e9..8427f5872b6 100644 --- a/configs/TQM850L_defconfig +++ b/configs/TQM850L_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM850L=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/TQM850M_defconfig b/configs/TQM850M_defconfig index ab3c44b3b01..1c3f4240a82 100644 --- a/configs/TQM850M_defconfig +++ b/configs/TQM850M_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM850M=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/TQM855L_defconfig b/configs/TQM855L_defconfig index 6ece0683bc9..0234813995f 100644 --- a/configs/TQM855L_defconfig +++ b/configs/TQM855L_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM855L=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/TQM855M_defconfig b/configs/TQM855M_defconfig index 9940f96e5bd..15541e5cfad 100644 --- a/configs/TQM855M_defconfig +++ b/configs/TQM855M_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM855M=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/TQM860L_defconfig b/configs/TQM860L_defconfig index 4aec4ff284f..becd4e1e2f8 100644 --- a/configs/TQM860L_defconfig +++ b/configs/TQM860L_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM860L=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/TQM860M_defconfig b/configs/TQM860M_defconfig index 12b090aef9f..3b27e7f89b8 100644 --- a/configs/TQM860M_defconfig +++ b/configs/TQM860M_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM860M=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/TQM862L_defconfig b/configs/TQM862L_defconfig index 41737a39f82..36e2433713f 100644 --- a/configs/TQM862L_defconfig +++ b/configs/TQM862L_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM862L=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/TQM862M_defconfig b/configs/TQM862M_defconfig index 642dd023cba..84d2cb2b963 100644 --- a/configs/TQM862M_defconfig +++ b/configs/TQM862M_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM862M=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/TQM866M_defconfig b/configs/TQM866M_defconfig index 3d0bf8c9e7d..ddde240b4c0 100644 --- a/configs/TQM866M_defconfig +++ b/configs/TQM866M_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM866M=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/TQM885D_defconfig b/configs/TQM885D_defconfig index 2238cdd752a..92b34f646b4 100644 --- a/configs/TQM885D_defconfig +++ b/configs/TQM885D_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM885D=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y diff --git a/configs/TTTech_defconfig b/configs/TTTech_defconfig index df4efa40c41..e5458480d0c 100644 --- a/configs/TTTech_defconfig +++ b/configs/TTTech_defconfig @@ -3,6 +3,7 @@ CONFIG_8xx=y CONFIG_TARGET_TQM823L=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig index 8d2f2e6ef3b..ae8feda7010 100644 --- a/configs/TWR-P1025_defconfig +++ b/configs/TWR-P1025_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/VCMA9_defconfig b/configs/VCMA9_defconfig index 4c2df57eeae..550e6b8431b 100644 --- a/configs/VCMA9_defconfig +++ b/configs/VCMA9_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_VCMA9=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="VCMA9 # " CONFIG_CMD_I2C=y diff --git a/configs/VOM405_defconfig b/configs/VOM405_defconfig index 8fb023a863f..800731b18e0 100644 --- a/configs/VOM405_defconfig +++ b/configs/VOM405_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_VOM405=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=3 CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/a3m071_defconfig b/configs/a3m071_defconfig index 97e4fc5e227..c62018369f5 100644 --- a/configs/a3m071_defconfig +++ b/configs/a3m071_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_A3M071=y CONFIG_SPL=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_LOOPW=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/a4m2k_defconfig b/configs/a4m2k_defconfig index fc344c5caaf..61f7da7e7fc 100644 --- a/configs/a4m2k_defconfig +++ b/configs/a4m2k_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="A4M2K" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_LOOPW=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/acadia_defconfig b/configs/acadia_defconfig index 31889fa7594..24d802eb278 100644 --- a/configs/acadia_defconfig +++ b/configs/acadia_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_ACADIA=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig index 6daefcc5477..0def407446b 100644 --- a/configs/adp-ag101p_defconfig +++ b/configs/adp-ag101p_defconfig @@ -1,5 +1,6 @@ CONFIG_NDS32=y CONFIG_TARGET_ADP_AG101P=y +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="NDS32 # " CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/alt_defconfig b/configs/alt_defconfig index bfa243fb242..661d5445456 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_RMOBILE=y CONFIG_TARGET_ALT=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 696024c451f..3a1e5a47da8 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -4,7 +4,9 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" CONFIG_SPL=y CONFIG_SPL_STACK_R=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="NAND" +CONFIG_SPL_LOAD_FIT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set @@ -27,6 +29,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2" CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y @@ -42,10 +45,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 -CONFIG_OF_LIBFDT=y -CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" CONFIG_RSA=y -CONFIG_FIT=y CONFIG_SPL_OF_LIBFDT=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2" diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig index 76a004e8a8a..f2306716c3b 100644 --- a/configs/am335x_evm_nor_defconfig +++ b/configs/am335x_evm_nor_defconfig @@ -38,4 +38,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 CONFIG_OF_LIBFDT=y -CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig index 99fc5559781..3fbc07b66b5 100644 --- a/configs/am335x_evm_norboot_defconfig +++ b/configs/am335x_evm_norboot_defconfig @@ -35,4 +35,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 CONFIG_OF_LIBFDT=y -CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index d5aa3a29cea..65d88d894ca 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -38,4 +38,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 CONFIG_OF_LIBFDT=y -CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig index cba5e84741c..eee5e9b8c33 100644 --- a/configs/am335x_evm_usbspl_defconfig +++ b/configs/am335x_evm_usbspl_defconfig @@ -38,4 +38,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 CONFIG_OF_LIBFDT=y -CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 3cd40e9d840..c227ef4725b 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -25,4 +25,3 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y -CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig index a8b84655367..6d1dcde1bec 100644 --- a/configs/am3517_crane_defconfig +++ b/configs/am3517_crane_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_AM3517_CRANE=y CONFIG_SPL=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AM3517_CRANE # " # CONFIG_CMD_IMI is not set diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index d400c35c722..b4aa3c63cd0 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_AM3517_EVM=y CONFIG_SPL=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="NAND" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AM3517_EVM # " CONFIG_CMD_BOOTZ=y diff --git a/configs/am437x_hs_evm_defconfig b/configs/am437x_hs_evm_defconfig index 3cd39eb65d4..95b28fb9c2b 100644 --- a/configs/am437x_hs_evm_defconfig +++ b/configs/am437x_hs_evm_defconfig @@ -2,13 +2,12 @@ CONFIG_ARM=y CONFIG_AM43XX=y CONFIG_TI_SECURE_DEVICE=y CONFIG_TARGET_AM43XX_EVM=y +CONFIG_ISW_ENTRY_ADDR=0x40302ae0 CONFIG_DM_SERIAL=y CONFIG_DM_GPIO=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -# Device tree file can be same on HS evm CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" CONFIG_SPL=y -CONFIG_ISW_ENTRY_ADDR=0x40302ae0 CONFIG_SPL_STACK_R=y CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1" CONFIG_HUSH_PARSER=y diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig index 3b958d79b83..9cdae19b993 100644 --- a/configs/am43xx_evm_ethboot_defconfig +++ b/configs/am43xx_evm_ethboot_defconfig @@ -41,4 +41,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0403 CONFIG_G_DNL_PRODUCT_NUM=0xbd00 CONFIG_OF_LIBFDT=y -CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL" diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index 52643325513..7b345adba9c 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -41,4 +41,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0403 CONFIG_G_DNL_PRODUCT_NUM=0xbd00 CONFIG_OF_LIBFDT=y -CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL" diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 34c875e5e84..6b53eba2091 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -1,14 +1,16 @@ CONFIG_ARM=y CONFIG_AM43XX=y CONFIG_TARGET_AM43XX_EVM=y +CONFIG_ISW_ENTRY_ADDR=0x40300350 CONFIG_DM_SERIAL=y CONFIG_DM_GPIO=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" CONFIG_SPL=y -CONFIG_ISW_ENTRY_ADDR=0x40300350 CONFIG_SPL_STACK_R=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT" +CONFIG_SPL_LOAD_FIT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set @@ -31,6 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" CONFIG_DM=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y @@ -51,9 +54,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0403 CONFIG_G_DNL_PRODUCT_NUM=0xbd00 -CONFIG_OF_LIBFDT=y -CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL" -CONFIG_FIT=y CONFIG_SPL_OF_LIBFDT=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 6743b846772..b63ff89da20 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -7,9 +7,9 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15" CONFIG_SPL=y CONFIG_SPL_STACK_R=y +CONFIG_OF_BOARD_SETUP=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y -CONFIG_OF_BOARD_SETUP=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index c109939fdac..aa459a1beda 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -8,9 +8,9 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15" CONFIG_SPL=y CONFIG_SPL_STACK_R=y +CONFIG_OF_BOARD_SETUP=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y -CONFIG_OF_BOARD_SETUP=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig index 91fa7346915..fbd63e97a89 100644 --- a/configs/ap121_defconfig +++ b/configs/ap121_defconfig @@ -5,6 +5,7 @@ CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_ARCH_ATH79=y CONFIG_DEFAULT_DEVICE_TREE="ap121" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="ap121 # " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set @@ -19,13 +20,9 @@ CONFIG_SYS_PROMPT="ap121 # " CONFIG_CMD_SF=y CONFIG_CMD_SPI=y # CONFIG_CMD_FPGA is not set -CONFIG_CMD_NET=y -CONFIG_CMD_NFS=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_DM_ETH=y -CONFIG_AG7XXX=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ATMEL=y @@ -38,6 +35,8 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_AG7XXX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_AR933X_PINCTRL=y @@ -48,5 +47,3 @@ CONFIG_DEBUG_UART_CLOCK=25000000 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_AR933X_UART=y CONFIG_ATH79_SPI=y -CONFIG_USE_PRIVATE_LIBGCC=y -CONFIG_OF_LIBFDT=y diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig index 1aa6e5d7abd..15fe36fca45 100644 --- a/configs/ap143_defconfig +++ b/configs/ap143_defconfig @@ -6,6 +6,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_ARCH_ATH79=y CONFIG_TARGET_AP143=y CONFIG_DEFAULT_DEVICE_TREE="ap143" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="ap143 # " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set @@ -43,5 +44,3 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_NS16550=y CONFIG_ATH79_SPI=y -CONFIG_USE_PRIVATE_LIBGCC=y -CONFIG_OF_LIBFDT=y diff --git a/configs/ap325rxa_defconfig b/configs/ap325rxa_defconfig index 51920329c37..51a48de877d 100644 --- a/configs/ap325rxa_defconfig +++ b/configs/ap325rxa_defconfig @@ -1,5 +1,6 @@ CONFIG_SH=y CONFIG_TARGET_AP325RXA=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/ap_sh4a_4a_defconfig b/configs/ap_sh4a_4a_defconfig index 77a0aa5120b..73e6f04a315 100644 --- a/configs/ap_sh4a_4a_defconfig +++ b/configs/ap_sh4a_4a_defconfig @@ -1,5 +1,6 @@ CONFIG_SH=y CONFIG_TARGET_AP_SH4A_4A=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index 40a65d21e63..17e8595bb26 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -38,4 +38,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="NVIDIA" CONFIG_G_DNL_VENDOR_NUM=0x0955 CONFIG_G_DNL_PRODUCT_NUM=0x701a -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig index 88912e50af1..a175274b24d 100644 --- a/configs/apf27_defconfig +++ b/configs/apf27_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_APF27=y CONFIG_SPL=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="BIOS> " # CONFIG_CMD_IMLS is not set diff --git a/configs/arcangel4-be_defconfig b/configs/arcangel4-be_defconfig index 4c6fcb02e21..c0c2e4be90b 100644 --- a/configs/arcangel4-be_defconfig +++ b/configs/arcangel4-be_defconfig @@ -5,6 +5,7 @@ CONFIG_DM_SERIAL=y CONFIG_SYS_CLK_FREQ=70000000 CONFIG_SYS_TEXT_BASE=0x81000000 CONFIG_DEFAULT_DEVICE_TREE="arcangel4" +CONFIG_BOOTDELAY=3 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/arcangel4_defconfig b/configs/arcangel4_defconfig index 2157e0cc334..efa55d0e99c 100644 --- a/configs/arcangel4_defconfig +++ b/configs/arcangel4_defconfig @@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y CONFIG_SYS_CLK_FREQ=70000000 CONFIG_SYS_TEXT_BASE=0x81000000 CONFIG_DEFAULT_DEVICE_TREE="arcangel4" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="arcangel4# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/arches_defconfig b/configs/arches_defconfig index e05a64c01e6..d97715b4b5d 100644 --- a/configs/arches_defconfig +++ b/configs/arches_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_CANYONLANDS=y CONFIG_ARCHES=y CONFIG_DEFAULT_DEVICE_TREE="arches" CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/aria_defconfig b/configs/aria_defconfig index fb3257b3ae7..14919e59fe8 100644 --- a/configs/aria_defconfig +++ b/configs/aria_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC512X=y CONFIG_TARGET_ARIA=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig index 1224da490a1..9bae3c3efac 100644 --- a/configs/armadillo-800eva_defconfig +++ b/configs/armadillo-800eva_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_RMOBILE=y CONFIG_TARGET_ARMADILLO_800EVA=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig index 4f5df351fcc..9ac66570cd3 100644 --- a/configs/aspenite_defconfig +++ b/configs/aspenite_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_ASPENITE=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y diff --git a/configs/at91rm9200ek_defconfig b/configs/at91rm9200ek_defconfig index bea73a5a453..f1303b3ae0a 100644 --- a/configs/at91rm9200ek_defconfig +++ b/configs/at91rm9200ek_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91RM9200EK=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig index 80125311754..8b00ee266ec 100644 --- a/configs/at91rm9200ek_ram_defconfig +++ b/configs/at91rm9200ek_ram_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91RM9200EK=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig index d8ec7f1c994..5a369bb0c1a 100644 --- a/configs/at91sam9260ek_dataflash_cs0_defconfig +++ b/configs/at91sam9260ek_dataflash_cs0_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig index eb17f913328..b465395914f 100644 --- a/configs/at91sam9260ek_dataflash_cs1_defconfig +++ b/configs/at91sam9260ek_dataflash_cs1_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig index 26ffd97e64a..a30c40bfe1a 100644 --- a/configs/at91sam9260ek_nandflash_defconfig +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig index 4e8dfa1943a..4406e58bb5a 100644 --- a/configs/at91sam9261ek_dataflash_cs0_defconfig +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig index c5684f2e34f..2d599156e11 100644 --- a/configs/at91sam9261ek_dataflash_cs3_defconfig +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index 0fba31434b3..45bc42769d4 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index b09395f6ff7..c94e7a43123 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index b09395f6ff7..c94e7a43123 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index dd46a686c6a..05c3f3dd9e7 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index 25b9a1710cf..eb20eba841b 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index 3cdce9b80fb..aed72da76bd 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig index 9ff65b514d9..f829a18306a 100644 --- a/configs/at91sam9g10ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig index 76c3b153617..a4b9719d9c2 100644 --- a/configs/at91sam9g10ek_dataflash_cs3_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig index 7438b86d1f5..199b5bbb1bd 100644 --- a/configs/at91sam9g10ek_nandflash_defconfig +++ b/configs/at91sam9g10ek_nandflash_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig index 0cded82d60b..bb176a095d7 100644 --- a/configs/at91sam9g20ek_2mmc_defconfig +++ b/configs/at91sam9g20ek_2mmc_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig index ddfce140aaf..7287860c635 100644 --- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig index 8ce99ee1101..ffc3a95312d 100644 --- a/configs/at91sam9g20ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig index 9ed2b84a706..9069f309699 100644 --- a/configs/at91sam9g20ek_dataflash_cs1_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig index f8f6afba2fe..eaaa6ae13be 100644 --- a/configs/at91sam9g20ek_nandflash_defconfig +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index c931af2b5b8..5452afd85c6 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9M10G45EK=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index 4aeca480d0c..011fdadc86a 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9M10G45EK=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index 2c4a81ab8e8..e61f3b90769 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9N12EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index 726d8114f97..62efd6ea913 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9N12EK=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index d0cff221986..6a54f033e67 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9N12EK=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig index dda3edfbee7..69be1d20d6b 100644 --- a/configs/at91sam9rlek_dataflash_defconfig +++ b/configs/at91sam9rlek_dataflash_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig index c300438920b..c49bf18192a 100644 --- a/configs/at91sam9rlek_mmc_defconfig +++ b/configs/at91sam9rlek_mmc_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig index 6b033fb96e1..142122ed094 100644 --- a/configs/at91sam9rlek_nandflash_defconfig +++ b/configs/at91sam9rlek_nandflash_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index 56aa2a00802..85ed41c8636 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index db501c5879a..cecd41651b8 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index 7f0b1a42bc9..002c833cecb 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index f7a4d16b6b8..cefe859cfaa 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig index 0ded2ab414b..77c65b25507 100644 --- a/configs/at91sam9xeek_dataflash_cs0_defconfig +++ b/configs/at91sam9xeek_dataflash_cs0_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig index 7995419ef66..9eaf146d8e4 100644 --- a/configs/at91sam9xeek_dataflash_cs1_defconfig +++ b/configs/at91sam9xeek_dataflash_cs1_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig index c859cb6e7fe..b17b9a5a016 100644 --- a/configs/at91sam9xeek_nandflash_defconfig +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index ba43e3501b6..0e0eadf6849 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_TAURUS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM" +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 07a6a1855e7..10e802d6553 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y CONFIG_SYS_CLK_FREQ=750000000 CONFIG_SYS_TEXT_BASE=0x81000000 CONFIG_DEFAULT_DEVICE_TREE="axs10x" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 01a51432ace..96a3de63c86 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y CONFIG_SYS_CLK_FREQ=50000000 CONFIG_SYS_TEXT_BASE=0x81000000 CONFIG_DEFAULT_DEVICE_TREE="axs10x" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index 1cfb380ce86..6da4b694a28 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=384 CONFIG_DRAM_EMR1=4 CONFIG_USB0_VBUS_PIN="PB9" diff --git a/configs/bamboo_defconfig b/configs/bamboo_defconfig index b0f6bb34e24..e1f1f3d582e 100644 --- a/configs/bamboo_defconfig +++ b/configs/bamboo_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_BAMBOO=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig index 4404f321536..71a52a12adf 100644 --- a/configs/bcm28155_ap_defconfig +++ b/configs/bcm28155_ap_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y CONFIG_TARGET_BCM28155_AP=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -22,4 +23,3 @@ CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation" CONFIG_G_DNL_VENDOR_NUM=0x18d1 CONFIG_G_DNL_PRODUCT_NUM=0x0d02 CONFIG_OF_LIBFDT=y -CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig index 60eb3281b65..97fe622f912 100644 --- a/configs/bcm28155_w1d_defconfig +++ b/configs/bcm28155_w1d_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y CONFIG_TARGET_BCM28155_AP=y CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC" CONFIG_HUSH_PARSER=y @@ -22,4 +23,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation" CONFIG_G_DNL_VENDOR_NUM=0x18d1 CONFIG_G_DNL_PRODUCT_NUM=0x0d02 -CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig index b9323c23386..8557c02d4e9 100644 --- a/configs/beaver_defconfig +++ b/configs/beaver_defconfig @@ -44,4 +44,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="NVIDIA" CONFIG_G_DNL_VENDOR_NUM=0x0955 CONFIG_G_DNL_PRODUCT_NUM=0x701a -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/bf525-ucr2_defconfig b/configs/bf525-ucr2_defconfig index 84f229fc141..68d2f48b451 100644 --- a/configs/bf525-ucr2_defconfig +++ b/configs/bf525-ucr2_defconfig @@ -1,5 +1,6 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF525_UCR2=y +CONFIG_BOOTDELAY=5 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y diff --git a/configs/bf537-minotaur_defconfig b/configs/bf537-minotaur_defconfig index 7c17cbb2ac9..fea8c3240f2 100644 --- a/configs/bf537-minotaur_defconfig +++ b/configs/bf537-minotaur_defconfig @@ -1,5 +1,6 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF537_MINOTAUR=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="minotaur> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/bf537-srv1_defconfig b/configs/bf537-srv1_defconfig index f8288d9d199..dc88c44fa56 100644 --- a/configs/bf537-srv1_defconfig +++ b/configs/bf537-srv1_defconfig @@ -1,5 +1,6 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF537_SRV1=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="srv1> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig index 709dfab9997..b3a13c63e6d 100644 --- a/configs/bg0900_defconfig +++ b/configs/bg0900_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_BG0900=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig index bb5db5cb3da..44ed67157f8 100644 --- a/configs/birdland_bav335a_defconfig +++ b/configs/birdland_bav335a_defconfig @@ -38,4 +38,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 CONFIG_OF_LIBFDT=y -CONFIG_SPL_NET_VCI_STRING="BAV335x U-Boot SPL" diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig index 39cc2220ecf..861bdcf4e2a 100644 --- a/configs/birdland_bav335b_defconfig +++ b/configs/birdland_bav335b_defconfig @@ -38,4 +38,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 CONFIG_OF_LIBFDT=y -CONFIG_SPL_NET_VCI_STRING="BAV335x U-Boot SPL" diff --git a/configs/blackstamp_defconfig b/configs/blackstamp_defconfig index 679aee167c3..7aa5a52f9b4 100644 --- a/configs/blackstamp_defconfig +++ b/configs/blackstamp_defconfig @@ -1,5 +1,6 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BLACKSTAMP=y +CONFIG_BOOTDELAY=5 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y diff --git a/configs/blackvme_defconfig b/configs/blackvme_defconfig index 808cc3de0f7..7c3eb9dc6b1 100644 --- a/configs/blackvme_defconfig +++ b/configs/blackvme_defconfig @@ -1,5 +1,6 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BLACKVME=y +CONFIG_BOOTDELAY=5 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y diff --git a/configs/bubinga_defconfig b/configs/bubinga_defconfig index d570d41e237..9bfe8285937 100644 --- a/configs/bubinga_defconfig +++ b/configs/bubinga_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_BUBINGA=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 2eefd15ca6d..c2e454a6580 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_VME8349=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="CADDY2" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/cam5200_defconfig b/configs/cam5200_defconfig index 722458883c2..f2da039223a 100644 --- a/configs/cam5200_defconfig +++ b/configs/cam5200_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y diff --git a/configs/cam5200_niosflash_defconfig b/configs/cam5200_niosflash_defconfig index 00d80454851..d04ac552a41 100644 --- a/configs/cam5200_niosflash_defconfig +++ b/configs/cam5200_niosflash_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y diff --git a/configs/canmb_defconfig b/configs/canmb_defconfig index 8d3b4764de1..f1e3265ec58 100644 --- a/configs/canmb_defconfig +++ b/configs/canmb_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_CANMB=y +CONFIG_BOOTDELAY=5 CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig index aac031b6f4d..fe9fbd041f9 100644 --- a/configs/canyonlands_defconfig +++ b/configs/canyonlands_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_CANYONLANDS=y CONFIG_CANYONLANDS=y CONFIG_DEFAULT_DEVICE_TREE="canyonlands" CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig index 979b6934ac0..ee8e7939264 100644 --- a/configs/cardhu_defconfig +++ b/configs/cardhu_defconfig @@ -36,4 +36,3 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA20_SLINK=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/charon_defconfig b/configs/charon_defconfig index ea50729efd6..ae9b62a711f 100644 --- a/configs/charon_defconfig +++ b/configs/charon_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_CHARON=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index d5bc5153b1b..6bebcee882d 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -73,7 +73,6 @@ CONFIG_ROCKCHIP_SPI=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y -CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index 75ea200b279..3bf538891b2 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -3,8 +3,9 @@ CONFIG_ARCH_MVEBU=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_CLEARFOG=y CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog" -CONFIG_HUSH_PARSER=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/cm5200_defconfig b/configs/cm5200_defconfig index c7df40022af..2a67b43ce87 100644 --- a/configs/cm5200_defconfig +++ b/configs/cm5200_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_CM5200=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig index 72283a61d40..bbb76a5c610 100644 --- a/configs/cm_t3517_defconfig +++ b/configs/cm_t3517_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_CM_T3517=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CM-T3517 # " CONFIG_CMD_BOOTZ=y diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig index 9a7b2057ccd..110e002d959 100644 --- a/configs/cm_t35_defconfig +++ b/configs/cm_t35_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_CM_T35=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CM-T3x # " CONFIG_CMD_BOOTZ=y diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig index bcab16bb058..4f2425b194e 100644 --- a/configs/cm_t54_defconfig +++ b/configs/cm_t54_defconfig @@ -3,6 +3,7 @@ CONFIG_OMAP54XX=y CONFIG_TARGET_CM_T54=y CONFIG_SPL=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CM-T54 # " CONFIG_CMD_BOOTZ=y diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig index 3cb69ac2055..400fca0f21c 100644 --- a/configs/cobra5272_defconfig +++ b/configs/cobra5272_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_COBRA5272=y CONFIG_SYS_TEXT_BASE=0xffe00000 +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="COBRA > " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index a3b2a3c862f..a0c40fecd14 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -44,4 +44,3 @@ CONFIG_G_DNL_VENDOR_NUM=0x0955 CONFIG_G_DNL_PRODUCT_NUM=0x701a CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index c920b396aa3..c7f6982f121 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -36,4 +36,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="NVIDIA" CONFIG_G_DNL_VENDOR_NUM=0x0955 CONFIG_G_DNL_PRODUCT_NUM=0x701a -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig index 7cc9a6ed68b..aff63280ca9 100644 --- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig +++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD,DEVELOP" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig index ee7739a57e4..74b67f71797 100644 --- a/configs/controlcenterd_36BIT_SDCARD_defconfig +++ b/configs/controlcenterd_36BIT_SDCARD_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index 37488dd4568..2efffb59851 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_CORVUS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index 0b77b1bdc0a..8282e25d9a4 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NET2BIG_V2=y CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="d2v2> " # CONFIG_CMD_IMLS is not set diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig index 8fd51ad5466..69839df7d21 100644 --- a/configs/da850_am18xxevm_defconfig +++ b/configs/da850_am18xxevm_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_DA850EVM=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 866d1877265..0e281a5e672 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_DA850EVM=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " # CONFIG_CMD_IMLS is not set diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 0bb2d37ac9a..9c5428db6ab 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_DA850EVM=y CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_ASKENV=y diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index 75eaad87757..980e153ce33 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -42,4 +42,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="NVIDIA" CONFIG_G_DNL_VENDOR_NUM=0x0955 CONFIG_G_DNL_PRODUCT_NUM=0x701a -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index e9ba1ef70ff..f06f27f9c53 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_DB_88F6720=y CONFIG_DEFAULT_DEVICE_TREE="armada-375-db" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index 7ad3bb66b1c..123e7fccd79 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_DB_88F6820_GP=y CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp" CONFIG_SPL=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 44f64fda640..f2c4a9ee6ad 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_DB_MV784MP_GP=y CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig index c3fa26faa42..996e2f78a52 100644 --- a/configs/dbau1000_defconfig +++ b/configs/dbau1000_defconfig @@ -12,4 +12,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # " # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig index 5e2c9bd1253..2b3ccd8915d 100644 --- a/configs/dbau1100_defconfig +++ b/configs/dbau1100_defconfig @@ -12,4 +12,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # " # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig index 10fe8aa37fa..7459c6342f4 100644 --- a/configs/dbau1500_defconfig +++ b/configs/dbau1500_defconfig @@ -12,4 +12,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # " # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/dbau1550_defconfig b/configs/dbau1550_defconfig index 7f1bdf41009..964d8a8eabe 100644 --- a/configs/dbau1550_defconfig +++ b/configs/dbau1550_defconfig @@ -9,4 +9,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # " # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/dbau1550_el_defconfig b/configs/dbau1550_el_defconfig index 6cd01614d54..dfe0102ffea 100644 --- a/configs/dbau1550_el_defconfig +++ b/configs/dbau1550_el_defconfig @@ -10,4 +10,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # " # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/devconcenter_defconfig b/configs/devconcenter_defconfig index 5449cff7101..bf7f545079a 100644 --- a/configs/devconcenter_defconfig +++ b/configs/devconcenter_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_INTIP=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig index 1ebfd23e4d4..e22461d480d 100644 --- a/configs/dlvision-10g_defconfig +++ b/configs/dlvision-10g_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_DLVISION_10G=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/dlvision_defconfig b/configs/dlvision_defconfig index 7b28d1d0bc2..fba36119037 100644 --- a/configs/dlvision_defconfig +++ b/configs/dlvision_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_DLVISION=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set CONFIG_CMD_ASKENV=y diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index a3d053d3f08..e997f6d0fb6 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_DNS325=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index 6ae447c9628..2d997960856 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_DOCKSTAR=y +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="DockStar> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 756af63c1fa..1237a732710 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -9,9 +9,11 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" CONFIG_SPL=y CONFIG_SPL_STACK_R=y +CONFIG_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SPL_LOAD_FIT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y -CONFIG_OF_BOARD_SETUP=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set @@ -32,6 +34,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_OF_LIST="dra7-evm dra72-evm" CONFIG_DM=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y @@ -53,7 +56,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 -CONFIG_FIT=y CONFIG_SPL_OF_LIBFDT=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_OF_LIST="dra7-evm dra72-evm" diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 6933ab5cc6f..07249166159 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_OMAP54XX=y -CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TI_SECURE_DEVICE=y CONFIG_TARGET_DRA7XX_EVM=y CONFIG_DM_SERIAL=y CONFIG_DM_SPI=y @@ -11,9 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" CONFIG_SPL=y CONFIG_SPL_STACK_R=y +CONFIG_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SPL_LOAD_FIT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y -CONFIG_OF_BOARD_SETUP=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set @@ -34,6 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_OF_LIST="dra7-evm dra72-evm" CONFIG_DM=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y @@ -55,7 +58,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 -CONFIG_FIT=y CONFIG_SPL_OF_LIBFDT=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_OF_LIST="dra7-evm dra72-evm" diff --git a/configs/draco_defconfig b/configs/draco_defconfig index 0a437ed16bb..d17e42f3e9f 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_DRACO=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index d293e3034b7..8f745f8b3b0 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_DREAMPLUG=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index 4d3cb344051..a21473255cf 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_DS414=y CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414" CONFIG_SPL=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig index f8155b2176b..ba50ce05159 100644 --- a/configs/dserve_dsrv9703c_defconfig +++ b/configs/dserve_dsrv9703c_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_MMC0_CD_PIN="PH1" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig index d6e51f80b09..57df04fb412 100644 --- a/configs/ea20_defconfig +++ b/configs/ea20_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_EA20=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ea20 > " # CONFIG_CMD_IMLS is not set diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index 55d5552354d..bf9177b3514 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_EB_CPU5282=y CONFIG_SYS_TEXT_BASE=0xFF000000 CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400" +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="\nEB+CPU5282> " # CONFIG_CMD_LOADB is not set CONFIG_CMD_I2C=y diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index e204ba266e1..4f6de89214c 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_EB_CPU5282=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418" +CONFIG_BOOTDELAY=5 # CONFIG_CMD_LOADB is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig index 467a0a14f31..b81ad58a15e 100644 --- a/configs/eco5pk_defconfig +++ b/configs/eco5pk_defconfig @@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y CONFIG_TARGET_ECO5PK=y CONFIG_SPL=y CONFIG_FIT=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ECO5-PK # " # CONFIG_CMD_IMLS is not set diff --git a/configs/ecovec_defconfig b/configs/ecovec_defconfig index 0066c7d9f49..a23f52a36ee 100644 --- a/configs/ecovec_defconfig +++ b/configs/ecovec_defconfig @@ -1,5 +1,6 @@ CONFIG_SH=y CONFIG_TARGET_ECOVEC=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig index fa7c1b5113e..e57dfdaa74b 100644 --- a/configs/edminiv2_defconfig +++ b/configs/edminiv2_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ORION5X=y CONFIG_TARGET_EDMINIV2=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="EDMiniV2> " CONFIG_CMD_I2C=y diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig index 0fe2759607b..8d0bacef522 100644 --- a/configs/espresso7420_defconfig +++ b/configs/espresso7420_defconfig @@ -1,9 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_ARCH_EXYNOS7=y -CONFIG_TARGET_ESPRESSO7420=y -CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420" CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420" CONFIG_SYS_PROMPT="ESPRESSO7420 # " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig index 579efd3f98a..a88d37b6207 100644 --- a/configs/ethernut5_defconfig +++ b/configs/ethernut5_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_ETHERNUT5=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 9894fffcca2..3f77981f948 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -39,6 +39,5 @@ CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 4af91206dcf..a64f6de349e 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -65,7 +65,6 @@ CONFIG_SYS_NS16550=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y -CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig index 298888c24bf..f6e01c1a36d 100644 --- a/configs/flea3_defconfig +++ b/configs/flea3_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_FLEA3=y CONFIG_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="flea3 U-Boot > " CONFIG_CMD_SPI=y diff --git a/configs/fo300_defconfig b/configs/fo300_defconfig index babfaf46758..aad6eaa8d48 100644 --- a/configs/fo300_defconfig +++ b/configs/fo300_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="FO300" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y diff --git a/configs/gdppc440etx_defconfig b/configs/gdppc440etx_defconfig index eacd4bb1eb6..ef4c4ed5d4b 100644 --- a/configs/gdppc440etx_defconfig +++ b/configs/gdppc440etx_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_GDPPC440ETX=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig index 6d0dabe119e..d8b42274d3e 100644 --- a/configs/glacier_defconfig +++ b/configs/glacier_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_CANYONLANDS=y CONFIG_GLACIER=y CONFIG_DEFAULT_DEVICE_TREE="glacier" CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig index e7e1287511f..2875492c3dc 100644 --- a/configs/glacier_ramboot_defconfig +++ b/configs/glacier_ramboot_defconfig @@ -5,6 +5,7 @@ CONFIG_GLACIER=y CONFIG_DEFAULT_DEVICE_TREE="glacier" CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index ee024694d68..cf251162a7f 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_GOFLEXHOME=y +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="GoFlexHome> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/gose_defconfig b/configs/gose_defconfig index 9f6589a1e98..f2075fe27db 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_RMOBILE=y CONFIG_TARGET_GOSE=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig index 2bdd0e7bed3..9fee96aee02 100644 --- a/configs/gplugd_defconfig +++ b/configs/gplugd_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_GPLUGD=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set diff --git a/configs/gr_cpci_ax2000_defconfig b/configs/gr_cpci_ax2000_defconfig index d3f9c0285ea..b30590ea2ba 100644 --- a/configs/gr_cpci_ax2000_defconfig +++ b/configs/gr_cpci_ax2000_defconfig @@ -1,6 +1,7 @@ CONFIG_SPARC=y -CONFIG_TARGET_GR_CPCI_AX2000=y CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_TARGET_GR_CPCI_AX2000=y +CONFIG_BOOTDELAY=5 # CONFIG_CMD_ELF is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y diff --git a/configs/gr_ep2s60_defconfig b/configs/gr_ep2s60_defconfig index 29c7f29beea..302d936e273 100644 --- a/configs/gr_ep2s60_defconfig +++ b/configs/gr_ep2s60_defconfig @@ -1,6 +1,7 @@ CONFIG_SPARC=y -CONFIG_TARGET_GR_EP2S60=y CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_TARGET_GR_EP2S60=y +CONFIG_BOOTDELAY=5 # CONFIG_CMD_ELF is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y diff --git a/configs/gr_xc3s_1500_defconfig b/configs/gr_xc3s_1500_defconfig index e4877f23f56..d6ed30581c9 100644 --- a/configs/gr_xc3s_1500_defconfig +++ b/configs/gr_xc3s_1500_defconfig @@ -1,6 +1,7 @@ CONFIG_SPARC=y -CONFIG_TARGET_GR_XC3S_1500=y CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_TARGET_GR_XC3S_1500=y +CONFIG_BOOTDELAY=5 # CONFIG_CMD_ELF is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y diff --git a/configs/grsim_defconfig b/configs/grsim_defconfig index d2f709f834e..f827113ab53 100644 --- a/configs/grsim_defconfig +++ b/configs/grsim_defconfig @@ -1,6 +1,7 @@ CONFIG_SPARC=y -CONFIG_TARGET_GRSIM=y CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_TARGET_GRSIM=y +CONFIG_BOOTDELAY=5 # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set diff --git a/configs/grsim_leon2_defconfig b/configs/grsim_leon2_defconfig index 9c9c9685824..f5e7c433fa5 100644 --- a/configs/grsim_leon2_defconfig +++ b/configs/grsim_leon2_defconfig @@ -1,6 +1,7 @@ CONFIG_SPARC=y -CONFIG_TARGET_GRSIM_LEON2=y CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_TARGET_GRSIM_LEON2=y +CONFIG_BOOTDELAY=5 # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index 0baf3a30af7..31794b9ea28 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_GURUPLUG=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index e04d96bee82..c4bd2c51de9 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -4,7 +4,6 @@ CONFIG_MACH_SUN8I_A83T=y CONFIG_DRAM_CLK=480 CONFIG_DRAM_ZQ=15355 CONFIG_DRAM_ODT_EN=y -CONFIG_MMC0_CD_PIN="PF6" CONFIG_USB0_VBUS_PIN="PL5" CONFIG_USB1_VBUS_PIN="PL6" CONFIG_AXP_GPIO=y diff --git a/configs/haleakala_defconfig b/configs/haleakala_defconfig index c90eff41418..4130e27602c 100644 --- a/configs/haleakala_defconfig +++ b/configs/haleakala_defconfig @@ -3,6 +3,7 @@ CONFIG_4xx=y CONFIG_TARGET_KILAUEA=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index 129a72b1cf9..16b0297f972 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -35,4 +35,3 @@ CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index d150dd3bcdb..ba0a37ebe2b 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey" CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y @@ -13,5 +14,3 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_LIBFDT=y -CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey" diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 32d04869558..f67eda701ca 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 657826a7a69..5eff4ac164c 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index 7ec54a738ed..ebf103a2ce9 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=4 CONFIG_MMC0_CD_PIN="PH1" diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index 5e68769fcd5..2cadf17201a 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_ZQ=127 CONFIG_DRAM_EMR1=4 diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 265114f2114..3b24256dd26 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_IB62X0=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ib62x0 => " CONFIG_CMD_BOOTZ=y diff --git a/configs/icon_defconfig b/configs/icon_defconfig index d32bbc4ce20..a2a70731da1 100644 --- a/configs/icon_defconfig +++ b/configs/icon_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_ICON=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index 44a474e634d..516b2393f25 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_ICONNECT=y +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="iconnect => " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/imx31_phycore_defconfig b/configs/imx31_phycore_defconfig index e824616c0f3..136b9d14ad0 100644 --- a/configs/imx31_phycore_defconfig +++ b/configs/imx31_phycore_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_IMX31_PHYCORE=y +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="uboot> " CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig index afe3c3c1b13..96252c3eacd 100644 --- a/configs/imx31_phycore_eet_defconfig +++ b/configs/imx31_phycore_eet_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_IMX31_PHYCORE=y CONFIG_SYS_EXTRA_OPTIONS="IMX31_PHYCORE_EET" +CONFIG_BOOTDELAY=3 CONFIG_CMD_SPI=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index a8b32cb3e62..e84ed57e53a 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=4 CONFIG_USB0_VBUS_PIN="PB9" diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig index 0b03e163c3a..2444a38c8fb 100644 --- a/configs/inet97fv2_defconfig +++ b/configs/inet97fv2_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_EMR1=4 CONFIG_USB0_VBUS_PIN="PB9" diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig index 153450ffc2d..a2489c4b1af 100644 --- a/configs/inet9f_rev03_defconfig +++ b/configs/inet9f_rev03_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_EMR1=4 CONFIG_USB0_VBUS_PIN="PB9" diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 483703ac362..3cbff46aa4d 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NETSPACE_V2=y CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set diff --git a/configs/intip_defconfig b/configs/intip_defconfig index 512d4a817fd..cd0f234e0c7 100644 --- a/configs/intip_defconfig +++ b/configs/intip_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_INTIP=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="INTIB" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/io64_defconfig b/configs/io64_defconfig index afc5a83db7e..27ffaeae104 100644 --- a/configs/io64_defconfig +++ b/configs/io64_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_IO64=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/io_defconfig b/configs/io_defconfig index 1bb9248c570..2392d9bcb9d 100644 --- a/configs/io_defconfig +++ b/configs/io_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_IO=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig index 2e66b9497e2..c7b3b277c40 100644 --- a/configs/iocon_defconfig +++ b/configs/iocon_defconfig @@ -3,6 +3,7 @@ CONFIG_4xx=y CONFIG_TARGET_IOCON=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/ipek01_defconfig b/configs/ipek01_defconfig index e0b4390c7d8..19f53dfb5cf 100644 --- a/configs/ipek01_defconfig +++ b/configs/ipek01_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_IPEK01=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index 9cb8b1da846..a9b90841cbf 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=312 CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index 7b04a0c150f..f672aa2f96b 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -44,4 +44,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="NVIDIA" CONFIG_G_DNL_VENDOR_NUM=0x0955 CONFIG_G_DNL_PRODUCT_NUM=0x701a -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/jupiter_defconfig b/configs/jupiter_defconfig index 21c448b8050..48249b0bd81 100644 --- a/configs/jupiter_defconfig +++ b/configs/jupiter_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_JUPITER=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_SNTP=y diff --git a/configs/katmai_defconfig b/configs/katmai_defconfig index b3e61f8a7d3..30c8bf02bf6 100644 --- a/configs/katmai_defconfig +++ b/configs/katmai_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_KATMAI=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/kilauea_defconfig b/configs/kilauea_defconfig index f85cfbb4b14..698de8c3866 100644 --- a/configs/kilauea_defconfig +++ b/configs/kilauea_defconfig @@ -3,6 +3,7 @@ CONFIG_4xx=y CONFIG_TARGET_KILAUEA=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="KILAUEA" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index 5c45f7be60b..217a868230b 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_RMOBILE=y CONFIG_TARGET_KOELSCH=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 0ff6c6b9a4a..bed9df82d04 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -34,6 +34,5 @@ CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y CONFIG_ROCKCHIP_3036_PINCTRL=y CONFIG_RAM=y -CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig index e3902ce01eb..00a54416b57 100644 --- a/configs/kzm9g_defconfig +++ b/configs/kzm9g_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_RMOBILE=y CONFIG_TARGET_KZM9G=y +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="KZM-A9-GT# " CONFIG_CMD_BOOTZ=y CONFIG_CMD_I2C=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index c26211706a2..19dd1fe27ee 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_RMOBILE=y CONFIG_TARGET_LAGER=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 04189debcf1..1aed0c45a83 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AFRDM=y # CONFIG_SYS_MALLOC_F is not set -CONFIG_SPI_FLASH=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" @@ -10,6 +9,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_SF=y @@ -25,6 +25,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_SYS_NS16550=y CONFIG_USB=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 935f2fdaa50..86ddf719d45 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AQDS=y # CONFIG_SYS_MALLOC_F is not set -CONFIG_SPI_FLASH=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" @@ -10,6 +9,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y @@ -26,6 +26,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 5c28bd10715..38064129192 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012ARDB=y # CONFIG_SYS_MALLOC_F is not set -CONFIG_SPI_FLASH=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" @@ -10,6 +9,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y @@ -26,6 +26,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index efaa7a9fd1c..6012d49595d 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -2,12 +2,12 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_DM_SERIAL=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_OF_LIBFDT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index 9fa5cb95262..685f1da1b3a 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -2,12 +2,12 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_DM_SERIAL=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart" -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_OF_LIBFDT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 24b7a15bfd5..eca1cca1138 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -1,9 +1,12 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y @@ -25,5 +28,3 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 5d2b57d489d..a39a4037aef 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -1,9 +1,12 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y # CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y @@ -27,5 +30,3 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 426a4bec039..67485465c16 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -2,11 +2,11 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_DM_SERIAL=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_OF_LIBFDT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 4f5c1e8200b..81035c9a1af 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -2,12 +2,12 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_DM_SERIAL=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart" -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_OF_LIBFDT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="LPUART" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 6a791c0a9c5..a1504c3a15b 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -2,12 +2,12 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_OF_LIBFDT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 33e5c0cec3c..f8bdfe8ec41 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -1,11 +1,11 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_OF_LIBFDT=y +CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 45f0f734c5c..a1ee5b95c41 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -2,11 +2,11 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_OF_LIBFDT=y +CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 16243ee4ff3..0d406ac24f2 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -1,9 +1,12 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y # CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y @@ -27,5 +30,3 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 315834032be..a6be6c63e68 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -2,11 +2,11 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y CONFIG_DM_SERIAL=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_OF_LIBFDT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index bbeb4bf1d50..3b6c5cf9610 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -2,12 +2,12 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y CONFIG_DM_SERIAL=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart" -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_OF_LIBFDT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="LPUART" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 6910c4e8501..0a6cbcd498a 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -2,12 +2,12 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y CONFIG_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_OF_LIBFDT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index f59ad74f16b..2128c464cc5 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -1,9 +1,12 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y @@ -24,5 +27,3 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 90f810adfae..8d1f8edef07 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -3,12 +3,12 @@ CONFIG_TARGET_LS1021ATWR=y CONFIG_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SPL=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_OF_LIBFDT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 1fbfd38d3f9..8dfad69a4a6 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 6b628d3c838..56f5efe5c51 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 90f870afa0f..61368878e70 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 813c269509f..7c78b6eaa66 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index e665ba44952..2b2a71426db 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 03a263a5eed..f90a6be38bf 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 0062f5c50ac..d85f7716287 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index bace827cb7b..218dd76dad2 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 48a89ab5f78..983e4c22b23 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 627a90dc6e2..c420548141d 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index c676a91c0f9..a5a870b1829 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig index 56922dc444a..21a02830d6e 100644 --- a/configs/ls2080a_emu_defconfig +++ b/configs/ls2080a_emu_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set @@ -25,5 +26,4 @@ CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y -CONFIG_BOOTP_VCI_STRING="U-Boot.LS2080A-EMU" CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig index f27fbb715e7..1b670b0c053 100644 --- a/configs/ls2080a_simu_defconfig +++ b/configs/ls2080a_simu_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set @@ -28,5 +29,4 @@ CONFIG_CMD_FAT=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y -CONFIG_BOOTP_VCI_STRING="U-Boot.LS2080A-SIMU" CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 49a4a26295b..947ac3d4201 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index c3053452ae3..cd8a7bdca61 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 8a6dd14b657..8c5b69d77fa 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index a2d88ccb905..8f98720ad11 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index dc2b872176a..c0b8a98da39 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index dbba8abae9a..26ffe985059 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index 4af7e5d7efa..002ca44d5b0 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_LSXL=y CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index 5bcd3678571..4f63da9b6c4 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_LSXL=y CONFIG_SYS_EXTRA_OPTIONS="LSXHL" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/luan_defconfig b/configs/luan_defconfig index e0fa8054200..90801f4a935 100644 --- a/configs/luan_defconfig +++ b/configs/luan_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_LUAN=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig index 64794a1f1ba..eaf6c97623a 100644 --- a/configs/lwmon5_defconfig +++ b/configs/lwmon5_defconfig @@ -3,6 +3,7 @@ CONFIG_4xx=y CONFIG_TARGET_LWMON5=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig index c598c7209d4..b505d293343 100644 --- a/configs/m28evk_defconfig +++ b/configs/m28evk_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_M28EVK=y CONFIG_SPL=y CONFIG_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig index 62496c39c60..962e03644de 100644 --- a/configs/m53evk_defconfig +++ b/configs/m53evk_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_M53EVK=y CONFIG_SPL=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig index 81a67004ff8..75affaa23fd 100644 --- a/configs/ma5d4evk_defconfig +++ b/configs/ma5d4evk_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MA5D4EVK=y CONFIG_SPL=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/makalu_defconfig b/configs/makalu_defconfig index 8f7baea6369..4967e10a105 100644 --- a/configs/makalu_defconfig +++ b/configs/makalu_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_MAKALU=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig index 7bef84c9c09..590f9b5674b 100644 --- a/configs/malta64_defconfig +++ b/configs/malta64_defconfig @@ -13,4 +13,3 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_OF_EMBED=y CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig index 47ded9ed8f9..ff93931c001 100644 --- a/configs/malta64el_defconfig +++ b/configs/malta64el_defconfig @@ -14,4 +14,3 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_OF_EMBED=y CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/malta_defconfig b/configs/malta_defconfig index 3c3bb165224..3a875860e48 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -12,4 +12,3 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_OF_EMBED=y CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index b245d915ef7..11ff25927ae 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -13,4 +13,3 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_OF_EMBED=y CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index 7a5eeba0224..b67bc51fe1b 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MAXBCM=y CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm" CONFIG_SPL=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig index ab814cc2138..2e819e40b4f 100644 --- a/configs/mcx_defconfig +++ b/configs/mcx_defconfig @@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y CONFIG_TARGET_MCX=y CONFIG_SPL=y CONFIG_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="mcx # " # CONFIG_CMD_IMI is not set diff --git a/configs/mecp5123_defconfig b/configs/mecp5123_defconfig index 9597482cb4e..98f006889fc 100644 --- a/configs/mecp5123_defconfig +++ b/configs/mecp5123_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC512X=y CONFIG_TARGET_MECP5123=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index 02eb70431b2..4dd4dcef162 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -34,4 +34,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig index 3d295f574d2..b214a923e40 100644 --- a/configs/meesc_dataflash_defconfig +++ b/configs/meesc_dataflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_MEESC=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig index aac7cc5e210..727d1936798 100644 --- a/configs/meesc_defconfig +++ b/configs/meesc_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_MEESC=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index d38bc7fdcfe..63b6a766f06 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_USB2_VBUS_PIN="PH12" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig index de1b73f2c81..c3664118053 100644 --- a/configs/mk802ii_defconfig +++ b/configs/mk802ii_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/mpc5121ads_defconfig b/configs/mpc5121ads_defconfig index 34935adcd2f..4bc7e4378e2 100644 --- a/configs/mpc5121ads_defconfig +++ b/configs/mpc5121ads_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC512X=y CONFIG_TARGET_MPC5121ADS=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/mpc5121ads_rev2_defconfig b/configs/mpc5121ads_rev2_defconfig index 664d9495e19..6c942fc3ecd 100644 --- a/configs/mpc5121ads_rev2_defconfig +++ b/configs/mpc5121ads_rev2_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC512X=y CONFIG_TARGET_MPC5121ADS=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="MPC5121ADS_REV2" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index 1f28c08f636..a1fdcf26eca 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC8308_P1M=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/ms7722se_defconfig b/configs/ms7722se_defconfig index a9bc3d4ea85..026f5667502 100644 --- a/configs/ms7722se_defconfig +++ b/configs/ms7722se_defconfig @@ -1,5 +1,6 @@ CONFIG_SH=y CONFIG_TARGET_MS7722SE=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig index dda0daa71b8..af583284489 100644 --- a/configs/mt_ventoux_defconfig +++ b/configs/mt_ventoux_defconfig @@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y CONFIG_TARGET_MT_VENTOUX=y CONFIG_SPL=y CONFIG_FIT=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="mt_ventoux => " # CONFIG_CMD_IMLS is not set diff --git a/configs/munices_defconfig b/configs/munices_defconfig index eabfe1ec4d5..169fc93cba5 100644 --- a/configs/munices_defconfig +++ b/configs/munices_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_MUNICES=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index e201abbb5ef..a028482bf08 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_MX23_OLINUXINO=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/mx31ads_defconfig b/configs/mx31ads_defconfig index 9ccf06964eb..b4c2ad3135c 100644 --- a/configs/mx31ads_defconfig +++ b/configs/mx31ads_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_MX31ADS=y +CONFIG_BOOTDELAY=3 CONFIG_CMD_SPI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig index 500b39c4daf..7a62c2b9542 100644 --- a/configs/mx53ard_defconfig +++ b/configs/mx53ard_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_MX53ARD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/mx53evk_defconfig b/configs/mx53evk_defconfig index 45f5e4570df..9a05a8bf8c9 100644 --- a/configs/mx53evk_defconfig +++ b/configs/mx53evk_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_MX53EVK=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y diff --git a/configs/mx53smd_defconfig b/configs/mx53smd_defconfig index c24aec6d685..93b20d7044f 100644 --- a/configs/mx53smd_defconfig +++ b/configs/mx53smd_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_MX53SMD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index f904e12b7b5..224b5b7805c 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NAS220=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="nas220> " # CONFIG_CMD_IMLS is not set diff --git a/configs/neo_defconfig b/configs/neo_defconfig index e306d681b3d..b61b7190a63 100644 --- a/configs/neo_defconfig +++ b/configs/neo_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_NEO=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set CONFIG_CMD_ASKENV=y diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index f930e473e4b..fcd4b13f2cd 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NET2BIG_V2=y CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="2big2> " # CONFIG_CMD_IMLS is not set diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 7917336c89a..a117946f485 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NETSPACE_V2=y CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index 55978f2ef9a..e4a1149b03c 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NETSPACE_V2=y CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index 67b142d236d..f46b9a1ecdf 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NETSPACE_V2=y CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 8199bbd911f..1b76bc27412 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NETSPACE_V2=y CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index 6eb01ea5111..da103929b73 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_NOKIA_RX51=y +CONFIG_BOOTDELAY=30 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Nokia RX-51 # " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index 51da5ad6ad6..fdec8dc04d4 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NSA310S=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="nsa310s => " CONFIG_CMD_BOOTZ=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 262042d87ff..6cf304f3b39 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -61,6 +61,5 @@ CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_TEGRA124=y CONFIG_VIDEO_BRIDGE=y -CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_TPM=y CONFIG_ERRNO_STR=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index c1d0fc3f8e1..44b5c160435 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_ARCH_EXYNOS5=y -CONFIG_TARGET_ODROID_XU3=y CONFIG_DM_I2C=y CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index 1a9f2076c77..adca5703270 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_EVM=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="OMAP3_EVM # " # CONFIG_CMD_IMI is not set diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig index 5f0dece597d..e446586dcba 100644 --- a/configs/omap3_ha_defconfig +++ b/configs/omap3_ha_defconfig @@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y CONFIG_TARGET_TAO3530=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index e7bf3854215..b8c76212980 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_LOGIC=y -CONFIG_USE_TINY_PRINTF=y CONFIG_SPL=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="NAND" @@ -34,4 +33,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="TI" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 +CONFIG_USE_TINY_PRINTF=y CONFIG_OF_LIBFDT=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 4d5e8a0c9e3..51dc1dba355 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_OMAPL138_LCDK=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " # CONFIG_CMD_IMLS is not set diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 700192132e0..2f4035541ee 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_OPENRD=y CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" +CONFIG_BOOTDELAY=3 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index fd53c783fc7..336104e695d 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_OPENRD=y CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" +CONFIG_BOOTDELAY=3 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index 52b9a5b74a2..11a49fe579c 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_OPENRD=y CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" +CONFIG_BOOTDELAY=3 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index 8b1082cd3e3..d5383d4c6ba 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -4,9 +4,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881979 CONFIG_DRAM_ODT_EN=y -CONFIG_MMC0_CD_PIN="PF6" CONFIG_USB1_VBUS_PIN="PG13" -# CONFIG_VIDEO is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig index be8afcab367..9b6a1af8fc8 100644 --- a/configs/orangepi_one_defconfig +++ b/configs/orangepi_one_defconfig @@ -4,8 +4,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881979 CONFIG_DRAM_ODT_EN=y -CONFIG_MMC0_CD_PIN="PF6" -# CONFIG_VIDEO is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index 7eaa795b32e..7f360f5d07e 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -4,7 +4,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881979 CONFIG_DRAM_ODT_EN=y -# CONFIG_VIDEO is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index 9ff433286f3..88df36064ed 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -4,10 +4,8 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881979 CONFIG_DRAM_ODT_EN=y -CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PG13" -# CONFIG_VIDEO is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/p2771-0000_defconfig b/configs/p2771-0000_defconfig index 9f2c418f9fe..1136e1f021b 100644 --- a/configs/p2771-0000_defconfig +++ b/configs/p2771-0000_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_TEGRA=y CONFIG_TEGRA186=y -CONFIG_TARGET_P2771_0000=y CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000" CONFIG_OF_SYSTEM_SETUP=y CONFIG_HUSH_PARSER=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index 0fe43b1c958..64b956f5948 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -33,4 +33,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/pb1000_defconfig b/configs/pb1000_defconfig index 6aa2c43ecb7..5a7fa80e0db 100644 --- a/configs/pb1000_defconfig +++ b/configs/pb1000_defconfig @@ -14,4 +14,3 @@ CONFIG_SYS_PROMPT="Pb1x00 # " CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/pcm030_LOWBOOT_defconfig b/configs/pcm030_LOWBOOT_defconfig index dbfaea1d902..6205aa3bd2c 100644 --- a/configs/pcm030_LOWBOOT_defconfig +++ b/configs/pcm030_LOWBOOT_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_PCM030=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000" +CONFIG_BOOTDELAY=3 CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/pcm030_defconfig b/configs/pcm030_defconfig index 6d2588498ef..994a369991f 100644 --- a/configs/pcm030_defconfig +++ b/configs/pcm030_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_PCM030=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="uboot> " CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig index 27f681ffe4e..7f291197f3e 100644 --- a/configs/pcm051_rev1_defconfig +++ b/configs/pcm051_rev1_defconfig @@ -30,4 +30,3 @@ CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_GADGET=y CONFIG_OF_LIBFDT=y -CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL" diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index b277b3aa0e0..eff099cd762 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -30,4 +30,3 @@ CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_GADGET=y CONFIG_OF_LIBFDT=y -CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL" diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index db8ebdd620f..5d30f30bb8c 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="pcm052" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/pdm360ng_defconfig b/configs/pdm360ng_defconfig index c3521955eef..f3de685392c 100644 --- a/configs/pdm360ng_defconfig +++ b/configs/pdm360ng_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_PDM360NG=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig index 9547d4891b0..d5e9408260b 100644 --- a/configs/pic32mzdask_defconfig +++ b/configs/pic32mzdask_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_PIC32=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="dask # " # CONFIG_CMD_IMLS is not set @@ -42,6 +43,5 @@ CONFIG_DM_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_PIC32=y CONFIG_USB_STORAGE=y -CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig index 723466f694e..f7069e90c1c 100644 --- a/configs/picosam9g45_defconfig +++ b/configs/picosam9g45_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_PICOSAM9G45=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index 0bf79bfd334..2d9c4a6990d 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN50I=y CONFIG_DRAM_CLK=672 @@ -9,4 +10,3 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set -CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig index ed519a04ab1..6b60335d92a 100644 --- a/configs/plutux_defconfig +++ b/configs/plutux_defconfig @@ -29,4 +29,3 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig index cb10fa37009..2062dcd3fc3 100644 --- a/configs/pm9261_defconfig +++ b/configs/pm9261_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_PM9261=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="pm9261> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig index 37629ba0f5b..e6ebd9b7839 100644 --- a/configs/pm9263_defconfig +++ b/configs/pm9263_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_PM9263=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="u-boot-pm9263> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig index 0949e1f6216..aea412ce5df 100644 --- a/configs/pm9g45_defconfig +++ b/configs/pm9g45_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_PM9G45=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_IMLS is not set diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index 2b3b4c84b8d..bd4db7165e9 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_POGO_E02=y +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="PogoE02> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/porter_defconfig b/configs/porter_defconfig index 2f819f50354..a587ed5ab2c 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_RMOBILE=y CONFIG_TARGET_PORTER=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig index 9aa52800a54..23bd9a9d09d 100644 --- a/configs/pov_protab2_ips9_defconfig +++ b/configs/pov_protab2_ips9_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 86556650a9b..6f70d6805b6 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_PXM2=y CONFIG_SPL=y CONFIG_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/qemu_mips64_defconfig b/configs/qemu_mips64_defconfig index 0826a0ca888..b013a17f9da 100644 --- a/configs/qemu_mips64_defconfig +++ b/configs/qemu_mips64_defconfig @@ -1,6 +1,7 @@ CONFIG_MIPS=y CONFIG_TARGET_QEMU_MIPS=y CONFIG_CPU_MIPS64_R1=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="qemu-mips64 # " # CONFIG_CMD_LOADB is not set @@ -11,4 +12,3 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/qemu_mips64el_defconfig b/configs/qemu_mips64el_defconfig index f70ebc30b18..bffa1a38cb1 100644 --- a/configs/qemu_mips64el_defconfig +++ b/configs/qemu_mips64el_defconfig @@ -2,6 +2,7 @@ CONFIG_MIPS=y CONFIG_TARGET_QEMU_MIPS=y CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_CPU_MIPS64_R1=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="qemu-mips64el # " # CONFIG_CMD_LOADB is not set @@ -12,4 +13,3 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/qemu_mips_defconfig b/configs/qemu_mips_defconfig index bb097966e8c..9cab7dd43ef 100644 --- a/configs/qemu_mips_defconfig +++ b/configs/qemu_mips_defconfig @@ -1,5 +1,6 @@ CONFIG_MIPS=y CONFIG_TARGET_QEMU_MIPS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="qemu-mips # " # CONFIG_CMD_LOADB is not set @@ -9,4 +10,3 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/qemu_mipsel_defconfig b/configs/qemu_mipsel_defconfig index 19e6c7d7ad5..b9226a8d4eb 100644 --- a/configs/qemu_mipsel_defconfig +++ b/configs/qemu_mipsel_defconfig @@ -1,6 +1,7 @@ CONFIG_MIPS=y CONFIG_TARGET_QEMU_MIPS=y CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="qemu-mipsel # " # CONFIG_CMD_LOADB is not set @@ -10,4 +11,3 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/r0p7734_defconfig b/configs/r0p7734_defconfig index 52149239d70..5f77e053487 100644 --- a/configs/r0p7734_defconfig +++ b/configs/r0p7734_defconfig @@ -1,5 +1,6 @@ CONFIG_SH=y CONFIG_TARGET_R0P7734=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/r7780mp_defconfig b/configs/r7780mp_defconfig index ad6f2f08150..fbf2dd51cf2 100644 --- a/configs/r7780mp_defconfig +++ b/configs/r7780mp_defconfig @@ -1,5 +1,6 @@ CONFIG_SH=y CONFIG_TARGET_R7780MP=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/rainier_defconfig b/configs/rainier_defconfig index 27998f38f8a..093207ce4ce 100644 --- a/configs/rainier_defconfig +++ b/configs/rainier_defconfig @@ -3,6 +3,7 @@ CONFIG_4xx=y CONFIG_TARGET_SEQUOIA=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="RAINIER" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/rainier_ramboot_defconfig b/configs/rainier_ramboot_defconfig index 6ebdb380ca1..a7879aef5d7 100644 --- a/configs/rainier_ramboot_defconfig +++ b/configs/rainier_ramboot_defconfig @@ -3,6 +3,7 @@ CONFIG_4xx=y CONFIG_TARGET_SEQUOIA=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index ec89f050c7b..7de5a199fe2 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_RASTABAN=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/redwood_defconfig b/configs/redwood_defconfig index 89c129f8feb..1cf4832c187 100644 --- a/configs/redwood_defconfig +++ b/configs/redwood_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_REDWOOD=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 3e16b805caa..516bee7a3cc 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -63,7 +63,6 @@ CONFIG_SYS_NS16550=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y -CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/rsk7264_defconfig b/configs/rsk7264_defconfig index 272bd863e80..9cc5a201f26 100644 --- a/configs/rsk7264_defconfig +++ b/configs/rsk7264_defconfig @@ -1,4 +1,5 @@ CONFIG_SH=y CONFIG_TARGET_RSK7264=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_SETEXPR is not set CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/rsk7269_defconfig b/configs/rsk7269_defconfig index 41e70a5c587..58a56442754 100644 --- a/configs/rsk7269_defconfig +++ b/configs/rsk7269_defconfig @@ -1,4 +1,5 @@ CONFIG_SH=y CONFIG_TARGET_RSK7269=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_SETEXPR is not set CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 406eaf33db6..14a158f6ef3 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_RUT=y CONFIG_SPL=y CONFIG_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/sama5d2_ptc_nandflash_defconfig b/configs/sama5d2_ptc_nandflash_defconfig index 74251840fce..fce501b32e6 100644 --- a/configs/sama5d2_ptc_nandflash_defconfig +++ b/configs/sama5d2_ptc_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D2_PTC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/sama5d2_ptc_spiflash_defconfig b/configs/sama5d2_ptc_spiflash_defconfig index 27fc394d42a..c090264e752 100644 --- a/configs/sama5d2_ptc_spiflash_defconfig +++ b/configs/sama5d2_ptc_spiflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D2_PTC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH" +CONFIG_BOOTDELAY=3 # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index 1880256125b..9ca2a9c5e9f 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -2,7 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D2_XPLAINED=y CONFIG_SPL=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -21,4 +23,3 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index de8f4d9256b..617d73a77ee 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -2,7 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D2_XPLAINED=y CONFIG_SPL=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -21,4 +23,3 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 1dabc5f49d5..db6592ac067 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -2,7 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D3_XPLAINED=y CONFIG_SPL=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -19,4 +21,3 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index 458a486acde..d70c3b78a94 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -2,7 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D3_XPLAINED=y CONFIG_SPL=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -19,4 +21,3 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 488d950fecb..5738d2a6a56 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -2,7 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D3XEK=y CONFIG_SPL=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -21,4 +23,3 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index 12f28f20131..93aef74e3f0 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -2,7 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D3XEK=y CONFIG_SPL=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -21,4 +23,3 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 42fcc1ed0ae..a938fe79654 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -2,7 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D3XEK=y CONFIG_SPL=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -21,4 +23,3 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 3110269a760..74e208769f4 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -2,7 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D4_XPLAINED=y CONFIG_SPL=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -22,4 +24,3 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 3ea4bd7f327..3af7ed48d1f 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -2,7 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D4_XPLAINED=y CONFIG_SPL=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -22,4 +24,3 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index dbec4ad3e45..0e037c3db3e 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -2,7 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D4_XPLAINED=y CONFIG_SPL=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -22,4 +24,3 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index f2a5844385d..98113266421 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -2,7 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D4EK=y CONFIG_SPL=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -22,4 +24,3 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index 58186cec624..37b080aadea 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -2,7 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D4EK=y CONFIG_SPL=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -22,4 +24,3 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index ab23e950f74..ba939b103b0 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -2,7 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D4EK=y CONFIG_SPL=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -22,4 +24,3 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y -CONFIG_FIT=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 4eb3c224fdc..71f713083a1 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -1,4 +1,5 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_BLK=y CONFIG_MMC=y CONFIG_PCI=y CONFIG_DEFAULT_DEVICE_TREE="sandbox" @@ -70,7 +71,6 @@ CONFIG_DEVRES=y CONFIG_DEBUG_DEVRES=y CONFIG_ADC=y CONFIG_ADC_SANDBOX=y -CONFIG_BLK=y CONFIG_CLK=y CONFIG_CPU=y CONFIG_DM_DEMO=y @@ -89,6 +89,9 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_SANDBOX_MBOX=y +CONFIG_MISC=y CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y @@ -170,6 +173,3 @@ CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y CONFIG_UT_ENV=y -CONFIG_MISC=y -CONFIG_DM_MAILBOX=y -CONFIG_SANDBOX_MBOX=y diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig index 9dd60b7b0ba..16f61de5217 100644 --- a/configs/sansa_fuze_plus_defconfig +++ b/configs/sansa_fuze_plus_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_SANSA_FUZE_PLUS=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 60bb817180d..7231b60274c 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8349=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 6c0fd99f077..bf125a56233 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8349=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M" +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index e22c70ad3d1..daa2313f394 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig index 6d5b3f6c467..c5fc4a0e046 100644 --- a/configs/sbc8548_PCI_33_PCIE_defconfig +++ b/configs/sbc8548_PCI_33_PCIE_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig index 8ecb12661a9..1fd17cabb49 100644 --- a/configs/sbc8548_PCI_33_defconfig +++ b/configs/sbc8548_PCI_33_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,33" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig index bbea0cb4c37..5396e5aa8e8 100644 --- a/configs/sbc8548_PCI_66_PCIE_defconfig +++ b/configs/sbc8548_PCI_66_PCIE_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig index f146b2d8462..ffde0564b35 100644 --- a/configs/sbc8548_PCI_66_defconfig +++ b/configs/sbc8548_PCI_66_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,66" +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig index 3dea198cb65..a8a8a93ee11 100644 --- a/configs/sbc8548_defconfig +++ b/configs/sbc8548_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig index ad384579918..a382794dad3 100644 --- a/configs/sbc8641d_defconfig +++ b/configs/sbc8641d_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC86xx=y CONFIG_TARGET_SBC8641D=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig index 4b73506c989..a3bf903ff18 100644 --- a/configs/sc_sps_1_defconfig +++ b/configs/sc_sps_1_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_SC_SPS_1=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index 3f8648ddeb1..9ffefbd4332 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -34,4 +34,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sequoia_defconfig b/configs/sequoia_defconfig index 66d6a1aba33..8619c57f8f0 100644 --- a/configs/sequoia_defconfig +++ b/configs/sequoia_defconfig @@ -3,6 +3,7 @@ CONFIG_4xx=y CONFIG_TARGET_SEQUOIA=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/sequoia_ramboot_defconfig b/configs/sequoia_ramboot_defconfig index 5c548ff2799..81cda465a46 100644 --- a/configs/sequoia_ramboot_defconfig +++ b/configs/sequoia_ramboot_defconfig @@ -3,6 +3,7 @@ CONFIG_4xx=y CONFIG_TARGET_SEQUOIA=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig index 07594d1abb2..f7e055b9223 100644 --- a/configs/sh7752evb_defconfig +++ b/configs/sh7752evb_defconfig @@ -1,6 +1,7 @@ CONFIG_SH=y CONFIG_SH_32BIT=y CONFIG_TARGET_SH7752EVB=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig index 5e7a9c9e048..fc6c7b16444 100644 --- a/configs/sh7753evb_defconfig +++ b/configs/sh7753evb_defconfig @@ -1,5 +1,6 @@ CONFIG_SH=y CONFIG_TARGET_SH7753EVB=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig index fafba4ce82d..b0d3f28591f 100644 --- a/configs/sh7757lcr_defconfig +++ b/configs/sh7757lcr_defconfig @@ -1,6 +1,7 @@ CONFIG_SH=y CONFIG_SH_32BIT=y CONFIG_TARGET_SH7757LCR=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/sh7785lcr_32bit_defconfig b/configs/sh7785lcr_32bit_defconfig index cc31e1cb4dc..d98e073e069 100644 --- a/configs/sh7785lcr_32bit_defconfig +++ b/configs/sh7785lcr_32bit_defconfig @@ -1,6 +1,7 @@ CONFIG_SH=y CONFIG_SH_32BIT=y CONFIG_TARGET_SH7785LCR=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/sh7785lcr_defconfig b/configs/sh7785lcr_defconfig index d7724b30d67..368cb3027b3 100644 --- a/configs/sh7785lcr_defconfig +++ b/configs/sh7785lcr_defconfig @@ -1,5 +1,6 @@ CONFIG_SH=y CONFIG_TARGET_SH7785LCR=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 71ce49c568d..5cd37a430e3 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_SHEEVAPLUG=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 0beef09f059..f5d7afde581 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_RMOBILE=y CONFIG_TARGET_SILK=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 2ec6e488681..1c29a290c06 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SMARTWEB=y CONFIG_SPL=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/smdk2410_defconfig b/configs/smdk2410_defconfig index 702b36c012c..4d40a29c14c 100644 --- a/configs/smdk2410_defconfig +++ b/configs/smdk2410_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_SMDK2410=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SMDK2410 # " CONFIG_CMD_USB=y diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig index a989e244a6d..0948534e89b 100644 --- a/configs/smdkc100_defconfig +++ b/configs/smdkc100_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_S5PC1XX=y CONFIG_TARGET_SMDKC100=y CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SMDKC100 # " # CONFIG_CMD_IMLS is not set diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig index 5ba6523bdb3..5e3844cf476 100644 --- a/configs/smdkv310_defconfig +++ b/configs/smdkv310_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_ARCH_EXYNOS4=y -CONFIG_TARGET_SMDKV310=y CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310" CONFIG_SPL=y CONFIG_HUSH_PARSER=y diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig index 2f8dd50ab39..166fd2f0e9c 100644 --- a/configs/snapper9260_defconfig +++ b/configs/snapper9260_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_SNAPPER9260=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Snapper> " # CONFIG_CMD_BDI is not set diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig index f72569323ec..3cfe694d064 100644 --- a/configs/snapper9g20_defconfig +++ b/configs/snapper9g20_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_SNAPPER9260=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index ec40ec72dca..2478ae571db 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y @@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk" CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set @@ -55,3 +55,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="altera" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 8e5c527ac2f..1619b86a9f0 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y @@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set @@ -55,3 +55,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="altera" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 034a2153610..43d939bbd18 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y @@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc" CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set @@ -49,3 +49,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="terasic" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 133a6eba2af..c5c662b47e5 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y @@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk" CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set @@ -49,3 +49,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="denx" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 8b1bcfcee61..1c4a40dd0eb 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y @@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit" CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set @@ -55,3 +55,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="terasic" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 56284a1c0a7..e34d13e39af 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y @@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set @@ -55,3 +55,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="ebv" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index d66f7c605ed..d1cfbcd7f85 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_SR1500=y @@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set @@ -44,3 +44,4 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y +CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 6ce4defca43..80552a5be26 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y @@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga" CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_FIT=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set @@ -55,3 +55,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="samtec" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_USE_TINY_PRINTF=y diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index 86dfd0e83fa..ae9976bb6e8 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_STM32=y CONFIG_STM32F4=y CONFIG_TARGET_STM32F429_DISCOVERY=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 00482269c25..e3e6333add6 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_STM32=y CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index a8f59ca86c7..9073c178755 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_RMOBILE=y CONFIG_TARGET_STOUT=y +CONFIG_BOOTDELAY=3 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 985aab8da23..6253615eb57 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index b7a16b7a381..3d325f43466 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON_DP" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 2766104a4c6..160df247f1b 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index db75c0d2d61..2a2733dfbaa 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU,STRIDER_CPU_DP" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 6a3b5b83571..40ca293bad3 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_STV0991=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="stv0991" CONFIG_SYS_EXTRA_OPTIONS="stv0991" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="STV0991> " CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index 6d39dec371b..5861cff64df 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=4 CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0" diff --git a/configs/sycamore_defconfig b/configs/sycamore_defconfig index 9fdb2b37225..5f7b40d8963 100644 --- a/configs/sycamore_defconfig +++ b/configs/sycamore_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_WALNUT=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/t3corp_defconfig b/configs/t3corp_defconfig index c5562c936d2..750599689f0 100644 --- a/configs/t3corp_defconfig +++ b/configs/t3corp_defconfig @@ -3,6 +3,7 @@ CONFIG_4xx=y CONFIG_TARGET_T3CORP=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig index 6d0877d165a..4ee5737ccce 100644 --- a/configs/tao3530_defconfig +++ b/configs/tao3530_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_TAO3530=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="TAO-3530 # " # CONFIG_CMD_IMI is not set diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 20f33a85289..e566f7f023a 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_TAURUS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig index 83b1b56c570..2d157b2b3ea 100644 --- a/configs/tb100_defconfig +++ b/configs/tb100_defconfig @@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y CONFIG_SYS_CLK_FREQ=500000000 CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100" +CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="[tb100]:~# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig index b7102298e37..7dbb4cd8d41 100644 --- a/configs/tec-ng_defconfig +++ b/configs/tec-ng_defconfig @@ -35,4 +35,3 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA20_SLINK=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/tec_defconfig b/configs/tec_defconfig index 20551013999..742d90d1c0a 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -34,4 +34,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index 83587575c50..05368bdfa08 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y CONFIG_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig index 157985f34bd..17bf8cd78e7 100644 --- a/configs/theadorable_defconfig +++ b/configs/theadorable_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y CONFIG_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index f9391f2f11b..0b69c075d65 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_THUBAN=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig index cb33f601bb6..4a8655f9bb5 100644 --- a/configs/thunderx_88xx_defconfig +++ b/configs/thunderx_88xx_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_THUNDERX_88XX=y CONFIG_DM_SERIAL=y CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx" CONFIG_SYS_EXTRA_OPTIONS="ARM64" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ThunderX_88XX> " # CONFIG_CMD_IMLS is not set @@ -22,4 +23,3 @@ CONFIG_DEBUG_UART_BASE=0x87e024000000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_REGEX=y -CONFIG_BOOTP_VCI_STRING="Diagnostics" diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig index 4eb79237233..c4240e900a1 100644 --- a/configs/ti816x_evm_defconfig +++ b/configs/ti816x_evm_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_TI816X_EVM=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot/ti816x# " # CONFIG_CMD_IMLS is not set diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig index 3eec4c2db94..a69c0b63b12 100644 --- a/configs/tplink_wdr4300_defconfig +++ b/configs/tplink_wdr4300_defconfig @@ -1,35 +1,24 @@ CONFIG_MIPS=y -CONFIG_ARCH_ATH79=y -CONFIG_BOARD_TPLINK_WDR4300=y -CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SYS_NS16550=y CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ARCH_ATH79=y +CONFIG_BOARD_TPLINK_WDR4300=y CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300" +CONFIG_BOOTDELAY=3 # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y # CONFIG_CMD_FPGA is not set -CONFIG_CMD_NET=y -CONFIG_CMD_NFS=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_DM_ETH=y -CONFIG_AG7XXX=y CONFIG_CLK=y -CONFIG_CMD_USB=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_STORAGE=y -CONFIG_ATH79_SPI=y -CONFIG_DM_SPI=y -CONFIG_DM_SPI_FLASH=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y @@ -41,4 +30,13 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_AG7XXX=y CONFIG_PINCTRL=y +CONFIG_SYS_NS16550=y +CONFIG_ATH79_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig index 67857a50247..72e641d9f60 100644 --- a/configs/trimslice_defconfig +++ b/configs/trimslice_defconfig @@ -36,4 +36,3 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA20_SFLASH=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/twister_defconfig b/configs/twister_defconfig index ffbc0251241..0e57f7c8522 100644 --- a/configs/twister_defconfig +++ b/configs/twister_defconfig @@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y CONFIG_TARGET_TWISTER=y CONFIG_SPL=y CONFIG_FIT=y +CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="twister => " # CONFIG_CMD_IMLS is not set diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig index ffcac79762a..e7f9b15a216 100644 --- a/configs/uniphier_ld11_defconfig +++ b/configs/uniphier_ld11_defconfig @@ -5,6 +5,7 @@ CONFIG_ARCH_UNIPHIER_LD11=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld11-ref" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_XIMG is not set # CONFIG_CMD_ENV_EXISTS is not set diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig index cbc65ddc8d1..d073e3d127b 100644 --- a/configs/uniphier_ld20_defconfig +++ b/configs/uniphier_ld20_defconfig @@ -5,6 +5,7 @@ CONFIG_ARCH_UNIPHIER_LD20=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_XIMG is not set # CONFIG_CMD_ENV_EXISTS is not set diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index 22615a647cc..04d651d358b 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -5,6 +5,7 @@ CONFIG_ARCH_UNIPHIER_LD4_SLD8=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_XIMG is not set diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig index 18f4caf33b5..d5fc13829f5 100644 --- a/configs/uniphier_pro4_defconfig +++ b/configs/uniphier_pro4_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_XIMG is not set diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig index cf6d3e42310..285ea98553c 100644 --- a/configs/uniphier_pxs2_ld6b_defconfig +++ b/configs/uniphier_pxs2_ld6b_defconfig @@ -5,6 +5,7 @@ CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_XIMG is not set diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig index 0965019318a..13f31470f0e 100644 --- a/configs/uniphier_sld3_defconfig +++ b/configs/uniphier_sld3_defconfig @@ -4,6 +4,7 @@ CONFIG_ARCH_UNIPHIER_SLD3=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_XIMG is not set diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig index fa5561aeb3e..916a9c69221 100644 --- a/configs/usb_a9263_dataflash_defconfig +++ b/configs/usb_a9263_dataflash_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_USB_A9263=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/v38b_defconfig b/configs/v38b_defconfig index 4dd26123ffc..a54999c7ce8 100644 --- a/configs/v38b_defconfig +++ b/configs/v38b_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_V38B=y +CONFIG_BOOTDELAY=3 CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig index ed27d853c23..c65a20014ba 100644 --- a/configs/vct_platinum_defconfig +++ b/configs/vct_platinum_defconfig @@ -1,6 +1,7 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y CONFIG_VCT_PLATINUM=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="$ " CONFIG_CMD_I2C=y CONFIG_CMD_USB=y @@ -10,4 +11,3 @@ CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_FAT=y CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig index 82708f0da2d..23bfe4ad66a 100644 --- a/configs/vct_platinum_onenand_defconfig +++ b/configs/vct_platinum_onenand_defconfig @@ -2,6 +2,7 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y CONFIG_VCT_PLATINUM=y CONFIG_VCT_ONENAND=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set @@ -13,4 +14,3 @@ CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_FAT=y CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_platinum_onenand_small_defconfig b/configs/vct_platinum_onenand_small_defconfig index 7b379be2cce..3306a45e48d 100644 --- a/configs/vct_platinum_onenand_small_defconfig +++ b/configs/vct_platinum_onenand_small_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_VCT=y CONFIG_VCT_PLATINUM=y CONFIG_VCT_ONENAND=y CONFIG_VCT_SMALL_IMAGE=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set @@ -19,4 +20,3 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_platinum_small_defconfig b/configs/vct_platinum_small_defconfig index 78d215d54ce..06476139ca5 100644 --- a/configs/vct_platinum_small_defconfig +++ b/configs/vct_platinum_small_defconfig @@ -2,6 +2,7 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y CONFIG_VCT_PLATINUM=y CONFIG_VCT_SMALL_IMAGE=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set @@ -16,4 +17,3 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_platinumavc_defconfig b/configs/vct_platinumavc_defconfig index c47f1026dfc..1660c662e83 100644 --- a/configs/vct_platinumavc_defconfig +++ b/configs/vct_platinumavc_defconfig @@ -1,6 +1,7 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y CONFIG_VCT_PLATINUMAVC=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="VCT# " CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set @@ -8,4 +9,3 @@ CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_platinumavc_onenand_defconfig b/configs/vct_platinumavc_onenand_defconfig index e7aef319c53..55dfd4cd49b 100644 --- a/configs/vct_platinumavc_onenand_defconfig +++ b/configs/vct_platinumavc_onenand_defconfig @@ -2,6 +2,7 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y CONFIG_VCT_PLATINUMAVC=y CONFIG_VCT_ONENAND=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set @@ -11,4 +12,3 @@ CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_platinumavc_onenand_small_defconfig b/configs/vct_platinumavc_onenand_small_defconfig index be70588cf00..98b5ea217c6 100644 --- a/configs/vct_platinumavc_onenand_small_defconfig +++ b/configs/vct_platinumavc_onenand_small_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_VCT=y CONFIG_VCT_PLATINUMAVC=y CONFIG_VCT_ONENAND=y CONFIG_VCT_SMALL_IMAGE=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set @@ -19,4 +20,3 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_platinumavc_small_defconfig b/configs/vct_platinumavc_small_defconfig index b7e0a782fb5..f4a95493db4 100644 --- a/configs/vct_platinumavc_small_defconfig +++ b/configs/vct_platinumavc_small_defconfig @@ -2,6 +2,7 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y CONFIG_VCT_PLATINUMAVC=y CONFIG_VCT_SMALL_IMAGE=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set @@ -16,4 +17,3 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig index 29d16e3aa10..f85deb38cf4 100644 --- a/configs/vct_premium_defconfig +++ b/configs/vct_premium_defconfig @@ -1,6 +1,7 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y CONFIG_VCT_PREMIUM=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="$ " CONFIG_CMD_I2C=y CONFIG_CMD_USB=y @@ -10,4 +11,3 @@ CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_FAT=y CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig index 31b89e3718f..11879e5bb9c 100644 --- a/configs/vct_premium_onenand_defconfig +++ b/configs/vct_premium_onenand_defconfig @@ -2,6 +2,7 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y CONFIG_VCT_PREMIUM=y CONFIG_VCT_ONENAND=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set @@ -13,4 +14,3 @@ CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_FAT=y CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_premium_onenand_small_defconfig b/configs/vct_premium_onenand_small_defconfig index a3a93b84cdb..ff5e7a68cd6 100644 --- a/configs/vct_premium_onenand_small_defconfig +++ b/configs/vct_premium_onenand_small_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_VCT=y CONFIG_VCT_PREMIUM=y CONFIG_VCT_ONENAND=y CONFIG_VCT_SMALL_IMAGE=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set @@ -19,4 +20,3 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_premium_small_defconfig b/configs/vct_premium_small_defconfig index fddc04d75dd..c601676bcba 100644 --- a/configs/vct_premium_small_defconfig +++ b/configs/vct_premium_small_defconfig @@ -2,6 +2,7 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y CONFIG_VCT_PREMIUM=y CONFIG_VCT_SMALL_IMAGE=y +CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set @@ -16,4 +17,3 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set CONFIG_SYS_NS16550=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 4ae35505b14..faeb15cc169 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC83xx=y CONFIG_TARGET_VE8313=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index 17a6000d774..edbb18fb6ac 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -42,4 +42,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="NVIDIA" CONFIG_G_DNL_VENDOR_NUM=0x0955 CONFIG_G_DNL_PRODUCT_NUM=0x701a -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index 97b13a1b1d4..aeb90250327 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -33,4 +33,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig index c0708b288e2..989f06880ec 100644 --- a/configs/vexpress_aemv8a_dram_defconfig +++ b/configs/vexpress_aemv8a_dram_defconfig @@ -24,4 +24,3 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y CONFIG_DM=y CONFIG_OF_LIBFDT=y -CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a" diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 5af9f582333..c70851fc4c1 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -24,4 +24,3 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y CONFIG_DM=y CONFIG_OF_LIBFDT=y -CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a" diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index 379dff24991..b0a2f6710ae 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -24,4 +24,3 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y CONFIG_DM=y CONFIG_OF_LIBFDT=y -CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a" diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig index c39faaa67a9..2f141dda06c 100644 --- a/configs/vexpress_ca15_tc2_defconfig +++ b/configs/vexpress_ca15_tc2_defconfig @@ -24,4 +24,3 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_LIBFDT=y -CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca15x2_tc2" diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig index e71d45ed055..c495ee589c3 100644 --- a/configs/vexpress_ca5x2_defconfig +++ b/configs/vexpress_ca5x2_defconfig @@ -24,4 +24,3 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_LIBFDT=y -CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca5x2" diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index 20100a30758..fcd6e26db5f 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -24,4 +24,3 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_LIBFDT=y -CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca9x4" diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig index c014294ae7e..63a6ab97df6 100644 --- a/configs/vf610twr_defconfig +++ b/configs/vf610twr_defconfig @@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="vf610-twr" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig index d50ad907877..f66ff4aec6b 100644 --- a/configs/vf610twr_nand_defconfig +++ b/configs/vf610twr_nand_defconfig @@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="vf610-twr" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig index e79cc4d21b5..0a373a39950 100644 --- a/configs/vinco_defconfig +++ b/configs/vinco_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_VINCO=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="vinco => " CONFIG_CMD_BOOTZ=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 887afdf9f20..b23f2356dca 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC83xx=y CONFIG_TARGET_VME8349=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/walnut_defconfig b/configs/walnut_defconfig index 9fdb2b37225..5f7b40d8963 100644 --- a/configs/walnut_defconfig +++ b/configs/walnut_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_WALNUT=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig index ca753a45417..754e5cb46aa 100644 --- a/configs/whistler_defconfig +++ b/configs/whistler_defconfig @@ -29,4 +29,3 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig index b4660cdb9b0..a2e59576108 100644 --- a/configs/woodburn_defconfig +++ b/configs/woodburn_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_WOODBURN=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="woodburn U-Boot > " CONFIG_CMD_MMC=y diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig index bb1ef0aa185..3b381302e61 100644 --- a/configs/woodburn_sd_defconfig +++ b/configs/woodburn_sd_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_WOODBURN_SD=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="woodburn U-Boot > " CONFIG_CMD_MMC=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 5663b2f3616..e9fa7734e6c 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_DM=y CONFIG_DM_SERIAL=y CONFIG_DM_GPIO=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/wtk_defconfig b/configs/wtk_defconfig index 9341087de20..336d8e42bf6 100644 --- a/configs/wtk_defconfig +++ b/configs/wtk_defconfig @@ -3,6 +3,7 @@ CONFIG_8xx=y CONFIG_TARGET_TQM823L=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ065T9DR51U" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/x600_defconfig b/configs/x600_defconfig index 14977dca8a1..b91a7111695 100644 --- a/configs/x600_defconfig +++ b/configs/x600_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_X600=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="X600> " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig index 59e1014a3ab..31a647e2e71 100644 --- a/configs/xfi3_defconfig +++ b/configs/xfi3_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_XFI3=y CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig index 6c021d70761..8e07d4001e3 100644 --- a/configs/xilinx-ppc405-generic_defconfig +++ b/configs/xilinx-ppc405-generic_defconfig @@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc405-generic" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="xlx-ppc405:/# " # CONFIG_CMD_IMLS is not set diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig index ab0ea5a7184..7f085de146d 100644 --- a/configs/xilinx-ppc440-generic_defconfig +++ b/configs/xilinx-ppc440-generic_defconfig @@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="board:/# " CONFIG_CMD_ASKENV=y diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index fa380ef7f08..7325f190f0b 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_CONSOLE is not set diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 35226d6fd3c..91af8ce3267 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index cc13179a1e5..3e7331257c8 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index 65703481ae3..2805219f7b1 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index e1fc8b0ee27..32bea4b20de 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig index 28290296853..d7eb8c27304 100644 --- a/configs/xilinx_zynqmp_zcu102_defconfig +++ b/configs/xilinx_zynqmp_zcu102_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 92633d6fcc9..80a59ef07dd 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set diff --git a/configs/xpedite1000_defconfig b/configs/xpedite1000_defconfig index 4c0e58ec0b0..f023c730842 100644 --- a/configs/xpedite1000_defconfig +++ b/configs/xpedite1000_defconfig @@ -3,6 +3,7 @@ CONFIG_4xx=y CONFIG_TARGET_XPEDITE1000=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig index b0e92e03086..2839bc6b2a7 100644 --- a/configs/xpedite517x_defconfig +++ b/configs/xpedite517x_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig index 4a328cd2284..c3b91f4e95e 100644 --- a/configs/xpedite520x_defconfig +++ b/configs/xpedite520x_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig index e0fe947ecbf..5ababef491b 100644 --- a/configs/xpedite537x_defconfig +++ b/configs/xpedite537x_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig index e16c8c8fd11..f893abf5edc 100644 --- a/configs/xpedite550x_defconfig +++ b/configs/xpedite550x_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y diff --git a/configs/yellowstone_defconfig b/configs/yellowstone_defconfig index 00992e0c0c7..059ff711752 100644 --- a/configs/yellowstone_defconfig +++ b/configs/yellowstone_defconfig @@ -3,6 +3,7 @@ CONFIG_4xx=y CONFIG_TARGET_YOSEMITE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/yosemite_defconfig b/configs/yosemite_defconfig index 3a803f61601..df37b909b97 100644 --- a/configs/yosemite_defconfig +++ b/configs/yosemite_defconfig @@ -3,6 +3,7 @@ CONFIG_4xx=y CONFIG_TARGET_YOSEMITE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE" +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/yucca_defconfig b/configs/yucca_defconfig index e219fd2a343..d3ccad7d098 100644 --- a/configs/yucca_defconfig +++ b/configs/yucca_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_YUCCA=y CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig index 9368610f2ef..42e38da55cc 100644 --- a/configs/zmx25_defconfig +++ b/configs/zmx25_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_ZMX25=y +CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="zmx25> " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index d0b1ec9463b..d88c61bf4e4 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index 36244248667..aeb127020fd 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="zynq_picozed" CONFIG_ARCH_ZYNQ=y CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed" CONFIG_SPL=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index e1b1fc93576..d68ed0edff7 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 63d32d90ddd..8bd92305804 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 6ccbb8ce68d..81f16ec1588 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index e6c646be6e6..271fcfd5383 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index a8cfeb8988b..a9ea9711268 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_GPIO=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index f2d00cad65f..56062b18a89 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 7783eeb0f6c..c70b860b622 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 9236c5e8274..624545edaa9 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h index dfc2cbc0223..92446804526 100644 --- a/include/config_distro_defaults.h +++ b/include/config_distro_defaults.h @@ -27,7 +27,6 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE -#define CONFIG_BOOTDELAY 2 #define CONFIG_SYS_LONGHELP #define CONFIG_MENU #define CONFIG_DOS_PARTITION diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 52497518304..2c3c4ac0933 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -802,7 +802,6 @@ unsigned long get_board_ddr_clk(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index b092933757e..0a9d8a64aff 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -394,7 +394,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index aaddfca2cd7..756beec61b7 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -632,7 +632,6 @@ combinations. this should be removed later #define CONFIG_UBOOTPATH "u-boot.bin" #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */ #ifdef CONFIG_SDCARD #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 1e5b501ab1a..69a9798540e 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -517,7 +517,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index b60da5e166f..c5c3a845e41 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -27,7 +27,6 @@ #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ #define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #undef CONFIG_BOOTARGS #undef CONFIG_BOOTCOMMAND diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index b66b3ff7efd..db953b9b4ae 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -31,7 +31,6 @@ #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ #define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #undef CONFIG_BOOTARGS #undef CONFIG_BOOTCOMMAND diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 2b2e4e7a5ad..b426c18b3bf 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -59,7 +59,6 @@ #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR -#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ #define CONFIG_UDP_CHECKSUM #ifdef CONFIG_MCFFEC diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index 85b1c1544e8..1e052b1b4ba 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -82,7 +82,6 @@ "" #endif -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ /* LCD */ #ifdef CONFIG_CMD_BMP #define CONFIG_LCD diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index bacd8e0f32d..006222881ab 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -76,7 +76,6 @@ #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ #define CONFIG_BOOTFILE "u-boot.bin" #ifdef CONFIG_MCFFEC # define CONFIG_IPADDR 192.162.1.2 diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 7c06fcea39b..6c90700ccf8 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -17,7 +17,6 @@ #undef CONFIG_WATCHDOG /* disable watchdog */ -#define CONFIG_BOOTDELAY 5 /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index d14f979cdde..faad9703b7c 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -18,7 +18,6 @@ #undef CONFIG_WATCHDOG /* disable watchdog */ -#define CONFIG_BOOTDELAY 5 /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 0753dc3afad..a8589049fdf 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -57,7 +57,6 @@ * Command line configuration. */ -#define CONFIG_BOOTDELAY 5 #define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC # define CONFIG_MII 1 diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 1709cccf896..1bdacbcdf86 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -104,7 +104,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x800000 -#define CONFIG_BOOTDELAY 5 #define CONFIG_BOOTCOMMAND "bootm ffe40000" #define CONFIG_SYS_MEMTEST_START 0x400 #define CONFIG_SYS_MEMTEST_END 0x380000 diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 8131ea0ee1f..62f25e90236 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -70,7 +70,6 @@ # endif /* CONFIG_SYS_DISCOVER_PHY */ #endif -#define CONFIG_BOOTDELAY 5 #ifdef CONFIG_MCFFEC # define CONFIG_IPADDR 192.162.1.2 # define CONFIG_NETMASK 255.255.255.0 diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 81e28f09241..03c18da52e2 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -79,7 +79,6 @@ #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR -#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ #define CONFIG_UDP_CHECKSUM #ifdef CONFIG_MCFFEC diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 661063ce5d9..fabbaf084d5 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -73,7 +73,6 @@ #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR -#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ #define CONFIG_UDP_CHECKSUM #ifdef CONFIG_MCFFEC diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index f0cf715ee26..8fb16bc294b 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -73,7 +73,6 @@ #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR -#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ #define CONFIG_UDP_CHECKSUM #ifdef CONFIG_MCFFEC diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index e10c3e19294..63b0a1e0ed5 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -75,7 +75,6 @@ #define CONFIG_SYS_FEC0_PHYADDR 0 #define CONFIG_SYS_FEC1_PHYADDR 1 -#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ #ifdef CONFIG_SYS_NAND_BOOT #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 00bdbd18242..599ffc79908 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -56,7 +56,6 @@ # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE # define MCFFEC_TOUT_LOOP 50000 -# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" # define CONFIG_ETHPRIME "FEC0" # define CONFIG_IPADDR 192.162.1.2 diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index f32dd3660a2..8301c4670fb 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -61,7 +61,6 @@ # define MCFFEC_TOUT_LOOP 50000 # define CONFIG_HAS_ETH1 -# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" # define CONFIG_ETHPRIME "FEC0" # define CONFIG_IPADDR 192.162.1.2 diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index 5fa9683e2c8..ccebc30e169 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -116,7 +116,6 @@ #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 #endif -#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ #define CONFIG_UDP_CHECKSUM #ifdef CONFIG_MCFFEC diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 9a23e22bfaf..7e9f978f6b9 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -111,7 +111,6 @@ #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 #endif -#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ #define CONFIG_UDP_CHECKSUM #define CONFIG_HOSTNAME M548xEVB diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 75a26edb25b..79027e214ce 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -97,7 +97,6 @@ * Environment definitions **************************************************************/ #define CONFIG_BAUDRATE 9600 /* STD Baudrate */ -#define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index e3e3b4414d8..578325cd05e 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -514,7 +514,6 @@ #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index fda894e1198..5613a4a0cd2 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -649,7 +649,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 800000 -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 41b40cb2d18..7ce5f599373 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -602,7 +602,6 @@ #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 5c40e5b3eac..13f954d00ed 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -492,7 +492,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 800000 -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 4a1cebb5d60..fd482606ada 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -569,7 +569,6 @@ #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 3518b3fd3b0..288b126d02e 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -734,7 +734,6 @@ #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 8161903f805..2721255254f 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -731,7 +731,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" #endif -#define CONFIG_BOOTDELAY 6 #define CONFIG_BOOTARGS \ "root=/dev/nfs rw" \ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 28ed9c03b94..921d5f399d2 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -659,7 +659,6 @@ extern int board_pci_host_broken(void); #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index fa131e23fbd..bb06e89b4ea 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -679,7 +679,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 800000 -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 03f17f9c35a..7c19ff84bcc 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -706,7 +706,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 38bd38c8f9e..fae4b0c5c53 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -392,7 +392,6 @@ #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index d827d2ab0b9..0c2afb50659 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -414,7 +414,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index f3036c1dc26..b9d97c10069 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -441,7 +441,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 5de8b198288..e73be48d518 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -540,7 +540,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index c68e1d83d1d..fcd55c7743a 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -409,7 +409,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index fb76dd1aead..4ed06c9ad41 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -434,7 +434,6 @@ #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 09e32ebcd70..39459ded28f 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -433,7 +433,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 923159b9043..192cc2ccf1a 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -528,7 +528,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index bb7f38e34a5..2e6989f8160 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -646,7 +646,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index f6d45a9e40a..81594932d76 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -500,7 +500,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 9b2623c7262..f90f7f24a47 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -666,7 +666,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index f4c93128436..80d8fcdd98f 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -16,7 +16,6 @@ #define CONFIG_CMD_SDRAM #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" #define CONFIG_VERSION_VARIABLE diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 4d0855567a0..5384584c184 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -850,7 +850,6 @@ extern unsigned long get_sdram_size(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 7457dfcd489..bdf0323bfc7 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -715,7 +715,6 @@ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index a10310ec273..07a594d15db 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -308,7 +308,6 @@ extern unsigned long get_clock_freq(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b3fb38c63a4..24e54318452 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -676,7 +676,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/PATI.h b/include/configs/PATI.h index 9f3c0372378..e96fbc5aac9 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -44,11 +44,6 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_IRQ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif #define CONFIG_BOOTCOMMAND "" /* autoboot command */ #define CONFIG_BOOTARGS "" /* */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 4506d86eee7..e7c7a990f4c 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -89,7 +89,6 @@ **************************************************************/ #define CONFIG_BAUDRATE 9600 /* STD Baudrate */ -#define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 71a03756d4f..558f3e2ba6c 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -118,7 +118,6 @@ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index a622578bd2b..5f17d767443 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -21,7 +21,6 @@ #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #undef CONFIG_BOOTARGS #undef CONFIG_BOOTCOMMAND diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 005fa2a5c1a..868ca84f993 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -229,7 +229,6 @@ "cp.b 200000 fff90000 70000\0" \ "" -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index ef2ede49b9f..b1519635028 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -867,7 +867,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 #define __USB_PHY_TYPE utmi diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 778c64b3f08..06d1d0fc497 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -867,7 +867,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 #define __USB_PHY_TYPE utmi diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index be4ae712b5e..9f5063c3337 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -749,7 +749,6 @@ unsigned long get_board_ddr_clk(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index ed3493b6849..a8f4f742e62 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -832,7 +832,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index f48697c0339..1f07a83a1a7 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -821,7 +821,6 @@ unsigned long get_board_ddr_clk(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index b6be46e004f..0ded41e0dd5 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -773,7 +773,6 @@ unsigned long get_board_ddr_clk(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 276428f4df3..f075dfb5f05 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -545,7 +545,6 @@ unsigned long get_board_ddr_clk(void); (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) #endif -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define __USB_PHY_TYPE utmi diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index ab838a8036c..9ba69a1d123 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -738,7 +738,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SHA_HW_ACCEL #endif -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define __USB_PHY_TYPE utmi diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 42ebcf04d1c..0e4067a3a92 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -199,7 +199,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 395805ca04e..c557ba17787 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -37,7 +37,6 @@ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_TYPES 1 /* support board types */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index ec366370ee4..814740b71d3 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -35,7 +35,6 @@ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_TYPES 1 /* support board types */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 2aac682a2c8..90e8dd9dd9e 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -481,7 +481,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 400000 -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 00c0cc3291b..58fd8a4d71a 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -30,7 +30,6 @@ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_TYPES 1 /* support board types */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index ca2602492ec..3a4f94c83a6 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -30,7 +30,6 @@ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_TYPES 1 /* support board types */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 39cf02e4c4b..134076c73a1 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -30,7 +30,6 @@ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_TYPES 1 /* support board types */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 30bfb8afdd0..ad6f8f4bb33 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -30,7 +30,6 @@ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_TYPES 1 /* support board types */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index abe49b9c929..b935f31100f 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -30,7 +30,6 @@ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_TYPES 1 /* support board types */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 48252c4f981..79248de0157 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -30,7 +30,6 @@ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_TYPES 1 /* support board types */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index a73395a2709..d360644c02e 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -33,7 +33,6 @@ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_TYPES 1 /* support board types */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 3db6fa17404..5c6013b41f8 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -33,7 +33,6 @@ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_TYPES 1 /* support board types */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index 76c8f7a499b..c098f72c675 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -44,7 +44,6 @@ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_TYPES 1 /* support board types */ diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index 88b97ab3193..9d8a607b6fe 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -40,7 +40,6 @@ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_TYPES 1 /* support board types */ diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 4ae61ca9cde..0c9e79f4a51 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -590,7 +590,6 @@ #if defined(CONFIG_DONGLE) -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootcmd=run prog_spi_mbrbootcramfs\0" \ "bootfile=uImage\0" \ @@ -720,7 +719,6 @@ #if defined(CONFIG_UCP1020T1) -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ "bootfile=uImage\0" \ @@ -810,7 +808,6 @@ #else /* For Arcturus Modules */ -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootcmd=run norkernel\0" \ "bootfile=uImage\0" \ diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 4e349d5caa5..968e1dfd64b 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -115,7 +115,6 @@ #define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 #define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_RESET_TO_RETRY #define CONFIG_ZERO_BOOTDELAY_CHECK diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index d401d3eedb7..dde98f6e759 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -27,7 +27,6 @@ #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ #define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #undef CONFIG_BOOTARGS #undef CONFIG_BOOTCOMMAND diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index e0c92d0497b..7ec404d5484 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -321,7 +321,6 @@ * Environment Configuration */ -#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS #define CONFIG_ZERO_BOOTDELAY_CHECK diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h index ee1bff858f7..4e240c6b89d 100644 --- a/include/configs/a4m072.h +++ b/include/configs/a4m072.h @@ -107,7 +107,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ #define CONFIG_SYS_AUTOLOAD "n" diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h index f0b5b3e1883..699ac41d778 100644 --- a/include/configs/ac14xx.h +++ b/include/configs/ac14xx.h @@ -462,7 +462,6 @@ /* default load addr for tftp and bootm */ #define CONFIG_LOADADDR 400000 -#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */ /* the builtin environment and standard greeting */ #define CONFIG_PREBOOT "echo;" \ diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index 7b9470c801d..c4e0a21b8d8 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -97,7 +97,6 @@ */ #define CONFIG_FTMAC100 -#define CONFIG_BOOTDELAY 3 /* * SD (MMC) controller diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index e9e971e5116..84548725542 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -10,7 +10,6 @@ #define __CONFIG_AM335X_EVM_H #include -#undef CONFIG_BOOTDELAY #ifndef CONFIG_SPL_BUILD # define CONFIG_TIMESTAMP diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 822e1c8edc7..a65d1a884b0 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -156,7 +156,6 @@ #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ /* Environment information */ -#define CONFIG_BOOTDELAY 10 #define CONFIG_BOOTFILE "uImage" diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 6f838708682..4d88aac6375 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -200,7 +200,6 @@ #endif /* CONFIG_NAND */ /* Environment information */ -#define CONFIG_BOOTDELAY 10 #define CONFIG_BOOTFILE "uImage" diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 9fa4d162439..2666ca6f691 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -60,7 +60,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/amcore.h b/include/configs/amcore.h index e819185f77b..5667680230a 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -18,7 +18,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_BOOTDELAY 1 #define CONFIG_BOOTCOMMAND "bootm ffc20000" #undef CONFIG_CMD_AES diff --git a/include/configs/ap121.h b/include/configs/ap121.h index b01031c8bbe..bf5746fcb8b 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -34,7 +34,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ {9600, 19200, 38400, 57600, 115200} -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock2 " \ "rootfstype=squashfs" diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 0fa73a79a59..5d7e49e4a14 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -38,7 +38,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ {9600, 19200, 38400, 57600, 115200} -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock2 " \ "rootfstype=squashfs" diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h index ae58ec8d2ae..7dd24612f1a 100644 --- a/include/configs/ap325rxa.h +++ b/include/configs/ap325rxa.h @@ -19,7 +19,6 @@ #define CONFIG_DOS_PARTITION #define CONFIG_BAUDRATE 38400 -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC2,38400" #define CONFIG_VERSION_VARIABLE diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h index be8feed124e..37f2d3093a7 100644 --- a/include/configs/ap_sh4a_4a.h +++ b/include/configs/ap_sh4a_4a.h @@ -22,7 +22,6 @@ #define CONFIG_CMD_ENV #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC4,115200" #define CONFIG_VERSION_VARIABLE diff --git a/include/configs/apf27.h b/include/configs/apf27.h index 2291647c64f..f44f71cebec 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -148,7 +148,6 @@ #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ #define CONFIG_INITRD_TAG /* send initrd params */ -#define CONFIG_BOOTDELAY 5 #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin" #define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," \ diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h index bb29f3f5bca..50eaf609b53 100644 --- a/include/configs/apx4devkit.h +++ b/include/configs/apx4devkit.h @@ -93,7 +93,6 @@ #endif /* Boot Linux */ -#define CONFIG_BOOTDELAY 1 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTCOMMAND "run bootcmd_nand" #define CONFIG_LOADADDR 0x41000000 diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h index 8a860eef6ad..d6081048fee 100644 --- a/include/configs/arcangel4.h +++ b/include/configs/arcangel4.h @@ -54,7 +54,6 @@ /* * Environment configuration */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTARGS "console=ttyARC0,115200n8" #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR diff --git a/include/configs/aria.h b/include/configs/aria.h index 2d32da1f949..cb506589d96 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -510,7 +510,6 @@ #define CONFIG_LOADADDR 400000 /* default load addr */ -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 681b4e743e6..522b2871044 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -22,7 +22,6 @@ #define BOARD_LATE_INIT #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "" #define CONFIG_VERSION_VARIABLE diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index b08276f32da..e8dca0b2ccd 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -148,19 +148,6 @@ /* AUTOBOOT settings - booting images automatically by u-boot after power on */ -/* - * used for autoboot, delay in seconds u-boot will wait before starting - * defined (auto-)boot command, setting to -1 disables delay, setting to - * 0 will too prevent access to u-boot command interface: u-boot then has - * to be reflashed - * beware - watchdog is not serviced during autoboot delay time! - */ -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_BOOTDELAY 1 -#else -#define CONFIG_BOOTDELAY 1 -#endif - /* * The following settings will be contained in the environment block ; if you * want to use a neutral environment all those settings can be manually set in diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index dc955b24524..9257c5f0292 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -34,7 +34,6 @@ /* general purpose I/O */ #define CONFIG_AT91_GPIO -#define CONFIG_BOOTDELAY 3 /* * BOOTP options diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index 2979b25abcc..c92ad852380 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -171,7 +171,6 @@ /* * Boot option */ -#define CONFIG_BOOTDELAY 3 /* default load address */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 9db8d128688..c6d3295f34f 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -61,7 +61,6 @@ #define CONFIG_RED_LED AT91_PIN_PA9 /* this is the power led */ #define CONFIG_GREEN_LED AT91_PIN_PA6 /* this is the user led */ -#define CONFIG_BOOTDELAY 3 /* * BOOTP options diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index b369624a2c7..9c9461bc98f 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -69,7 +69,6 @@ #define CONFIG_GREEN_LED AT91_PIN_PA13 /* this is the user1 led */ #define CONFIG_YELLOW_LED AT91_PIN_PA14 /* this is the user2 led */ -#define CONFIG_BOOTDELAY 3 /* * BOOTP options diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index f248049e544..e7bfd494504 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -76,7 +76,6 @@ #define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */ #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */ -#define CONFIG_BOOTDELAY 3 /* * BOOTP options diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 18eb01dc8c6..290b039e11e 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -59,7 +59,6 @@ #define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ #define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */ -#define CONFIG_BOOTDELAY 3 /* * BOOTP options diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 2f8c3774139..297938b93e7 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -51,7 +51,6 @@ #define CONFIG_ATMEL_LCD_RGB565 #define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_BOOTDELAY 3 /* * BOOTP options diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index d178d9d44b4..a383de64bc3 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -65,7 +65,6 @@ #define CONFIG_GREEN_LED AT91_PIN_PD15 /* this is the user1 led */ #define CONFIG_YELLOW_LED AT91_PIN_PD16 /* this is the user2 led */ -#define CONFIG_BOOTDELAY 3 /* * Command line configuration. diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 251094e60b8..743fc397d14 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -47,7 +47,6 @@ #define CONFIG_ATMEL_LCD_RGB565 #define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_BOOTDELAY 3 /* * BOOTP options diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index e6f6125dd2c..a0f451b1a05 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -62,7 +62,6 @@ #define CONFIG_BOOTCOMMAND \ "fsload; bootm" -#define CONFIG_BOOTDELAY 1 /* * After booting the board for the first time, new ethernet addresses diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index dfa2d93a90d..4d9282a7bf8 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -81,7 +81,6 @@ #define CONFIG_BOOTCOMMAND \ "fsload 0x10400000 /uImage; bootm" -#define CONFIG_BOOTDELAY 1 /* * After booting the board for the first time, new ethernet addresses diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 9a647d8446f..9ddfff2b2c4 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -79,7 +79,6 @@ #define CONFIG_BOOTCOMMAND \ "fsload; bootm $(fileaddr)" -#define CONFIG_BOOTDELAY 1 /* * After booting the board for the first time, new ethernet addresses diff --git a/include/configs/axs101.h b/include/configs/axs101.h index 05d2d45b251..c0b68e22775 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -119,7 +119,6 @@ /* * Environment configuration */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTARGS "console=ttyS3,115200n8" #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h index e95deac7378..de60bb10358 100644 --- a/include/configs/bct-brettl2.h +++ b/include/configs/bct-brettl2.h @@ -117,7 +117,6 @@ /* * Misc Settings */ -#define CONFIG_BOOTDELAY 1 #define CONFIG_LOADADDR 0x800000 #define CONFIG_MISC_INIT_R #define CONFIG_UART_CONSOLE 0 diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h index 66339ca9718..f7a45e9fdd2 100644 --- a/include/configs/bf525-ucr2.h +++ b/include/configs/bf525-ucr2.h @@ -85,7 +85,6 @@ #define CONFIG_BFIN_SERIAL #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" #define CONFIG_BOOTCOMMAND "run sfboot" -#define CONFIG_BOOTDELAY 5 #define CONFIG_EXTRA_ENV_SETTINGS \ "sfboot=sf probe 1;" \ "sf read 0x1000000 0x20000 0x300000;" \ diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h index 43a90328fed..2c7972043a6 100644 --- a/include/configs/bf537-minotaur.h +++ b/include/configs/bf537-minotaur.h @@ -129,12 +129,6 @@ #define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_LOADS_ECHO 1 -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) -# define CONFIG_BOOTDELAY -1 -#else -# define CONFIG_BOOTDELAY 5 -#endif - #define CONFIG_CMD_BOOTLDR #define CONFIG_CMD_DATE diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h index 70553662e7f..6ad5682a19e 100644 --- a/include/configs/bf537-srv1.h +++ b/include/configs/bf537-srv1.h @@ -129,15 +129,6 @@ #define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_LOADS_ECHO 1 -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) -# define CONFIG_BOOTDELAY -1 -#else -# define CONFIG_BOOTDELAY 5 -#endif - -#ifdef CONFIG_BFIN_MAC -#endif - #define CONFIG_CMD_BOOTLDR #define CONFIG_CMD_DATE diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 88d2ae997ea..13076072e46 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -99,9 +99,7 @@ */ #ifndef CONFIG_BOOTDELAY # if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) -# define CONFIG_BOOTDELAY -1 # else -# define CONFIG_BOOTDELAY 5 # endif #endif #ifndef CONFIG_BOOTCOMMAND diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h index 6a5bc126b07..e13f736a8f4 100644 --- a/include/configs/bg0900.h +++ b/include/configs/bg0900.h @@ -55,7 +55,6 @@ #endif /* Boot Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTARGS "console=ttyAMA0,115200" #define CONFIG_BOOTCOMMAND "bootm" diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h index 6eb83a05a7e..dc596fae3ec 100644 --- a/include/configs/blackstamp.h +++ b/include/configs/blackstamp.h @@ -106,7 +106,6 @@ #define CONFIG_CMD_CPLBINFO #define CONFIG_CMD_DATE -#define CONFIG_BOOTDELAY 5 #define CONFIG_BOOTCOMMAND "run ramboot" #define CONFIG_BOOTARGS \ "root=/dev/mtdblock0 rw " \ diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h index ba90830a1e6..d3dc216c5f0 100644 --- a/include/configs/blackvme.h +++ b/include/configs/blackvme.h @@ -155,7 +155,6 @@ * Default: boot from SPI flash. * "sfboot" is a composite command defined in extra settings */ -#define CONFIG_BOOTDELAY 5 #define CONFIG_BOOTCOMMAND "run sfboot" /* diff --git a/include/configs/br4.h b/include/configs/br4.h index 402f352fc56..16e4a1d4e2c 100644 --- a/include/configs/br4.h +++ b/include/configs/br4.h @@ -119,7 +119,6 @@ #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 #define CONFIG_BOOTCOMMAND "run nandboot" -#define CONFIG_BOOTDELAY 2 #define CONFIG_LOADADDR 0x2000000 /* diff --git a/include/configs/calimain.h b/include/configs/calimain.h index 506ad882c8e..3b10360b5e3 100644 --- a/include/configs/calimain.h +++ b/include/configs/calimain.h @@ -214,7 +214,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTARGS "" #define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;" -#define CONFIG_BOOTDELAY 0 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */ #define CONFIG_RESET_TO_RETRY diff --git a/include/configs/canmb.h b/include/configs/canmb.h index 31fe5f6b814..b41666064cf 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -65,7 +65,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index 99182f4de39..0dd5e996b66 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -64,7 +64,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \ "echo" diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 0fb853002c0..de1999d431e 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -145,7 +145,6 @@ /* devices */ /* Environment information */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index 7c087c6f5d1..87e41bfabab 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -152,7 +152,6 @@ /* devices */ /* Environment information */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h index ff63d7a7756..68851ee90fd 100644 --- a/include/configs/cm_t54.h +++ b/include/configs/cm_t54.h @@ -108,9 +108,7 @@ #undef CONFIG_SYS_AUTOLOAD #undef CONFIG_EXTRA_ENV_SETTINGS #undef CONFIG_BOOTCOMMAND -#undef CONFIG_BOOTDELAY -#define CONFIG_BOOTDELAY 3 #define CONFIG_SYS_AUTOLOAD "no" #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 509c8b42fba..4396698b7f1 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -149,7 +149,6 @@ /*AUTOBOOT settings - booting images automatically by u-boot after power on*/ -#define CONFIG_BOOTDELAY 5 /* used for autoboot, delay in seconds u-boot will wait before starting defined (auto-)boot command, setting to -1 disables delay, setting to 0 will too prevent access to u-boot command interface: u-boot then has to reflashed */ diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 5dffc9e186e..ba8d93ce1ff 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -37,7 +37,6 @@ "bootm 0xc0000;" #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" #define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_LZMA /* LZMA compression support */ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 50f7c21ac2b..58925952ddd 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -89,7 +89,6 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 -#define CONFIG_BOOTDELAY 1 #define CONFIG_BOARD_LATE_INIT #define CONFIG_LOADADDR 0x80008000 diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index c60c6443936..30c283185bc 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -417,7 +417,6 @@ #ifdef CONFIG_TRAILBLAZER -#define CONFIG_BOOTDELAY 0 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -432,7 +431,6 @@ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index a06bfe05adb..4a770b05460 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -682,7 +682,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 8b3c7153f02..686760d0a53 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -54,7 +54,6 @@ #define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ #define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */ -#define CONFIG_BOOTDELAY 3 /* * BOOTP options diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 660646eb918..708d5f730dd 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -505,7 +505,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index af220febf49..3e4bba55872 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -278,7 +278,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTARGS \ "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" -#define CONFIG_BOOTDELAY 3 #define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes" /* diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index 68ff02509b5..dbd2bb3b094 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -37,7 +37,6 @@ #endif #endif -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 913b9481f23..73f53d4a2b8 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -179,7 +179,6 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_BOOTDELAY 1 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTARGS "console=ttyS0,115200n8" diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index 18804d43fd8..1145e376397 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -117,7 +117,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 1 #undef CONFIG_BOOTARGS diff --git a/include/configs/draco.h b/include/configs/draco.h index 8aee25b96a2..5d866c48685 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -82,7 +82,6 @@ #ifndef CONFIG_RESTORE_FLASH /* set to negative value for no autoboot */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND \ "if dfubutton; then " \ @@ -94,7 +93,6 @@ "reset;" #else -#define CONFIG_BOOTDELAY 0 #define CONFIG_BOOTCOMMAND \ "setenv autoload no; " \ diff --git a/include/configs/ea20.h b/include/configs/ea20.h index d4f3cfa8e9f..3f8578fd58e 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -137,7 +137,6 @@ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTDELAY 3 /* * U-Boot commands diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 521e3cf335c..6d469a383c6 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -69,7 +69,6 @@ #define CONFIG_MCFTMR -#define CONFIG_BOOTDELAY 5 #define CONFIG_SYS_LONGHELP 1 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ diff --git a/include/configs/eco5pk.h b/include/configs/eco5pk.h index bb5d7e581ed..c7b0a389c91 100644 --- a/include/configs/eco5pk.h +++ b/include/configs/eco5pk.h @@ -31,7 +31,6 @@ #define MACH_TYPE_ECO5_PK 4017 #define CONFIG_MACH_TYPE MACH_TYPE_ECO5_PK -#define CONFIG_BOOTDELAY 10 #define CONFIG_BOOTFILE "uImage" #define CONFIG_AUTO_COMPLETE diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h index 2ac7757b0cf..706ad1d2a3a 100644 --- a/include/configs/ecovec.h +++ b/include/configs/ecovec.h @@ -37,7 +37,6 @@ #define CONFIG_DOS_PARTITION #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_VERSION_VARIABLE diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h index 174cdf33024..f3f75496889 100644 --- a/include/configs/edb93xx.h +++ b/include/configs/edb93xx.h @@ -26,7 +26,6 @@ #endif /* Initial environment and monitor configuration options. */ -#define CONFIG_BOOTDELAY 2 #define CONFIG_CMDLINE_TAG 1 #define CONFIG_INITRD_TAG 1 #define CONFIG_SETUP_MEMORY_TAGS 1 diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 99d16b06c09..f9d4683fcbe 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -115,7 +115,6 @@ #define CONFIG_SYS_FLASH_BASE 0xfff80000 /* auto boot */ -#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ /* * For booting Linux, the board info and command line data diff --git a/include/configs/espt.h b/include/configs/espt.h index 3d673764980..86e726c63c5 100644 --- a/include/configs/espt.h +++ b/include/configs/espt.h @@ -20,7 +20,6 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_ENV -#define CONFIG_BOOTDELAY -1 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" #define CONFIG_ENV_OVERWRITE 1 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 94fee54ccd1..bd32cdbf735 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -205,7 +205,6 @@ #define CONFIG_RBTREE /* Boot command */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/flea3.h b/include/configs/flea3.h index 7400870b214..824aca45b64 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -81,7 +81,6 @@ #define CONFIG_NET_RETRY_COUNT 100 -#define CONFIG_BOOTDELAY 3 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 13048798765..42771b51d44 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -36,7 +36,6 @@ #define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_BOOTDELAY 1 #include "mx6_common.h" #include diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h index e6b7953c929..8b573545cd8 100644 --- a/include/configs/gr_cpci_ax2000.h +++ b/include/configs/gr_cpci_ax2000.h @@ -65,7 +65,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h index 956c0e27bda..4e7819912d7 100644 --- a/include/configs/gr_ep2s60.h +++ b/include/configs/gr_ep2s60.h @@ -67,7 +67,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h index 908d545070f..36acf016319 100644 --- a/include/configs/gr_xc3s_1500.h +++ b/include/configs/gr_xc3s_1500.h @@ -46,7 +46,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h index 83f1d73087a..f1afdedb3c0 100644 --- a/include/configs/grasshopper.h +++ b/include/configs/grasshopper.h @@ -74,7 +74,6 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 1 /* * After booting the board for the first time, new ethernet addresses diff --git a/include/configs/grsim.h b/include/configs/grsim.h index 6a889015a36..c2656fbeb28 100644 --- a/include/configs/grsim.h +++ b/include/configs/grsim.h @@ -58,7 +58,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h index 0ebded6bd28..59adbdc1028 100644 --- a/include/configs/grsim_leon2.h +++ b/include/configs/grsim_leon2.h @@ -53,7 +53,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ diff --git a/include/configs/h2200.h b/include/configs/h2200.h index 3d510d6d887..3e419c64459 100644 --- a/include/configs/h2200.h +++ b/include/configs/h2200.h @@ -135,7 +135,6 @@ #define CONFIG_USB_DEV_PULLUP_GPIO 33 /* USB VBUS GPIO 3 */ -#define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTCOMMAND \ "setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \ "if bootp ; then setenv downloaded 1 ; fi ; done ; " \ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 9f02a654c3b..6a8660b0880 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -621,7 +621,6 @@ void fpga_control_clear(unsigned int bus, int pin); #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ #define CONFIG_HOSTNAME hrcon #define CONFIG_ROOTPATH "/opt/nfsroot" diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 04515ba80a6..b750d72d35b 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -25,7 +25,6 @@ #define CONFIG_BOOT_RETRY_TIME 900 #define CONFIG_BOOT_RETRY_MIN 30 -#define CONFIG_BOOTDELAY 1 #define CONFIG_RESET_TO_RETRY #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index b8ee44d8681..80628ddaf3c 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -175,7 +175,6 @@ #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NAND -#define CONFIG_BOOTDELAY 5 #define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 94fc0775398..50dfc115235 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -54,7 +54,6 @@ ***********************************************************/ #define CONFIG_CMD_EEPROM -#define CONFIG_BOOTDELAY 3 #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro," \ "1536k(kernel),-(root)" diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 0d4f2925cd4..3420a39adee 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -92,7 +92,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ #define CONFIG_PREBOOT "echo;" \ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index a5a88197272..e7d058f7a84 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -31,7 +31,6 @@ /* * Command line configuration. */ -#define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAM0 console=tty" #define CONFIG_BOOTCOMMAND "" diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index af69ad99c4c..d0b6af8cadc 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -31,7 +31,6 @@ /* * Command line configuration. */ -#define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" #define CONFIG_BOOTCOMMAND "tftpboot ; bootm" #define CONFIG_SERVERIP 192.168.1.100 diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h index b2a6e7fb056..b36b75dfb68 100644 --- a/include/configs/ipam390.h +++ b/include/configs/ipam390.h @@ -223,7 +223,6 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_REVISION_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTDELAY 2 #define CONFIG_EXTRA_ENV_SETTINGS \ "defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \ "root=/dev/mtdblock5 rw noinitrd " \ diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h index 55ed6569ef8..eb4e3aea386 100644 --- a/include/configs/ipek01.h +++ b/include/configs/ipek01.h @@ -115,7 +115,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 062820305dd..65f53b76125 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -92,7 +92,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 9f76034e61a..6f2773b88c1 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -21,7 +21,6 @@ #undef CONFIG_WATCHDOG /* disable platform specific watchdog */ -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ /* diff --git a/include/configs/kwb.h b/include/configs/kwb.h index bcb9e7e8be0..2bddc6b7df8 100644 --- a/include/configs/kwb.h +++ b/include/configs/kwb.h @@ -103,7 +103,6 @@ BUR_COMMON_ENV \ #define CONFIG_BOOTCOMMAND \ "run usbscript;" -#define CONFIG_BOOTDELAY 0 /* undefine command which we not need here */ #undef CONFIG_BOOTM_NETBSD diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 710629b6bd9..1b4c7d43889 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -31,7 +31,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200" -#define CONFIG_BOOTDELAY 3 #define CONFIG_VERSION_VARIABLE #undef CONFIG_SHOW_BOOT_PROGRESS diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 1aad97d970b..f52750e591b 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -168,7 +168,6 @@ #define CONFIG_SERIAL_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_SETUP_INITRD_TAG -#define CONFIG_BOOTDELAY 0 #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_BOOTCOMMAND \ "if mmc rescan; then " \ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index ccd94ec952c..fba2facfbde 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -125,7 +125,6 @@ #define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ "$kernel_start $kernel_size && "\ "bootm $kernel_load" -#define CONFIG_BOOTDELAY 10 /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 1edf798e32d..db684d25582 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -567,7 +567,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_DEVICE_DISABLE -#define CONFIG_BOOTDELAY 3 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 30f5655dcb8..0fb28eff557 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -416,7 +416,6 @@ #define CONFIG_FSL_DEVICE_DISABLE -#define CONFIG_BOOTDELAY 3 #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index a7d49ed6e84..b0d4a8d10ac 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -264,7 +264,6 @@ #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" #endif -#define CONFIG_BOOTDELAY 10 /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index c78aeb57ed4..2bf524f69af 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -255,7 +255,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ " cp.b $kernel_start $kernel_load" \ " $kernel_size && bootm $kernel_load" -#define CONFIG_BOOTDELAY 10 /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index d5082fa4ccf..0abfb00ef0b 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -340,7 +340,6 @@ "" #define CONFIG_BOOTCOMMAND "run flash_self" -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 428128d2977..e7fd6395e09 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -130,7 +130,6 @@ #endif /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " #define CONFIG_BOOTCOMMAND "run mmc_mmc" diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index 4349357b540..781a1623dde 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -226,7 +226,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttymxc1,115200" #define CONFIG_LOADADDR 0x70800000 diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h index fb144637d58..b4bd6b0e1ec 100644 --- a/include/configs/ma5d4evk.h +++ b/include/configs/ma5d4evk.h @@ -128,7 +128,6 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttyS3,115200" #define CONFIG_LOADADDR 0x20800000 diff --git a/include/configs/manroland/common.h b/include/configs/manroland/common.h index 8d4a8cd0c2d..937febea214 100644 --- a/include/configs/manroland/common.h +++ b/include/configs/manroland/common.h @@ -37,7 +37,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 3dbd9204af6..0c6e1117d4f 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -149,7 +149,6 @@ #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ /* Environment information */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index 9262f720853..4211e72dbaf 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -362,7 +362,6 @@ #define CONFIG_LOADADDR 400000 /* def. location for tftp and bootm */ -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_PREBOOT "echo;" \ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index f71b66245fa..fbcad4ac808 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -69,7 +69,6 @@ #define CONFIG_USART_ID ATMEL_ID_SYS #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 801d6746100..93fb166665e 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -239,7 +239,6 @@ /* default load address */ #define CONFIG_SYS_LOAD_ADDR 0 -#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ #define CONFIG_BOOTARGS "root=romfs" #define CONFIG_HOSTNAME XILINX_BOARD_NAME #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 62919e9cf92..2a83c608b1c 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -63,7 +63,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ #undef CONFIG_BOOTARGS #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index e0c9a98de75..3cdd0dcf62d 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -516,7 +516,6 @@ #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 66e1a45e166..57cb7956a46 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -474,7 +474,6 @@ #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index f983f2d1b50..27e9c0a8f3f 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -16,7 +16,6 @@ #define CONFIG_CMD_SDRAM #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" #define CONFIG_VERSION_VARIABLE diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h index 025a4a66985..c0fb16d0952 100644 --- a/include/configs/ms7750se.h +++ b/include/configs/ms7750se.h @@ -23,7 +23,6 @@ #define CONFIG_CONS_SCIF1 1 #define CONFIG_BOARD_LATE_INIT -#define CONFIG_BOOTDELAY -1 #define CONFIG_BOOTARGS "console=ttySC0,38400" #define CONFIG_ENV_OVERWRITE 1 diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h index 3073db9ff8f..29564d758b0 100644 --- a/include/configs/mt_ventoux.h +++ b/include/configs/mt_ventoux.h @@ -22,7 +22,6 @@ #define MACH_TYPE_AM3517_MT_VENTOUX 3832 #define CONFIG_MACH_TYPE MACH_TYPE_AM3517_MT_VENTOUX -#define CONFIG_BOOTDELAY 10 #define CONFIG_BOOTFILE "uImage" #define CONFIG_AUTO_COMPLETE diff --git a/include/configs/munices.h b/include/configs/munices.h index efbd44779eb..3e4c062dbfc 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -41,7 +41,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #undef CONFIG_BOOTARGS #define CONFIG_PREBOOT "echo;" \ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 6d4bbd1f9a7..62f4937c662 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -57,7 +57,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200,230400, 460800, 921600 } /* auto boot */ -#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ #define CONFIG_PREBOOT /* diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index 1bdbe4bba98..774725871ac 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -57,7 +57,6 @@ #endif /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 542f1f42b88..3f9bb0ab466 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -56,7 +56,6 @@ #endif /* Boot Linux */ -#define CONFIG_BOOTDELAY 1 #define CONFIG_BOOTFILE "uImage" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index c63887bb8c7..ea0d605fe35 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -117,7 +117,6 @@ /* Ethernet Configs */ -#define CONFIG_BOOTDELAY 1 #define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index b3c03b3bb3d..068596f397f 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -137,7 +137,6 @@ #endif /* Boot Linux */ -#define CONFIG_BOOTDELAY 1 #define CONFIG_BOOTFILE "uImage" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index b9992deaab7..8de9dec66f8 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -64,7 +64,6 @@ ***********************************************************/ #define CONFIG_CMD_DATE -#define CONFIG_BOOTDELAY 3 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 3f63007819a..a81dd784c99 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -84,7 +84,6 @@ #define CONFIG_BOARD_LATE_INIT -#define CONFIG_BOOTDELAY 1 #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index aed0939ce60..1d1178798ef 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -91,7 +91,6 @@ #define CONFIG_DOS_PARTITION #define CONFIG_EFI_PARTITION -#define CONFIG_BOOTDELAY 1 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 23b8b46d8c6..93ad048b118 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -120,7 +120,6 @@ #define CONFIG_CMD_DATE -#define CONFIG_BOOTDELAY 1 #define CONFIG_ETHPRIME "FEC0" diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index e6972612482..0419050354a 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -70,7 +70,6 @@ #define CONFIG_BAUDRATE 115200 /* Command definition */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_ETHPRIME "smc911x" diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index feb55802398..5e1c5977eaf 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -77,7 +77,6 @@ #define CONFIG_BAUDRATE 115200 /* Command definition */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_ETHPRIME "FEC0" diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 8743ddce683..1b580f04c71 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -87,7 +87,6 @@ /* Command definition */ #define CONFIG_SUPPORT_RAW_INITRD -#define CONFIG_BOOTDELAY 1 #define CONFIG_ETHPRIME "FEC0" diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index 9c76678b1c4..632ebba35c0 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -64,7 +64,6 @@ #define CONFIG_BAUDRATE 115200 /* Command definition */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_ETHPRIME "FEC0" diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 17b6c48c1c6..27f38f497e4 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -60,7 +60,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #ifndef CONFIG_BOOTDELAY -#define CONFIG_BOOTDELAY 3 #endif /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 3c9a794f81f..5e5656d4806 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -35,7 +35,6 @@ #define CONFIG_SYS_TEXT_BASE 0x87800000 #ifndef CONFIG_BOOTDELAY -#define CONFIG_BOOTDELAY 3 #endif /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 0fbbce6d029..cd154a4bbb3 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -379,7 +379,6 @@ int rx51_kp_getc(struct stdio_dev *sdev); "run attachboot;" \ "echo" -#define CONFIG_BOOTDELAY 30 #define CONFIG_MENU #define CONFIG_MENU_SHOW diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h index 16fa046687a..891378420e0 100644 --- a/include/configs/o2dnt-common.h +++ b/include/configs/o2dnt-common.h @@ -90,7 +90,6 @@ #error "CONFIG_SYS_TEXT_BASE value is invalid" #endif -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "run master" diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h index 3f777b6aebc..96c3c4b958d 100644 --- a/include/configs/omap3_cairo.h +++ b/include/configs/omap3_cairo.h @@ -74,8 +74,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ /* override default CONFIG_BOOTDELAY */ -#undef CONFIG_BOOTDELAY -#define CONFIG_BOOTDELAY 0 #define CONFIG_EXTRA_ENV_SETTINGS \ "machid=ffffffff\0" \ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 9dbca1c6f4d..1726a3ed198 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -106,7 +106,6 @@ * Default environment * ----------------------------------------------------------------------------- */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h index a93a2fa0d6b..b7d8765db5c 100644 --- a/include/configs/omap3_evm_quick_mmc.h +++ b/include/configs/omap3_evm_quick_mmc.h @@ -55,7 +55,6 @@ * Default environment * ----------------------------------------------------------------------------- */ -#define CONFIG_BOOTDELAY 0 #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h index bb908fad3ea..da5d32517d2 100644 --- a/include/configs/omap3_evm_quick_nand.h +++ b/include/configs/omap3_evm_quick_nand.h @@ -45,7 +45,6 @@ * Default environment * ----------------------------------------------------------------------------- */ -#define CONFIG_BOOTDELAY 0 #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index f3287e3ad3c..1f36d36f45c 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -204,7 +204,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTARGS "console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off" #define CONFIG_BOOTCOMMAND "if mmc rescan 0; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi" -#define CONFIG_BOOTDELAY 3 /* * U-Boot commands diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 71b2fa9c074..4f22d12a3f2 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -944,7 +944,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 9b75afe92a5..30bfbf44f5c 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -468,7 +468,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index b907419a598..a649991d1a6 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -31,7 +31,6 @@ #endif #endif -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h index 0007c50ad99..80d5d6c858e 100644 --- a/include/configs/pcm030.h +++ b/include/configs/pcm030.h @@ -70,7 +70,6 @@ Serial console configuration /*----------------------------------------------------------------------------- Autobooting -----------------------------------------------------------------------------*/ -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */ /* even with bootdelay=0 */ #undef CONFIG_BOOTARGS diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 494524d0650..74e22db1512 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -113,7 +113,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_EEPROM_BUS 2 -#define CONFIG_BOOTDELAY 3 #define CONFIG_LOADADDR 0x82000000 diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h index 3b6c7dc111c..6d03d6908ef 100644 --- a/include/configs/pdm360ng.h +++ b/include/configs/pdm360ng.h @@ -448,7 +448,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 400000 -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ #define CONFIG_PREBOOT "echo;" \ "echo PDM360NG SAMPLE;" \ diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 319e3b5111e..49c98d81c46 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -125,7 +125,6 @@ * Board boot configuration */ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_BOOTDELAY 5 #define MEM_LAYOUT_ENV_SETTINGS \ "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h index 44ffd6d2044..7d7315ea1c8 100644 --- a/include/configs/picosam9g45.h +++ b/include/configs/picosam9g45.h @@ -61,7 +61,6 @@ #define CONFIG_AT91_LED #define CONFIG_GREEN_LED AT91_PIN_PD31 /* this is the user1 led */ -#define CONFIG_BOOTDELAY 3 /* * BOOTP options diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 39af5c02400..0abd84a1470 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -168,7 +168,6 @@ #define CONFIG_GREEN_LED GPIO_PIN_PC(13) #define CONFIG_YELLOW_LED GPIO_PIN_PC(15) -#define CONFIG_BOOTDELAY 3 /* * BOOTP options diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 111e0f50cd5..b8ce17e807d 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -182,7 +182,6 @@ #define CONFIG_RED_LED GPIO_PIN_PB(7) /* this is the power led */ #define CONFIG_GREEN_LED GPIO_PIN_PB(8) /* this is the user1 led */ -#define CONFIG_BOOTDELAY 3 /* * BOOTP options diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index facba3864da..0e944d871ff 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -57,7 +57,6 @@ #define CONFIG_RED_LED GPIO_PIN_PD(31) /* this is the user1 led */ #define CONFIG_GREEN_LED GPIO_PIN_PD(0) /* this is the user2 led */ -#define CONFIG_BOOTDELAY 3 /* * BOOTP options diff --git a/include/configs/pr1.h b/include/configs/pr1.h index 9b394ddb138..6804acb0cdf 100644 --- a/include/configs/pr1.h +++ b/include/configs/pr1.h @@ -119,7 +119,6 @@ #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 #define CONFIG_BOOTCOMMAND "run nandboot" -#define CONFIG_BOOTDELAY 2 #define CONFIG_LOADADDR 0x2000000 /* diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 7450a1a42ac..794650a51cb 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -92,7 +92,6 @@ #ifndef CONFIG_RESTORE_FLASH /* set to negative value for no autoboot */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND \ "if dfubutton; then " \ @@ -118,7 +117,6 @@ "reset;" #else -#define CONFIG_BOOTDELAY 0 #define CONFIG_BOOTCOMMAND \ "setenv autoload no; " \ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index f58fc4c3779..546c508d270 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -17,7 +17,6 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_R -#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index 2190d162007..6cab7192037 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -17,7 +17,6 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_R -#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 73b377155cf..0b8640223f4 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -179,7 +179,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 1 #define CONFIG_BOOTCOMMAND \ "test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0" diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h index 437ea92a981..c5e57244ab8 100644 --- a/include/configs/r0p7734.h +++ b/include/configs/r0p7734.h @@ -22,7 +22,6 @@ #define CONFIG_CMD_ENV #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC3,115200" #define CONFIG_VERSION_VARIABLE diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index bf81d2b0ee4..1fc919b6eb4 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -22,7 +22,6 @@ #define CONFIG_CONS_SCIF1 1 #define CONFIG_BOARD_LATE_INIT -#define CONFIG_BOOTDELAY -1 #define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_ENV_OVERWRITE 1 diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index 6097dc2ca86..c15580c582b 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -28,7 +28,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_CONS_SCIF0 1 -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_ENV_OVERWRITE 1 diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 47d23791c01..6c8681ab4a0 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -85,7 +85,6 @@ #ifndef CONFIG_RESTORE_FLASH /* set to negative value for no autoboot */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND \ "if dfubutton; then " \ @@ -97,7 +96,6 @@ "reset;" #else -#define CONFIG_BOOTDELAY 0 #define CONFIG_BOOTCOMMAND \ "setenv autoload no; " \ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 337ba02a63f..80313fc8c57 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -31,7 +31,6 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_BAUDRATE 38400 -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "" #define CONFIG_VERSION_VARIABLE diff --git a/include/configs/redwood.h b/include/configs/redwood.h index 622b7c79e64..72fbf108fa4 100644 --- a/include/configs/redwood.h +++ b/include/configs/redwood.h @@ -132,7 +132,6 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_IBM_EMAC4_V4 1 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 9ef5eae304e..dbbb81efa99 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -214,6 +214,5 @@ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV -#define CONFIG_BOOTDELAY 2 #endif diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h index c60e233e9f7..3f9fb7bc028 100644 --- a/include/configs/rsk7264.h +++ b/include/configs/rsk7264.h @@ -17,7 +17,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC3,115200" -#define CONFIG_BOOTDELAY 3 #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h index b4fbc9c17db..b7f361be254 100644 --- a/include/configs/rsk7269.h +++ b/include/configs/rsk7269.h @@ -16,7 +16,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC7,115200" -#define CONFIG_BOOTDELAY 3 #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } #define CONFIG_SYS_LONGHELP /* undef to save memory */ diff --git a/include/configs/rut.h b/include/configs/rut.h index bf2cc2f2bbf..b0dcbd8c5a4 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -85,7 +85,6 @@ #ifndef CONFIG_RESTORE_FLASH /* set to negative value for no autoboot */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND \ "if mmc rescan; then " \ @@ -107,7 +106,6 @@ "reset;" #else -#define CONFIG_BOOTDELAY 0 #define CONFIG_BOOTCOMMAND \ "setenv autoload no; " \ diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h index 0c8ecc181bc..d58b9637f17 100644 --- a/include/configs/sansa_fuze_plus.h +++ b/include/configs/sansa_fuze_plus.h @@ -28,7 +28,6 @@ #define CONFIG_ENV_OVERWRITE /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " #define CONFIG_LOADADDR 0x42000000 diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 6c0932a8dfd..567c4d588b4 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -641,7 +641,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 800000 -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index bbd1a633440..46766a67797 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -579,7 +579,6 @@ #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index c9970f1f3e2..248785db381 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -527,7 +527,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h index 42237d373e9..b490b62c2dc 100644 --- a/include/configs/sc_sps_1.h +++ b/include/configs/sc_sps_1.h @@ -52,7 +52,6 @@ #endif /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTARGS "console=ttyAMA0,115200" #define CONFIG_BOOTCOMMAND "bootm" diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index 80997a49bd9..fb6e05fafc6 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -24,7 +24,6 @@ #define CONFIG_MAC_PARTITION #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" #define CONFIG_VERSION_VARIABLE diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index 248435b9d17..64e9e52e701 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -24,7 +24,6 @@ #define CONFIG_MAC_PARTITION #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" #define CONFIG_VERSION_VARIABLE diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index 547b5003083..f9a9a03ef48 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -24,7 +24,6 @@ #define CONFIG_MAC_PARTITION #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" #define CONFIG_VERSION_VARIABLE diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index 9f1e6d7fee7..538ba98ae5d 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -20,7 +20,6 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_JFFS2 -#define CONFIG_BOOTDELAY -1 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01" #define CONFIG_ENV_OVERWRITE 1 diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h index bd4c6bd13a9..794c48c49a2 100644 --- a/include/configs/sh7785lcr.h +++ b/include/configs/sh7785lcr.h @@ -22,7 +22,6 @@ #define CONFIG_MAC_PARTITION #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp" #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 40b0cd2132c..fc4153aba84 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -178,7 +178,6 @@ #endif /* General Boot Parameter */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND "run flashboot" #define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_PBSIZE \ diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index c5c0c2cb962..f733c350243 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -80,7 +80,6 @@ #define CONFIG_CMDLINE_EDITING /* autoboot */ -#define CONFIG_BOOTDELAY 5 #define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_RESET_TO_RETRY #define CONFIG_ZERO_BOOTDELAY_CHECK diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 0f1a1ecc294..fe41d17149d 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -71,7 +71,6 @@ #define CONFIG_CMD_ONENAND #define CONFIG_CMD_MTDPARTS -#define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 16aefc25b46..7981a8d80ba 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -117,7 +117,6 @@ /* Boot options */ #define CONFIG_SYS_LOAD_ADDR 0x23000000 -#define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_BOOTP_BOOTFILESIZE diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index ca7f8a28b27..3b0b41612da 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -18,7 +18,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "zImage" #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index a2da7d47c52..7ced6a68a6c 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -18,7 +18,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "zImage" #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index fdddfa3cd24..6b9546e8f75 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -18,7 +18,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index f0fb43a82f3..d1b31c4cfa3 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -18,7 +18,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */ /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) #define CONFIG_PREBOOT "run try_bootscript" diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 675f5d16e93..3fceb31df98 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -18,7 +18,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h index 79c16ce91d0..c9473df9123 100644 --- a/include/configs/socfpga_socrates.h +++ b/include/configs/socfpga_socrates.h @@ -18,7 +18,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */ /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "zImage" #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index c097f47edd4..286e746a149 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -20,7 +20,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 1ccde1a76fe..1c7d45e4a8f 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -21,7 +21,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */ /* Booting Linux */ -#define CONFIG_BOOTDELAY 5 #define CONFIG_BOOTFILE "openwrt-socfpga-socfpga_cyclone5_vining_fpga-fit-uImage.itb" #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) #define CONFIG_BOOTCOMMAND "run selboot" diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 4ed524b0236..624cef712df 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -346,7 +346,6 @@ #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ -#define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */ #define CONFIG_PREBOOT "echo;" \ "echo Welcome on the ABB Socrates Board;" \ diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 7b2d262b4bb..43ba84ab588 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -104,12 +104,6 @@ /* * Default Environment Varible definitions */ -#if defined(CONFIG_SPEAR_USBTTY) -#define CONFIG_BOOTDELAY -1 -#else -#define CONFIG_BOOTDELAY 1 -#endif - #define CONFIG_ENV_OVERWRITE /* diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index d53f8c18a22..8bbe580ebf3 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -82,7 +82,6 @@ "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ "bootm 0x08044000 - 0x08042000\0" -#define CONFIG_BOOTDELAY 3 #define CONFIG_AUTOBOOT /* diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 9d1f02ea15d..e544a218dd7 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -69,7 +69,6 @@ "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ "bootm 0x08044000 - 0x08042000\0" -#define CONFIG_BOOTDELAY 3 /* * Command line configuration. diff --git a/include/configs/strider.h b/include/configs/strider.h index 90492f4fdb6..36561e0346e 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -659,7 +659,6 @@ void fpga_control_clear(unsigned int bus, int pin); #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ #define CONFIG_HOSTNAME hrcon #define CONFIG_ROOTPATH "/opt/nfsroot" diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index d3704a4e2cc..bfd1bd71928 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -66,7 +66,6 @@ #define CONFIG_SYS_LONGHELP #define CONFIG_CMDLINE_EDITING -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND "go 0x40040000" /* diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 4d66dd2407b..6616d7396e7 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -128,7 +128,6 @@ /* devices */ #define CONFIG_SYS_NAND_BUSWIDTH_16BIT /* Environment information */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 321fb4756d1..0b05289d07e 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -60,7 +60,6 @@ #define CONFIG_USART_ID ATMEL_ID_SYS #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 /* * Command line configuration. diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 870406b208e..39bb5b35dad 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -79,7 +79,6 @@ /* * Environment configuration */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTARGS "console=ttyS0,115200n8" #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 5fed55da1c8..a03f87c2fb9 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -78,7 +78,6 @@ #ifndef CONFIG_RESTORE_FLASH /* set to negative value for no autoboot */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND \ "if dfubutton; then " \ @@ -90,7 +89,6 @@ "reset;" #else -#define CONFIG_BOOTDELAY 0 #define CONFIG_BOOTCOMMAND \ "setenv autoload no; " \ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index e43a7fdf3cf..5c3b3da73c0 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -84,7 +84,6 @@ "earlycon=pl011,0x87e024000000 " \ "debug maxcpus=48 rootwait rw "\ "root=/dev/sda2 coherent_pool=16M" -#define CONFIG_BOOTDELAY 5 /* Do not preserve environment */ #define CONFIG_ENV_IS_NOWHERE 1 diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 09f8e8fe5cc..3c058832e17 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -39,7 +39,6 @@ /* commands to include */ #define CONFIG_VERSION_VARIABLE -#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */ #define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 2e84dd27e4f..05fd00fd5d2 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -34,7 +34,6 @@ #define CONFIG_VERSION_VARIABLE #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_BOOTDELAY 3 /* set negative for no autoboot */ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x81000000\0" \ diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index abe1da2bd68..74a9a098a0b 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -39,7 +39,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ {9600, 19200, 38400, 57600, 115200} -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS \ "console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 855d789c18e..aed3931515e 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -162,7 +162,6 @@ /* Environment information (this is the common part) */ -#define CONFIG_BOOTDELAY 0 /* hang() the board on panic() */ #define CONFIG_PANIC_HANG diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h index aa0605f28d7..8b4726f19c3 100644 --- a/include/configs/ts4800.h +++ b/include/configs/ts4800.h @@ -90,7 +90,6 @@ /* Environment variables */ -#define CONFIG_BOOTDELAY 1 #define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */ diff --git a/include/configs/tseries.h b/include/configs/tseries.h index b6a1ae0554a..8ed9eb080d6 100644 --- a/include/configs/tseries.h +++ b/include/configs/tseries.h @@ -195,7 +195,6 @@ MMCARGS #define CONFIG_BOOTCOMMAND \ "run defboot;" -#define CONFIG_BOOTDELAY 0 #ifdef CONFIG_NAND /* diff --git a/include/configs/twister.h b/include/configs/twister.h index 4f5560fec3b..66f4680b7e1 100644 --- a/include/configs/twister.h +++ b/include/configs/twister.h @@ -20,7 +20,6 @@ #define CONFIG_TAM3517_SW3_SETTINGS #define CONFIG_XR16L2751 -#define CONFIG_BOOTDELAY 10 #define CONFIG_BOOTFILE "uImage" diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index c826b200ba4..9d14c2d59c9 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -148,7 +148,6 @@ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) -#define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ /* diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index d118928ebdd..ad541921942 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -46,7 +46,6 @@ #define CONFIG_USART_ID ATMEL_ID_SYS #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 /* * BOOTP options diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 9a113f4e32d..28c748d074c 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -102,7 +102,6 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #define CONFIG_PREBOOT "echo;" \ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ diff --git a/include/configs/vct.h b/include/configs/vct.h index cc5e3546b08..2bc98a8e8a3 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -240,7 +240,6 @@ int vct_gpio_get(int pin); #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CONFIG_BOOTCOMMAND "run test3" -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ /* * UBI configuration diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 2425ebf6693..83d0004f537 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -465,7 +465,6 @@ #define CONFIG_HOSTNAME ve8313 #define CONFIG_UBOOTPATH ve8313/u-boot.bin -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 6a3758216fd..46cf83be02e 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -216,7 +216,6 @@ "fi ; " \ "booti ${kernel_addr} ${initrd_param} ${fdt_addr}" -#define CONFIG_BOOTDELAY 1 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -241,7 +240,6 @@ "fdt chosen ${initrd_addr} ${initrd_end}; " \ "booti $kernel_addr - $fdt_addr" -#define CONFIG_BOOTDELAY 1 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -260,7 +258,6 @@ #define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr" -#define CONFIG_BOOTDELAY 1 #endif diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 6dc8f25b909..51898e623cb 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -168,7 +168,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000) #define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) -#define CONFIG_BOOTDELAY 2 /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index b240613bb55..c4a1fd091ab 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -103,7 +103,6 @@ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_BOOTDELAY 3 #define CONFIG_SYS_LOAD_ADDR 0x82000000 diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 732d0915832..60513df0327 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -542,7 +542,6 @@ #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* boot command will set bootargs */ #define CONFIG_BAUDRATE 9600 diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 4dfcd28eaf6..f112fa5f162 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -9,7 +9,6 @@ #ifndef __WARP7_CONFIG_H #define __WARP7_CONFIG_H -#define CONFIG_BOOTDELAY 1 #include "mx7_common.h" #define PHYS_SDRAM_SIZE SZ_512M diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index a4ae304ade4..153466a623f 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -97,7 +97,6 @@ #define CONFIG_NET_RETRY_COUNT 100 -#define CONFIG_BOOTDELAY 3 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index b81b6ff1faf..ba222f936f8 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -175,7 +175,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTARGS "console=ttyS2,115200n8" diff --git a/include/configs/x600.h b/include/configs/x600.h index 07c8abe2a79..71c0b458423 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -124,7 +124,6 @@ #define CONFIG_SUPPORT_VFAT #define CONFIG_DOS_PARTITION -#define CONFIG_BOOTDELAY 3 /* * U-Boot Environment placing definitions. diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index b4aad6cd24f..fdefeaf24cf 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -225,6 +225,5 @@ "tftpboot $loadaddr $bootfile;" \ "zboot $loadaddr" -#define CONFIG_BOOTDELAY 2 #endif /* __CONFIG_H */ diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h index 4d68c21ae05..69558fdfd20 100644 --- a/include/configs/xfi3.h +++ b/include/configs/xfi3.h @@ -28,7 +28,6 @@ #define CONFIG_ENV_OVERWRITE /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " #define CONFIG_LOADADDR 0x42000000 diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h index 067cfa69f2f..e97e9d08163 100644 --- a/include/configs/xilinx-ppc.h +++ b/include/configs/xilinx-ppc.h @@ -33,7 +33,6 @@ #undef CONFIG_CMD_EEPROM /*Misc*/ -#define CONFIG_BOOTDELAY 5/* autoboot after 5 seconds */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index b848150182e..e776e324120 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -144,7 +144,6 @@ # define DFU_ALT_INFO #endif -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h index 9838fbfa2e0..73c8d5b6fd4 100644 --- a/include/configs/xpedite1000.h +++ b/include/configs/xpedite1000.h @@ -196,7 +196,6 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ -#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ #define CONFIG_PANIC_HANG /* do not reset board on panic */ #define CONFIG_PREBOOT /* enable preboot variable */ #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 86c9b4c41f6..9f3158d056b 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -536,7 +536,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ #define CONFIG_PANIC_HANG /* do not reset board on panic */ #define CONFIG_PREBOOT /* enable preboot variable */ #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index d1847ac2e8c..a418fc5c9e2 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -319,7 +319,6 @@ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ #define CONFIG_PANIC_HANG /* do not reset board on panic */ #define CONFIG_PREBOOT /* enable preboot variable */ #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 6a06b0ab1c9..36df6682b28 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -391,7 +391,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ #define CONFIG_PANIC_HANG /* do not reset board on panic */ #define CONFIG_PREBOOT /* enable preboot variable */ #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 5b377e35eed..1794ba10a37 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -375,7 +375,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ #define CONFIG_PANIC_HANG /* do not reset board on panic */ #define CONFIG_PREBOOT /* enable preboot variable */ #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index fcd77726429..6e83cc9180d 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -40,7 +40,6 @@ #define CONFIG_BOOTARGS \ "console=tty0 console=ttyS2,115200 fbcon=rotate:3" #define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_SYS_TEXT_BASE 0x0 diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 264bb63c069..ea1ead23b72 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -137,7 +137,6 @@ #define CONFIG_PREBOOT "" -#define CONFIG_BOOTDELAY 5 /* * Size of malloc() pool diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 82ece0df2d6..8dbac8728f0 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -236,7 +236,6 @@ #endif #define CONFIG_BOOTCOMMAND "run $modeboot" -#define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */ #define CONFIG_SYS_LOAD_ADDR 0 /* default? */ /* Miscellaneous configurable options */ -- cgit v1.3.1 From 640ff60af7a36ba9649dc79be6d117c9c12429fe Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 7 Jun 2016 08:31:16 +0200 Subject: power, tps65217: add some defines add the following defines, needed for the upcoming shc board support: Signed-off-by: Heiko Schocher Reviewed-by: Tom Rini --- include/power/tps65217.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/power/tps65217.h b/include/power/tps65217.h index 93cbe36c472..69a49f76fef 100644 --- a/include/power/tps65217.h +++ b/include/power/tps65217.h @@ -65,7 +65,10 @@ enum { #define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02 #define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03 +#define TPS65217_DCDC_VOLT_SEL_950MV 0x02 +#define TPS65217_DCDC_VOLT_SEL_1100MV 0x08 #define TPS65217_DCDC_VOLT_SEL_1125MV 0x09 +#define TPS65217_DCDC_VOLT_SEL_1200MV 0x0c #define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F #define TPS65217_DCDC_VOLT_SEL_1325MV 0x11 -- cgit v1.3.1 From 496c5483e9ad80d34ff0d9ee9abb813e51be2237 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 7 Jun 2016 08:31:20 +0200 Subject: bootstage: call show_boot_progress also in SPL show_boot_progress() is now called from SPL also. Signed-off-by: Heiko Schocher --- common/init/board_init.c | 5 +++++ common/spl/spl.c | 5 +++++ include/bootstage.h | 6 +++--- 3 files changed, 13 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/common/init/board_init.c b/common/init/board_init.c index d17bb298d72..ef01a9aeaad 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -146,3 +146,8 @@ void board_init_f_init_reserve(ulong base) base += CONFIG_SYS_MALLOC_F_LEN; #endif } + +/* + * Board-specific Platform code can reimplement show_boot_progress () if needed + */ +__weak void show_boot_progress(int val) {} diff --git a/common/spl/spl.c b/common/spl/spl.c index c8dfc14508f..840910a6844 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -35,6 +35,11 @@ struct spl_image_info spl_image; /* Define board data structure */ static bd_t bdata __attribute__ ((section(".data"))); +/* + * Board-specific Platform code can reimplement show_boot_progress () if needed + */ +__weak void show_boot_progress(int val) {} + /* * Default function to determine if u-boot or the OS should * be started. This implementation always returns 1. diff --git a/include/bootstage.h b/include/bootstage.h index 0880a680b9e..a589be6316e 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -213,7 +213,9 @@ enum bootstage_id { */ ulong timer_get_boot_us(void); -#if !defined(CONFIG_SPL_BUILD) && !defined(USE_HOSTCC) +#if defined(USE_HOSTCC) +#define show_boot_progress(val) do {} while (0) +#else /* * Board code can implement show_boot_progress() if needed. * @@ -221,8 +223,6 @@ ulong timer_get_boot_us(void); * has occurred. */ void show_boot_progress(int val); -#else -#define show_boot_progress(val) do {} while (0) #endif #if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD) && \ -- cgit v1.3.1 From d8ccbe93b576696852a7cdb2ac8018bb47ce787e Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 7 Jun 2016 08:31:25 +0200 Subject: am335x, shc: add support for the am335x based bosch shc board U-Boot SPL 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:40:06) SHC C3-Sample MPU reference clock runs at 6 MHz Setting MPU clock to 594 MHz Enabling Spread Spectrum of 18 permille for MPU Trying to boot from MMC reading u-boot.img reading u-boot.img U-Boot 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:05:35 +0100) Watchdog enabled I2C: ready DRAM: 512 MiB reloc off 1f783000 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 Net: cpsw U-Boot# Signed-off-by: Heiko Schocher --- arch/arm/Kconfig | 9 + board/bosch/shc/Kconfig | 87 ++++ board/bosch/shc/MAINTAINERS | 11 + board/bosch/shc/Makefile | 10 + board/bosch/shc/README | 114 +++++ board/bosch/shc/board.c | 648 +++++++++++++++++++++++++++++ board/bosch/shc/board.h | 187 +++++++++ board/bosch/shc/mux.c | 261 ++++++++++++ configs/am335x_shc_defconfig | 21 + configs/am335x_shc_ict_defconfig | 21 + configs/am335x_shc_netboot_defconfig | 21 + configs/am335x_shc_prompt_defconfig | 19 + configs/am335x_shc_sdboot_defconfig | 21 + configs/am335x_shc_sdboot_prompt_defconfig | 21 + include/configs/am335x_shc.h | 340 +++++++++++++++ 15 files changed, 1791 insertions(+) create mode 100644 board/bosch/shc/Kconfig create mode 100644 board/bosch/shc/MAINTAINERS create mode 100644 board/bosch/shc/Makefile create mode 100644 board/bosch/shc/README create mode 100644 board/bosch/shc/board.c create mode 100644 board/bosch/shc/board.h create mode 100644 board/bosch/shc/mux.c create mode 100644 configs/am335x_shc_defconfig create mode 100644 configs/am335x_shc_ict_defconfig create mode 100644 configs/am335x_shc_netboot_defconfig create mode 100644 configs/am335x_shc_prompt_defconfig create mode 100644 configs/am335x_shc_sdboot_defconfig create mode 100644 configs/am335x_shc_sdboot_prompt_defconfig create mode 100644 include/configs/am335x_shc.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 30ed279474b..26ccf628299 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -396,6 +396,14 @@ config TARGET_AM335X_EVM select DM_GPIO select TI_I2C_BOARD_DETECT +config TARGET_AM335X_SHC + bool "Support am335x based shc board from bosch" + select CPU_V7 + select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO + config TARGET_AM335X_SL50 bool "Support am335x_sl50" select CPU_V7 @@ -875,6 +883,7 @@ source "arch/arm/cpu/armv8/Kconfig" source "arch/arm/imx-common/Kconfig" +source "board/bosch/shc/Kconfig" source "board/BuR/kwb/Kconfig" source "board/BuR/tseries/Kconfig" source "board/CarMediaLab/flea3/Kconfig" diff --git a/board/bosch/shc/Kconfig b/board/bosch/shc/Kconfig new file mode 100644 index 00000000000..c71af11c1cd --- /dev/null +++ b/board/bosch/shc/Kconfig @@ -0,0 +1,87 @@ +if TARGET_AM335X_SHC + +config SYS_BOARD + default "shc" + +config SYS_VENDOR + default "bosch" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "am335x_shc" + +choice + prompt "enable different boot versions for the shc board" + default EMMC + help + Select the boot version of the shc board. + +config SHC_EMMC + bool "enable eMMC" + help + enable here the eMMC functionality on the bosch shc board. + +config SHC_ICT + bool "enable ICT" + help + enable here the ICT functionality on the bosch shc board + +config SHC_NETBOOT + bool "enable NETBOOT" + help + enable here the NETBOOT functionality on the bosch shc board + +config SHC_SDBOOT + bool "enable SDBOOT" + help + enable here the SDBOOT functionality on the bosch shc board + +endchoice + +choice + prompt "enable different board versions for the shc board" + default C3_SAMPLE + help + Select the board version of the shc board. + +config B_SAMPLE + bool "B Sample board version" + help + activate, if you want to build for the B sample version + of the bosch shc board + +config B2_SAMPLE + bool "B2 Sample board version" + help + activate, if you want to build for the B2 sample version + of the bosch shc board + +config C_SAMPLE + bool "C Sample board version" + help + activate, if you want to build for the C sample version + of the bosch shc board + +config C2_SAMPLE + bool "C2 Sample board version" + help + activate, if you want to build for the C2 sample version + of the bosch shc board + +config C3_SAMPLE + bool "C3 Sample board version" + help + activate, if you want to build for the C3 sample version + of the bosch shc board + +config SERIES + bool "Series board version" + help + activate, if you want to build for the Series version + of the bosch shc board + +endchoice + +endif diff --git a/board/bosch/shc/MAINTAINERS b/board/bosch/shc/MAINTAINERS new file mode 100644 index 00000000000..ae3c0355c07 --- /dev/null +++ b/board/bosch/shc/MAINTAINERS @@ -0,0 +1,11 @@ +SHC BOARD +M: Heiko Schocher +S: Maintained +F: board/bosch/shc +F: include/configs/am335x_shc.h +F: configs/am335x_shc_defconfig +F: configs/am335x_shc_ict_defconfig +F: configs/am335x_shc_netboot_defconfig +F: configs/am335x_shc_prompt_defconfig +F: configs/am335x_shc_sdboot_defconfig +F: configs/am335x_shc_sdboot_prompt_defconfig diff --git a/board/bosch/shc/Makefile b/board/bosch/shc/Makefile new file mode 100644 index 00000000000..4fec2bff295 --- /dev/null +++ b/board/bosch/shc/Makefile @@ -0,0 +1,10 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mux.o +obj-y += board.o diff --git a/board/bosch/shc/README b/board/bosch/shc/README new file mode 100644 index 00000000000..2f206e0d551 --- /dev/null +++ b/board/bosch/shc/README @@ -0,0 +1,114 @@ +Summary +======= + +This document covers various features of the 'am335x_shc' build. + +Hardware +======== + +AM335X based board: + +I2C: ready +DRAM: 512 MiB +Enabling the D-Cache +MMC: OMAP SD/MMC: 0 @ 26 MHz, OMAP SD/MMC: 1 @ 26 MHz +Net: cpsw + +Following boot options are possible: + +2 Jumpers: + +Jumper 1 Jumper 2 Bootmode +off off eMMC boot +on off SD boot +off on Net boot + +Compiling +========= + +$ make am335x_shc_defconfig + HOSTCC scripts/basic/fixdep + HOSTCC scripts/kconfig/conf.o + SHIPPED scripts/kconfig/zconf.tab.c + SHIPPED scripts/kconfig/zconf.lex.c + SHIPPED scripts/kconfig/zconf.hash.c + HOSTCC scripts/kconfig/zconf.tab.o + HOSTLD scripts/kconfig/conf +# +# configuration written to .config +# +$ make -s all + +-> now you have the MLO and the u-boot.img file, you can put +on your SD card or eMMC. + +Configuring +=========== + +There are a lot of board versions and boot configurations, which +can be selected through "make menuconfig" + +ARM architecture ---> + enable different boot versions for the shc board (enable eMMC) ---> + (X) enable eMMC + ( ) enable ICT + ( ) enable NETBOOT + ( ) enable SDBOOT + + enable different board versions for the shc board (C3 Sample board version) ---> + ( ) B Sample board version + ( ) B2 Sample board version + ( ) C Sample board version + ( ) C2 Sample board version + (X) C3 Sample board version + ( ) Series board version + +Netboot +======= +- see also doc/SPL/README.am335x-network + +- set the jumper into netboot mode +- compile the U-boot sources with: + make am335x_shc_netboot_defconfig + make all +- copy the images into your tftp boot directory + cp spl/u-boot-spl.bin /tftpboot/.../u-boot-spl-restore.bin + cp u-boot.img /tftpboot/.../u-boot-restore.img +- power on the board, and you should get something like this: + +U-Boot SPL 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18) +#### NETBOOT #### +SHC +MPU reference clock runs at 6 MHz +Setting MPU clock to 594 MHz +Enabling Spread Spectrum of 18 permille for MPU +Trying to boot from net +Using default environment + + not set. Validating first E-fuse MAC +cpsw +cpsw Waiting for PHY auto negotiation to complete... done +link up on port 0, speed 100, full duplex +BOOTP broadcast 1 +BOOTP broadcast 2 +DHCP client bound to address 192.168.20.91 (258 ms) +Using cpsw device +TFTP from server 192.168.1.1; our IP address is 192.168.20.91 +Filename 'shc/u-boot-restore.img'. +Load address: 0x807fffc0 +Loading: ################## + 1.2 MiB/s +done +Bytes transferred = 262480 (40150 hex) + + +U-Boot 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18 +0200) + + Watchdog enabled +I2C: ready +DRAM: 512 MiB +MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 +*** Warning - bad CRC, using default environment + +Net: cpsw +switch to partitions #0, OK diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c new file mode 100644 index 00000000000..e90693feeaa --- /dev/null +++ b/board/bosch/shc/board.c @@ -0,0 +1,648 @@ +/* + * board.c + * + * (C) Copyright 2016 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Board functions for TI AM335X based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mmc.h" +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_SPL_BUILD) || \ + (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH)) +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; +#endif +static struct shc_eeprom __attribute__((section(".data"))) header; +static int shc_eeprom_valid; + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, + sizeof(header))) { + puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return -EIO; + } + + if (header.magic != HDR_MAGIC) { + printf("Incorrect magic number (0x%x) in EEPROM\n", + header.magic); + return -EIO; + } + + shc_eeprom_valid = 1; + + return 0; +} + +static void shc_request_gpio(void) +{ + gpio_request(LED_PWR_BL_GPIO, "LED PWR BL"); + gpio_request(LED_PWR_RD_GPIO, "LED PWR RD"); + gpio_request(RESET_GPIO, "reset"); + gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN"); + gpio_request(WIFI_RST_GPIO, "WIFI rst"); + gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst"); + gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst"); + gpio_request(ENOC_RST_GPIO, "ENOC rst"); +#if defined CONFIG_B_SAMPLE + gpio_request(LED_PWR_GN_GPIO, "LED PWR GN"); + gpio_request(LED_CONN_BL_GPIO, "LED CONN BL"); + gpio_request(LED_CONN_RD_GPIO, "LED CONN RD"); + gpio_request(LED_CONN_GN_GPIO, "LED CONN GN"); +#else + gpio_request(LED_LAN_BL_GPIO, "LED LAN BL"); + gpio_request(LED_LAN_RD_GPIO, "LED LAN RD"); + gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL"); + gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD"); + gpio_request(LED_PWM_GPIO, "LED PWM"); + gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst"); +#endif + gpio_request(BACK_BUTTON_GPIO, "Back button"); + gpio_request(FRONT_BUTTON_GPIO, "Front button"); +} + +/* + * Function which forces all installed modules into running state for ICT + * testing. Called by SPL. + */ +static void __maybe_unused force_modules_running(void) +{ + /* Wi-Fi power regulator enable - high = enabled */ + gpio_direction_output(WIFI_REGEN_GPIO, 1); + /* + * Wait for Wi-Fi power regulator to reach a stable voltage + * (soft-start time, max. 350 µs) + */ + __udelay(350); + + /* Wi-Fi module reset - high = running */ + gpio_direction_output(WIFI_RST_GPIO, 1); + + /* ZigBee reset - high = running */ + gpio_direction_output(ZIGBEE_RST_GPIO, 1); + + /* BidCos reset - high = running */ + gpio_direction_output(BIDCOS_RST_GPIO, 1); + +#if !defined(CONFIG_B_SAMPLE) + /* Z-Wave reset - high = running */ + gpio_direction_output(Z_WAVE_RST_GPIO, 1); +#endif + + /* EnOcean reset - low = running */ + gpio_direction_output(ENOC_RST_GPIO, 0); +} + +/* + * Function which forces all installed modules into reset - to be released by + * the OS, called by SPL + */ +static void __maybe_unused force_modules_reset(void) +{ + /* Wi-Fi module reset - low = reset */ + gpio_direction_output(WIFI_RST_GPIO, 0); + + /* Wi-Fi power regulator enable - low = disabled */ + gpio_direction_output(WIFI_REGEN_GPIO, 0); + + /* ZigBee reset - low = reset */ + gpio_direction_output(ZIGBEE_RST_GPIO, 0); + + /* BidCos reset - low = reset */ + /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/ + +#if !defined(CONFIG_B_SAMPLE) + /* Z-Wave reset - low = reset */ + gpio_direction_output(Z_WAVE_RST_GPIO, 0); +#endif + + /* EnOcean reset - high = reset*/ + gpio_direction_output(ENOC_RST_GPIO, 1); +} + +/* + * Function to set the LEDs in the state "Bootloader booting" + */ +static void __maybe_unused leds_set_booting(void) +{ +#if defined(CONFIG_B_SAMPLE) + + /* Turn all red LEDs on */ + gpio_direction_output(LED_PWR_RD_GPIO, 1); + gpio_direction_output(LED_CONN_RD_GPIO, 1); + +#else /* All other SHCs starting with B2-Sample */ + /* Set the PWM GPIO */ + gpio_direction_output(LED_PWM_GPIO, 1); + /* Turn all red LEDs on */ + gpio_direction_output(LED_PWR_RD_GPIO, 1); + gpio_direction_output(LED_LAN_RD_GPIO, 1); + gpio_direction_output(LED_CLOUD_RD_GPIO, 1); + +#endif +} + +/* + * Function to set the LEDs in the state "Bootloader error" + */ +static void leds_set_failure(int state) +{ +#if defined(CONFIG_B_SAMPLE) + /* Turn all blue and green LEDs off */ + gpio_set_value(LED_PWR_BL_GPIO, 0); + gpio_set_value(LED_PWR_GN_GPIO, 0); + gpio_set_value(LED_CONN_BL_GPIO, 0); + gpio_set_value(LED_CONN_GN_GPIO, 0); + + /* Turn all red LEDs to 'state' */ + gpio_set_value(LED_PWR_RD_GPIO, state); + gpio_set_value(LED_CONN_RD_GPIO, state); + +#else /* All other SHCs starting with B2-Sample */ + /* Set the PWM GPIO */ + gpio_direction_output(LED_PWM_GPIO, 1); + + /* Turn all blue LEDs off */ + gpio_set_value(LED_PWR_BL_GPIO, 0); + gpio_set_value(LED_LAN_BL_GPIO, 0); + gpio_set_value(LED_CLOUD_BL_GPIO, 0); + + /* Turn all red LEDs to 'state' */ + gpio_set_value(LED_PWR_RD_GPIO, state); + gpio_set_value(LED_LAN_RD_GPIO, state); + gpio_set_value(LED_CLOUD_RD_GPIO, state); +#endif +} + +/* + * Function to set the LEDs in the state "Bootloader finished" + */ +static void leds_set_finish(void) +{ +#if defined(CONFIG_B_SAMPLE) + /* Turn all LEDs off */ + gpio_set_value(LED_PWR_BL_GPIO, 0); + gpio_set_value(LED_PWR_RD_GPIO, 0); + gpio_set_value(LED_PWR_GN_GPIO, 0); + gpio_set_value(LED_CONN_BL_GPIO, 0); + gpio_set_value(LED_CONN_RD_GPIO, 0); + gpio_set_value(LED_CONN_GN_GPIO, 0); +#else /* All other SHCs starting with B2-Sample */ + /* Turn all LEDs off */ + gpio_set_value(LED_PWR_BL_GPIO, 0); + gpio_set_value(LED_PWR_RD_GPIO, 0); + gpio_set_value(LED_LAN_BL_GPIO, 0); + gpio_set_value(LED_LAN_RD_GPIO, 0); + gpio_set_value(LED_CLOUD_BL_GPIO, 0); + gpio_set_value(LED_CLOUD_RD_GPIO, 0); + + /* Turn off the PWM GPIO and mux it to EHRPWM */ + gpio_set_value(LED_PWM_GPIO, 0); + enable_shc_board_pwm_pin_mux(); +#endif +} + +static void check_button_status(void) +{ + ulong value; + gpio_direction_input(FRONT_BUTTON_GPIO); + value = gpio_get_value(FRONT_BUTTON_GPIO); + + if (value == 0) { + printf("front button activated !\n"); + setenv("harakiri", "1"); + } +} + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + return 1; +} +#endif + +static void shc_board_early_init(void) +{ + shc_request_gpio(); +# ifdef CONFIG_SHC_ICT + /* Force all modules into enabled state for ICT testing */ + force_modules_running(); +# else + /* Force all modules to enter Reset state until released by the OS */ + force_modules_reset(); +# endif + leds_set_booting(); +} + +#define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */ +#define OSC (V_OSCK/1000000) +/* Bosch: Predivider must be fixed to 4, so N = 4-1 */ +#define MPUPLL_N (4-1) +/* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */ +#define MPUPLL_FREF (OSC / (MPUPLL_N + 1)) + +const struct dpll_params dpll_ddr_shc = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr_shc; +} + +/* + * As we enabled downspread SSC with 1.8%, the values needed to be corrected + * such that the 20% overshoot will not lead to too high frequencies. + * In all cases, this is achieved by subtracting one from M (6 MHz less). + * Example: 600 MHz CPU + * Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz + * 600 MHz - 6 MHz (1x Fref) = 594 MHz + * SSC: 594 MHz * 1.8% = 10.7 MHz SSC + * Overshoot: 10.7 MHz * 20 % = 2.2 MHz + * --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK! + */ +const struct dpll_params dpll_mpu_shc_opp100 = { + 99, MPUPLL_N, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + int sil_rev; + int mpu_vdd; + + puts(BOARD_ID_STR); + + /* + * Set CORE Frequency to OPP100 + * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100) + */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + sil_rev = readl(&cdev->deviceid) >> 28; + if (sil_rev < 2) { + puts("We do not support Silicon Revisions below 2.0!\n"); + return; + } + + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + if (i2c_probe(TPS65217_CHIP_PM)) + return; + + /* + * Retrieve the CPU max frequency by reading the efuse + * SHC-Default: 600 MHz + */ + switch (dpll_mpu_opp100.m) { + case MPUPLL_M_1000: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + break; + case MPUPLL_M_800: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + break; + case MPUPLL_M_720: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV; + break; + case MPUPLL_M_600: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV; + break; + case MPUPLL_M_300: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV; + break; + default: + puts("Cannot determine the frequency, failing!\n"); + return; + } + + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set MPU Frequency to what we detected */ + printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF); + printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF * + dpll_mpu_shc_opp100.m); + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100); + + /* Enable Spread Spectrum for this freq to be clean on EMI side */ + set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE); + + /* + * Using the default voltages for the PMIC (TPS65217D) + * LS1 = 1.8V (VDD_1V8) + * LS2 = 3.3V (VDD_3V3A) + * LDO1 = 1.8V (VIO and VRTC) + * LDO2 = 3.3V (VDD_3V3AUX) + */ + shc_board_early_init(); +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_shc_board_pin_mux(); +} + +const struct ctrl_ioregs ioregs_evmsk = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +static const struct ddr_data ddr3_shc_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_shc_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_shc_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +void sdram_init(void) +{ + /* Configure the DDR3 RAM */ + config_ddr(400, &ioregs_evmsk, &ddr3_shc_data, + &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0); +} +#endif + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("EEPROM Content Invalid.\n"); + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#if defined(CONFIG_NOR) || defined(CONFIG_NAND) + gpmc_init(); +#endif + shc_request_gpio(); + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + check_button_status(); +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + if (shc_eeprom_valid) + if (is_valid_ethaddr(header.mac_addr)) + eth_setenv_enetaddr("ethaddr", header.mac_addr); +#endif + + return 0; +} +#endif + +#ifndef CONFIG_DM_ETH +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif + +/* + * This function will: + * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr + * in the environment + * Perform fixups to the PHY present on certain boards. We only need this + * function in: + * - SPL with either CPSW or USB ethernet support + * - Full U-Boot, with either CPSW or USB ethernet + * Build in only these cases to avoid warnings about unused variables + * when we build an SPL that has neither option but full U-Boot will. + */ +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \ + defined(CONFIG_SPL_USBETH_SUPPORT)) && \ + defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + if (!getenv("ethaddr")) { + printf(" not set. Validating first E-fuse MAC\n"); + + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + writel(MII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII; + cpsw_slaves[1].phy_if = cpsw_slaves[0].phy_if; + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + +#if defined(CONFIG_USB_ETHER) && \ + (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("usbnet_devaddr", mac_addr); + + rv = usb_eth_initialize(bis); + if (rv < 0) + printf("Error %d registering USB_ETHER\n", rv); + else + n += rv; +#endif + return n; +} +#endif + +#endif /* CONFIG_DM_ETH */ + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +static void bosch_check_reset_pin(void) +{ + if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) { + printf("Resetting ...\n"); + writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0); + disable_interrupts(); + reset_cpu(0); + /*NOTREACHED*/ + } +} + +static void hang_bosch(const char *cause, int code) +{ + int lv; + + gpio_direction_input(RESET_GPIO); + + /* Enable reset pin interrupt on falling edge */ + writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0); + writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT); + enable_interrupts(); + + puts(cause); + for (;;) { + for (lv = 0; lv < code; lv++) { + bosch_check_reset_pin(); + leds_set_failure(1); + __udelay(150 * 1000); + leds_set_failure(0); + __udelay(150 * 1000); + } +#if defined(BLINK_CODE) + __udelay(300 * 1000); +#endif + } +} + +void show_boot_progress(int val) +{ + switch (val) { + case BOOTSTAGE_ID_NEED_RESET: + hang_bosch("need reset", 4); + break; + } +} +#endif + +void arch_preboot_os(void) +{ + leds_set_finish(); +} + +#if defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* Bosch: Do not enable 52MHz for eMMC device to avoid EMI */ + ret = omap_mmc_init(0, MMC_MODE_HS_52MHz, 26000000, -1, -1); + if (ret) + return ret; + + ret = omap_mmc_init(1, MMC_MODE_HS_52MHz, 26000000, -1, -1); + return ret; +} +#endif diff --git a/board/bosch/shc/board.h b/board/bosch/shc/board.h new file mode 100644 index 00000000000..46167fe59ec --- /dev/null +++ b/board/bosch/shc/board.h @@ -0,0 +1,187 @@ +/* + * board.h + * + * (C) Copyright 2016 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* Definition to control the GPIOs (for LEDs and Reset) */ +#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) + +static inline int board_is_b_sample(void) +{ +#if defined CONFIG_B_SAMPLE + return 1; +#else + return 0; +#endif +} + +static inline int board_is_c_sample(void) +{ +#if defined CONFIG_C_SAMPLE + return 1; +#else + return 0; +#endif +} + +static inline int board_is_c3_sample(void) +{ +#if defined CONFIG_C3_SAMPLE + return 1; +#else + return 0; +#endif +} + +static inline int board_is_series(void) +{ +#if defined CONFIG_SERIES + return 1; +#else + return 0; +#endif +} + +/* + * Definitions for pinmuxing header and Board ID strings + */ +#if defined CONFIG_B_SAMPLE +# define BOARD_ID_STR "SHC B-Sample\n" +#elif defined CONFIG_B2_SAMPLE +# define BOARD_ID_STR "SHC B2-Sample\n" +#elif defined CONFIG_C_SAMPLE +# if defined(CONFIG_SHC_NETBOOT) +# define BOARD_ID_STR "#### NETBOOT ####\nSHC C-Sample\n" +# elif defined(CONFIG_SHC_SDBOOT) +# define BOARD_ID_STR "#### SDBOOT ####\nSHC C-Sample\n" +# else +# define BOARD_ID_STR "SHC C-Sample\n" +# endif +#elif defined CONFIG_C2_SAMPLE +# if defined(CONFIG_SHC_ICT) +# define BOARD_ID_STR "#### ICT ####\nSHC C2-Sample\n" +# elif defined(CONFIG_SHC_NETBOOT) +# define BOARD_ID_STR "#### NETBOOT ####\nSHC C2-Sample\n" +# elif defined(CONFIG_SHC_SDBOOT) +# define BOARD_ID_STR "#### SDBOOT ####\nSHC C2-Sample\n" +# else +# define BOARD_ID_STR "SHC C2-Sample\n" +# endif +#elif defined CONFIG_C3_SAMPLE +# if defined(CONFIG_SHC_ICT) +# define BOARD_ID_STR "#### ICT ####\nSHC C3-Sample\n" +# elif defined(CONFIG_SHC_NETBOOT) +# define BOARD_ID_STR "#### NETBOOT ####\nSHC C3-Sample\n" +# elif defined(CONFIG_SHC_SDBOOT) +# define BOARD_ID_STR "#### SDBOOT ####\nSHC C3-Sample\n" +# else +# define BOARD_ID_STR "SHC C3-Sample\n" +# endif +#elif defined CONFIG_SERIES +# if defined(CONFIG_SHC_ICT) +# define BOARD_ID_STR "#### ICT ####\nSHC\n" +# elif defined(CONFIG_SHC_NETBOOT) +# define BOARD_ID_STR "#### NETBOOT ####\nSHC\n" +# elif defined(CONFIG_SHC_SDBOOT) +# define BOARD_ID_STR "#### SDBOOT ####\nSHC\n" +# else +# define BOARD_ID_STR "SHC\n" +# endif +#else +# define BOARD_ID_STR "Unknown device!\n" +#endif + +/* + * Definitions for GPIO pin assignments + */ +#if defined CONFIG_B_SAMPLE + +# define LED_PWR_BL_GPIO GPIO_TO_PIN(1, 17) +# define LED_PWR_RD_GPIO GPIO_TO_PIN(1, 18) +# define LED_PWR_GN_GPIO GPIO_TO_PIN(1, 19) +# define LED_CONN_BL_GPIO GPIO_TO_PIN(0, 26) +# define LED_CONN_RD_GPIO GPIO_TO_PIN(0, 22) +# define LED_CONN_GN_GPIO GPIO_TO_PIN(0, 23) +# define RESET_GPIO GPIO_TO_PIN(1, 29) +# define WIFI_REGEN_GPIO GPIO_TO_PIN(1, 16) +# define WIFI_RST_GPIO GPIO_TO_PIN(0, 27) +# define ZIGBEE_RST_GPIO GPIO_TO_PIN(3, 18) +# define BIDCOS_RST_GPIO GPIO_TO_PIN(0, 12) +# define ENOC_RST_GPIO GPIO_TO_PIN(1, 22) + +#else + +# define LED_PWR_BL_GPIO GPIO_TO_PIN(0, 22) +# define LED_PWR_RD_GPIO GPIO_TO_PIN(0, 23) +# define LED_LAN_BL_GPIO GPIO_TO_PIN(1, 17) +# define LED_LAN_RD_GPIO GPIO_TO_PIN(0, 26) +# define LED_CLOUD_BL_GPIO GPIO_TO_PIN(1, 18) +# define LED_CLOUD_RD_GPIO GPIO_TO_PIN(2, 2) +# define LED_PWM_GPIO GPIO_TO_PIN(1, 19) +# define RESET_GPIO GPIO_TO_PIN(1, 29) +# define WIFI_REGEN_GPIO GPIO_TO_PIN(1, 16) +# define WIFI_RST_GPIO GPIO_TO_PIN(0, 27) +# define ZIGBEE_RST_GPIO GPIO_TO_PIN(3, 18) +# define BIDCOS_RST_GPIO GPIO_TO_PIN(1, 24) +# define Z_WAVE_RST_GPIO GPIO_TO_PIN(1, 21) +# define ENOC_RST_GPIO GPIO_TO_PIN(1, 22) + +#endif + +#define BACK_BUTTON_GPIO GPIO_TO_PIN(1, 29) +#define FRONT_BUTTON_GPIO GPIO_TO_PIN(1, 25) + +/* Reset is on GPIO pin 29 of GPIO bank 1 */ +#define RESET_MASK (0x1 << 29) + +#define HDR_MAGIC 0x43485342 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 +#define HDR_REV_LEN 8 +#define HDR_SER_LEN 16 +#define HDR_ROOT_LEN 12 +#define HDR_FATC_LEN 12 + +/* +* SHC parameters held in On-Board I²C EEPROM device. +* +* Header Format +* +* Name Size Contents +*------------------------------------------------------------- +* Magic 4 0x42 0x53 0x48 0x43 [BSHC] +* +* Version 2 0x0100 for v1.0 +* +* Lenght 2 The length of the complete structure, not only this header +* +* Eth-MAC 6 Ethernet MAC Address +* SHC Pool: 7C:AC:B2:00:10:01 - TBD +* +* --- Further values follow, not important for Bootloader --- +*/ + +struct shc_eeprom { + u32 magic; + u16 version; + u16 lenght; + uint8_t mac_addr[HDR_ETH_ALEN]; +}; + +void enable_uart0_pin_mux(void); +void enable_shc_board_pin_mux(void); +void enable_shc_board_pwm_pin_mux(void); + +#endif diff --git a/board/bosch/shc/mux.c b/board/bosch/shc/mux.c new file mode 100644 index 00000000000..e8ada6540c0 --- /dev/null +++ b/board/bosch/shc/mux.c @@ -0,0 +1,261 @@ +/* + * mux.c + * + * (C) Copyright 2016 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */ + {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_CTS */ + {OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)}, /* UART0_RTS */ + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)}, /* UART1_TXD */ + {OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART1_CTS */ + {OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)}, /* UART1_RTS */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDDIS)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux spi1_pin_mux[] = { + {OFFSET(mcasp0_aclkx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_SCLK */ + {OFFSET(mcasp0_fsx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D0 */ + {OFFSET(mcasp0_axr0), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D1 */ + {OFFSET(mcasp0_ahclkr), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_CS0 */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(gpmc_wpn), (MODE(6) | PULLUP_EN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_CMD */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDDIS)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUDDIS)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {-1}, +}; + +static struct module_pin_mux mmc2_pin_mux[] = { + {OFFSET(gpmc_ad12), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT0 */ + {OFFSET(gpmc_ad13), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT1 */ + {OFFSET(gpmc_ad14), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT2 */ + {OFFSET(gpmc_ad15), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT3 */ + {OFFSET(gpmc_csn3), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CMD */ + {OFFSET(gpmc_clk), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CLK */ + {-1}, +}; +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux gpio0_7_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUP_EN)}, /* GPIO0_7 */ + {-1}, +}; + +static struct module_pin_mux jtag_pin_mux[] = { + {OFFSET(xdma_event_intr0), (MODE(6) | RXACTIVE | PULLUDDIS)}, + {OFFSET(xdma_event_intr1), (MODE(6) | RXACTIVE | PULLUDDIS)}, + {OFFSET(nresetin_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(tdo), (MODE(0) | PULLUP_EN)}, + {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ntrst), (MODE(0) | RXACTIVE)}, + {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)}, + {OFFSET(rsvd2), (MODE(0) | PULLUP_EN)}, + {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)}, + {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN)}, + {OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux gpio_pin_mux[] = { + {OFFSET(gpmc_ad8), (MODE(7) | PULLUDDIS)}, /* gpio0[22] - LED_PWR_BL (external pull-down) */ + {OFFSET(gpmc_ad9), (MODE(7) | PULLUDDIS)}, /* gpio0[23] - LED_PWR_RD (external pull-down) */ + {OFFSET(gpmc_ad10), (MODE(7) | PULLUDDIS)}, /* gpio0[26] - LED_LAN_RD (external pull-down) */ + {OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)}, /* gpio0[27] - #WIFI_RST (external pull-down) */ + {OFFSET(gpmc_a0), (MODE(7) | PULLUDDIS)}, /* gpio1[16] - WIFI_REGEN */ + {OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS)}, /* gpio1[17] - LED_LAN_BL */ + {OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS)}, /* gpio1[18] - LED_Cloud_BL */ + {OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS)}, /* gpio1[19] - LED_PWM as GPIO */ + {OFFSET(gpmc_a4), (MODE(7))}, /* gpio1[20] - #eMMC_RST */ + {OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)}, /* gpio1[21] - #Z-Wave_RST */ + {OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)}, /* gpio1[22] - ENOC_RST */ + {OFFSET(gpmc_a7), (MODE(7) | PULLUP_EN)}, /* gpio1[23] - WIFI_MODE */ + {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[24] - #BIDCOS_RST */ + {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[25] - USR_BUTTON */ + {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[26] - #USB1_OC */ + {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[27] - BIDCOS_PROG */ + {OFFSET(gpmc_be1n), (MODE(7) | PULLUP_EN)}, /* gpio1[28] - ZIGBEE_PC7 */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[29] - RESET_BUTTON */ + {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS)}, /* gpio2[2] - LED_Cloud_RD */ + {OFFSET(gpmc_oen_ren), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* gpio2[3] - #WIFI_POR */ + {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, /* gpio2[4] - N/C */ + {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)}, /* gpio2[5] - EEPROM_WP */ + {OFFSET(lcd_data0), (MODE(7) | PULLUDDIS)}, /* gpio2[6] */ + {OFFSET(lcd_data1), (MODE(7) | PULLUDDIS)}, /* gpio2[7] */ + {OFFSET(lcd_data2), (MODE(7) | PULLUDDIS)}, /* gpio2[8] */ + {OFFSET(lcd_data3), (MODE(7) | PULLUDDIS)}, /* gpio2[9] */ + {OFFSET(lcd_data4), (MODE(7) | PULLUDDIS)}, /* gpio2[10] */ + {OFFSET(lcd_data5), (MODE(7) | PULLUDDIS)}, /* gpio2[11] */ + {OFFSET(lcd_data6), (MODE(7) | PULLUDDIS)}, /* gpio2[12] */ + {OFFSET(lcd_data7), (MODE(7) | PULLUDDIS)}, /* gpio2[13] */ + {OFFSET(lcd_data8), (MODE(7) | PULLUDDIS)}, /* gpio2[14] */ + {OFFSET(lcd_data9), (MODE(7) | PULLUDDIS)}, /* gpio2[15] */ + {OFFSET(lcd_data10), (MODE(7) | PULLUDDIS)}, /* gpio2[16] */ + {OFFSET(lcd_data11), (MODE(7) | PULLUDDIS)}, /* gpio2[17] */ + {OFFSET(lcd_data12), (MODE(7) | PULLUDDIS)}, /* gpio0[8] */ + {OFFSET(lcd_data13), (MODE(7) | PULLUDDIS)}, /* gpio0[9] */ + {OFFSET(lcd_data14), (MODE(7) | PULLUDDIS)}, /* gpio0[10] */ + {OFFSET(lcd_data15), (MODE(7) | PULLUDDIS)}, /* gpio0[11] */ + {OFFSET(lcd_vsync), (MODE(7) | PULLUDDIS)}, /* gpio2[22] */ + {OFFSET(lcd_hsync), (MODE(7) | PULLUDDIS)}, /* gpio2[23] */ + {OFFSET(lcd_pclk), (MODE(7) | PULLUDDIS)}, /* gpio2[24] */ + {OFFSET(lcd_ac_bias_en), (MODE(7) | PULLUDDIS)},/* gpio2[25] */ + {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS)}, /* gpio0[4] */ + {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)}, /* gpio0[5] */ + {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS)}, /* gpio3[18] - #ZIGBEE_RST */ + {OFFSET(mcasp0_fsr), (MODE(7)) | PULLUDDIS}, /* gpio3[19] - ZIGBEE_BOOT */ + {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)}, /* gpio3[19] - ZIGBEE_BOOT */ + {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE | PULLUP_EN)},/* gpio3[21] - ZIGBEE_PC5 */ + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, + {OFFSET(mii1_txen), MODE(0)}, + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, + {OFFSET(mii1_txd3), MODE(0)}, + {OFFSET(mii1_txd2), MODE(0)}, + {OFFSET(mii1_txd1), MODE(0) | RXACTIVE}, + {OFFSET(mii1_txd0), MODE(0) | RXACTIVE}, + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, + {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, + {-1}, +}; + +static struct module_pin_mux pwm_pin_mux[] = { + {OFFSET(gpmc_a3), (MODE(6) | PULLUDDIS)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart1_pin_mux(void) +{ + configure_module_pin_mux(uart1_pin_mux); +} + +void enable_uart2_pin_mux(void) +{ + configure_module_pin_mux(uart2_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ +} + +void enable_uart4_pin_mux(void) +{ + configure_module_pin_mux(uart4_pin_mux); +} + +void enable_uart5_pin_mux(void) +{ +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_shc_board_pwm_pin_mux(void) +{ + configure_module_pin_mux(pwm_pin_mux); +} + +void enable_shc_board_pin_mux(void) +{ + /* Do board-specific muxes. */ + if (board_is_c3_sample() || board_is_series()) { + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(mmc1_pin_mux); + configure_module_pin_mux(mmc2_pin_mux); + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(gpio0_7_pin_mux); + configure_module_pin_mux(gpio_pin_mux); + configure_module_pin_mux(uart1_pin_mux); + configure_module_pin_mux(uart2_pin_mux); + configure_module_pin_mux(uart4_pin_mux); + configure_module_pin_mux(spi1_pin_mux); + configure_module_pin_mux(jtag_pin_mux); + } else { + puts("Unknown board, cannot configure pinmux."); + hang(); + } +} diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig new file mode 100644 index 00000000000..2c7091b5847 --- /dev/null +++ b/configs/am335x_shc_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM335X_SHC=y +CONFIG_SERIES=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=0 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n" +CONFIG_AUTOBOOT_DELAY_STR="shc" +CONFIG_AUTOBOOT_STOP_STR="noautoboot" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig new file mode 100644 index 00000000000..ffda4d2ce77 --- /dev/null +++ b/configs/am335x_shc_ict_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM335X_SHC=y +CONFIG_SHC_ICT=y +CONFIG_SERIES=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=0 +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n" +CONFIG_AUTOBOOT_DELAY_STR="shc" +CONFIG_AUTOBOOT_STOP_STR="noautoboot" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig new file mode 100644 index 00000000000..54558b68a57 --- /dev/null +++ b/configs/am335x_shc_netboot_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM335X_SHC=y +CONFIG_SHC_NETBOOT=y +CONFIG_SERIES=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=0 +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n" +CONFIG_AUTOBOOT_DELAY_STR="shc" +CONFIG_AUTOBOOT_STOP_STR="noautoboot" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_shc_prompt_defconfig b/configs/am335x_shc_prompt_defconfig new file mode 100644 index 00000000000..a415ab471f9 --- /dev/null +++ b/configs/am335x_shc_prompt_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM335X_SHC=y +CONFIG_SERIES=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=5 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n" +CONFIG_AUTOBOOT_DELAY_STR="shc" +CONFIG_AUTOBOOT_STOP_STR="noautoboot" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig new file mode 100644 index 00000000000..944256fe9c6 --- /dev/null +++ b/configs/am335x_shc_sdboot_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM335X_SHC=y +CONFIG_SHC_SDBOOT=y +CONFIG_SERIES=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=0 +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n" +CONFIG_AUTOBOOT_DELAY_STR="shc" +CONFIG_AUTOBOOT_STOP_STR="noautoboot" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_shc_sdboot_prompt_defconfig b/configs/am335x_shc_sdboot_prompt_defconfig new file mode 100644 index 00000000000..27670124293 --- /dev/null +++ b/configs/am335x_shc_sdboot_prompt_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM335X_SHC=y +CONFIG_SHC_SDBOOT=y +CONFIG_SERIES=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=5 +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n" +CONFIG_AUTOBOOT_DELAY_STR="shc" +CONFIG_AUTOBOOT_STOP_STR="noautoboot" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h new file mode 100644 index 00000000000..f2484cb1702 --- /dev/null +++ b/include/configs/am335x_shc.h @@ -0,0 +1,340 @@ +/* + * (C) Copyright 2016 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_AM335X_SHC_H +#define __CONFIG_AM335X_SHC_H + +#include + +/* settings we don;t want on this board */ +#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC +#undef CONFIG_CMD_EXT4 +#undef CONFIG_CMD_EXT4_WRITE +#undef CONFIG_CMD_MMC_SPI +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_PXE + +#define CONFIG_CMD_CACHE + +#ifndef CONFIG_SPL_BUILD +# define CONFIG_TIMESTAMP +# define CONFIG_LZO +#endif + +#define CONFIG_SYS_BOOTM_LEN (16 << 20) + +#define MACH_TYPE_BOSCH_SHC_B 9001 +#define MACH_TYPE_BOSCH_SHC_B2 9002 +#define MACH_TYPE_BOSCH_SHC_C 9003 +#define MACH_TYPE_BOSCH_SHC_C2 9004 +#define MACH_TYPE_BOSCH_SHC_C3 9005 +#define MACH_TYPE_BOSCH_SHC 9006 +#ifdef CONFIG_B_SAMPLE +# define CONFIG_MACH_TYPE MACH_TYPE_BOSCH_SHC_B +#elif defined CONFIG_B2_SAMPLE +# define CONFIG_MACH_TYPE MACH_TYPE_BOSCH_SHC_B2 +#elif defined CONFIG_C_SAMPLE +# define CONFIG_MACH_TYPE MACH_TYPE_BOSCH_SHC_C +#elif defined CONFIG_C2_SAMPLE +# define CONFIG_MACH_TYPE MACH_TYPE_BOSCH_SHC_C2 +#elif defined CONFIG_C3_SAMPLE +# define CONFIG_MACH_TYPE MACH_TYPE_BOSCH_SHC_C3 +#elif defined CONFIG_SERIES +# define CONFIG_MACH_TYPE MACH_TYPE_BOSCH_SHC +#endif /* #ifdef CONFIG_B_SAMPLE */ + +#define CONFIG_BOARD_LATE_INIT + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_VERSION_VARIABLE + +#define CONFIG_ENV_IS_IN_MMC 1 + +/* + * in case of SD Card or Network boot we want to have a possibility to + * debrick the shc, therefore do not read environment from eMMC + */ +#if defined(CONFIG_SHC_SDBOOT) || defined(CONFIG_SHC_NETBOOT) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#else +#define CONFIG_SYS_MMC_ENV_DEV 1 +#endif + +/* + * Info when using boot partitions: As environment resides within first + * 128 kB, MLO must start at 128 kB == 0x20000 + * ENV at MMC Boot0 Partition - 0/Undefined=user, 1=boot0, 2=boot1, + * 4..7=general0..3 + */ +#define CONFIG_ENV_SIZE 0x1000 /* 4 KB */ +#define CONFIG_ENV_OFFSET 0x7000 /* 28 kB */ + +#define CONFIG_HSMMC2_8BIT + +#define CONFIG_ENV_OFFSET_REDUND 0x9000 /* 36 kB */ +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_ISO_PARTITION +#endif +#ifndef CONFIG_SHC_ICT +/* + * In builds other than ICT, reset to retry after timeout + * Define a timeout after which a stopped bootloader continues autoboot + * (only works with CONFIG_RESET_TO_RETRY) + */ +# define CONFIG_BOOT_RETRY_TIME 30 +# define CONFIG_RESET_TO_RETRY +#endif + +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "kloadaddr=0x84000000\0" \ + "fdtaddr=0x85000000\0" \ + "fdt_high=0xffffffff\0" \ + "rdaddr=0x81000000\0" \ + "bootfile=uImage\0" \ + "fdtfile=am335x-shc.dtb\0" \ + "verify=no\0" \ + "serverip=10.55.152.184\0" \ + "rootpath=/srv/nfs/shc-rootfs\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=quiet\0" \ + "mmcdev=1\0" \ + "harakiri=0\0" \ + "mmcpart=2\0" \ + "active_root=root1\0" \ + "inactive_root=root2\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "nfsopts=nolock\0" \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ + "ip_method=none\0" \ + "bootargs_defaults=setenv bootargs " \ + "console=${console} " \ + "${optargs}\0" \ + "mmcargs=run bootargs_defaults;" \ + "setenv bootargs ${bootargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype} ip=${ip_method}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=if fatload mmc ${mmcdev} ${loadaddr} ${bootenv}; then " \ + "echo Loaded environment from ${bootenv}; " \ + "run importbootenv; " \ + "fi;\0" \ + "importbootenv=echo Importing environment variables from uEnv.txt ...; " \ + "env import -t $loadaddr $filesize\0" \ + "loaduimagefat=fatload mmc ${mmcdev} ${kloadaddr} ${bootfile}\0" \ + "loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${kloadaddr} /boot/${bootfile}\0" \ + "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdtaddr} /boot/${fdtfile}\0" \ + "netloaduimage=tftp ${loadaddr} ${bootfile}\0" \ + "netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \ + "mmcboot=echo Booting Linux from ${mmcdevice} ...; " \ + "run mmcargs; " \ + "if run loadfdt; then " \ + "echo device tree detected; " \ + "bootm ${kloadaddr} - ${fdtaddr}; " \ + "else " \ + "bootm ${kloadaddr}; " \ + "fi; \0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "run netloaduimage; " \ + "run netargs; " \ + "echo NFS path: ${serverip}:${rootpath};" \ + "if run netloadfdt; then " \ + "echo device tree detected; " \ + "bootm ${loadaddr} - ${fdtaddr}; " \ + "else " \ + "bootm ${loadaddr}; " \ + "fi; \0" \ + "emmc_erase=if test ${harakiri} = 1 ; then echo erase emmc ...; setenv mmcdev 1; mmc erase 0 200; reset; fi; \0" \ + "mmcpart_gp=mmcpart gp 1 40; \0" \ + "mmcpart_enhance=mmcpart enhance 0 64; \0" \ + "mmcpart_rel_write=mmcpart rel_write 1f; \0" \ + "mmcpart_commit=mmcpart commit 1; \0" \ + "mmc_hw_part=run mmcpart_gp; run mmcpart_enhance; run mmcpart_rel_write; run mmcpart_commit; \0" \ + "led_success=gpio set 22; \0" \ + "fusecmd=mmc dev 1; if mmcpart iscommitted; then echo HW Partitioning already committed; mmcpart list; else run mmc_hw_part; fi; run led_success; \0" \ + "uenv_exec=if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi;\0" \ + "sd_setup=echo SD/MMC-Card detected on device 0; " \ + "setenv mmcdevice SD; " \ + "setenv mmcdev 0; " \ + "setenv mmcpart 2; " \ + "setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0" \ + "emmc_setup=echo eMMC detected on device 1; " \ + "setenv mmcdevice eMMC; " \ + "setenv mmcdev 1; " \ + "run emmc_erase; " \ + "if test ${active_root} = root2; then " \ + "echo Active root is partition 6 (root2); " \ + "setenv mmcpart 6; " \ + "else " \ + "echo Active root is partition 5 (root1); " \ + "setenv mmcpart 5; " \ + "fi; " \ + "setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0" +#endif /* #ifndef CONFIG_SPL_BUILD */ + +#if defined CONFIG_SHC_NETBOOT +/* Network Boot */ +# define CONFIG_BOOTCOMMAND \ + "run fusecmd; " \ + "if run netboot; then " \ + "echo Booting from network; " \ + "else " \ + "echo ERROR: Cannot boot from network!; " \ + "panic; " \ + "fi; " + +#elif defined CONFIG_SHC_SDBOOT /* !defined CONFIG_SHC_NETBOOT */ +/* SD-Card Boot */ +# define CONFIG_BOOTCOMMAND \ + "if mmc dev 0; mmc rescan; then " \ + "run sd_setup; " \ + "else " \ + "echo ERROR: SD/MMC-Card not detected!; " \ + "panic; " \ + "fi; " \ + "if run loaduimage; then " \ + "echo Bootable SD/MMC-Card inserted, booting from it!; " \ + "run mmcboot; " \ + "else " \ + "echo ERROR: Unable to load uImage from SD/MMC-Card!; " \ + "panic; " \ + "fi; " + +#elif defined CONFIG_SHC_ICT +/* ICT adapter boots only u-boot and does HW partitioning */ +# define CONFIG_BOOTCOMMAND \ + "if mmc dev 0; mmc rescan; then " \ + "run sd_setup; " \ + "else " \ + "echo ERROR: SD/MMC-Card not detected!; " \ + "panic; " \ + "fi; " \ + "run fusecmd; " + +#else /* !defined CONFIG_SHC_NETBOOT, !defined CONFIG_SHC_SDBOOT */ +/* Regular Boot from internal eMMC */ +# define CONFIG_BOOTCOMMAND \ + "if mmc dev 1; mmc rescan; then " \ + "run emmc_setup; " \ + "else " \ + "echo ERROR: eMMC device not detected!; " \ + "panic; " \ + "fi; " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else " \ + "echo ERROR Unable to load uImage from eMMC!; " \ + "echo Performing Rollback!; " \ + "setenv _active_ ${active_root}; " \ + "setenv _inactive_ ${inactive_root}; " \ + "setenv active_root ${_inactive_}; " \ + "setenv inactive_root ${_active_}; " \ + "saveenv; " \ + "reset; " \ + "fi; " + +#endif /* Regular Boot */ + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_CONS_INDEX 1 + +/* PMIC support */ +#define CONFIG_POWER_TPS65217 + +/* SPL */ +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#ifndef CONFIG_SPL_USBETH_SUPPORT +/* To support eMMC booting */ +#define CONFIG_STORAGE_EMMC +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 +#endif + +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_MMC +#undef CONFIG_TIMER +#endif + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 0 +#define CONFIG_PHY_SMSC + +/* I2C configuration */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 1 + +#define CONFIG_SHOW_BOOT_PROGRESS + +#if defined CONFIG_SHC_NETBOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ETH_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_IS_IN_MMC +#endif +#endif +#endif /* ! __CONFIG_AM335X_SHC_H */ -- cgit v1.3.1 From 3c5d51fffc92417b38a2c94f4253e9a8a04100b8 Mon Sep 17 00:00:00 2001 From: Samuel Egli Date: Tue, 7 Jun 2016 08:55:39 +0200 Subject: siemens,am33x: add ubi fastmap support From: Samuel Egli Signed-off-by: Heiko Schocher --- include/configs/siemens-am33x-common.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index dfc928d33b8..ae26dad4aa6 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -288,6 +288,8 @@ #define CONFIG_LZO #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS +#define CONFIG_MTD_UBI_FASTMAP +#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1 #endif /* Commen environment */ -- cgit v1.3.1 From 6b3943f1b04be60f147ee540fbd72c4c7ea89f80 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 7 Jun 2016 08:55:45 +0200 Subject: siemens,am33x: add draco etamin board In the draco CPU board family, etamin is a new variant with bigger flash and more RAM. Due to new flash that uses larger pages (4K) some changes are necessary because it impacts the MTD partition layout and the ubi mount parameters. Signed-off-by: Samuel Egli Signed-off-by: Heiko Schocher [trini: Move BOOTDELAY into defconfig, just always be 3 now] Signed-off-by: Tom Rini --- arch/arm/Kconfig | 5 + board/siemens/common/board.c | 4 + board/siemens/draco/Kconfig | 16 ++ board/siemens/draco/MAINTAINERS | 1 + board/siemens/draco/board.c | 39 ++++- board/siemens/draco/mux.c | 2 +- configs/etamin_defconfig | 18 +++ include/configs/draco.h | 1 + include/configs/etamin.h | 257 +++++++++++++++++++++++++++++++++ include/configs/pxm2.h | 1 + include/configs/rastaban.h | 1 + include/configs/rut.h | 1 + include/configs/siemens-am33x-common.h | 5 +- include/configs/thuban.h | 1 + 14 files changed, 348 insertions(+), 4 deletions(-) create mode 100644 configs/etamin_defconfig create mode 100644 include/configs/etamin.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 26ccf628299..e75c4c0fa6d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -361,6 +361,11 @@ config TARGET_RASTABAN select CPU_V7 select SUPPORT_SPL +config TARGET_ETAMIN + bool "Support etamin" + select CPU_V7 + select SUPPORT_SPL + config TARGET_PXM2 bool "Support pxm2" select CPU_V7 diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index c127f6ca271..9cafcea53a3 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -83,8 +83,12 @@ int board_init(void) #ifdef CONFIG_FACTORYSET factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR); #endif + gpmc_init(); +#ifdef CONFIG_NAND_CS_INIT + board_nand_cs_init(); +#endif #ifdef CONFIG_VIDEO board_video_init(); #endif diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig index 819d187087f..a699c7d46f7 100644 --- a/board/siemens/draco/Kconfig +++ b/board/siemens/draco/Kconfig @@ -45,3 +45,19 @@ config SYS_CONFIG_NAME default "rastaban" endif + +if TARGET_ETAMIN + +config SYS_BOARD + default "draco" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "etamin" + +endif diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS index 484dd739c1f..e9107f08bfa 100644 --- a/board/siemens/draco/MAINTAINERS +++ b/board/siemens/draco/MAINTAINERS @@ -4,6 +4,7 @@ S: Maintained F: board/siemens/draco/ F: include/configs/draco.h F: configs/draco_defconfig +F: configs/etamin_defconfig F: include/configs/thuban.h F: configs/thuban_defconfig F: include/configs/rastaban.h diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c index 41bdef0f6be..d8869a09dd0 100644 --- a/board/siemens/draco/board.c +++ b/board/siemens/draco/board.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -33,6 +34,7 @@ #include #include "board.h" #include "../common/factoryset.h" +#include DECLARE_GLOBAL_DATA_PTR; @@ -40,6 +42,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct draco_baseboard_id __attribute__((section(".data"))) settings; #if DDR_PLL_FREQ == 303 +#if !defined(CONFIG_TARGET_ETAMIN) /* Default@303MHz-i0 */ const struct ddr3_data ddr3_default = { 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F, @@ -48,6 +51,16 @@ const struct ddr3_data ddr3_default = { "default name @303MHz \0", "default marking \0", }; +#else +/* etamin board */ +const struct ddr3_data ddr3_default = { + 0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F, + 0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2, + 0x0000093B, 0x0000018A, + "test-etamin \0", + "generic-8Gbit \0", +}; +#endif #elif DDR_PLL_FREQ == 400 /* Default@400MHz-i0 */ const struct ddr3_data ddr3_default = { @@ -210,6 +223,7 @@ struct ctrl_ioregs draco_ddr3_ioregs = { draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 = settings.ddr3.emif_ddr_phy_ctlr_1; draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config; + draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000; draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl; draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0; @@ -251,6 +265,10 @@ int board_late_init(void) nand_curr_device = 0; omap_nand_switch_ecc(1, ecc_type); +#ifdef CONFIG_TARGET_ETAMIN + nand_curr_device = 1; + omap_nand_switch_ecc(1, ecc_type); +#endif #ifdef CONFIG_FACTORYSET /* Set ASN in environment*/ if (factory_dat.asn[0] != 0) { @@ -326,7 +344,7 @@ int board_eth_init(bd_t *bis) } static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]) + char *const argv[]) { /* Reset SMSC LAN9303 switch for default configuration */ gpio_request(GPIO_LAN9303_NRST, "nRST"); @@ -346,4 +364,23 @@ U_BOOT_CMD( #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ +#ifdef CONFIG_NAND_CS_INIT +/* GPMC definitions for second nand cs1 */ +static const u32 gpmc_nand_config[] = { + ETAMIN_NAND_GPMC_CONFIG1, + ETAMIN_NAND_GPMC_CONFIG2, + ETAMIN_NAND_GPMC_CONFIG3, + ETAMIN_NAND_GPMC_CONFIG4, + ETAMIN_NAND_GPMC_CONFIG5, + ETAMIN_NAND_GPMC_CONFIG6, + /*CONFIG7- computed as params */ +}; + +static void board_nand_cs_init(void) +{ + enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1], + 0x18000000, GPMC_SIZE_16M); +} +#endif + #include "../common/board.c" diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c index dbcc80b61ff..38a484eb432 100644 --- a/board/siemens/draco/mux.c +++ b/board/siemens/draco/mux.c @@ -51,6 +51,7 @@ static struct module_pin_mux nand_pin_mux[] = { {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_csn1), MODE(0) | PULLUDEN | PULLUP_EN}, /* NAND_CS1 */ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ @@ -68,7 +69,6 @@ static struct module_pin_mux gpios_pin_mux[] = { {OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/ {OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/ /* Triacs initial HW Rev */ - {OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_30 Y0 */ {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */ {OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */ {OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */ diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig new file mode 100644 index 00000000000..6c747df66b4 --- /dev/null +++ b/configs/etamin_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_TARGET_ETAMIN=y +CONFIG_SPL=y +CONFIG_BOOTDELAY=3 +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" +CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/draco.h b/include/configs/draco.h index 5d866c48685..889178c2834 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -73,6 +73,7 @@ /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=draco\0" \ + "ubi_off=2048\0"\ "nand_img_size=0x400000\0" \ "optargs=\0" \ "preboot=draco_led 0\0" \ diff --git a/include/configs/etamin.h b/include/configs/etamin.h new file mode 100644 index 00000000000..4919cfe3536 --- /dev/null +++ b/include/configs/etamin.h @@ -0,0 +1,257 @@ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ETAMIN_H +#define __CONFIG_ETAMIN_H + +#include "siemens-am33x-common.h" +/* NAND specific changes for etamin due to different page size */ +#undef CONFIG_SYS_NAND_PAGE_SIZE +#undef CONFIG_SYS_NAND_OOBSIZE +#undef CONFIG_SYS_NAND_BLOCK_SIZE +#undef CONFIG_SYS_NAND_ECCPOS +#undef CONFIG_SYS_NAND_U_BOOT_OFFS +#undef CONFIG_SYS_ENV_SECT_SIZE +#undef CONFIG_ENV_OFFSET +#undef CONFIG_NAND_OMAP_ECCSCHEME +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW + +#define CONFIG_ENV_OFFSET 0x980000 +#define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */ +#define CONFIG_SYS_NAND_PAGE_SIZE 4096 +#define CONFIG_SYS_NAND_OOBSIZE 224 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ + 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ + 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \ + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \ + 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \ + 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ + 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \ + 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \ + 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \ + 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \ + 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \ + 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \ + 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \ + 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \ + 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ + 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ + } + +#undef CONFIG_SYS_NAND_ECCSIZE +#undef CONFIG_SYS_NAND_ECCBYTES +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 26 + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 + +#define CONFIG_SYS_NAND_MAX_CHIPS 1 + +#undef CONFIG_SYS_MAX_NAND_DEVICE +#define CONFIG_SYS_MAX_NAND_DEVICE 3 +#define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */ +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ + CONFIG_SYS_NAND_BASE2} + +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_SYS_MPUCLK 300 +#define DDR_PLL_FREQ 303 +#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC + +/* FWD Button = 27 + * SRV Button = 87 */ +#define BOARD_DFU_BUTTON_GPIO 27 +#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ +/* In dfu mode keep led1 on */ +#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + "button_dfu0=27\0" \ + "button_dfu1=87\0" \ + "led0=3,0,1\0" \ + "led1=4,0,0\0" \ + "led2=5,0,1\0" \ + "led3=87,0,1\0" \ + "led4=60,0,1\0" \ + "led5=63,0,1\0" + +#undef CONFIG_DOS_PARTITION +#undef CONFIG_CMD_FAT + +#define CONFIG_BOARD_LATE_INIT + +/* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define EEPROM_ADDR_DDR3 0x90 +#define EEPROM_ADDR_CHIP 0x120 + +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 + +#undef CONFIG_SPL_NET_SUPPORT +#undef CONFIG_SPL_NET_VCI_STRING +#undef CONFIG_SPL_ETH_SUPPORT + +#undef CONFIG_MII +#undef CONFIG_PHY_GIGE +#define CONFIG_PHY_SMSC + +#define CONFIG_FACTORYSET + +/* use both define to compile a SPL compliance test */ +/* +#define CONFIG_SPL_CMT +#define CONFIG_SPL_CMT_DEBUG +*/ + +/* nedded by compliance test in read mode */ +#if defined(CONFIG_SPL_CMT) +#define CONFIG_SYS_DCACHE_OFF +#endif + +/* Watchdog */ +#define CONFIG_OMAP_WATCHDOG + +/* Define own nand partitions */ +#define CONFIG_ENV_OFFSET_REDUND 0xB80000 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) + + + +#define CONFIG_DFU_MTD +#undef COMMON_ENV_DFU_ARGS +#define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \ + "setenv bootargs ${bootargs};" \ + "mtdparts default;" \ + "draco_led 1;" \ + "dfu 0 mtd 0;" \ + "draco_led 0;\0" \ + +#undef DFU_ALT_INFO_NAND_V2 +#define DFU_ALT_INFO_NAND_V2 \ + "spl mtddev;" \ + "spl.backup1 mtddev;" \ + "spl.backup2 mtddev;" \ + "spl.backup3 mtddev;" \ + "u-boot mtddev;" \ + "u-boot.env0 mtddev;" \ + "u-boot.env1 mtddev;" \ + "rootfs mtddevubi" \ + +#undef MTDIDS_NAME_STR +#define MTDIDS_NAME_STR "omap2-nand_concat" +#undef MTDIDS_DEFAULT +#define MTDIDS_DEFAULT "nand2=" MTDIDS_NAME_STR + +#undef MTDPARTS_DEFAULT_V2 +#define MTDPARTS_DEFAULT_V2 "mtdparts=" MTDIDS_NAME_STR ":" \ + "512k(spl)," \ + "512k(spl.backup1)," \ + "512k(spl.backup2)," \ + "512k(spl.backup3)," \ + "7680k(u-boot)," \ + "2048k(u-boot.env0)," \ + "2048k(u-boot.env1)," \ + "2048k(mtdoops)," \ + "-(rootfs)" + +#undef MTDPARTS_DEFAULT +#define MTDPARTS_DEFAULT MTDPARTS_DEFAULT_V2 + +#undef CONFIG_ENV_SETTINGS_NAND_V2 +#define CONFIG_ENV_SETTINGS_NAND_V2 \ + "nand_active_ubi_vol=rootfs_a\0" \ + "rootfs_name=rootfs\0" \ + "kernel_name=uImage\0"\ + "nand_root_fs_type=ubifs rootwait=1\0" \ + "nand_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv ${partitionset_active} true;" \ + "if test -n ${A}; then " \ + "setenv nand_active_ubi_vol ${rootfs_name}_a;" \ + "fi;" \ + "if test -n ${B}; then " \ + "setenv nand_active_ubi_vol ${rootfs_name}_b;" \ + "fi;" \ + "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ + "ubi.mtd=rootfs,${ubi_off};" \ + "setenv bootargs ${bootargs} " \ + "root=${nand_root} noinitrd ${mtdparts} " \ + "rootfstype=${nand_root_fs_type} ip=${ip_method} " \ + "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \ + "=mtdoops\0" \ + COMMON_ENV_DFU_ARGS \ + "dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \ + COMMON_ENV_NAND_BOOT \ + "ubi part rootfs ${ubi_off};" \ + "ubifsmount ubi0:${nand_active_ubi_vol};" \ + "ubifsload ${kloadaddr} boot/${kernel_name};" \ + "ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \ + "bootm ${kloadaddr} - ${loadaddr}\0" \ + "nand_boot_backup=ubifsload ${loadaddr} boot/am335x-draco.dtb;" \ + "bootm ${kloadaddr} - ${loadaddr}\0" \ + COMMON_ENV_NAND_CMDS + +#ifndef CONFIG_SPL_BUILD + +#define CONFIG_NAND_CS_INIT +#define ETAMIN_NAND_GPMC_CONFIG1 0x00000800 +#define ETAMIN_NAND_GPMC_CONFIG2 0x001e1e00 +#define ETAMIN_NAND_GPMC_CONFIG3 0x001e1e00 +#define ETAMIN_NAND_GPMC_CONFIG4 0x16051807 +#define ETAMIN_NAND_GPMC_CONFIG5 0x00151e1e +#define ETAMIN_NAND_GPMC_CONFIG6 0x16000f80 +#define CONFIG_MTD_CONCAT + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=etamin\0" \ + "ubi_off=4096\0"\ + "nand_img_size=0x400000\0" \ + "optargs=\0" \ + "preboot=draco_led 0\0" \ + CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CONFIG_ENV_SETTINGS_V2 \ + CONFIG_ENV_SETTINGS_NAND_V2 + +#ifndef CONFIG_RESTORE_FLASH + +#define CONFIG_BOOTCOMMAND \ +"if dfubutton; then " \ + "run dfu_start; " \ + "reset; " \ +"fi;" \ +"run nand_boot;" \ +"run nand_boot_backup;" \ +"reset;" + + +#else +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif +#endif /* CONFIG_SPL_BUILD */ +#endif /* ! __CONFIG_ETAMIN_H */ diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 794650a51cb..990fd84b32a 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -61,6 +61,7 @@ /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=pxm2\0" \ + "ubi_off=2048\0"\ "nand_img_size=0x500000\0" \ "optargs=\0" \ "preboot=draco_led 0\0" \ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 6c8681ab4a0..55be46bcf2c 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -76,6 +76,7 @@ /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=rastaban\0" \ + "ubi_off=2048\0"\ "nand_img_size=0x400000\0" \ "optargs=\0" \ "preboot=draco_led 0\0" \ diff --git a/include/configs/rut.h b/include/configs/rut.h index b0dcbd8c5a4..aea8e217d01 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -56,6 +56,7 @@ /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=rut\0" \ + "ubi_off=2048\0"\ "nand_img_size=0x500000\0" \ "splashpos=m,m\0" \ "optargs=fixrtc --no-log consoleblank=0 \0" \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index ae26dad4aa6..5969541de64 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -159,6 +159,7 @@ #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC +#define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) @@ -421,7 +422,7 @@ "setenv nand_src_addr ${nand_src_addr_B};" \ "fi;" \ "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ - "ubi.mtd=9,2048;" \ + "ubi.mtd=9,${ubi_off};" \ "setenv bootargs ${bootargs} " \ "root=${nand_root} noinitrd ${mtdparts} " \ "rootfstype=${nand_root_fs_type} ip=${ip_method} " \ @@ -513,7 +514,7 @@ COMMON_ENV_DFU_ARGS \ "dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \ COMMON_ENV_NAND_BOOT \ - "ubi part rootfs 2048;" \ + "ubi part rootfs ${ubi_off};" \ "ubifsmount ubi0:${nand_active_ubi_vol};" \ "ubifsload ${kloadaddr} boot/${kernel_name};" \ "ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \ diff --git a/include/configs/thuban.h b/include/configs/thuban.h index a03f87c2fb9..25ac2cba4b5 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -69,6 +69,7 @@ /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=thuban\0" \ + "ubi_off=2048\0"\ "nand_img_size=0x400000\0" \ "optargs=\0" \ "preboot=draco_led 0\0" \ -- cgit v1.3.1