From b4f3fab643324d41ff0074ebed49713ddd4009eb Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Mon, 28 Apr 2025 18:37:24 +0800 Subject: firmware: scmi: support to manage SCMI protocol drivers with a linker-genetated array U_BOOT_SCMI_PROTO_DRIVER macro is used to add a SCMI protocol driver to scmi_proto_driver list. scmi_proto_driver_get() function can be used to match a SCMI protocol id and its driver. Signed-off-by: Alice Guo --- include/scmi_agent-uclass.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include') diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h index 33e0e18c30d..842c56858af 100644 --- a/include/scmi_agent-uclass.h +++ b/include/scmi_agent-uclass.h @@ -115,4 +115,19 @@ struct scmi_agent_ops { struct scmi_msg *msg); }; +struct scmi_proto_match { + unsigned int proto_id; +}; + +struct scmi_proto_driver { + struct driver *driver; + const struct scmi_proto_match *match; +}; + +#define U_BOOT_SCMI_PROTO_DRIVER(__name, __match) \ + ll_entry_declare(struct scmi_proto_driver, __name, scmi_proto_driver) = { \ + .driver = llsym(struct driver, __name, driver), \ + .match = __match, \ + } + #endif /* _SCMI_TRANSPORT_UCLASS_H */ -- cgit v1.2.3 From 8706d383ad0ebcaf92b1dd1799b310f96cfb36f3 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Mon, 28 Apr 2025 18:37:26 +0800 Subject: pinctrl: nxp: add a pin controller driver based on SCMI pin control protocol This patch provides a pinctrl driver based on SCMI pin control protocol. Currently, only the PINCTRL_CONFIG_SET command is implemented. Signed-off-by: Ranjani Vaidyanathan Signed-off-by: Peng Fan Signed-off-by: Alice Guo Reviewed-by: Ye Li --- include/scmi_protocols.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'include') diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index 7abb2a6f36b..279ebbad440 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -24,6 +24,7 @@ enum scmi_std_protocol { SCMI_PROTOCOL_ID_SENSOR = 0x15, SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16, SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN = 0x17, + SCMI_PROTOCOL_ID_PINCTRL = 0x19, }; enum scmi_status_code { @@ -1005,4 +1006,39 @@ struct scmi_voltd_level_get_out { s32 voltage_level; }; +/* SCMI Pinctrl Protocol */ +enum scmi_pinctrl_message_id { + SCMI_MSG_PINCTRL_CONFIG_SET = 0x6 +}; + +struct scmi_pin_config { + u32 type; + u32 val; +}; + +/** + * struct scmi_pad_config_set_in - Message payload for PAD_CONFIG_SET command + * @identifier: Identifier for the pin or group. + * @function_id: Identifier for the function selected to be enabled + * for the selected pin or group. This field is set to + * 0xFFFFFFFF if no function should be enabled by the + * pin or group. + * @attributes: Bits[31:11] Reserved, must be zero. + * Bit[10] Function valid. + * Bits[9:2] Number of configurations to set. + * Bits[1:0] Selector: Whether the identifier field + * refers to a pin or a group. + * @configs: Array of configurations. + */ +struct scmi_pinctrl_config_set_in { + u32 identifier; + u32 function_id; + u32 attributes; + struct scmi_pin_config configs[4]; +}; + +struct scmi_pinctrl_config_set_out { + s32 status; +}; + #endif /* _SCMI_PROTOCOLS_H */ -- cgit v1.2.3 From bf2ea4fde7c3bcf8509fd0fe49670faa639d5d80 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Mon, 28 Apr 2025 18:37:27 +0800 Subject: firmware: scmi_agent: add SCMI pin control protocol support This patch adds SCMI pin control protocol support to make the pin controller driver based on SCMI, such as drivers/pinctrl/nxp/pinctrl-imx-scmi.c, can be bound to the SCMI agent device whose protocol id is 0x19. Signed-off-by: Alice Guo --- include/scmi_agent-uclass.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h index 842c56858af..d6586eb3ff9 100644 --- a/include/scmi_agent-uclass.h +++ b/include/scmi_agent-uclass.h @@ -27,6 +27,7 @@ struct scmi_channel; * @clock_dev: SCMI clock protocol device * @resetdom_dev: SCMI reset domain protocol device * @voltagedom_dev: SCMI voltage domain protocol device + * @pinctrl_dev: SCMI pin control protocol device */ struct scmi_agent_priv { u32 version; @@ -43,6 +44,7 @@ struct scmi_agent_priv { struct udevice *clock_dev; struct udevice *resetdom_dev; struct udevice *voltagedom_dev; + struct udevice *pinctrl_dev; }; static inline u32 scmi_version(struct udevice *dev) -- cgit v1.2.3 From 0556c2f020b4d01c40189b6aa2213e4091007189 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 28 Apr 2025 18:37:28 +0800 Subject: scmi_protocols: add SCMI misc protocol protocol_id and message_id for getting the ROM passover data SCMI misc protocol is intended for miscellaneous functions which are device specific and are usually defined to access bit fields. It is i.MX specific. This patch adds SCMI misc protocol protocol_id and message_id for getting the ROM passover data. Signed-off-by: Peng Fan Signed-off-by: Alice Guo Reviewed-by: Ye Li Reviewed-by: Marek Vasut --- include/scmi_protocols.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index 279ebbad440..06de4a601f8 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -25,6 +25,7 @@ enum scmi_std_protocol { SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16, SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN = 0x17, SCMI_PROTOCOL_ID_PINCTRL = 0x19, + SCMI_PROTOCOL_ID_IMX_MISC = 0x84, }; enum scmi_status_code { @@ -50,6 +51,10 @@ enum scmi_discovery_id { SCMI_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2, }; +enum scmi_imx_misc_message_id { + SCMI_MISC_ROM_PASSOVER_GET = 0x7 +}; + /* * SCMI Base Protocol */ -- cgit v1.2.3 From ba0f560432b5c6607ece882a37fa6a6dfffc9bc7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 28 Apr 2025 18:37:29 +0800 Subject: scmi_protocols: add SCMI Performance domain management protocol message IDs SCMI Performance domain management protocol is intended for performance management of groups of devices or APs that run in the same performance domain. The functionality provided by the callee-side can be used by passing the corresponding message_id. Signed-off-by: Peng Fan Signed-off-by: Alice Guo Reviewed-by: Ye Li Reviewed-by: Marek Vasut --- include/scmi_protocols.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'include') diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index 06de4a601f8..34f272c448c 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -1046,4 +1046,22 @@ struct scmi_pinctrl_config_set_out { s32 status; }; +/* SCMI Perf Protocol */ +enum scmi_perf_message_id { + SCMI_PERF_DOMAIN_ATTRIBUTES = 0x3, + SCMI_PERF_DESCRIBE_LEVELS = 0x4, + SCMI_PERF_LIMITS_SET = 0x5, + SCMI_PERF_LIMITS_GET = 0x6, + SCMI_PERF_LEVEL_SET = 0x7, + SCMI_PERF_LEVEL_GET = 0x8 +}; + +struct scmi_perf_in { + u32 domain_id; + u32 perf_level; +}; + +struct scmi_perf_out { + s32 status; +}; #endif /* _SCMI_PROTOCOLS_H */ -- cgit v1.2.3 From af2a671f78ee230dd81679b944ef02e9ffe2ec45 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 28 Apr 2025 18:37:30 +0800 Subject: clk: scmi: add the command CLOCK_PARENT_SET This patch adds the command CLOCK_PARENT_SET that can be used to set the parent of a clock. ARM SCMI Version 3.2 supports to change the parent of a clock device. Signed-off-by: Peng Fan Signed-off-by: Alice Guo Reviewed-by: Ye Li Reviewed-by: Marek Vasut --- include/scmi_protocols.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'include') diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index 34f272c448c..342a65ae7f4 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -737,6 +737,7 @@ enum scmi_clock_message_id { SCMI_CLOCK_RATE_SET = 0x5, SCMI_CLOCK_RATE_GET = 0x6, SCMI_CLOCK_CONFIG_SET = 0x7, + SCMI_CLOCK_PARENT_SET = 0xD, }; #define SCMI_CLK_PROTO_ATTR_COUNT_MASK GENMASK(15, 0) @@ -839,6 +840,24 @@ struct scmi_clk_rate_set_out { s32 status; }; +/** + * struct scmi_clk_parent_state_in - Message payload for CLOCK_PARENT_SET command + * @clock_id: SCMI clock ID + * @parent_clk: SCMI clock ID + */ +struct scmi_clk_parent_set_in { + u32 clock_id; + u32 parent_clk; +}; + +/** + * struct scmi_clk_parent_set_out - Response payload for CLOCK_PARENT_SET command + * @status: SCMI command status + */ +struct scmi_clk_parent_set_out { + s32 status; +}; + /* * SCMI Reset Domain Protocol */ -- cgit v1.2.3 From 15fdfef6642c8262331e22f8d9507ee5c11f027a Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Mon, 28 Apr 2025 18:37:31 +0800 Subject: clk: scmi: check the clock state/parent/rate control permissions Clock driver based on SCMI clock management protocol in Linux checks clock state, parent and rate control permissions. To be consistent with the kernel driver, add this check here. CLOCK_GET_PERMISSIONS is from ARM System Control and Management Interface Platform Design Document 3.2. When using common clock framework (CCF), use the clock signal ID to get the clock registered by clk_register() in scmi_clk_probe(), and then obatin the struct clk_scmi variable with container_of(). Signed-off-by: Alice Guo Signed-off-by: Ye Li Reviewed-by: Peng Fan --- include/scmi_protocols.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'include') diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index 342a65ae7f4..519b906b4ce 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -731,6 +731,7 @@ int scmi_pwd_name_get(struct udevice *dev, u32 domain_id, u8 **name); /* * SCMI Clock Protocol */ +#define CLOCK_PROTOCOL_VERSION_3_0 0x30000 enum scmi_clock_message_id { SCMI_CLOCK_ATTRIBUTES = 0x3, @@ -738,6 +739,7 @@ enum scmi_clock_message_id { SCMI_CLOCK_RATE_GET = 0x6, SCMI_CLOCK_CONFIG_SET = 0x7, SCMI_CLOCK_PARENT_SET = 0xD, + SCMI_CLOCK_GET_PERMISSIONS = 0xF, }; #define SCMI_CLK_PROTO_ATTR_COUNT_MASK GENMASK(15, 0) @@ -776,6 +778,7 @@ struct scmi_clk_attribute_in { struct scmi_clk_attribute_out { s32 status; u32 attributes; +#define CLK_HAS_RESTRICTIONS(x) ((x) & BIT(1)) char clock_name[SCMI_CLOCK_NAME_LENGTH_MAX]; }; @@ -858,6 +861,27 @@ struct scmi_clk_parent_set_out { s32 status; }; +/** + * @clock_id: Identifier for the clock device. + */ +struct scmi_clk_get_permissions_in { + u32 clock_id; +}; + +/** + * @status: Negative 32-bit integers are used to return error status codes. + * @permissions: Bit[31] Clock state control, Bit[30] Clock parent control, + * Bit[29] Clock rate control, Bits[28:0] Reserved, must be zero. + */ +struct scmi_clk_get_permissions_out { + s32 status; + u32 permissions; +}; + +#define SUPPORT_CLK_STAT_CONTROL BIT(31) +#define SUPPORT_CLK_PARENT_CONTROL BIT(30) +#define SUPPORT_CLK_RATE_CONTROL BIT(29) + /* * SCMI Reset Domain Protocol */ -- cgit v1.2.3 From a881951c63153de39e448a1f51f65e34b48251fd Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 28 Apr 2025 18:37:33 +0800 Subject: scmi_protocols: update struct scmi_base_discover_list_protocols_out @protocols is an array of protocol identifiers that are implemented, excluding the Base protocol. Four protocol identifiers are packed into each array element. The number of elements of @protocols is specified by callee-side. Signed-off-by: Ye Li Signed-off-by: Alice Guo --- include/scmi_protocols.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index 519b906b4ce..9046de7e3e7 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -145,7 +145,7 @@ struct scmi_base_discover_impl_version_out { struct scmi_base_discover_list_protocols_out { s32 status; u32 num_protocols; - u32 protocols[3]; + u32 protocols[]; }; /** -- cgit v1.2.3 From 5f28a6599f010333390035baa4b516d364407a53 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Mon, 28 Apr 2025 18:37:40 +0800 Subject: tools: imx8image: add i.MX95 support i.MX95 uses binman to invoke mkimage to create image container. 2 image containers are needed currently. The first one is composed of ahab-container.img, LPDDR firmware images, OEI images, System Manager image and u-boot-spl.bin. The second one is consisted of ARM Trusted firmware and u-boot.bin. Because DDR OEI image and LPDDR firmware images have to be packaged together and named as m33-oei-ddrfw.bin by binman, so imx9_image.sh does not check if m33-oei-ddrfw.bin exists. When using "make imx95_19x19_evk_defconfig; make", imx9_image.sh will delete the line for u-boot.bin in container.cfg. In fact, binman is always called after the u-boot.bin is built, so imx9_image.sh does not check if u-boot.bin exists. Signed-off-by: Alice Guo --- include/imx8image.h | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/imx8image.h b/include/imx8image.h index 6b95e93fb50..e0d25c5b6c9 100644 --- a/include/imx8image.h +++ b/include/imx8image.h @@ -157,7 +157,9 @@ enum imx8image_cmd { CMD_SOC_TYPE, CMD_CONTAINER, CMD_IMAGE, - CMD_DATA + CMD_DATA, + CMD_DUMMY_V2X, + CMD_HOLD, }; enum imx8image_core_type { @@ -169,7 +171,9 @@ enum imx8image_core_type { CFG_A35, CFG_A55, CFG_A53, - CFG_A72 + CFG_A72, + CFG_M33, + CFG_OEI, }; enum imx8image_fld_types { @@ -208,7 +212,10 @@ typedef enum option_type { FILEOFF, MSG_BLOCK, SENTINEL, - UPOWER + UPOWER, + OEI, + DUMMY_V2X, + HOLD, } option_type_t; typedef struct { @@ -227,12 +234,16 @@ typedef struct { #define CORE_CA35 4 #define CORE_CA72 5 #define CORE_SECO 6 +#define CORE_M33 7 #define CORE_ULP_CM33 0x1 #define CORE_ULP_CA35 0x2 #define CORE_ULP_UPOWER 0x4 #define CORE_ULP_SENTINEL 0x6 +#define CORE_IMX95_M33P 0 +#define CORE_IMX95_A55C0 2 + #define SC_R_OTP 357U #define SC_R_DEBUG 354U #define SC_R_ROM_0 236U @@ -246,10 +257,12 @@ typedef struct { #define IMG_TYPE_EXEC 0x03 /* Executable image type */ #define IMG_TYPE_DATA 0x04 /* Data image type */ #define IMG_TYPE_DCD_DDR 0x05 /* DCD/DDR image type */ +#define IMG_TYPE_OEI 0x05 /* Optional Executable image type */ #define IMG_TYPE_SECO 0x06 /* SECO image type */ #define IMG_TYPE_SENTINEL 0x06 /* SENTINEL image type */ #define IMG_TYPE_PROV 0x07 /* Provisioning image type */ #define IMG_TYPE_DEK 0x08 /* DEK validation type */ +#define IMG_TYPE_V2X_DUMMY 0x0E /* V2X Dummy image */ #define IMG_TYPE_SHIFT 0 #define IMG_TYPE_MASK 0x1f -- cgit v1.2.3 From 0cbd26bee49addcc05faa29cc289116a96fb11d8 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 28 Apr 2025 18:37:43 +0800 Subject: imx95_evk: add i.MX95 19x19 EVK board basic support This patch adds i.MX95 19x19 EVK board basic support. Messaging unit for EdgeLock Secure Enclave, messaging unit for System Manager, uSDHC for SD Card, gpio, lpuart are supported now. Signed-off-by: Ye Li Signed-off-by: Alice Guo Reviewed-by: Peng Fan --- include/configs/imx95_evk.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 include/configs/imx95_evk.h (limited to 'include') diff --git a/include/configs/imx95_evk.h b/include/configs/imx95_evk.h new file mode 100644 index 00000000000..2eebdadc51d --- /dev/null +++ b/include/configs/imx95_evk.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 NXP + */ + +#ifndef __IMX95_EVK_H +#define __IMX95_EVK_H + +#include +#include +#include + +#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x90000000 +#define PHYS_SDRAM 0x90000000 +/* Totally 16GB */ +#define PHYS_SDRAM_SIZE 0x70000000 /* 2GB - 256MB DDR */ +#define PHYS_SDRAM_2_SIZE 0x380000000 /* 14GB */ + +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#endif -- cgit v1.2.3