From 7c1860fce4e369bdcabc1f574feb6b9af19999a3 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 7 Jul 2022 10:45:36 +0200 Subject: lmb: Fix lmb property's defination under struct lmb Under struct lmb {} the lmb property's should be defined only if CONFIG_LMB_MEMORY_REGIONS is defined. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c24a2b1d6f5db4eb65393f6a77fae129b30b6233.1657183534.git.michal.simek@amd.com --- include/lmb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/lmb.h b/include/lmb.h index ab277ca8000..1476d78c282 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -68,7 +68,7 @@ struct lmb_region { struct lmb { struct lmb_region memory; struct lmb_region reserved; -#if !IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS) +#if IS_ENABLED(CONFIG_LMB_MEMORY_REGIONS) struct lmb_property memory_regions[CONFIG_LMB_MEMORY_REGIONS]; struct lmb_property reserved_regions[CONFIG_LMB_RESERVED_REGIONS]; #endif -- cgit v1.2.3 From 7e9c2cd4e46cb93c22ea513c24c83b07873deac6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Jul 2022 13:06:16 +0200 Subject: xilinx: Remove duplicate PMIO_NODE_ID_BASE macro PMIO_NODE_ID_BASE is defined twice that's why remove one instance. Fixes: 248fe9f302df ("spi: cadence_qspi: Enable apb linear mode for apb read & write operations") Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/ce9a601bb99418aa20272d046c74678829d942cc.1657191974.git.michal.simek@amd.com --- include/zynqmp_firmware.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 6c4fd9a6c5f..86c14d560e1 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -435,8 +435,6 @@ enum pm_gem_config_type { #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) #define PMIO_NODE_ID_BASE 0x1410801B -#define PMIO_NODE_ID_BASE 0x1410801B - /* * Return payload size * Not every firmware call expects the same amount of return bytes, however the -- cgit v1.2.3 From 165694b1254909953eea9768ea3d914555c17cc5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Jul 2022 13:10:53 +0200 Subject: dt-bindings: versal: Add versal reset IDs The same file is already the part of Linux kernel that's why add it also to u-boot to be able to use it in source code and DT files. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/1c3bc464536a9bf64a2e8bfe18a938c9cb490620.1657192249.git.michal.simek@amd.com --- include/dt-bindings/reset/xlnx-versal-resets.h | 105 +++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 include/dt-bindings/reset/xlnx-versal-resets.h (limited to 'include') diff --git a/include/dt-bindings/reset/xlnx-versal-resets.h b/include/dt-bindings/reset/xlnx-versal-resets.h new file mode 100644 index 00000000000..895424e9b0e --- /dev/null +++ b/include/dt-bindings/reset/xlnx-versal-resets.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_VERSAL_RESETS_H +#define _DT_BINDINGS_VERSAL_RESETS_H + +#define VERSAL_RST_PMC_POR (0xc30c001U) +#define VERSAL_RST_PMC (0xc410002U) +#define VERSAL_RST_PS_POR (0xc30c003U) +#define VERSAL_RST_PL_POR (0xc30c004U) +#define VERSAL_RST_NOC_POR (0xc30c005U) +#define VERSAL_RST_FPD_POR (0xc30c006U) +#define VERSAL_RST_ACPU_0_POR (0xc30c007U) +#define VERSAL_RST_ACPU_1_POR (0xc30c008U) +#define VERSAL_RST_OCM2_POR (0xc30c009U) +#define VERSAL_RST_PS_SRST (0xc41000aU) +#define VERSAL_RST_PL_SRST (0xc41000bU) +#define VERSAL_RST_NOC (0xc41000cU) +#define VERSAL_RST_NPI (0xc41000dU) +#define VERSAL_RST_SYS_RST_1 (0xc41000eU) +#define VERSAL_RST_SYS_RST_2 (0xc41000fU) +#define VERSAL_RST_SYS_RST_3 (0xc410010U) +#define VERSAL_RST_FPD (0xc410011U) +#define VERSAL_RST_PL0 (0xc410012U) +#define VERSAL_RST_PL1 (0xc410013U) +#define VERSAL_RST_PL2 (0xc410014U) +#define VERSAL_RST_PL3 (0xc410015U) +#define VERSAL_RST_APU (0xc410016U) +#define VERSAL_RST_ACPU_0 (0xc410017U) +#define VERSAL_RST_ACPU_1 (0xc410018U) +#define VERSAL_RST_ACPU_L2 (0xc410019U) +#define VERSAL_RST_ACPU_GIC (0xc41001aU) +#define VERSAL_RST_RPU_ISLAND (0xc41001bU) +#define VERSAL_RST_RPU_AMBA (0xc41001cU) +#define VERSAL_RST_R5_0 (0xc41001dU) +#define VERSAL_RST_R5_1 (0xc41001eU) +#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) +#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) +#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) +#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) +#define VERSAL_RST_SYSMON_LPD (0xc410023U) +#define VERSAL_RST_PDMA_RST1 (0xc410024U) +#define VERSAL_RST_PDMA_RST0 (0xc410025U) +#define VERSAL_RST_ADMA (0xc410026U) +#define VERSAL_RST_TIMESTAMP (0xc410027U) +#define VERSAL_RST_OCM (0xc410028U) +#define VERSAL_RST_OCM2_RST (0xc410029U) +#define VERSAL_RST_IPI (0xc41002aU) +#define VERSAL_RST_SBI (0xc41002bU) +#define VERSAL_RST_LPD (0xc41002cU) +#define VERSAL_RST_QSPI (0xc10402dU) +#define VERSAL_RST_OSPI (0xc10402eU) +#define VERSAL_RST_SDIO_0 (0xc10402fU) +#define VERSAL_RST_SDIO_1 (0xc104030U) +#define VERSAL_RST_I2C_PMC (0xc104031U) +#define VERSAL_RST_GPIO_PMC (0xc104032U) +#define VERSAL_RST_GEM_0 (0xc104033U) +#define VERSAL_RST_GEM_1 (0xc104034U) +#define VERSAL_RST_SPARE (0xc104035U) +#define VERSAL_RST_USB_0 (0xc104036U) +#define VERSAL_RST_UART_0 (0xc104037U) +#define VERSAL_RST_UART_1 (0xc104038U) +#define VERSAL_RST_SPI_0 (0xc104039U) +#define VERSAL_RST_SPI_1 (0xc10403aU) +#define VERSAL_RST_CAN_FD_0 (0xc10403bU) +#define VERSAL_RST_CAN_FD_1 (0xc10403cU) +#define VERSAL_RST_I2C_0 (0xc10403dU) +#define VERSAL_RST_I2C_1 (0xc10403eU) +#define VERSAL_RST_GPIO_LPD (0xc10403fU) +#define VERSAL_RST_TTC_0 (0xc104040U) +#define VERSAL_RST_TTC_1 (0xc104041U) +#define VERSAL_RST_TTC_2 (0xc104042U) +#define VERSAL_RST_TTC_3 (0xc104043U) +#define VERSAL_RST_SWDT_FPD (0xc104044U) +#define VERSAL_RST_SWDT_LPD (0xc104045U) +#define VERSAL_RST_USB (0xc104046U) +#define VERSAL_RST_DPC (0xc208047U) +#define VERSAL_RST_PMCDBG (0xc208048U) +#define VERSAL_RST_DBG_TRACE (0xc208049U) +#define VERSAL_RST_DBG_FPD (0xc20804aU) +#define VERSAL_RST_DBG_TSTMP (0xc20804bU) +#define VERSAL_RST_RPU0_DBG (0xc20804cU) +#define VERSAL_RST_RPU1_DBG (0xc20804dU) +#define VERSAL_RST_HSDP (0xc20804eU) +#define VERSAL_RST_DBG_LPD (0xc20804fU) +#define VERSAL_RST_CPM_POR (0xc30c050U) +#define VERSAL_RST_CPM (0xc410051U) +#define VERSAL_RST_CPMDBG (0xc208052U) +#define VERSAL_RST_PCIE_CFG (0xc410053U) +#define VERSAL_RST_PCIE_CORE0 (0xc410054U) +#define VERSAL_RST_PCIE_CORE1 (0xc410055U) +#define VERSAL_RST_PCIE_DMA (0xc410056U) +#define VERSAL_RST_CMN (0xc410057U) +#define VERSAL_RST_L2_0 (0xc410058U) +#define VERSAL_RST_L2_1 (0xc410059U) +#define VERSAL_RST_ADDR_REMAP (0xc41005aU) +#define VERSAL_RST_CPI0 (0xc41005bU) +#define VERSAL_RST_CPI1 (0xc41005cU) +#define VERSAL_RST_XRAM (0xc30c05dU) +#define VERSAL_RST_AIE_ARRAY (0xc10405eU) +#define VERSAL_RST_AIE_SHIM (0xc10405fU) + +#endif -- cgit v1.2.3 From c9f12ed9bcb973297a33f50e1fa28506118bcb91 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Fri, 22 Jul 2022 02:46:54 -0600 Subject: firmware: zynqmp: Change prototype of zynqmp_pmufw_load_config_object() zynqmp_pmufw_load_config_object() has some error cases and it is better to return those errors. Change prototype of this function to return errors. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20220722084658.30995-2-ashok.reddy.soma@xilinx.com --- include/zynqmp_firmware.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 86c14d560e1..52bc20f195e 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -447,7 +447,7 @@ enum pm_gem_config_type { unsigned int zynqmp_firmware_version(void); int zynqmp_pmufw_node(u32 id); int zynqmp_pmufw_config_close(void); -void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size); +int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size); int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload); int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value); -- cgit v1.2.3 From cce33515010287a5bd7f4b6f9ebce0f56268a7f1 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Fri, 22 Jul 2022 02:46:57 -0600 Subject: mailbox: zynqmp: Move struct zynqmp_ipi_msg from sys_proto.h Mailbox driver might be need for Versal and other future platforms. To remove the dependency, move struct zynqmp_ipi_msg to zynqmp_firmware.h so that mailbox driver compiles for other platforms easily. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20220722084658.30995-5-ashok.reddy.soma@xilinx.com --- include/zynqmp_firmware.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 52bc20f195e..f7a4a39d350 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -490,4 +490,9 @@ enum zynqmp_pm_request_ack { /* PM API versions */ #define PM_API_VERSION_2 2 +struct zynqmp_ipi_msg { + size_t len; + u32 *buf; +}; + #endif /* _ZYNQMP_FIRMWARE_H_ */ -- cgit v1.2.3 From 8c09cb6f4dc5eda57d2e9e76ee8b0f4e2e340071 Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Thu, 21 Jul 2022 15:31:22 +0200 Subject: fpga: Convert SYS_FPGA_PROG_FEEDBACK to Kconfig This converts the following to Kconfig: SYS_FPGA_PROG_FEEDBACK Signed-off-by: Alexander Dahl Link: https://lore.kernel.org/r/20220721133122.32428-3-ada@thorsis.com Signed-off-by: Michal Simek --- include/configs/astro_mcf5373l.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index a8265e961a2..da4d49741d2 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -131,7 +131,6 @@ * it needs non-blocking CFI routines. */ -#define CONFIG_SYS_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_WAIT 1000 /* End of user parameters to be customized */ -- cgit v1.2.3 From f18adf106576f298ead743a02800c6fdc90d884c Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Fri, 22 Jul 2022 17:16:03 +0300 Subject: fpga: xilinx: add missed identifier names Function definition arguments should also have identifier names. Add missed ones to struct xilinx_fpga_op callbacks, unifying code. Signed-off-by: Oleksandr Suvorov Tested-by: Ricardo Salveti Tested-by: Adrian Fiergolski Link: https://lore.kernel.org/r/20220722141614.297383-3-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek --- include/xilinx.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/xilinx.h b/include/xilinx.h index ab4537becfa..362943bc717 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -48,12 +48,14 @@ typedef struct { /* typedef xilinx_desc */ } xilinx_desc; /* end, typedef xilinx_desc */ struct xilinx_fpga_op { - int (*load)(xilinx_desc *, const void *, size_t, bitstream_type); - int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *); + int (*load)(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype); + int (*loadfs)(xilinx_desc *desc, const void *buf, size_t bsize, + fpga_fs_info *fpga_fsinfo); int (*loads)(xilinx_desc *desc, const void *buf, size_t bsize, struct fpga_secure_info *fpga_sec_info); - int (*dump)(xilinx_desc *, const void *, size_t); - int (*info)(xilinx_desc *); + int (*dump)(xilinx_desc *desc, const void *buf, size_t bsize); + int (*info)(xilinx_desc *desc); }; /* Generic Xilinx Functions -- cgit v1.2.3 From d7fcbfc19b4e83930a90c834046d4bf7dc3adefe Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Fri, 22 Jul 2022 17:16:04 +0300 Subject: fpga: xilinx: add bitstream flags to driver desc Store a set of supported bitstream types in xilinx_desc structure. It will be used to determine whether an FPGA image is able to be loaded with a given driver. Signed-off-by: Oleksandr Suvorov Tested-by: Ricardo Salveti Tested-by: Adrian Fiergolski Link: https://lore.kernel.org/r/20220722141614.297383-4-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek --- include/versalpl.h | 3 --- include/xilinx.h | 4 ++++ include/zynqmppl.h | 3 +-- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/versalpl.h b/include/versalpl.h index b94c82e6e66..0cc101be2f8 100644 --- a/include/versalpl.h +++ b/include/versalpl.h @@ -14,7 +14,4 @@ extern struct xilinx_fpga_op versal_op; -#define XILINX_VERSAL_DESC \ -{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op } - #endif /* _VERSALPL_H_ */ diff --git a/include/xilinx.h b/include/xilinx.h index 362943bc717..d9e4b8da968 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -37,6 +37,9 @@ typedef enum { /* typedef xilinx_family */ max_xilinx_type /* insert all new types before this */ } xilinx_family; /* end, typedef xilinx_family */ +/* FPGA bitstream supported types */ +#define FPGA_LEGACY BIT(0) + typedef struct { /* typedef xilinx_desc */ xilinx_family family; /* part type */ xilinx_iface iface; /* interface type */ @@ -45,6 +48,7 @@ typedef struct { /* typedef xilinx_desc */ int cookie; /* implementation specific cookie */ struct xilinx_fpga_op *operations; /* operations */ char *name; /* device name in bitstream */ + int flags; /* compatible flags */ } xilinx_desc; /* end, typedef xilinx_desc */ struct xilinx_fpga_op { diff --git a/include/zynqmppl.h b/include/zynqmppl.h index 35cfe17d444..8401a850afb 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -25,7 +25,6 @@ extern struct xilinx_fpga_op zynqmp_op; -#define XILINX_ZYNQMP_DESC \ -{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op } +#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY) #endif /* _ZYNQMPPL_H_ */ -- cgit v1.2.3 From 24307b06b71a3c9b4aa556eefdad1f8fcca116bd Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Fri, 22 Jul 2022 17:16:05 +0300 Subject: fpga: zynqmp: add str2flags call Add a call to convert FPGA "compatible" string to a binary flag. Signed-off-by: Oleksandr Suvorov Tested-by: Ricardo Salveti Tested-by: Adrian Fiergolski Link: https://lore.kernel.org/r/20220722141614.297383-5-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek --- include/xilinx.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/xilinx.h b/include/xilinx.h index d9e4b8da968..ff5486d98a7 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -60,6 +60,9 @@ struct xilinx_fpga_op { struct fpga_secure_info *fpga_sec_info); int (*dump)(xilinx_desc *desc, const void *buf, size_t bsize); int (*info)(xilinx_desc *desc); +#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE) + int (*str2flag)(xilinx_desc *desc, const char *string); +#endif }; /* Generic Xilinx Functions -- cgit v1.2.3 From 7a9a0df89bf1cb9f7e78378f946f1d9c9b002d72 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Fri, 22 Jul 2022 17:16:06 +0300 Subject: fpga: xilinx: pass compatible flags to xilinx_load() This flag is used to check whether a Xilinx FPGA driver is able to load a particular FPGA bitstream image. Signed-off-by: Oleksandr Suvorov Tested-by: Ricardo Salveti Tested-by: Adrian Fiergolski Link: https://lore.kernel.org/r/20220722141614.297383-6-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek --- include/xilinx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/xilinx.h b/include/xilinx.h index ff5486d98a7..0bbf14d8a1d 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -68,7 +68,7 @@ struct xilinx_fpga_op { /* Generic Xilinx Functions *********************************************************************/ int xilinx_load(xilinx_desc *desc, const void *image, size_t size, - bitstream_type bstype); + bitstream_type bstype, int flags); int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize); int xilinx_info(xilinx_desc *desc); int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, -- cgit v1.2.3 From 282eed50ecb73c20dd35bf3ea7a579e79b20cd54 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Fri, 22 Jul 2022 17:16:07 +0300 Subject: fpga: pass compatible flags to fpga_load() These flags may be used to check whether an FPGA driver is able to load a particular FPGA bitstream image. Signed-off-by: Oleksandr Suvorov Tested-by: Ricardo Salveti Tested-by: Adrian Fiergolski Link: https://lore.kernel.org/r/20220722141614.297383-7-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek --- include/fpga.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/fpga.h b/include/fpga.h index ec5144334df..6365e1569e3 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -64,7 +64,7 @@ int fpga_count(void); const fpga_desc *const fpga_get_desc(int devnum); int fpga_is_partial_data(int devnum, size_t img_len); int fpga_load(int devnum, const void *buf, size_t bsize, - bitstream_type bstype); + bitstream_type bstype, int flags); int fpga_fsload(int devnum, const void *buf, size_t size, fpga_fs_info *fpga_fsinfo); int fpga_loads(int devnum, const void *buf, size_t size, -- cgit v1.2.3 From 2c60514d9aecf7fbbbe3c4cb3a4a4acc421e5239 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Fri, 22 Jul 2022 17:16:08 +0300 Subject: fpga: add fpga_compatible2flag Add a "compatible" string to binary flag converter, which uses a callback str2flag() of given FPGA driver if available. Signed-off-by: Oleksandr Suvorov Tested-by: Ricardo Salveti Tested-by: Adrian Fiergolski Link: https://lore.kernel.org/r/20220722141614.297383-8-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek --- include/fpga.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fpga.h b/include/fpga.h index 6365e1569e3..13b1bbee3ca 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -75,5 +75,6 @@ int fpga_dump(int devnum, const void *buf, size_t bsize); int fpga_info(int devnum); const fpga_desc *const fpga_validate(int devnum, const void *buf, size_t bsize, char *fn); +int fpga_compatible2flag(int devnum, const char *compatible); #endif /* _FPGA_H_ */ -- cgit v1.2.3 From 3e78481de94d94f753bbf05486734b8da394643f Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Fri, 22 Jul 2022 17:16:10 +0300 Subject: fpga: xilinx: pass compatible flags to load() callback These flags may be used to check whether an FPGA driver is able to load a particular FPGA bitstream image. Signed-off-by: Oleksandr Suvorov Tested-by: Ricardo Salveti Tested-by: Adrian Fiergolski Link: https://lore.kernel.org/r/20220722141614.297383-10-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek --- include/xilinx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/xilinx.h b/include/xilinx.h index 0bbf14d8a1d..e5f6db33fa2 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -53,7 +53,7 @@ typedef struct { /* typedef xilinx_desc */ struct xilinx_fpga_op { int (*load)(xilinx_desc *desc, const void *buf, size_t bsize, - bitstream_type bstype); + bitstream_type bstype, int flags); int (*loadfs)(xilinx_desc *desc, const void *buf, size_t bsize, fpga_fs_info *fpga_fsinfo); int (*loads)(xilinx_desc *desc, const void *buf, size_t bsize, -- cgit v1.2.3 From a3a1afb747d4d71c3dd5ba01b2796cebd65c65cd Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Fri, 22 Jul 2022 17:16:13 +0300 Subject: fpga: zynqmp: support loading authenticated images Add supporting new compatible string "u-boot,zynqmp-fpga-ddrauth" to handle loading authenticated images (DDR). Based on solution by Jorge Ramirez-Ortiz Signed-off-by: Oleksandr Suvorov Tested-by: Ricardo Salveti Link: https://lore.kernel.org/r/20220722141614.297383-13-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek --- include/xilinx.h | 1 + include/zynqmppl.h | 4 ++++ 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/include/xilinx.h b/include/xilinx.h index e5f6db33fa2..97ee12cec42 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -39,6 +39,7 @@ typedef enum { /* typedef xilinx_family */ /* FPGA bitstream supported types */ #define FPGA_LEGACY BIT(0) +#define FPGA_XILINX_ZYNQMP_DDRAUTH BIT(1) typedef struct { /* typedef xilinx_desc */ xilinx_family family; /* part type */ diff --git a/include/zynqmppl.h b/include/zynqmppl.h index 8401a850afb..87ccd2f394c 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -25,6 +25,10 @@ extern struct xilinx_fpga_op zynqmp_op; +#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE) +#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY | FPGA_XILINX_ZYNQMP_DDRAUTH) +#else #define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY) +#endif #endif /* _ZYNQMPPL_H_ */ -- cgit v1.2.3 From b524f8fb1e94a8e649ba06a7cb87e6dcaa96ebc3 Mon Sep 17 00:00:00 2001 From: Adrian Fiergolski Date: Fri, 22 Jul 2022 17:16:14 +0300 Subject: fpga: zynqmp: support loading encrypted bitfiles Add supporting new compatible string "u-boot,zynqmp-fpga-enc" to handle loading encrypted bitfiles. This feature requires encrypted FSBL, as according to UG1085: "The CSU automatically locks out the AES key, stored in either BBRAM or eFUSEs, as a key source to the AES engine if the FSBL is not encrypted. This prevents using the BBRAM or eFUSE as the key source to the AES engine during run-time applications." Signed-off-by: Adrian Fiergolski Co-developed-by: Oleksandr Suvorov Signed-off-by: Oleksandr Suvorov Tested-by: Adrian Fiergolski Link: https://lore.kernel.org/r/20220722141614.297383-14-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek --- include/fpga.h | 1 + include/xilinx.h | 1 + include/zynqmppl.h | 4 +++- 3 files changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/fpga.h b/include/fpga.h index 13b1bbee3ca..a4e16401da7 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -20,6 +20,7 @@ /* device numbers must be non-negative */ #define FPGA_INVALID_DEVICE -1 +#define FPGA_ENC_DEV_KEY 0 #define FPGA_ENC_USR_KEY 1 #define FPGA_NO_ENC_OR_NO_AUTH 2 diff --git a/include/xilinx.h b/include/xilinx.h index 97ee12cec42..e4e29797988 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -40,6 +40,7 @@ typedef enum { /* typedef xilinx_family */ /* FPGA bitstream supported types */ #define FPGA_LEGACY BIT(0) #define FPGA_XILINX_ZYNQMP_DDRAUTH BIT(1) +#define FPGA_XILINX_ZYNQMP_ENC BIT(2) typedef struct { /* typedef xilinx_desc */ xilinx_family family; /* part type */ diff --git a/include/zynqmppl.h b/include/zynqmppl.h index 87ccd2f394c..acf75a8f079 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -26,7 +26,9 @@ extern struct xilinx_fpga_op zynqmp_op; #if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE) -#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY | FPGA_XILINX_ZYNQMP_DDRAUTH) +#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY | \ + FPGA_XILINX_ZYNQMP_DDRAUTH | \ + FPGA_XILINX_ZYNQMP_ENC) #else #define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY) #endif -- cgit v1.2.3