From 5c01d1c0d0e673dbd5739256e77e9dca9dc74816 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 21 Jan 2019 14:53:21 -0700 Subject: gpio: Add a simple GPIO API for SPL In space-constrained environments or before driver model is available, it is sometimes necessary to set GPIO values. Add an SPL API for this, to allow early board code to change GPIOs. The caller must provide the register address, so that the drivers can be fairly generic. This API can be implemented by GPIO drivers, behind a suitable guard, like #ifdef CONFIG_SPL_BUILD. Signed-off-by: Simon Glass Reviewed-by: Philipp Tomsich --- include/spl_gpio.h | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 include/spl_gpio.h (limited to 'include') diff --git a/include/spl_gpio.h b/include/spl_gpio.h new file mode 100644 index 00000000000..e410e62914d --- /dev/null +++ b/include/spl_gpio.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Simple GPIO access from SPL. This only supports a single GPIO space, + * typically the SoC GPIO banks. + * + * Copyright 2018 Google LLC + */ + +#ifndef __SPL_GPIO_H +#define __SPL_GPIO_H + +#include + +/* + * The functions listed here should be implemented in the SoC GPIO driver. + * They correspond to the normal GPIO API (asm-generic/gpio.h). The GPIO + * number is encoded in an unsigned int by an SoC-specific means. Pull + * values are also SoC-specific. + * + * This API should only be used in TPL/SPL where GPIO access is needed but + * driver model is not available (yet) or adds too much overhead. + * + * The caller must supply the GPIO register base since this information is + * often specific to a particular SoC generation. This allows the GPIO + * code to be fairly generic. + * + * Only a single implementation of each of these functions can be provided. + * + * The 'gpio' value can include both a bank and a GPIO number, if desired. The + * encoding is SoC-specific. + */ + +/** + * spl_gpio_set_pull() - Set the pull up/down state of a GPIO + * + * @regs: Pointer to GPIO registers + * @gpio: GPIO to adjust (SoC-specific) + * @pull: Pull value (SoC-specific) + * @return return 0 if OK, -ve on error + */ +int spl_gpio_set_pull(void *regs, uint gpio, int pull); + +/** + * spl_gpio_output() - Set a GPIO as an output + * + * @regs: Pointer to GPIO registers + * @gpio: GPIO to adjust (SoC-specific) + * @value: 0 to set the output low, 1 to set it high + * @return return 0 if OK, -ve on error + */ +int spl_gpio_output(void *regs, uint gpio, int value); + +/** + * spl_gpio_input() - Set a GPIO as an input + * + * @regs: Pointer to GPIO registers + * @gpio: GPIO to adjust (SoC-specific) + * @return return 0 if OK, -ve on error + */ +int spl_gpio_input(void *regs, uint gpio); + +#endif /* __SPL_GPIO_H */ -- cgit v1.3.1 From 8a0c6aa33f0a077fee52b5b0e68190c7f8339ff0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 21 Jan 2019 14:53:32 -0700 Subject: rockchip: rk3399: Add ROCKCHIP_DEVICE_SETTINGS to set env Some boards use different stdio environment variables from the default. Provide a #define for this which can be set before including the header file. Signed-off-by: Simon Glass Reviewed-by: Philipp Tomsich --- include/configs/rk3399_common.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 9a4da395f92..b977b1faa73 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -49,11 +49,16 @@ "kernel_addr_r=0x02080000\0" \ "ramdisk_addr_r=0x04000000\0" +#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + #include #define CONFIG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ BOOTENV #endif -- cgit v1.3.1 From 9e92116bc84851d7a2a05f186468e77614bf3d67 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 21 Jan 2019 14:53:36 -0700 Subject: rockchip: Add support for chromebook_bob Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports for both power and external display. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions. Support so far includes only: - UART - SDRAM - MMC, SD card - Cros EC (but not keyboard) Not included: - Keyboard - Display - Sound - USB - TPM Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support for this is not provided in this series. Signed-off-by: Simon Glass Reviewed-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/sys_proto.h | 3 + arch/arm/mach-rockchip/rk3399-board-spl.c | 39 +++++++++- arch/arm/mach-rockchip/rk3399/Kconfig | 10 +++ board/google/gru/Kconfig | 15 ++++ board/google/gru/MAINTAINERS | 6 ++ board/google/gru/Makefile | 5 ++ board/google/gru/gru.c | 16 ++++ configs/chromebook_bob_defconfig | 100 +++++++++++++++++++++++++ doc/README.rockchip | 6 +- include/configs/gru.h | 18 +++++ 10 files changed, 215 insertions(+), 3 deletions(-) create mode 100644 board/google/gru/Kconfig create mode 100644 board/google/gru/MAINTAINERS create mode 100644 board/google/gru/Makefile create mode 100644 board/google/gru/gru.c create mode 100644 configs/chromebook_bob_defconfig create mode 100644 include/configs/gru.h (limited to 'include') diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h index 925fcc888c9..928e4f258bb 100644 --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h @@ -29,4 +29,7 @@ static void configure_l2ctlr(void) } #endif /* CONFIG_ROCKCHIP_RK3288 */ +/* provided to defeat compiler optimisation in board_init_f() */ +void gru_dummy_function(int i); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 5453b2a61e0..906aaf46241 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -16,6 +17,7 @@ #include #include #include +#include #include void board_return_to_bootrom(void) @@ -128,7 +130,13 @@ void secure_timer_init(void) void board_debug_uart_init(void) { #define GRF_BASE 0xff770000 +#define GPIO0_BASE 0xff720000 +#define PMUGRF_BASE 0xff320000 struct rk3399_grf_regs * const grf = (void *)GRF_BASE; +#ifdef CONFIG_TARGET_CHROMEBOOK_BOB + struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; + struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; +#endif #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) /* Enable early UART0 on the RK3399 */ @@ -139,6 +147,20 @@ void board_debug_uart_init(void) GRF_GPIO2C1_SEL_MASK, GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT); #else +# ifdef CONFIG_TARGET_CHROMEBOOK_BOB + rk_setreg(&grf->io_vsel, 1 << 0); + + /* + * Let's enable these power rails here, we are already running the SPI + * Flash based code. + */ + spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL); + + spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL); +#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ + /* Enable early UART2 channel C on the RK3399 */ rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C3_SEL_MASK, @@ -163,6 +185,22 @@ void board_init_f(ulong dummy) #define EARLY_UART #ifdef EARLY_UART +# ifdef CONFIG_TARGET_CHROMEBOOK_BOB + int sum, i; + + debug_uart_init(); + + /* + * Add a delay and ensure that the compiler does not optimise this out. + * This is needed since the power rails tail a while to turn on, and + * we get garbage serial output otherwise. + */ + sum = 0; + for (i = 0; i < 150000; i++) + sum += i; + gru_dummy_function(sum); +#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ + /* * Debug UART can be used from here if required: * @@ -171,7 +209,6 @@ void board_init_f(ulong dummy) * printhex8(0x1234); * printascii("string"); */ - debug_uart_init(); printascii("U-Boot SPL board init\n"); #endif diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 8f18e33c76f..2408adb4206 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -53,6 +53,15 @@ config TARGET_ROCK960_RK3399 * 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only), 1x USB 3.0 type C OTG +config TARGET_CHROMEBOOK_BOB + bool "Asus Flip C101PA Chromebook (RK3399)" + help + Bob is a small RK3299-based device similar in apperance to Minnie. + It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 10.1", + 1280x800 display. It uses its USB ports for both power and external + display. It includes a Chrome OS EC (Cortex-M3) to provide access to + the keyboard and battery functions. + endchoice config SYS_SOC @@ -64,5 +73,6 @@ config SYS_MALLOC_F_LEN source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" +source "board/google/gru/Kconfig" endif diff --git a/board/google/gru/Kconfig b/board/google/gru/Kconfig new file mode 100644 index 00000000000..61f7bbca989 --- /dev/null +++ b/board/google/gru/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CHROMEBOOK_BOB + +config SYS_BOARD + default "gru" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "gru" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/google/gru/MAINTAINERS b/board/google/gru/MAINTAINERS new file mode 100644 index 00000000000..e1cda756b8c --- /dev/null +++ b/board/google/gru/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK BOB BOARD +M: Simon Glass +S: Maintained +F: board/google/gru/ +F: include/configs/gru.h +F: configs/chromebook_bob_defconfig diff --git a/board/google/gru/Makefile b/board/google/gru/Makefile new file mode 100644 index 00000000000..9117534a493 --- /dev/null +++ b/board/google/gru/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Google LLC + +obj-y += gru.o diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c new file mode 100644 index 00000000000..b116b1a549b --- /dev/null +++ b/board/google/gru/gru.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google + */ + +#include + +int board_init(void) +{ + return 0; +} + +/* provided to defeat compiler optimisation in board_init_f() */ +void gru_dummy_function(int i) +{ +} diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig new file mode 100644 index 00000000000..56b52bc1609 --- /dev/null +++ b/configs/chromebook_bob_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_BOOT_MODE_REG=0 +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_TARGET_CHROMEBOOK_BOB=y +CONFIG_DEBUG_UART_BASE=0xff1a0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_LOG_DEFAULT_LEVEL=7 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_LOG=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEYBOARD=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/doc/README.rockchip b/doc/README.rockchip index db5724e0730..ec10ebbc260 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -52,13 +52,14 @@ One RK3328 board is supported: - EVB RK3328 -Five RK3399 boards are supported (aarch64): +Size RK3399 boards are supported (aarch64): - EBV RK3399 - use evb_rk3399 configuration - Firefly RK3399 - use the firefly_rk3399 configuration - Puma - use puma_rk3399 configuration - Ficus - use ficus-rk3399 configuration - Rock960 (Vamrs) - use rock960-rk3399 configuration + - Bob - use chromebook_bob configuration Four RK3368 boards are supported: @@ -253,7 +254,8 @@ You should see something like: Booting from SPI ================ -To write an image that boots from SPI flash (e.g. for the Haier Chromebook): +To write an image that boots from SPI flash (e.g. for the Haier Chromebook or +Bob): ./chromebook_jerry/tools/mkimage -n rk3288 -T rkspi \ -d chromebook_jerry/spl/u-boot-spl-dtb.bin spl.bin && \ diff --git a/include/configs/gru.h b/include/configs/gru.h new file mode 100644 index 00000000000..a0d27b6d51a --- /dev/null +++ b/include/configs/gru.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#endif -- cgit v1.3.1