From e74b74c52876d776dda7a7ee5e2a8d555eaa5c4f Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 30 Jan 2019 13:07:05 +0100 Subject: dts: stm32mp1: clock tree update - Add st,digbypass on clk_hse node (needed for board rev.C) - MLAHB/AHB max frequency increased from 200 to 209MHz, with: - PLL3P set to 208.8MHz for MCU sub-system - PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S - PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S - PLL4P set to 99MHz for SDMMC and SPDIFRX - PLL4Q set to 74.25MHz for EVAL board Signed-off-by: Patrick Delaunay --- include/dt-bindings/clock/stm32mp1-clks.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 90ec780bfc6..4cdaf135829 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -248,7 +248,4 @@ #define STM32MP1_LAST_CLK 232 -#define LTDC_K LTDC_PX -#define ETHMAC_K ETHCK_K - #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ -- cgit v1.2.3