From ad005d8a77b182b2acfa79a7e92a99580773b01b Mon Sep 17 00:00:00 2001 From: Duy Nguyen Date: Sun, 28 Jan 2024 16:51:59 +0100 Subject: dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V4M (R8A779H0) SoC. The current version is imported from: https://lore.kernel.org/linux-renesas-soc/11acbd2a30b58607474e9c32eb798b3a00e85e73.1706194617.git.geert+renesas@glider.be/ Signed-off-by: Duy Nguyen Signed-off-by: Hai Pham --- .../dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h | 96 ++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h (limited to 'include') diff --git a/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h new file mode 100644 index 00000000000..7ab6cfbaf90 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ + +#include + +/* r8a779h0 CPG Core Clocks */ + +#define R8A779H0_CLK_ZX 0 +#define R8A779H0_CLK_ZD 1 +#define R8A779H0_CLK_ZS 2 +#define R8A779H0_CLK_ZT 3 +#define R8A779H0_CLK_ZTR 4 +#define R8A779H0_CLK_S0D2 5 +#define R8A779H0_CLK_S0D3 6 +#define R8A779H0_CLK_S0D4 7 +#define R8A779H0_CLK_S0D1_VIO 8 +#define R8A779H0_CLK_S0D2_VIO 9 +#define R8A779H0_CLK_S0D4_VIO 10 +#define R8A779H0_CLK_S0D8_VIO 11 +#define R8A779H0_CLK_VIOBUSD1 12 +#define R8A779H0_CLK_VIOBUSD2 13 +#define R8A779H0_CLK_S0D1_VC 14 +#define R8A779H0_CLK_S0D2_VC 15 +#define R8A779H0_CLK_S0D4_VC 16 +#define R8A779H0_CLK_VCBUSD1 17 +#define R8A779H0_CLK_VCBUSD2 18 +#define R8A779H0_CLK_S0D2_MM 19 +#define R8A779H0_CLK_S0D4_MM 20 +#define R8A779H0_CLK_S0D2_U3DG 21 +#define R8A779H0_CLK_S0D4_U3DG 22 +#define R8A779H0_CLK_S0D2_RT 23 +#define R8A779H0_CLK_S0D3_RT 24 +#define R8A779H0_CLK_S0D4_RT 25 +#define R8A779H0_CLK_S0D6_RT 26 +#define R8A779H0_CLK_S0D2_PER 27 +#define R8A779H0_CLK_S0D3_PER 28 +#define R8A779H0_CLK_S0D4_PER 29 +#define R8A779H0_CLK_S0D6_PER 30 +#define R8A779H0_CLK_S0D12_PER 31 +#define R8A779H0_CLK_S0D24_PER 32 +#define R8A779H0_CLK_S0D1_HSC 33 +#define R8A779H0_CLK_S0D2_HSC 34 +#define R8A779H0_CLK_S0D4_HSC 35 +#define R8A779H0_CLK_S0D8_HSC 36 +#define R8A779H0_CLK_SVD1_IR 37 +#define R8A779H0_CLK_SVD2_IR 38 +#define R8A779H0_CLK_IMPAD1 39 +#define R8A779H0_CLK_IMPAD4 40 +#define R8A779H0_CLK_IMPB 41 +#define R8A779H0_CLK_SVD1_VIP 42 +#define R8A779H0_CLK_SVD2_VIP 43 +#define R8A779H0_CLK_CL 44 +#define R8A779H0_CLK_CL16M 45 +#define R8A779H0_CLK_CL16M_MM 46 +#define R8A779H0_CLK_CL16M_RT 47 +#define R8A779H0_CLK_CL16M_PER 48 +#define R8A779H0_CLK_CL16M_HSC 49 +#define R8A779H0_CLK_ZC0 50 +#define R8A779H0_CLK_ZC1 51 +#define R8A779H0_CLK_ZC2 52 +#define R8A779H0_CLK_ZC3 53 +#define R8A779H0_CLK_ZB3 54 +#define R8A779H0_CLK_ZB3D2 55 +#define R8A779H0_CLK_ZB3D4 56 +#define R8A779H0_CLK_ZG 57 +#define R8A779H0_CLK_SD0H 58 +#define R8A779H0_CLK_SD0 59 +#define R8A779H0_CLK_RPC 60 +#define R8A779H0_CLK_RPCD2 61 +#define R8A779H0_CLK_MSO 62 +#define R8A779H0_CLK_CANFD 63 +#define R8A779H0_CLK_CSI 64 +#define R8A779H0_CLK_FRAY 65 +#define R8A779H0_CLK_IPC 66 +#define R8A779H0_CLK_SASYNCRT 67 +#define R8A779H0_CLK_SASYNCPERD1 68 +#define R8A779H0_CLK_SASYNCPERD2 69 +#define R8A779H0_CLK_SASYNCPERD4 70 +#define R8A779H0_CLK_DSIEXT 71 +#define R8A779H0_CLK_DSIREF 72 +#define R8A779H0_CLK_ADGH 73 +#define R8A779H0_CLK_OSC 74 +#define R8A779H0_CLK_ZR0 75 +#define R8A779H0_CLK_ZR1 76 +#define R8A779H0_CLK_ZR2 77 +#define R8A779H0_CLK_RGMII 78 +#define R8A779H0_CLK_CPEX 79 +#define R8A779H0_CLK_CP 80 +#define R8A779H0_CLK_CBFUSA 81 +#define R8A779H0_CLK_R 82 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */ -- cgit v1.3.1 From 42a064d1d76892981301921ae90905d8aa29a86d Mon Sep 17 00:00:00 2001 From: Duy Nguyen Date: Sun, 28 Jan 2024 16:52:00 +0100 Subject: dt-bindings: power: Add R8A779H0 V4M SYSC power domain definitions Add power domain indices for R-Car V4M (R8A779H0). The current version is imported from: https://lore.kernel.org/linux-renesas-soc/c5cbef71178cada761e9da7bcbb6f21334f93ef8.1706194617.git.geert+renesas@glider.be/ Signed-off-by: Duy Nguyen Signed-off-by: Hai Pham --- include/dt-bindings/power/renesas,r8a779h0-sysc.h | 49 +++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 include/dt-bindings/power/renesas,r8a779h0-sysc.h (limited to 'include') diff --git a/include/dt-bindings/power/renesas,r8a779h0-sysc.h b/include/dt-bindings/power/renesas,r8a779h0-sysc.h new file mode 100644 index 00000000000..f27976f523e --- /dev/null +++ b/include/dt-bindings/power/renesas,r8a779h0-sysc.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ +#define __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779H0_PD_A1E0D0C0 0 +#define R8A779H0_PD_A1E0D0C1 1 +#define R8A779H0_PD_A1E0D0C2 2 +#define R8A779H0_PD_A1E0D0C3 3 +#define R8A779H0_PD_A2E0D0 16 +#define R8A779H0_PD_A3CR0 21 +#define R8A779H0_PD_A3CR1 22 +#define R8A779H0_PD_A3CR2 23 +#define R8A779H0_PD_A33DGA 24 +#define R8A779H0_PD_A23DGB 25 +#define R8A779H0_PD_C4 31 +#define R8A779H0_PD_A1DSP0 33 +#define R8A779H0_PD_A2IMP01 34 +#define R8A779H0_PD_A2PSC 35 +#define R8A779H0_PD_A2CV0 36 +#define R8A779H0_PD_A2CV1 37 +#define R8A779H0_PD_A3IMR0 38 +#define R8A779H0_PD_A3IMR1 39 +#define R8A779H0_PD_A3VC 40 +#define R8A779H0_PD_A2CN0 42 +#define R8A779H0_PD_A1CN0 44 +#define R8A779H0_PD_A1DSP1 45 +#define R8A779H0_PD_A2DMA 47 +#define R8A779H0_PD_A2CV2 48 +#define R8A779H0_PD_A2CV3 49 +#define R8A779H0_PD_A3IMR2 50 +#define R8A779H0_PD_A3IMR3 51 +#define R8A779H0_PD_A3PCI 52 +#define R8A779H0_PD_A2PCIPHY 53 +#define R8A779H0_PD_A3VIP0 56 +#define R8A779H0_PD_A3VIP2 58 +#define R8A779H0_PD_A3ISP0 60 +#define R8A779H0_PD_A3DUL 62 + +/* Always-on power area */ +#define R8A779H0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ */ -- cgit v1.3.1 From 53066deccbedf02439309b0d4aca9f0be853a8da Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Sun, 28 Jan 2024 16:52:09 +0100 Subject: ARM: renesas: Add Renesas R8A779H0 V4M Gray Hawk board code Add board code for the Renesas R8A779H0 V4M Gray Hawk board. Signed-off-by: Hai Pham --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts | 42 +++++++++++++++++ arch/arm/mach-rmobile/Kconfig.rcar4 | 7 +++ board/renesas/grayhawk/Kconfig | 15 ++++++ board/renesas/grayhawk/MAINTAINERS | 5 ++ board/renesas/grayhawk/Makefile | 9 ++++ board/renesas/grayhawk/grayhawk.c | 66 ++++++++++++++++++++++++++ configs/r8a779h0_grayhawk_defconfig | 75 ++++++++++++++++++++++++++++++ include/configs/grayhawk.h | 14 ++++++ 9 files changed, 235 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts create mode 100644 board/renesas/grayhawk/Kconfig create mode 100644 board/renesas/grayhawk/MAINTAINERS create mode 100644 board/renesas/grayhawk/Makefile create mode 100644 board/renesas/grayhawk/grayhawk.c create mode 100644 configs/r8a779h0_grayhawk_defconfig create mode 100644 include/configs/grayhawk.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3beb8f1b9d4..ce10d3dbb07 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1172,7 +1172,8 @@ dtb-$(CONFIG_RCAR_GEN3) += \ dtb-$(CONFIG_RCAR_GEN4) += \ r8a779a0-falcon-u-boot.dtb \ r8a779f0-spider-u-boot.dtb \ - r8a779g0-white-hawk-u-boot.dtb + r8a779g0-white-hawk-u-boot.dtb \ + r8a779h0-gray-hawk-u-boot.dtb dtb-$(CONFIG_TARGET_RZG2L) += \ r9a07g044l2-smarc.dts diff --git a/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts b/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts new file mode 100644 index 00000000000..935ba9465dc --- /dev/null +++ b/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Gray Hawk board + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include "r8a779h0-gray-hawk.dts" +#include "r8a779h0-u-boot.dtsi" + +/ { + aliases { + spi0 = &rpc; + }; +}; + +&pfc { + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <40000000>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4 b/arch/arm/mach-rmobile/Kconfig.rcar4 index 3c8d683974c..e80dce11f54 100644 --- a/arch/arm/mach-rmobile/Kconfig.rcar4 +++ b/arch/arm/mach-rmobile/Kconfig.rcar4 @@ -50,10 +50,17 @@ config TARGET_WHITEHAWK help Support for Renesas R-Car Gen4 White Hawk platform +config TARGET_GRAYHAWK + bool "Gray Hawk board" + imply R8A779H0 + help + Support for Renesas R-Car Gen4 Gray Hawk platform + endchoice source "board/renesas/falcon/Kconfig" source "board/renesas/spider/Kconfig" source "board/renesas/whitehawk/Kconfig" +source "board/renesas/grayhawk/Kconfig" endif diff --git a/board/renesas/grayhawk/Kconfig b/board/renesas/grayhawk/Kconfig new file mode 100644 index 00000000000..97621a30ad0 --- /dev/null +++ b/board/renesas/grayhawk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_GRAYHAWK + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "grayhawk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "grayhawk" + +endif diff --git a/board/renesas/grayhawk/MAINTAINERS b/board/renesas/grayhawk/MAINTAINERS new file mode 100644 index 00000000000..1d5de580a7c --- /dev/null +++ b/board/renesas/grayhawk/MAINTAINERS @@ -0,0 +1,5 @@ +GRAYHAWK BOARD +M: Marek Vasut +S: Maintained +N: grayhawk +N: r8a779h0 diff --git a/board/renesas/grayhawk/Makefile b/board/renesas/grayhawk/Makefile new file mode 100644 index 00000000000..9c5b8c9a12f --- /dev/null +++ b/board/renesas/grayhawk/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/grayhawk/Makefile +# +# Copyright (C) 2023 Renesas Electronics Corp. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := grayhawk.o ../rcar-common/common.o diff --git a/board/renesas/grayhawk/grayhawk.c b/board/renesas/grayhawk/grayhawk.c new file mode 100644 index 00000000000..6f2e73f7d38 --- /dev/null +++ b/board/renesas/grayhawk/grayhawk.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * board/renesas/grayhawk/grayhawk.c + * This file is Gray Hawk board support. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void init_generic_timer(void) +{ + const u32 freq = CONFIG_SYS_CLK_FREQ; + + /* Update memory mapped and register based freqency */ + asm volatile ("msr cntfrq_el0, %0" :: "r" (freq)); + writel(freq, CNTFID0); + + /* Enable counter */ + setbits_le32(CNTCR_BASE, CNTCR_EN); +} + +static void init_gic_v3(void) +{ + /* GIC v3 power on */ + writel(BIT(1), GICR_LPI_PWRR); + + /* Wait till the WAKER_CA_BIT changes to 0 */ + clrbits_le32(GICR_LPI_WAKER, BIT(1)); + while (readl(GICR_LPI_WAKER) & BIT(2)) + ; + + writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0); +} + +void s_init(void) +{ + if (current_el() == 3) + init_generic_timer(); +} + +int board_early_init_f(void) +{ + /* Unlock CPG access */ + writel(0x5A5AFFFF, CPGWPR); + writel(0xA5A50000, CPGWPCR); + + return 0; +} + +int board_init(void) +{ + if (current_el() == 3) + init_gic_v3(); + + return 0; +} diff --git a/configs/r8a779h0_grayhawk_defconfig b/configs/r8a779h0_grayhawk_defconfig new file mode 100644 index 00000000000..41aa0207086 --- /dev/null +++ b/configs/r8a779h0_grayhawk_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0xFFFE0000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="r8a779h0-gray-hawk-u-boot" +CONFIG_RCAR_GEN4=y +CONFIG_TARGET_GRAYHAWK=y +CONFIG_SYS_MONITOR_LEN=1048576 +CONFIG_SYS_CLK_FREQ=16666666 +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0x58000000 +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_BARGSIZE=2048 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779h0-gray-hawk.dtb && booti 0x48080000 - 0x48000000" +CONFIG_DEFAULT_FDT_FILE="r8a779h0-gray-hawk.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_VERSION_VARIABLE=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_I2C=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH_PHY=y +CONFIG_RENESAS_RAVB=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_BAUDRATE=921600 +CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y diff --git a/include/configs/grayhawk.h b/include/configs/grayhawk.h new file mode 100644 index 00000000000..f1bb84f0a13 --- /dev/null +++ b/include/configs/grayhawk.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/grayhawk.h + * This file is Gray Hawk board configuration. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#ifndef __GRAYHAWK_H +#define __GRAYHAWK_H + +#include "rcar-gen4-common.h" + +#endif /* __GRAYHAWK_H */ -- cgit v1.3.1