From 4302e6564791b99c755f2cd76c8495c222357832 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 7 Aug 2024 22:14:07 -0500 Subject: mmc: dw_mmc: Remove unused version field from struct dwmci_host Nobody seems to use it, so just remove it. No functional change. Signed-off-by: Sam Protsenko Reviewed-by: Quentin Schulz Signed-off-by: Minkyu Kang --- include/dwmmc.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/dwmmc.h b/include/dwmmc.h index 136a95b8cdb..39024fb38aa 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -163,7 +163,6 @@ struct dwmci_host { void *ioaddr; unsigned int quirks; unsigned int caps; - unsigned int version; unsigned int clock; unsigned int bus_hz; unsigned int div; -- cgit v1.2.3 From 96ea89000f3f2b395daeef9401dd3fab6d7c62b7 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 7 Aug 2024 22:14:08 -0500 Subject: mmc: dw_mmc: Move struct idmac to dw_mmc.c struct idmac is only used in dw_mmc.c, so move it there from dwmmc.h to avoid cluttering the interface in the header. No functional change. Signed-off-by: Sam Protsenko Reviewed-by: Quentin Schulz Signed-off-by: Minkyu Kang --- include/dwmmc.h | 7 ------- 1 file changed, 7 deletions(-) (limited to 'include') diff --git a/include/dwmmc.h b/include/dwmmc.h index 39024fb38aa..7e4acf096dc 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -198,13 +198,6 @@ struct dwmci_host { bool fifo_mode; }; -struct dwmci_idmac { - u32 flags; - u32 cnt; - u32 addr; - u32 next_addr; -} __aligned(ARCH_DMA_MINALIGN); - static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) { writel(val, host->ioaddr + reg); -- cgit v1.2.3 From e760a245e2c5463a91fd86b122a35aed91326232 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 7 Aug 2024 22:14:16 -0500 Subject: mmc: dw_mmc: Add support for 64-bit IDMAC Some DW MMC blocks (e.g. those on modern Exynos chips) support 64-bit DMA addressing mode. 64-bit DW MMC variants differ from their 32-bit counterparts: - the register layout is a bit different (because there are additional IDMAC registers present for storing upper part of 64-bit addresses) - DMA descriptor structure is bigger and different from 32-bit one Introduce all necessary changes to enable support for 64-bit DMA capable DW MMC blocks. Next changes were made: 1. Check which DMA address mode is supported in current IP-core version. HCON register (bit 27) indicates whether it's 32-bit or 64-bit addressing. Add boolean .dma_64bit_address field to struct dwmci_host and store the result there. dwmci_init_dma() function is introduced for doing so, which is called on driver's init. 2. Add 64-bit DMA descriptor (struct dwmci_idmac64) and use it in dwmci_prepare_desc() in case if .dma_64bit_address field is true. A new dwmci_set_idma_desc64() function was added for populating that descriptor. 3. Add registers for 64-bit DMA capable blocks. To make the access to IDMAC registers universal between 32-bit / 64-bit cases, a new struct dwmci_idmac_regs (and corresponding host->regs field) was introduced, which abstracts the hardware by being set to appropriate offset constants on init. All direct calls to IDMAC registers were correspondingly replaced by accessing host->regs. 4. Allocate and use 64-bit DMA descriptors buffer in case when IDMAC is 64-bit capable. Extract all the code (except for the IDMAC descriptors buffer allocation) from dwmci_send_cmd() to dwmci_send_cmd_common(), so that it's possible to keep IDMAC buffer (either 32-bit or 64-bit) on stack during send_cmd routine. The insights for this implementation were taken from Linux kernel DW MMC driver. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- include/dwmmc.h | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/dwmmc.h b/include/dwmmc.h index 7e4acf096dc..de18fda68ac 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -44,12 +44,22 @@ #define DWMCI_UHS_REG 0x074 #define DWMCI_BMOD 0x080 #define DWMCI_PLDMND 0x084 +#define DWMCI_DATA 0x200 +/* Registers to support IDMAC 32-bit address mode */ #define DWMCI_DBADDR 0x088 #define DWMCI_IDSTS 0x08C #define DWMCI_IDINTEN 0x090 #define DWMCI_DSCADDR 0x094 #define DWMCI_BUFADDR 0x098 -#define DWMCI_DATA 0x200 +/* Registers to support IDMAC 64-bit address mode */ +#define DWMCI_DBADDRL 0x088 +#define DWMCI_DBADDRU 0x08c +#define DWMCI_IDSTS64 0x090 +#define DWMCI_IDINTEN64 0x094 +#define DWMCI_DSCADDRL 0x098 +#define DWMCI_DSCADDRU 0x09c +#define DWMCI_BUFADDRL 0x0a0 +#define DWMCI_BUFADDRU 0x0a4 /* Interrupt Mask register */ #define DWMCI_INTMSK_ALL 0xffffffff @@ -142,6 +152,29 @@ /* quirks */ #define DWMCI_QUIRK_DISABLE_SMU (1 << 0) +/** + * struct dwmci_idmac_regs - Offsets of IDMAC registers + * + * @dbaddrl: Descriptor base address, lower 32 bits + * @dbaddru: Descriptor base address, upper 32 bits + * @idsts: Internal DMA status + * @idinten: Internal DMA interrupt enable + * @dscaddrl: IDMAC descriptor address, lower 32 bits + * @dscaddru: IDMAC descriptor address, upper 32 bits + * @bufaddrl: Current data buffer address, lower 32 bits + * @bufaddru: Current data buffer address, upper 32 bits + */ +struct dwmci_idmac_regs { + u32 dbaddrl; + u32 dbaddru; + u32 idsts; + u32 idinten; + u32 dscaddrl; + u32 dscaddru; + u32 bufaddrl; + u32 bufaddru; +}; + /** * struct dwmci_host - Information about a designware MMC host * @@ -157,6 +190,8 @@ * @fifoth_val: Value for FIFOTH register (or 0 to leave unset) * @mmc: Pointer to generic MMC structure for this device * @priv: Private pointer for use by controller + * @dma_64bit_address: Whether DMA supports 64-bit address mode or not + * @regs: Registers that can vary for different DW MMC block versions */ struct dwmci_host { const char *name; @@ -196,6 +231,8 @@ struct dwmci_host { /* use fifo mode to read and write data */ bool fifo_mode; + bool dma_64bit_address; + const struct dwmci_idmac_regs *regs; }; static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) -- cgit v1.2.3 From ffd62e051b6d42a408f4c750f8f35603453fe577 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 7 Aug 2024 22:14:17 -0500 Subject: mmc: dw_mmc: Replace fifoth_val property with fifo-depth Replace fifoth_val property with its fifo-depth counterpart in all DW MMC drivers. fifo-depth is a common property used in upstream Linux kernel. The FIFOTH register value will be calculated using fifo-depth value in DW MMC core (dw_mmc.c). This change reduces code duplication in platform drivers, and pulls common FIFOTH register value calculation into core dw_mmc driver where it belongs. No functional change. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- include/dwmmc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/dwmmc.h b/include/dwmmc.h index de18fda68ac..7bb456e792b 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -187,7 +187,7 @@ struct dwmci_idmac_regs { * @dev_index: Arbitrary device index for use by controller * @dev_id: Arbitrary device ID for use by controller * @buswidth: Bus width in bits (8 or 4) - * @fifoth_val: Value for FIFOTH register (or 0 to leave unset) + * @fifo_depth: Depth of FIFO, bytes (or 0 for automatic detection) * @mmc: Pointer to generic MMC structure for this device * @priv: Private pointer for use by controller * @dma_64bit_address: Whether DMA supports 64-bit address mode or not @@ -204,7 +204,7 @@ struct dwmci_host { int dev_index; int dev_id; int buswidth; - u32 fifoth_val; + u32 fifo_depth; struct mmc *mmc; void *priv; -- cgit v1.2.3 From 5a9a0e42bcf87e7d097f12820007bfa710ac1c58 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 7 Aug 2024 22:14:18 -0500 Subject: mmc: dw_mmc: Fix kernel-doc comments in dwmmc.h Rework kernel-doc comments in dwmmc.h header so it's actually possible to generate a proper documentation from it usin scripts/kernel-doc script, with no errors. No functional change. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- include/dwmmc.h | 41 ++++++++++++++++++++++------------------- 1 file changed, 22 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/include/dwmmc.h b/include/dwmmc.h index 7bb456e792b..77c8989148a 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -182,6 +182,7 @@ struct dwmci_idmac_regs { * @ioaddr: Base I/O address of controller * @quirks: Quick flags - see DWMCI_QUIRK_... * @caps: Capabilities - see MMC_MODE_... + * @clock: Current clock frequency (after internal divider), Hz * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL * @div: Arbitrary clock divider value for use by controller * @dev_index: Arbitrary device index for use by controller @@ -190,6 +191,10 @@ struct dwmci_idmac_regs { * @fifo_depth: Depth of FIFO, bytes (or 0 for automatic detection) * @mmc: Pointer to generic MMC structure for this device * @priv: Private pointer for use by controller + * @clksel: (Optional) Platform function to run when speed/width is changed + * @board_init: (Optional) Platform function to run on init + * @cfg: Internal MMC configuration, for !CONFIG_BLK cases + * @fifo_mode: Use FIFO mode (not DMA) to read and write data * @dma_64bit_address: Whether DMA supports 64-bit address mode or not * @regs: Registers that can vary for different DW MMC block versions */ @@ -210,9 +215,12 @@ struct dwmci_host { int (*clksel)(struct dwmci_host *host); void (*board_init)(struct dwmci_host *host); - /** - * Get / set a particular MMC clock frequency + * @get_mmc_clk: (Optional) Platform function to get/set a particular + * MMC clock frequency + * + * @host: DWMMC host + * @freq: Frequency the host is trying to achieve * * This is used to request the current clock frequency of the clock * that drives the DWMMC peripheral. The caller will then use this @@ -220,16 +228,12 @@ struct dwmci_host { * required MMC bus clock frequency. If you want to handle the * clock external to DWMMC, use @freq to select the frequency and * return that value too. Then DWMMC will put itself in bypass mode. - * - * @host: DWMMC host - * @freq: Frequency the host is trying to achieve */ unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq); #ifndef CONFIG_BLK struct mmc_config cfg; #endif - /* use fifo mode to read and write data */ bool fifo_mode; bool dma_64bit_address; const struct dwmci_idmac_regs *regs; @@ -267,6 +271,10 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg) #ifdef CONFIG_BLK /** * dwmci_setup_cfg() - Set up the configuration for DWMMC + * @cfg: Configuration structure to fill in (generally &plat->mmc) + * @host: DWMMC host + * @max_clk: Maximum supported clock speed in Hz (e.g. 150000000) + * @min_clk: Minimum supported clock speed in Hz (e.g. 400000) * * This is used to set up a DWMMC device when you are using CONFIG_BLK. * @@ -291,28 +299,23 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg) * struct rockchip_mmc_plat *plat = dev_get_plat(dev); * * See rockchip_dw_mmc.c for an example. - * - * @cfg: Configuration structure to fill in (generally &plat->mmc) - * @host: DWMMC host - * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) - * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) */ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, u32 max_clk, u32 min_clk); /** * dwmci_bind() - Set up a new MMC block device + * @dev: Device to set up + * @mmc: Pointer to mmc structure (normally &plat->mmc) + * @cfg: Empty configuration structure (generally &plat->cfg). This is + * normally all zeroes at this point. The only purpose of passing + * this in is to set mmc->cfg to it. * * This is used to set up a DWMMC block device when you are using CONFIG_BLK. * It should be called from your driver's bind() method. * * See rockchip_dw_mmc.c for an example. * - * @dev: Device to set up - * @mmc: Pointer to mmc structure (normally &plat->mmc) - * @cfg: Empty configuration structure (generally &plat->cfg). This is - * normally all zeroes at this point. The only purpose of passing - * this in is to set mmc->cfg to it. * Return: 0 if OK, -ve if the block device could not be created */ int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); @@ -320,12 +323,12 @@ int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); #else /** * add_dwmci() - Add a new DWMMC interface + * @host: DWMMC host structure + * @max_clk: Maximum supported clock speed in Hz (e.g. 150000000) + * @min_clk: Minimum supported clock speed in Hz (e.g. 400000) * * This is used when you are not using CONFIG_BLK. Convert your driver over! * - * @host: DWMMC host structure - * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) - * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) * Return: 0 if OK, -ve on error */ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); -- cgit v1.2.3 From 84d5bd070c40529021120eb9bdca16849d363619 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 7 Aug 2024 22:14:19 -0500 Subject: mmc: dw_mmc: Improve coding style Fix most of checkpatch warnings and other obvious style issues. No functional change. Signed-off-by: Sam Protsenko Reviewed-by: Quentin Schulz Signed-off-by: Minkyu Kang --- include/dwmmc.h | 149 +++++++++++++++++++++++++++++--------------------------- 1 file changed, 77 insertions(+), 72 deletions(-) (limited to 'include') diff --git a/include/dwmmc.h b/include/dwmmc.h index 77c8989148a..a99b2f3bf0c 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -15,31 +15,31 @@ #define DWMCI_CTRL 0x000 #define DWMCI_PWREN 0x004 #define DWMCI_CLKDIV 0x008 -#define DWMCI_CLKSRC 0x00C +#define DWMCI_CLKSRC 0x00c #define DWMCI_CLKENA 0x010 #define DWMCI_TMOUT 0x014 #define DWMCI_CTYPE 0x018 -#define DWMCI_BLKSIZ 0x01C +#define DWMCI_BLKSIZ 0x01c #define DWMCI_BYTCNT 0x020 #define DWMCI_INTMASK 0x024 #define DWMCI_CMDARG 0x028 -#define DWMCI_CMD 0x02C +#define DWMCI_CMD 0x02c #define DWMCI_RESP0 0x030 #define DWMCI_RESP1 0x034 #define DWMCI_RESP2 0x038 -#define DWMCI_RESP3 0x03C +#define DWMCI_RESP3 0x03c #define DWMCI_MINTSTS 0x040 #define DWMCI_RINTSTS 0x044 #define DWMCI_STATUS 0x048 -#define DWMCI_FIFOTH 0x04C +#define DWMCI_FIFOTH 0x04c #define DWMCI_CDETECT 0x050 #define DWMCI_WRTPRT 0x054 #define DWMCI_GPIO 0x058 -#define DWMCI_TCMCNT 0x05C +#define DWMCI_TCMCNT 0x05c #define DWMCI_TBBCNT 0x060 #define DWMCI_DEBNCE 0x064 #define DWMCI_USRID 0x068 -#define DWMCI_VERID 0x06C +#define DWMCI_VERID 0x06c #define DWMCI_HCON 0x070 #define DWMCI_UHS_REG 0x074 #define DWMCI_BMOD 0x080 @@ -47,7 +47,7 @@ #define DWMCI_DATA 0x200 /* Registers to support IDMAC 32-bit address mode */ #define DWMCI_DBADDR 0x088 -#define DWMCI_IDSTS 0x08C +#define DWMCI_IDSTS 0x08c #define DWMCI_IDINTEN 0x090 #define DWMCI_DSCADDR 0x094 #define DWMCI_BUFADDR 0x098 @@ -63,94 +63,94 @@ /* Interrupt Mask register */ #define DWMCI_INTMSK_ALL 0xffffffff -#define DWMCI_INTMSK_RE (1 << 1) -#define DWMCI_INTMSK_CDONE (1 << 2) -#define DWMCI_INTMSK_DTO (1 << 3) -#define DWMCI_INTMSK_TXDR (1 << 4) -#define DWMCI_INTMSK_RXDR (1 << 5) -#define DWMCI_INTMSK_RCRC (1 << 6) -#define DWMCI_INTMSK_DCRC (1 << 7) -#define DWMCI_INTMSK_RTO (1 << 8) -#define DWMCI_INTMSK_DRTO (1 << 9) -#define DWMCI_INTMSK_HTO (1 << 10) -#define DWMCI_INTMSK_FRUN (1 << 11) -#define DWMCI_INTMSK_HLE (1 << 12) -#define DWMCI_INTMSK_SBE (1 << 13) -#define DWMCI_INTMSK_ACD (1 << 14) -#define DWMCI_INTMSK_EBE (1 << 15) - -/* Raw interrupt Regsiter */ -#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\ - DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) -#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) +#define DWMCI_INTMSK_RE BIT(1) +#define DWMCI_INTMSK_CDONE BIT(2) +#define DWMCI_INTMSK_DTO BIT(3) +#define DWMCI_INTMSK_TXDR BIT(4) +#define DWMCI_INTMSK_RXDR BIT(5) +#define DWMCI_INTMSK_RCRC BIT(6) +#define DWMCI_INTMSK_DCRC BIT(7) +#define DWMCI_INTMSK_RTO BIT(8) +#define DWMCI_INTMSK_DRTO BIT(9) +#define DWMCI_INTMSK_HTO BIT(10) +#define DWMCI_INTMSK_FRUN BIT(11) +#define DWMCI_INTMSK_HLE BIT(12) +#define DWMCI_INTMSK_SBE BIT(13) +#define DWMCI_INTMSK_ACD BIT(14) +#define DWMCI_INTMSK_EBE BIT(15) + +/* Raw interrupt register */ +#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | \ + DWMCI_INTMSK_HLE | DWMCI_INTMSK_FRUN | \ + DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) +#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) + /* CTRL register */ -#define DWMCI_CTRL_RESET (1 << 0) -#define DWMCI_CTRL_FIFO_RESET (1 << 1) -#define DWMCI_CTRL_DMA_RESET (1 << 2) -#define DWMCI_DMA_EN (1 << 5) -#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10) -#define DWMCI_IDMAC_EN (1 << 25) +#define DWMCI_CTRL_RESET BIT(0) +#define DWMCI_CTRL_FIFO_RESET BIT(1) +#define DWMCI_CTRL_DMA_RESET BIT(2) +#define DWMCI_DMA_EN BIT(5) +#define DWMCI_CTRL_SEND_AS_CCSD BIT(10) +#define DWMCI_IDMAC_EN BIT(25) #define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\ DWMCI_CTRL_DMA_RESET) /* CMD register */ -#define DWMCI_CMD_RESP_EXP (1 << 6) -#define DWMCI_CMD_RESP_LENGTH (1 << 7) -#define DWMCI_CMD_CHECK_CRC (1 << 8) -#define DWMCI_CMD_DATA_EXP (1 << 9) -#define DWMCI_CMD_RW (1 << 10) -#define DWMCI_CMD_SEND_STOP (1 << 12) -#define DWMCI_CMD_ABORT_STOP (1 << 14) -#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13) -#define DWMCI_CMD_UPD_CLK (1 << 21) -#define DWMCI_CMD_USE_HOLD_REG (1 << 29) -#define DWMCI_CMD_START (1 << 31) +#define DWMCI_CMD_RESP_EXP BIT(6) +#define DWMCI_CMD_RESP_LENGTH BIT(7) +#define DWMCI_CMD_CHECK_CRC BIT(8) +#define DWMCI_CMD_DATA_EXP BIT(9) +#define DWMCI_CMD_RW BIT(10) +#define DWMCI_CMD_SEND_STOP BIT(12) +#define DWMCI_CMD_ABORT_STOP BIT(14) +#define DWMCI_CMD_PRV_DAT_WAIT BIT(13) +#define DWMCI_CMD_UPD_CLK BIT(21) +#define DWMCI_CMD_USE_HOLD_REG BIT(29) +#define DWMCI_CMD_START BIT(31) /* CLKENA register */ -#define DWMCI_CLKEN_ENABLE (1 << 0) -#define DWMCI_CLKEN_LOW_PWR (1 << 16) +#define DWMCI_CLKEN_ENABLE BIT(0) +#define DWMCI_CLKEN_LOW_PWR BIT(16) -/* Card-type registe */ +/* Card type register */ #define DWMCI_CTYPE_1BIT 0 -#define DWMCI_CTYPE_4BIT (1 << 0) -#define DWMCI_CTYPE_8BIT (1 << 16) +#define DWMCI_CTYPE_4BIT BIT(0) +#define DWMCI_CTYPE_8BIT BIT(16) -/* Status Register */ -#define DWMCI_FIFO_EMPTY (1 << 2) -#define DWMCI_FIFO_FULL (1 << 3) -#define DWMCI_BUSY (1 << 9) +/* Status register */ +#define DWMCI_FIFO_EMPTY BIT(2) +#define DWMCI_FIFO_FULL BIT(3) +#define DWMCI_BUSY BIT(9) #define DWMCI_FIFO_MASK 0x1fff #define DWMCI_FIFO_SHIFT 17 -/* FIFOTH Register */ +/* FIFOTH register */ #define MSIZE(x) ((x) << 28) #define RX_WMARK(x) ((x) << 16) #define TX_WMARK(x) (x) #define RX_WMARK_SHIFT 16 #define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT) -#define DWMCI_IDMAC_OWN (1 << 31) -#define DWMCI_IDMAC_CH (1 << 4) -#define DWMCI_IDMAC_FS (1 << 3) -#define DWMCI_IDMAC_LD (1 << 2) +#define DWMCI_IDMAC_OWN BIT(31) +#define DWMCI_IDMAC_CH BIT(4) +#define DWMCI_IDMAC_FS BIT(3) +#define DWMCI_IDMAC_LD BIT(2) -/* Bus Mode Register */ -#define DWMCI_BMOD_IDMAC_RESET (1 << 0) -#define DWMCI_BMOD_IDMAC_FB (1 << 1) -#define DWMCI_BMOD_IDMAC_EN (1 << 7) +/* Bus Mode register */ +#define DWMCI_BMOD_IDMAC_RESET BIT(0) +#define DWMCI_BMOD_IDMAC_FB BIT(1) +#define DWMCI_BMOD_IDMAC_EN BIT(7) /* UHS register */ -#define DWMCI_DDR_MODE (1 << 16) +#define DWMCI_DDR_MODE BIT(16) /* Internal IDMAC interrupt defines */ -#define DWMCI_IDINTEN_RI BIT(1) -#define DWMCI_IDINTEN_TI BIT(0) +#define DWMCI_IDINTEN_RI BIT(1) +#define DWMCI_IDINTEN_TI BIT(0) +#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | DWMCI_IDINTEN_RI) -#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | \ - DWMCI_IDINTEN_RI) - -/* quirks */ -#define DWMCI_QUIRK_DISABLE_SMU (1 << 0) +/* Quirks */ +#define DWMCI_QUIRK_DISABLE_SMU BIT(0) /** * struct dwmci_idmac_regs - Offsets of IDMAC registers @@ -230,6 +230,7 @@ struct dwmci_host { * return that value too. Then DWMMC will put itself in bypass mode. */ unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq); + #ifndef CONFIG_BLK struct mmc_config cfg; #endif @@ -253,6 +254,7 @@ static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val) { writeb(val, host->ioaddr + reg); } + static inline u32 dwmci_readl(struct dwmci_host *host, int reg) { return readl(host->ioaddr + reg); @@ -269,6 +271,7 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg) } #ifdef CONFIG_BLK + /** * dwmci_setup_cfg() - Set up the configuration for DWMMC * @cfg: Configuration structure to fill in (generally &plat->mmc) @@ -301,7 +304,7 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg) * See rockchip_dw_mmc.c for an example. */ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, - u32 max_clk, u32 min_clk); + u32 max_clk, u32 min_clk); /** * dwmci_bind() - Set up a new MMC block device @@ -321,6 +324,7 @@ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); #else + /** * add_dwmci() - Add a new DWMMC interface * @host: DWMMC host structure @@ -332,6 +336,7 @@ int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); * Return: 0 if OK, -ve on error */ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); + #endif /* !CONFIG_BLK */ #ifdef CONFIG_DM_MMC -- cgit v1.2.3 From 56ba9455a5dc2faaf409aa4e403576ec9b85ac6c Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 7 Aug 2024 22:14:31 -0500 Subject: mmc: exynos_dw_mmc: Refactor fixed CIU clock divider Some chips like Exynos4412 have fixed internal CIU clock divider. Instead of reading it from non-standard "div" dts property, store its value in the driver internally, in static chip data associated with corresponding compatible. This makes it possible to avoid using host->div for storing it, so the latter can be removed safely. Also create a helper function called exynos_dwmmc_get_ciu_div() for getting the current div value: in case the fixed div is provided in the chip data it will be used, otherwise the current div value is being read from CLKSEL register. The insights for this change were taken from dw_mmc-exynos.c driver in Linux kernel. No functional change. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- include/dwmmc.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/dwmmc.h b/include/dwmmc.h index a99b2f3bf0c..8c2500da9ef 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -184,7 +184,6 @@ struct dwmci_idmac_regs { * @caps: Capabilities - see MMC_MODE_... * @clock: Current clock frequency (after internal divider), Hz * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL - * @div: Arbitrary clock divider value for use by controller * @dev_index: Arbitrary device index for use by controller * @dev_id: Arbitrary device ID for use by controller * @buswidth: Bus width in bits (8 or 4) @@ -205,7 +204,6 @@ struct dwmci_host { unsigned int caps; unsigned int clock; unsigned int bus_hz; - unsigned int div; int dev_index; int dev_id; int buswidth; -- cgit v1.2.3 From b8ea3810aa94a294fab12f496592c39498361fa5 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 7 Aug 2024 22:14:34 -0500 Subject: mmc: exynos_dw_mmc: Move quirks from struct dwmci_host to chip data host->quirks field is only used internally in exynos_dw_mmc.c driver. To avoid cluttering the scope of struct dwmci_host, move quirks field into Exynos driver's chip data, where it can be statically defined. No functional change. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- include/dwmmc.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include') diff --git a/include/dwmmc.h b/include/dwmmc.h index 8c2500da9ef..6edb9e1a59c 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -149,9 +149,6 @@ #define DWMCI_IDINTEN_TI BIT(0) #define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | DWMCI_IDINTEN_RI) -/* Quirks */ -#define DWMCI_QUIRK_DISABLE_SMU BIT(0) - /** * struct dwmci_idmac_regs - Offsets of IDMAC registers * @@ -180,7 +177,6 @@ struct dwmci_idmac_regs { * * @name: Device name * @ioaddr: Base I/O address of controller - * @quirks: Quick flags - see DWMCI_QUIRK_... * @caps: Capabilities - see MMC_MODE_... * @clock: Current clock frequency (after internal divider), Hz * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL @@ -200,7 +196,6 @@ struct dwmci_idmac_regs { struct dwmci_host { const char *name; void *ioaddr; - unsigned int quirks; unsigned int caps; unsigned int clock; unsigned int bus_hz; -- cgit v1.2.3