From 942ecc8bd81a7802fc3b82057da6a146909c0016 Mon Sep 17 00:00:00 2001 From: Sriram Dash Date: Tue, 6 Feb 2018 11:26:30 +0530 Subject: drivers: i2c: mxc: Update SYS_I2C_MXC_I2C support in Kconfig NXP layerscape platforms like ls1088a, ls2088a uses MXC I2C Controller. -Remove dependency of MX6 for the same. Update related configs to use Kconfig file. -Add SYS_I2C_MXC_I2C1,_I2C2,_I2C3,_I2C4 in Kconfig -Add CONFIG_SYS_MXC_I2C1_SPEED,_I2C2_,_I2C3_,_I2C4_ in Kconfig -Add CONFIG_SYS_MXC_I2C1_SLAVE,_I2C2_,_I2C3_,_I2C4_ in Kconfig Signed-off-by: Sriram Dash Signed-off-by: Priyanka Jain --- include/configs/ls1012a_common.h | 3 --- include/configs/ls1043a_common.h | 5 ----- include/configs/ls1046a_common.h | 5 ----- include/configs/ls1088a_common.h | 5 ----- include/configs/ls2080a_common.h | 5 ----- include/configs/ls2080a_emu.h | 3 --- include/configs/ls2080a_simu.h | 3 --- 7 files changed, 29 deletions(-) (limited to 'include') diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 46b3566adf8..73cd049f28d 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -77,9 +77,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 4c961862892..9e1b81a5649 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -148,11 +148,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 -#define CONFIG_SYS_I2C_MXC_I2C4 /* PCIe */ #ifndef SPL_NO_PCIE diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index b5af4b053bd..2494d9dc941 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -126,11 +126,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 -#define CONFIG_SYS_I2C_MXC_I2C4 /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index a3a393e472e..393ce4ff9da 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -67,11 +67,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index edf954dadd7..3e05b2788a1 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -77,11 +77,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h index 6b34edfbf11..c2fdc4daf6f 100644 --- a/include/configs/ls2080a_emu.h +++ b/include/configs/ls2080a_emu.h @@ -12,9 +12,6 @@ #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 -#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 -#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 - #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ #define SPD_EEPROM_ADDRESS1 0x51 diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h index dad1090f84f..103ebec79e2 100644 --- a/include/configs/ls2080a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -12,9 +12,6 @@ #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 -#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 -#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 - #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR -- cgit v1.3.1 From d8b3ec4d1a2c08ee325da8b61bcc4a3f804be2b4 Mon Sep 17 00:00:00 2001 From: Nandor Han Date: Thu, 15 Feb 2018 11:41:21 +0100 Subject: board: ge: ppd: Fix environment variable location This fixes environment variable location to avoid overlapping with U-Boot itself. Also more space for environment variables has been reserved to prevent future issues. Signed-off-by: Nandor Han Signed-off-by: Sebastian Reichel --- include/configs/mx53ppd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index ed8ac48e015..00132d17431 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -199,8 +199,8 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* FLASH and environment organization */ -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET (12 * 64 * 1024) +#define CONFIG_ENV_SIZE (10 * 1024) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 -- cgit v1.3.1 From dad75e241c0a62b48ad40f4edbf81aecbbce8fd7 Mon Sep 17 00:00:00 2001 From: Eran Matityahu Date: Wed, 28 Feb 2018 09:51:34 +0200 Subject: mx7_common: Fix SPL compilation with secure boot support enabled The SPL MISC driver support must be enabled, so that the driver can use OTP fuse to check if HAB is enabled. Signed-off-by: Eran Matityahu --- include/configs/mx7_common.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index defb38c5b33..6ebf2e1c686 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -59,6 +59,9 @@ /* Secure boot (HAB) support */ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CSF_SIZE 0x2000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#endif #endif #endif -- cgit v1.3.1 From 852cc548b3fdf6d5b46e2a96f876d14608ccdcf4 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Mon, 26 Mar 2018 15:27:34 +0100 Subject: warp7: Set u-boot serial# based on OTP value u-boot has a standard "serial#" environment variable that is suitable for storing the iSerial number we will supply via the USB device descriptor. serial# is automatically picked up by the disk subsystem in u-boot - thus providing a handy unique identifier in /dev/disk/by-id as detailed below. Storing the hardware serial identifier in serial# means we can change the serial# if we want before USB enumeration - thus making iSerial automatic via OTP but overridable if necessary. This patch reads the defined OTP fuse and sets environment variable "serial#" to the value read. With this patch in place the USB mass storage device will appear in /dev/disk/by-id with a unique name based on the OTP value. For example /dev/disk/by-id/usb-Linux_UMS_disk_0_WaRP7-0xf42400d3000001d4-0:0 Signed-off-by: Bryan O'Donoghue Cc: Fabio Estevam Cc: Rui Miguel Silva Cc: Ryan Harkin Reviewed-by: Fabio Estevam --- board/warp7/warp7.c | 14 ++++++++++++++ include/configs/warp7.h | 3 +++ 2 files changed, 17 insertions(+) (limited to 'include') diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index d422d63df55..327f656c44c 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -23,6 +23,8 @@ #include #include #include "../freescale/common/pfuze.h" +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -186,6 +188,10 @@ int board_usb_phy_mode(int port) int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; +#ifdef CONFIG_SERIAL_TAG + struct tag_serialnr serialnr; + char serial_string[0x20]; +#endif imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); @@ -197,5 +203,13 @@ int board_late_init(void) */ clrsetbits_le16(&wdog->wcr, 0, 0x10); +#ifdef CONFIG_SERIAL_TAG + /* Set serial# standard environment variable based on OTP settings */ + get_board_serial(&serialnr); + snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x", + serialnr.low, serialnr.high); + env_set("serial#", serial_string); +#endif + return 0; } diff --git a/include/configs/warp7.h b/include/configs/warp7.h index fe96988be7b..0c3b605de33 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -24,6 +24,9 @@ #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +/* Switch on SERIAL_TAG */ +#define CONFIG_SERIAL_TAG + #define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \ -- cgit v1.3.1 From f4d8fccd3884ea8f76503966b14d0c25129e23eb Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Mon, 26 Mar 2018 15:36:45 +0100 Subject: imximage: Encase majority of header in __ASSEMBLY__ declaration Subsequent patches will want to include imageimage.h but in doing so include it on an assembly compile path causing a range of compile errors. Fix the errors pre-emptively by encasing the majority of the declarations in imximage.h inside an ifdef __ASSEMBLY__ block. Signed-off-by: Bryan O'Donoghue Cc: Utkarsh Gupta Cc: Breno Lima Cc: Fabio Estevam Signed-off-by: Bryan O'Donoghue Tested-by: Breno Lima --- include/imximage.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/imximage.h b/include/imximage.h index de1ea8ff147..553b8523672 100644 --- a/include/imximage.h +++ b/include/imximage.h @@ -56,6 +56,7 @@ #define DCD_CHECK_BITS_SET_PARAM 0x14 #define DCD_CHECK_BITS_CLR_PARAM 0x04 +#ifndef __ASSEMBLY__ enum imximage_cmd { CMD_INVALID, CMD_IMAGE_VERSION, @@ -197,4 +198,5 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr, typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len, uint32_t entry_point, uint32_t flash_offset); +#endif /* __ASSEMBLY__ */ #endif /* _IMXIMAGE_H_ */ -- cgit v1.3.1 From 6c0e6b45f9bd4fdc795f4aec72dd13fd6fc6f617 Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Wed, 4 Apr 2018 10:50:17 +0200 Subject: board: ge: bx50v3: enable backlight on demand Enable display backlight only if a message needs to be displayed. The kernel re-initializes the backlight, which results in some unwanted artifacts. Signed-off-by: Ian Ray Signed-off-by: Sebastian Reichel --- board/ge/bx50v3/bx50v3.c | 45 ++++++++++++++++++++++++++++----------------- include/configs/ge_bx50v3.h | 1 + 2 files changed, 29 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index c7a29185bf4..46321ae666f 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -786,23 +786,6 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif -#ifdef CONFIG_VIDEO_IPUV3 - /* We need at least 200ms between power on and backlight on - * as per specifications from CHI MEI */ - mdelay(250); - - /* enable backlight PWM 1 */ - pwm_init(0, 0, 0); - - /* duty cycle 5000000ns, period: 5000000ns */ - pwm_config(0, 5000000, 5000000); - - /* Backlight Power */ - gpio_direction_output(LVDS_BACKLIGHT_GP, 1); - - pwm_enable(0); -#endif - /* board specific pmic init */ pmic_init(); @@ -843,3 +826,31 @@ int checkboard(void) printf("BOARD: %s\n", CONFIG_BOARD_NAME); return 0; } + +static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ +#ifdef CONFIG_VIDEO_IPUV3 + /* We need at least 200ms between power on and backlight on + * as per specifications from CHI MEI */ + mdelay(250); + + /* enable backlight PWM 1 */ + pwm_init(0, 0, 0); + + /* duty cycle 5000000ns, period: 5000000ns */ + pwm_config(0, 5000000, 5000000); + + /* Backlight Power */ + gpio_direction_output(LVDS_BACKLIGHT_GP, 1); + + pwm_enable(0); +#endif + + return 0; +} + +U_BOOT_CMD( + bx50_backlight_enable, 1, 1, do_backlight_enable, + "enable Bx50 backlight", + "" +); diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index cbfe30d536d..925507fe81f 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -128,6 +128,7 @@ "swappartitions=" \ "setexpr partnum 3 - ${partnum}\0" \ "failbootcmd=" \ + "bx50_backlight_enable; " \ "msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \ "echo $msg; " \ "setenv stdout vga; " \ -- cgit v1.3.1 From dd4671cb3f12a6e24eec8b76cbcb09a35bd30738 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 5 Apr 2018 09:04:38 +0200 Subject: imx: board: Add support for the K+P's kp_imx6q_tpc board This commit provides support for Kieback & Peter GmbH IMX6Q based TPC board. U-boot console output: U-Boot SPL 2018.05-rc1-00005-g631e2d01fd (Apr 04 2018 - 21:16:24 +0200) Trying to boot from MMC1 U-Boot 2018.05-rc1-00005-g631e2d01fd (Apr 04 2018 - 21:16:24 +0200) CPU: Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz) CPU: Extended Commercial temperature grade (-20C to 105C) at 37C Reset cause: POR Board: K+P KP_IMX6Q_TPC i.MX6Q Watchdog enabled I2C: ready DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: FEC [PRIME] Autoboot in 3 seconds --- arch/arm/mach-imx/mx6/Kconfig | 11 + board/k+p/kp_imx6q_tpc/Kconfig | 12 ++ board/k+p/kp_imx6q_tpc/MAINTAINERS | 6 + board/k+p/kp_imx6q_tpc/Makefile | 11 + board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c | 302 ++++++++++++++++++++++++++ board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c | 338 ++++++++++++++++++++++++++++++ configs/kp_imx6q_tpc_defconfig | 42 ++++ include/configs/kp_imx6q_tpc.h | 141 +++++++++++++ 8 files changed, 863 insertions(+) create mode 100644 board/k+p/kp_imx6q_tpc/Kconfig create mode 100644 board/k+p/kp_imx6q_tpc/MAINTAINERS create mode 100644 board/k+p/kp_imx6q_tpc/Makefile create mode 100644 board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c create mode 100644 board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c create mode 100644 configs/kp_imx6q_tpc_defconfig create mode 100644 include/configs/kp_imx6q_tpc.h (limited to 'include') diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index d4ce38db8d8..aa6f5facbf8 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -387,6 +387,16 @@ config TARGET_TBS2910 config TARGET_TITANIUM bool "titanium" +config TARGET_KP_IMX6Q_TPC + bool "K+P KP_IMX6Q_TPC i.MX6 Quad" + select MX6QDL + select BOARD_LATE_INIT + select BOARD_EARLY_INIT_F + select SUPPORT_SPL + select DM + select DM_THERMAL + imply CMD_SPL + config TARGET_TQMA6 bool "TQ Systems TQMa6 board" select BOARD_LATE_INIT @@ -493,6 +503,7 @@ source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/toradex/apalis_imx6/Kconfig" source "board/toradex/colibri_imx6/Kconfig" +source "board/k+p/kp_imx6q_tpc/Kconfig" source "board/udoo/Kconfig" source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" diff --git a/board/k+p/kp_imx6q_tpc/Kconfig b/board/k+p/kp_imx6q_tpc/Kconfig new file mode 100644 index 00000000000..62e34978ecd --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KP_IMX6Q_TPC + +config SYS_BOARD + default "kp_imx6q_tpc" + +config SYS_VENDOR + default "k+p" + +config SYS_CONFIG_NAME + default "kp_imx6q_tpc" + +endif diff --git a/board/k+p/kp_imx6q_tpc/MAINTAINERS b/board/k+p/kp_imx6q_tpc/MAINTAINERS new file mode 100644 index 00000000000..6c4c8dd28e3 --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/MAINTAINERS @@ -0,0 +1,6 @@ +KP_IMX6Q_TPC BOARD +M: Lukasz Majewski +S: Maintained +F: board/k+p/kp_imx6q_tpc/ +F: include/configs/kp_imx6q_tpc.h +F: configs/kp_imx6q_tpc_defconfig diff --git a/board/k+p/kp_imx6q_tpc/Makefile b/board/k+p/kp_imx6q_tpc/Makefile new file mode 100644 index 00000000000..51cbd3e8439 --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2018 Lukasz Majewski +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := kp_imx6q_tpc_spl.o +else +obj-y := kp_imx6q_tpc.o +endif diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c new file mode 100644 index 00000000000..9a5b88029f8 --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c @@ -0,0 +1,302 @@ +/* + * K+P iMX6Q KP_IMX6Q_TPC board configuration + * + * Copyright (C) 2018 Lukasz Majewski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ENET_PAD_CTRL \ + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) + +#define I2C_PAD_CTRL \ + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL | PC, + .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 | PC, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const enet_pads[] = { + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + /* AR8031 PHY Reset */ + IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void eth_phy_reset(void) +{ + /* Reset AR8031 PHY */ + gpio_direction_output(IMX_GPIO_NR(1, 25), 0); + mdelay(10); + gpio_set_value(IMX_GPIO_NR(1, 25), 1); + udelay(100); +} + +static int setup_fec_clock(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* set gpr1[21] to select anatop clock */ + clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21); + + return enable_fec_anatop_clock(0, ENET_50MHZ); +} + +int board_eth_init(bd_t *bis) +{ + SETUP_IOMUX_PADS(enet_pads); + setup_fec_clock(); + eth_phy_reset(); + + return cpu_eth_init(bis); +} + +static int ar8031_phy_fixup(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8031 output a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + ar8031_phy_fixup(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { USDHC2_BASE_ADDR }, + { USDHC4_BASE_ADDR }, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + return !gpio_get_value(USDHC2_CD_GPIO); + case USDHC4_BASE_ADDR: + return 1; /* eMMC/uSDHC4 is always present */ + } + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 micro SD + * mmc2 eMMC + */ + gpio_direction_input(USDHC2_CD_GPIO); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +static void setup_usb(void) +{ + /* + * Set daisy chain for otg_pin_id on MX6Q. + * For MX6DL, this bit is reserved. + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return USB_INIT_DEVICE; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + break; + case 1: + gpio_direction_output(IMX_GPIO_NR(3, 31), !!on); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + + return 0; +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + + return 0; +} + +int board_init(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* Enable eim_slow clocks */ + setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info1); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + /* 8 bit bus width */ + {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + env_set("boardname", "kp-tpc"); + env_set("boardsoc", "imx6q"); + return 0; +} + +int checkboard(void) +{ + puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n"); + return 0; +} diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c new file mode 100644 index 00000000000..3fdfea75469 --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c @@ -0,0 +1,338 @@ +/* + * K+P iMX6Q KP_IMX6Q_TPC board configuration + * + * Copyright (C) 2018 Lukasz Majewski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define UART_PAD_CTRL \ + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL \ + (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +DECLARE_GLOBAL_DATA_PTR; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +/* onboard microSD */ +static iomux_v3_cfg_t const usdhc2_pads[] = { + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +/* eMMC */ +static iomux_v3_cfg_t const usdhc4_pads[] = { + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +/* SD */ +static void setup_iomux_sd(void) +{ + SETUP_IOMUX_PADS(usdhc2_pads); + SETUP_IOMUX_PADS(usdhc4_pads); +} + +/* UART */ +static iomux_v3_cfg_t const uart1_pads[] = { + IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +/* USB */ +static iomux_v3_cfg_t const usb_pads[] = { + IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void setup_iomux_usb(void) +{ + SETUP_IOMUX_PADS(usb_pads); +} + +/* DDR3 */ +static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = 0x00000030, + .dram_sdclk_1 = 0x00000030, + .dram_cas = 0x00000030, + .dram_ras = 0x00000030, + .dram_reset = 0x00000030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00000030, + .dram_sdodt1 = 0x00000030, + + .dram_sdqs0 = 0x00000018, + .dram_sdqs1 = 0x00000018, + .dram_sdqs2 = 0x00000018, + .dram_sdqs3 = 0x00000018, + .dram_sdqs4 = 0x00000018, + .dram_sdqs5 = 0x00000018, + .dram_sdqs6 = 0x00000018, + .dram_sdqs7 = 0x00000018, + + .dram_dqm0 = 0x00000018, + .dram_dqm1 = 0x00000018, + .dram_dqm2 = 0x00000018, + .dram_dqm3 = 0x00000018, + .dram_dqm4 = 0x00000018, + .dram_dqm5 = 0x00000018, + .dram_dqm6 = 0x00000018, + .dram_dqm7 = 0x00000018, +}; + +static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000018, + .grp_b1ds = 0x00000018, + .grp_b2ds = 0x00000018, + .grp_b3ds = 0x00000018, + .grp_b4ds = 0x00000018, + .grp_b5ds = 0x00000018, + .grp_b6ds = 0x00000018, + .grp_b7ds = 0x00000018, +}; + +static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = { + .p0_mpwldectrl0 = 0x001F001F, + .p0_mpwldectrl1 = 0x001F001F, + .p1_mpwldectrl0 = 0x001F001F, + .p1_mpwldectrl1 = 0x001F001F, + .p0_mpdgctrl0 = 0x43270338, + .p0_mpdgctrl1 = 0x03200314, + .p1_mpdgctrl0 = 0x431A032F, + .p1_mpdgctrl1 = 0x03200263, + .p0_mprddlctl = 0x4B434748, + .p1_mprddlctl = 0x4445404C, + .p0_mpwrdlctl = 0x38444542, + .p1_mpwrdlctl = 0x4935493A, +}; + +/* MT41K256M16 (4Gb density) */ +static const struct mx6_ddr3_cfg mt41k256m16 = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +#ifdef CONFIG_MX6_DDRCAL +static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + struct mx6_mmdc_calibration calibration = {0}; + + mmdc_read_calibration(sysinfo, &calibration); + + debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0); + debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1); + debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl); + debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl); + debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0); + debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1); + debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0); + debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1); + debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl); + debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl); + debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0); + debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1); +} + +static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + int ret; + + /* Perform DDR DRAM calibration */ + udelay(100); + ret = mmdc_do_write_level_calibration(sysinfo); + if (ret) { + printf("DDR: Write level calibration error [%d]\n", ret); + return; + } + + ret = mmdc_do_dqs_calibration(sysinfo); + if (ret) { + printf("DDR: DQS calibration error [%d]\n", ret); + return; + } + + spl_dram_print_cal(sysinfo); +} +#endif /* CONFIG_MX6_DDRCAL */ + +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = 2, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .pd_fast_exit = 1, /* enable precharge power-down fast exit */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ + }; + + mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16); + +#ifdef CONFIG_MX6_DDRCAL + spl_dram_perform_cal(&sysinfo); +#endif +} + +struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC2_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/uSDHC4 is always present */ + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bd) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned int reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x3 SD4 + */ + + switch (reg & 0x3) { + case 0x1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x3: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + } + + return fsl_esdhc_initialize(bd, &usdhc_cfg[0]); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* setup GP timer */ + timer_init(); + + setup_iomux_sd(); + setup_iomux_uart(); + setup_iomux_usb(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig new file mode 100644 index 00000000000..d2c6e2e6ba4 --- /dev/null +++ b/configs/kp_imx6q_tpc_defconfig @@ -0,0 +1,42 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_MX6_DDRCAL=y +CONFIG_TARGET_KP_IMX6Q_TPC=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SPL=y +CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR="." +# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_ENV_IS_IN_MMC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h new file mode 100644 index 00000000000..fae2faec2f3 --- /dev/null +++ b/include/configs/kp_imx6q_tpc.h @@ -0,0 +1,141 @@ +/* + * K+P iMX6Q KP_IMX6Q_TPC board configuration + * + * Copyright (C) 2018 Lukasz Majewski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __KP_IMX6Q_TPC_IMX6_CONFIG_H_ +#define __KP_IMX6Q_TPC_IMX6_CONFIG_H_ + +#include + +#include "mx6_common.h" + +/* SPL */ +#include "imx6_spl.h" /* common IMX6 SPL configuration */ + +/* Miscellaneous configurable options */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_BOUNCE_BUFFER + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) + +/* FEC ethernet */ +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_ARP_TIMEOUT 200UL + +/* Fuses */ +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */ + +/* UART */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ +#endif + +/* Watchdog */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_IMX_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ + "fdt_addr=0x18000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x10008000\0" \ + "fdt_addr_r=0x13000000\0" \ + "ramdisk_addr_r=0x18000000\0" \ + "scriptaddr=0x14000000\0" \ + "kernel_file=fitImage\0"\ + "rdinit=/sbin/init\0" \ + "addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \ + "fit_config=mx6q_tpc70_conf\0" \ + "upd_image=st.4k\0" \ + "updargs=setenv bootargs console=${console} ${smp}"\ + "rdinit=${rdinit} ${debug} ${displayargs}\0" \ + "loadusb=usb start; " \ + "fatload usb 0 ${loadaddr} ${upd_image}\0" \ + "usbupd=echo Booting update from usb ...; " \ + "setenv bootargs; " \ + "run updargs; " \ + "run loadusb; " \ + "bootm ${loadaddr}#${fit_config}\0" \ + BOOTENV + +#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) + +#include +#endif + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment */ +#define CONFIG_ENV_SIZE (SZ_8K) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#endif /* __KP_IMX6Q_TPC_IMX6_CONFIG_H_ */ -- cgit v1.3.1 From ebca6013c086356419a462dc1adbef858a5ada67 Mon Sep 17 00:00:00 2001 From: Vanessa Maegima Date: Fri, 6 Apr 2018 16:54:41 -0300 Subject: pico-imx7d: Replace fatload command Replace fatload with the fs generic loading interface ('load' command). Signed-off-by: Vanessa Maegima Reviewed-by: Fabio Estevam --- configs/pico-imx7d_defconfig | 1 + include/configs/pico-imx7d.h | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index edfe7257bdd..b85486db4ea 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y CONFIG_PHYLIB=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index ee483635906..a81548cb001 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -50,8 +50,8 @@ "finduuid=part uuid mmc 0:2 uuid\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=PARTUUID=${uuid} rootwait rw\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run finduuid; " \ "run mmcargs; " \ -- cgit v1.3.1 From bcca8aa9ee43be0f0bf7c14ce34cfbbd891c373e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 6 Apr 2018 16:27:54 -0400 Subject: imx31_phycore: Delete This platform has been marked as orphaned since September 2013, remove. Signed-off-by: Tom Rini --- arch/arm/Kconfig | 12 --- board/imx31_phycore/Kconfig | 12 --- board/imx31_phycore/MAINTAINERS | 11 --- board/imx31_phycore/Makefile | 9 --- board/imx31_phycore/imx31_phycore.c | 154 ----------------------------------- board/imx31_phycore/lowlevel_init.S | 88 -------------------- configs/imx31_phycore_defconfig | 19 ----- configs/imx31_phycore_eet_defconfig | 25 ------ drivers/video/Makefile | 1 - drivers/video/s6e63d6.c | 60 -------------- include/configs/imx31_phycore.h | 156 ------------------------------------ include/s6e63d6.h | 21 ----- 12 files changed, 568 deletions(-) delete mode 100644 board/imx31_phycore/Kconfig delete mode 100644 board/imx31_phycore/MAINTAINERS delete mode 100644 board/imx31_phycore/Makefile delete mode 100644 board/imx31_phycore/imx31_phycore.c delete mode 100644 board/imx31_phycore/lowlevel_init.S delete mode 100644 configs/imx31_phycore_defconfig delete mode 100644 configs/imx31_phycore_eet_defconfig delete mode 100644 drivers/video/s6e63d6.c delete mode 100644 include/configs/imx31_phycore.h delete mode 100644 include/s6e63d6.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2c52ff025a2..056dacc16f1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -444,17 +444,6 @@ config TARGET_X600 select SUPPORT_SPL select PL011_SERIAL -config TARGET_IMX31_PHYCORE - bool "Support imx31_phycore_eet" - select CPU_ARM1136 - select BOARD_EARLY_INIT_F - -config TARGET_IMX31_PHYCORE_EET - bool "Support imx31_phycore_eet" - select BOARD_LATE_INIT - select CPU_ARM1136 - select BOARD_EARLY_INIT_F - config TARGET_MX31ADS bool "Support mx31ads" select CPU_ARM1136 @@ -1317,7 +1306,6 @@ source "board/gumstix/pepper/Kconfig" source "board/h2200/Kconfig" source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/poplar/Kconfig" -source "board/imx31_phycore/Kconfig" source "board/isee/igep003x/Kconfig" source "board/phytec/pcm051/Kconfig" source "board/silica/pengwyn/Kconfig" diff --git a/board/imx31_phycore/Kconfig b/board/imx31_phycore/Kconfig deleted file mode 100644 index e897ee1c3ac..00000000000 --- a/board/imx31_phycore/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IMX31_PHYCORE || TARGET_IMX31_PHYCORE_EET - -config SYS_BOARD - default "imx31_phycore" - -config SYS_SOC - default "mx31" - -config SYS_CONFIG_NAME - default "imx31_phycore" - -endif diff --git a/board/imx31_phycore/MAINTAINERS b/board/imx31_phycore/MAINTAINERS deleted file mode 100644 index 41f6cae81b5..00000000000 --- a/board/imx31_phycore/MAINTAINERS +++ /dev/null @@ -1,11 +0,0 @@ -IMX31_PHYCORE BOARD -#M: - -S: Maintained -F: board/imx31_phycore/ -F: include/configs/imx31_phycore.h -F: configs/imx31_phycore_defconfig - -IMX31_PHYCORE_EET BOARD -#M: (resigned) Guennadi Liakhovetski -S: Orphan (since 2013-09) -F: configs/imx31_phycore_eet_defconfig diff --git a/board/imx31_phycore/Makefile b/board/imx31_phycore/Makefile deleted file mode 100644 index e781c139362..00000000000 --- a/board/imx31_phycore/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := imx31_phycore.o -obj-y += lowlevel_init.o diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c deleted file mode 100644 index 653246615fd..00000000000 --- a/board/imx31_phycore/imx31_phycore.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - return 0; -} - -int board_init(void) -{ - - gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ - gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ - - return 0; -} - -int board_early_init_f(void) -{ - /* CS0: Nor Flash */ - static const struct mxc_weimcs cs0 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) - }; - - /* CS1: Network Controller */ - static const struct mxc_weimcs cs1 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) - }; - - /* CS4: SRAM */ - static const struct mxc_weimcs cs4 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) - }; - - mxc_setup_weimcs(0, &cs0); - mxc_setup_weimcs(1, &cs1); - mxc_setup_weimcs(4, &cs4); - - /* setup pins for UART1 */ - mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); - mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); - mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); - mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); - - /* setup pins for I2C2 (for EEPROM, RTC) */ - mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL); - mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA); - - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ -#ifdef CONFIG_S6E63D6 - struct s6e63d6 data = { - /* - * See comment in mxc_spi.c::decode_cs() for .cs field format. - * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect - * 2 of the SPI controller #1, since it is unused. - */ - .cs = 2 | (57 << 8), - .bus = 0, - .id = 0, - }; - int ret; - - /* SPI1 */ - mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK); - mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B); - mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI); - mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO); - mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B); - mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B); - mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B); - - /* start SPI1 clock */ - __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2); - - /* GPIO 57 */ - /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */ - mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO)); - - /* SPI1 CS2 is free */ - ret = s6e63d6_init(&data); - if (ret) - return ret; - - /* - * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC - * OLED display connected to a S6E63D6 SPI display controller in the - * 18 bit RGB mode - */ - s6e63d6_index(&data, 2); - s6e63d6_param(&data, 0x0182); - s6e63d6_index(&data, 3); - s6e63d6_param(&data, 0x8130); - s6e63d6_index(&data, 0x10); - s6e63d6_param(&data, 0x0000); - s6e63d6_index(&data, 5); - s6e63d6_param(&data, 0x0001); - s6e63d6_index(&data, 0x22); -#endif - return 0; -} -#endif - -int checkboard (void) -{ - printf("Board: Phytec phyCore i.MX31\n"); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S deleted file mode 100644 index 6ea3878ef9c..00000000000 --- a/board/imx31_phycore/lowlevel_init.S +++ /dev/null @@ -1,88 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -.macro REG reg, val - ldr r2, =\reg - ldr r3, =\val - str r3, [r2] -.endm - -.macro REG8 reg, val - ldr r2, =\reg - ldr r3, =\val - strb r3, [r2] -.endm - -.macro DELAY loops - ldr r2, =\loops -1: - subs r2, r2, #1 - nop - bcs 1b -.endm - -.globl lowlevel_init -lowlevel_init: - - REG IPU_CONF, IPU_CONF_DI_EN - REG CCM_CCMR, 0x074B0BF5 - - DELAY 0x40000 - - REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE - REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS - - REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0) - - REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd) - - REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1) - - REG 0x43FAC26C, 0 /* SDCLK */ - REG 0x43FAC270, 0 /* CAS */ - REG 0x43FAC274, 0 /* RAS */ - REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */ - REG 0x43FAC284, 0 /* DQM3 */ - REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ - REG 0x43FAC28C, 0 - REG 0x43FAC290, 0 - REG 0x43FAC294, 0 - REG 0x43FAC298, 0 - REG 0x43FAC29C, 0 - REG 0x43FAC2A0, 0 - REG 0x43FAC2A4, 0 - REG 0x43FAC2A8, 0 - REG 0x43FAC2AC, 0 - REG 0x43FAC2B0, 0 - REG 0x43FAC2B4, 0 - REG 0x43FAC2B8, 0 - REG 0x43FAC2BC, 0 - REG 0x43FAC2C0, 0 - REG 0x43FAC2C4, 0 - REG 0x43FAC2C8, 0 - REG 0x43FAC2CC, 0 - REG 0x43FAC2D0, 0 - REG 0x43FAC2D4, 0 - REG 0x43FAC2D8, 0 - REG 0x43FAC2DC, 0 - REG 0xB8001010, 0x00000004 - REG 0xB8001004, 0x006ac73a - REG 0xB8001000, 0x92100000 - REG 0x80000f00, 0x12344321 - REG 0xB8001000, 0xa2100000 - REG 0x80000000, 0x12344321 - REG 0x80000000, 0x12344321 - REG 0xB8001000, 0xb2100000 - REG8 0x80000033, 0xda - REG8 0x81000000, 0xff - REG 0xB8001000, 0x82226080 - REG 0x80000000, 0xDEADBEEF - REG 0xB8001010, 0x0000000c - - mov pc, lr diff --git a/configs/imx31_phycore_defconfig b/configs/imx31_phycore_defconfig deleted file mode 100644 index bd5717bb893..00000000000 --- a/configs/imx31_phycore_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_IMX31_PHYCORE=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -CONFIG_BOOTDELAY=3 -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="uboot> " -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)" -CONFIG_ENV_IS_IN_EEPROM=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_NETDEVICES=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0xa8000000 -CONFIG_SMC911X_32_BIT=y diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig deleted file mode 100644 index 7be4f899a8e..00000000000 --- a/configs/imx31_phycore_eet_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_IMX31_PHYCORE_EET=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)" -CONFIG_ENV_IS_IN_EEPROM=y -CONFIG_MXC_GPIO=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_NETDEVICES=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0xa8000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_MXC_SPI=y -CONFIG_VIDEO=y diff --git a/drivers/video/Makefile b/drivers/video/Makefile index dfafe08fc50..ab897e145c9 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -30,7 +30,6 @@ obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o obj-$(CONFIG_PXA_LCD) += pxa_lcd.o obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o obj-$(CONFIG_S6E8AX0) += s6e8ax0.o -obj-$(CONFIG_S6E63D6) += s6e63d6.o obj-$(CONFIG_LD9040) += ld9040.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o diff --git a/drivers/video/s6e63d6.c b/drivers/video/s6e63d6.c deleted file mode 100644 index f077260d76d..00000000000 --- a/drivers/video/s6e63d6.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2009 - * Guennadi Liakhovetski, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include - -/* - * Each transfer is performed as: - * 1. chip-select active - * 2. send 8-bit start code - * 3. send 16-bit data - * 4. chip-select inactive - */ -static int send_word(struct s6e63d6 *data, u8 rs, u16 word) -{ - /* - * The start byte looks like (binary): - * 01110 - * RS is 0 for index or 1 for data, and R/W is 0 for write. - */ - u32 buf8 = 0x70 | data->id | (rs & 2); - u32 buf16 = cpu_to_le16(word); - u32 buf_in; - int err; - - err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN); - if (err) - return err; - - return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END); -} - -/* Index and param differ in Register Select bit */ -int s6e63d6_index(struct s6e63d6 *data, u8 idx) -{ - return send_word(data, 0, idx); -} - -int s6e63d6_param(struct s6e63d6 *data, u16 param) -{ - return send_word(data, 2, param); -} - -int s6e63d6_init(struct s6e63d6 *data) -{ - if (data->id != 0 && data->id != 4) { - printf("s6e63d6: invalid ID %u\n", data->id); - return 1; - } - - data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3); - if (!data->slave) - return 1; - - return 0; -} diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h deleted file mode 100644 index 3b5eb4fa6cf..00000000000 --- a/include/configs/imx31_phycore.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments. - * Richard Woodruff - * Kshitij Gupta - * - * Configuration settings for the phyCORE-i.MX31 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* High Level Configuration Options */ -#define CONFIG_MX31 /* This is a mx31 */ -#define CONFIG_MX31_CLK32 32000 - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 - -/*********************************************************** - * Command definition - ***********************************************************/ - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.23.168 -#define CONFIG_SERVERIP 192.168.23.2 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \ - "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ - "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ - "bootargs_flash=setenv bootargs $(bootargs) " \ - "root=/dev/mtdblock2 rootfstype=jffs2\0" \ - "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \ - "bootcmd=run bootcmd_net\0" \ - "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \ - "tftpboot 0x80000000 $(uimage);bootm\0" \ - "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \ - "bootm 0x80000000\0" \ - "unlock=yes\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "prg_uboot=tftpboot 0x80000000 $(uboot);" \ - "protect off 0xa0000000 +0x20000;" \ - "erase 0xa0000000 +0x20000;" \ - "cp.b 0x80000000 0xa0000000 $(filesize)\0" \ - "prg_kernel=tftpboot 0x80000000 $(uimage);" \ - "erase 0xa0040000 +0x180000;" \ - "cp.b 0x80000000 0xa0040000 $(filesize)\0" \ - "prg_jffs2=tftpboot 0x80000000 $(jffs2);" \ - "erase 0xa01c0000 0xa1ffffff;" \ - "cp.b 0x80000000 0xa01c0000 $(filesize)\0" \ - "videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \ - "pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \ - "sync:1241513985,vmode:0\0" - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE 0xa0000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */ -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */ -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */ - -/* - * CFI FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */ - -/* - * Timeout for Flash Erase and Flash Write - * timeout values are in ticks - */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) - -/* - * JFFS2 partitions - */ -#define CONFIG_JFFS2_DEV "nor0" - -/* EET platform additions */ -#ifdef CONFIG_TARGET_IMX31_PHYCORE_EET -#define CONFIG_HARD_SPI - -#define CONFIG_S6E63D6 - -#define CONFIG_VIDEO_MX3 -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_BMP_16BPP -#endif - -#endif /* __CONFIG_H */ diff --git a/include/s6e63d6.h b/include/s6e63d6.h deleted file mode 100644 index aa583eed1b8..00000000000 --- a/include/s6e63d6.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2009 - * Guennadi Liakhovetski, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _S6E63D6_H_ -#define _S6E63D6_H_ - -struct s6e63d6 { - unsigned int bus; - unsigned int cs; - unsigned int id; - struct spi_slave *slave; -}; - -extern int s6e63d6_init(struct s6e63d6 *data); -extern int s6e63d6_index(struct s6e63d6 *data, u8 idx); -extern int s6e63d6_param(struct s6e63d6 *data, u16 param); - -#endif -- cgit v1.3.1 From 448fc44fb87cb678594541c6695f49debb5c1be3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 6 Apr 2018 16:27:55 -0400 Subject: mx31ads: Delete This platform has been marked as orphaned since September 2013, remove. Signed-off-by: Tom Rini --- arch/arm/Kconfig | 6 - board/freescale/mx31ads/Kconfig | 15 -- board/freescale/mx31ads/MAINTAINERS | 6 - board/freescale/mx31ads/Makefile | 8 - board/freescale/mx31ads/lowlevel_init.S | 268 -------------------------------- board/freescale/mx31ads/mx31ads.c | 114 -------------- board/freescale/mx31ads/u-boot.lds | 110 ------------- configs/mx31ads_defconfig | 15 -- include/configs/mx31ads.h | 145 ----------------- 9 files changed, 687 deletions(-) delete mode 100644 board/freescale/mx31ads/Kconfig delete mode 100644 board/freescale/mx31ads/MAINTAINERS delete mode 100644 board/freescale/mx31ads/Makefile delete mode 100644 board/freescale/mx31ads/lowlevel_init.S delete mode 100644 board/freescale/mx31ads/mx31ads.c delete mode 100644 board/freescale/mx31ads/u-boot.lds delete mode 100644 configs/mx31ads_defconfig delete mode 100644 include/configs/mx31ads.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 056dacc16f1..49bcf995207 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -444,11 +444,6 @@ config TARGET_X600 select SUPPORT_SPL select PL011_SERIAL -config TARGET_MX31ADS - bool "Support mx31ads" - select CPU_ARM1136 - select BOARD_EARLY_INIT_F - config TARGET_MX31PDK bool "Support mx31pdk" select BOARD_LATE_INIT @@ -1296,7 +1291,6 @@ source "board/freescale/ls1046ardb/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" -source "board/freescale/mx31ads/Kconfig" source "board/freescale/mx31pdk/Kconfig" source "board/freescale/mx35pdk/Kconfig" source "board/freescale/s32v234evb/Kconfig" diff --git a/board/freescale/mx31ads/Kconfig b/board/freescale/mx31ads/Kconfig deleted file mode 100644 index eeeb6f490fd..00000000000 --- a/board/freescale/mx31ads/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX31ADS - -config SYS_BOARD - default "mx31ads" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx31" - -config SYS_CONFIG_NAME - default "mx31ads" - -endif diff --git a/board/freescale/mx31ads/MAINTAINERS b/board/freescale/mx31ads/MAINTAINERS deleted file mode 100644 index 5f6ec268c7e..00000000000 --- a/board/freescale/mx31ads/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX31ADS BOARD -#M: (resigned) Guennadi Liakhovetski -S: Orphan (since 2013-09) -F: board/freescale/mx31ads/ -F: include/configs/mx31ads.h -F: configs/mx31ads_defconfig diff --git a/board/freescale/mx31ads/Makefile b/board/freescale/mx31ads/Makefile deleted file mode 100644 index 5e1440d5966..00000000000 --- a/board/freescale/mx31ads/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2008, Guennadi Liakhovetski -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mx31ads.o -obj-y += lowlevel_init.o diff --git a/board/freescale/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S deleted file mode 100644 index fcb5549d774..00000000000 --- a/board/freescale/mx31ads/lowlevel_init.S +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright (C) 2008, Guennadi Liakhovetski - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -.macro REG reg, val - ldr r2, =\reg - ldr r3, =\val - str r3, [r2] -.endm - -.macro REG8 reg, val - ldr r2, =\reg - ldr r3, =\val - strb r3, [r2] -.endm - -.macro DELAY loops - ldr r2, =\loops -1: - subs r2, r2, #1 - nop - bcs 1b -.endm - -/* RedBoot: AIPS setup - Only setup MPROTx registers. - * The PACR default values are good.*/ -.macro init_aips - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - ldr r0, =0x43F00000 - ldr r1, =0x77777777 - str r1, [r0, #0x00] - str r1, [r0, #0x04] - ldr r0, =0x53F00000 - str r1, [r0, #0x00] - str r1, [r0, #0x04] - - /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ - ldr r0, =0x43F00000 - ldr r1, =0x0 - str r1, [r0, #0x40] - str r1, [r0, #0x44] - str r1, [r0, #0x48] - str r1, [r0, #0x4C] - ldr r1, [r0, #0x50] - and r1, r1, #0x00FFFFFF - str r1, [r0, #0x50] - - ldr r0, =0x53F00000 - ldr r1, =0x0 - str r1, [r0, #0x40] - str r1, [r0, #0x44] - str r1, [r0, #0x48] - str r1, [r0, #0x4C] - ldr r1, [r0, #0x50] - and r1, r1, #0x00FFFFFF - str r1, [r0, #0x50] -.endm /* init_aips */ - -/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */ -.macro init_max - ldr r0, =0x43F04000 - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ - ldr r1, =0x00302154 - str r1, [r0, #0x000] /* for S0 */ - str r1, [r0, #0x100] /* for S1 */ - str r1, [r0, #0x200] /* for S2 */ - str r1, [r0, #0x300] /* for S3 */ - str r1, [r0, #0x400] /* for S4 */ - /* SGPCR - always park on last master */ - ldr r1, =0x10 - str r1, [r0, #0x010] /* for S0 */ - str r1, [r0, #0x110] /* for S1 */ - str r1, [r0, #0x210] /* for S2 */ - str r1, [r0, #0x310] /* for S3 */ - str r1, [r0, #0x410] /* for S4 */ - /* MGPCR - restore default values */ - ldr r1, =0x0 - str r1, [r0, #0x800] /* for M0 */ - str r1, [r0, #0x900] /* for M1 */ - str r1, [r0, #0xA00] /* for M2 */ - str r1, [r0, #0xB00] /* for M3 */ - str r1, [r0, #0xC00] /* for M4 */ - str r1, [r0, #0xD00] /* for M5 */ -.endm /* init_max */ - -/* RedBoot: M3IF setup */ -.macro init_m3if - /* Configure M3IF registers */ - ldr r1, =0xB8003000 - /* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ - ldr r0, =0x00000040 - str r0, [r1] /* M3IF control reg */ -.endm /* init_m3if */ - -/* RedBoot: To support 133MHz DDR */ -.macro init_drive_strength - /* - * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits - * in SW_PAD_CTL registers - */ - - /* SDCLK */ - ldr r1, =0x43FAC200 - ldr r0, [r1, #0x6C] - bic r0, r0, #(1 << 12) - str r0, [r1, #0x6C] - - /* CAS */ - ldr r0, [r1, #0x70] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x70] - - /* RAS */ - ldr r0, [r1, #0x74] - bic r0, r0, #(1 << 2) - str r0, [r1, #0x74] - - /* CS2 (CSD0) */ - ldr r0, [r1, #0x7C] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x7C] - - /* DQM3 */ - ldr r0, [r1, #0x84] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x84] - - /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ - ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */ -pad_loop: - ldr r0, [r1, #0x88] - bic r0, r0, #(1 << 22) - bic r0, r0, #(1 << 12) - bic r0, r0, #(1 << 2) - str r0, [r1, #0x88] - add r1, r1, #4 - subs r2, r2, #0x1 - bne pad_loop -.endm /* init_drive_strength */ - -/* CPLD on CS4 setup */ -.macro init_cs4 - ldr r0, =WEIM_BASE - ldr r1, =0x0000D843 - str r1, [r0, #0x40] - ldr r1, =0x22252521 - str r1, [r0, #0x44] - ldr r1, =0x22220A00 - str r1, [r0, #0x48] -.endm /* init_cs4 */ - -.globl lowlevel_init -lowlevel_init: - - /* Redboot initializes very early AIPS, what for? - * Then it also initializes Multi-Layer AHB Crossbar Switch, - * M3IF */ - /* Also setup the Peripheral Port Remap register inside the core */ - ldr r0, =0x40000015 /* start from AIPS 2GB region */ - mcr p15, 0, r0, c15, c2, 4 - - init_aips - - init_max - - init_m3if - - init_drive_strength - - init_cs4 - - /* Image Processing Unit: */ - /* Too early to switch display on? */ - REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */ - /* Clock Control Module: */ - REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */ - - DELAY 0x40000 - - REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */ - REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */ - - /* PBC CPLD on CS4 */ - mov r1, #CS4_BASE - ldrh r1, [r1, #0x2] - /* Is 27MHz switch set? */ - ands r1, r1, #0x10 - - /* 532-133-66.5 */ - ldr r0, =CCM_BASE - ldr r1, =0xFF871D58 - /* PDR0 */ - str r1, [r0, #0x4] - ldreq r1, MPCTL_PARAM_532 - ldrne r1, MPCTL_PARAM_532_27 - /* MPCTL */ - str r1, [r0, #0x10] - - /* Set UPLL=240MHz, USB=60MHz */ - ldr r1, =0x49FCFE7F - /* PDR1 */ - str r1, [r0, #0x8] - ldreq r1, UPCTL_PARAM_240 - ldrne r1, UPCTL_PARAM_240_27 - /* UPCTL */ - str r1, [r0, #0x14] - /* default CLKO to 1/8 of the ARM core */ - mov r1, #0x000002C0 - add r1, r1, #0x00000006 - /* COSR */ - str r1, [r0, #0x1c] - - /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */ -/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/ - - /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */ -/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/ - /* Default: 1, 4, 12, 1 */ - REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) - - /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ - REG 0xB8001010, 0x00000004 - REG 0xB8001004, 0x006ac73a - REG 0xB8001000, 0x92100000 - REG 0x80000f00, 0x12344321 - REG 0xB8001000, 0xa2100000 - REG 0x80000000, 0x12344321 - REG 0x80000000, 0x12344321 - REG 0xB8001000, 0xb2100000 - REG8 0x80000033, 0xda - REG8 0x81000000, 0xff - REG 0xB8001000, 0x82226080 - REG 0x80000000, 0xDEADBEEF - REG 0xB8001010, 0x0000000c - - mov pc, lr - -MPCTL_PARAM_532: - .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0)) -MPCTL_PARAM_532_27: - .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0)) -UPCTL_PARAM_240: - .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) -UPCTL_PARAM_240_27: - .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0)) diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c deleted file mode 100644 index ad89cb021db..00000000000 --- a/board/freescale/mx31ads/mx31ads.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (C) 2008, Guennadi Liakhovetski - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - return 0; -} - -int board_early_init_f(void) -{ - int i; - - /* CS0: Nor Flash */ - /* - * CS0L and CS0A values are from the RedBoot sources by Freescale - * and are also equal to those used by Sascha Hauer for the Phytec - * i.MX31 board. CS0U is just a slightly optimized hardware default: - * the only non-zero field "Wait State Control" is set to half the - * default value. - */ - static const struct mxc_weimcs cs0 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) - }; - - mxc_setup_weimcs(0, &cs0); - - /* setup pins for UART1 */ - mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); - mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); - mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); - mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); - - /* SPI2 */ - mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); - mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); - mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); - mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); - mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); - mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); - mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); - - /* start SPI2 clock */ - __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); - - /* PBC setup */ - /* Enable UART transceivers also reset the Ethernet/external UART */ - readw(CS4_BASE + 4); - - writew(0x8023, CS4_BASE + 4); - - /* RedBoot also has an empty loop with 100000 iterations here - - * clock doesn't run yet */ - for (i = 0; i < 100000; i++) - ; - - /* Clear the reset, toggle the LEDs */ - writew(0xDF, CS4_BASE + 6); - - /* clock still doesn't run */ - for (i = 0; i < 100000; i++) - ; - - /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */ - readb(CS4_BASE + 8); - readb(CS4_BASE + 7); - readb(CS4_BASE + 8); - readb(CS4_BASE + 7); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */ - - return 0; -} - -int checkboard(void) -{ - printf("Board: MX31ADS\n"); - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds deleted file mode 100644 index 71a63f188e7..00000000000 --- a/board/freescale/mx31ads/u-boot.lds +++ /dev/null @@ -1,110 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.__image_copy_start) - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - * (.vectors) - arch/arm/cpu/arm1136/start.o (.text*) - board/freescale/mx31ads/built-in.o (.text*) - arch/arm/lib/built-in.o (.text*) - net/built-in.o (.text*) - drivers/mtd/built-in.o (.text*) - - . = DEFINED(env_offset) ? env_offset : .; - env/embedded.o(.text*) - - *(.text*) - } - . = ALIGN(4); - .rodata : { *(.rodata*) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - .hash : { *(.hash*) } - - .end : - { - *(.__end) - } - - _image_binary_end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _image_binary_end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .gnu.hash : { *(.gnu.hash) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/configs/mx31ads_defconfig b/configs/mx31ads_defconfig deleted file mode 100644 index 9a4622577c1..00000000000 --- a/configs/mx31ads_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_MX31ADS=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_MXC_GPIO=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_MXC_SPI=y diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h deleted file mode 100644 index 0fe37c71da9..00000000000 --- a/include/configs/mx31ads.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (C) 2008, Guennadi Liakhovetski - * - * Configuration settings for the MX31ADS Freescale board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - - /* High Level Configuration Options */ -#define CONFIG_MX31 1 /* This is a mx31 */ - -#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -#define CONFIG_HARD_SPI 1 -#define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) - -/* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL -#define CONFIG_FSL_PMIC_BUS 1 -#define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 - -#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot_addr=0xa0000000\0" \ - "uboot=mx31ads/u-boot.bin\0" \ - "kernel=mx31ads/uImage\0" \ - "nfsroot=/opt/eldk/arm\0" \ - "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ - "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "bootcmd=run bootcmd_net\0" \ - "bootcmd_net=run bootargs_base bootargs_nfs; " \ - "tftpboot ${loadaddr} ${kernel}; bootm\0" \ - "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ - "protect off ${uboot_addr} 0xa003ffff; " \ - "erase ${uboot_addr} 0xa003ffff; " \ - "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ - "setenv filesize; saveenv\0" - -#define CONFIG_CS8900 -#define CONFIG_CS8900_BASE 0xb4020300 -#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ - -/* - * The MX31ADS board seems to have a hardware "peculiarity" confirmed under - * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A - * controller inverted. The controller is capable of detecting and correcting - * this, but it needs 4 network packets for that. Which means, at startup, you - * will not receive answers to the first 4 packest, unless there have been some - * broadcasts on the network, or your board is on a hub. Reducing the ARP - * timeout from default 5 seconds to 200ms we speed up the initial TFTP - * transfer, should the user wish one, significantly. - */ -#define CONFIG_ARP_TIMEOUT 200UL - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ - -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* - * JFFS2 partitions - */ -#define CONFIG_JFFS2_DEV "nor0" - -#endif /* __CONFIG_H */ -- cgit v1.3.1