From ff1da6fb5fe50ac15dd988e81a782a4599102424 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sat, 16 Mar 2013 18:58:03 +0000 Subject: tegra: spi: rename tegra SPI drivers Rename tegra SPI drivers to tegra20_flash and tegra20_slink in preparation for commonization and addition of tegra114_spi. Signed-off-by: Allen Martin Signed-off-by: Tom Warren Reviewed-by: Stephen Warren --- include/configs/cardhu.h | 2 +- include/configs/trimslice.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 55dc83da6a1..6a991752114 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -60,7 +60,7 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* SPI */ -#define CONFIG_TEGRA_SLINK +#define CONFIG_TEGRA20_SLINK #define CONFIG_TEGRA_SLINK_CTRLS 6 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_WINBOND diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 0644f7a5b8f..b92531477e7 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -46,7 +46,7 @@ #define CONFIG_BOARD_EARLY_INIT_F /* SPI */ -#define CONFIG_TEGRA_SPI +#define CONFIG_TEGRA20_SFLASH #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -- cgit v1.3.1 From 78f47b7353ebe1f243203dcc1ce0a2a374c08a40 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sat, 16 Mar 2013 18:58:07 +0000 Subject: spi: add common fdt SPI driver interface Add a common interface to fdt based SPI drivers. Each driver is represented by a table entry in fdt_spi_drivers[]. If there are multiple SPI drivers in the table, the first driver to return success from spi_init() will be registered as the SPI driver. Signed-off-by: Allen Martin Signed-off-by: Tom Warren Reviewed-by: Stephen Warren --- arch/arm/include/asm/arch-tegra20/tegra20_sflash.h | 11 ++ arch/arm/include/asm/arch-tegra20/tegra20_slink.h | 11 ++ board/nvidia/common/board.c | 2 +- drivers/spi/Makefile | 1 + drivers/spi/fdt_spi.c | 171 +++++++++++++++++++++ drivers/spi/tegra20_sflash.c | 41 ++--- drivers/spi/tegra20_slink.c | 29 ++-- include/configs/tegra-common-post.h | 4 + 8 files changed, 224 insertions(+), 46 deletions(-) create mode 100644 drivers/spi/fdt_spi.c (limited to 'include') diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h index 28775db2a90..e8cc68c6eaf 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h +++ b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h @@ -27,4 +27,15 @@ #include +int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs); +struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); +void tegra20_spi_free_slave(struct spi_slave *slave); +int tegra20_spi_init(int *node_list, int count); +int tegra20_spi_claim_bus(struct spi_slave *slave); +void tegra20_spi_cs_activate(struct spi_slave *slave); +void tegra20_spi_cs_deactivate(struct spi_slave *slave); +int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags); + #endif /* _TEGRA20_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h index fe8b5347f88..5aa74ddd6d2 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h +++ b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h @@ -27,4 +27,15 @@ #include +int tegra30_spi_init(int *node_list, int count); +int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs); +struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); +void tegra30_spi_free_slave(struct spi_slave *slave); +int tegra30_spi_claim_bus(struct spi_slave *slave); +void tegra30_spi_cs_activate(struct spi_slave *slave); +void tegra30_spi_cs_deactivate(struct spi_slave *slave); +int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags); + #endif /* _TEGRA30_SPI_H_ */ diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 87a418bc6a3..8d7a22765a1 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -132,7 +132,7 @@ int board_init(void) clock_init(); clock_verify(); -#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) +#ifdef CONFIG_FDT_SPI pin_mux_spi(); spi_init(); #endif diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 78e3d3d5683..3762d59dd01 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o +COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o diff --git a/drivers/spi/fdt_spi.c b/drivers/spi/fdt_spi.c new file mode 100644 index 00000000000..c6ae719d63b --- /dev/null +++ b/drivers/spi/fdt_spi.c @@ -0,0 +1,171 @@ +/* + * Common fdt based SPI driver front end + * + * Copyright (c) 2013 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct fdt_spi_driver { + int compat; + int max_ctrls; + int (*init)(int *node_list, int count); + int (*claim_bus)(struct spi_slave *slave); + int (*release_bus)(struct spi_slave *slave); + int (*cs_is_valid)(unsigned int bus, unsigned int cs); + struct spi_slave *(*setup_slave)(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); + void (*free_slave)(struct spi_slave *slave); + void (*cs_activate)(struct spi_slave *slave); + void (*cs_deactivate)(struct spi_slave *slave); + int (*xfer)(struct spi_slave *slave, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags); +}; + +static struct fdt_spi_driver fdt_spi_drivers[] = { +#ifdef CONFIG_TEGRA20_SFLASH + { + .compat = COMPAT_NVIDIA_TEGRA20_SFLASH, + .max_ctrls = 1, + .init = tegra20_spi_init, + .claim_bus = tegra20_spi_claim_bus, + .cs_is_valid = tegra20_spi_cs_is_valid, + .setup_slave = tegra20_spi_setup_slave, + .free_slave = tegra20_spi_free_slave, + .cs_activate = tegra20_spi_cs_activate, + .cs_deactivate = tegra20_spi_cs_deactivate, + .xfer = tegra20_spi_xfer, + }, +#endif +#ifdef CONFIG_TEGRA20_SLINK + { + .compat = COMPAT_NVIDIA_TEGRA20_SLINK, + .max_ctrls = CONFIG_TEGRA_SLINK_CTRLS, + .init = tegra30_spi_init, + .claim_bus = tegra30_spi_claim_bus, + .cs_is_valid = tegra30_spi_cs_is_valid, + .setup_slave = tegra30_spi_setup_slave, + .free_slave = tegra30_spi_free_slave, + .cs_activate = tegra30_spi_cs_activate, + .cs_deactivate = tegra30_spi_cs_deactivate, + .xfer = tegra30_spi_xfer, + }, +#endif +}; + +static struct fdt_spi_driver *driver; + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + if (!driver) + return 0; + else if (!driver->cs_is_valid) + return 1; + else + return driver->cs_is_valid(bus, cs); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + if (!driver || !driver->setup_slave) + return NULL; + + return driver->setup_slave(bus, cs, max_hz, mode); +} + +void spi_free_slave(struct spi_slave *slave) +{ + if (driver && driver->free_slave) + return driver->free_slave(slave); +} + +static int spi_init_driver(struct fdt_spi_driver *driver) +{ + int count; + int node_list[driver->max_ctrls]; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi", + driver->compat, + node_list, + driver->max_ctrls); + return driver->init(node_list, count); +} + +void spi_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(fdt_spi_drivers); i++) { + driver = &fdt_spi_drivers[i]; + if (!spi_init_driver(driver)) + break; + } + if (i == ARRAY_SIZE(fdt_spi_drivers)) + driver = NULL; +} + +int spi_claim_bus(struct spi_slave *slave) +{ + if (!driver) + return 1; + if (!driver->claim_bus) + return 0; + + return driver->claim_bus(slave); +} + +void spi_release_bus(struct spi_slave *slave) +{ + if (driver && driver->release_bus) + driver->release_bus(slave); +} + +void spi_cs_activate(struct spi_slave *slave) +{ + if (driver && driver->cs_activate) + driver->cs_activate(slave); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + if (driver && driver->cs_deactivate) + driver->cs_deactivate(slave); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags) +{ + if (!driver || !driver->xfer) + return -1; + + return driver->xfer(slave, bitlen, data_out, data_in, flags); +} diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c index bb1e57d5e80..a4e6c9aa3f2 100644 --- a/drivers/spi/tegra20_sflash.c +++ b/drivers/spi/tegra20_sflash.c @@ -101,7 +101,7 @@ static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) return container_of(slave, struct tegra_spi_slave, slave); } -int spi_cs_is_valid(unsigned int bus, unsigned int cs) +int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs) { /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */ if (bus != 0 || cs != 0) @@ -110,8 +110,8 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) return 1; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) +struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { struct tegra_spi_slave *spi; @@ -151,25 +151,20 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return &spi->slave; } -void spi_free_slave(struct spi_slave *slave) +void tegra20_spi_free_slave(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); free(spi); } -void spi_init(void) +int tegra20_spi_init(int *node_list, int count) { struct tegra_spi_ctrl *ctrl; int i; int node = 0; - int count; - int node_list[1]; + int found = 0; - count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi", - COMPAT_NVIDIA_TEGRA20_SFLASH, - node_list, - 1); for (i = 0; i < count; i++) { ctrl = &spi_ctrls[i]; node = node_list[i]; @@ -193,13 +188,15 @@ void spi_init(void) continue; } ctrl->valid = 1; + found = 1; debug("%s: found controller at %p, freq = %u, periph_id = %d\n", __func__, ctrl->regs, ctrl->freq, ctrl->periph_id); } + return !found; } -int spi_claim_bus(struct spi_slave *slave) +int tegra20_spi_claim_bus(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); struct spi_regs *regs = spi->ctrl->regs; @@ -213,7 +210,7 @@ int spi_claim_bus(struct spi_slave *slave) reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \ SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF; writel(reg, ®s->status); - debug("spi_init: STATUS = %08x\n", readl(®s->status)); + debug("%s: STATUS = %08x\n", __func__, readl(®s->status)); /* * Use sw-controlled CS, so we can clock in data after ReadID, etc. @@ -223,7 +220,7 @@ int spi_claim_bus(struct spi_slave *slave) reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT; clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK | SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg); - debug("spi_init: COMMAND = %08x\n", readl(®s->command)); + debug("%s: COMMAND = %08x\n", __func__, readl(®s->command)); /* * SPI pins on Tegra20 are muxed - change pinmux later due to UART @@ -236,17 +233,7 @@ int spi_claim_bus(struct spi_slave *slave) return 0; } -void spi_release_bus(struct spi_slave *slave) -{ - /* - * We can't release UART_DISABLE and set pinmux to UART4 here since - * some code (e,g, spi_flash_probe) uses printf() while the SPI - * bus is held. That is arguably bad, but it has the advantage of - * already being in the source tree. - */ -} - -void spi_cs_activate(struct spi_slave *slave) +void tegra20_spi_cs_activate(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); struct spi_regs *regs = spi->ctrl->regs; @@ -255,7 +242,7 @@ void spi_cs_activate(struct spi_slave *slave) setbits_le32(®s->command, SPI_CMD_CS_VAL); } -void spi_cs_deactivate(struct spi_slave *slave) +void tegra20_spi_cs_deactivate(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); struct spi_regs *regs = spi->ctrl->regs; @@ -264,7 +251,7 @@ void spi_cs_deactivate(struct spi_slave *slave) clrbits_le32(®s->command, SPI_CMD_CS_VAL); } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, +int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, void *data_in, unsigned long flags) { struct tegra_spi_slave *spi = to_tegra_spi(slave); diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index f3b09644889..2ef2eb8495e 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -107,7 +107,7 @@ static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) return container_of(slave, struct tegra_spi_slave, slave); } -int spi_cs_is_valid(unsigned int bus, unsigned int cs) +int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs) { if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid) return 0; @@ -115,7 +115,7 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) return 1; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, +struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct tegra_spi_slave *spi; @@ -159,25 +159,20 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return &spi->slave; } -void spi_free_slave(struct spi_slave *slave) +void tegra30_spi_free_slave(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); free(spi); } -void spi_init(void) +int tegra30_spi_init(int *node_list, int count) { struct tegra_spi_ctrl *ctrl; int i; int node = 0; - int count; - int node_list[CONFIG_TEGRA_SLINK_CTRLS]; + int found = 0; - count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi", - COMPAT_NVIDIA_TEGRA20_SLINK, - node_list, - CONFIG_TEGRA_SLINK_CTRLS); for (i = 0; i < count; i++) { ctrl = &spi_ctrls[i]; node = node_list[i]; @@ -201,13 +196,15 @@ void spi_init(void) continue; } ctrl->valid = 1; + found = 1; debug("%s: found controller at %p, freq = %u, periph_id = %d\n", __func__, ctrl->regs, ctrl->freq, ctrl->periph_id); } + return !found; } -int spi_claim_bus(struct spi_slave *slave) +int tegra30_spi_claim_bus(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); struct spi_regs *regs = spi->ctrl->regs; @@ -232,11 +229,7 @@ int spi_claim_bus(struct spi_slave *slave) return 0; } -void spi_release_bus(struct spi_slave *slave) -{ -} - -void spi_cs_activate(struct spi_slave *slave) +void tegra30_spi_cs_activate(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); struct spi_regs *regs = spi->ctrl->regs; @@ -245,7 +238,7 @@ void spi_cs_activate(struct spi_slave *slave) setbits_le32(®s->command, SLINK_CMD_CS_VAL); } -void spi_cs_deactivate(struct spi_slave *slave) +void tegra30_spi_cs_deactivate(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); struct spi_regs *regs = spi->ctrl->regs; @@ -254,7 +247,7 @@ void spi_cs_deactivate(struct spi_slave *slave) clrbits_le32(®s->command, SLINK_CMD_CS_VAL); } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, +int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, void *data_in, unsigned long flags) { struct tegra_spi_slave *spi = to_tegra_spi(slave); diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index f2a70b1a35c..d967a75b3a8 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -150,6 +150,10 @@ MEM_LAYOUT_ENV_SETTINGS \ BOOTCMDS_COMMON +#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) +#define CONFIG_FDT_SPI +#endif + /* overrides for SPL build here */ #ifdef CONFIG_SPL_BUILD -- cgit v1.3.1 From c3bb3c8bb3de2078334f4b95e04d37eed78781c2 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sat, 16 Mar 2013 18:58:09 +0000 Subject: tegra114: fdt: add compatible string for tegra114 SPI ctrl Add "nvidia,tegra114-spi" to represent t114 SPI controller hardware. Signed-off-by: Allen Martin Signed-off-by: Tom Warren Reviewed-by: Stephen Warren --- include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 21894835d1b..19c970743b1 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -75,6 +75,7 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */ COMPAT_NVIDIA_TEGRA20_SLINK, /* Tegra 2 SPI SLINK controller */ + COMPAT_NVIDIA_TEGRA114_SPI, /* Tegra 114 SPI controller */ COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */ COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */ COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 43f29f5c6b4..c56f7d4845d 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -50,6 +50,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"), COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"), COMPAT(NVIDIA_TEGRA20_SLINK, "nvidia,tegra20-slink"), + COMPAT(NVIDIA_TEGRA114_SPI, "nvidia,tegra114-spi"), COMPAT(SMSC_LAN9215, "smsc,lan9215"), COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"), COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"), -- cgit v1.3.1 From 77c42e80b936cf44334a59a7890c775712f5b707 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sat, 16 Mar 2013 18:58:13 +0000 Subject: tegra114: add SPI driver Add driver for tegra114 SPI controller. This controller is not compatible with either the tegra20 or tegra30 controllers, so it requires a new driver. Signed-off-by: Allen Martin Signed-off-by: Tom Warren Reviewed-by: Stephen Warren --- arch/arm/include/asm/arch-tegra114/tegra114_spi.h | 41 +++ drivers/spi/Makefile | 1 + drivers/spi/fdt_spi.c | 15 + drivers/spi/tegra114_spi.c | 405 ++++++++++++++++++++++ include/configs/tegra-common-post.h | 2 +- 5 files changed, 463 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-tegra114/tegra114_spi.h create mode 100644 drivers/spi/tegra114_spi.c (limited to 'include') diff --git a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h new file mode 100644 index 00000000000..48197bc27fc --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h @@ -0,0 +1,41 @@ +/* + * NVIDIA Tegra SPI controller + * + * Copyright 2010-2013 NVIDIA Corporation + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA114_SPI_H_ +#define _TEGRA114_SPI_H_ + +#include + +int tegra114_spi_init(int *node_list, int count); +int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs); +struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); +void tegra114_spi_free_slave(struct spi_slave *slave); +int tegra114_spi_claim_bus(struct spi_slave *slave); +void tegra114_spi_cs_activate(struct spi_slave *slave); +void tegra114_spi_cs_deactivate(struct spi_slave *slave); +int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags); + +#endif /* _TEGRA114_SPI_H_ */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3762d59dd01..46e8fa3bef7 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -49,6 +49,7 @@ COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o +COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o COBJS := $(COBJS-y) diff --git a/drivers/spi/fdt_spi.c b/drivers/spi/fdt_spi.c index c6ae719d63b..58f139a54ea 100644 --- a/drivers/spi/fdt_spi.c +++ b/drivers/spi/fdt_spi.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -79,6 +80,20 @@ static struct fdt_spi_driver fdt_spi_drivers[] = { .xfer = tegra30_spi_xfer, }, #endif +#ifdef CONFIG_TEGRA114_SPI + { + .compat = COMPAT_NVIDIA_TEGRA114_SPI, + .max_ctrls = CONFIG_TEGRA114_SPI_CTRLS, + .init = tegra114_spi_init, + .claim_bus = tegra114_spi_claim_bus, + .cs_is_valid = tegra114_spi_cs_is_valid, + .setup_slave = tegra114_spi_setup_slave, + .free_slave = tegra114_spi_free_slave, + .cs_activate = tegra114_spi_cs_activate, + .cs_deactivate = tegra114_spi_cs_deactivate, + .xfer = tegra114_spi_xfer, + }, +#endif }; static struct fdt_spi_driver *driver; diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c new file mode 100644 index 00000000000..b11a0a1ff7c --- /dev/null +++ b/drivers/spi/tegra114_spi.c @@ -0,0 +1,405 @@ +/* + * NVIDIA Tegra SPI controller (T114 and later) + * + * Copyright (c) 2010-2013 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* COMMAND1 */ +#define SPI_CMD1_GO (1 << 31) +#define SPI_CMD1_M_S (1 << 30) +#define SPI_CMD1_MODE_MASK 0x3 +#define SPI_CMD1_MODE_SHIFT 28 +#define SPI_CMD1_CS_SEL_MASK 0x3 +#define SPI_CMD1_CS_SEL_SHIFT 26 +#define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25) +#define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24) +#define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23) +#define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22) +#define SPI_CMD1_CS_SW_HW (1 << 21) +#define SPI_CMD1_CS_SW_VAL (1 << 20) +#define SPI_CMD1_IDLE_SDA_MASK 0x3 +#define SPI_CMD1_IDLE_SDA_SHIFT 18 +#define SPI_CMD1_BIDIR (1 << 17) +#define SPI_CMD1_LSBI_FE (1 << 16) +#define SPI_CMD1_LSBY_FE (1 << 15) +#define SPI_CMD1_BOTH_EN_BIT (1 << 14) +#define SPI_CMD1_BOTH_EN_BYTE (1 << 13) +#define SPI_CMD1_RX_EN (1 << 12) +#define SPI_CMD1_TX_EN (1 << 11) +#define SPI_CMD1_PACKED (1 << 5) +#define SPI_CMD1_BIT_LEN_MASK 0x1F +#define SPI_CMD1_BIT_LEN_SHIFT 0 + +/* COMMAND2 */ +#define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6) +#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) +#define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0) +#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) + +/* TRANSFER STATUS */ +#define SPI_XFER_STS_RDY (1 << 30) + +/* FIFO STATUS */ +#define SPI_FIFO_STS_CS_INACTIVE (1 << 31) +#define SPI_FIFO_STS_FRAME_END (1 << 30) +#define SPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15) +#define SPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14) +#define SPI_FIFO_STS_ERR (1 << 8) +#define SPI_FIFO_STS_TX_FIFO_OVF (1 << 7) +#define SPI_FIFO_STS_TX_FIFO_UNR (1 << 6) +#define SPI_FIFO_STS_RX_FIFO_OVF (1 << 5) +#define SPI_FIFO_STS_RX_FIFO_UNR (1 << 4) +#define SPI_FIFO_STS_TX_FIFO_FULL (1 << 3) +#define SPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2) +#define SPI_FIFO_STS_RX_FIFO_FULL (1 << 1) +#define SPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0) + +#define SPI_TIMEOUT 1000 +#define TEGRA_SPI_MAX_FREQ 52000000 + +struct spi_regs { + u32 command1; /* 000:SPI_COMMAND1 register */ + u32 command2; /* 004:SPI_COMMAND2 register */ + u32 timing1; /* 008:SPI_CS_TIM1 register */ + u32 timing2; /* 00c:SPI_CS_TIM2 register */ + u32 xfer_status;/* 010:SPI_TRANS_STATUS register */ + u32 fifo_status;/* 014:SPI_FIFO_STATUS register */ + u32 tx_data; /* 018:SPI_TX_DATA register */ + u32 rx_data; /* 01c:SPI_RX_DATA register */ + u32 dma_ctl; /* 020:SPI_DMA_CTL register */ + u32 dma_blk; /* 024:SPI_DMA_BLK register */ + u32 rsvd[56]; /* 028-107 reserved */ + u32 tx_fifo; /* 108:SPI_FIFO1 register */ + u32 rsvd2[31]; /* 10c-187 reserved */ + u32 rx_fifo; /* 188:SPI_FIFO2 register */ + u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */ +}; + +struct tegra_spi_ctrl { + struct spi_regs *regs; + unsigned int freq; + unsigned int mode; + int periph_id; + int valid; +}; + +struct tegra_spi_slave { + struct spi_slave slave; + struct tegra_spi_ctrl *ctrl; +}; + +static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA114_SPI_CTRLS]; + +static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) +{ + return container_of(slave, struct tegra_spi_slave, slave); +} + +int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + if (bus >= CONFIG_TEGRA114_SPI_CTRLS || cs > 3 || !spi_ctrls[bus].valid) + return 0; + else + return 1; +} + +struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct tegra_spi_slave *spi; + + debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__, + bus, cs, max_hz, mode); + + if (!spi_cs_is_valid(bus, cs)) { + printf("SPI error: unsupported bus %d / chip select %d\n", + bus, cs); + return NULL; + } + + if (max_hz > TEGRA_SPI_MAX_FREQ) { + printf("SPI error: unsupported frequency %d Hz. Max frequency" + " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ); + return NULL; + } + + spi = malloc(sizeof(struct tegra_spi_slave)); + if (!spi) { + printf("SPI error: malloc of SPI structure failed\n"); + return NULL; + } + spi->slave.bus = bus; + spi->slave.cs = cs; + spi->ctrl = &spi_ctrls[bus]; + if (!spi->ctrl) { + printf("SPI error: could not find controller for bus %d\n", + bus); + return NULL; + } + + if (max_hz < spi->ctrl->freq) { + debug("%s: limiting frequency from %u to %u\n", __func__, + spi->ctrl->freq, max_hz); + spi->ctrl->freq = max_hz; + } + spi->ctrl->mode = mode; + + return &spi->slave; +} + +void tegra114_spi_free_slave(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + + free(spi); +} + +int tegra114_spi_init(int *node_list, int count) +{ + struct tegra_spi_ctrl *ctrl; + int i; + int node = 0; + int found = 0; + + for (i = 0; i < count; i++) { + ctrl = &spi_ctrls[i]; + node = node_list[i]; + + ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob, + node, "reg"); + if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) { + debug("%s: no spi register found\n", __func__); + continue; + } + ctrl->freq = fdtdec_get_int(gd->fdt_blob, node, + "spi-max-frequency", 0); + if (!ctrl->freq) { + debug("%s: no spi max frequency found\n", __func__); + continue; + } + + ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node); + if (ctrl->periph_id == PERIPH_ID_NONE) { + debug("%s: could not decode periph id\n", __func__); + continue; + } + ctrl->valid = 1; + found = 1; + + debug("%s: found controller at %p, freq = %u, periph_id = %d\n", + __func__, ctrl->regs, ctrl->freq, ctrl->periph_id); + } + + return !found; +} + +int tegra114_spi_claim_bus(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + struct spi_regs *regs = spi->ctrl->regs; + + /* Change SPI clock to correct frequency, PLLP_OUT0 source */ + clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH, + spi->ctrl->freq); + + /* Clear stale status here */ + setbits_le32(®s->fifo_status, + SPI_FIFO_STS_ERR | + SPI_FIFO_STS_TX_FIFO_OVF | + SPI_FIFO_STS_TX_FIFO_UNR | + SPI_FIFO_STS_RX_FIFO_OVF | + SPI_FIFO_STS_RX_FIFO_UNR | + SPI_FIFO_STS_TX_FIFO_FULL | + SPI_FIFO_STS_TX_FIFO_EMPTY | + SPI_FIFO_STS_RX_FIFO_FULL | + SPI_FIFO_STS_RX_FIFO_EMPTY); + debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); + + /* Set master mode and sw controlled CS */ + setbits_le32(®s->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW | + (spi->ctrl->mode << SPI_CMD1_MODE_SHIFT)); + debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); + + return 0; +} + +void tegra114_spi_cs_activate(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + struct spi_regs *regs = spi->ctrl->regs; + + clrbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL); +} + +void tegra114_spi_cs_deactivate(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + struct spi_regs *regs = spi->ctrl->regs; + + setbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL); +} + +int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + struct spi_regs *regs = spi->ctrl->regs; + u32 reg, tmpdout, tmpdin = 0; + const u8 *dout = data_out; + u8 *din = data_in; + int num_bytes; + int ret; + + debug("%s: slave %u:%u dout %p din %p bitlen %u\n", + __func__, slave->bus, slave->cs, dout, din, bitlen); + if (bitlen % 8) + return -1; + num_bytes = bitlen / 8; + + ret = 0; + + /* clear all error status bits */ + reg = readl(®s->fifo_status); + writel(reg, ®s->fifo_status); + + /* clear ready bit */ + setbits_le32(®s->xfer_status, SPI_XFER_STS_RDY); + + clrsetbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL, + SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE | + (slave->cs << SPI_CMD1_CS_SEL_SHIFT)); + + /* set xfer size to 1 block (32 bits) */ + writel(0, ®s->dma_blk); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + /* handle data in 32-bit chunks */ + while (num_bytes > 0) { + int bytes; + int is_read = 0; + int tm, i; + + tmpdout = 0; + bytes = (num_bytes > 4) ? 4 : num_bytes; + + if (dout != NULL) { + for (i = 0; i < bytes; ++i) + tmpdout = (tmpdout << 8) | dout[i]; + dout += bytes; + } + + num_bytes -= bytes; + + clrsetbits_le32(®s->command1, + SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT, + (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT); + writel(tmpdout, ®s->tx_fifo); + setbits_le32(®s->command1, SPI_CMD1_GO); + + /* + * Wait for SPI transmit FIFO to empty, or to time out. + * The RX FIFO status will be read and cleared last + */ + for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { + u32 fifo_status, xfer_status; + + fifo_status = readl(®s->fifo_status); + + /* We can exit when we've had both RX and TX activity */ + if (is_read && + (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)) + break; + + xfer_status = readl(®s->xfer_status); + if (!(xfer_status & SPI_XFER_STS_RDY)) + continue; + + if (fifo_status & SPI_FIFO_STS_ERR) { + debug("%s: got a fifo error: ", __func__); + if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF) + debug("tx FIFO overflow "); + if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR) + debug("tx FIFO underrun "); + if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF) + debug("rx FIFO overflow "); + if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR) + debug("rx FIFO underrun "); + if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL) + debug("tx FIFO full "); + if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY) + debug("tx FIFO empty "); + if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL) + debug("rx FIFO full "); + if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY) + debug("rx FIFO empty "); + debug("\n"); + break; + } + + if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) { + tmpdin = readl(®s->rx_fifo); + is_read = 1; + + /* swap bytes read in */ + if (din != NULL) { + for (i = bytes - 1; i >= 0; --i) { + din[i] = tmpdin & 0xff; + tmpdin >>= 8; + } + din += bytes; + } + } + } + + if (tm >= SPI_TIMEOUT) + ret = tm; + + /* clear ACK RDY, etc. bits */ + writel(readl(®s->fifo_status), ®s->fifo_status); + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", + __func__, tmpdin, readl(®s->fifo_status)); + + if (ret) { + printf("%s: timeout during SPI transfer, tm %d\n", + __func__, ret); + return -1; + } + + return 0; +} diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index d967a75b3a8..bf186995ed4 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -150,7 +150,7 @@ MEM_LAYOUT_ENV_SETTINGS \ BOOTCMDS_COMMON -#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) +#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) #define CONFIG_FDT_SPI #endif -- cgit v1.3.1 From ec37b2b423df552425d59a63763ce0c4773e57f8 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sat, 16 Mar 2013 18:58:14 +0000 Subject: tegra114: dalmore: config: enable SPI Turn on SPI in dalmore config file Signed-off-by: Allen Martin Signed-off-by: Tom Warren Reviewed-by: Stephen Warren --- include/configs/dalmore.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index b1a6e34ebad..c7deea5350f 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -54,6 +54,17 @@ #define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */ +/* SPI */ +#define CONFIG_TEGRA114_SPI +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + #include "tegra-common-post.h" #endif /* __CONFIG_H */ -- cgit v1.3.1 From f789be6086f3e6302fe4b163fa9b7bd6b358c4ce Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Mon, 18 Mar 2013 14:52:26 -0700 Subject: Tegra114: MMC: Enable DT MMC driver support for Tegra114 Dalmore boards Tested on my Dalmore E1611 board, eMMC and SD-Card work fine, can load a kernel off of an SD card OK, card detect works, and the env is now stored in eMMC (end of the 2nd 'boot' sector, same as Tegra20/30). Signed-off-by: Tom Warren Reviewed-by: Stephen Warren --- include/configs/dalmore.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index c7deea5350f..7b68f7ca987 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -50,7 +50,17 @@ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_CMD_I2C -#define CONFIG_ENV_IS_NOWHERE +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET ((4096 * 1024) - CONFIG_ENV_SIZE) #define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */ -- cgit v1.3.1