From ed2f65f0105dacb98e5c4d2b435dd009de06c2d1 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 23 Apr 2019 23:44:57 +0300 Subject: ARM: renesas: Add R8A77980 V3HSK board and CPLD code Add board code for the R8A77980 V3HSK board. Add CPLD sysreset driver to the R-Car V3H SK board. Extracted from a larger patch by Valentine Barshak. Reviewed-by: Marek Vasut Signed-off-by: Valentine Barshak Signed-off-by: Hai Pham Signed-off-by: Tam Nguyen Signed-off-by: Marek Vasut [Marek: Sync configs and board code with V3H Condor, squash CPLD driver in] --- include/configs/v3hsk.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 include/configs/v3hsk.h (limited to 'include') diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h new file mode 100644 index 00000000000..58c2e88c0b7 --- /dev/null +++ b/include/configs/v3hsk.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/v3hsk.h + * This file is V3HSK board configuration. + * + * Copyright (C) 2019 Renesas Electronics Corporation + * Copyright (C) 2019 Cogent Embedded, Inc. + */ + +#ifndef __V3HSK_H +#define __V3HSK_H + +#include "rcar-gen3-common.h" + +/* Environment compatibility */ + +/* SH Ether */ +#define CFG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_PHY_ADDR 0x0 +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID +#define CFG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_ALIGNE_SIZE 64 + +/* Board Clock */ +/* XTAL_CLK : 33.33MHz */ + +#endif /* __V3HSK_H */ -- cgit v1.2.3