From 5f2e1425270c1461e4d633d3ff9042d29f7531d1 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Mon, 27 Feb 2012 21:19:02 +0000 Subject: ARM: dreamplug: Enable FDT support I have tested booting both FDT and non-FDT based Linux kernels (based on http://marc.info/?l=linux-arm-kernel&m=133002679716986 and http://marc.info/?l=linux-arm-kernel&m=132328894303581 respectively). Signed-off-by: Ian Campbell Cc: Jason Cc: Prafulla Wadaskar Acked-by: Jason Cooper --- include/configs/dreamplug.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 0f2f9a2743f..76f9eeaed80 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -148,4 +148,6 @@ */ #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_OF_LIBFDT + #endif /* _CONFIG_DREAMPLUG_H */ -- cgit v1.3.1 From 463ec1caa3cb9401da8f788fc7d4eee08a5f0edc Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 19 Apr 2012 04:33:10 +0000 Subject: devkit3250: add Timll DevKit3250 board initial support This change adds a basic support for Embest/Timll DevKit3250 board, NOR and UART are the only supported peripherals for a moment. The board doesn't require low-level init, because the initial SDRAM and GPIO configuration is performed during kickstart bootloader execution. Signed-off-by: Vladimir Zapolskiy Cc: Albert ARIBAUD Acked-by: Marek Vasut --- MAINTAINERS | 4 ++ board/timll/devkit3250/Makefile | 44 ++++++++++++++ board/timll/devkit3250/devkit3250.c | 65 ++++++++++++++++++++ boards.cfg | 1 + include/configs/devkit3250.h | 117 ++++++++++++++++++++++++++++++++++++ 5 files changed, 231 insertions(+) create mode 100644 board/timll/devkit3250/Makefile create mode 100644 board/timll/devkit3250/devkit3250.c create mode 100644 include/configs/devkit3250.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index e2441d8d312..4ede19befc6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -932,6 +932,10 @@ Sughosh Ganu hawkboard ARM926EJS (OMAP-L138) +Vladimir Zapolskiy + + devkit3250 lpc32xx + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/board/timll/devkit3250/Makefile b/board/timll/devkit3250/Makefile new file mode 100644 index 00000000000..ea7827c80db --- /dev/null +++ b/board/timll/devkit3250/Makefile @@ -0,0 +1,44 @@ +# +# Copyright (C) 2011 by Vladimir Zapolskiy +# Copyright (C) 2008, Guennadi Liakhovetski +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301, USA. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := devkit3250.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c new file mode 100644 index 00000000000..6b0ec80fcd0 --- /dev/null +++ b/board/timll/devkit3250/devkit3250.c @@ -0,0 +1,65 @@ +/* + * Embest/Timll DevKit3250 board support + * + * Copyright (C) 2011 Vladimir Zapolskiy + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; + +int board_early_init_f(void) +{ + lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_SYS_FLASH_CFI + /* Use 16-bit memory interface for NOR Flash */ + emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT; + + /* Change the NOR timings to optimum value to get maximum bandwidth */ + emc->stat[0].waitwen = EMC_STAT_WAITWEN(1); + emc->stat[0].waitoen = EMC_STAT_WAITOEN(1); + emc->stat[0].waitrd = EMC_STAT_WAITRD(12); + emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12); + emc->stat[0].waitwr = EMC_STAT_WAITWR(5); + emc->stat[0].waitturn = EMC_STAT_WAITTURN(2); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} diff --git a/boards.cfg b/boards.cfg index 5f328b586d6..9460c38572c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -154,6 +154,7 @@ openrd_ultimate arm arm926ejs openrd Marvell rd6281a arm arm926ejs - Marvell kirkwood sheevaplug arm arm926ejs - Marvell kirkwood dockstar arm arm926ejs - Seagate kirkwood +devkit3250 arm arm926ejs devkit3250 timll lpc32xx jadecpu arm arm926ejs jadecpu syteco mb86r0x mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg tx25 arm arm926ejs tx25 karo mx25 diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h new file mode 100644 index 00000000000..9f15ffb0fd4 --- /dev/null +++ b/include/configs/devkit3250.h @@ -0,0 +1,117 @@ +/* + * Embest/Timll DevKit3250 board configuration file + * + * Copyright (C) 2011 Vladimir Zapolskiy + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __CONFIG_DEVKIT3250_H__ +#define __CONFIG_DEVKIT3250_H__ + +/* SoC and board defines */ +#include +#include + +/* + * Define DevKit3250 machine type by hand until it lands in mach-types + */ +#define MACH_TYPE_DEVKIT3250 3697 +#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250 + +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +/* + * Memory configurations + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_STACKSIZE SZ_32K +#define CONFIG_SYS_MALLOC_LEN SZ_1M +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CONFIG_SYS_SDRAM_SIZE SZ_64M +#define CONFIG_SYS_TEXT_BASE 0x83FA0000 +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ + - GENERATED_GBL_DATA_SIZE) + +/* + * Serial Driver + */ +#define CONFIG_SYS_LPC32XX_UART 2 /* UART2 */ +#define CONFIG_BAUDRATE 115200 + +/* + * NOR Flash + */ +#define CONFIG_CMD_FLASH +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 71 +#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE +#define CONFIG_SYS_FLASH_SIZE SZ_4M +#define CONFIG_SYS_FLASH_CFI + +/* + * U-Boot General Configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE SZ_128K + +/* + * U-Boot Commands + */ +#include +#define CONFIG_CMD_CACHE + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyS2,115200n8" +#define CONFIG_LOADADDR 0x80008000 + +/* + * Include SoC specific configuration + */ +#include + +#endif /* __CONFIG_DEVKIT3250_H__*/ -- cgit v1.3.1 From e5841e12114fbc55dcc2b409ba5cd09081f33483 Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Tue, 17 Apr 2012 09:22:17 +0000 Subject: kirkwood: add NAS62x0 board support Add support for new boards RaidSonic ICY BOX NAS6210 and NAS6220. NAS6210 has 1 SATA and 1 eSATA port while NAS6220 has 2 SATA ports. More information about the boards can be found here: http://www.raidsonic.de/en/products/nas-systems.php?we_objectID=7036 http://www.raidsonic.de/en/products/nas-systems.php?we_objectID=7515 Signed-off-by: Luka Perkov Signed-off-by: Gerald Kerma Signed-off-by: Simon Baatz --- MAINTAINERS | 4 + board/raidsonic/ib62x0/Makefile | 43 +++++++++ board/raidsonic/ib62x0/ib62x0.c | 79 +++++++++++++++++ board/raidsonic/ib62x0/ib62x0.h | 40 +++++++++ board/raidsonic/ib62x0/kwbimage.cfg | 169 ++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/ib62x0.h | 152 ++++++++++++++++++++++++++++++++ 7 files changed, 488 insertions(+) create mode 100644 board/raidsonic/ib62x0/Makefile create mode 100644 board/raidsonic/ib62x0/ib62x0.c create mode 100644 board/raidsonic/ib62x0/ib62x0.h create mode 100644 board/raidsonic/ib62x0/kwbimage.cfg create mode 100644 include/configs/ib62x0.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 4ede19befc6..71a2a8407d3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -777,6 +777,10 @@ Linus Walleij integratorap various integratorcp various +Luka Perkov + + ib62x0 ARM926EJS + Dave Peverley omap730p2 ARM926EJS diff --git a/board/raidsonic/ib62x0/Makefile b/board/raidsonic/ib62x0/Makefile new file mode 100644 index 00000000000..d450f8d0aba --- /dev/null +++ b/board/raidsonic/ib62x0/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := ib62x0.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c new file mode 100644 index 00000000000..65f2c2ea6a0 --- /dev/null +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2011-2012 + * Gerald Kerma + * Luka Perkov + * Simon Baatz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include "ib62x0.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(IB62x0_OE_VAL_LOW, + IB62x0_OE_VAL_HIGH, + IB62x0_OE_LOW, IB62x0_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP22_GPIO, /* Power LED red */ + MPP24_GPIO, /* Power off device */ + MPP25_GPIO, /* Power LED green */ + MPP27_GPIO, /* USB transfer LED */ + MPP28_GPIO, /* Reset button */ + MPP29_GPIO, /* USB Copy button */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} diff --git a/board/raidsonic/ib62x0/ib62x0.h b/board/raidsonic/ib62x0/ib62x0.h new file mode 100644 index 00000000000..0c30690697f --- /dev/null +++ b/board/raidsonic/ib62x0/ib62x0.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2011-2012 + * Gerald Kerma + * Simon Baatz + * Luka Perkov + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __IB62x0_H +#define __IB62x0_H + +#define IB62x0_OE_LOW (~(1 << 22 | 1 << 24 | 1 << 25 | 1 << 27)) +#define IB62x0_OE_HIGH (~(0)) +#define IB62x0_OE_VAL_LOW 0 +#define IB62x0_OE_VAL_HIGH 0 + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __IB62x0_H */ diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg new file mode 100644 index 00000000000..bd594ebd5d7 --- /dev/null +++ b/board/raidsonic/ib62x0/kwbimage.cfg @@ -0,0 +1,169 @@ +# +# Copyright (C) 2011-2012 +# Gerald Kerma +# Simon Baatz +# Luka Perkov +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand # change from nand to uart if building UART image +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xffd100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xffd01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30, (3120 DDR2 clks refresh rate) +# bit23-14: 0x0, +# bit24: 0x1, enable exit self refresh mode on DDR access +# bit25: 0x1, required +# bit29-26: 0x0, +# bit31-30: 0x1, + +DATA 0xffd01404 0x37543000 # DDR Controller Control Low +# bit4: 0x0, addr/cmd in smame cycle +# bit5: 0x0, clk is driven during self refresh, we don't care for APX +# bit6: 0x0, use recommended falling edge of clk for addr/cmd +# bit14: 0x0, input buffer always powered up +# bit18: 0x1, cpu lock transaction enabled +# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 0x3, required +# bit31: 0x0, no additional STARTBURST delay + +DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11-8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xffd0140c 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: 0x0, required + +DATA 0xffd01410 0x0000000c # DDR Address Control +# bit1-0: 00, Cs0width (x8) +# bit3-2: 11, Cs0size (1Gb) +# bit5-4: 00, Cs1width (x8) +# bit7-6: 11, Cs1size (1Gb) +# bit9-8: 00, Cs2width (nonexistent +# bit11-10: 00, Cs2size (nonexistent +# bit13-12: 00, Cs3width (nonexistent +# bit15-14: 00, Cs3size (nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0x0, required + +DATA 0xffd01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0x0, required + +DATA 0xffd01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0x0, required + +DATA 0xffd0141c 0x00000c52 # DDR Mode +# bit2-0: 0x2, BurstLen=2 required +# bit3: 0x0, BurstType=0 required +# bit6-4: 0x4, CL=5 +# bit7: 0x0, TestMode=0 normal +# bit8: 0x0, DLL reset=0 normal +# bit11-9: 0x6, auto-precharge write recovery ???????????? +# bit12: 0x0, PD must be zero +# bit31-13: 0x0, required + +DATA 0xffd01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 1, DDR ODT control lsd (disabled) +# bit5-3: 0x0, required +# bit6: 0, DDR ODT control msb, (disabled) +# bit9-7: 0x0, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0x0, required + +DATA 0xffd01424 0x0000f17f # DDR Controller Control High +# bit2-0: 0x7, required +# bit3: 0x1, MBUS Burst Chop disabled +# bit6-4: 0x7, required +# bit7: 0x0, +# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9: 0x0, no half clock cycle addition to dataout +# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh +# bit15-12: 0xf, required +# bit31-16: 0, required + +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xffd01504 0x0ffffff1 # CS[0]n Size +# bit0: 0x1, Window enabled +# bit1: 0x0, Write Protect disabled +# bit3-2: 0x0, CS0 hit selected +# bit23-4: 0xfffff, required +# bit31-24: 0x0f, Size (i.e. 256MB) + +DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled + +DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled + +DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) +# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above +# bit3-2: 0x1, ODT1 active NEVER! +# bit31-4: 0x0, required + +DATA 0xffd0149c 0x0000e803 # CPU ODT Control +DATA 0xffd01480 0x00000001 # DDR Initialization Control +# bit0: 0x1, enable DDR init upon this register write + +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index 9460c38572c..8f01c602d57 100644 --- a/boards.cfg +++ b/boards.cfg @@ -153,6 +153,7 @@ openrd_client arm arm926ejs openrd Marvell openrd_ultimate arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_ULTIMATE rd6281a arm arm926ejs - Marvell kirkwood sheevaplug arm arm926ejs - Marvell kirkwood +ib62x0 arm arm926ejs ib62x0 raidsonic kirkwood dockstar arm arm926ejs - Seagate kirkwood devkit3250 arm arm926ejs devkit3250 timll lpc32xx jadecpu arm arm926ejs jadecpu syteco mb86r0x diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h new file mode 100644 index 00000000000..85856f290ed --- /dev/null +++ b/include/configs/ib62x0.h @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2011-2012 + * Gerald Kerma + * Luka Perkov + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _CONFIG_IB62x0_H +#define _CONFIG_IB62x0_H + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING " RaidSonic ICY BOX IB-NAS62x0" + +/* + * High level configuration options + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Machine type + */ +#define CONFIG_MACH_TYPE MACH_TYPE_NAS6210 + +/* + * Compression configuration + */ +#define CONFIG_BZIP2 +#define CONFIG_LZMA +#define CONFIG_LZO + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#include +#define CONFIG_CMD_ENV +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "ib62x0 => " + +/* + * Environment variables configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x80000 + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount root; " \ + "ubifsload 0x800000 ${kernel}; " \ + "ubifsload 0x1100000 ${initrd}; " \ + "bootm 0x800000 0x1100000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "0x80000@0x0(uboot)," \ + "0x20000@0x80000(uboot_env)," \ + "-@0xa0000(root)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS \ + "kernel=/boot/uImage\0" \ + "initrd=/boot/uInitrd\0" \ + "bootargs_root=ubi.mtd=2 root=ubi0:root rootfstype=ubifs\0" + +/* + * Ethernet driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#undef CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +/* + * SATA driver configuration + */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_DOS_PARTITION +#define CONFIG_MVSATA_IDE_USE_PORT0 +#define CONFIG_MVSATA_IDE_USE_PORT1 +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /* CONFIG_CMD_IDE */ + +/* + * RTC driver configuration + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS + +#endif /* _CONFIG_IB62x0_H */ -- cgit v1.3.1 From 1d0f5fa11d8b21b010ca5ee0cb2a3e921345afc4 Mon Sep 17 00:00:00 2001 From: David Purdy Date: Tue, 27 Mar 2012 16:01:09 +0000 Subject: kirkwood: add support for Cloud Engines Pogoplug E02 This patch adds support for Cloud Engines Pogoplug E02 Information regarding the CE Pogoplug E02 board can be found at: http://archlinuxarm.org/platforms/armv5/pogoplug-v2-pinkgray Signed-off-by: Dave Purdy Cc: prafulla@marvell.com Cc: albert.u.boot@aribaud.net --- MAINTAINERS | 4 + board/cloudengines/pogo_e02/Makefile | 43 ++++++++ board/cloudengines/pogo_e02/kwbimage.cfg | 169 +++++++++++++++++++++++++++++++ board/cloudengines/pogo_e02/pogo_e02.c | 118 +++++++++++++++++++++ board/cloudengines/pogo_e02/pogo_e02.h | 44 ++++++++ boards.cfg | 1 + include/configs/pogo_e02.h | 119 ++++++++++++++++++++++ 7 files changed, 498 insertions(+) create mode 100644 board/cloudengines/pogo_e02/Makefile create mode 100644 board/cloudengines/pogo_e02/kwbimage.cfg create mode 100644 board/cloudengines/pogo_e02/pogo_e02.c create mode 100644 board/cloudengines/pogo_e02/pogo_e02.h create mode 100644 include/configs/pogo_e02.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 71a2a8407d3..a28967fe7db 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -792,6 +792,10 @@ Stelian Pop at91sam9263ek ARM926EJS (AT91SAM9263 SoC) at91sam9rlek ARM926EJS (AT91SAM9RL SoC) +Dave Purdy + + pogo_e02 ARM926EJS (Kirkwood SoC) + Thierry Reding plutux Tegra2 (ARM7 & A9 Dual Core) diff --git a/board/cloudengines/pogo_e02/Makefile b/board/cloudengines/pogo_e02/Makefile new file mode 100644 index 00000000000..7f866910e8b --- /dev/null +++ b/board/cloudengines/pogo_e02/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; If not, see . +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := pogo_e02.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cloudengines/pogo_e02/kwbimage.cfg b/board/cloudengines/pogo_e02/kwbimage.cfg new file mode 100644 index 00000000000..a02e88d97b2 --- /dev/null +++ b/board/cloudengines/pogo_e02/kwbimage.cfg @@ -0,0 +1,169 @@ +# +# Copyright (C) 2012 +# David Purdy +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; If not, see . +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xffd100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xffd01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xffd01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xffd0140c 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xffd01410 0x000000cc # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=x8 +# bit7-6: 11, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xffd01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xffd01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xffd0141c 0x00000c52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xffd01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xffd01424 0x0000f17f # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xffd01504 0x0ffffff1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xffd0150c 0x00000000 # CS[2]n Size, window disabled + +DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled + +DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) +# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xffd0149c 0x0000e803 # CPU ODT Control +DATA 0xffd01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c new file mode 100644 index 00000000000..ff3421d5761 --- /dev/null +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2012 + * David Purdy + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, see . + */ + +#include +#include +#include +#include +#include +#include "pogo_e02.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(POGO_E02_OE_VAL_LOW, + POGO_E02_OE_VAL_HIGH, + POGO_E02_OE_LOW, POGO_E02_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_UART0_RTS, + MPP9_UART0_CTS, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP29_TSMP9, /* USB Power Enable */ + MPP48_GPIO, /* LED green */ + MPP49_GPIO, /* LED orange */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + return 0; +} + +int board_init(void) +{ + /* Boot parameters address */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and initialize PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..(%s) could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + debug("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/cloudengines/pogo_e02/pogo_e02.h b/board/cloudengines/pogo_e02/pogo_e02.h new file mode 100644 index 00000000000..40b4bab9e05 --- /dev/null +++ b/board/cloudengines/pogo_e02/pogo_e02.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 + * David Purdy + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, see . + */ + +#ifndef __POGO_E02_H +#define __POGO_E02_H + +/* GPIO configuration */ +#define POGO_E02_OE_LOW (~(0)) +#define POGO_E02_OE_HIGH (~(0)) +#define POGO_E02_OE_VAL_LOW (1 << 29) +#define POGO_E02_OE_VAL_HIGH 0 + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __POGO_E02_H */ diff --git a/boards.cfg b/boards.cfg index 8f01c602d57..4e94197bc2b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -136,6 +136,7 @@ hawkboard arm arm926ejs da8xxevm davinci hawkboard_uart arm arm926ejs da8xxevm davinci davinci hawkboard:UART_U_BOOT enbw_cmc arm arm926ejs enbw_cmc enbw davinci calimain arm arm926ejs calimain omicron davinci +pogo_e02 arm arm926ejs - cloudengines kirkwood dns325 arm arm926ejs - d-link kirkwood km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_RECONFIG_XLX diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h new file mode 100644 index 00000000000..df46be5469d --- /dev/null +++ b/include/configs/pogo_e02.h @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2012 + * David Purdy + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, see . + */ + +#ifndef _CONFIG_POGO_E02_H +#define _CONFIG_POGO_E02_H + +/* + * Machine type definition and ID + */ +#define MACH_TYPE_POGO_E02 3542 +#define CONFIG_MACH_TYPE MACH_TYPE_POGO_E02 +#define CONFIG_IDENT_STRING "\nPogo E02" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#include +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */ +#define CONFIG_SYS_PROMPT "PogoE02> " + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs $(bootargs_console); " \ + "run bootcmd_usb; " \ + "bootm 0x00800000 0x01100000" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage)," \ + "32M(rootfs),-(data)\0"\ + "mtdids=nand0=orion_nand\0"\ + "bootargs_console=console=ttyS0,115200\0" \ + "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \ + "ext2load usb 0:1 0x01100000 /uInitrd\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#endif /* CONFIG_CMD_NET */ + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +#endif /* _CONFIG_POGO_E02_H */ -- cgit v1.3.1 From dc7a9e64bfdd0504e1a985b6a6121ed1b5a015d7 Mon Sep 17 00:00:00 2001 From: Enric Balletbò i Serra Date: Mon, 5 Mar 2012 11:32:16 +0000 Subject: OMAP3: igep00x0: Reduce lines of code for IGEP-based boards. This is rework on config files of IGEP-based boards with the aim to remove duplicated code to be more maintainable. Basically this patch creates a common configuration file for both boards and only sets the specific option in the board config file. On board files the hardcored mach type was replaced in favour of using the CONFIG_MACH_TYPE option. More than 200 duplicated lines have been deleted. Signed-off-by: Enric Balletbo i Serra --- board/isee/igep0020/igep0020.c | 2 - board/isee/igep0030/igep0030.c | 2 - boards.cfg | 4 +- include/configs/igep0020.h | 272 ---------------------------------------- include/configs/igep0030.h | 261 -------------------------------------- include/configs/igep00x0.h | 275 +++++++++++++++++++++++++++++++++++++++++ 6 files changed, 277 insertions(+), 539 deletions(-) delete mode 100644 include/configs/igep0020.h delete mode 100644 include/configs/igep0030.h create mode 100644 include/configs/igep00x0.h (limited to 'include') diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index 1919085d5ca..971e31b5f36 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -52,8 +52,6 @@ static const u32 gpmc_lan_config[] = { int board_init(void) { gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_IGEP0020; /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 492d9d40ffa..653c1b5abb1 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -39,8 +39,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_IGEP0030; /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); diff --git a/boards.cfg b/boards.cfg index 4e94197bc2b..4d839d2ab20 100644 --- a/boards.cfg +++ b/boards.cfg @@ -199,8 +199,8 @@ cm_t35 arm armv7 cm_t35 - omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 dig297 arm armv7 dig297 comelit omap3 -igep0020 arm armv7 igep0020 isee omap3 -igep0030 arm armv7 igep0030 isee omap3 +igep0020 arm armv7 igep0020 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020 +igep0030 arm armv7 igep0030 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030 am3517_evm arm armv7 am3517evm logicpd omap3 mt_ventoux arm armv7 mt_ventoux teejet omap3 omap3_zoom1 arm armv7 zoom1 logicpd omap3 diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h deleted file mode 100644 index c2fcdffdae1..00000000000 --- a/include/configs/igep0020.h +++ /dev/null @@ -1,272 +0,0 @@ -/* - * (C) Copyright 2010 - * ISEE 2007 SL, - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H -#include - -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3_IGEP0020 1 /* working with IGEP0020 */ - -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include -#include - -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#define CONFIG_OF_LIBFDT 1 - -/* - * NS16550 Configuration - */ - -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* select serial console configuration */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - -/* USB */ -#define CONFIG_MUSB_UDC 1 -#define CONFIG_USB_OMAP3 1 -#define CONFIG_TWL4030_USB 1 - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 - -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "IGEP" - -/* commands to include */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_ONENAND /* ONENAND support */ -#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_NFS /* NFS support */ -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ -#define CONFIG_MTD_DEVICE - -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#undef CONFIG_CMD_IMLS /* List all found images */ - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER 1 - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "usbtty=cdc_acm\0" \ - "loadaddr=0x82000000\0" \ - "usbtty=cdc_acm\0" \ - "console=ttyS2,115200n8\0" \ - "mpurate=500\0" \ - "vram=12M\0" \ - "dvimode=1024x768MR-16@60\0" \ - "defaultdisplay=dvi\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "nandroot=/dev/mtdblock4 rw\0" \ - "nandrootfstype=jffs2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from onenand ...; " \ - "run nandargs; " \ - "onenand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" - -#define CONFIG_AUTO_COMPLETE 1 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT "U-Boot # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ - /* works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ - -/* - * Physical Memory Map - * - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* - * FLASH and environment organization - */ - -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */ - -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_ENV_IS_IN_ONENAND 1 -#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ -#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -/* - * SMSC911x Ethernet - */ -#if defined(CONFIG_CMD_NET) -#define CONFIG_SMC911X -#define CONFIG_SMC911X_32_BIT -#define CONFIG_SMC911X_BASE 0x2C000000 -#endif /* (CONFIG_CMD_NET) */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/igep0030.h b/include/configs/igep0030.h deleted file mode 100644 index bf39ba56d79..00000000000 --- a/include/configs/igep0030.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - * (C) Copyright 2010 - * ISEE 2007 SL, - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H -#include - -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3_IGEP0030 1 /* working with IGEP0030 */ - -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include -#include - -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#define CONFIG_OF_LIBFDT 1 - -/* - * NS16550 Configuration - */ - -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* select serial console configuration */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - -/* USB */ -#define CONFIG_MUSB_UDC 1 -#define CONFIG_USB_OMAP3 1 -#define CONFIG_TWL4030_USB 1 - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 - -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "IGEP" - -/* commands to include */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_ONENAND /* ONENAND support */ -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ -#define CONFIG_MTD_DEVICE - -#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#undef CONFIG_CMD_NFS /* nfs */ -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#undef CONFIG_CMD_IMLS /* List all found images */ - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER 1 - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "usbtty=cdc_acm\0" \ - "loadaddr=0x82000000\0" \ - "usbtty=cdc_acm\0" \ - "console=ttyS2,115200n8\0" \ - "mpurate=500\0" \ - "vram=12M\0" \ - "dvimode=1024x768MR-16@60\0" \ - "defaultdisplay=dvi\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "nandroot=/dev/mtdblock4 rw\0" \ - "nandrootfstype=jffs2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from onenand ...; " \ - "run nandargs; " \ - "onenand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" - -#define CONFIG_AUTO_COMPLETE 1 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT "U-Boot # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ - /* works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ - -/* - * Physical Memory Map - * - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* - * FLASH and environment organization - */ - -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */ - -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_ENV_IS_IN_ONENAND 1 -#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ -#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h new file mode 100644 index 00000000000..d2b4b849290 --- /dev/null +++ b/include/configs/igep00x0.h @@ -0,0 +1,275 @@ +/* + * Common configuration settings for IGEP technology based boards + * + * (C) Copyright 2012 + * ISEE 2007 SL, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IGEP00X0_H +#define __IGEP00X0_H + +#include + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ + +#define CONFIG_SDRC /* The chip has SDRC controller */ + +#include +#include + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +#define CONFIG_OF_LIBFDT 1 + +/* + * NS16550 Configuration + */ + +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* select serial console configuration */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ + 115200} +#define CONFIG_GENERIC_MMC 1 +#define CONFIG_MMC 1 +#define CONFIG_OMAP_HSMMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* USB */ +#define CONFIG_MUSB_UDC 1 +#define CONFIG_USB_OMAP3 1 +#define CONFIG_TWL4030_USB 1 + +/* USB device configuration */ +#define CONFIG_USB_DEVICE 1 +#define CONFIG_USB_TTY 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +/* Change these to suit your needs */ +#define CONFIG_USBD_VENDORID 0x0451 +#define CONFIG_USBD_PRODUCTID 0x5678 +#define CONFIG_USBD_MANUFACTURER "Texas Instruments" +#define CONFIG_USBD_PRODUCT_NAME "IGEP" + +/* commands to include */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_ONENAND /* ONENAND support */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ +#define CONFIG_MTD_DEVICE + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_POWER 1 + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "usbtty=cdc_acm\0" \ + "loadaddr=0x82000000\0" \ + "usbtty=cdc_acm\0" \ + "console=ttyS2,115200n8\0" \ + "mpurate=500\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=jffs2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from onenand ...; " \ + "run nandargs; " \ + "onenand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "U-Boot # " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ + /* works on */ +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ + /* load address */ + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* + * Physical Memory Map + * + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * FLASH and environment organization + */ + +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */ + +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_ENV_IS_IN_ONENAND 1 +#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ +#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) + +/* + * SMSC911x Ethernet + */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_SMC911X +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE 0x2C000000 +#endif /* (CONFIG_CMD_NET) */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#endif /* __IGEP00X0_H */ -- cgit v1.3.1 From 7a4bf209306346e30df18703b8c9af13e42fd10a Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Mon, 12 Mar 2012 02:25:44 +0000 Subject: OMAP5: defconfig: Align the defconfig for 5430 ES1.0 Adding the nessecary changes for OMAP5430 ES1.0 silicon. Signed-off-by: R Sricharan --- include/configs/omap5_evm.h | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index d3d526310ea..0bdfd6948b0 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -49,8 +49,10 @@ #define CONFIG_DISPLAY_BOARDINFO /* Clock Defines */ -#define V_OSCK 38400000 /* Clock output from T2 */ +#define V_OSCK 19200000 /* Clock output from T2 */ #define V_SCLK V_OSCK +#define CONFIG_SYS_CLOCKS_ENABLE_ALL 1 /* Enable all clocks */ +#define CONFIG_SYS_ENABLE_PADS_ALL 1 /* Enable all PADS for now */ #undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R @@ -97,10 +99,6 @@ #define CONFIG_DRIVER_OMAP34XX_I2C #define CONFIG_I2C_MULTI_BUS -/* TWL6030 */ -#define CONFIG_TWL6030_POWER -#define CONFIG_CMD_BAT - /* MMC */ #define CONFIG_GENERIC_MMC #define CONFIG_MMC @@ -112,13 +110,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ #define CONFIG_ENV_OFFSET 0xE0000 -/* USB */ -#define CONFIG_MUSB_UDC -#define CONFIG_USB_OMAP3 - -/* USB device configuration */ -#define CONFIG_USB_DEVICE -#define CONFIG_USB_TTY #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Flash */ @@ -154,7 +145,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ - "console=ttyS2,115200n8\0" \ + "console=ttyO2,115200n8\0" \ "usbtty=cdc_acm\0" \ "vram=16M\0" \ "mmcdev=0\0" \ @@ -250,8 +241,8 @@ /* Defines for SPL */ #define CONFIG_SPL -#define CONFIG_SPL_TEXT_BASE 0x40304350 -#define CONFIG_SPL_MAX_SIZE 0x1E000 /* 120K */ +#define CONFIG_SPL_TEXT_BASE 0x40300350 +#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -- cgit v1.3.1 From 211442989628d72fad1f2663a0bf5076e425fabd Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Mon, 12 Mar 2012 02:25:48 +0000 Subject: power: twl6035: add palmas PMIC support palmas/TWL6035 is power IC for omap5 evm boards Signed-off-by: Balaji T K --- board/ti/omap5_evm/evm.c | 6 +++--- drivers/power/Makefile | 1 + drivers/power/twl6035.c | 40 ++++++++++++++++++++++++++++++++++++++++ include/configs/omap5_evm.h | 5 +++++ include/twl6035.h | 41 +++++++++++++++++++++++++++++++++++++++++ 5 files changed, 90 insertions(+), 3 deletions(-) create mode 100644 drivers/power/twl6035.c create mode 100644 include/twl6035.h (limited to 'include') diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_evm/evm.c index 88dac80225e..c8dfdf81429 100644 --- a/board/ti/omap5_evm/evm.c +++ b/board/ti/omap5_evm/evm.c @@ -23,7 +23,7 @@ * MA 02111-1307 USA */ #include -#include +#include #include #include @@ -63,8 +63,8 @@ int board_eth_init(bd_t *bis) */ int misc_init_r(void) { -#ifdef CONFIG_TWL6030_POWER - twl6030_init_battery_charging(); +#ifdef CONFIG_TWL6035_POWER + twl6035_init_settings(); #endif return 0; } diff --git a/drivers/power/Makefile b/drivers/power/Makefile index ead00f8dae6..f24b93cc318 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libpower.o COBJS-$(CONFIG_FTPMU010_POWER) += ftpmu010.o COBJS-$(CONFIG_TWL4030_POWER) += twl4030.o COBJS-$(CONFIG_TWL6030_POWER) += twl6030.o +COBJS-$(CONFIG_TWL6035_POWER) += twl6035.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/power/twl6035.c b/drivers/power/twl6035.c new file mode 100644 index 00000000000..d75212c9641 --- /dev/null +++ b/drivers/power/twl6035.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2012 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include + +/* Functions to read and write from TWL6030 */ +int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg) +{ + return i2c_write(chip_no, reg, 1, &val, 1); +} + +int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg) +{ + return i2c_read(chip_no, reg, 1, val, 1); +} + +void twl6035_init_settings(void) +{ + return; +} diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index 0bdfd6948b0..2dc98118056 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -99,6 +99,11 @@ #define CONFIG_DRIVER_OMAP34XX_I2C #define CONFIG_I2C_MULTI_BUS +/* TWL6035 */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_TWL6035_POWER +#endif + /* MMC */ #define CONFIG_GENERIC_MMC #define CONFIG_MMC diff --git a/include/twl6035.h b/include/twl6035.h new file mode 100644 index 00000000000..1e133175d72 --- /dev/null +++ b/include/twl6035.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2012 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* I2C chip addresses */ +#define TWL6035_CHIP_ADDR 0x48 + +/* 0x1XY translates to page 1, register address 0xXY */ +#define LDO9_CTRL 0x60 +#define LDO9_VOLTAGE 0x61 + +/* Bit field definitions for LDOx_CTRL */ +#define LDO_ON (1 << 4) +#define LDO_MODE_SLEEP (1 << 2) +#define LDO_MODE_ACTIVE (1 << 0) + +int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg); +int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg); +void twl6035_init_settings(void); -- cgit v1.3.1 From dd23e59d595f02f6f79b003c372b22b467a005f2 Mon Sep 17 00:00:00 2001 From: Balaji T K Date: Mon, 12 Mar 2012 02:25:49 +0000 Subject: omap5: pbias ldo9 turn on Add omap5 pbias configuration for mmc1/sd lines and set voltage for sd data i/o lines Signed-off-by: Balaji T K --- arch/arm/include/asm/arch-omap5/omap.h | 7 ++++--- drivers/mmc/omap_hsmmc.c | 33 +++++++++++++++++++++++++++++++++ drivers/power/twl6035.c | 25 +++++++++++++++++++++++++ include/twl6035.h | 1 + 4 files changed, 63 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 27253929699..d672b6f9d9f 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -125,9 +125,10 @@ /* CONTROL_EFUSE_2 */ #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 -#define MMC1_PWRDNZ (1 << 26) -#define MMC1_PBIASLITE_PWRDNZ (1 << 22) -#define MMC1_PBIASLITE_VMODE (1 << 21) +#define SDCARD_PWRDNZ (1 << 26) +#define SDCARD_BIAS_HIZ_MODE (1 << 25) +#define SDCARD_BIAS_PWRDNZ (1 << 22) +#define SDCARD_PBIASLITE_VMODE (1 << 21) #ifndef __ASSEMBLY__ diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index f421ff9eede..e3670d4ad48 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -60,6 +61,34 @@ static void omap4_vmmc_pbias_config(struct mmc *mmc) } #endif +#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER) +static void omap5_pbias_config(struct mmc *mmc) +{ + u32 value = 0; + struct omap_sys_ctrl_regs *const ctrl = + (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + + value = readl(&ctrl->control_pbias); + value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); + value |= SDCARD_BIAS_HIZ_MODE; + writel(value, &ctrl->control_pbias); + + twl6035_mmc1_poweron_ldo(); + + value = readl(&ctrl->control_pbias); + value &= ~SDCARD_BIAS_HIZ_MODE; + value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ; + writel(value, &ctrl->control_pbias); + + value = readl(&ctrl->control_pbias); + if (value & (1 << 23)) { + value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); + value |= SDCARD_BIAS_HIZ_MODE; + writel(value, &ctrl->control_pbias); + } +} +#endif + unsigned char mmc_board_init(struct mmc *mmc) { #if defined(CONFIG_TWL4030_POWER) @@ -99,6 +128,10 @@ unsigned char mmc_board_init(struct mmc *mmc) if (mmc->block_dev.dev == 0) omap4_vmmc_pbias_config(mmc); #endif +#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER) + if (mmc->block_dev.dev == 0) + omap5_pbias_config(mmc); +#endif return 0; } diff --git a/drivers/power/twl6035.c b/drivers/power/twl6035.c index d75212c9641..624c09e85dc 100644 --- a/drivers/power/twl6035.c +++ b/drivers/power/twl6035.c @@ -34,7 +34,32 @@ int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg) return i2c_read(chip_no, reg, 1, val, 1); } +/* To align with i2c mw/mr address, reg, val command syntax */ +static inline int palmas_write_u8(u8 chip_no, u8 reg, u8 val) +{ + return i2c_write(chip_no, reg, 1, &val, 1); +} + +static inline int palmas_read_u8(u8 chip_no, u8 reg, u8 *val) +{ + return i2c_read(chip_no, reg, 1, val, 1); +} + void twl6035_init_settings(void) { return; } + +void twl6035_mmc1_poweron_ldo(void) +{ + u8 val = 0; + + /* set LDO9 TWL6035 to 3V */ + val = 0x2b; /* (3 -.9)*28 +1 */ + palmas_write_u8(0x48, LDO9_VOLTAGE, val); + + /* TURN ON LDO9 */ + val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE; + palmas_write_u8(0x48, LDO9_CTRL, val); + return; +} diff --git a/include/twl6035.h b/include/twl6035.h index 1e133175d72..e21ddbaf22f 100644 --- a/include/twl6035.h +++ b/include/twl6035.h @@ -39,3 +39,4 @@ int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg); int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg); void twl6035_init_settings(void); +void twl6035_mmc1_poweron_ldo(void); -- cgit v1.3.1 From 328aecaf3dbca4eea31632a5bfddf38b63204227 Mon Sep 17 00:00:00 2001 From: Balaji T K Date: Mon, 12 Mar 2012 02:25:50 +0000 Subject: mmc: omap5evm: Add eMMC saveenv support Save env to eMMC Signed-off-by: Balaji T K --- include/configs/omap5_evm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index 2dc98118056..6c91ee884e8 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -114,6 +114,7 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ #define CONFIG_ENV_OFFSET 0xE0000 +#define CONFIG_CMD_SAVEENV #define CONFIG_SYS_CONSOLE_IS_IN_ENV -- cgit v1.3.1 From 7245536d19aaf0a6dc1c2d4a8fa80adf2f2ae739 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Thu, 8 Mar 2012 07:20:17 +0000 Subject: arm: adapt asm/linkage.h from Linux This will add ARM specific over-rides for the defines from linux/linkage.h Signed-off-by: Aneesh V Tested-by: Mike Frysinger --- arch/arm/include/asm/linkage.h | 7 +++++++ include/linux/linkage.h | 7 ++++++- 2 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/linkage.h (limited to 'include') diff --git a/arch/arm/include/asm/linkage.h b/arch/arm/include/asm/linkage.h new file mode 100644 index 00000000000..dbe4b4e31a5 --- /dev/null +++ b/arch/arm/include/asm/linkage.h @@ -0,0 +1,7 @@ +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H + +#define __ALIGN .align 0 +#define __ALIGN_STR ".align 0" + +#endif diff --git a/include/linux/linkage.h b/include/linux/linkage.h index ed4cf6cbcd5..7b749bbda70 100644 --- a/include/linux/linkage.h +++ b/include/linux/linkage.h @@ -44,8 +44,13 @@ #define SYMBOL_NAME_LABEL(X) X: #endif +#ifndef __ALIGN #define __ALIGN .align 4 +#endif + +#ifndef __ALIGN_STR #define __ALIGN_STR ".align 4" +#endif #ifdef __ASSEMBLY__ @@ -67,7 +72,7 @@ #ifndef ENDPROC #define ENDPROC(name) \ - .type name, @function; \ + .type name STT_FUNC; \ END(name) #endif -- cgit v1.3.1 From 20c6312913f7f2f86e0266320fbef3236382b7aa Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Thu, 8 Mar 2012 07:20:22 +0000 Subject: OMAP4: enable Thumb build Signed-off-by: Aneesh V --- include/configs/omap4_common.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index a989721afc4..01b4d6c6b71 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -287,4 +287,6 @@ #define CONFIG_SYS_ENABLE_PADS_ALL +#define CONFIG_SYS_THUMB_BUILD + #endif /* __CONFIG_OMAP4_COMMON_H */ -- cgit v1.3.1 From 9baa37b1df1dde38d53c55eaece19e17929f120f Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Thu, 22 Mar 2012 13:49:23 +0000 Subject: OMAP3: pandora: drop console kernel argument As ttyS0 is no longer valid for newer OMAP kernels, and pandora serial cables are not widespread, simply drop console argument. This should allow booting old and new kernels with default arguments, and those who need serial can use a boot script on SD card. Signed-off-by: Grazvydas Ignotas --- include/configs/omap3_pandora.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 4df5f5dac55..d02f3384374 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -174,8 +174,7 @@ "usbtty=cdc_acm\0" \ "loadaddr=0x82000000\0" \ "bootargs=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \ - "rw rootflags=bulk_read console=ttyS0,115200n8 " \ - "vram=6272K omapfb.vram=0:3000K\0" \ + "rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ #define CONFIG_BOOTCOMMAND \ -- cgit v1.3.1 From 4335517088e2fbab72254eac989e95d2090dc884 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 13 Apr 2012 12:19:59 +0000 Subject: omap4: Remove CONFIG_SYS_MMC_SET_DEV This is only used on !CONFIG_GENERIC_MMC which is false here. Signed-off-by: Tom Rini --- include/configs/omap4_common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 01b4d6c6b71..4ace07b6244 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -106,7 +106,6 @@ #define CONFIG_GENERIC_MMC 1 #define CONFIG_MMC 1 #define CONFIG_OMAP_HSMMC 1 -#define CONFIG_SYS_MMC_SET_DEV 1 #define CONFIG_DOS_PARTITION 1 -- cgit v1.3.1 From aa2889c8c3e49d3bae3ce8132ca55b62e841835e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 13 Apr 2012 12:20:00 +0000 Subject: omap4+: Remove CONFIG_ARCH_CPU_INIT OMAP4/5 had an empty arch_cpu_init() so drop that along with CONFIG_ARCH_CPU_INIT Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 10 ---------- include/configs/omap4_common.h | 1 - include/configs/omap5_evm.h | 1 - 3 files changed, 12 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 10e76698055..cf71ab44438 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -202,16 +202,6 @@ int checkboard(void) return 0; } -/* -* This function is called by start_armboot. You can reliably use static -* data. Any boot-time function that require static data should be -* called from here -*/ -int arch_cpu_init(void) -{ - return 0; -} - /* * get_device_type(): tell if GP/HS/EMU/TST */ diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 4ace07b6244..5507c8f4c64 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -35,7 +35,6 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP44XX 1 /* which is a 44XX */ #define CONFIG_OMAP4430 1 /* which is in a 4430 */ -#define CONFIG_ARCH_CPU_INIT /* Get CPU defs */ #include diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index 6c91ee884e8..38b5028060a 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -38,7 +38,6 @@ #define CONFIG_OMAP54XX /* which is a 54XX */ #define CONFIG_OMAP5430 /* which is in a 5430 */ #define CONFIG_5430EVM /* working with EVM */ -#define CONFIG_ARCH_CPU_INIT /* Get CPU defs */ #include -- cgit v1.3.1 From b8f4a728e6ece65857e855feaa3aac7996ef8d5c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 13 Apr 2012 12:20:01 +0000 Subject: omap5912osk: Remove empty misc_init_r We had a do-nothing misc_init_r, remove along with CONFIG_MISC_INIT_R Signed-off-by: Tom Rini --- board/ti/omap5912osk/omap5912osk.c | 7 ------- include/configs/omap5912osk.h | 2 -- 2 files changed, 9 deletions(-) (limited to 'include') diff --git a/board/ti/omap5912osk/omap5912osk.c b/board/ti/omap5912osk/omap5912osk.c index 6f0e763f011..fac683a7e63 100644 --- a/board/ti/omap5912osk/omap5912osk.c +++ b/board/ti/omap5912osk/omap5912osk.c @@ -81,13 +81,6 @@ int board_init (void) return 0; } - -int misc_init_r (void) -{ - /* currently empty */ - return (0); -} - /****************************** Routine: Description: diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h index a8dfef321d3..d3a2438e282 100644 --- a/include/configs/omap5912osk.h +++ b/include/configs/omap5912osk.h @@ -44,8 +44,6 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_MISC_INIT_R - #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */ -- cgit v1.3.1 From 60bd10df8a3d553962b9f6704e055c2475a2414a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 13 Apr 2012 12:20:02 +0000 Subject: omap730p2: Remove empty misc_init_r We had a do-nothing misc_init_r, remove along with CONFIG_MISC_INIT_R Signed-off-by: Tom Rini --- board/ti/omap730p2/omap730p2.c | 6 ------ include/configs/omap730p2.h | 2 -- 2 files changed, 8 deletions(-) (limited to 'include') diff --git a/board/ti/omap730p2/omap730p2.c b/board/ti/omap730p2/omap730p2.c index 954ced5efe5..36204b2c88e 100644 --- a/board/ti/omap730p2/omap730p2.c +++ b/board/ti/omap730p2/omap730p2.c @@ -129,12 +129,6 @@ int board_init (void) return 0; } -int misc_init_r (void) -{ - /* currently empty */ - return (0); -} - /****************************** Routine: Description: diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h index 26e7e1f1e0e..f7900e0d83f 100644 --- a/include/configs/omap730p2.h +++ b/include/configs/omap730p2.h @@ -49,8 +49,6 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_MISC_INIT_R - #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 -- cgit v1.3.1 From 1005ccfda493febde8543fef3b0d41f5c74cd06d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 13 Apr 2012 12:20:04 +0000 Subject: include/configs: Remove CONFIG_SYS_64BIT_VSPRINTF This define does not control anything, remove it. Signed-off-by: Tom Rini --- include/configs/P1023RDS.h | 1 - include/configs/P2020COME.h | 1 - include/configs/am3517_crane.h | 1 - include/configs/am3517_evm.h | 2 -- include/configs/at91sam9263ek.h | 2 -- include/configs/da830evm.h | 1 - include/configs/ea20.h | 1 - include/configs/eb_cpux9k2.h | 2 -- include/configs/flea3.h | 2 -- include/configs/hawkboard.h | 1 - include/configs/imx27lite-common.h | 1 - include/configs/mcx.h | 2 -- include/configs/meesc.h | 1 - include/configs/mv-common.h | 1 - include/configs/mx25pdk.h | 1 - include/configs/mx35pdk.h | 2 -- include/configs/otc570.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/spear-common.h | 1 - include/configs/tam3517-common.h | 1 - include/configs/tx25.h | 2 -- include/configs/zmx25.h | 2 -- 22 files changed, 30 deletions(-) (limited to 'include') diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index e057b1f9459..b7236b25733 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -310,7 +310,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_BOARD_SETUP #define CONFIG_OF_STDOUT_VIA_ALIAS -#define CONFIG_SYS_64BIT_VSPRINTF #define CONFIG_SYS_64BIT_STRTOUL /* new uImage format support */ diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h index 365322c6a59..12f9860edd1 100644 --- a/include/configs/P2020COME.h +++ b/include/configs/P2020COME.h @@ -416,7 +416,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* Misc Extra Settings */ -#define CONFIG_SYS_64BIT_VSPRINTF 1 #define CONFIG_SYS_64BIT_STRTOUL 1 #define CONFIG_CMD_DHCP 1 diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index b0dd2f0af61..71321f339e8 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -174,7 +174,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ /* NAND devices */ -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index b5f75d1e8da..bbd19def5d5 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -173,8 +173,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ /* NAND devices */ -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ - #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 83992461f90..f424e5a5bd7 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -283,8 +283,6 @@ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 - -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* Ethernet */ diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index 4532e4f4fdd..781878ef399 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -111,7 +111,6 @@ #define CONFIG_SYS_NAND_CS 3 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE #define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define CONFIG_SYS_CLE_MASK 0x10 #define CONFIG_SYS_ALE_MASK 0x8 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ diff --git a/include/configs/ea20.h b/include/configs/ea20.h index e059b308266..04e7a2d4de9 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -203,7 +203,6 @@ #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* SPI Flash */ diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h index eb05e2a0b06..21c471adf6c 100644 --- a/include/configs/eb_cpux9k2.h +++ b/include/configs/eb_cpux9k2.h @@ -288,8 +288,6 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 -#define CONFIG_SYS_64BIT_VSPRINTF 1 - /* Status LED's */ #define CONFIG_STATUS_LED 1 diff --git a/include/configs/flea3.h b/include/configs/flea3.h index f046a587bec..dd7c73f3c7b 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -48,8 +48,6 @@ /* Set TEXT at the beginning of the NOR flash */ #define CONFIG_SYS_TEXT_BASE 0xA0000000 -#define CONFIG_SYS_64BIT_VSPRINTF - /* This is required to setup the ESDC controller */ #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h index 08593713879..6d2d4fb91d7 100644 --- a/include/configs/hawkboard.h +++ b/include/configs/hawkboard.h @@ -127,7 +127,6 @@ #define CFG_DAVINCI_STD_NAND_LAYOUT #define CONFIG_SYS_NAND_CS 3 #define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE_LIST { 0x62000000, } diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 2af4e7af314..c1f1aa6a8a3 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -153,7 +153,6 @@ #define CONFIG_SYS_NAND_BASE 0xd8000000 #define CONFIG_JFFS2_NAND #define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ /* * SD/MMC diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 1315c3ceb81..e190e3e02d7 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -171,8 +171,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ /* NAND devices */ -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ - #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" diff --git a/include/configs/meesc.h b/include/configs/meesc.h index d6197bc610a..db1e87d69c1 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -164,7 +164,6 @@ # define CONFIG_SYS_NAND_MASK_CLE (1 << 22) # define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 # define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 -# define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* Ethernet */ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 1a6379176b3..27b489902bd 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -132,7 +132,6 @@ */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index d1ba02b6eed..7210b6e80f2 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -65,7 +65,6 @@ #define CONFIG_ENV_IS_NOWHERE #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_64BIT_VSPRINTF /* U-Boot general configuration */ #define CONFIG_SYS_PROMPT "MX25PDK U-Boot > " diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index de4b954a52f..bd57baa808f 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -39,8 +39,6 @@ #define CONFIG_SYS_TEXT_BASE 0xA0000000 #define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_64BIT_VSPRINTF - #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/otc570.h b/include/configs/otc570.h index b322c775a10..85993789b97 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -215,7 +215,6 @@ # define CONFIG_SYS_NAND_MASK_CLE (1 << 22) # define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 # define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 -# define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* Ethernet */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 9f2951d6879..46218adf08a 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -534,7 +534,6 @@ #define CONFIG_OF_BOARD_SETUP #define CONFIG_OF_STDOUT_VIA_ALIAS -#define CONFIG_SYS_64BIT_VSPRINTF #define CONFIG_SYS_64BIT_STRTOUL /* new uImage format support */ diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index a79181565e2..ab1b33209e3 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -196,7 +196,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR 0x00800000 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 -#define CONFIG_SYS_64BIT_VSPRINTF 1 #define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 4c4321d2ff3..37eb87bf0a3 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -146,7 +146,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ /* NAND devices */ -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define CONFIG_AUTO_COMPLETE diff --git a/include/configs/tx25.h b/include/configs/tx25.h index 87bd8a6756c..3dfafa50775 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -117,8 +117,6 @@ #define CONFIG_MXC_NAND_HWECC #define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_64BIT_VSPRINTF - /* U-Boot general configuration */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 599d5bb42aa..d7ce6c64de6 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -93,8 +93,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_CACHE -#define CONFIG_SYS_64BIT_VSPRINTF - /* * Additional command */ -- cgit v1.3.1 From 4ac16f2bbd0f90522a48bbd52a382a1db065d11a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 13 Apr 2012 12:20:05 +0000 Subject: include/configs: Remove CONFIG_SYS_64BIT_STRTOUL This define does not control anything, remove it. Signed-off-by: Tom Rini --- include/configs/P1023RDS.h | 2 -- include/configs/P2020COME.h | 1 - include/configs/p1_p2_rdb_pc.h | 2 -- 3 files changed, 5 deletions(-) (limited to 'include') diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index b7236b25733..e632d1bd37e 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -310,8 +310,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_BOARD_SETUP #define CONFIG_OF_STDOUT_VIA_ALIAS -#define CONFIG_SYS_64BIT_STRTOUL - /* new uImage format support */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h index 12f9860edd1..28122ecc115 100644 --- a/include/configs/P2020COME.h +++ b/include/configs/P2020COME.h @@ -416,7 +416,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* Misc Extra Settings */ -#define CONFIG_SYS_64BIT_STRTOUL 1 #define CONFIG_CMD_DHCP 1 #define CONFIG_CMD_DATE 1 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 46218adf08a..04fd8d07f58 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -534,8 +534,6 @@ #define CONFIG_OF_BOARD_SETUP #define CONFIG_OF_STDOUT_VIA_ALIAS -#define CONFIG_SYS_64BIT_STRTOUL - /* new uImage format support */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ -- cgit v1.3.1 From 79874ae9341d000d7428ae05d3bce54d90adb81c Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Mon, 2 Apr 2012 02:29:31 +0000 Subject: cm-t35: add I2C multi-bus support Enable I2C multi-bus support and config I2C muxes for I2C2 and I2C3. Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg --- board/cm_t35/cm_t35.c | 6 ++++++ include/configs/cm_t35.h | 1 + 2 files changed, 7 insertions(+) (limited to 'include') diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index 4c77790e4f2..89e6b08e7fa 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -230,6 +230,12 @@ static void cm_t3x_set_common_muxconf(void) /* I2C1 */ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ + /* I2C2 */ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ + /* I2C3 */ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ /* control and debug */ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index fe91c10409b..b28bd8e3139 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -156,6 +156,7 @@ #define CONFIG_DRIVER_OMAP34XX_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_I2C_MULTI_BUS /* * TWL4030 -- cgit v1.3.1 From 8913e6b3c3be991f669c4d6e2e797f37a2f96972 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 17 Apr 2012 16:42:22 +0000 Subject: arm: cam_enc_4xx: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT With almost all the architecture and board BOARD_LATE_INIT does not use. CONFIG_BOARD_LATE_INIT is used instead. This changed CONFIG_BOARD_LATE_INIT from BOARD_LATE_INIT. Signed-off-by: Nobuhiro Iwamatsu CC: Heiko Schocher Acked-by: Heiko Schocher --- include/configs/cam_enc_4xx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index 99856ebfdf2..71faf1cc9ff 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -37,7 +37,7 @@ #define CONFIG_HOSTNAME cam_enc_4xx -#define BOARD_LATE_INIT +#define CONFIG_BOARD_LATE_INIT #define CONFIG_CAM_ENC_LED_MASK 0x0fc00000 /* Memory Info */ -- cgit v1.3.1 From 2d594fd55d5d85f68b80cb7cc231157b9df231c7 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 17 Apr 2012 16:41:54 +0000 Subject: arm: ea20: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT With almost all the architecture and board BOARD_LATE_INIT does not use. CONFIG_BOARD_LATE_INIT is used instead. This changed CONFIG_BOARD_LATE_INIT from BOARD_LATE_INIT. Signed-off-by: Nobuhiro Iwamatsu CC: Stefano Babic Acked-by: Stefano Babic --- board/davinci/ea20/ea20.c | 4 ++-- include/configs/ea20.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index 43632c2fd80..7e000404ee6 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -272,7 +272,7 @@ int board_init(void) return 0; } -#ifdef BOARD_LATE_INIT +#ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { @@ -287,7 +287,7 @@ int board_late_init(void) return 0; } -#endif /* BOARD_LATE_INIT */ +#endif /* CONFIG_BOARD_LATE_INIT */ #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/include/configs/ea20.h b/include/configs/ea20.h index 04e7a2d4de9..88b085d4a7a 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -31,7 +31,7 @@ #define CONFIG_SYS_USE_NAND #define CONFIG_DRIVER_TI_EMAC_USE_RMII #define CONFIG_BOARD_EARLY_INIT_F -#define BOARD_LATE_INIT +#define CONFIG_BOARD_LATE_INIT #define CONFIG_VIDEO #define CONFIG_PREBOOT -- cgit v1.3.1 From 4d86bf086009a4edfe747341e7cb83bf46e6f022 Mon Sep 17 00:00:00 2001 From: Łukasz Majewski Date: Mon, 26 Mar 2012 21:53:48 +0000 Subject: ARM: Exynos4: ADC: Universal_C210: Enable LDO4 power line for ADC measurement This patch enables LDO4 power line for preparing proper voltages to be measured by ADC converter. This measurement is used for determination of target board HW revision. Test HW: Universal_C210 (Exynos4210) rev. 0.0 Signed-off-by: Lukasz Majewski Signed-off-by: Kyungmin Park Cc: Minkyu Kang Signed-off-by: Minkyu Kang --- board/samsung/universal_c210/universal.c | 25 ++++++++++++++++++++++--- include/max8998_pmic.h | 1 + 2 files changed, 23 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index d0ff8341f64..90fff5cf5e1 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -58,13 +58,13 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - check_hw_revision(); - printf("HW Revision:\t0x%x\n", board_rev); - #if defined(CONFIG_PMIC) pmic_init(); #endif + check_hw_revision(); + printf("HW Revision:\t0x%x\n", board_rev); + return 0; } @@ -109,10 +109,27 @@ static unsigned short get_adc_value(int channel) return ret; } +static int adc_power_control(int on) +{ + int ret; + struct pmic *p = get_pmic(); + + if (pmic_probe(p)) + return -1; + + ret = pmic_set_output(p, + MAX8998_REG_ONOFF1, + MAX8998_LDO4, !!on); + + return ret; +} + static unsigned int get_hw_revision(void) { int hwrev, mode0, mode1; + adc_power_control(1); + mode0 = get_adc_value(1); /* HWREV_MODE0 */ mode1 = get_adc_value(2); /* HWREV_MODE1 */ @@ -135,6 +152,8 @@ static unsigned int get_hw_revision(void) debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev); + adc_power_control(0); + return hwrev; } diff --git a/include/max8998_pmic.h b/include/max8998_pmic.h index 10c892a51df..ca21f882c29 100644 --- a/include/max8998_pmic.h +++ b/include/max8998_pmic.h @@ -75,6 +75,7 @@ enum { }; #define MAX8998_LDO3 (1 << 2) +#define MAX8998_LDO4 (1 << 1) #define MAX8998_LDO8 (1 << 5) #define MAX8998_SAFEOUT1 (1 << 4) -- cgit v1.3.1 From e687c5a8be4d268530dc17bb2690db87a69da90e Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Tue, 27 Mar 2012 20:05:25 +0000 Subject: TRATS: modify the trats's configuration Trats is supported 1GiB memory size. (Each bank size is 512MB.) And INITRD is unnecessary. So removed them. Signed-off-by: Jaehoon Chung Signed-off-by: Kyungmin Park Signed-off-by: Minkyu Kang --- include/configs/trats.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/trats.h b/include/configs/trats.h index 10f11d95792..674bc7194d8 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -53,7 +53,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG #define CONFIG_CMDLINE_EDITING #define CONFIG_SKIP_LOWLEVEL_INIT @@ -174,9 +173,9 @@ /* TRATS has 2 banks of DRAM */ #define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */ -#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */ +#define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */ #define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */ -#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */ +#define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */ #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ -- cgit v1.3.1 From 8504296045f714430cd755434ccb094711ea95fe Mon Sep 17 00:00:00 2001 From: Łukasz Majewski Date: Thu, 29 Mar 2012 01:29:17 +0000 Subject: misc:pmic:max8997 MAX8997 support for PMIC driver This commit adds support for MAX8997 PMIC driver. Signed-off-by: Lukasz Majewski Signed-off-by: Kyungmin Park Acked-by: Stefano Babic --- drivers/misc/Makefile | 1 + drivers/misc/pmic_max8997.c | 43 ++++++++++ include/max8997_pmic.h | 190 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 234 insertions(+) create mode 100644 drivers/misc/pmic_max8997.c create mode 100644 include/max8997_pmic.h (limited to 'include') diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index a70970784c2..30c7f8dd148 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_PMIC_FSL) += pmic_fsl.o COBJS-$(CONFIG_PMIC_I2C) += pmic_i2c.o COBJS-$(CONFIG_PMIC_SPI) += pmic_spi.o COBJS-$(CONFIG_PMIC_MAX8998) += pmic_max8998.o +COBJS-$(CONFIG_PMIC_MAX8997) += pmic_max8997.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/misc/pmic_max8997.c b/drivers/misc/pmic_max8997.c new file mode 100644 index 00000000000..62dbc05311c --- /dev/null +++ b/drivers/misc/pmic_max8997.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Lukasz Majewski + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +int pmic_init(void) +{ + struct pmic *p = get_pmic(); + static const char name[] = "MAX8997_PMIC"; + + puts("Board PMIC init\n"); + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = PMIC_NUM_OF_REGS; + p->hw.i2c.addr = MAX8997_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = I2C_PMIC; + + return 0; +} diff --git a/include/max8997_pmic.h b/include/max8997_pmic.h new file mode 100644 index 00000000000..17ae24ea6a0 --- /dev/null +++ b/include/max8997_pmic.h @@ -0,0 +1,190 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * Lukasz Majewski + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MAX8997_PMIC_H_ +#define __MAX8997_PMIC_H_ + +/* MAX 8997 registers */ +enum { + MAX8997_REG_PMIC_ID0 = 0x00, + MAX8997_REG_PMIC_ID1 = 0x01, + MAX8997_REG_INTSRC = 0x02, + MAX8997_REG_INT1 = 0x03, + MAX8997_REG_INT2 = 0x04, + MAX8997_REG_INT3 = 0x05, + MAX8997_REG_INT4 = 0x06, + + MAX8997_REG_INT1MSK = 0x08, + MAX8997_REG_INT2MSK = 0x09, + MAX8997_REG_INT3MSK = 0x0a, + MAX8997_REG_INT4MSK = 0x0b, + + MAX8997_REG_STATUS1 = 0x0d, + MAX8997_REG_STATUS2 = 0x0e, + MAX8997_REG_STATUS3 = 0x0f, + MAX8997_REG_STATUS4 = 0x10, + + MAX8997_REG_MAINCON1 = 0x13, + MAX8997_REG_MAINCON2 = 0x14, + MAX8997_REG_BUCKRAMP = 0x15, + + MAX8997_REG_BUCK1CTRL = 0x18, + MAX8997_REG_BUCK1DVS1 = 0x19, + MAX8997_REG_BUCK1DVS2 = 0x1a, + MAX8997_REG_BUCK1DVS3 = 0x1b, + MAX8997_REG_BUCK1DVS4 = 0x1c, + MAX8997_REG_BUCK1DVS5 = 0x1d, + MAX8997_REG_BUCK1DVS6 = 0x1e, + MAX8997_REG_BUCK1DVS7 = 0x1f, + MAX8997_REG_BUCK1DVS8 = 0x20, + MAX8997_REG_BUCK2CTRL = 0x21, + MAX8997_REG_BUCK2DVS1 = 0x22, + MAX8997_REG_BUCK2DVS2 = 0x23, + MAX8997_REG_BUCK2DVS3 = 0x24, + MAX8997_REG_BUCK2DVS4 = 0x25, + MAX8997_REG_BUCK2DVS5 = 0x26, + MAX8997_REG_BUCK2DVS6 = 0x27, + MAX8997_REG_BUCK2DVS7 = 0x28, + MAX8997_REG_BUCK2DVS8 = 0x29, + MAX8997_REG_BUCK3CTRL = 0x2a, + MAX8997_REG_BUCK3DVS = 0x2b, + MAX8997_REG_BUCK4CTRL = 0x2c, + MAX8997_REG_BUCK4DVS = 0x2d, + MAX8997_REG_BUCK5CTRL = 0x2e, + MAX8997_REG_BUCK5DVS1 = 0x2f, + MAX8997_REG_BUCK5DVS2 = 0x30, + MAX8997_REG_BUCK5DVS3 = 0x31, + MAX8997_REG_BUCK5DVS4 = 0x32, + MAX8997_REG_BUCK5DVS5 = 0x33, + MAX8997_REG_BUCK5DVS6 = 0x34, + MAX8997_REG_BUCK5DVS7 = 0x35, + MAX8997_REG_BUCK5DVS8 = 0x36, + MAX8997_REG_BUCK6CTRL = 0x37, + MAX8997_REG_BUCK6BPSKIPCTRL = 0x38, + MAX8997_REG_BUCK7CTRL = 0x39, + MAX8997_REG_BUCK7DVS = 0x3a, + MAX8997_REG_LDO1CTRL = 0x3b, + MAX8997_REG_LDO2CTRL = 0x3c, + MAX8997_REG_LDO3CTRL = 0x3d, + MAX8997_REG_LDO4CTRL = 0x3e, + MAX8997_REG_LDO5CTRL = 0x3f, + MAX8997_REG_LDO6CTRL = 0x40, + MAX8997_REG_LDO7CTRL = 0x41, + MAX8997_REG_LDO8CTRL = 0x42, + MAX8997_REG_LDO9CTRL = 0x43, + MAX8997_REG_LDO10CTRL = 0x44, + MAX8997_REG_LDO11CTRL = 0x45, + MAX8997_REG_LDO12CTRL = 0x46, + MAX8997_REG_LDO13CTRL = 0x47, + MAX8997_REG_LDO14CTRL = 0x48, + MAX8997_REG_LDO15CTRL = 0x49, + MAX8997_REG_LDO16CTRL = 0x4a, + MAX8997_REG_LDO17CTRL = 0x4b, + MAX8997_REG_LDO18CTRL = 0x4c, + MAX8997_REG_LDO21CTRL = 0x4d, + + MAX8997_REG_MBCCTRL1 = 0x50, + MAX8997_REG_MBCCTRL2 = 0x51, + MAX8997_REG_MBCCTRL3 = 0x52, + MAX8997_REG_MBCCTRL4 = 0x53, + MAX8997_REG_MBCCTRL5 = 0x54, + MAX8997_REG_MBCCTRL6 = 0x55, + MAX8997_REG_OTPCGHCVS = 0x56, + + MAX8997_REG_SAFEOUTCTRL = 0x5a, + + MAX8997_REG_LBCNFG1 = 0x5e, + MAX8997_REG_LBCNFG2 = 0x5f, + MAX8997_REG_BBCCTRL = 0x60, + + MAX8997_REG_FLASH1_CUR = 0x63, /* 0x63 ~ 0x6e for FLASH */ + MAX8997_REG_FLASH2_CUR = 0x64, + MAX8997_REG_MOVIE_CUR = 0x65, + MAX8997_REG_GSMB_CUR = 0x66, + MAX8997_REG_BOOST_CNTL = 0x67, + MAX8997_REG_LEN_CNTL = 0x68, + MAX8997_REG_FLASH_CNTL = 0x69, + MAX8997_REG_WDT_CNTL = 0x6a, + MAX8997_REG_MAXFLASH1 = 0x6b, + MAX8997_REG_MAXFLASH2 = 0x6c, + MAX8997_REG_FLASHSTATUS = 0x6d, + MAX8997_REG_FLASHSTATUSMASK = 0x6e, + + MAX8997_REG_GPIOCNTL1 = 0x70, + MAX8997_REG_GPIOCNTL2 = 0x71, + MAX8997_REG_GPIOCNTL3 = 0x72, + MAX8997_REG_GPIOCNTL4 = 0x73, + MAX8997_REG_GPIOCNTL5 = 0x74, + MAX8997_REG_GPIOCNTL6 = 0x75, + MAX8997_REG_GPIOCNTL7 = 0x76, + MAX8997_REG_GPIOCNTL8 = 0x77, + MAX8997_REG_GPIOCNTL9 = 0x78, + MAX8997_REG_GPIOCNTL10 = 0x79, + MAX8997_REG_GPIOCNTL11 = 0x7a, + MAX8997_REG_GPIOCNTL12 = 0x7b, + + MAX8997_REG_LDO1CONFIG = 0x80, + MAX8997_REG_LDO2CONFIG = 0x81, + MAX8997_REG_LDO3CONFIG = 0x82, + MAX8997_REG_LDO4CONFIG = 0x83, + MAX8997_REG_LDO5CONFIG = 0x84, + MAX8997_REG_LDO6CONFIG = 0x85, + MAX8997_REG_LDO7CONFIG = 0x86, + MAX8997_REG_LDO8CONFIG = 0x87, + MAX8997_REG_LDO9CONFIG = 0x88, + MAX8997_REG_LDO10CONFIG = 0x89, + MAX8997_REG_LDO11CONFIG = 0x8a, + MAX8997_REG_LDO12CONFIG = 0x8b, + MAX8997_REG_LDO13CONFIG = 0x8c, + MAX8997_REG_LDO14CONFIG = 0x8d, + MAX8997_REG_LDO15CONFIG = 0x8e, + MAX8997_REG_LDO16CONFIG = 0x8f, + MAX8997_REG_LDO17CONFIG = 0x90, + MAX8997_REG_LDO18CONFIG = 0x91, + MAX8997_REG_LDO21CONFIG = 0x92, + + MAX8997_REG_DVSOKTIMER1 = 0x97, + MAX8997_REG_DVSOKTIMER2 = 0x98, + MAX8997_REG_DVSOKTIMER4 = 0x99, + MAX8997_REG_DVSOKTIMER5 = 0x9a, + + PMIC_NUM_OF_REGS = 0x9b, +}; + +#define ENSAFEOUT1 (1 << 6) +#define ENSAFEOUT2 (1 << 7) + +#define MAX8997_I2C_ADDR (0xCC >> 1) +#define MAX8997_RTC_ADDR (0x0C >> 1) +#define MAX8997_MUIC_ADDR (0x4A >> 1) +#define MAX8997_FG_ADDR (0x6C >> 1) + +enum { + LDO_OFF = 0, + LDO_ON = 1, + + DIS_LDO = (0x00 << 6), + EN_LDO = (0x3 << 6), +}; + +#endif /* __MAX8997_PMIC_H_ */ -- cgit v1.3.1 From 04ce68eee39eeaebbea60394cc0bba2c6ea49c12 Mon Sep 17 00:00:00 2001 From: Łukasz Majewski Date: Thu, 29 Mar 2012 01:29:18 +0000 Subject: misc:pmic:samsung Convert TRATS target to use MAX8997 instead of MAX8998 TRATS target uses MAX8997 PMIC device instead of MAX8998. Signed-off-by: Lukasz Majewski Signed-off-by: Kyungmin Park Acked-by: Minkyu Kang --- board/samsung/trats/trats.c | 27 ++++++++++----------------- include/configs/trats.h | 2 +- 2 files changed, 11 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index aa4291df4ab..a7b4e4a4f99 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include "setup.h" @@ -216,26 +216,19 @@ static int s5pc210_phy_control(int on) return -1; if (on) { - ret |= pmic_set_output(p, - MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, - MAX8998_SAFEOUT1, LDO_ON); - ret |= pmic_set_output(p, MAX8998_REG_ONOFF1, - MAX8998_LDO3, LDO_ON); - ret |= pmic_set_output(p, MAX8998_REG_ONOFF2, - MAX8998_LDO8, LDO_ON); - + ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, + ENSAFEOUT1, LDO_ON); + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO); + ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO); } else { - ret |= pmic_set_output(p, MAX8998_REG_ONOFF2, - MAX8998_LDO8, LDO_OFF); - ret |= pmic_set_output(p, MAX8998_REG_ONOFF1, - MAX8998_LDO3, LDO_OFF); - ret |= pmic_set_output(p, - MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, - MAX8998_SAFEOUT1, LDO_OFF); + ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO); + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO); + ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, + ENSAFEOUT1, LDO_OFF); } if (ret) { - puts("MAX8998 LDO setting error!\n"); + puts("MAX8997 LDO setting error!\n"); return -1; } diff --git a/include/configs/trats.h b/include/configs/trats.h index 674bc7194d8..1bc2bb212e5 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -207,7 +207,7 @@ #define CONFIG_PMIC #define CONFIG_PMIC_I2C -#define CONFIG_PMIC_MAX8998 +#define CONFIG_PMIC_MAX8997 #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG -- cgit v1.3.1 From 559a05cc32a0162d4d2aebe6d3410e91f883a04d Mon Sep 17 00:00:00 2001 From: Donghwa Lee Date: Thu, 5 Apr 2012 19:36:15 +0000 Subject: LCD: add data structure for EXYNOS display driver Add vidinfo data structure for EXYNOS display driver Signed-off-by: Donghwa Lee Signed-off-by: Kyungmin Park Signed-off-by: Inki Dae Acked-by: Anatolij Gustschin --- include/lcd.h | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'include') diff --git a/include/lcd.h b/include/lcd.h index d95feeb791d..3d9ef167107 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -183,6 +183,70 @@ typedef struct vidinfo { u_long mmio; /* Memory mapped registers */ } vidinfo_t; +#elif defined(CONFIG_EXYNOS_FB) + +enum { + FIMD_RGB_INTERFACE = 1, + FIMD_CPU_INTERFACE = 2, +}; + +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 640) */ + ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_width; /* Width of display area in millimeters */ + ushort vl_height; /* Height of display area in millimeters */ + + /* LCD configuration register */ + u_char vl_freq; /* Frequency */ + u_char vl_clkp; /* Clock polarity */ + u_char vl_oep; /* Output Enable polarity */ + u_char vl_hsp; /* Horizontal Sync polarity */ + u_char vl_vsp; /* Vertical Sync polarity */ + u_char vl_dp; /* Data polarity */ + u_char vl_bpix; /* Bits per pixel */ + + /* Horizontal control register. Timing from data sheet */ + u_char vl_hspw; /* Horz sync pulse width */ + u_char vl_hfpd; /* Wait before of line */ + u_char vl_hbpd; /* Wait end of line */ + + /* Vertical control register. */ + u_char vl_vspw; /* Vertical sync pulse width */ + u_char vl_vfpd; /* Wait before of frame */ + u_char vl_vbpd; /* Wait end of frame */ + u_char vl_cmd_allow_len; /* Wait end of frame */ + + void (*cfg_gpio)(void); + void (*backlight_on)(unsigned int onoff); + void (*reset_lcd)(void); + void (*lcd_power_on)(void); + void (*cfg_ldo)(void); + void (*enable_ldo)(unsigned int onoff); + void (*mipi_power)(void); + void (*backlight_reset)(void); + + unsigned int win_id; + unsigned int init_delay; + unsigned int power_on_delay; + unsigned int reset_delay; + unsigned int interface_mode; + unsigned int mipi_enabled; + unsigned int cs_setup; + unsigned int wr_setup; + unsigned int wr_act; + unsigned int wr_hold; + + /* parent clock name(MPLL, EPLL or VPLL) */ + unsigned int pclk_name; + /* ratio value for source clock from parent clock. */ + unsigned int sclk_div; + + unsigned int dual_lcd_enabled; + +} vidinfo_t; + +void init_panel_info(vidinfo_t *vid); + #else typedef struct vidinfo { -- cgit v1.3.1 From 51b1cd6df7fbabe3f85ff3ba693f181deef44473 Mon Sep 17 00:00:00 2001 From: Donghwa Lee Date: Thu, 5 Apr 2012 19:36:27 +0000 Subject: EXYNOS: support TRATS board display function This patch support TRATS board configuration and display function. Signed-off-by: Donghwa Lee Signed-off-by: Kyungmin Park Signed-off-by: Inki Dae Signed-off-by: Minkyu Kang --- board/samsung/trats/trats.c | 146 ++++++++++++++++++++++++++++++++++++++++++++ include/configs/trats.h | 8 +++ 2 files changed, 154 insertions(+) (limited to 'include') diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index a7b4e4a4f99..f0775fd038f 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -2,6 +2,7 @@ * Copyright (C) 2011 Samsung Electronics * Heungjun Kim * Kyungmin Park + * Donghwa Lee * * See file CREDITS for list of people who contributed to this * project. @@ -23,11 +24,14 @@ */ #include +#include #include #include #include #include #include +#include +#include #include #include #include @@ -357,3 +361,145 @@ int board_early_init_f(void) return 0; } + +static void lcd_reset(void) +{ + struct exynos4_gpio_part2 *gpio2 = + (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); + + s5p_gpio_direction_output(&gpio2->y4, 5, 1); + udelay(10000); + s5p_gpio_direction_output(&gpio2->y4, 5, 0); + udelay(10000); + s5p_gpio_direction_output(&gpio2->y4, 5, 1); +} + +static int lcd_power(void) +{ + int ret = 0; + struct pmic *p = get_pmic(); + + if (pmic_probe(p)) + return 0; + + /* LDO15 voltage: 2.2v */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO); + /* LDO13 voltage: 3.0v */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO); + + if (ret) { + puts("MAX8997 LDO setting error!\n"); + return -1; + } + + return 0; +} + +static struct mipi_dsim_config dsim_config = { + .e_interface = DSIM_VIDEO, + .e_virtual_ch = DSIM_VIRTUAL_CH_0, + .e_pixel_format = DSIM_24BPP_888, + .e_burst_mode = DSIM_BURST_SYNC_EVENT, + .e_no_data_lane = DSIM_DATA_LANE_4, + .e_byte_clk = DSIM_PLL_OUT_DIV8, + .hfp = 1, + + .p = 3, + .m = 120, + .s = 1, + + /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ + .pll_stable_time = 500, + + /* escape clk : 10MHz */ + .esc_clk = 20 * 1000000, + + /* stop state holding counter after bta change count 0 ~ 0xfff */ + .stop_holding_cnt = 0x7ff, + /* bta timeout 0 ~ 0xff */ + .bta_timeout = 0xff, + /* lp rx timeout 0 ~ 0xffff */ + .rx_timeout = 0xffff, +}; + +static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = { + .lcd_panel_info = NULL, + .dsim_config = &dsim_config, +}; + +static struct mipi_dsim_lcd_device mipi_lcd_device = { + .name = "s6e8ax0", + .id = -1, + .bus_id = 0, + .platform_data = (void *)&s6e8ax0_platform_data, +}; + +static int mipi_power(void) +{ + int ret = 0; + struct pmic *p = get_pmic(); + + if (pmic_probe(p)) + return 0; + + /* LDO3 voltage: 1.1v */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO); + /* LDO4 voltage: 1.8v */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO); + + if (ret) { + puts("MAX8997 LDO setting error!\n"); + return -1; + } + + return 0; +} + +void init_panel_info(vidinfo_t *vid) +{ + vid->vl_freq = 60; + vid->vl_col = 720; + vid->vl_row = 1280; + vid->vl_width = 720; + vid->vl_height = 1280; + vid->vl_clkp = CONFIG_SYS_HIGH; + vid->vl_hsp = CONFIG_SYS_LOW; + vid->vl_vsp = CONFIG_SYS_LOW; + vid->vl_dp = CONFIG_SYS_LOW; + + vid->vl_bpix = 32; + vid->dual_lcd_enabled = 0; + + /* s6e8ax0 Panel */ + vid->vl_hspw = 5; + vid->vl_hbpd = 10; + vid->vl_hfpd = 10; + + vid->vl_vspw = 2; + vid->vl_vbpd = 1; + vid->vl_vfpd = 13; + vid->vl_cmd_allow_len = 0xf; + + vid->win_id = 3; + vid->cfg_gpio = NULL; + vid->backlight_on = NULL; + vid->lcd_power_on = NULL; /* lcd_power_on in mipi dsi driver */ + vid->reset_lcd = lcd_reset; + + vid->init_delay = 0; + vid->power_on_delay = 0; + vid->reset_delay = 0; + vid->interface_mode = FIMD_RGB_INTERFACE; + vid->mipi_enabled = 1; + + strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name); + s6e8ax0_platform_data.lcd_power = lcd_power; + s6e8ax0_platform_data.mipi_power = mipi_power; + s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl; + s6e8ax0_platform_data.lcd_panel_info = (void *)vid; + exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); + s6e8ax0_init(); + exynos_set_dsim_platform_data(&s6e8ax0_platform_data); + + setenv("lcdinfo", "lcd=s6e8ax0"); +} diff --git a/include/configs/trats.h b/include/configs/trats.h index 1bc2bb212e5..5f913ca9ac0 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -213,4 +213,12 @@ #define CONFIG_USB_GADGET_S3C_UDC_OTG #define CONFIG_USB_GADGET_DUALSPEED +/* LCD */ +#define CONFIG_EXYNOS_FB +#define CONFIG_LCD +#define CONFIG_FB_ADDR 0x52504000 +#define CONFIG_S6E8AX0 +#define CONFIG_EXYNOS_MIPI_DSIM +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1280 * 720 * 4) + #endif /* __CONFIG_H */ -- cgit v1.3.1 From 9f472e6540f5632ce27b779d841a006d1c1b3d55 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 22 Feb 2012 00:24:39 +0000 Subject: SATA: add driver for MX5 / MX6 SOCs This driver is part of Freescale's LTIB for MX5 / MX6. Signed-off-by: Stefano Babic Signed-off-by: Terry Lv CC: Fabio Estevam CC: Dirk Behme --- drivers/block/Makefile | 1 + drivers/block/dwc_ahsata.c | 969 +++++++++++++++++++++++++++++++++++++++++++++ drivers/block/dwc_ahsata.h | 335 ++++++++++++++++ include/ahci.h | 5 +- 4 files changed, 1308 insertions(+), 2 deletions(-) create mode 100644 drivers/block/dwc_ahsata.c create mode 100644 drivers/block/dwc_ahsata.h (limited to 'include') diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 98560ef76f3..b9c20475c26 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libblock.o COBJS-$(CONFIG_SCSI_AHCI) += ahci.o COBJS-$(CONFIG_ATA_PIIX) += ata_piix.o +COBJS-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o COBJS-$(CONFIG_IDE_FTIDE020) += ftide020.o COBJS-$(CONFIG_LIBATA) += libata.o diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c new file mode 100644 index 00000000000..2703d3dc84f --- /dev/null +++ b/drivers/block/dwc_ahsata.c @@ -0,0 +1,969 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Terry Lv + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + * + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include "dwc_ahsata.h" + +struct sata_port_regs { + u32 clb; + u32 clbu; + u32 fb; + u32 fbu; + u32 is; + u32 ie; + u32 cmd; + u32 res1[1]; + u32 tfd; + u32 sig; + u32 ssts; + u32 sctl; + u32 serr; + u32 sact; + u32 ci; + u32 sntf; + u32 res2[1]; + u32 dmacr; + u32 res3[1]; + u32 phycr; + u32 physr; +}; + +struct sata_host_regs { + u32 cap; + u32 ghc; + u32 is; + u32 pi; + u32 vs; + u32 ccc_ctl; + u32 ccc_ports; + u32 res1[2]; + u32 cap2; + u32 res2[30]; + u32 bistafr; + u32 bistcr; + u32 bistfctr; + u32 bistsr; + u32 bistdecr; + u32 res3[2]; + u32 oobr; + u32 res4[8]; + u32 timer1ms; + u32 res5[1]; + u32 gparam1r; + u32 gparam2r; + u32 pparamr; + u32 testr; + u32 versionr; + u32 idr; +}; + +#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024) +#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG) + +#define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0) + +static int is_ready; + +static inline u32 ahci_port_base(u32 base, u32 port) +{ + return base + 0x100 + (port * 0x80); +} + +static int waiting_for_cmd_completed(u8 *offset, + int timeout_msec, + u32 sign) +{ + int i; + u32 status; + + for (i = 0; + ((status = readl(offset)) & sign) && i < timeout_msec; + ++i) + mdelay(1); + + return (i < timeout_msec) ? 0 : -1; +} + +static int ahci_setup_oobr(struct ahci_probe_ent *probe_ent, + int clk) +{ + struct sata_host_regs *host_mmio = + (struct sata_host_regs *)probe_ent->mmio_base; + + writel(SATA_HOST_OOBR_WE, &(host_mmio->oobr)); + writel(0x02060b14, &(host_mmio->oobr)); + + return 0; +} + +static int ahci_host_init(struct ahci_probe_ent *probe_ent) +{ + u32 tmp, cap_save, num_ports; + int i, j, timeout = 1000; + struct sata_port_regs *port_mmio = NULL; + struct sata_host_regs *host_mmio = + (struct sata_host_regs *)probe_ent->mmio_base; + int clk = mxc_get_clock(MXC_SATA_CLK); + + cap_save = readl(&(host_mmio->cap)); + cap_save |= SATA_HOST_CAP_SSS; + + /* global controller reset */ + tmp = readl(&(host_mmio->ghc)); + if ((tmp & SATA_HOST_GHC_HR) == 0) + writel_with_flush(tmp | SATA_HOST_GHC_HR, &(host_mmio->ghc)); + + while ((readl(&(host_mmio->ghc)) & SATA_HOST_GHC_HR) + && --timeout) + ; + + if (timeout <= 0) { + debug("controller reset failed (0x%x)\n", tmp); + return -1; + } + + /* Set timer 1ms */ + writel(clk / 1000, &(host_mmio->timer1ms)); + + ahci_setup_oobr(probe_ent, 0); + + writel_with_flush(SATA_HOST_GHC_AE, &(host_mmio->ghc)); + writel(cap_save, &(host_mmio->cap)); + num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1; + writel_with_flush((1 << num_ports) - 1, + &(host_mmio->pi)); + + /* + * Determine which Ports are implemented by the DWC_ahsata, + * by reading the PI register. This bit map value aids the + * software to determine how many Ports are available and + * which Port registers need to be initialized. + */ + probe_ent->cap = readl(&(host_mmio->cap)); + probe_ent->port_map = readl(&(host_mmio->pi)); + + /* Determine how many command slots the HBA supports */ + probe_ent->n_ports = + (probe_ent->cap & SATA_HOST_CAP_NP_MASK) + 1; + + debug("cap 0x%x port_map 0x%x n_ports %d\n", + probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); + + for (i = 0; i < probe_ent->n_ports; i++) { + probe_ent->port[i].port_mmio = + ahci_port_base((u32)host_mmio, i); + port_mmio = + (struct sata_port_regs *)probe_ent->port[i].port_mmio; + + /* Ensure that the DWC_ahsata is in idle state */ + tmp = readl(&(port_mmio->cmd)); + + /* + * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR + * are all cleared, the Port is in an idle state. + */ + if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR | + SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) { + + /* + * System software places a Port into the idle state by + * clearing P#CMD.ST and waiting for P#CMD.CR to return + * 0 when read. + */ + tmp &= ~SATA_PORT_CMD_ST; + writel_with_flush(tmp, &(port_mmio->cmd)); + + /* + * spec says 500 msecs for each bit, so + * this is slightly incorrect. + */ + mdelay(500); + + timeout = 1000; + while ((readl(&(port_mmio->cmd)) & SATA_PORT_CMD_CR) + && --timeout) + ; + + if (timeout <= 0) { + debug("port reset failed (0x%x)\n", tmp); + return -1; + } + } + + /* Spin-up device */ + tmp = readl(&(port_mmio->cmd)); + writel((tmp | SATA_PORT_CMD_SUD), &(port_mmio->cmd)); + + /* Wait for spin-up to finish */ + timeout = 1000; + while (!(readl(&(port_mmio->cmd)) | SATA_PORT_CMD_SUD) + && --timeout) + ; + if (timeout <= 0) { + debug("Spin-Up can't finish!\n"); + return -1; + } + + for (j = 0; j < 100; ++j) { + mdelay(10); + tmp = readl(&(port_mmio->ssts)); + if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) || + ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1)) + break; + } + + /* Wait for COMINIT bit 26 (DIAG_X) in SERR */ + timeout = 1000; + while (!(readl(&(port_mmio->serr)) | SATA_PORT_SERR_DIAG_X) + && --timeout) + ; + if (timeout <= 0) { + debug("Can't find DIAG_X set!\n"); + return -1; + } + + /* + * For each implemented Port, clear the P#SERR + * register, by writing ones to each implemented\ + * bit location. + */ + tmp = readl(&(port_mmio->serr)); + debug("P#SERR 0x%x\n", + tmp); + writel(tmp, &(port_mmio->serr)); + + /* Ack any pending irq events for this port */ + tmp = readl(&(host_mmio->is)); + debug("IS 0x%x\n", tmp); + if (tmp) + writel(tmp, &(host_mmio->is)); + + writel(1 << i, &(host_mmio->is)); + + /* set irq mask (enables interrupts) */ + writel(DEF_PORT_IRQ, &(port_mmio->ie)); + + /* register linkup ports */ + tmp = readl(&(port_mmio->ssts)); + debug("Port %d status: 0x%x\n", i, tmp); + if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03) + probe_ent->link_port_map |= (0x01 << i); + } + + tmp = readl(&(host_mmio->ghc)); + debug("GHC 0x%x\n", tmp); + writel(tmp | SATA_HOST_GHC_IE, &(host_mmio->ghc)); + tmp = readl(&(host_mmio->ghc)); + debug("GHC 0x%x\n", tmp); + + return 0; +} + +static void ahci_print_info(struct ahci_probe_ent *probe_ent) +{ + struct sata_host_regs *host_mmio = + (struct sata_host_regs *)probe_ent->mmio_base; + u32 vers, cap, impl, speed; + const char *speed_s; + const char *scc_s; + + vers = readl(&(host_mmio->vs)); + cap = probe_ent->cap; + impl = probe_ent->port_map; + + speed = (cap & SATA_HOST_CAP_ISS_MASK) + >> SATA_HOST_CAP_ISS_OFFSET; + if (speed == 1) + speed_s = "1.5"; + else if (speed == 2) + speed_s = "3"; + else + speed_s = "?"; + + scc_s = "SATA"; + + printf("AHCI %02x%02x.%02x%02x " + "%u slots %u ports %s Gbps 0x%x impl %s mode\n", + (vers >> 24) & 0xff, + (vers >> 16) & 0xff, + (vers >> 8) & 0xff, + vers & 0xff, + ((cap >> 8) & 0x1f) + 1, + (cap & 0x1f) + 1, + speed_s, + impl, + scc_s); + + printf("flags: " + "%s%s%s%s%s%s" + "%s%s%s%s%s%s%s\n", + cap & (1 << 31) ? "64bit " : "", + cap & (1 << 30) ? "ncq " : "", + cap & (1 << 28) ? "ilck " : "", + cap & (1 << 27) ? "stag " : "", + cap & (1 << 26) ? "pm " : "", + cap & (1 << 25) ? "led " : "", + cap & (1 << 24) ? "clo " : "", + cap & (1 << 19) ? "nz " : "", + cap & (1 << 18) ? "only " : "", + cap & (1 << 17) ? "pmp " : "", + cap & (1 << 15) ? "pio " : "", + cap & (1 << 14) ? "slum " : "", + cap & (1 << 13) ? "part " : ""); +} + +static int ahci_init_one(int pdev) +{ + int rc; + struct ahci_probe_ent *probe_ent = NULL; + + probe_ent = malloc(sizeof(struct ahci_probe_ent)); + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); + probe_ent->dev = pdev; + + probe_ent->host_flags = ATA_FLAG_SATA + | ATA_FLAG_NO_LEGACY + | ATA_FLAG_MMIO + | ATA_FLAG_PIO_DMA + | ATA_FLAG_NO_ATAPI; + + probe_ent->mmio_base = CONFIG_DWC_AHSATA_BASE_ADDR; + + /* initialize adapter */ + rc = ahci_host_init(probe_ent); + if (rc) + goto err_out; + + ahci_print_info(probe_ent); + + /* Save the private struct to block device struct */ + sata_dev_desc[pdev].priv = (void *)probe_ent; + + return 0; + +err_out: + return rc; +} + +static int ahci_fill_sg(struct ahci_probe_ent *probe_ent, + u8 port, unsigned char *buf, int buf_len) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); + struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; + u32 sg_count, max_bytes; + int i; + + max_bytes = MAX_DATA_BYTES_PER_SG; + sg_count = ((buf_len - 1) / max_bytes) + 1; + if (sg_count > AHCI_MAX_SG) { + printf("Error:Too much sg!\n"); + return -1; + } + + for (i = 0; i < sg_count; i++) { + ahci_sg->addr = + cpu_to_le32((u32)buf + i * max_bytes); + ahci_sg->addr_hi = 0; + ahci_sg->flags_size = cpu_to_le32(0x3fffff & + (buf_len < max_bytes + ? (buf_len - 1) + : (max_bytes - 1))); + ahci_sg++; + buf_len -= max_bytes; + } + + return sg_count; +} + +static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) +{ + struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + + AHCI_CMD_SLOT_SZ * cmd_slot); + + memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); + cmd_hdr->opts = cpu_to_le32(opts); + cmd_hdr->status = 0; + cmd_hdr->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); + cmd_hdr->tbl_addr_hi = 0; +} + +#define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0) + +static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent, + u8 port, struct sata_fis_h2d *cfis, + u8 *buf, u32 buf_len, s32 is_write) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); + struct sata_port_regs *port_mmio = + (struct sata_port_regs *)pp->port_mmio; + u32 opts; + int sg_count = 0, cmd_slot = 0; + + cmd_slot = AHCI_GET_CMD_SLOT(readl(&(port_mmio->ci))); + if (32 == cmd_slot) { + printf("Can't find empty command slot!\n"); + return 0; + } + + /* Check xfer length */ + if (buf_len > MAX_BYTES_PER_TRANS) { + printf("Max transfer length is %dB\n\r", + MAX_BYTES_PER_TRANS); + return 0; + } + + memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d)); + if (buf && buf_len) + sg_count = ahci_fill_sg(probe_ent, port, buf, buf_len); + opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16); + if (is_write) + opts |= 0x40; + ahci_fill_cmd_slot(pp, cmd_slot, opts); + + writel_with_flush(1 << cmd_slot, &(port_mmio->ci)); + + if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci), + 10000, 0x1 << cmd_slot)) { + printf("timeout exit!\n"); + return -1; + } + debug("ahci_exec_ata_cmd: %d byte transferred.\n", + pp->cmd_slot->status); + + return buf_len; +} + +static void ahci_set_feature(u8 dev, u8 port) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + struct sata_fis_h2d h2d, *cfis = &h2d; + + memset(cfis, 0, sizeof(struct sata_fis_h2d)); + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis->pm_port_c = 1 << 7; + cfis->command = ATA_CMD_SET_FEATURES; + cfis->features = SETFEATURES_XFER; + cfis->sector_count = ffs(probe_ent->udma_mask + 1) + 0x3e; + + ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, READ_CMD); +} + +static int ahci_port_start(struct ahci_probe_ent *probe_ent, + u8 port) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); + struct sata_port_regs *port_mmio = + (struct sata_port_regs *)pp->port_mmio; + u32 port_status; + u32 mem; + int timeout = 10000000; + + debug("Enter start port: %d\n", port); + port_status = readl(&(port_mmio->ssts)); + debug("Port %d status: %x\n", port, port_status); + if ((port_status & 0xf) != 0x03) { + printf("No Link on this port!\n"); + return -1; + } + + mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); + if (!mem) { + free(pp); + printf("No mem for table!\n"); + return -ENOMEM; + } + + mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */ + memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); + + /* + * First item in chunk of DMA memory: 32-slot command table, + * 32 bytes each in size + */ + pp->cmd_slot = (struct ahci_cmd_hdr *)mem; + debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot); + mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS); + + /* + * Second item: Received-FIS area, 256-Byte aligned + */ + pp->rx_fis = mem; + mem += AHCI_RX_FIS_SZ; + + /* + * Third item: data area for storing a single command + * and its scatter-gather table + */ + pp->cmd_tbl = mem; + debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); + + mem += AHCI_CMD_TBL_HDR; + + writel_with_flush(0x00004444, &(port_mmio->dmacr)); + pp->cmd_tbl_sg = (struct ahci_sg *)mem; + writel_with_flush((u32)pp->cmd_slot, &(port_mmio->clb)); + writel_with_flush(pp->rx_fis, &(port_mmio->fb)); + + /* Enable FRE */ + writel_with_flush((SATA_PORT_CMD_FRE | readl(&(port_mmio->cmd))), + &(port_mmio->cmd)); + + /* Wait device ready */ + while ((readl(&(port_mmio->tfd)) & (SATA_PORT_TFD_STS_ERR | + SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY)) + && --timeout) + ; + if (timeout <= 0) { + debug("Device not ready for BSY, DRQ and" + "ERR in TFD!\n"); + return -1; + } + + writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | + PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | + PORT_CMD_START, &(port_mmio->cmd)); + + debug("Exit start port %d\n", port); + + return 0; +} + +int init_sata(int dev) +{ + int i; + u32 linkmap; + struct ahci_probe_ent *probe_ent = NULL; + + if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { + printf("The sata index %d is out of ranges\n\r", dev); + return -1; + } + + ahci_init_one(dev); + + probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + linkmap = probe_ent->link_port_map; + + if (0 == linkmap) { + printf("No port device detected!\n"); + return 1; + } + + for (i = 0; i < probe_ent->n_ports; i++) { + if ((linkmap >> i) && ((linkmap >> i) & 0x01)) { + if (ahci_port_start(probe_ent, (u8)i)) { + printf("Can not start port %d\n", i); + return 1; + } + probe_ent->hard_port_no = i; + break; + } + } + + return 0; +} + +static void dwc_ahsata_print_info(int dev) +{ + block_dev_desc_t *pdev = &(sata_dev_desc[dev]); + + printf("SATA Device Info:\n\r"); +#ifdef CONFIG_SYS_64BIT_LBA + printf("S/N: %s\n\rProduct model number: %s\n\r" + "Firmware version: %s\n\rCapacity: %lld sectors\n\r", + pdev->product, pdev->vendor, pdev->revision, pdev->lba); +#else + printf("S/N: %s\n\rProduct model number: %s\n\r" + "Firmware version: %s\n\rCapacity: %ld sectors\n\r", + pdev->product, pdev->vendor, pdev->revision, pdev->lba); +#endif +} + +static void dwc_ahsata_identify(int dev, u16 *id) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + struct sata_fis_h2d h2d, *cfis = &h2d; + u8 port = probe_ent->hard_port_no; + + memset(cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis->pm_port_c = 0x80; /* is command */ + cfis->command = ATA_CMD_ID_ATA; + + ahci_exec_ata_cmd(probe_ent, port, cfis, + (u8 *)id, ATA_ID_WORDS * 2, READ_CMD); + ata_swap_buf_le16(id, ATA_ID_WORDS); +} + +static void dwc_ahsata_xfer_mode(int dev, u16 *id) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + + probe_ent->pio_mask = id[ATA_ID_PIO_MODES]; + probe_ent->udma_mask = id[ATA_ID_UDMA_MODES]; + debug("pio %04x, udma %04x\n\r", + probe_ent->pio_mask, probe_ent->udma_mask); +} + +static u32 dwc_ahsata_rw_cmd(int dev, u32 start, u32 blkcnt, + u8 *buffer, int is_write) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + struct sata_fis_h2d h2d, *cfis = &h2d; + u8 port = probe_ent->hard_port_no; + u32 block; + + block = start; + + memset(cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis->pm_port_c = 0x80; /* is command */ + cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; + cfis->device = ATA_LBA; + + cfis->device |= (block >> 24) & 0xf; + cfis->lba_high = (block >> 16) & 0xff; + cfis->lba_mid = (block >> 8) & 0xff; + cfis->lba_low = block & 0xff; + cfis->sector_count = (u8)(blkcnt & 0xff); + + if (ahci_exec_ata_cmd(probe_ent, port, cfis, + buffer, ATA_SECT_SIZE * blkcnt, is_write) > 0) + return blkcnt; + else + return 0; +} + +void dwc_ahsata_flush_cache(int dev) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + struct sata_fis_h2d h2d, *cfis = &h2d; + u8 port = probe_ent->hard_port_no; + + memset(cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis->pm_port_c = 0x80; /* is command */ + cfis->command = ATA_CMD_FLUSH; + + ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0); +} + +static u32 dwc_ahsata_rw_cmd_ext(int dev, u32 start, lbaint_t blkcnt, + u8 *buffer, int is_write) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + struct sata_fis_h2d h2d, *cfis = &h2d; + u8 port = probe_ent->hard_port_no; + u64 block; + + block = (u64)start; + + memset(cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis->pm_port_c = 0x80; /* is command */ + + cfis->command = (is_write) ? ATA_CMD_WRITE_EXT + : ATA_CMD_READ_EXT; + + cfis->lba_high_exp = (block >> 40) & 0xff; + cfis->lba_mid_exp = (block >> 32) & 0xff; + cfis->lba_low_exp = (block >> 24) & 0xff; + cfis->lba_high = (block >> 16) & 0xff; + cfis->lba_mid = (block >> 8) & 0xff; + cfis->lba_low = block & 0xff; + cfis->device = ATA_LBA; + cfis->sector_count_exp = (blkcnt >> 8) & 0xff; + cfis->sector_count = blkcnt & 0xff; + + if (ahci_exec_ata_cmd(probe_ent, port, cfis, buffer, + ATA_SECT_SIZE * blkcnt, is_write) > 0) + return blkcnt; + else + return 0; +} + +u32 dwc_ahsata_rw_ncq_cmd(int dev, u32 start, lbaint_t blkcnt, + u8 *buffer, int is_write) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + struct sata_fis_h2d h2d, *cfis = &h2d; + u8 port = probe_ent->hard_port_no; + u64 block; + + if (sata_dev_desc[dev].lba48 != 1) { + printf("execute FPDMA command on non-LBA48 hard disk\n\r"); + return -1; + } + + block = (u64)start; + + memset(cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis->pm_port_c = 0x80; /* is command */ + + cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE + : ATA_CMD_FPDMA_READ; + + cfis->lba_high_exp = (block >> 40) & 0xff; + cfis->lba_mid_exp = (block >> 32) & 0xff; + cfis->lba_low_exp = (block >> 24) & 0xff; + cfis->lba_high = (block >> 16) & 0xff; + cfis->lba_mid = (block >> 8) & 0xff; + cfis->lba_low = block & 0xff; + + cfis->device = ATA_LBA; + cfis->features_exp = (blkcnt >> 8) & 0xff; + cfis->features = blkcnt & 0xff; + + /* Use the latest queue */ + ahci_exec_ata_cmd(probe_ent, port, cfis, + buffer, ATA_SECT_SIZE * blkcnt, is_write); + + return blkcnt; +} + +void dwc_ahsata_flush_cache_ext(int dev) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + struct sata_fis_h2d h2d, *cfis = &h2d; + u8 port = probe_ent->hard_port_no; + + memset(cfis, 0, sizeof(struct sata_fis_h2d)); + + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; + cfis->pm_port_c = 0x80; /* is command */ + cfis->command = ATA_CMD_FLUSH_EXT; + + ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0); +} + +static void dwc_ahsata_init_wcache(int dev, u16 *id) +{ + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + + if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id)) + probe_ent->flags |= SATA_FLAG_WCACHE; + if (ata_id_has_flush(id)) + probe_ent->flags |= SATA_FLAG_FLUSH; + if (ata_id_has_flush_ext(id)) + probe_ent->flags |= SATA_FLAG_FLUSH_EXT; +} + +u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt, + void *buffer, int is_write) +{ + u32 start, blks; + u8 *addr; + int max_blks; + + start = blknr; + blks = blkcnt; + addr = (u8 *)buffer; + + max_blks = ATA_MAX_SECTORS_LBA48; + + do { + if (blks > max_blks) { + if (max_blks != dwc_ahsata_rw_cmd_ext(dev, start, + max_blks, addr, is_write)) + return 0; + start += max_blks; + blks -= max_blks; + addr += ATA_SECT_SIZE * max_blks; + } else { + if (blks != dwc_ahsata_rw_cmd_ext(dev, start, + blks, addr, is_write)) + return 0; + start += blks; + blks = 0; + addr += ATA_SECT_SIZE * blks; + } + } while (blks != 0); + + return blkcnt; +} + +u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt, + void *buffer, int is_write) +{ + u32 start, blks; + u8 *addr; + int max_blks; + + start = blknr; + blks = blkcnt; + addr = (u8 *)buffer; + + max_blks = ATA_MAX_SECTORS; + do { + if (blks > max_blks) { + if (max_blks != dwc_ahsata_rw_cmd(dev, start, + max_blks, addr, is_write)) + return 0; + start += max_blks; + blks -= max_blks; + addr += ATA_SECT_SIZE * max_blks; + } else { + if (blks != dwc_ahsata_rw_cmd(dev, start, + blks, addr, is_write)) + return 0; + start += blks; + blks = 0; + addr += ATA_SECT_SIZE * blks; + } + } while (blks != 0); + + return blkcnt; +} + +/* + * SATA interface between low level driver and command layer + */ +ulong sata_read(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer) +{ + u32 rc; + + if (sata_dev_desc[dev].lba48) + rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, + buffer, READ_CMD); + else + rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, + buffer, READ_CMD); + return rc; +} + +ulong sata_write(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer) +{ + u32 rc; + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + u32 flags = probe_ent->flags; + + if (sata_dev_desc[dev].lba48) { + rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, + buffer, WRITE_CMD); + if ((flags & SATA_FLAG_WCACHE) && + (flags & SATA_FLAG_FLUSH_EXT)) + dwc_ahsata_flush_cache_ext(dev); + } else { + rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, + buffer, WRITE_CMD); + if ((flags & SATA_FLAG_WCACHE) && + (flags & SATA_FLAG_FLUSH)) + dwc_ahsata_flush_cache(dev); + } + return rc; +} + +int scan_sata(int dev) +{ + u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 }; + u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 }; + u8 product[ATA_ID_PROD_LEN + 1] = { 0 }; + u16 *id; + u64 n_sectors; + struct ahci_probe_ent *probe_ent = + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + u8 port = probe_ent->hard_port_no; + block_dev_desc_t *pdev = &(sata_dev_desc[dev]); + + id = (u16 *)malloc(ATA_ID_WORDS * 2); + if (!id) { + printf("id malloc failed\n\r"); + return -1; + } + + /* Identify device to get information */ + dwc_ahsata_identify(dev, id); + + /* Serial number */ + ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); + memcpy(pdev->product, serial, sizeof(serial)); + + /* Firmware version */ + ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); + memcpy(pdev->revision, firmware, sizeof(firmware)); + + /* Product model */ + ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); + memcpy(pdev->vendor, product, sizeof(product)); + + /* Totoal sectors */ + n_sectors = ata_id_n_sectors(id); + pdev->lba = (u32)n_sectors; + + pdev->type = DEV_TYPE_HARDDISK; + pdev->blksz = ATA_SECT_SIZE; + pdev->lun = 0 ; + + /* Check if support LBA48 */ + if (ata_id_has_lba48(id)) { + pdev->lba48 = 1; + debug("Device support LBA48\n\r"); + } + + /* Get the NCQ queue depth from device */ + probe_ent->flags &= (~SATA_FLAG_Q_DEP_MASK); + probe_ent->flags |= ata_id_queue_depth(id); + + /* Get the xfer mode from device */ + dwc_ahsata_xfer_mode(dev, id); + + /* Get the write cache status from device */ + dwc_ahsata_init_wcache(dev, id); + + /* Set the xfer mode to highest speed */ + ahci_set_feature(dev, port); + + free((void *)id); + + dwc_ahsata_print_info(dev); + + is_ready = 1; + + return 0; +} diff --git a/drivers/block/dwc_ahsata.h b/drivers/block/dwc_ahsata.h new file mode 100644 index 00000000000..84860ea4925 --- /dev/null +++ b/drivers/block/dwc_ahsata.h @@ -0,0 +1,335 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Terry Lv + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSL_SATA_H__ +#define __FSL_SATA_H__ + +#define DWC_AHSATA_MAX_CMD_SLOTS 32 + +/* Max host controller numbers */ +#define SATA_HC_MAX_NUM 4 +/* Max command queue depth per host controller */ +#define DWC_AHSATA_HC_MAX_CMD 32 +/* Max port number per host controller */ +#define SATA_HC_MAX_PORT 16 + +/* Generic Host Register */ + +/* HBA Capabilities Register */ +#define SATA_HOST_CAP_S64A 0x80000000 +#define SATA_HOST_CAP_SNCQ 0x40000000 +#define SATA_HOST_CAP_SSNTF 0x20000000 +#define SATA_HOST_CAP_SMPS 0x10000000 +#define SATA_HOST_CAP_SSS 0x08000000 +#define SATA_HOST_CAP_SALP 0x04000000 +#define SATA_HOST_CAP_SAL 0x02000000 +#define SATA_HOST_CAP_SCLO 0x01000000 +#define SATA_HOST_CAP_ISS_MASK 0x00f00000 +#define SATA_HOST_CAP_ISS_OFFSET 20 +#define SATA_HOST_CAP_SNZO 0x00080000 +#define SATA_HOST_CAP_SAM 0x00040000 +#define SATA_HOST_CAP_SPM 0x00020000 +#define SATA_HOST_CAP_PMD 0x00008000 +#define SATA_HOST_CAP_SSC 0x00004000 +#define SATA_HOST_CAP_PSC 0x00002000 +#define SATA_HOST_CAP_NCS 0x00001f00 +#define SATA_HOST_CAP_CCCS 0x00000080 +#define SATA_HOST_CAP_EMS 0x00000040 +#define SATA_HOST_CAP_SXS 0x00000020 +#define SATA_HOST_CAP_NP_MASK 0x0000001f + +/* Global HBA Control Register */ +#define SATA_HOST_GHC_AE 0x80000000 +#define SATA_HOST_GHC_IE 0x00000002 +#define SATA_HOST_GHC_HR 0x00000001 + +/* Interrupt Status Register */ + +/* Ports Implemented Register */ + +/* AHCI Version Register */ +#define SATA_HOST_VS_MJR_MASK 0xffff0000 +#define SATA_HOST_VS_MJR_OFFSET 16 +#define SATA_HOST_VS_MJR_MNR 0x0000ffff + +/* Command Completion Coalescing Control */ +#define SATA_HOST_CCC_CTL_TV_MASK 0xffff0000 +#define SATA_HOST_CCC_CTL_TV_OFFSET 16 +#define SATA_HOST_CCC_CTL_CC_MASK 0x0000ff00 +#define SATA_HOST_CCC_CTL_CC_OFFSET 8 +#define SATA_HOST_CCC_CTL_INT_MASK 0x000000f8 +#define SATA_HOST_CCC_CTL_INT_OFFSET 3 +#define SATA_HOST_CCC_CTL_EN 0x00000001 + +/* Command Completion Coalescing Ports */ + +/* HBA Capabilities Extended Register */ +#define SATA_HOST_CAP2_APST 0x00000004 + +/* BIST Activate FIS Register */ +#define SATA_HOST_BISTAFR_NCP_MASK 0x0000ff00 +#define SATA_HOST_BISTAFR_NCP_OFFSET 8 +#define SATA_HOST_BISTAFR_PD_MASK 0x000000ff +#define SATA_HOST_BISTAFR_PD_OFFSET 0 + +/* BIST Control Register */ +#define SATA_HOST_BISTCR_FERLB 0x00100000 +#define SATA_HOST_BISTCR_TXO 0x00040000 +#define SATA_HOST_BISTCR_CNTCLR 0x00020000 +#define SATA_HOST_BISTCR_NEALB 0x00010000 +#define SATA_HOST_BISTCR_LLC_MASK 0x00000700 +#define SATA_HOST_BISTCR_LLC_OFFSET 8 +#define SATA_HOST_BISTCR_ERREN 0x00000040 +#define SATA_HOST_BISTCR_FLIP 0x00000020 +#define SATA_HOST_BISTCR_PV 0x00000010 +#define SATA_HOST_BISTCR_PATTERN_MASK 0x0000000f +#define SATA_HOST_BISTCR_PATTERN_OFFSET 0 + +/* BIST FIS Count Register */ + +/* BIST Status Register */ +#define SATA_HOST_BISTSR_FRAMERR_MASK 0x0000ffff +#define SATA_HOST_BISTSR_FRAMERR_OFFSET 0 +#define SATA_HOST_BISTSR_BRSTERR_MASK 0x00ff0000 +#define SATA_HOST_BISTSR_BRSTERR_OFFSET 16 + +/* BIST DWORD Error Count Register */ + +/* OOB Register*/ +#define SATA_HOST_OOBR_WE 0x80000000 +#define SATA_HOST_OOBR_cwMin_MASK 0x7f000000 +#define SATA_HOST_OOBR_cwMAX_MASK 0x00ff0000 +#define SATA_HOST_OOBR_ciMin_MASK 0x0000ff00 +#define SATA_HOST_OOBR_ciMax_MASK 0x000000ff + +/* Timer 1-ms Register */ + +/* Global Parameter 1 Register */ +#define SATA_HOST_GPARAM1R_ALIGN_M 0x80000000 +#define SATA_HOST_GPARAM1R_RX_BUFFER 0x40000000 +#define SATA_HOST_GPARAM1R_PHY_DATA_MASK 0x30000000 +#define SATA_HOST_GPARAM1R_PHY_RST 0x08000000 +#define SATA_HOST_GPARAM1R_PHY_CTRL_MASK 0x07e00000 +#define SATA_HOST_GPARAM1R_PHY_STAT_MASK 0x001f8000 +#define SATA_HOST_GPARAM1R_LATCH_M 0x00004000 +#define SATA_HOST_GPARAM1R_BIST_M 0x00002000 +#define SATA_HOST_GPARAM1R_PHY_TYPE 0x00001000 +#define SATA_HOST_GPARAM1R_RETURN_ERR 0x00000400 +#define SATA_HOST_GPARAM1R_AHB_ENDIAN_MASK 0x00000300 +#define SATA_HOST_GPARAM1R_S_HADDR 0X00000080 +#define SATA_HOST_GPARAM1R_M_HADDR 0X00000040 + +/* Global Parameter 2 Register */ +#define SATA_HOST_GPARAM2R_DEV_CP 0x00004000 +#define SATA_HOST_GPARAM2R_DEV_MP 0x00002000 +#define SATA_HOST_GPARAM2R_DEV_ENCODE_M 0x00001000 +#define SATA_HOST_GPARAM2R_RXOOB_CLK_M 0x00000800 +#define SATA_HOST_GPARAM2R_RXOOB_M 0x00000400 +#define SATA_HOST_GPARAM2R_TX_OOB_M 0x00000200 +#define SATA_HOST_GPARAM2R_RXOOB_CLK_MASK 0x000001ff + +/* Port Parameter Register */ +#define SATA_HOST_PPARAMR_TX_MEM_M 0x00000200 +#define SATA_HOST_PPARAMR_TX_MEM_S 0x00000100 +#define SATA_HOST_PPARAMR_RX_MEM_M 0x00000080 +#define SATA_HOST_PPARAMR_RX_MEM_S 0x00000040 +#define SATA_HOST_PPARAMR_TXFIFO_DEPTH_MASK 0x00000038 +#define SATA_HOST_PPARAMR_RXFIFO_DEPTH_MASK 0x00000007 + +/* Test Register */ +#define SATA_HOST_TESTR_PSEL_MASK 0x00070000 +#define SATA_HOST_TESTR_TEST_IF 0x00000001 + +/* Port Register Descriptions */ +/* Port# Command List Base Address Register */ +#define SATA_PORT_CLB_CLB_MASK 0xfffffc00 + +/* Port# Command List Base Address Upper 32-Bits Register */ + +/* Port# FIS Base Address Register */ +#define SATA_PORT_FB_FB_MASK 0xfffffff0 + +/* Port# FIS Base Address Upper 32-Bits Register */ + +/* Port# Interrupt Status Register */ +#define SATA_PORT_IS_CPDS 0x80000000 +#define SATA_PORT_IS_TFES 0x40000000 +#define SATA_PORT_IS_HBFS 0x20000000 +#define SATA_PORT_IS_HBDS 0x10000000 +#define SATA_PORT_IS_IFS 0x08000000 +#define SATA_PORT_IS_INFS 0x04000000 +#define SATA_PORT_IS_OFS 0x01000000 +#define SATA_PORT_IS_IPMS 0x00800000 +#define SATA_PORT_IS_PRCS 0x00400000 +#define SATA_PORT_IS_DMPS 0x00000080 +#define SATA_PORT_IS_PCS 0x00000040 +#define SATA_PORT_IS_DPS 0x00000020 +#define SATA_PORT_IS_UFS 0x00000010 +#define SATA_PORT_IS_SDBS 0x00000008 +#define SATA_PORT_IS_DSS 0x00000004 +#define SATA_PORT_IS_PSS 0x00000002 +#define SATA_PORT_IS_DHRS 0x00000001 + +/* Port# Interrupt Enable Register */ +#define SATA_PORT_IE_CPDE 0x80000000 +#define SATA_PORT_IE_TFEE 0x40000000 +#define SATA_PORT_IE_HBFE 0x20000000 +#define SATA_PORT_IE_HBDE 0x10000000 +#define SATA_PORT_IE_IFE 0x08000000 +#define SATA_PORT_IE_INFE 0x04000000 +#define SATA_PORT_IE_OFE 0x01000000 +#define SATA_PORT_IE_IPME 0x00800000 +#define SATA_PORT_IE_PRCE 0x00400000 +#define SATA_PORT_IE_DMPE 0x00000080 +#define SATA_PORT_IE_PCE 0x00000040 +#define SATA_PORT_IE_DPE 0x00000020 +#define SATA_PORT_IE_UFE 0x00000010 +#define SATA_PORT_IE_SDBE 0x00000008 +#define SATA_PORT_IE_DSE 0x00000004 +#define SATA_PORT_IE_PSE 0x00000002 +#define SATA_PORT_IE_DHRE 0x00000001 + +/* Port# Command Register */ +#define SATA_PORT_CMD_ICC_MASK 0xf0000000 +#define SATA_PORT_CMD_ASP 0x08000000 +#define SATA_PORT_CMD_ALPE 0x04000000 +#define SATA_PORT_CMD_DLAE 0x02000000 +#define SATA_PORT_CMD_ATAPI 0x01000000 +#define SATA_PORT_CMD_APSTE 0x00800000 +#define SATA_PORT_CMD_ESP 0x00200000 +#define SATA_PORT_CMD_CPD 0x00100000 +#define SATA_PORT_CMD_MPSP 0x00080000 +#define SATA_PORT_CMD_HPCP 0x00040000 +#define SATA_PORT_CMD_PMA 0x00020000 +#define SATA_PORT_CMD_CPS 0x00010000 +#define SATA_PORT_CMD_CR 0x00008000 +#define SATA_PORT_CMD_FR 0x00004000 +#define SATA_PORT_CMD_MPSS 0x00002000 +#define SATA_PORT_CMD_CCS_MASK 0x00001f00 +#define SATA_PORT_CMD_FRE 0x00000010 +#define SATA_PORT_CMD_CLO 0x00000008 +#define SATA_PORT_CMD_POD 0x00000004 +#define SATA_PORT_CMD_SUD 0x00000002 +#define SATA_PORT_CMD_ST 0x00000001 + +/* Port# Task File Data Register */ +#define SATA_PORT_TFD_ERR_MASK 0x0000ff00 +#define SATA_PORT_TFD_STS_MASK 0x000000ff +#define SATA_PORT_TFD_STS_ERR 0x00000001 +#define SATA_PORT_TFD_STS_DRQ 0x00000008 +#define SATA_PORT_TFD_STS_BSY 0x00000080 + +/* Port# Signature Register */ + +/* Port# Serial ATA Status {SStatus} Register */ +#define SATA_PORT_SSTS_IPM_MASK 0x00000f00 +#define SATA_PORT_SSTS_SPD_MASK 0x000000f0 +#define SATA_PORT_SSTS_DET_MASK 0x0000000f + +/* Port# Serial ATA Control {SControl} Register */ +#define SATA_PORT_SCTL_IPM_MASK 0x00000f00 +#define SATA_PORT_SCTL_SPD_MASK 0x000000f0 +#define SATA_PORT_SCTL_DET_MASK 0x0000000f + +/* Port# Serial ATA Error {SError} Register */ +#define SATA_PORT_SERR_DIAG_X 0x04000000 +#define SATA_PORT_SERR_DIAG_F 0x02000000 +#define SATA_PORT_SERR_DIAG_T 0x01000000 +#define SATA_PORT_SERR_DIAG_S 0x00800000 +#define SATA_PORT_SERR_DIAG_H 0x00400000 +#define SATA_PORT_SERR_DIAG_C 0x00200000 +#define SATA_PORT_SERR_DIAG_D 0x00100000 +#define SATA_PORT_SERR_DIAG_B 0x00080000 +#define SATA_PORT_SERR_DIAG_W 0x00040000 +#define SATA_PORT_SERR_DIAG_I 0x00020000 +#define SATA_PORT_SERR_DIAG_N 0x00010000 +#define SATA_PORT_SERR_ERR_E 0x00000800 +#define SATA_PORT_SERR_ERR_P 0x00000400 +#define SATA_PORT_SERR_ERR_C 0x00000200 +#define SATA_PORT_SERR_ERR_T 0x00000100 +#define SATA_PORT_SERR_ERR_M 0x00000002 +#define SATA_PORT_SERR_ERR_I 0x00000001 + +/* Port# Serial ATA Active {SActive} Register */ + +/* Port# Command Issue Register */ + +/* Port# Serial ATA Notification Register */ + +/* Port# DMA Control Register */ +#define SATA_PORT_DMACR_RXABL_MASK 0x0000f000 +#define SATA_PORT_DMACR_TXABL_MASK 0x00000f00 +#define SATA_PORT_DMACR_RXTS_MASK 0x000000f0 +#define SATA_PORT_DMACR_TXTS_MASK 0x0000000f + +/* Port# PHY Control Register */ + +/* Port# PHY Status Register */ + +#define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry) + +/* DW0 +*/ +#define CMD_HDR_DI_CFL_MASK 0x0000001f +#define CMD_HDR_DI_CFL_OFFSET 0 +#define CMD_HDR_DI_A 0x00000020 +#define CMD_HDR_DI_W 0x00000040 +#define CMD_HDR_DI_P 0x00000080 +#define CMD_HDR_DI_R 0x00000100 +#define CMD_HDR_DI_B 0x00000200 +#define CMD_HDR_DI_C 0x00000400 +#define CMD_HDR_DI_PMP_MASK 0x0000f000 +#define CMD_HDR_DI_PMP_OFFSET 12 +#define CMD_HDR_DI_PRDTL 0xffff0000 +#define CMD_HDR_DI_PRDTL_OFFSET 16 + +/* prde_fis_len +*/ +#define CMD_HDR_PRD_ENTRY_SHIFT 16 +#define CMD_HDR_PRD_ENTRY_MASK 0x003f0000 +#define CMD_HDR_FIS_LEN_SHIFT 2 + +/* attribute +*/ +#define CMD_HDR_ATTR_RES 0x00000800 /* Reserved bit, should be 1 */ +#define CMD_HDR_ATTR_VBIST 0x00000400 /* Vendor BIST */ +/* Snoop enable for all descriptor */ +#define CMD_HDR_ATTR_SNOOP 0x00000200 +#define CMD_HDR_ATTR_FPDMA 0x00000100 /* FPDMA queued command */ +#define CMD_HDR_ATTR_RESET 0x00000080 /* Reset - a SRST or device reset */ +/* BIST - require the host to enter BIST mode */ +#define CMD_HDR_ATTR_BIST 0x00000040 +#define CMD_HDR_ATTR_ATAPI 0x00000020 /* ATAPI command */ +#define CMD_HDR_ATTR_TAG 0x0000001f /* TAG mask */ + +#define FLAGS_DMA 0x00000000 +#define FLAGS_FPDMA 0x00000001 + +#define SATA_FLAG_Q_DEP_MASK 0x0000000f +#define SATA_FLAG_WCACHE 0x00000100 +#define SATA_FLAG_FLUSH 0x00000200 +#define SATA_FLAG_FLUSH_EXT 0x00000400 + +#define READ_CMD 0 +#define WRITE_CMD 1 + +extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; + +#endif /* __FSL_SATA_H__ */ diff --git a/include/ahci.h b/include/ahci.h index 465ea7fcbbb..c4fb9e79a55 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -30,12 +30,13 @@ #define AHCI_PCI_BAR 0x24 #define AHCI_MAX_SG 56 /* hardware max is 64K */ #define AHCI_CMD_SLOT_SZ 32 +#define AHCI_MAX_CMD_SLOT 32 #define AHCI_RX_FIS_SZ 256 #define AHCI_CMD_TBL_HDR 0x80 #define AHCI_CMD_TBL_CDB 0x40 #define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) -#define AHCI_PORT_PRIV_DMA_SZ AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ \ - + AHCI_RX_FIS_SZ +#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \ + AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ) #define AHCI_CMD_ATAPI (1 << 5) #define AHCI_CMD_WRITE (1 << 6) #define AHCI_CMD_PREFETCH (1 << 7) -- cgit v1.3.1 From 79656d27b3e2eb4c9ceb273cc1efd33e51a9951a Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 22 Feb 2012 00:24:40 +0000 Subject: MX53: Add support to ESG ima3 board The ESG ima3-mx53 board is based on the Freescale i.MX53 SOC. It boots from NOR (128 MB) and supports Ethernet (FEC), SATA. Signed-off-by: Stefano Babic --- board/esg/ima3-mx53/Makefile | 41 ++++++ board/esg/ima3-mx53/ima3-mx53.c | 302 +++++++++++++++++++++++++++++++++++++++ board/esg/ima3-mx53/imximage.cfg | 108 ++++++++++++++ boards.cfg | 1 + include/configs/ima3-mx53.h | 269 ++++++++++++++++++++++++++++++++++ 5 files changed, 721 insertions(+) create mode 100644 board/esg/ima3-mx53/Makefile create mode 100644 board/esg/ima3-mx53/ima3-mx53.c create mode 100644 board/esg/ima3-mx53/imximage.cfg create mode 100644 include/configs/ima3-mx53.h (limited to 'include') diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile new file mode 100644 index 00000000000..f3b13bccaf5 --- /dev/null +++ b/board/esg/ima3-mx53/Makefile @@ -0,0 +1,41 @@ +# +# Copyright (C) 2012, Stefano Babic +# +# Based on ti/evm/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := ima3-mx53.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c new file mode 100644 index 00000000000..9ecf31d7c2d --- /dev/null +++ b/board/esg/ima3-mx53/ima3-mx53.c @@ -0,0 +1,302 @@ +/* + * (C) Copyright 2012, Stefano Babic + * + * (C) Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* NOR flash configuration */ +#define IMA3_MX53_CS0GCR1 (CSEN | DSZ(2)) +#define IMA3_MX53_CS0GCR2 0 +#define IMA3_MX53_CS0RCR1 (RCSN(2) | OEN(1) | RWSC(15)) +#define IMA3_MX53_CS0RCR2 0 +#define IMA3_MX53_CS0WCR1 (WBED1 | WCSN(2) | WEN(1) | WWSC(15)) +#define IMA3_MX53_CS0WCR2 0 + +DECLARE_GLOBAL_DATA_PTR; + +static void weim_nor_settings(void) +{ + struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; + + writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1); + writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2); + writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1); + writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2); + writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1); + writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2); + writel(0x0, &weim_regs->wcr); + + set_chipselect_size(CS0_128); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + return 0; +} + +static void setup_iomux_uart(void) +{ + /* UART4 RXD */ + mxc_request_iomux(MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX53_PIN_CSI0_D13, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); + mxc_iomux_set_input(MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3); + + /* UART4 TXD */ + mxc_request_iomux(MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX53_PIN_CSI0_D12, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); +} + +static void setup_iomux_fec(void) +{ + /*FEC_MDIO*/ + mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); + + /*FEC_MDC*/ + mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); + + /* FEC RXD3 */ + mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX53_PIN_KEY_COL0, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC RXD2 */ + mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX53_PIN_KEY_COL2, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC RXD1 */ + mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC RXD0 */ + mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC TXD3 */ + mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX53_PIN_GPIO_19, PAD_CTL_DRV_HIGH); + + /* FEC TXD2 */ + mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH); + + /* FEC TXD1 */ + mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); + + /* FEC TXD0 */ + mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); + + /* FEC TX_EN */ + mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); + + /* FEC TX_CLK */ + mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC RX_ER */ + mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC RX_DV */ + mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC CRS */ + mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX53_PIN_KEY_COL3, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC COL */ + mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + mxc_iomux_set_input(MX53_FEC_FEC_COL_SELECT_INPUT, 0x0); + + /* FEC RX_CLK */ + mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX53_PIN_KEY_COL1, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + mxc_iomux_set_input(MX53_FEC_FEC_RX_CLK_SELECT_INPUT, 0x0); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR, 1 }; + +int board_mmc_getcd(struct mmc *mmc) +{ + int ret; + + ret = !gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1)); + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX53_PIN_GPIO_1, + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE); + gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1)); + + mxc_iomux_set_pad(MX53_PIN_SD1_CMD, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_CLK, + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | + PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + + return fsl_esdhc_initialize(bis, &esdhc_cfg); +} +#endif + +static void setup_iomux_spi(void) +{ + /* SCLK */ + mxc_request_iomux(MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_input(MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x1); + /* MOSI */ + mxc_request_iomux(MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, 0x1); + /* MISO */ + mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_CSI0_D10, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, 0x1); + /* SSEL 0 */ + mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX53_PIN_CSI0_D11, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11), 1); +} + +int board_early_init_f(void) +{ + /* configure I/O pads */ + setup_iomux_uart(); + setup_iomux_fec(); + + weim_nor_settings(); + + /* configure spi */ + setup_iomux_spi(); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + mxc_set_sata_internal_clock(); + + return 0; +} + +#if defined(CONFIG_RESET_PHY_R) +#include + +void reset_phy(void) +{ + unsigned short reg; + + /* reset the phy */ + miiphy_reset("FEC", CONFIG_PHY_ADDR); + + /* set hard link to 100Mbit, full-duplex */ + miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, ®); + reg &= ~BMCR_ANENABLE; + reg |= (BMCR_SPEED100 | BMCR_FULLDPLX); + miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg); + + miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, ®); + reg |= (1 << 5); + miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg); +} +#endif + +int checkboard(void) +{ + puts("Board: IMA3_MX53\n"); + + return 0; +} diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg new file mode 100644 index 00000000000..fa6b42ddcce --- /dev/null +++ b/board/esg/ima3-mx53/imximage.cfg @@ -0,0 +1,108 @@ +# +# (C) Copyright 2012 +# Stefano Babic DENX Software Engineering sbabic@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# image version + +IMAGE_VERSION 2 + +# Boot Device : one of +# spi, sd (the board has no nand neither onenand) + +BOOT_FROM nor + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register + +# IOMUX for RAM only +DATA 4 0x53fa8554 0x300020 +DATA 4 0x53fa8560 0x300020 +DATA 4 0x53fa8594 0x300020 +DATA 4 0x53fa8584 0x300020 +DATA 4 0x53fa8558 0x300040 +DATA 4 0x53fa8568 0x300040 +DATA 4 0x53fa8590 0x300040 +DATA 4 0x53fa857c 0x300040 +DATA 4 0x53fa8564 0x300040 +DATA 4 0x53fa8580 0x300040 +DATA 4 0x53fa8570 0x300220 +DATA 4 0x53fa8578 0x300220 +DATA 4 0x53fa872c 0x300000 +DATA 4 0x53fa8728 0x300000 +DATA 4 0x53fa871c 0x300000 +DATA 4 0x53fa8718 0x300000 +DATA 4 0x53fa8574 0x300020 +DATA 4 0x53fa8588 0x300020 +DATA 4 0x53fa855c 0x0 +DATA 4 0x53fa858c 0x0 +DATA 4 0x53fa856c 0x300040 +DATA 4 0x53fa86f0 0x300000 +DATA 4 0x53fa8720 0x300000 +DATA 4 0x53fa86fc 0x0 +DATA 4 0x53fa86f4 0x0 +DATA 4 0x53fa8714 0x0 +DATA 4 0x53fa8724 0x4000000 +# +# DDR RAM +DATA 4 0x63fd9088 0x40404040 +DATA 4 0x63fd9090 0x40404040 +DATA 4 0x63fd907C 0x01420143 +DATA 4 0x63fd9080 0x01450146 +DATA 4 0x63fd9018 0x00111740 +DATA 4 0x63fd9000 0x84190000 +# esdcfgX +DATA 4 0x63fd900C 0x9f5152e3 +DATA 4 0x63fd9010 0xb68e8a63 +DATA 4 0x63fd9014 0x01ff00db +# Read/Write command delay +DATA 4 0x63fd902c 0x000026d2 +# Out of reset delays +DATA 4 0x63fd9030 0x00ff0e21 +# ESDCTL ODT timing control +DATA 4 0x63fd9008 0x12273030 +# ESDCTL power down control +DATA 4 0x63fd9004 0x0002002d +# Set registers in DDR memory chips +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x052080b0 +DATA 4 0x63fd901c 0x04008040 +# ESDCTL refresh control +DATA 4 0x63fd9020 0x00005800 +# PHY ZQ HW control +DATA 4 0x63fd9040 0x05380003 +# PHY ODT control +DATA 4 0x63fd9058 0x00022222 +# start DDR3 +DATA 4 0x63fd901c 0x00000000 diff --git a/boards.cfg b/boards.cfg index 4d839d2ab20..0dee43ff3dd 100644 --- a/boards.cfg +++ b/boards.cfg @@ -192,6 +192,7 @@ mx53ard arm armv7 mx53ard freesca mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg mx53loco arm armv7 mx53loco freescale mx5 mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg +ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/mx6qsabrelite/imximage.cfg diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h new file mode 100644 index 00000000000..ea48d646356 --- /dev/null +++ b/include/configs/ima3-mx53.h @@ -0,0 +1,269 @@ +/* + * (C) Copyright 2012, Stefano Babic + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX53-EVK Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* SOC type must be included before imx-regs.h */ +#define CONFIG_MX53 +#include +#include + +#define CONFIG_SYS_MX5_HCLK 24000000 +#define CONFIG_SYS_MX5_CLK32 32768 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_OF_LIBFDT + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F + +/* Enable GPIOs */ +#define CONFIG_MXC_GPIO + +/* UART */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR + +/* MMC */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION + +/* Ethernet on FEC */ +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x01 +#define CONFIG_PHY_ADDR CONFIG_FEC_MXC_PHYADDR +#define CONFIG_RESET_PHY_R +#define CONFIG_FEC_MXC_NO_ANEG +#define CONFIG_PRIME "FEC0" + +/* SPI */ +#define CONFIG_HARD_SPI +#define CONFIG_MXC_SPI +#define CONFIG_DEFAULT_SPI_BUS 1 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 + +/* SPI FLASH - not used for environment */ +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_CS (IOMUX_TO_GPIO(MX53_PIN_CSI0_D11) \ + << 8) | 0 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 25000000 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* Command definition */ +#include +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_GPIO + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_SYS_TEXT_BASE 0xf0001400 /* uboot in nor flash */ + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "IMA3 MX53 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x70000000 +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_CMDLINE_EDITING + +/* Stack sizes */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define MTDIDS_DEFAULT "nor0=f0000000.flash" + +/* FLASH and environment organization */ + +#define CONFIG_SYS_FLASH_BASE 0xF0000000 +#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */ +#define CONFIG_FLASH_CFI_MTD /* with MTD support */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) + +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* + * Default environment and default scripts + * to update uboot and load kernel + */ + +#define HOSTNAME ima3-mx53 +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_HOSTNAME ima3-mx53 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram0 rw\0" \ + "addip_sta=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ + "addip=if test -n ${ipdyn};then run addip_dyn;" \ + "else run addip_sta;fi\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=${console},${baudrate}\0" \ + "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ + "console=ttymxc3\0" \ + "loadaddr=70800000\0" \ + "kernel_addr_r=70800000\0" \ + "ramdisk_addr_r=71000000\0" \ + "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ + "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \ + "mmcargs=setenv bootargs root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "mmcroot=/dev/mmcblk0p3 rw\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs addip addtty addmtd addmisc mmcload;" \ + "bootm\0" \ + "mmcload=fatload mmc ${mmcdev}:${mmcpart} " \ + "${loadaddr} ${uimage}\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "flash_self=run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r}\0" \ + "net_self_load=tftp ${ramdisk_addr_r} ${ramdisk_file};" \ + "tftp ${kernel_addr_r} ${bootfile}\0" \ + "net_self=if run net_self_load;then " \ + "run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ + "else echo Images not loades;fi\0" \ + "satargs=setenv bootargs root=/dev/sda1\0" \ + "satafile=boot/uImage\0" \ + "ssdboot=echo Booting from ssd ...; " \ + "run satargs addip addtty addmtd addmisc;" \ + "sata init;ext2load sata 0:1 ${kernel_addr_r} " \ + "${satafile};bootm\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.imx\0" \ + "uimage=uImage\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "uboot_addr=0xf0001000\0" \ + "update=protect off 0xf0000000 +60000;" \ + "erase ${uboot_addr} +60000;" \ + "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ + "upd=if run load;then echo Updating u-boot;if run update;" \ + "then echo U-Boot updated;" \ + "else echo Error updating u-boot !;" \ + "echo Board without bootloader !!;" \ + "fi;" \ + "else echo U-Boot not downloaded..exiting;fi\0" \ + "bootcmd=run net_nfs\0" + + +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA + #define CONFIG_DWC_AHSATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR + #define CONFIG_LBA48 + #define CONFIG_LIBATA +#endif + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From f92e4e6c1908c72ca06dbaca235005eefedd8f6c Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 22 Feb 2012 00:24:41 +0000 Subject: MX53: mx53loco: Add SATA support Signed-off-by: Stefano Babic CC: Jason Liu Acked-by: Jason Liu --- board/freescale/mx53loco/mx53loco.c | 3 +++ include/configs/mx53loco.h | 11 +++++++++++ 2 files changed, 14 insertions(+) (limited to 'include') diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index d736141e287..7ea9f6eadd2 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -302,6 +303,8 @@ int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + mxc_set_sata_internal_clock(); + return 0; } diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 34a4edd41e9..af59307293f 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -56,6 +56,7 @@ #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC #define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 #define CONFIG_DOS_PARTITION /* Eth Configs */ @@ -193,4 +194,14 @@ #define CONFIG_OF_LIBFDT +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA + #define CONFIG_DWC_AHSATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR + #define CONFIG_LBA48 + #define CONFIG_LIBATA +#endif + #endif /* __CONFIG_H */ -- cgit v1.3.1 From 20831061d8cec4ec537fada6b9abe263e208b4ae Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 20 Mar 2012 11:40:06 +0000 Subject: pmic: Add support for the Dialog DA9053 PMIC Add support for the Dialog DA9053 PMIC. Signed-off-by: Fabio Estevam --- drivers/misc/Makefile | 1 + drivers/misc/pmic_dialog.c | 37 +++++++++ include/dialog_pmic.h | 187 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 225 insertions(+) create mode 100644 drivers/misc/pmic_dialog.c create mode 100644 include/dialog_pmic.h (limited to 'include') diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 30c7f8dd148..271463cf142 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -35,6 +35,7 @@ COBJS-$(CONFIG_PDSP188x) += pdsp188x.o COBJS-$(CONFIG_STATUS_LED) += status_led.o COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o COBJS-$(CONFIG_PMIC) += pmic_core.o +COBJS-$(CONFIG_DIALOG_PMIC) += pmic_dialog.o COBJS-$(CONFIG_PMIC_FSL) += pmic_fsl.o COBJS-$(CONFIG_PMIC_I2C) += pmic_i2c.o COBJS-$(CONFIG_PMIC_SPI) += pmic_spi.o diff --git a/drivers/misc/pmic_dialog.c b/drivers/misc/pmic_dialog.c new file mode 100644 index 00000000000..724207349c5 --- /dev/null +++ b/drivers/misc/pmic_dialog.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * Lukasz Majewski + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +int pmic_init(void) +{ + struct pmic *p = get_pmic(); + static const char name[] = "DIALOG_PMIC"; + + p->name = name; + p->number_of_regs = PMIC_NUM_OF_REGS; + + p->interface = PMIC_I2C; + p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = I2C_PMIC; + + return 0; +} diff --git a/include/dialog_pmic.h b/include/dialog_pmic.h new file mode 100644 index 00000000000..b0925f5ce7e --- /dev/null +++ b/include/dialog_pmic.h @@ -0,0 +1,187 @@ +/* + * da9053 register declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __DIALOG_PMIC_H__ +#define __DIALOG_PMIC_H__ + +enum { + DA9053_PAGECON0_REG = 0, + DA9053_STATUSA_REG, + DA9053_STATUSB_REG, + DA9053_STATUSC_REG, + DA9053_STATUSD_REG, + DA9053_EVENTA_REG, + DA9053_EVENTB_REG, + DA9053_EVENTC_REG, + DA9053_EVENTD_REG, + DA9053_FAULTLOG_REG, + DA9053_IRQMASKA_REG, + DA9053_IRQMASKB_REG, + DA9053_IRQMASKC_REG, + DA9053_IRQMASKD_REG, + DA9053_CONTROLA_REG, + DA9053_CONTROLB_REG, + DA9053_CONTROLC_REG, + DA9053_CONTROLD_REG, + DA9053_PDDIS_REG, + DA9053_INTERFACE_REG, + DA9053_RESET_REG, + DA9053_GPIO0001_REG, + DA9053_GPIO0203_REG, + DA9053_GPIO0405_REG, + DA9053_GPIO0607_REG, + DA9053_GPIO0809_REG, + DA9053_GPIO1011_REG, + DA9053_GPIO1213_REG, + DA9053_GPIO1415_REG, + DA9053_ID01_REG, + DA9053_ID23_REG, + DA9053_ID45_REG, + DA9053_ID67_REG, + DA9053_ID89_REG, + DA9053_ID1011_REG, + DA9053_ID1213_REG, + DA9053_ID1415_REG, + DA9053_ID1617_REG, + DA9053_ID1819_REG, + DA9053_ID2021_REG, + DA9053_SEQSTATUS_REG, + DA9053_SEQA_REG, + DA9053_SEQB_REG, + DA9053_SEQTIMER_REG, + DA9053_BUCKA_REG, + DA9053_BUCKB_REG, + DA9053_BUCKCORE_REG, + DA9053_BUCKPRO_REG, + DA9053_BUCKMEM_REG, + DA9053_BUCKPERI_REG, + DA9053_LDO1_REG, + DA9053_LDO2_REG, + DA9053_LDO3_REG, + DA9053_LDO4_REG, + DA9053_LDO5_REG, + DA9053_LDO6_REG, + DA9053_LDO7_REG, + DA9053_LDO8_REG, + DA9053_LDO9_REG, + DA9053_LDO10_REG, + DA9053_SUPPLY_REG, + DA9053_PULLDOWN_REG, + DA9053_CHGBUCK_REG, + DA9053_WAITCONT_REG, + DA9053_ISET_REG, + DA9053_BATCHG_REG, + DA9053_CHGCONT_REG, + DA9053_INPUTCONT_REG, + DA9053_CHGTIME_REG, + DA9053_BBATCONT_REG, + DA9053_BOOST_REG, + DA9053_LEDCONT_REG, + DA9053_LEDMIN123_REG, + DA9053_LED1CONF_REG, + DA9053_LED2CONF_REG, + DA9053_LED3CONF_REG, + DA9053_LED1CONT_REG, + DA9053_LED2CONT_REG, + DA9053_LED3CONT_REG, + DA9053_LED4CONT_REG, + DA9053_LED5CONT_REG, + DA9053_ADCMAN_REG, + DA9053_ADCCONT_REG, + DA9053_ADCRESL_REG, + DA9053_ADCRESH_REG, + DA9053_VDDRES_REG, + DA9053_VDDMON_REG, + DA9053_ICHGAV_REG, + DA9053_ICHGTHD_REG, + DA9053_ICHGEND_REG, + DA9053_TBATRES_REG, + DA9053_TBATHIGHP_REG, + DA9053_TBATHIGHIN_REG, + DA9053_TBATLOW_REG, + DA9053_TOFFSET_REG, + DA9053_ADCIN4RES_REG, + DA9053_AUTO4HIGH_REG, + DA9053_AUTO4LOW_REG, + DA9053_ADCIN5RES_REG, + DA9053_AUTO5HIGH_REG, + DA9053_AUTO5LOW_REG, + DA9053_ADCIN6RES_REG, + DA9053_AUTO6HIGH_REG, + DA9053_AUTO6LOW_REG, + DA9053_TJUNCRES_REG, + DA9053_TSICONTA_REG, + DA9053_TSICONTB_REG, + DA9053_TSIXMSB_REG, + DA9053_TSIYMSB_REG, + DA9053_TSILSB_REG, + DA9053_TSIZMSB_REG, + DA9053_COUNTS_REG, + DA9053_COUNTMI_REG, + DA9053_COUNTH_REG, + DA9053_COUNTD_REG, + DA9053_COUNTMO_REG, + DA9053_COUNTY_REG, + DA9053_ALARMMI_REG, + DA9053_ALARMH_REG, + DA9053_ALARMD_REG, + DA9053_ALARMMO_REG, + DA9053_ALARMY_REG, + DA9053_SECONDA_REG, + DA9053_SECONDB_REG, + DA9053_SECONDC_REG, + DA9053_SECONDD_REG, + DA9053_PAGECON128_REG, + DA9053_CHIPID_REG, + DA9053_CONFIGID_REG, + DA9053_OTPCONT_REG, + DA9053_OSCTRIM_REG, + DA9053_GPID0_REG, + DA9053_GPID1_REG, + DA9053_GPID2_REG, + DA9053_GPID3_REG, + DA9053_GPID4_REG, + DA9053_GPID5_REG, + DA9053_GPID6_REG, + DA9053_GPID7_REG, + DA9053_GPID8_REG, + DA9053_GPID9_REG, + PMIC_NUM_OF_REGS, +}; + +#define DA_BUCKCORE_VBCORE_1_250V 0x1E + +/* BUCKCORE REGISTER */ +#define DA9052_BUCKCORE_BCORECONF (1 << 7) +#define DA9052_BUCKCORE_BCOREEN (1 << 6) +#define DA9052_BUCKCORE_VBCORE 63 + +/* SUPPLY REGISTER */ +#define DA9052_SUPPLY_VLOCK (1 << 7) +#define DA9052_SUPPLY_VMEMSWEN (1 << 6) +#define DA9052_SUPPLY_VPERISWEN (1 << 5) +#define DA9052_SUPPLY_VLDO3GO (1 << 4) +#define DA9052_SUPPLY_VLDO2GO (1 << 3) +#define DA9052_SUPPLY_VBMEMGO (1 << 2) +#define DA9052_SUPPLY_VBPROGO (1 << 1) +#define DA9052_SUPPLY_VBCOREGO (1 << 0) + +#endif /* __DIALOG_PMIC_H__ */ -- cgit v1.3.1 From e310016bdf1286f89e6f42b94c0fffaa765eb10d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Apr 2012 06:06:28 +0000 Subject: mx28evk: Allow to booting a dt kernel Allow to booting a dt kernel. Signed-off-by: Fabio Estevam --- include/configs/mx28evk.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 02f3366ed26..cb4ff37e599 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -225,6 +225,7 @@ #define CONFIG_BOOTCOMMAND "run bootcmd_net" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_OF_LIBFDT /* * Extra Environments -- cgit v1.3.1 From b91ce01841134ec304d77f13efcc9acf63bdaeb9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Apr 2012 06:06:29 +0000 Subject: m28evk: Allow to booting a dt kernel Allow to booting a dt kernel. Signed-off-by: Fabio Estevam --- include/configs/m28evk.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 012381a500a..39d6a071eb7 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -279,6 +279,7 @@ #define CONFIG_BOOTCOMMAND "run bootcmd_net" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_OF_LIBFDT /* * Extra Environments -- cgit v1.3.1 From 34990e12063a27144d0dcf95aa1b07d3200d1349 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Apr 2012 06:31:15 +0000 Subject: mx28evk: Allow booting a zImage kernel Allow booting a zImage kernel. Signed-off-by: Fabio Estevam --- include/configs/mx28evk.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index cb4ff37e599..31dc718ffb6 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -67,6 +67,7 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_CMD_USB +#define CONFIG_CMD_BOOTZ /* * Memory configurations -- cgit v1.3.1 From 5fbfd1c29bce9446f7151ae514cfc71fba00cf3d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Apr 2012 06:31:16 +0000 Subject: mx6qsabrelite: Allow booting a zImage kernel Allow booting a zImage kernel. Cc: Jason Liu Signed-off-by: Fabio Estevam --- include/configs/mx6qsabrelite.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 3f7e51d877c..492c618df8c 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -211,6 +211,7 @@ #endif #define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ #define CONFIG_SYS_DCACHE_OFF -- cgit v1.3.1 From f0e77b35be03e151f431b1efbe3a8b1a5bfc0018 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Apr 2012 06:31:17 +0000 Subject: mx6qarm2: Allow booting a zImage kernel Allow booting a zImage kernel. Cc: Jason Liu Signed-off-by: Fabio Estevam Acked-by: Jason Liu --- include/configs/mx6qarm2.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index e83aec6c21e..90652c66299 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -168,6 +168,7 @@ #define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ #define CONFIG_SYS_DCACHE_OFF -- cgit v1.3.1 From 0c23d84c864b459bc74cbe34d625afd6e038aa37 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Apr 2012 06:31:18 +0000 Subject: mx31pdk: Allow booting a zImage kernel Allow booting a zImage kernel. Signed-off-by: Fabio Estevam --- include/configs/mx31pdk.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 49d440b9ae3..6ce97bc69fe 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -99,6 +99,7 @@ #define CONFIG_CMD_SPI #define CONFIG_CMD_DATE #define CONFIG_CMD_NAND +#define CONFIG_CMD_BOOTZ /* * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require -- cgit v1.3.1 From 28fdbddc943173d5f199fe2de9bc74bc6172940e Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Wed, 25 Apr 2012 14:14:04 +0000 Subject: i.MX6Q: mx6qsabrelite: Add keypress support to alter boot flow Uses the 'magic_keys' idiom as described in doc/README.kbd: http://lists.denx.de/pipermail/u-boot/2012-April/122502.html Signed-off-by: Eric Nelson Acked-by: Marek Vasut Acked-by: Stefano Babic --- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 122 +++++++++++++++++++++++++- include/configs/mx6qsabrelite.h | 3 + 2 files changed, 123 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index b4d9519747c..90773aaa214 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -50,6 +50,10 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -122,6 +126,22 @@ iomux_v3_cfg_t enet_pads2[] = { MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; +/* Button assignments for J14 */ +static iomux_v3_cfg_t button_pads[] = { + /* Menu */ + MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Back */ + MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Labelled Search (mapped to Power under Android) */ + MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Home */ + MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Volume Down */ + MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Volume Up */ + MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), +}; + static void setup_iomux_enet(void) { gpio_direction_output(87, 0); /* GPIO 3-23 */ @@ -267,11 +287,18 @@ int board_eth_init(bd_t *bis) return 0; } +static void setup_buttons(void) +{ + imx_iomux_v3_setup_multiple_pads(button_pads, + ARRAY_SIZE(button_pads)); +} + int board_early_init_f(void) { - setup_iomux_uart(); + setup_iomux_uart(); + setup_buttons(); - return 0; + return 0; } int board_init(void) @@ -292,3 +319,94 @@ int checkboard(void) return 0; } + +struct button_key { + char const *name; + unsigned gpnum; + char ident; +}; + +static struct button_key const buttons[] = { + {"back", GPIO_NUMBER(2, 2), 'B'}, + {"home", GPIO_NUMBER(2, 4), 'H'}, + {"menu", GPIO_NUMBER(2, 1), 'M'}, + {"search", GPIO_NUMBER(2, 3), 'S'}, + {"volup", GPIO_NUMBER(7, 13), 'V'}, + {"voldown", GPIO_NUMBER(4, 5), 'v'}, +}; + +/* + * generate a null-terminated string containing the buttons pressed + * returns number of keys pressed + */ +static int read_keys(char *buf) +{ + int i, numpressed = 0; + for (i = 0; i < ARRAY_SIZE(buttons); i++) { + if (!gpio_get_value(buttons[i].gpnum)) + buf[numpressed++] = buttons[i].ident; + } + buf[numpressed] = '\0'; + return numpressed; +} + +static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char envvalue[ARRAY_SIZE(buttons)+1]; + int numpressed = read_keys(envvalue); + setenv("keybd", envvalue); + return numpressed == 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "Tests for keypresses, sets 'keybd' environment variable", + "Returns 0 (true) to shell if key is pressed." +); + +#ifdef CONFIG_PREBOOT +static char const kbd_magic_prefix[] = "key_magic"; +static char const kbd_command_prefix[] = "key_cmd"; + +static void preboot_keys(void) +{ + int numpressed; + char keypress[ARRAY_SIZE(buttons)+1]; + numpressed = read_keys(keypress); + if (numpressed) { + char *kbd_magic_keys = getenv("magic_keys"); + char *suffix; + /* + * loop over all magic keys + */ + for (suffix = kbd_magic_keys; *suffix; ++suffix) { + char *keys; + char magic[sizeof(kbd_magic_prefix) + 1]; + sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); + keys = getenv(magic); + if (keys) { + if (!strcmp(keys, keypress)) + break; + } + } + if (*suffix) { + char cmd_name[sizeof(kbd_command_prefix) + 1]; + char *cmd; + sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); + cmd = getenv(cmd_name); + if (cmd) { + setenv("preboot", cmd); + return; + } + } + } +} +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_PREBOOT + preboot_keys(); +#endif + return 0; +} diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 492c618df8c..48be6e6f3f8 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -42,6 +42,7 @@ #define CONFIG_ARCH_CPU_INIT #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R #define CONFIG_MXC_GPIO #define CONFIG_MXC_UART @@ -110,6 +111,8 @@ #define CONFIG_BOOTDELAY 3 +#define CONFIG_PREBOOT "" + #define CONFIG_LOADADDR 0x10800000 #define CONFIG_SYS_TEXT_BASE 0x17800000 -- cgit v1.3.1 From 1fc56f1cb06a1d83bd90626677a236761e812324 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 30 Apr 2012 08:12:03 +0000 Subject: mx53loco: Allow to print CPU information at a later stage Print CPU information within board_late_init(). This is in preparation for adding 1GHz support, which requires programming a PMIC via I2C. As I2C is only available after relocation, print the CPU information later at board_late_init(), so that the CPU frequency can be printed correctly. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic --- arch/arm/cpu/armv7/imx-common/cpu.c | 2 +- arch/arm/include/asm/arch-mx5/sys_proto.h | 1 + board/freescale/mx53loco/mx53loco.c | 22 ++++++++++++++++++++++ include/configs/mx53loco.h | 1 - 4 files changed, 24 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c index b96fa5bdb96..b3195dd6fb2 100644 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ b/arch/arm/cpu/armv7/imx-common/cpu.c @@ -35,7 +35,7 @@ #include #endif -static char *get_reset_cause(void) +char *get_reset_cause(void) { u32 cause; struct src *src_regs = (struct src *)SRC_BASE_ADDR; diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index 3f10d2914cb..7b5246eea67 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -37,5 +37,6 @@ void set_chipselect_size(int const); int fecmxc_initialize(bd_t *bis); u32 get_ahb_clk(void); u32 get_periph_clk(void); +char *get_reset_cause(void); #endif diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 7ea9f6eadd2..46aaeb21598 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -299,6 +299,28 @@ int board_early_init_f(void) return 0; } +int print_cpuinfo(void) +{ + u32 cpurev; + + cpurev = get_cpu_rev(); + printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n", + (cpurev & 0xFF000) >> 12, + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("Reset cause: %s\n", get_reset_cause()); + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + print_cpuinfo(); + return 0; +} +#endif + int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index af59307293f..0778bde9776 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -27,7 +27,6 @@ #define CONFIG_SYS_MX5_HCLK 24000000 #define CONFIG_SYS_MX5_CLK32 32768 -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO -- cgit v1.3.1 From e7e337227bc3895668ad8333cc106e4f813ac96e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 30 Apr 2012 08:12:04 +0000 Subject: mx53loco: Add support for 1GHz operation for DA9053-based boards There are two types of mx53loco boards: initial boards were built with a Dialog DA9053 PMIC and more recent version is based on a Freescale MC34708 PMIC. Add DA9053 PMIC support and adjust the required voltages and clocks for running the CPU at 1GHz. Tested on both versions of mx53loco boards. In the case of a MC34708-based board the CPU operating voltage remains at 800MHz. Signed-off-by: Fabio Estevam Acked-by : Stefano Babic --- board/freescale/mx53loco/mx53loco.c | 71 +++++++++++++++++++++++++++++++++++++ include/configs/mx53loco.h | 14 ++++++++ 2 files changed, 85 insertions(+) (limited to 'include') diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 46aaeb21598..0dcec9b987b 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -36,6 +36,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -291,6 +293,71 @@ int board_mmc_init(bd_t *bis) } #endif +static void setup_iomux_i2c(void) +{ + /* I2C1 SDA */ + mxc_request_iomux(MX53_PIN_CSI0_D8, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + /* I2C1 SCL */ + mxc_request_iomux(MX53_PIN_CSI0_D9, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); +} + +static int power_init(void) +{ + unsigned int val, ret; + struct pmic *p; + + pmic_init(); + p = get_pmic(); + + /* Set VDDA to 1.25V */ + val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; + ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); + + ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val); + val |= DA9052_SUPPLY_VBCOREGO; + ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val); + + /* Set Vcc peripheral to 1.35V */ + ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); + ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); + + return ret; +} + +static void clock_1GHz(void) +{ + int ret; + u32 ref_clk = CONFIG_SYS_MX5_HCLK; + /* + * After increasing voltage to 1.25V, we can switch + * CPU clock to 1GHz and DDR to 400MHz safely + */ + ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to 1GHZ failed\n"); + + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to 400MHz failed\n"); +} + int board_early_init_f(void) { setup_iomux_uart(); @@ -316,7 +383,11 @@ int print_cpuinfo(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { + setup_iomux_i2c(); + if (!power_init()) + clock_1GHz(); print_cpuinfo(); + return 0; } #endif diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 0778bde9776..8f43eecdd3b 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -41,6 +41,7 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_GPIO #define CONFIG_MXC_UART @@ -85,6 +86,19 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 +/* I2C Configs */ +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_MX53_PORT1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +/* PMIC Controller */ +#define CONFIG_PMIC +#define CONFIG_PMIC_I2C +#define CONFIG_DIALOG_PMIC +#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -- cgit v1.3.1 From 6725ebdff566df1e7bb137f03e775b9339595e5f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 3 May 2012 05:47:21 +0000 Subject: M28: Enable FDT support This will eventually be needed with Linux 3.5, which will be the point when MXS will be switched to FDT. Signed-off-by: Marek Vasut Cc: Wolfgang Denk Cc: Detlev Zundel Cc: Stefano Babic Cc: Fabio Estevam --- include/configs/m28evk.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 39d6a071eb7..40845d3e732 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -43,6 +43,8 @@ #define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_MISC_INIT +#define CONFIG_OF_LIBFDT + /* * SPL */ -- cgit v1.3.1 From feef24ee11461532d66e16baea556d3bb8bcc047 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 3 May 2012 05:47:19 +0000 Subject: M28: Scan only first 512 MB of DRAM to avoid memory wraparound Signed-off-by: Marek Vasut Cc: Wolfgang Denk Cc: Detlev Zundel Cc: Stefano Babic Cc: Fabio Estevam --- include/configs/m28evk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 40845d3e732..8cd5f31c857 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -86,7 +86,7 @@ */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ +#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ #define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */ #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ -- cgit v1.3.1 From ecb7be2985e130d1d3f7569f086cf50bfe60d337 Mon Sep 17 00:00:00 2001 From: Lauri Hintsala Date: Tue, 17 Apr 2012 00:35:46 +0000 Subject: mx28evk: add NAND support NAND support is not enabled by default because Eval Kit is not delivered with NAND chip. To enable NAND support add CONFIG_CMD_NAND to board config. Signed-off-by: Lauri Hintsala Acked-by: Marek Vasut --- board/freescale/mx28evk/iomux.c | 21 +++++++++++++++++++++ include/configs/mx28evk.h | 10 ++++++++++ 2 files changed, 31 insertions(+) (limited to 'include') diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index 396761bdff0..6587c454fe7 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -26,6 +26,7 @@ #include #define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) #define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) @@ -55,6 +56,26 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_PWM3__GPIO_3_28 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), +#ifdef CONFIG_NAND_MXS + /* GPMI NAND */ + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDN__GPMI_RDN | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, +#endif + /* FEC0 */ MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 31dc718ffb6..5cd97305126 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -148,6 +148,16 @@ #define CONFIG_MXS_MMC #endif +/* + * NAND Driver + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x60000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#endif + /* * Ethernet on SOC (FEC) */ -- cgit v1.3.1 From 3996a96c5e33aeb676b364936c95e61a987c4e61 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 1 May 2012 09:55:11 +0000 Subject: i.MX6: mx6q_sabrelite: add SATA bindings Signed-off-by: Eric Nelson Acked-by: Marek Vasut Acked-by: stefano Babic --- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 31 +++++++++++++++++++++++++++ include/configs/mx6qsabrelite.h | 13 +++++++++++ 2 files changed, 44 insertions(+) (limited to 'include') diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 90773aaa214..29cbfed120b 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -293,6 +294,32 @@ static void setup_buttons(void) ARRAY_SIZE(button_pads)); } +#ifdef CONFIG_CMD_SATA + +int setup_sata(void) +{ + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; + int ret = enable_sata_clock(); + if (ret) + return ret; + + clrsetbits_le32(&iomuxc_regs->gpr[13], + IOMUXC_GPR13_SATA_MASK, + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(3< Date: Mon, 7 May 2012 10:25:58 +0000 Subject: pmic: dialog: Avoid name conflicts As mx53loco board has two variants: one with Dialog PMIC and another with FSL MC34708 PMIC, we need to be able to build both drivers. Change pmic_init() and PMIC_NUM_OF_REGS names to avoid build conflicts when both drivers are present. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic --- board/freescale/mx53loco/mx53loco.c | 2 +- drivers/misc/pmic_dialog.c | 4 ++-- include/dialog_pmic.h | 2 +- include/pmic.h | 1 + 4 files changed, 5 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 0dcec9b987b..7ed5c4e4dac 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -322,7 +322,7 @@ static int power_init(void) unsigned int val, ret; struct pmic *p; - pmic_init(); + pmic_dialog_init(); p = get_pmic(); /* Set VDDA to 1.25V */ diff --git a/drivers/misc/pmic_dialog.c b/drivers/misc/pmic_dialog.c index 724207349c5..e97af1d1d01 100644 --- a/drivers/misc/pmic_dialog.c +++ b/drivers/misc/pmic_dialog.c @@ -20,13 +20,13 @@ #include #include -int pmic_init(void) +int pmic_dialog_init(void) { struct pmic *p = get_pmic(); static const char name[] = "DIALOG_PMIC"; p->name = name; - p->number_of_regs = PMIC_NUM_OF_REGS; + p->number_of_regs = DIALOG_NUM_OF_REGS; p->interface = PMIC_I2C; p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR; diff --git a/include/dialog_pmic.h b/include/dialog_pmic.h index b0925f5ce7e..8d43585e242 100644 --- a/include/dialog_pmic.h +++ b/include/dialog_pmic.h @@ -164,7 +164,7 @@ enum { DA9053_GPID7_REG, DA9053_GPID8_REG, DA9053_GPID9_REG, - PMIC_NUM_OF_REGS, + DIALOG_NUM_OF_REGS, }; #define DA_BUCKCORE_VBCORE_1_250V 0x1E diff --git a/include/pmic.h b/include/pmic.h index 52a1526d951..6a05b40aefe 100644 --- a/include/pmic.h +++ b/include/pmic.h @@ -55,6 +55,7 @@ struct pmic { }; int pmic_init(void); +int pmic_dialog_init(void); int check_reg(u32 reg); struct pmic *get_pmic(void); int pmic_probe(struct pmic *p); -- cgit v1.3.1 From 5b547f3c20cc0d394f0bbab817e2a50d1a18235f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 7 May 2012 10:25:59 +0000 Subject: mx53loco: Add mc34708 support and set mx53 frequency at 1GHz Add mc34708 support and set mx53 core frequency at its maximum value of 1GHz. Signed-off-by: Fabio Estevam Acked-by: Jason Liu Acked-by: Stefano Babic --- board/freescale/mx53loco/mx53loco.c | 48 +++++++++++++++++++++++++++---------- include/configs/mx53loco.h | 2 ++ include/fsl_pmic.h | 10 ++++++++ 3 files changed, 48 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 7ed5c4e4dac..8f5ded988d1 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -38,6 +38,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -319,23 +320,46 @@ static void setup_iomux_i2c(void) static int power_init(void) { - unsigned int val, ret; + unsigned int val; + int ret = -1; struct pmic *p; - pmic_dialog_init(); - p = get_pmic(); + if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { + pmic_dialog_init(); + p = get_pmic(); - /* Set VDDA to 1.25V */ - val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; - ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); + /* Set VDDA to 1.25V */ + val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; + ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); - ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val); - val |= DA9052_SUPPLY_VBCOREGO; - ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val); + ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val); + val |= DA9052_SUPPLY_VBCOREGO; + ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val); - /* Set Vcc peripheral to 1.35V */ - ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); - ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); + /* Set Vcc peripheral to 1.30V */ + ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); + ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); + } + + if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { + pmic_init(); + p = get_pmic(); + + /* Set VDDGP to 1.25V for 1GHz on SW1 */ + pmic_reg_read(p, REG_SW_0, &val); + val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; + ret = pmic_reg_write(p, REG_SW_0, val); + + /* Set VCC as 1.30V on SW2 */ + pmic_reg_read(p, REG_SW_1, &val); + val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; + ret |= pmic_reg_write(p, REG_SW_1, val); + + /* Set global reset timer to 4s */ + pmic_reg_read(p, REG_POWER_CTL2, &val); + val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; + ret |= pmic_reg_write(p, REG_POWER_CTL2, val); + } return ret; } diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 8f43eecdd3b..87f6ed1e2f6 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -97,7 +97,9 @@ #define CONFIG_PMIC #define CONFIG_PMIC_I2C #define CONFIG_DIALOG_PMIC +#define CONFIG_PMIC_FSL #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 +#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h index 742f2e19f9e..3b7cd37fb70 100644 --- a/include/fsl_pmic.h +++ b/include/fsl_pmic.h @@ -122,4 +122,14 @@ enum { /* Interrupt status 1 */ #define RTCRSTI (1 << 7) +/* MC34708 Definitions */ +#define SWx_VOLT_MASK_MC34708 0x3F +#define SWx_1_250V_MC34708 0x30 +#define SWx_1_300V_MC34708 0x34 +#define TIMER_MASK_MC34708 0x300 +#define TIMER_4S_MC34708 0x100 +#define VUSBSEL_MC34708 (1 << 2) +#define VUSBEN_MC34708 (1 << 3) +#define SWBST_CTRL 31 + #endif -- cgit v1.3.1 From 768a05971030c0c57e05063f20449b8d4138293e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 7 May 2012 10:26:00 +0000 Subject: mx53loco: Turn on VUSB regulator On the mx53loco board with mc34708 PMIC it is necessary to turn on VUSB regulator so that the mx53 USBH1 PHY receives the 3.3V voltage. Tested by inserting a USB pen drive in the upper USB slot (USBH1) and then issued the commands: usb start usb info ,which correctly detected and printed the USB pen drive information. Signed-off-by: Fabio Estevam Acked-by: Jason Liu Acked-by: Stefano Babic --- board/freescale/mx53loco/mx53loco.c | 9 +++++++++ include/fsl_pmic.h | 1 + 2 files changed, 10 insertions(+) (limited to 'include') diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 8f5ded988d1..a49b00a8125 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -359,6 +359,15 @@ static int power_init(void) pmic_reg_read(p, REG_POWER_CTL2, &val); val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; ret |= pmic_reg_write(p, REG_POWER_CTL2, val); + + /* Set VUSBSEL and VUSBEN for USB PHY supply*/ + pmic_reg_read(p, REG_MODE_0, &val); + val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); + ret |= pmic_reg_write(p, REG_MODE_0, val); + + /* Set SWBST to 5V in auto mode */ + val = SWBST_AUTO; + ret |= pmic_reg_write(p, SWBST_CTRL, val); } return ret; diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h index 3b7cd37fb70..64c1e2ef65e 100644 --- a/include/fsl_pmic.h +++ b/include/fsl_pmic.h @@ -131,5 +131,6 @@ enum { #define VUSBSEL_MC34708 (1 << 2) #define VUSBEN_MC34708 (1 << 3) #define SWBST_CTRL 31 +#define SWBST_AUTO 0x8 #endif -- cgit v1.3.1 From 54cd1dee8f9537c2e3d5bfe2029bf31b2b1cf2f3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 8 May 2012 03:40:49 +0000 Subject: mx53loco: Add CONFIG_REVISION_TAG FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. The kernel uses this data to distinguish between Dialog versus mc34708 based boards, and also to distinguish between revA and revB of the mc34708 based boards. Suggested-by: Yu Li Signed-off-by: Fabio Estevam Acked-by: Stefano Babic --- arch/arm/include/asm/arch-mx5/imx-regs.h | 5 +++++ board/freescale/mx53loco/mx53loco.c | 12 ++++++++++++ include/configs/mx53loco.h | 1 + 3 files changed, 18 insertions(+) (limited to 'include') diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index a4245a3cff3..cef419077e6 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -491,6 +491,11 @@ struct iim_regs { } bank[4]; }; +struct fuse_bank0_regs { + u32 fuse0_23[24]; + u32 gp[8]; +}; + struct fuse_bank1_regs { u32 fuse0_8[9]; u32 mac_addr[6]; diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index a49b00a8125..fb138957dbe 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -62,6 +62,18 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; } +u32 get_board_rev(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + int rev = readl(&fuse->gp[6]); + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} + static void setup_iomux_uart(void) { /* UART1 RXD */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 87f6ed1e2f6..eab0e27fb5f 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -43,6 +43,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_GPIO +#define CONFIG_REVISION_TAG #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -- cgit v1.3.1 From 9a0f98d39714f5d681ee541e88a91a59a4e5407f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 May 2012 11:09:43 +0000 Subject: M28EVK: Add SD update command Add "update_sd_firmware" command to easily reload the SD card of m28evk kit. This comes handy when the board boots from SD card. Signed-off-by: Marek Vasut Cc: Detlev Zundel Cc: Fabio Estevam Cc: Stefano Babic Cc: Wolfgang Denk --- include/configs/m28evk.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 8cd5f31c857..60f8a6c3691 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -289,6 +289,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "update_nand_full_filename=u-boot.nand\0" \ "update_nand_firmware_filename=u-boot.sb\0" \ + "update_sd_firmware_filename=u-boot.sd\0" \ "update_nand_firmware_maxsz=0x100000\0" \ "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ @@ -315,6 +316,14 @@ "nand erase ${fcb_sz} ${fw_sz} ; " \ "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ + "fi\0" \ + "update_sd_firmware=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if tftp ${update_sd_firmware_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "setexpr fw_sz ${fw_sz} + 1 ; " \ + "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ + "fi ; " \ "fi\0" #endif /* __M28_H__ */ -- cgit v1.3.1 From f8c4a86b5e9717c1539b6aa45667ba531581ab28 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 May 2012 11:09:45 +0000 Subject: i.MX28: Implement boot pads sampling and reporting This patch implements code that samples i.MX28 boot pads and reports boot mode accordingly. Signed-off-by: Marek Vasut Cc: Detlev Zundel Cc: Fabio Estevam Cc: Stefano Babic Cc: Wolfgang Denk --- arch/arm/cpu/arm926ejs/mx28/mx28.c | 4 +++ arch/arm/cpu/arm926ejs/mx28/spl_boot.c | 48 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx28/sys_proto.h | 26 ++++++++++++++++ include/configs/m28evk.h | 1 + include/configs/mx28evk.h | 1 + 5 files changed, 80 insertions(+) (limited to 'include') diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c index 54a68e17897..865dbb3ffd6 100644 --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c +++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c @@ -185,8 +185,12 @@ int arch_cpu_init(void) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { + struct mx28_spl_data *data = (struct mx28_spl_data *) + ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); + printf("Freescale i.MX28 family at %d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("BOOT: %s\n", mx28_boot_modes[data->boot_mode_idx].mode); return 0; } #endif diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c index 37e1eb75ee8..c9b45661b51 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "mx28_init.h" @@ -47,11 +48,56 @@ void early_delay(int delay) ; } +#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +const iomux_cfg_t iomux_boot[] = { + MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, +}; + +uint8_t mx28_get_bootmode_index(void) +{ + uint8_t bootmode = 0; + int i; + uint8_t masked; + + /* Setup IOMUX of bootmode pads to GPIO */ + mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot)); + + /* Setup bootmode pins as GPIO input */ + gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0); + gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1); + gpio_direction_input(MX28_PAD_LCD_D02__GPIO_1_2); + gpio_direction_input(MX28_PAD_LCD_D03__GPIO_1_3); + gpio_direction_input(MX28_PAD_LCD_D04__GPIO_1_4); + gpio_direction_input(MX28_PAD_LCD_D05__GPIO_1_5); + + /* Read bootmode pads */ + bootmode |= (gpio_get_value(MX28_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; + + for (i = 0; i < ARRAY_SIZE(mx28_boot_modes); i++) { + masked = bootmode & mx28_boot_modes[i].boot_mask; + if (masked == mx28_boot_modes[i].boot_pads) + break; + } + + return i; +} + void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, const unsigned int iomux_size) { struct mx28_spl_data *data = (struct mx28_spl_data *) ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); + uint8_t bootmode = mx28_get_bootmode_index(); mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size); mx28_power_init(); @@ -59,6 +105,8 @@ void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, mx28_mem_init(); data->mem_dram_size = mx28_mem_get_size(); + data->boot_mode_idx = bootmode; + mx28_power_wait_pswitch(); } diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h index 04f2e4db3c6..e701c6409e0 100644 --- a/arch/arm/include/asm/arch-mx28/sys_proto.h +++ b/arch/arm/include/asm/arch-mx28/sys_proto.h @@ -39,7 +39,33 @@ void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, const unsigned int iomux_size); #endif +struct mx28_pair { + uint8_t boot_pads; + uint8_t boot_mask; + const char *mode; +}; + +static const struct mx28_pair mx28_boot_modes[] = { + { 0x00, 0x0f, "USB #0" }, + { 0x01, 0x1f, "I2C #0, master, 3V3" }, + { 0x11, 0x1f, "I2C #0, master, 1V8" }, + { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" }, + { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" }, + { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" }, + { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, + { 0x04, 0x1f, "NAND, 3V3" }, + { 0x14, 0x1f, "NAND, 1V8" }, + { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, + { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, + { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, + { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" }, + { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" }, + { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" }, + { 0x00, 0x00, "Reserved/Unknown/Wrong" }, +}; + struct mx28_spl_data { + uint8_t boot_mode_idx; uint32_t mem_dram_size; }; diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 60f8a6c3691..c62f4d01fd3 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -54,6 +54,7 @@ #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT /* * U-Boot Commands diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 5cd97305126..0c18e5022a1 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -46,6 +46,7 @@ #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT /* * U-Boot Commands -- cgit v1.3.1 From 96875e7d3b9900d0e63f0b591ff5693b31c4d9c3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 2 Apr 2012 13:18:41 +0000 Subject: fdt: Add function to locate an array in the device tree fdtdec_locate_array() locates an integer array but does not copy it. This saves the caller having to allocated wasted space. Access to array elements should be through the fdt32_to_cpu() macro. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/fdtdec.h | 19 +++++++++++++++++++ lib/fdtdec.c | 11 +++++++++++ 2 files changed, 30 insertions(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 171c6284853..84f07685268 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -271,6 +271,25 @@ int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name); int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, u32 *array, int count); +/** + * Look up a property in a node and return a pointer to its contents as a + * unsigned int array of given length. The property must have at least enough + * data for the array ('count' cells). It may have more, but this will be + * ignored. The data is not copied. + * + * Note that you must access elements of the array with fdt32_to_cpu(), + * since the elements will be big endian even on a little endian machine. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param count number of array elements + * @return pointer to array if found, or NULL if the property is not + * found or there is not enough data + */ +const u32 *fdtdec_locate_array(const void *blob, int node, + const char *prop_name, int count); + /** * Look up a boolean property in a node and return it. * diff --git a/lib/fdtdec.c b/lib/fdtdec.c index bdec1a0d962..4a5ab712b54 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -363,6 +363,17 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, return err; } +const u32 *fdtdec_locate_array(const void *blob, int node, + const char *prop_name, int count) +{ + const u32 *cell; + int err; + + cell = get_prop_check_min_len(blob, node, prop_name, + sizeof(u32) * count, &err); + return err ? NULL : cell; +} + int fdtdec_get_bool(const void *blob, int node, const char *prop_name) { const s32 *cell; -- cgit v1.3.1 From 3ddecfc74086aa185a2f671cc07cb826b72d35f0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 2 Apr 2012 13:18:42 +0000 Subject: fdt: Add function to return next compatible subnode We need to iterate through subnodes of a parent, looking only at compatible nodes. Add a utility function to do this for us. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/fdtdec.h | 17 +++++++++++++++++ lib/fdtdec.c | 15 +++++++++++++++ 2 files changed, 32 insertions(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 84f07685268..0351a25a98a 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -116,6 +116,23 @@ int fdtdec_next_alias(const void *blob, const char *name, int fdtdec_next_compatible(const void *blob, int node, enum fdt_compat_id id); +/** + * Find the next compatible subnode for a peripheral. + * + * Do the first call with node set to the parent and depth = 0. This + * function will return the offset of the next compatible node. Next time + * you call this function, pass the node value returned last time, with + * depth unchanged, and the next node will be provided. + * + * @param blob FDT blob to use + * @param node Start node for search + * @param id Compatible ID to look for (enum fdt_compat_id) + * @param depthp Current depth (set to 0 before first call) + * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more + */ +int fdtdec_next_compatible_subnode(const void *blob, int node, + enum fdt_compat_id id, int *depthp); + /** * Look up an address property in a node and return it as an address. * The property must hold either one address with no trailing data or diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 4a5ab712b54..76d38089ee3 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -133,6 +133,21 @@ int fdtdec_next_compatible(const void *blob, int node, return fdt_node_offset_by_compatible(blob, node, compat_names[id]); } +int fdtdec_next_compatible_subnode(const void *blob, int node, + enum fdt_compat_id id, int *depthp) +{ + do { + node = fdt_next_node(blob, node, depthp); + } while (*depthp > 1); + + /* If this is a direct subnode, and compatible, return it */ + if (*depthp == 1 && 0 == fdt_node_check_compatible( + blob, node, compat_names[id])) + return node; + + return -FDT_ERR_NOTFOUND; +} + int fdtdec_next_alias(const void *blob, const char *name, enum fdt_compat_id id, int *upto) { -- cgit v1.3.1 From a35925b8c10c99a7020bfcda74c8a6c72ed90cf5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 10 May 2012 11:37:35 +0000 Subject: Add abs() macro to return absolute value This macro is generally useful to make it available in common. Signed-off-by: Simon Glass Signed-off-by: Tom Warren Acked-by: Tom Rini Acked-by: Mike Frysinger --- arch/arm/cpu/armv7/omap4/clocks.c | 2 -- drivers/bios_emulator/x86emu/prim_ops.c | 5 ----- include/common.h | 25 +++++++++++++++++++++++++ 3 files changed, 25 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index dd694c409f8..3f0dfd72758 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -46,8 +46,6 @@ #define puts(s) #endif -#define abs(x) (((x) < 0) ? ((x)*-1) : (x)) - struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100; const u32 sys_clk_array[8] = { diff --git a/drivers/bios_emulator/x86emu/prim_ops.c b/drivers/bios_emulator/x86emu/prim_ops.c index 7553087b263..5f6c795fb7f 100644 --- a/drivers/bios_emulator/x86emu/prim_ops.c +++ b/drivers/bios_emulator/x86emu/prim_ops.c @@ -118,11 +118,6 @@ static u32 x86emu_parity_tab[8] = #define PARITY(x) (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0) #define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) -/*----------------------------- Implementation ----------------------------*/ -int abs(int v) -{ - return (v>0)?v:-v; -} /*----------------------------- Implementation ----------------------------*/ diff --git a/include/common.h b/include/common.h index 4b5841ef470..ff7126d35d8 100644 --- a/include/common.h +++ b/include/common.h @@ -222,6 +222,31 @@ typedef void (interrupt_handler_t)(void *); #define MIN(x, y) min(x, y) #define MAX(x, y) max(x, y) +/* + * Return the absolute value of a number. + * + * This handles unsigned and signed longs, ints, shorts and chars. For all + * input types abs() returns a signed long. + * + * For 64-bit types, use abs64() + */ +#define abs(x) ({ \ + long ret; \ + if (sizeof(x) == sizeof(long)) { \ + long __x = (x); \ + ret = (__x < 0) ? -__x : __x; \ + } else { \ + int __x = (x); \ + ret = (__x < 0) ? -__x : __x; \ + } \ + ret; \ + }) + +#define abs64(x) ({ \ + s64 __x = (x); \ + (__x < 0) ? -__x : __x; \ + }) + #if defined(CONFIG_ENV_IS_EMBEDDED) #define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN #elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \ -- cgit v1.3.1 From 1aa7e23e2ba41c94d61bcd9199afb23817400f3c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 2 Apr 2012 13:18:44 +0000 Subject: i2c: Add TPS6586X driver This power management chip supports battery charging and a large number of power supplies. This initial driver only provides the ability to adjust the two synchronous buck converters SM0 and SM1 in a stepwise manner. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- drivers/power/Makefile | 1 + drivers/power/tps6586x.c | 280 +++++++++++++++++++++++++++++++++++++++++++++++ include/tps6586x.h | 68 ++++++++++++ 3 files changed, 349 insertions(+) create mode 100644 drivers/power/tps6586x.c create mode 100644 include/tps6586x.h (limited to 'include') diff --git a/drivers/power/Makefile b/drivers/power/Makefile index f24b93cc318..6bf388cb7d5 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libpower.o COBJS-$(CONFIG_FTPMU010_POWER) += ftpmu010.o +COBJS-$(CONFIG_TPS6586X_POWER) += tps6586x.o COBJS-$(CONFIG_TWL4030_POWER) += twl4030.o COBJS-$(CONFIG_TWL6030_POWER) += twl6030.o COBJS-$(CONFIG_TWL6035_POWER) += twl6035.o diff --git a/drivers/power/tps6586x.c b/drivers/power/tps6586x.c new file mode 100644 index 00000000000..f3f2ec6e58e --- /dev/null +++ b/drivers/power/tps6586x.c @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +static int bus_num; /* I2C bus we are on */ +#define I2C_ADDRESS 0x34 /* chip requires this address */ +static char inited; /* 1 if we have been inited */ + +enum { + /* Registers that we access */ + SUPPLY_CONTROL1 = 0x20, + SUPPLY_CONTROL2, + SM1_VOLTAGE_V1 = 0x23, + SM1_VOLTAGE_V2, + SM0_VOLTAGE_V1 = 0x26, + SM0_VOLTAGE_V2, + PFM_MODE = 0x47, + + /* Bits in the supply control registers */ + CTRL_SM1_RAMP = 0x01, + CTRL_SM1_SUPPLY2 = 0x02, + CTRL_SM0_RAMP = 0x04, + CTRL_SM0_SUPPLY2 = 0x08, +}; + +#define MAX_I2C_RETRY 3 +int tps6586x_read(int reg) +{ + int i; + uchar data; + int retval = -1; + int old_bus_num; + + old_bus_num = i2c_get_bus_num(); + i2c_set_bus_num(bus_num); + + for (i = 0; i < MAX_I2C_RETRY; ++i) { + if (!i2c_read(I2C_ADDRESS, reg, 1, &data, 1)) { + retval = (int)data; + goto exit; + } + + /* i2c access failed, retry */ + udelay(100); + } + +exit: + i2c_set_bus_num(old_bus_num); + debug("pmu_read %x=%x\n", reg, retval); + if (retval < 0) + debug("%s: failed to read register %#x: %d\n", __func__, reg, + retval); + return retval; +} + +int tps6586x_write(int reg, uchar *data, uint len) +{ + int i; + int retval = -1; + int old_bus_num; + + old_bus_num = i2c_get_bus_num(); + i2c_set_bus_num(bus_num); + + for (i = 0; i < MAX_I2C_RETRY; ++i) { + if (!i2c_write(I2C_ADDRESS, reg, 1, data, len)) { + retval = 0; + goto exit; + } + + /* i2c access failed, retry */ + udelay(100); + } + +exit: + i2c_set_bus_num(old_bus_num); + debug("pmu_write %x=%x: ", reg, retval); + for (i = 0; i < len; i++) + debug("%x ", data[i]); + if (retval) + debug("%s: failed to write register %#x\n", __func__, reg); + return retval; +} + +/* + * Get current voltage of SM0 and SM1 + * + * @param sm0 Place to put SM0 voltage + * @param sm1 Place to put SM1 voltage + * @return 0 if ok, -1 on error + */ +static int read_voltages(int *sm0, int *sm1) +{ + int ctrl1, ctrl2; + int is_v2; + + /* + * Each vdd has two supply sources, ie, v1 and v2. + * The supply control reg1 and reg2 determine the current selection. + */ + ctrl1 = tps6586x_read(SUPPLY_CONTROL1); + ctrl2 = tps6586x_read(SUPPLY_CONTROL2); + if (ctrl1 == -1 || ctrl2 == -1) + return -1; + + /* Figure out whether V1 or V2 is selected */ + is_v2 = (ctrl1 | ctrl2) & CTRL_SM0_SUPPLY2; + *sm0 = tps6586x_read(is_v2 ? SM0_VOLTAGE_V2 : SM0_VOLTAGE_V1); + *sm1 = tps6586x_read(is_v2 ? SM1_VOLTAGE_V2 : SM1_VOLTAGE_V1); + if (*sm0 == -1 || *sm1 == -1) + return -1; + + return 0; +} + +static int set_voltage(int reg, int data, int rate) +{ + uchar control_bit; + uchar buff[3]; + + control_bit = (reg == SM0_VOLTAGE_V1 ? CTRL_SM0_RAMP : CTRL_SM1_RAMP); + + /* + * Only one supply is needed in u-boot. set both v1 and v2 to + * same value. + * + * When both v1 and v2 are set to same value, we just need to set + * control1 reg to trigger the supply selection. + */ + buff[0] = buff[1] = (uchar)data; + buff[2] = rate; + + /* write v1, v2 and rate, then trigger */ + if (tps6586x_write(reg, buff, 3) || + tps6586x_write(SUPPLY_CONTROL1, &control_bit, 1)) + return -1; + + return 0; +} + +static int calculate_next_voltage(int voltage, int target, int step) +{ + int diff = voltage < target ? step : -step; + + if (abs(target - voltage) > step) + voltage += diff; + else + voltage = target; + + return voltage; +} + +int tps6586x_set_pwm_mode(int mask) +{ + uchar val; + int ret; + + assert(inited); + ret = tps6586x_read(PFM_MODE); + if (ret != -1) { + val = (uchar)ret; + val |= mask; + + ret = tps6586x_write(PFM_MODE, &val, 1); + } + + if (ret == -1) + debug("%s: Failed to read/write PWM mode reg\n", __func__); + + return ret; +} + +int tps6586x_adjust_sm0_sm1(int sm0_target, int sm1_target, int step, int rate, + int min_sm0_over_sm1) +{ + int sm0, sm1; + int bad; + + assert(inited); + + /* get current voltage settings */ + if (read_voltages(&sm0, &sm1)) { + debug("%s: Cannot read voltage settings\n", __func__); + return -1; + } + + /* + * if vdd_core < vdd_cpu + rel + * skip + * + * This condition may happen when system reboots due to kernel crash. + */ + if (min_sm0_over_sm1 != -1 && sm0 < sm1 + min_sm0_over_sm1) { + debug("%s: SM0 is %d, SM1 is %d, but min_sm0_over_sm1 is %d\n", + __func__, sm0, sm1, min_sm0_over_sm1); + return -1; + } + + /* + * Since vdd_core and vdd_cpu may both stand at either greater or less + * than their nominal voltage, the adjustment may go either directions. + * + * Make sure vdd_core is always higher than vdd_cpu with certain margin. + * So, find out which vdd to adjust first in each step. + * + * case 1: both sm0 and sm1 need to move up + * adjust sm0 before sm1 + * + * case 2: both sm0 and sm1 need to move down + * adjust sm1 before sm0 + * + * case 3: sm0 moves down and sm1 moves up + * adjusting either one first is fine. + * + * Adjust vdd_core and vdd_cpu one step at a time until they reach + * their nominal values. + */ + bad = 0; + while (!bad && (sm0 != sm0_target || sm1 != sm1_target)) { + int adjust_sm0_late = 0; /* flag to adjust vdd_core later */ + + debug("%d-%d %d-%d ", sm0, sm0_target, sm1, sm1_target); + + if (sm0 != sm0_target) { + /* + * if case 1 and case 3, set new sm0 first. + * otherwise, hold down until new sm1 is set. + */ + sm0 = calculate_next_voltage(sm0, sm0_target, step); + if (sm1 < sm1_target) + bad |= set_voltage(SM0_VOLTAGE_V1, sm0, rate); + else + adjust_sm0_late = 1; + } + + if (sm1 != sm1_target) { + sm1 = calculate_next_voltage(sm1, sm1_target, step); + bad |= set_voltage(SM1_VOLTAGE_V1, sm1, rate); + } + + if (adjust_sm0_late) + bad |= set_voltage(SM0_VOLTAGE_V1, sm0, rate); + debug("%d\n", adjust_sm0_late); + } + debug("%d-%d %d-%d done\n", sm0, sm0_target, sm1, sm1_target); + + return bad ? -1 : 0; +} + +int tps6586x_init(int bus) +{ + bus_num = bus; + inited = 1; + + return 0; +} diff --git a/include/tps6586x.h b/include/tps6586x.h new file mode 100644 index 00000000000..ab880823a37 --- /dev/null +++ b/include/tps6586x.h @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __H_ +#define _TPS6586X_H_ + +enum { + /* SM0-2 PWM/PFM Mode Selection */ + TPS6586X_PWM_SM0 = 1 << 0, + TPS6586X_PWM_SM1 = 1 << 1, + TPS6586X_PWM_SM2 = 1 << 2, +}; + +/** + * Enable PWM mode for selected SM0-2 + * + * @param mask Mask of synchronous converter to enable (TPS6586X_PWM_...) + * @return 0 if ok, -1 on error + */ +int tps6586x_set_pwm_mode(int mask); + +/** + * Adjust SM0 and SM1 voltages to the given targets in incremental steps. + * + * @param sm0_target Target voltage for SM0 in 25mW units, 0=725mV, 31=1.5V + * @param sm1_target Target voltage for SM1 in 25mW units, 0=725mV, 31=1.5V + * @param step Amount to change voltage in each step, in 25mW units + * @param rate Slew ratein mV/us: 0=instantly, 1=0.11, 2=0.22, + * 3=0.44, 4=0.88, 5=1.76, 6=3.52, 7=7.04 + * @param min_sm0_over_sm1 Minimum amount by which sm0 must exceed sm1. + * If this condition is not met, no adjustment will be + * done and an error will be reported. Use -1 to skip + * this check. + * @return 0 if ok, -1 on error + */ +int tps6586x_adjust_sm0_sm1(int sm0_target, int sm1_target, int step, int rate, + int min_sm0_over_sm1); + +/** + * Set up the TPS6586X I2C bus number. This will be used for all operations + * on the device. This function must be called before using other functions. + * + * @param bus I2C bus number containing the TPS6586X chip + * @return 0 (always succeeds) + */ +int tps6586x_init(int bus); + +#endif /* _TPS6586X_H_ */ -- cgit v1.3.1 From 5b1a5451d5aa3f440da071d303bc8064ae5571b9 Mon Sep 17 00:00:00 2001 From: Yen Lin Date: Thu, 5 Apr 2012 11:54:58 +0000 Subject: Add AES crypto library Add support for AES using an implementation from Karl Malbrain. This offers small code size (around 5KB on ARM) and supports 128-bit AES only. Signed-off-by: Yen Lin Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/aes.h | 70 +++++++ lib/Makefile | 1 + lib/aes.c | 598 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 669 insertions(+) create mode 100644 include/aes.h create mode 100644 lib/aes.c (limited to 'include') diff --git a/include/aes.h b/include/aes.h new file mode 100644 index 00000000000..41b0db29c1b --- /dev/null +++ b/include/aes.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010 - 2011 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _AES_REF_H_ +#define _AES_REF_H_ + +/* + * AES encryption library, with small code size, supporting only 128-bit AES + * + * AES is a stream cipher which works a block at a time, with each block + * in this case being AES_KEY_LENGTH bytes. + */ + +enum { + AES_STATECOLS = 4, /* columns in the state & expanded key */ + AES_KEYCOLS = 4, /* columns in a key */ + AES_ROUNDS = 10, /* rounds in encryption */ + + AES_KEY_LENGTH = 128 / 8, + AES_EXPAND_KEY_LENGTH = 4 * AES_STATECOLS * (AES_ROUNDS + 1), +}; + +/** + * Expand a key into a key schedule, which is then used for the other + * operations. + * + * \param key Key, of length AES_KEY_LENGTH bytes + * \param expkey Buffer to place expanded key, AES_EXPAND_KEY_LENGTH + */ +void aes_expand_key(u8 *key, u8 *expkey); + +/** + * Encrypt a single block of data + * + * in Input data + * expkey Expanded key to use for encryption (from aes_expand_key()) + * out Output data + */ +void aes_encrypt(u8 *in, u8 *expkey, u8 *out); + +/** + * Decrypt a single block of data + * + * in Input data + * expkey Expanded key to use for decryption (from aes_expand_key()) + * out Output data + */ +void aes_decrypt(u8 *in, u8 *expkey, u8 *out); + +#endif /* _AES_REF_H_ */ diff --git a/lib/Makefile b/lib/Makefile index a0fec60a136..1e8478f0312 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -28,6 +28,7 @@ LIB = $(obj)libgeneric.o ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_ADDR_MAP) += addr_map.o COBJS-$(CONFIG_BCH) += bch.o +COBJS-$(CONFIG_AES) += aes.o COBJS-$(CONFIG_BZIP2) += bzlib.o COBJS-$(CONFIG_BZIP2) += bzlib_crctable.o COBJS-$(CONFIG_BZIP2) += bzlib_decompress.o diff --git a/lib/aes.c b/lib/aes.c new file mode 100644 index 00000000000..7da9edb7e67 --- /dev/null +++ b/lib/aes.c @@ -0,0 +1,598 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2011 NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * advanced encryption standard + * author: karl malbrain, malbrain@yahoo.com + * + * This work, including the source code, documentation + * and related data, is placed into the public domain. + * + * The orginal author is Karl Malbrain. + * + * THIS SOFTWARE IS PROVIDED AS-IS WITHOUT WARRANTY + * OF ANY KIND, NOT EVEN THE IMPLIED WARRANTY OF + * MERCHANTABILITY. THE AUTHOR OF THIS SOFTWARE, + * ASSUMES _NO_ RESPONSIBILITY FOR ANY CONSEQUENCE + * RESULTING FROM THE USE, MODIFICATION, OR + * REDISTRIBUTION OF THIS SOFTWARE. +*/ + +#include +#include "aes.h" + +/* forward s-box */ +static const u8 sbox[256] = { + 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, + 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, + 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, + 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, + 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, + 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, + 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, + 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, + 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, + 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, + 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, + 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, + 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, + 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, + 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, + 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, + 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, + 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, + 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, + 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, + 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, + 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, + 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, + 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, + 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, + 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, + 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, + 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, + 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, + 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, + 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, + 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 +}; + +/* inverse s-box */ +static const u8 inv_sbox[256] = { + 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, + 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb, + 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, + 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, + 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, + 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, + 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, + 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, + 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, + 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, + 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, + 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84, + 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, + 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, + 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, + 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, + 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, + 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, + 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, + 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e, + 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, + 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, + 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, + 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, + 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, + 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, + 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, + 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, + 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, + 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, + 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, + 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d +}; + +/* combined Xtimes2[Sbox[]] */ +static const u8 x2_sbox[256] = { + 0xc6, 0xf8, 0xee, 0xf6, 0xff, 0xd6, 0xde, 0x91, + 0x60, 0x02, 0xce, 0x56, 0xe7, 0xb5, 0x4d, 0xec, + 0x8f, 0x1f, 0x89, 0xfa, 0xef, 0xb2, 0x8e, 0xfb, + 0x41, 0xb3, 0x5f, 0x45, 0x23, 0x53, 0xe4, 0x9b, + 0x75, 0xe1, 0x3d, 0x4c, 0x6c, 0x7e, 0xf5, 0x83, + 0x68, 0x51, 0xd1, 0xf9, 0xe2, 0xab, 0x62, 0x2a, + 0x08, 0x95, 0x46, 0x9d, 0x30, 0x37, 0x0a, 0x2f, + 0x0e, 0x24, 0x1b, 0xdf, 0xcd, 0x4e, 0x7f, 0xea, + 0x12, 0x1d, 0x58, 0x34, 0x36, 0xdc, 0xb4, 0x5b, + 0xa4, 0x76, 0xb7, 0x7d, 0x52, 0xdd, 0x5e, 0x13, + 0xa6, 0xb9, 0x00, 0xc1, 0x40, 0xe3, 0x79, 0xb6, + 0xd4, 0x8d, 0x67, 0x72, 0x94, 0x98, 0xb0, 0x85, + 0xbb, 0xc5, 0x4f, 0xed, 0x86, 0x9a, 0x66, 0x11, + 0x8a, 0xe9, 0x04, 0xfe, 0xa0, 0x78, 0x25, 0x4b, + 0xa2, 0x5d, 0x80, 0x05, 0x3f, 0x21, 0x70, 0xf1, + 0x63, 0x77, 0xaf, 0x42, 0x20, 0xe5, 0xfd, 0xbf, + 0x81, 0x18, 0x26, 0xc3, 0xbe, 0x35, 0x88, 0x2e, + 0x93, 0x55, 0xfc, 0x7a, 0xc8, 0xba, 0x32, 0xe6, + 0xc0, 0x19, 0x9e, 0xa3, 0x44, 0x54, 0x3b, 0x0b, + 0x8c, 0xc7, 0x6b, 0x28, 0xa7, 0xbc, 0x16, 0xad, + 0xdb, 0x64, 0x74, 0x14, 0x92, 0x0c, 0x48, 0xb8, + 0x9f, 0xbd, 0x43, 0xc4, 0x39, 0x31, 0xd3, 0xf2, + 0xd5, 0x8b, 0x6e, 0xda, 0x01, 0xb1, 0x9c, 0x49, + 0xd8, 0xac, 0xf3, 0xcf, 0xca, 0xf4, 0x47, 0x10, + 0x6f, 0xf0, 0x4a, 0x5c, 0x38, 0x57, 0x73, 0x97, + 0xcb, 0xa1, 0xe8, 0x3e, 0x96, 0x61, 0x0d, 0x0f, + 0xe0, 0x7c, 0x71, 0xcc, 0x90, 0x06, 0xf7, 0x1c, + 0xc2, 0x6a, 0xae, 0x69, 0x17, 0x99, 0x3a, 0x27, + 0xd9, 0xeb, 0x2b, 0x22, 0xd2, 0xa9, 0x07, 0x33, + 0x2d, 0x3c, 0x15, 0xc9, 0x87, 0xaa, 0x50, 0xa5, + 0x03, 0x59, 0x09, 0x1a, 0x65, 0xd7, 0x84, 0xd0, + 0x82, 0x29, 0x5a, 0x1e, 0x7b, 0xa8, 0x6d, 0x2c +}; + +/* combined Xtimes3[Sbox[]] */ +static const u8 x3_sbox[256] = { + 0xa5, 0x84, 0x99, 0x8d, 0x0d, 0xbd, 0xb1, 0x54, + 0x50, 0x03, 0xa9, 0x7d, 0x19, 0x62, 0xe6, 0x9a, + 0x45, 0x9d, 0x40, 0x87, 0x15, 0xeb, 0xc9, 0x0b, + 0xec, 0x67, 0xfd, 0xea, 0xbf, 0xf7, 0x96, 0x5b, + 0xc2, 0x1c, 0xae, 0x6a, 0x5a, 0x41, 0x02, 0x4f, + 0x5c, 0xf4, 0x34, 0x08, 0x93, 0x73, 0x53, 0x3f, + 0x0c, 0x52, 0x65, 0x5e, 0x28, 0xa1, 0x0f, 0xb5, + 0x09, 0x36, 0x9b, 0x3d, 0x26, 0x69, 0xcd, 0x9f, + 0x1b, 0x9e, 0x74, 0x2e, 0x2d, 0xb2, 0xee, 0xfb, + 0xf6, 0x4d, 0x61, 0xce, 0x7b, 0x3e, 0x71, 0x97, + 0xf5, 0x68, 0x00, 0x2c, 0x60, 0x1f, 0xc8, 0xed, + 0xbe, 0x46, 0xd9, 0x4b, 0xde, 0xd4, 0xe8, 0x4a, + 0x6b, 0x2a, 0xe5, 0x16, 0xc5, 0xd7, 0x55, 0x94, + 0xcf, 0x10, 0x06, 0x81, 0xf0, 0x44, 0xba, 0xe3, + 0xf3, 0xfe, 0xc0, 0x8a, 0xad, 0xbc, 0x48, 0x04, + 0xdf, 0xc1, 0x75, 0x63, 0x30, 0x1a, 0x0e, 0x6d, + 0x4c, 0x14, 0x35, 0x2f, 0xe1, 0xa2, 0xcc, 0x39, + 0x57, 0xf2, 0x82, 0x47, 0xac, 0xe7, 0x2b, 0x95, + 0xa0, 0x98, 0xd1, 0x7f, 0x66, 0x7e, 0xab, 0x83, + 0xca, 0x29, 0xd3, 0x3c, 0x79, 0xe2, 0x1d, 0x76, + 0x3b, 0x56, 0x4e, 0x1e, 0xdb, 0x0a, 0x6c, 0xe4, + 0x5d, 0x6e, 0xef, 0xa6, 0xa8, 0xa4, 0x37, 0x8b, + 0x32, 0x43, 0x59, 0xb7, 0x8c, 0x64, 0xd2, 0xe0, + 0xb4, 0xfa, 0x07, 0x25, 0xaf, 0x8e, 0xe9, 0x18, + 0xd5, 0x88, 0x6f, 0x72, 0x24, 0xf1, 0xc7, 0x51, + 0x23, 0x7c, 0x9c, 0x21, 0xdd, 0xdc, 0x86, 0x85, + 0x90, 0x42, 0xc4, 0xaa, 0xd8, 0x05, 0x01, 0x12, + 0xa3, 0x5f, 0xf9, 0xd0, 0x91, 0x58, 0x27, 0xb9, + 0x38, 0x13, 0xb3, 0x33, 0xbb, 0x70, 0x89, 0xa7, + 0xb6, 0x22, 0x92, 0x20, 0x49, 0xff, 0x78, 0x7a, + 0x8f, 0xf8, 0x80, 0x17, 0xda, 0x31, 0xc6, 0xb8, + 0xc3, 0xb0, 0x77, 0x11, 0xcb, 0xfc, 0xd6, 0x3a +}; + +/* + * modular multiplication tables based on: + * + * Xtime2[x] = (x & 0x80 ? 0x1b : 0) ^ (x + x) + * Xtime3[x] = x^Xtime2[x]; + */ +static const u8 x_time_9[256] = { + 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, + 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77, + 0x90, 0x99, 0x82, 0x8b, 0xb4, 0xbd, 0xa6, 0xaf, + 0xd8, 0xd1, 0xca, 0xc3, 0xfc, 0xf5, 0xee, 0xe7, + 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, + 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c, + 0xab, 0xa2, 0xb9, 0xb0, 0x8f, 0x86, 0x9d, 0x94, + 0xe3, 0xea, 0xf1, 0xf8, 0xc7, 0xce, 0xd5, 0xdc, + 0x76, 0x7f, 0x64, 0x6d, 0x52, 0x5b, 0x40, 0x49, + 0x3e, 0x37, 0x2c, 0x25, 0x1a, 0x13, 0x08, 0x01, + 0xe6, 0xef, 0xf4, 0xfd, 0xc2, 0xcb, 0xd0, 0xd9, + 0xae, 0xa7, 0xbc, 0xb5, 0x8a, 0x83, 0x98, 0x91, + 0x4d, 0x44, 0x5f, 0x56, 0x69, 0x60, 0x7b, 0x72, + 0x05, 0x0c, 0x17, 0x1e, 0x21, 0x28, 0x33, 0x3a, + 0xdd, 0xd4, 0xcf, 0xc6, 0xf9, 0xf0, 0xeb, 0xe2, + 0x95, 0x9c, 0x87, 0x8e, 0xb1, 0xb8, 0xa3, 0xaa, + 0xec, 0xe5, 0xfe, 0xf7, 0xc8, 0xc1, 0xda, 0xd3, + 0xa4, 0xad, 0xb6, 0xbf, 0x80, 0x89, 0x92, 0x9b, + 0x7c, 0x75, 0x6e, 0x67, 0x58, 0x51, 0x4a, 0x43, + 0x34, 0x3d, 0x26, 0x2f, 0x10, 0x19, 0x02, 0x0b, + 0xd7, 0xde, 0xc5, 0xcc, 0xf3, 0xfa, 0xe1, 0xe8, + 0x9f, 0x96, 0x8d, 0x84, 0xbb, 0xb2, 0xa9, 0xa0, + 0x47, 0x4e, 0x55, 0x5c, 0x63, 0x6a, 0x71, 0x78, + 0x0f, 0x06, 0x1d, 0x14, 0x2b, 0x22, 0x39, 0x30, + 0x9a, 0x93, 0x88, 0x81, 0xbe, 0xb7, 0xac, 0xa5, + 0xd2, 0xdb, 0xc0, 0xc9, 0xf6, 0xff, 0xe4, 0xed, + 0x0a, 0x03, 0x18, 0x11, 0x2e, 0x27, 0x3c, 0x35, + 0x42, 0x4b, 0x50, 0x59, 0x66, 0x6f, 0x74, 0x7d, + 0xa1, 0xa8, 0xb3, 0xba, 0x85, 0x8c, 0x97, 0x9e, + 0xe9, 0xe0, 0xfb, 0xf2, 0xcd, 0xc4, 0xdf, 0xd6, + 0x31, 0x38, 0x23, 0x2a, 0x15, 0x1c, 0x07, 0x0e, + 0x79, 0x70, 0x6b, 0x62, 0x5d, 0x54, 0x4f, 0x46 +}; + +static const u8 x_time_b[256] = { + 0x00, 0x0b, 0x16, 0x1d, 0x2c, 0x27, 0x3a, 0x31, + 0x58, 0x53, 0x4e, 0x45, 0x74, 0x7f, 0x62, 0x69, + 0xb0, 0xbb, 0xa6, 0xad, 0x9c, 0x97, 0x8a, 0x81, + 0xe8, 0xe3, 0xfe, 0xf5, 0xc4, 0xcf, 0xd2, 0xd9, + 0x7b, 0x70, 0x6d, 0x66, 0x57, 0x5c, 0x41, 0x4a, + 0x23, 0x28, 0x35, 0x3e, 0x0f, 0x04, 0x19, 0x12, + 0xcb, 0xc0, 0xdd, 0xd6, 0xe7, 0xec, 0xf1, 0xfa, + 0x93, 0x98, 0x85, 0x8e, 0xbf, 0xb4, 0xa9, 0xa2, + 0xf6, 0xfd, 0xe0, 0xeb, 0xda, 0xd1, 0xcc, 0xc7, + 0xae, 0xa5, 0xb8, 0xb3, 0x82, 0x89, 0x94, 0x9f, + 0x46, 0x4d, 0x50, 0x5b, 0x6a, 0x61, 0x7c, 0x77, + 0x1e, 0x15, 0x08, 0x03, 0x32, 0x39, 0x24, 0x2f, + 0x8d, 0x86, 0x9b, 0x90, 0xa1, 0xaa, 0xb7, 0xbc, + 0xd5, 0xde, 0xc3, 0xc8, 0xf9, 0xf2, 0xef, 0xe4, + 0x3d, 0x36, 0x2b, 0x20, 0x11, 0x1a, 0x07, 0x0c, + 0x65, 0x6e, 0x73, 0x78, 0x49, 0x42, 0x5f, 0x54, + 0xf7, 0xfc, 0xe1, 0xea, 0xdb, 0xd0, 0xcd, 0xc6, + 0xaf, 0xa4, 0xb9, 0xb2, 0x83, 0x88, 0x95, 0x9e, + 0x47, 0x4c, 0x51, 0x5a, 0x6b, 0x60, 0x7d, 0x76, + 0x1f, 0x14, 0x09, 0x02, 0x33, 0x38, 0x25, 0x2e, + 0x8c, 0x87, 0x9a, 0x91, 0xa0, 0xab, 0xb6, 0xbd, + 0xd4, 0xdf, 0xc2, 0xc9, 0xf8, 0xf3, 0xee, 0xe5, + 0x3c, 0x37, 0x2a, 0x21, 0x10, 0x1b, 0x06, 0x0d, + 0x64, 0x6f, 0x72, 0x79, 0x48, 0x43, 0x5e, 0x55, + 0x01, 0x0a, 0x17, 0x1c, 0x2d, 0x26, 0x3b, 0x30, + 0x59, 0x52, 0x4f, 0x44, 0x75, 0x7e, 0x63, 0x68, + 0xb1, 0xba, 0xa7, 0xac, 0x9d, 0x96, 0x8b, 0x80, + 0xe9, 0xe2, 0xff, 0xf4, 0xc5, 0xce, 0xd3, 0xd8, + 0x7a, 0x71, 0x6c, 0x67, 0x56, 0x5d, 0x40, 0x4b, + 0x22, 0x29, 0x34, 0x3f, 0x0e, 0x05, 0x18, 0x13, + 0xca, 0xc1, 0xdc, 0xd7, 0xe6, 0xed, 0xf0, 0xfb, + 0x92, 0x99, 0x84, 0x8f, 0xbe, 0xb5, 0xa8, 0xa3 +}; + +static const u8 x_time_d[256] = { + 0x00, 0x0d, 0x1a, 0x17, 0x34, 0x39, 0x2e, 0x23, + 0x68, 0x65, 0x72, 0x7f, 0x5c, 0x51, 0x46, 0x4b, + 0xd0, 0xdd, 0xca, 0xc7, 0xe4, 0xe9, 0xfe, 0xf3, + 0xb8, 0xb5, 0xa2, 0xaf, 0x8c, 0x81, 0x96, 0x9b, + 0xbb, 0xb6, 0xa1, 0xac, 0x8f, 0x82, 0x95, 0x98, + 0xd3, 0xde, 0xc9, 0xc4, 0xe7, 0xea, 0xfd, 0xf0, + 0x6b, 0x66, 0x71, 0x7c, 0x5f, 0x52, 0x45, 0x48, + 0x03, 0x0e, 0x19, 0x14, 0x37, 0x3a, 0x2d, 0x20, + 0x6d, 0x60, 0x77, 0x7a, 0x59, 0x54, 0x43, 0x4e, + 0x05, 0x08, 0x1f, 0x12, 0x31, 0x3c, 0x2b, 0x26, + 0xbd, 0xb0, 0xa7, 0xaa, 0x89, 0x84, 0x93, 0x9e, + 0xd5, 0xd8, 0xcf, 0xc2, 0xe1, 0xec, 0xfb, 0xf6, + 0xd6, 0xdb, 0xcc, 0xc1, 0xe2, 0xef, 0xf8, 0xf5, + 0xbe, 0xb3, 0xa4, 0xa9, 0x8a, 0x87, 0x90, 0x9d, + 0x06, 0x0b, 0x1c, 0x11, 0x32, 0x3f, 0x28, 0x25, + 0x6e, 0x63, 0x74, 0x79, 0x5a, 0x57, 0x40, 0x4d, + 0xda, 0xd7, 0xc0, 0xcd, 0xee, 0xe3, 0xf4, 0xf9, + 0xb2, 0xbf, 0xa8, 0xa5, 0x86, 0x8b, 0x9c, 0x91, + 0x0a, 0x07, 0x10, 0x1d, 0x3e, 0x33, 0x24, 0x29, + 0x62, 0x6f, 0x78, 0x75, 0x56, 0x5b, 0x4c, 0x41, + 0x61, 0x6c, 0x7b, 0x76, 0x55, 0x58, 0x4f, 0x42, + 0x09, 0x04, 0x13, 0x1e, 0x3d, 0x30, 0x27, 0x2a, + 0xb1, 0xbc, 0xab, 0xa6, 0x85, 0x88, 0x9f, 0x92, + 0xd9, 0xd4, 0xc3, 0xce, 0xed, 0xe0, 0xf7, 0xfa, + 0xb7, 0xba, 0xad, 0xa0, 0x83, 0x8e, 0x99, 0x94, + 0xdf, 0xd2, 0xc5, 0xc8, 0xeb, 0xe6, 0xf1, 0xfc, + 0x67, 0x6a, 0x7d, 0x70, 0x53, 0x5e, 0x49, 0x44, + 0x0f, 0x02, 0x15, 0x18, 0x3b, 0x36, 0x21, 0x2c, + 0x0c, 0x01, 0x16, 0x1b, 0x38, 0x35, 0x22, 0x2f, + 0x64, 0x69, 0x7e, 0x73, 0x50, 0x5d, 0x4a, 0x47, + 0xdc, 0xd1, 0xc6, 0xcb, 0xe8, 0xe5, 0xf2, 0xff, + 0xb4, 0xb9, 0xae, 0xa3, 0x80, 0x8d, 0x9a, 0x97 +}; + +static const u8 x_time_e[256] = { + 0x00, 0x0e, 0x1c, 0x12, 0x38, 0x36, 0x24, 0x2a, + 0x70, 0x7e, 0x6c, 0x62, 0x48, 0x46, 0x54, 0x5a, + 0xe0, 0xee, 0xfc, 0xf2, 0xd8, 0xd6, 0xc4, 0xca, + 0x90, 0x9e, 0x8c, 0x82, 0xa8, 0xa6, 0xb4, 0xba, + 0xdb, 0xd5, 0xc7, 0xc9, 0xe3, 0xed, 0xff, 0xf1, + 0xab, 0xa5, 0xb7, 0xb9, 0x93, 0x9d, 0x8f, 0x81, + 0x3b, 0x35, 0x27, 0x29, 0x03, 0x0d, 0x1f, 0x11, + 0x4b, 0x45, 0x57, 0x59, 0x73, 0x7d, 0x6f, 0x61, + 0xad, 0xa3, 0xb1, 0xbf, 0x95, 0x9b, 0x89, 0x87, + 0xdd, 0xd3, 0xc1, 0xcf, 0xe5, 0xeb, 0xf9, 0xf7, + 0x4d, 0x43, 0x51, 0x5f, 0x75, 0x7b, 0x69, 0x67, + 0x3d, 0x33, 0x21, 0x2f, 0x05, 0x0b, 0x19, 0x17, + 0x76, 0x78, 0x6a, 0x64, 0x4e, 0x40, 0x52, 0x5c, + 0x06, 0x08, 0x1a, 0x14, 0x3e, 0x30, 0x22, 0x2c, + 0x96, 0x98, 0x8a, 0x84, 0xae, 0xa0, 0xb2, 0xbc, + 0xe6, 0xe8, 0xfa, 0xf4, 0xde, 0xd0, 0xc2, 0xcc, + 0x41, 0x4f, 0x5d, 0x53, 0x79, 0x77, 0x65, 0x6b, + 0x31, 0x3f, 0x2d, 0x23, 0x09, 0x07, 0x15, 0x1b, + 0xa1, 0xaf, 0xbd, 0xb3, 0x99, 0x97, 0x85, 0x8b, + 0xd1, 0xdf, 0xcd, 0xc3, 0xe9, 0xe7, 0xf5, 0xfb, + 0x9a, 0x94, 0x86, 0x88, 0xa2, 0xac, 0xbe, 0xb0, + 0xea, 0xe4, 0xf6, 0xf8, 0xd2, 0xdc, 0xce, 0xc0, + 0x7a, 0x74, 0x66, 0x68, 0x42, 0x4c, 0x5e, 0x50, + 0x0a, 0x04, 0x16, 0x18, 0x32, 0x3c, 0x2e, 0x20, + 0xec, 0xe2, 0xf0, 0xfe, 0xd4, 0xda, 0xc8, 0xc6, + 0x9c, 0x92, 0x80, 0x8e, 0xa4, 0xaa, 0xb8, 0xb6, + 0x0c, 0x02, 0x10, 0x1e, 0x34, 0x3a, 0x28, 0x26, + 0x7c, 0x72, 0x60, 0x6e, 0x44, 0x4a, 0x58, 0x56, + 0x37, 0x39, 0x2b, 0x25, 0x0f, 0x01, 0x13, 0x1d, + 0x47, 0x49, 0x5b, 0x55, 0x7f, 0x71, 0x63, 0x6d, + 0xd7, 0xd9, 0xcb, 0xc5, 0xef, 0xe1, 0xf3, 0xfd, + 0xa7, 0xa9, 0xbb, 0xb5, 0x9f, 0x91, 0x83, 0x8d +}; + +/* + * Exchanges columns in each of 4 rows + * row0 - unchanged, row1- shifted left 1, + * row2 - shifted left 2 and row3 - shifted left 3 + */ +static void shift_rows(u8 *state) +{ + u8 tmp; + + /* just substitute row 0 */ + state[0] = sbox[state[0]]; + state[4] = sbox[state[4]]; + state[8] = sbox[state[8]]; + state[12] = sbox[state[12]]; + + /* rotate row 1 */ + tmp = sbox[state[1]]; + state[1] = sbox[state[5]]; + state[5] = sbox[state[9]]; + state[9] = sbox[state[13]]; + state[13] = tmp; + + /* rotate row 2 */ + tmp = sbox[state[2]]; + state[2] = sbox[state[10]]; + state[10] = tmp; + tmp = sbox[state[6]]; + state[6] = sbox[state[14]]; + state[14] = tmp; + + /* rotate row 3 */ + tmp = sbox[state[15]]; + state[15] = sbox[state[11]]; + state[11] = sbox[state[7]]; + state[7] = sbox[state[3]]; + state[3] = tmp; +} + +/* + * restores columns in each of 4 rows + * row0 - unchanged, row1- shifted right 1, + * row2 - shifted right 2 and row3 - shifted right 3 + */ +static void inv_shift_rows(u8 *state) +{ + u8 tmp; + + /* restore row 0 */ + state[0] = inv_sbox[state[0]]; + state[4] = inv_sbox[state[4]]; + state[8] = inv_sbox[state[8]]; + state[12] = inv_sbox[state[12]]; + + /* restore row 1 */ + tmp = inv_sbox[state[13]]; + state[13] = inv_sbox[state[9]]; + state[9] = inv_sbox[state[5]]; + state[5] = inv_sbox[state[1]]; + state[1] = tmp; + + /* restore row 2 */ + tmp = inv_sbox[state[2]]; + state[2] = inv_sbox[state[10]]; + state[10] = tmp; + tmp = inv_sbox[state[6]]; + state[6] = inv_sbox[state[14]]; + state[14] = tmp; + + /* restore row 3 */ + tmp = inv_sbox[state[3]]; + state[3] = inv_sbox[state[7]]; + state[7] = inv_sbox[state[11]]; + state[11] = inv_sbox[state[15]]; + state[15] = tmp; +} + +/* recombine and mix each row in a column */ +static void mix_sub_columns(u8 *state) +{ + u8 tmp[4 * AES_STATECOLS]; + + /* mixing column 0 */ + tmp[0] = x2_sbox[state[0]] ^ x3_sbox[state[5]] ^ + sbox[state[10]] ^ sbox[state[15]]; + tmp[1] = sbox[state[0]] ^ x2_sbox[state[5]] ^ + x3_sbox[state[10]] ^ sbox[state[15]]; + tmp[2] = sbox[state[0]] ^ sbox[state[5]] ^ + x2_sbox[state[10]] ^ x3_sbox[state[15]]; + tmp[3] = x3_sbox[state[0]] ^ sbox[state[5]] ^ + sbox[state[10]] ^ x2_sbox[state[15]]; + + /* mixing column 1 */ + tmp[4] = x2_sbox[state[4]] ^ x3_sbox[state[9]] ^ + sbox[state[14]] ^ sbox[state[3]]; + tmp[5] = sbox[state[4]] ^ x2_sbox[state[9]] ^ + x3_sbox[state[14]] ^ sbox[state[3]]; + tmp[6] = sbox[state[4]] ^ sbox[state[9]] ^ + x2_sbox[state[14]] ^ x3_sbox[state[3]]; + tmp[7] = x3_sbox[state[4]] ^ sbox[state[9]] ^ + sbox[state[14]] ^ x2_sbox[state[3]]; + + /* mixing column 2 */ + tmp[8] = x2_sbox[state[8]] ^ x3_sbox[state[13]] ^ + sbox[state[2]] ^ sbox[state[7]]; + tmp[9] = sbox[state[8]] ^ x2_sbox[state[13]] ^ + x3_sbox[state[2]] ^ sbox[state[7]]; + tmp[10] = sbox[state[8]] ^ sbox[state[13]] ^ + x2_sbox[state[2]] ^ x3_sbox[state[7]]; + tmp[11] = x3_sbox[state[8]] ^ sbox[state[13]] ^ + sbox[state[2]] ^ x2_sbox[state[7]]; + + /* mixing column 3 */ + tmp[12] = x2_sbox[state[12]] ^ x3_sbox[state[1]] ^ + sbox[state[6]] ^ sbox[state[11]]; + tmp[13] = sbox[state[12]] ^ x2_sbox[state[1]] ^ + x3_sbox[state[6]] ^ sbox[state[11]]; + tmp[14] = sbox[state[12]] ^ sbox[state[1]] ^ + x2_sbox[state[6]] ^ x3_sbox[state[11]]; + tmp[15] = x3_sbox[state[12]] ^ sbox[state[1]] ^ + sbox[state[6]] ^ x2_sbox[state[11]]; + + memcpy(state, tmp, sizeof(tmp)); +} + +/* restore and un-mix each row in a column */ +static void inv_mix_sub_columns(u8 *state) +{ + u8 tmp[4 * AES_STATECOLS]; + int i; + + /* restore column 0 */ + tmp[0] = x_time_e[state[0]] ^ x_time_b[state[1]] ^ + x_time_d[state[2]] ^ x_time_9[state[3]]; + tmp[5] = x_time_9[state[0]] ^ x_time_e[state[1]] ^ + x_time_b[state[2]] ^ x_time_d[state[3]]; + tmp[10] = x_time_d[state[0]] ^ x_time_9[state[1]] ^ + x_time_e[state[2]] ^ x_time_b[state[3]]; + tmp[15] = x_time_b[state[0]] ^ x_time_d[state[1]] ^ + x_time_9[state[2]] ^ x_time_e[state[3]]; + + /* restore column 1 */ + tmp[4] = x_time_e[state[4]] ^ x_time_b[state[5]] ^ + x_time_d[state[6]] ^ x_time_9[state[7]]; + tmp[9] = x_time_9[state[4]] ^ x_time_e[state[5]] ^ + x_time_b[state[6]] ^ x_time_d[state[7]]; + tmp[14] = x_time_d[state[4]] ^ x_time_9[state[5]] ^ + x_time_e[state[6]] ^ x_time_b[state[7]]; + tmp[3] = x_time_b[state[4]] ^ x_time_d[state[5]] ^ + x_time_9[state[6]] ^ x_time_e[state[7]]; + + /* restore column 2 */ + tmp[8] = x_time_e[state[8]] ^ x_time_b[state[9]] ^ + x_time_d[state[10]] ^ x_time_9[state[11]]; + tmp[13] = x_time_9[state[8]] ^ x_time_e[state[9]] ^ + x_time_b[state[10]] ^ x_time_d[state[11]]; + tmp[2] = x_time_d[state[8]] ^ x_time_9[state[9]] ^ + x_time_e[state[10]] ^ x_time_b[state[11]]; + tmp[7] = x_time_b[state[8]] ^ x_time_d[state[9]] ^ + x_time_9[state[10]] ^ x_time_e[state[11]]; + + /* restore column 3 */ + tmp[12] = x_time_e[state[12]] ^ x_time_b[state[13]] ^ + x_time_d[state[14]] ^ x_time_9[state[15]]; + tmp[1] = x_time_9[state[12]] ^ x_time_e[state[13]] ^ + x_time_b[state[14]] ^ x_time_d[state[15]]; + tmp[6] = x_time_d[state[12]] ^ x_time_9[state[13]] ^ + x_time_e[state[14]] ^ x_time_b[state[15]]; + tmp[11] = x_time_b[state[12]] ^ x_time_d[state[13]] ^ + x_time_9[state[14]] ^ x_time_e[state[15]]; + + for (i = 0; i < 4 * AES_STATECOLS; i++) + state[i] = inv_sbox[tmp[i]]; +} + +/* + * encrypt/decrypt columns of the key + * n.b. you can replace this with byte-wise xor if you wish. + */ +static void add_round_key(u32 *state, u32 *key) +{ + int idx; + + for (idx = 0; idx < 4; idx++) + state[idx] ^= key[idx]; +} + +static u8 rcon[11] = { + 0x00, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36 +}; + +/* produce AES_STATECOLS bytes for each round */ +void aes_expand_key(u8 *key, u8 *expkey) +{ + u8 tmp0, tmp1, tmp2, tmp3, tmp4; + u32 idx; + + memcpy(expkey, key, AES_KEYCOLS * 4); + + for (idx = AES_KEYCOLS; idx < AES_STATECOLS * (AES_ROUNDS + 1); idx++) { + tmp0 = expkey[4*idx - 4]; + tmp1 = expkey[4*idx - 3]; + tmp2 = expkey[4*idx - 2]; + tmp3 = expkey[4*idx - 1]; + if (!(idx % AES_KEYCOLS)) { + tmp4 = tmp3; + tmp3 = sbox[tmp0]; + tmp0 = sbox[tmp1] ^ rcon[idx / AES_KEYCOLS]; + tmp1 = sbox[tmp2]; + tmp2 = sbox[tmp4]; + } else if ((AES_KEYCOLS > 6) && (idx % AES_KEYCOLS == 4)) { + tmp0 = sbox[tmp0]; + tmp1 = sbox[tmp1]; + tmp2 = sbox[tmp2]; + tmp3 = sbox[tmp3]; + } + + expkey[4*idx+0] = expkey[4*idx - 4*AES_KEYCOLS + 0] ^ tmp0; + expkey[4*idx+1] = expkey[4*idx - 4*AES_KEYCOLS + 1] ^ tmp1; + expkey[4*idx+2] = expkey[4*idx - 4*AES_KEYCOLS + 2] ^ tmp2; + expkey[4*idx+3] = expkey[4*idx - 4*AES_KEYCOLS + 3] ^ tmp3; + } +} + +/* encrypt one 128 bit block */ +void aes_encrypt(u8 *in, u8 *expkey, u8 *out) +{ + u8 state[AES_STATECOLS * 4]; + u32 round; + + memcpy(state, in, AES_STATECOLS * 4); + add_round_key((u32 *)state, (u32 *)expkey); + + for (round = 1; round < AES_ROUNDS + 1; round++) { + if (round < AES_ROUNDS) + mix_sub_columns(state); + else + shift_rows(state); + + add_round_key((u32 *)state, + (u32 *)expkey + round * AES_STATECOLS); + } + + memcpy(out, state, sizeof(state)); +} + +void aes_decrypt(u8 *in, u8 *expkey, u8 *out) +{ + u8 state[AES_STATECOLS * 4]; + int round; + + memcpy(state, in, sizeof(state)); + + add_round_key((u32 *)state, + (u32 *)expkey + AES_ROUNDS * AES_STATECOLS); + inv_shift_rows(state); + + for (round = AES_ROUNDS; round--; ) { + add_round_key((u32 *)state, + (u32 *)expkey + round * AES_STATECOLS); + if (round) + inv_mix_sub_columns(state); + } + + memcpy(out, state, sizeof(state)); +} -- cgit v1.3.1 From 0e35ad053f239912ebf879c20d44689ff0834c03 Mon Sep 17 00:00:00 2001 From: Jimmy Zhang Date: Mon, 2 Apr 2012 13:18:52 +0000 Subject: tegra: Add EMC support for optimal memory timings Add support for setting up the memory controller parameters. Boards can set up an appropriate table in the device tree. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/cpu/armv7/tegra2/Makefile | 1 + arch/arm/cpu/armv7/tegra2/emc.c | 286 +++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra2/emc.h | 113 +++++++++++++ include/fdtdec.h | 2 + lib/fdtdec.c | 2 + 5 files changed, 404 insertions(+) create mode 100644 arch/arm/cpu/armv7/tegra2/emc.c create mode 100644 arch/arm/include/asm/arch-tegra2/emc.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index e9ac6c9a710..dcd6329405e 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -34,6 +34,7 @@ LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o COBJS-y := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o COBJS := $(COBJS-y) diff --git a/arch/arm/cpu/armv7/tegra2/emc.c b/arch/arm/cpu/armv7/tegra2/emc.c new file mode 100644 index 00000000000..c0e5c565f1f --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/emc.c @@ -0,0 +1,286 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The EMC registers have shadow registers. When the EMC clock is updated + * in the clock controller, the shadow registers are copied to the active + * registers, allowing glitchless memory bus frequency changes. + * This function updates the shadow registers for a new clock frequency, + * and relies on the clock lock on the emc clock to avoid races between + * multiple frequency changes + */ + +/* + * This table defines the ordering of the registers provided to + * tegra_set_mmc() + * TODO: Convert to fdt version once available + */ +static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = { + 0x2c, /* RC */ + 0x30, /* RFC */ + 0x34, /* RAS */ + 0x38, /* RP */ + 0x3c, /* R2W */ + 0x40, /* W2R */ + 0x44, /* R2P */ + 0x48, /* W2P */ + 0x4c, /* RD_RCD */ + 0x50, /* WR_RCD */ + 0x54, /* RRD */ + 0x58, /* REXT */ + 0x5c, /* WDV */ + 0x60, /* QUSE */ + 0x64, /* QRST */ + 0x68, /* QSAFE */ + 0x6c, /* RDV */ + 0x70, /* REFRESH */ + 0x74, /* BURST_REFRESH_NUM */ + 0x78, /* PDEX2WR */ + 0x7c, /* PDEX2RD */ + 0x80, /* PCHG2PDEN */ + 0x84, /* ACT2PDEN */ + 0x88, /* AR2PDEN */ + 0x8c, /* RW2PDEN */ + 0x90, /* TXSR */ + 0x94, /* TCKE */ + 0x98, /* TFAW */ + 0x9c, /* TRPAB */ + 0xa0, /* TCLKSTABLE */ + 0xa4, /* TCLKSTOP */ + 0xa8, /* TREFBW */ + 0xac, /* QUSE_EXTRA */ + 0x114, /* FBIO_CFG6 */ + 0xb0, /* ODT_WRITE */ + 0xb4, /* ODT_READ */ + 0x104, /* FBIO_CFG5 */ + 0x2bc, /* CFG_DIG_DLL */ + 0x2c0, /* DLL_XFORM_DQS */ + 0x2c4, /* DLL_XFORM_QUSE */ + 0x2e0, /* ZCAL_REF_CNT */ + 0x2e4, /* ZCAL_WAIT_CNT */ + 0x2a8, /* AUTO_CAL_INTERVAL */ + 0x2d0, /* CFG_CLKTRIM_0 */ + 0x2d4, /* CFG_CLKTRIM_1 */ + 0x2d8, /* CFG_CLKTRIM_2 */ +}; + +struct emc_ctlr *emc_get_controller(const void *blob) +{ + fdt_addr_t addr; + int node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC); + if (node > 0) { + addr = fdtdec_get_addr(blob, node, "reg"); + if (addr != FDT_ADDR_T_NONE) + return (struct emc_ctlr *)addr; + } + return NULL; +} + +/* Error codes we use */ +enum { + ERR_NO_EMC_NODE = -10, + ERR_NO_EMC_REG, + ERR_NO_FREQ, + ERR_FREQ_NOT_FOUND, + ERR_BAD_REGS, + ERR_NO_RAM_CODE, + ERR_RAM_CODE_NOT_FOUND, +}; + +/** + * Find EMC tables for the given ram code. + * + * The tegra EMC binding has two options, one using the ram code and one not. + * We detect which is in use by looking for the nvidia,use-ram-code property. + * If this is not present, then the EMC tables are directly below 'node', + * otherwise we select the correct emc-tables subnode based on the 'ram_code' + * value. + * + * @param blob Device tree blob + * @param node EMC node (nvidia,tegra20-emc compatible string) + * @param ram_code RAM code to select (0-3, or -1 if unknown) + * @return 0 if ok, otherwise a -ve ERR_ code (see enum above) + */ +static int find_emc_tables(const void *blob, int node, int ram_code) +{ + int need_ram_code; + int depth; + int offset; + + /* If we are using RAM codes, scan through the tables for our code */ + need_ram_code = fdtdec_get_bool(blob, node, "nvidia,use-ram-code"); + if (!need_ram_code) + return node; + if (ram_code == -1) { + debug("%s: RAM code required but not supplied\n", __func__); + return ERR_NO_RAM_CODE; + } + + offset = node; + depth = 0; + do { + /* + * Sadly there is no compatible string so we cannot use + * fdtdec_next_compatible_subnode(). + */ + offset = fdt_next_node(blob, offset, &depth); + if (depth <= 0) + break; + + /* Make sure this is a direct subnode */ + if (depth != 1) + continue; + if (strcmp("emc-tables", fdt_get_name(blob, offset, NULL))) + continue; + + if (fdtdec_get_int(blob, offset, "nvidia,ram-code", -1) + == ram_code) + return offset; + } while (1); + + debug("%s: Could not find tables for RAM code %d\n", __func__, + ram_code); + return ERR_RAM_CODE_NOT_FOUND; +} + +/** + * Decode the EMC node of the device tree, returning a pointer to the emc + * controller and the table to be used for the given rate. + * + * @param blob Device tree blob + * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) + * @param emcp Returns address of EMC controller registers + * @param tablep Returns pointer to table to program into EMC. There are + * TEGRA_EMC_NUM_REGS entries, destined for offsets as per the + * emc_reg_addr array. + * @return 0 if ok, otherwise a -ve error code which will allow someone to + * figure out roughly what went wrong by looking at this code. + */ +static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp, + const u32 **tablep) +{ + struct apb_misc_pp_ctlr *pp = + (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE; + int ram_code; + int depth; + int node; + + ram_code = (readl(&pp->strapping_opt_a) & RAM_CODE_MASK) + >> RAM_CODE_SHIFT; + /* + * The EMC clock rate is twice the bus rate, and the bus rate is + * measured in kHz + */ + rate = rate / 2 / 1000; + + node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC); + if (node < 0) { + debug("%s: No EMC node found in FDT\n", __func__); + return ERR_NO_EMC_NODE; + } + *emcp = (struct emc_ctlr *)fdtdec_get_addr(blob, node, "reg"); + if (*emcp == (struct emc_ctlr *)FDT_ADDR_T_NONE) { + debug("%s: No EMC node reg property\n", __func__); + return ERR_NO_EMC_REG; + } + + /* Work out the parent node which contains our EMC tables */ + node = find_emc_tables(blob, node, ram_code & 3); + if (node < 0) + return node; + + depth = 0; + for (;;) { + int node_rate; + + node = fdtdec_next_compatible_subnode(blob, node, + COMPAT_NVIDIA_TEGRA20_EMC_TABLE, &depth); + if (node < 0) + break; + node_rate = fdtdec_get_int(blob, node, "clock-frequency", -1); + if (node_rate == -1) { + debug("%s: Missing clock-frequency\n", __func__); + return ERR_NO_FREQ; /* we expect this property */ + } + + if (node_rate == rate) + break; + } + if (node < 0) { + debug("%s: No node found for clock frequency %d\n", __func__, + rate); + return ERR_FREQ_NOT_FOUND; + } + + *tablep = fdtdec_locate_array(blob, node, "nvidia,emc-registers", + TEGRA_EMC_NUM_REGS); + if (!*tablep) { + debug("%s: node '%s' array missing / wrong size\n", __func__, + fdt_get_name(blob, node, NULL)); + return ERR_BAD_REGS; + } + + /* All seems well */ + return 0; +} + +int tegra_set_emc(const void *blob, unsigned rate) +{ + struct emc_ctlr *emc; + const u32 *table; + int err, i; + + err = decode_emc(blob, rate, &emc, &table); + if (err) { + debug("Warning: no valid EMC (%d), memory timings unset\n", + err); + return err; + } + + debug("%s: Table found, setting EMC values as follows:\n", __func__); + for (i = 0; i < TEGRA_EMC_NUM_REGS; i++) { + u32 value = fdt32_to_cpu(table[i]); + u32 addr = (uintptr_t)emc + emc_reg_addr[i]; + + debug(" %#x: %#x\n", addr, value); + writel(value, addr); + } + + /* trigger emc with new settings */ + clock_adjust_periph_pll_div(PERIPH_ID_EMC, CLOCK_ID_MEMORY, + clock_get_rate(CLOCK_ID_MEMORY), NULL); + debug("EMC clock set to %lu\n", + clock_get_periph_rate(PERIPH_ID_EMC, CLOCK_ID_MEMORY)); + + return 0; +} diff --git a/arch/arm/include/asm/arch-tegra2/emc.h b/arch/arm/include/asm/arch-tegra2/emc.h new file mode 100644 index 00000000000..deb3d36ed22 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/emc.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ARCH_EMC_H_ +#define _ARCH_EMC_H_ + +#include + +#define TEGRA_EMC_NUM_REGS 46 + +/* EMC Registers */ +struct emc_ctlr { + u32 cfg; /* 0x00: EMC_CFG */ + u32 reserved0[3]; /* 0x04 ~ 0x0C */ + u32 adr_cfg; /* 0x10: EMC_ADR_CFG */ + u32 adr_cfg1; /* 0x14: EMC_ADR_CFG_1 */ + u32 reserved1[2]; /* 0x18 ~ 0x18 */ + u32 refresh_ctrl; /* 0x20: EMC_REFCTRL */ + u32 pin; /* 0x24: EMC_PIN */ + u32 timing_ctrl; /* 0x28: EMC_TIMING_CONTROL */ + u32 rc; /* 0x2C: EMC_RC */ + u32 rfc; /* 0x30: EMC_RFC */ + u32 ras; /* 0x34: EMC_RAS */ + u32 rp; /* 0x38: EMC_RP */ + u32 r2w; /* 0x3C: EMC_R2W */ + u32 w2r; /* 0x40: EMC_W2R */ + u32 r2p; /* 0x44: EMC_R2P */ + u32 w2p; /* 0x48: EMC_W2P */ + u32 rd_rcd; /* 0x4C: EMC_RD_RCD */ + u32 wd_rcd; /* 0x50: EMC_WD_RCD */ + u32 rrd; /* 0x54: EMC_RRD */ + u32 rext; /* 0x58: EMC_REXT */ + u32 wdv; /* 0x5C: EMC_WDV */ + u32 quse; /* 0x60: EMC_QUSE */ + u32 qrst; /* 0x64: EMC_QRST */ + u32 qsafe; /* 0x68: EMC_QSAFE */ + u32 rdv; /* 0x6C: EMC_RDV */ + u32 refresh; /* 0x70: EMC_REFRESH */ + u32 burst_refresh_num; /* 0x74: EMC_BURST_REFRESH_NUM */ + u32 pdex2wr; /* 0x78: EMC_PDEX2WR */ + u32 pdex2rd; /* 0x7c: EMC_PDEX2RD */ + u32 pchg2pden; /* 0x80: EMC_PCHG2PDEN */ + u32 act2pden; /* 0x84: EMC_ACT2PDEN */ + u32 ar2pden; /* 0x88: EMC_AR2PDEN */ + u32 rw2pden; /* 0x8C: EMC_RW2PDEN */ + u32 txsr; /* 0x90: EMC_TXSR */ + u32 tcke; /* 0x94: EMC_TCKE */ + u32 tfaw; /* 0x98: EMC_TFAW */ + u32 trpab; /* 0x9C: EMC_TRPAB */ + u32 tclkstable; /* 0xA0: EMC_TCLKSTABLE */ + u32 tclkstop; /* 0xA4: EMC_TCLKSTOP */ + u32 trefbw; /* 0xA8: EMC_TREFBW */ + u32 quse_extra; /* 0xAC: EMC_QUSE_EXTRA */ + u32 odt_write; /* 0xB0: EMC_ODT_WRITE */ + u32 odt_read; /* 0xB4: EMC_ODT_READ */ + u32 reserved2[5]; /* 0xB8 ~ 0xC8 */ + u32 mrs; /* 0xCC: EMC_MRS */ + u32 emrs; /* 0xD0: EMC_EMRS */ + u32 ref; /* 0xD4: EMC_REF */ + u32 pre; /* 0xD8: EMC_PRE */ + u32 nop; /* 0xDC: EMC_NOP */ + u32 self_ref; /* 0xE0: EMC_SELF_REF */ + u32 dpd; /* 0xE4: EMC_DPD */ + u32 mrw; /* 0xE8: EMC_MRW */ + u32 mrr; /* 0xEC: EMC_MRR */ + u32 reserved3; /* 0xF0: */ + u32 fbio_cfg1; /* 0xF4: EMC_FBIO_CFG1 */ + u32 fbio_dqsib_dly; /* 0xF8: EMC_FBIO_DQSIB_DLY */ + u32 fbio_dqsib_dly_msb; /* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */ + u32 fbio_spare; /* 0x100: SBIO_SPARE */ + /* There are more registers ... */ +}; + +/** + * Set up the EMC for the given rate. The timing parameters are retrieved + * from the device tree "nvidia,tegra20-emc" node and its + * "nvidia,tegra20-emc-table" sub-nodes. + * + * @param blob Device tree blob + * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) + * @return 0 if ok, else -ve error code (look in emc.c to decode it) + */ +int tegra_set_emc(const void *blob, unsigned rate); + +/** + * Get a pointer to the EMC controller from the device tree. + * + * @param blob Device tree blob + * @return pointer to EMC controller + */ +struct emc_ctlr *emc_get_controller(const void *blob); + +#endif diff --git a/include/fdtdec.h b/include/fdtdec.h index 0351a25a98a..49251d59c3d 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -60,6 +60,8 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_USB, /* Tegra2 USB port */ COMPAT_NVIDIA_TEGRA20_I2C, /* Tegra2 i2c */ COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra2 dvc (really just i2c) */ + COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra2 memory controller */ + COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra2 memory timing table */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 76d38089ee3..42c3e893d6a 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -40,6 +40,8 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"), COMPAT(NVIDIA_TEGRA20_I2C, "nvidia,tegra20-i2c"), COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"), + COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"), + COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- cgit v1.3.1 From 649d0ffbc1eca693726937ff40e7d7ab852f4ae9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 2 Apr 2012 13:19:03 +0000 Subject: tegra: Enable LP0 on Seaboard This enables LP0 to support suspend / resume on Seaboard. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/seaboard.h | 8 ++++++++ include/configs/tegra2-common.h | 17 +++++++++++++++++ 2 files changed, 25 insertions(+) (limited to 'include') diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index ae075e786ef..7e7c38ea852 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -25,6 +25,14 @@ #define __CONFIG_H #include + +/* LP0 suspend / resume */ +#define CONFIG_TEGRA2_LP0 +#define CONFIG_AES +#define CONFIG_TEGRA_PMU +#define CONFIG_TPS6586X_POWER +#define CONFIG_TEGRA_CLOCK_SCALING + #include "tegra2-common.h" /* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */ diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 837f859c7cc..c5870dd4be2 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -25,6 +25,14 @@ #define __TEGRA2_COMMON_H #include +/* + * QUOTE(m) will evaluate to a string version of the value of the macro m + * passed in. The extra level of indirection here is to first evaluate the + * macro m before applying the quoting operator. + */ +#define QUOTE_(m) #m +#define QUOTE(m) QUOTE_(m) + /* * High Level Configuration Options */ @@ -50,6 +58,15 @@ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ +#ifdef CONFIG_TEGRA2_LP0 +#define TEGRA_LP0_ADDR 0x1C406000 +#define TEGRA_LP0_SIZE 0x2000 +#define TEGRA_LP0_VEC \ + "lp0_vec=" QUOTE(TEGRA_LP0_SIZE) "@" QUOTE(TEGRA_LP0_ADDR) " " +#else +#define TEGRA_LP0_VEC +#endif + /* Environment */ #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ -- cgit v1.3.1 From bed4d89277629904bfcefa37589c71e4b7424bea Mon Sep 17 00:00:00 2001 From: Anton Staff Date: Tue, 17 Apr 2012 09:01:28 +0000 Subject: fdt: Add fdtdec functions to read byte array Sometimes we don't need a full cell for each value. This provides a simple function to read a byte array, both with and without copying it. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/fdtdec.h | 32 ++++++++++++++++++++++++++++++++ lib/fdtdec.c | 24 ++++++++++++++++++++++++ 2 files changed, 56 insertions(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 49251d59c3d..b6db0278bdc 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -349,3 +349,35 @@ int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name, * @return 0 if all ok or gpio was FDT_GPIO_NONE; -1 on error */ int fdtdec_setup_gpio(struct fdt_gpio_state *gpio); + +/* + * Look up a property in a node and return its contents in a byte + * array of given length. The property must have at least enough data for + * the array (count bytes). It may have more, but this will be ignored. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param array array to fill with data + * @param count number of array elements + * @return 0 if ok, or -FDT_ERR_MISSING if the property is not found, + * or -FDT_ERR_BADLAYOUT if not enough data + */ +int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name, + u8 *array, int count); + +/** + * Look up a property in a node and return a pointer to its contents as a + * byte array of given length. The property must have at least enough data + * for the array (count bytes). It may have more, but this will be ignored. + * The data is not copied. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param count number of array elements + * @return pointer to byte array if found, or NULL if the property is not + * found or there is not enough data + */ +const u8 *fdtdec_locate_byte_array(const void *blob, int node, + const char *prop_name, int count); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 42c3e893d6a..ba5c591489a 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -476,3 +476,27 @@ int fdtdec_setup_gpio(struct fdt_gpio_state *gpio) return -1; return 0; } + +int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name, + u8 *array, int count) +{ + const u8 *cell; + int err; + + cell = get_prop_check_min_len(blob, node, prop_name, count, &err); + if (!err) + memcpy(array, cell, count); + return err; +} + +const u8 *fdtdec_locate_byte_array(const void *blob, int node, + const char *prop_name, int count) +{ + const u8 *cell; + int err; + + cell = get_prop_check_min_len(blob, node, prop_name, count, &err); + if (err) + return NULL; + return cell; +} -- cgit v1.3.1 From d81e270d95da63e1ff5147dd9ba0a9d99e8974af Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 17 Apr 2012 09:01:29 +0000 Subject: input: Add linux/input.h for key code support We want to able to decode Linux fdt keymaps, so bring part of this enormous header file over to U-Boot. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/linux/input.h | 155 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100644 include/linux/input.h (limited to 'include') diff --git a/include/linux/input.h b/include/linux/input.h new file mode 100644 index 00000000000..44aec763dcf --- /dev/null +++ b/include/linux/input.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 1999-2002 Vojtech Pavlik + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ + +#ifndef _LINUX_INPUT_H +#define _LINUX_INPUT_H + +/* + * Keys and buttons + * + * Most of the keys/buttons are modeled after USB HUT 1.12 + * (see http://www.usb.org/developers/hidpage). + * Abbreviations in the comments: + * AC - Application Control + * AL - Application Launch Button + * SC - System Control + */ + +#define KEY_RESERVED 0 +#define KEY_ESC 1 +#define KEY_1 2 +#define KEY_2 3 +#define KEY_3 4 +#define KEY_4 5 +#define KEY_5 6 +#define KEY_6 7 +#define KEY_7 8 +#define KEY_8 9 +#define KEY_9 10 +#define KEY_0 11 +#define KEY_MINUS 12 +#define KEY_EQUAL 13 +#define KEY_BACKSPACE 14 +#define KEY_TAB 15 +#define KEY_Q 16 +#define KEY_W 17 +#define KEY_E 18 +#define KEY_R 19 +#define KEY_T 20 +#define KEY_Y 21 +#define KEY_U 22 +#define KEY_I 23 +#define KEY_O 24 +#define KEY_P 25 +#define KEY_LEFTBRACE 26 +#define KEY_RIGHTBRACE 27 +#define KEY_ENTER 28 +#define KEY_LEFTCTRL 29 +#define KEY_A 30 +#define KEY_S 31 +#define KEY_D 32 +#define KEY_F 33 +#define KEY_G 34 +#define KEY_H 35 +#define KEY_J 36 +#define KEY_K 37 +#define KEY_L 38 +#define KEY_SEMICOLON 39 +#define KEY_APOSTROPHE 40 +#define KEY_GRAVE 41 +#define KEY_LEFTSHIFT 42 +#define KEY_BACKSLASH 43 +#define KEY_Z 44 +#define KEY_X 45 +#define KEY_C 46 +#define KEY_V 47 +#define KEY_B 48 +#define KEY_N 49 +#define KEY_M 50 +#define KEY_COMMA 51 +#define KEY_DOT 52 +#define KEY_SLASH 53 +#define KEY_RIGHTSHIFT 54 +#define KEY_KPASTERISK 55 +#define KEY_LEFTALT 56 +#define KEY_SPACE 57 +#define KEY_CAPSLOCK 58 +#define KEY_F1 59 +#define KEY_F2 60 +#define KEY_F3 61 +#define KEY_F4 62 +#define KEY_F5 63 +#define KEY_F6 64 +#define KEY_F7 65 +#define KEY_F8 66 +#define KEY_F9 67 +#define KEY_F10 68 +#define KEY_NUMLOCK 69 +#define KEY_SCROLLLOCK 70 +#define KEY_KP7 71 +#define KEY_KP8 72 +#define KEY_KP9 73 +#define KEY_KPMINUS 74 +#define KEY_KP4 75 +#define KEY_KP5 76 +#define KEY_KP6 77 +#define KEY_KPPLUS 78 +#define KEY_KP1 79 +#define KEY_KP2 80 +#define KEY_KP3 81 +#define KEY_KP0 82 +#define KEY_KPDOT 83 + +#define KEY_ZENKAKUHANKAKU 85 +#define KEY_102ND 86 +#define KEY_F11 87 +#define KEY_F12 88 +#define KEY_RO 89 +#define KEY_KATAKANA 90 +#define KEY_HIRAGANA 91 +#define KEY_HENKAN 92 +#define KEY_KATAKANAHIRAGANA 93 +#define KEY_MUHENKAN 94 +#define KEY_KPJPCOMMA 95 +#define KEY_KPENTER 96 +#define KEY_RIGHTCTRL 97 +#define KEY_KPSLASH 98 +#define KEY_SYSRQ 99 +#define KEY_RIGHTALT 100 +#define KEY_LINEFEED 101 +#define KEY_HOME 102 +#define KEY_UP 103 +#define KEY_PAGEUP 104 +#define KEY_LEFT 105 +#define KEY_RIGHT 106 +#define KEY_END 107 +#define KEY_DOWN 108 +#define KEY_PAGEDOWN 109 +#define KEY_INSERT 110 +#define KEY_DELETE 111 +#define KEY_MACRO 112 +#define KEY_MUTE 113 +#define KEY_VOLUMEDOWN 114 +#define KEY_VOLUMEUP 115 +#define KEY_POWER 116 /* SC System Power Down */ +#define KEY_KPEQUAL 117 +#define KEY_KPPLUSMINUS 118 +#define KEY_PAUSE 119 +#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ + +#define KEY_KPCOMMA 121 +#define KEY_HANGEUL 122 +#define KEY_HANGUEL KEY_HANGEUL +#define KEY_HANJA 123 +#define KEY_YEN 124 +#define KEY_LEFTMETA 125 +#define KEY_RIGHTMETA 126 +#define KEY_COMPOSE 127 +#define KEY_FN 0x1d0 + +#endif -- cgit v1.3.1 From 9bc590e5119f38fd822dedb16e3e0e2363f09756 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 17 Apr 2012 09:01:30 +0000 Subject: input: Add generic keyboard input handler Add a module which understands converting key codes (or scan codes) to ASCII characters. It includes FIFO support and can call back to drivers to read new characters when its FIFO is empty. Keycode maps are provided for un-modified, shift and ctrl keys. The plan is to use this module where such mapping is required. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- drivers/input/Makefile | 1 + drivers/input/input.c | 430 +++++++++++++++++++++++++++++++++++++++++++++++++ include/input.h | 147 +++++++++++++++++ 3 files changed, 578 insertions(+) create mode 100644 drivers/input/input.c create mode 100644 include/input.h (limited to 'include') diff --git a/drivers/input/Makefile b/drivers/input/Makefile index 1f4dad35b53..d06acb9c95b 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -30,6 +30,7 @@ ifdef CONFIG_PS2KBD COBJS-y += keyboard.o pc_keyb.o COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o endif +COBJS-y += input.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/input/input.c b/drivers/input/input.c new file mode 100644 index 00000000000..4eadd773b4f --- /dev/null +++ b/drivers/input/input.c @@ -0,0 +1,430 @@ +/* + * Translate key codes into ASCII + * + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2004 DENX Software Engineering, Wolfgang Denk, wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +enum { + /* These correspond to the lights on the keyboard */ + FLAG_NUM_LOCK = 1 << 0, + FLAG_CAPS_LOCK = 1 << 1, + FLAG_SCROLL_LOCK = 1 << 2, + + /* Special flag ORed with key code to indicate release */ + KEY_RELEASE = 1 << 15, + KEY_MASK = 0xfff, +}; + +/* + * These takes map key codes to ASCII. 0xff means no key, or special key. + * Three tables are provided - one for plain keys, one for when the shift + * 'modifier' key is pressed and one for when the ctrl modifier key is + * pressed. + */ +static const uchar kbd_plain_xlate[] = { + 0xff, 0x1b, '1', '2', '3', '4', '5', '6', + '7', '8', '9', '0', '-', '=', '\b', '\t', /* 0x00 - 0x0f */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', + 'o', 'p', '[', ']', '\r', 0xff, 'a', 's', /* 0x10 - 0x1f */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', + '\'', '`', 0xff, '\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */ + 'b', 'n', 'm', ',' , '.', '/', 0xff, 0xff, 0xff, + ' ', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x30 - 0x3f */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '7', + '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.', 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x50 - 0x5F */ + '\r', 0xff, 0xff +}; + +static unsigned char kbd_shift_xlate[] = { + 0xff, 0x1b, '!', '@', '#', '$', '%', '^', + '&', '*', '(', ')', '_', '+', '\b', '\t', /* 0x00 - 0x0f */ + 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', + 'O', 'P', '{', '}', '\r', 0xff, 'A', 'S', /* 0x10 - 0x1f */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', + '"', '~', 0xff, '|', 'Z', 'X', 'C', 'V', /* 0x20 - 0x2f */ + 'B', 'N', 'M', '<', '>', '?', 0xff, 0xff, 0xff, + ' ', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x30 - 0x3f */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '7', + '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.', 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x50 - 0x5F */ + '\r', 0xff, 0xff +}; + +static unsigned char kbd_ctrl_xlate[] = { + 0xff, 0x1b, '1', 0x00, '3', '4', '5', 0x1E, + '7', '8', '9', '0', 0x1F, '=', '\b', '\t', /* 0x00 - 0x0f */ + 0x11, 0x17, 0x05, 0x12, 0x14, 0x18, 0x15, 0x09, + 0x0f, 0x10, 0x1b, 0x1d, '\n', 0xff, 0x01, 0x13, /* 0x10 - 0x1f */ + 0x04, 0x06, 0x08, 0x09, 0x0a, 0x0b, 0x0c, ';', + '\'', '~', 0x00, 0x1c, 0x1a, 0x18, 0x03, 0x16, /* 0x20 - 0x2f */ + 0x02, 0x0e, 0x0d, '<', '>', '?', 0xff, 0xff, + 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x30 - 0x3f */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '7', + '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.', 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x50 - 0x5F */ + '\r', 0xff, 0xff +}; + + +int input_queue_ascii(struct input_config *config, int ch) +{ + if (config->fifo_in + 1 == INPUT_BUFFER_LEN) { + if (!config->fifo_out) + return -1; /* buffer full */ + else + config->fifo_in = 0; + } else { + if (config->fifo_in + 1 == config->fifo_out) + return -1; /* buffer full */ + config->fifo_in++; + } + config->fifo[config->fifo_in] = (uchar)ch; + + return 0; +} + +int input_tstc(struct input_config *config) +{ + if (config->fifo_in == config->fifo_out && config->read_keys) { + if (!(*config->read_keys)(config)) + return 0; + } + return config->fifo_in != config->fifo_out; +} + +int input_getc(struct input_config *config) +{ + int err = 0; + + while (config->fifo_in == config->fifo_out) { + if (config->read_keys) + err = (*config->read_keys)(config); + if (err) + return -1; + } + + if (++config->fifo_out == INPUT_BUFFER_LEN) + config->fifo_out = 0; + + return config->fifo[config->fifo_out]; +} + +/** + * Process a modifier/special key press or release and decide which key + * translation array should be used as a result. + * + * TODO: Should keep track of modifier press/release + * + * @param config Input state + * @param key Key code to process + * @param release 0 if a press, 1 if a release + * @return pointer to keycode->ascii translation table that should be used + */ +static struct input_key_xlate *process_modifier(struct input_config *config, + int key, int release) +{ + struct input_key_xlate *table; + int flip = -1; + int i; + + /* Start with the main table, and see what modifiers change it */ + assert(config->num_tables > 0); + table = &config->table[0]; + for (i = 1; i < config->num_tables; i++) { + struct input_key_xlate *tab = &config->table[i]; + + if (key == tab->left_keycode || key == tab->right_keycode) + table = tab; + } + + /* Handle the lighted keys */ + if (!release) { + switch (key) { + case KEY_SCROLLLOCK: + flip = FLAG_SCROLL_LOCK; + break; + case KEY_NUMLOCK: + flip = FLAG_NUM_LOCK; + break; + case KEY_CAPSLOCK: + flip = FLAG_CAPS_LOCK; + break; + } + } + + if (flip != -1) { + int leds = 0; + + config->leds ^= flip; + if (config->flags & FLAG_NUM_LOCK) + leds |= INPUT_LED_NUM; + if (config->flags & FLAG_CAPS_LOCK) + leds |= INPUT_LED_CAPS; + if (config->flags & FLAG_SCROLL_LOCK) + leds |= INPUT_LED_SCROLL; + config->leds = leds; + } + + return table; +} + +/** + * Search an int array for a key value + * + * @param array Array to search + * @param count Number of elements in array + * @param key Key value to find + * @return element where value was first found, -1 if none + */ +static int array_search(int *array, int count, int key) +{ + int i; + + for (i = 0; i < count; i++) { + if (array[i] == key) + return i; + } + + return -1; +} + +/** + * Sort an array so that those elements that exist in the ordering are + * first in the array, and in the same order as the ordering. The algorithm + * is O(count * ocount) and designed for small arrays. + * + * TODO: Move this to common / lib? + * + * @param dest Array with elements to sort, also destination array + * @param count Number of elements to sort + * @param order Array containing ordering elements + * @param ocount Number of ordering elements + * @return number of elements in dest that are in order (these will be at the + * start of dest). + */ +static int sort_array_by_ordering(int *dest, int count, int *order, + int ocount) +{ + int temp[count]; + int dest_count; + int same; /* number of elements which are the same */ + int i; + + /* setup output items, copy items to be sorted into our temp area */ + memcpy(temp, dest, count * sizeof(*dest)); + dest_count = 0; + + /* work through the ordering, move over the elements we agree on */ + for (i = 0; i < ocount; i++) { + if (array_search(temp, count, order[i]) != -1) + dest[dest_count++] = order[i]; + } + same = dest_count; + + /* now move over the elements that are not in the ordering */ + for (i = 0; i < count; i++) { + if (array_search(order, ocount, temp[i]) == -1) + dest[dest_count++] = temp[i]; + } + assert(dest_count == count); + return same; +} + +/** + * Check a list of key codes against the previous key scan + * + * Given a list of new key codes, we check how many of these are the same + * as last time. + * + * @param config Input state + * @param keycode List of key codes to examine + * @param num_keycodes Number of key codes + * @param same Returns number of key codes which are the same + */ +static int input_check_keycodes(struct input_config *config, + int keycode[], int num_keycodes, int *same) +{ + /* Select the 'plain' xlate table to start with */ + if (!config->num_tables) { + debug("%s: No xlate tables: cannot decode keys\n", __func__); + return -1; + } + + /* sort the keycodes into the same order as the previous ones */ + *same = sort_array_by_ordering(keycode, num_keycodes, + config->prev_keycodes, config->num_prev_keycodes); + + memcpy(config->prev_keycodes, keycode, num_keycodes * sizeof(int)); + config->num_prev_keycodes = num_keycodes; + + return *same != num_keycodes; +} + +/** + * Convert a list of key codes into ASCII + * + * You must call input_check_keycodes() before this. It turns the keycode + * list into a list of ASCII characters which are ready to send to the + * input layer. + * + * Characters which were seen last time do not generate fresh ASCII output. + * + * @param config Input state + * @param keycode List of key codes to examine + * @param num_keycodes Number of key codes + * @param same Number of key codes which are the same + */ +static int input_keycodes_to_ascii(struct input_config *config, + int keycode[], int num_keycodes, char output_ch[], int same) +{ + struct input_key_xlate *table; + int ch_count; + int i; + + table = &config->table[0]; + + /* deal with modifiers first */ + for (i = 0; i < num_keycodes; i++) { + int key = keycode[i] & KEY_MASK; + + if (key >= table->num_entries || table->xlate[key] == 0xff) { + table = process_modifier(config, key, + keycode[i] & KEY_RELEASE); + } + } + + /* now find normal keys */ + for (i = ch_count = 0; i < num_keycodes; i++) { + int key = keycode[i]; + + if (key < table->num_entries && i >= same) { + int ch = table->xlate[key]; + + /* If a normal key with an ASCII value, add it! */ + if (ch != 0xff) + output_ch[ch_count++] = (uchar)ch; + } + } + + /* ok, so return keys */ + return ch_count; +} + +int input_send_keycodes(struct input_config *config, + int keycode[], int num_keycodes) +{ + char ch[num_keycodes]; + int count, i, same = 0; + int is_repeat = 0; + unsigned delay_ms; + + config->modifiers = 0; + if (!input_check_keycodes(config, keycode, num_keycodes, &same)) { + /* + * Same as last time - is it time for another repeat? + * TODO(sjg@chromium.org) We drop repeats here and since + * the caller may not call in again for a while, our + * auto-repeat speed is not quite correct. We should + * insert another character if we later realise that we + * have missed a repeat slot. + */ + is_repeat = (int)get_timer(config->next_repeat_ms) >= 0; + if (!is_repeat) + return 0; + } + + count = input_keycodes_to_ascii(config, keycode, num_keycodes, + ch, is_repeat ? 0 : same); + for (i = 0; i < count; i++) + input_queue_ascii(config, ch[i]); + delay_ms = is_repeat ? + config->repeat_rate_ms : + config->repeat_delay_ms; + + config->next_repeat_ms = get_timer(0) + delay_ms; + return 0; +} + +int input_add_table(struct input_config *config, int left_keycode, + int right_keycode, const uchar *xlate, int num_entries) +{ + struct input_key_xlate *table; + + if (config->num_tables == INPUT_MAX_MODIFIERS) { + debug("%s: Too many modifier tables\n", __func__); + return -1; + } + + table = &config->table[config->num_tables++]; + table->left_keycode = left_keycode; + table->right_keycode = right_keycode; + table->xlate = xlate; + table->num_entries = num_entries; + + return 0; +} + +int input_init(struct input_config *config, int leds, int repeat_delay_ms, + int repeat_rate_ms) +{ + memset(config, '\0', sizeof(*config)); + config->leds = leds; + config->repeat_delay_ms = repeat_delay_ms; + config->repeat_rate_ms = repeat_rate_ms; + if (input_add_table(config, -1, -1, + kbd_plain_xlate, ARRAY_SIZE(kbd_plain_xlate)) || + input_add_table(config, KEY_LEFTSHIFT, KEY_RIGHTSHIFT, + kbd_shift_xlate, ARRAY_SIZE(kbd_shift_xlate)) || + input_add_table(config, KEY_LEFTCTRL, KEY_RIGHTCTRL, + kbd_ctrl_xlate, ARRAY_SIZE(kbd_ctrl_xlate))) { + debug("%s: Could not add modifier tables\n", __func__); + return -1; + } + + return 0; +} + +int input_stdio_register(struct stdio_dev *dev) +{ + int error; + + error = stdio_register(dev); + + /* check if this is the standard input device */ + if (!error && strcmp(getenv("stdin"), dev->name) == 0) { + /* reassign the console */ + if (OVERWRITE_CONSOLE || + console_assign(stdin, dev->name)) + return -1; + } + + return 0; +} diff --git a/include/input.h b/include/input.h new file mode 100644 index 00000000000..31b1ef96032 --- /dev/null +++ b/include/input.h @@ -0,0 +1,147 @@ +/* + * Keyboard input helper functions (too small to be called a layer) + * + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _INPUT_H +#define _INPUT_H + +enum { + INPUT_MAX_MODIFIERS = 4, + INPUT_BUFFER_LEN = 16, +}; + +enum { + /* Keyboard LEDs */ + INPUT_LED_SCROLL = 1 << 0, + INPUT_LED_CAPS = 1 << 1, + INPUT_LED_NUM = 1 << 2, +}; + +/* + * This table translates key codes to ASCII. Most of the entries are ASCII + * codes, but entries after KEY_FIRST_MOD indicate that this key is a + * modifier key, like shift, ctrl. KEY_FIRST_MOD + MOD_SHIFT is the shift + * key, for example. + */ +struct input_key_xlate { + /* keycode of the modifiers which select this table, -1 if none */ + int left_keycode; + int right_keycode; + const uchar *xlate; /* keycode to ASCII table */ + int num_entries; /* number of entries in this table */ +}; + +struct input_config { + uchar fifo[INPUT_BUFFER_LEN]; + int fifo_in, fifo_out; + + /* Which modifiers are active (1 bit for each MOD_... value) */ + uchar modifiers; + uchar flags; /* active state keys (FLAGS_...) */ + uchar leds; /* active LEDS (INPUT_LED_...) */ + uchar num_tables; /* number of modifier tables */ + int prev_keycodes[INPUT_BUFFER_LEN]; /* keys held last time */ + int num_prev_keycodes; /* number of prev keys */ + struct input_key_xlate table[INPUT_MAX_MODIFIERS]; + + /** + * Function the input helper calls to scan the keyboard + * + * @param config Input state + * @return 0 if no keys read, otherwise number of keys read, or 1 if + * unknown + */ + int (*read_keys)(struct input_config *config); + unsigned int next_repeat_ms; /* Next time we repeat a key */ + unsigned int repeat_delay_ms; /* Time before autorepeat starts */ + unsigned int repeat_rate_ms; /* Autorepeat rate in ms */ +}; + +struct stdio_dev; + +/** + * Convert a list of key codes into ASCII and send them + * + * @param config Input state + * @param keycode List of key codes to examine + * @param num_keycodes Number of key codes + */ +int input_send_keycodes(struct input_config *config, int keycode[], int count); + +/** + * Add a new key translation table to the input + * + * @param config Input state + * @param left_keycode Key to hold to get into this table + * @param right_keycode Another key to hold to get into this table + * @param xlate Conversion table from key codes to ASCII + * @param num_entries Number of entries in xlate table + */ +int input_add_table(struct input_config *config, int left_keycode, + int right_keycode, const uchar *xlate, int num_entries); + +/** + * Test if keys are available to be read + * + * @param config Input state + * @return 0 if no keys available, 1 if keys are available + */ +int input_tstc(struct input_config *config); + +/** + * Read a key + * + * TODO: U-Boot wants 0 for no key, but Ctrl-@ is a valid key... + * + * @param config Input state + * @return key, or 0 if no key, or -1 if error + */ +int input_getc(struct input_config *config); + +/** + * Register a new device with stdio and switch to it if wanted + * + * @param dev Pointer to device + * @return 0 if ok, -1 on error + */ +int input_stdio_register(struct stdio_dev *dev); + +/** + * Set up the input handler with basic key maps. + * + * @param config Input state + * @param leds Initial LED value (INPUT_LED_ mask), 0 suggested + * @param repeat_delay_ms Delay before key auto-repeat starts (in ms) + * @param repeat_rate_ms Delay between successive key repeats (in ms) + * @return 0 if ok, -1 on error + */ +int input_init(struct input_config *config, int leds, int repeat_delay_ms, + int repeat_rate_ms); + +#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +extern int overwrite_console(void); +#define OVERWRITE_CONSOLE overwrite_console() +#else +#define OVERWRITE_CONSOLE 0 +#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */ + +#endif -- cgit v1.3.1 From 92c27c5193154465df03a4713b1a5323bb18506b Mon Sep 17 00:00:00 2001 From: Bernie Thompson Date: Tue, 17 Apr 2012 09:01:31 +0000 Subject: input: Add support for keyboard matrix decoding from an fdt Matrix keyboards require a key map to be set up, and must also deal with key ghosting. Create a keyboard matrix management implementation which can be leveraged by various keyboard drivers. This includes code to read the keymap from the FDT and perform debouncing. Signed-off-by: Bernie Thompson Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- drivers/input/Makefile | 2 + drivers/input/key_matrix.c | 208 +++++++++++++++++++++++++++++++++++++++++++++ include/key_matrix.h | 99 +++++++++++++++++++++ 3 files changed, 309 insertions(+) create mode 100644 drivers/input/key_matrix.c create mode 100644 include/key_matrix.h (limited to 'include') diff --git a/drivers/input/Makefile b/drivers/input/Makefile index d06acb9c95b..5c831b26116 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -26,11 +26,13 @@ include $(TOPDIR)/config.mk LIB := $(obj)libinput.o COBJS-$(CONFIG_I8042_KBD) += i8042.o +COBJS-$(CONFIG_TEGRA2_KEYBOARD) += tegra-kbc.o ifdef CONFIG_PS2KBD COBJS-y += keyboard.o pc_keyb.o COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o endif COBJS-y += input.o +COBJS-$(CONFIG_OF_CONTROL) += key_matrix.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/input/key_matrix.c b/drivers/input/key_matrix.c new file mode 100644 index 00000000000..84b898ff384 --- /dev/null +++ b/drivers/input/key_matrix.c @@ -0,0 +1,208 @@ +/* + * Manage Keyboard Matrices + * + * Copyright (c) 2012 The Chromium OS Authors. + * (C) Copyright 2004 DENX Software Engineering, Wolfgang Denk, wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/** + * Determine if the current keypress configuration can cause key ghosting + * + * We figure this out by seeing if we have two or more keys in the same + * column, as well as two or more keys in the same row. + * + * @param config Keyboard matrix config + * @param keys List of keys to check + * @param valid Number of valid keypresses to check + * @return 0 if no ghosting is possible, 1 if it is + */ +static int has_ghosting(struct key_matrix *config, struct key_matrix_key *keys, + int valid) +{ + int key_in_same_col = 0, key_in_same_row = 0; + int i, j; + + for (i = 0; i < valid; i++) { + /* + * Find 2 keys such that one key is in the same row + * and the other is in the same column as the i-th key. + */ + for (j = i + 1; j < valid; j++) { + if (keys[j].col == keys[i].col) + key_in_same_col = 1; + if (keys[j].row == keys[i].row) + key_in_same_row = 1; + } + } + + if (key_in_same_col && key_in_same_row) + return 1; + else + return 0; +} + +int key_matrix_decode(struct key_matrix *config, struct key_matrix_key keys[], + int num_keys, int keycode[], int max_keycodes) +{ + const u8 *keymap; + int valid, upto; + int pos; + + debug("%s: num_keys = %d\n", __func__, num_keys); + keymap = config->plain_keycode; + for (valid = upto = 0; upto < num_keys; upto++) { + struct key_matrix_key *key = &keys[upto]; + + debug(" valid=%d, row=%d, col=%d\n", key->valid, key->row, + key->col); + if (!key->valid) + continue; + pos = key->row * config->num_cols + key->col; + if (config->fn_keycode && pos == config->fn_pos) + keymap = config->fn_keycode; + + /* Convert the (row, col) values into a keycode */ + if (valid < max_keycodes) + keycode[valid++] = keymap[pos]; + debug(" keycode=%d\n", keymap[pos]); + } + + /* For a ghost key config, ignore the keypresses for this iteration. */ + if (valid >= 3 && has_ghosting(config, keys, valid)) { + valid = 0; + debug(" ghosting detected!\n"); + } + debug(" %d valid keycodes found\n", valid); + + return valid; +} + +/** + * Create a new keycode map from some provided data + * + * This decodes a keycode map in the format used by the fdt, which is one + * word per entry, with the row, col and keycode encoded in that word. + * + * We create a (row x col) size byte array with each entry containing the + * keycode for that (row, col). We also search for map_keycode and return + * its position if found (this is used for finding the Fn key). + * + * @param config Key matrix dimensions structure + * @param data Keycode data + * @param len Number of entries in keycode table + * @param map_keycode Key code to find in the map + * @param pos Returns position of map_keycode, if found, else -1 + * @return map Pointer to allocated map + */ +static uchar *create_keymap(struct key_matrix *config, u32 *data, int len, + int map_keycode, int *pos) +{ + uchar *map; + + if (pos) + *pos = -1; + map = (uchar *)calloc(1, config->key_count); + if (!map) { + debug("%s: failed to malloc %d bytes\n", __func__, + config->key_count); + return NULL; + } + + for (; len >= sizeof(u32); data++, len -= 4) { + u32 tmp = fdt32_to_cpu(*data); + int key_code, row, col; + int entry; + + row = (tmp >> 24) & 0xff; + col = (tmp >> 16) & 0xff; + key_code = tmp & 0xffff; + entry = row * config->num_cols + col; + map[entry] = key_code; + if (pos && map_keycode == key_code) + *pos = entry; + } + + return map; +} + +int key_matrix_decode_fdt(struct key_matrix *config, const void *blob, + int node) +{ + const struct fdt_property *prop; + int offset; + + /* Check each property name for ones that we understand */ + for (offset = fdt_first_property_offset(blob, node); + offset > 0; + offset = fdt_next_property_offset(blob, offset)) { + const char *name; + int len; + + prop = fdt_get_property_by_offset(blob, offset, NULL); + name = fdt_string(blob, fdt32_to_cpu(prop->nameoff)); + len = strlen(name); + + /* Name needs to match "1,keymap" */ + debug("%s: property '%s'\n", __func__, name); + if (strncmp(name, "1,", 2) || len < 8 || + strcmp(name + len - 6, "keymap")) + continue; + + len -= 8; + if (len == 0) { + config->plain_keycode = create_keymap(config, + (u32 *)prop->data, fdt32_to_cpu(prop->len), + KEY_FN, &config->fn_pos); + } else if (0 == strncmp(name + 2, "fn-", len)) { + config->fn_keycode = create_keymap(config, + (u32 *)prop->data, fdt32_to_cpu(prop->len), + -1, NULL); + } else { + debug("%s: unrecognised property '%s'\n", __func__, + name); + } + } + debug("%s: Decoded key maps %p, %p from fdt\n", __func__, + config->plain_keycode, config->fn_keycode); + + if (!config->plain_keycode) { + debug("%s: cannot find keycode-plain map\n", __func__); + return -1; + } + + return 0; +} + +int key_matrix_init(struct key_matrix *config, int rows, int cols) +{ + memset(config, '\0', sizeof(*config)); + config->num_rows = rows; + config->num_cols = cols; + config->key_count = rows * cols; + assert(config->key_count > 0); + + return 0; +} diff --git a/include/key_matrix.h b/include/key_matrix.h new file mode 100644 index 00000000000..f41331407dc --- /dev/null +++ b/include/key_matrix.h @@ -0,0 +1,99 @@ +/* + * Keyboard matrix helper functions + * + * Copyright (c) 2012 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _KEY_MATRIX_H +#define _KEY_MATRIX_H + +#include + +/* Information about a matrix keyboard */ +struct key_matrix { + /* Dimensions of the keyboard matrix, in rows and columns */ + int num_rows; + int num_cols; + int key_count; /* number of keys in the matrix (= rows * cols) */ + + /* + * Information about keycode mappings. The plain_keycode array must + * exist but fn may be NULL in which case it is not decoded. + */ + const u8 *plain_keycode; /* key code for each row / column */ + const u8 *fn_keycode; /* ...when Fn held down */ + int fn_pos; /* position of Fn key in key (or -1) */ +}; + +/* Information about a particular key (row, column pair) in the matrix */ +struct key_matrix_key { + uint8_t row; /* row number (0 = first) */ + uint8_t col; /* column number (0 = first) */ + uint8_t valid; /* 1 if valid, 0 to ignore this */ +}; + +/** + * Decode a set of pressed keys into key codes + * + * Given a list of keys that are pressed, this converts this list into + * a list of key codes. Each of the keys has a valid flag, which can be + * used to mark a particular key as invalid (so that it is ignored). + * + * The plain keymap is used, unless the Fn key is detected along the way, + * at which point we switch to the Fn key map. + * + * If key ghosting is detected, we simply ignore the keys and return 0. + * + * @param config Keyboard matrix config + * @param keys List of keys to process (each is row, col) + * @param num_keys Number of keys to process + * @param keycode Returns a list of key codes, decoded from input + * @param max_keycodes Size of key codes array (suggest 8) + * + */ +int key_matrix_decode(struct key_matrix *config, struct key_matrix_key *keys, + int num_keys, int keycode[], int max_keycodes); + +/** + * Read the keyboard configuration out of the fdt. + * + * Decode properties of named "linux,keymap" where is either + * empty, or "fn-". Then set up the plain key map (and the FN keymap if + * present). + * + * @param config Keyboard matrix config + * @param blob FDT blob + * @param node Node containing compatible data + * @return 0 if ok, -1 on error + */ +int key_matrix_decode_fdt(struct key_matrix *config, const void *blob, + int node); + +/** + * Set up a new key matrix. + * + * @param config Keyboard matrix config + * @param rows Number of rows in key matrix + * @param cols Number of columns in key matrix + * @return 0 if ok, -1 on error + */ +int key_matrix_init(struct key_matrix *config, int rows, int cols); + +#endif -- cgit v1.3.1 From 6642a681e410c1b3d767742d74146cb624dca287 Mon Sep 17 00:00:00 2001 From: Rakesh Iyer Date: Tue, 17 Apr 2012 09:01:35 +0000 Subject: tegra: Add tegra keyboard driver Add support for internal matrix keyboard controller for Nvidia Tegra platforms. This driver uses the fdt decode function to obtain its key codes. Support for the Ctrl modifier is provided. The left and right ctrl keys are dealt with in the same way. This uses the new keyboard input library (drivers/input/input.c) to decode keys and handle most of the common input logic. The new key matrix library is also used to decode (row, column) key positions into key codes. The intent is to make this driver purely about dealing with the hardware. Key detection before the driver is loaded is supported. This key will be picked up when the keyboard driver is initialized. Modified by Bernie Thompson and Simon Glass for device tree, input layer, key matrix and various other things. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- drivers/input/tegra-kbc.c | 375 ++++++++++++++++++++++++++++++++++++++++++++++ include/fdtdec.h | 1 + include/tegra-kbc.h | 33 ++++ lib/fdtdec.c | 1 + 4 files changed, 410 insertions(+) create mode 100644 drivers/input/tegra-kbc.c create mode 100644 include/tegra-kbc.h (limited to 'include') diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c new file mode 100644 index 00000000000..f164791bee6 --- /dev/null +++ b/drivers/input/tegra-kbc.c @@ -0,0 +1,375 @@ +/* + * (C) Copyright 2011 + * NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum { + KBC_MAX_GPIO = 24, + KBC_MAX_KPENT = 8, /* size of keypress entry queue */ +}; + +#define KBC_FIFO_TH_CNT_SHIFT 14 +#define KBC_DEBOUNCE_CNT_SHIFT 4 +#define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3) +#define KBC_CONTROL_KBC_EN (1 << 0) +#define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2) +#define KBC_KPENT_VALID (1 << 7) +#define KBC_ST_STATUS (1 << 3) + +enum { + KBC_DEBOUNCE_COUNT = 2, + KBC_REPEAT_RATE_MS = 30, + KBC_REPEAT_DELAY_MS = 240, + KBC_CLOCK_KHZ = 32, /* Keyboard uses a 32KHz clock */ +}; + +/* keyboard controller config and state */ +static struct keyb { + struct input_config input; /* The input layer */ + struct key_matrix matrix; /* The key matrix layer */ + + struct kbc_tegra *kbc; /* tegra keyboard controller */ + unsigned char inited; /* 1 if keyboard has been inited */ + unsigned char first_scan; /* 1 if this is our first key scan */ + + /* + * After init we must wait a short time before polling the keyboard. + * This gives the tegra keyboard controller time to react after reset + * and lets us grab keys pressed during reset. + */ + unsigned int init_dly_ms; /* Delay before we can read keyboard */ + unsigned int start_time_ms; /* Time that we inited (in ms) */ + unsigned int last_poll_ms; /* Time we should last polled */ + unsigned int next_repeat_ms; /* Next time we repeat a key */ +} config; + +/** + * reads the keyboard fifo for current keypresses + * + * @param config Keyboard config + * @param fifo Place to put fifo results + * @param max_keycodes Maximum number of key codes to put in the fifo + * @return number of items put into fifo + */ +static int tegra_kbc_find_keys(struct keyb *config, int *fifo, + int max_keycodes) +{ + struct key_matrix_key keys[KBC_MAX_KPENT], *key; + u32 kp_ent = 0; + int i; + + for (key = keys, i = 0; i < KBC_MAX_KPENT; i++, key++) { + /* Get next word */ + if (!(i & 3)) + kp_ent = readl(&config->kbc->kp_ent[i / 4]); + + key->valid = (kp_ent & KBC_KPENT_VALID) != 0; + key->row = (kp_ent >> 3) & 0xf; + key->col = kp_ent & 0x7; + + /* Shift to get next entry */ + kp_ent >>= 8; + } + return key_matrix_decode(&config->matrix, keys, KBC_MAX_KPENT, fifo, + max_keycodes); +} + +/** + * Process all the keypress sequences in fifo and send key codes + * + * The fifo contains zero or more keypress sets. Each set + * consists of from 1-8 keycodes, representing the keycodes which + * were simultaneously pressed during that scan. + * + * This function works through each set and generates ASCII characters + * for each. Not that one set may produce more than one ASCII characters - + * for example holding down 'd' and 'f' at the same time will generate + * two ASCII characters. + * + * Note: if fifo_cnt is 0, we will tell the input layer that no keys are + * pressed. + * + * @param config Keyboard config + * @param fifo_cnt Number of entries in the keyboard fifo + */ +static void process_fifo(struct keyb *config, int fifo_cnt) +{ + int fifo[KBC_MAX_KPENT]; + int cnt = 0; + + /* Always call input_send_keycodes() at least once */ + do { + if (fifo_cnt) + cnt = tegra_kbc_find_keys(config, fifo, KBC_MAX_KPENT); + + input_send_keycodes(&config->input, fifo, cnt); + } while (--fifo_cnt > 0); +} + +/** + * Check the keyboard controller and emit ASCII characters for any keys that + * are pressed. + * + * @param config Keyboard config + */ +static void check_for_keys(struct keyb *config) +{ + int fifo_cnt; + + if (!config->first_scan && + get_timer(config->last_poll_ms) < KBC_REPEAT_RATE_MS) + return; + config->last_poll_ms = get_timer(0); + config->first_scan = 0; + + /* + * Once we get here we know the keyboard has been scanned. So if there + * scan waiting for us, we know that nothing is held down. + */ + fifo_cnt = (readl(&config->kbc->interrupt) >> 4) & 0xf; + process_fifo(config, fifo_cnt); +} + +/** + * In order to detect keys pressed on boot, wait for the hardware to + * complete scanning the keys. This includes time to transition from + * Wkup mode to Continous polling mode and the repoll time. We can + * deduct the time that's already elapsed. + * + * @param config Keyboard config + */ +static void kbd_wait_for_fifo_init(struct keyb *config) +{ + if (!config->inited) { + unsigned long elapsed_time; + long delay_ms; + + elapsed_time = get_timer(config->start_time_ms); + delay_ms = config->init_dly_ms - elapsed_time; + if (delay_ms > 0) { + udelay(delay_ms * 1000); + debug("%s: delay %ldms\n", __func__, delay_ms); + } + + config->inited = 1; + } +} + +/** + * Check the tegra keyboard, and send any keys that are pressed. + * + * This is called by input_tstc() and input_getc() when they need more + * characters + * + * @param input Input configuration + * @return 1, to indicate that we have something to look at + */ +int tegra_kbc_check(struct input_config *input) +{ + kbd_wait_for_fifo_init(&config); + check_for_keys(&config); + + return 1; +} + +/** + * Test if keys are available to be read + * + * @return 0 if no keys available, 1 if keys are available + */ +static int kbd_tstc(void) +{ + /* Just get input to do this for us */ + return input_tstc(&config.input); +} + +/** + * Read a key + * + * TODO: U-Boot wants 0 for no key, but Ctrl-@ is a valid key... + * + * @return ASCII key code, or 0 if no key, or -1 if error + */ +static int kbd_getc(void) +{ + /* Just get input to do this for us */ + return input_getc(&config.input); +} + +/* configures keyboard GPIO registers to use the rows and columns */ +static void config_kbc_gpio(struct kbc_tegra *kbc) +{ + int i; + + for (i = 0; i < KBC_MAX_GPIO; i++) { + u32 row_cfg, col_cfg; + u32 r_shift = 5 * (i % 6); + u32 c_shift = 4 * (i % 8); + u32 r_mask = 0x1f << r_shift; + u32 c_mask = 0xf << c_shift; + u32 r_offs = i / 6; + u32 c_offs = i / 8; + + row_cfg = readl(&kbc->row_cfg[r_offs]); + col_cfg = readl(&kbc->col_cfg[c_offs]); + + row_cfg &= ~r_mask; + col_cfg &= ~c_mask; + + if (i < config.matrix.num_rows) { + row_cfg |= ((i << 1) | 1) << r_shift; + } else { + col_cfg |= (((i - config.matrix.num_rows) << 1) | 1) + << c_shift; + } + + writel(row_cfg, &kbc->row_cfg[r_offs]); + writel(col_cfg, &kbc->col_cfg[c_offs]); + } +} + +/** + * Start up the keyboard device + */ +static void tegra_kbc_open(void) +{ + struct kbc_tegra *kbc = config.kbc; + unsigned int scan_period; + u32 val; + + /* + * We will scan at twice the keyboard repeat rate, so that there is + * always a scan ready when we check it in check_for_keys(). + */ + scan_period = KBC_REPEAT_RATE_MS / 2; + writel(scan_period * KBC_CLOCK_KHZ, &kbc->rpt_dly); + writel(scan_period * KBC_CLOCK_KHZ, &kbc->init_dly); + /* + * Before reading from the keyboard we must wait for the init_dly + * plus the rpt_delay, plus 2ms for the row scan time. + */ + config.init_dly_ms = scan_period * 2 + 2; + + val = KBC_DEBOUNCE_COUNT << KBC_DEBOUNCE_CNT_SHIFT; + val |= 1 << KBC_FIFO_TH_CNT_SHIFT; /* fifo interrupt threshold */ + val |= KBC_CONTROL_KBC_EN; /* enable */ + writel(val, &kbc->control); + + config.start_time_ms = get_timer(0); + config.last_poll_ms = config.next_repeat_ms = get_timer(0); + config.first_scan = 1; +} + +/** + * Set up the tegra keyboard. This is called by the stdio device handler + * + * We want to do this init when the keyboard is actually used rather than + * at start-up, since keyboard input may not currently be selected. + * + * Once the keyboard starts there will be a period during which we must + * wait for the keyboard to init. We do this only when a key is first + * read - see kbd_wait_for_fifo_init(). + * + * @return 0 if ok, -ve on error + */ +static int init_tegra_keyboard(void) +{ +#ifdef CONFIG_OF_CONTROL + int node; + + node = fdtdec_next_compatible(gd->fdt_blob, 0, + COMPAT_NVIDIA_TEGRA20_KBC); + if (node < 0) { + debug("%s: cannot locate keyboard node\n", __func__); + return node; + } + config.kbc = (struct kbc_tegra *)fdtdec_get_addr(gd->fdt_blob, + node, "reg"); + if ((fdt_addr_t)config.kbc == FDT_ADDR_T_NONE) { + debug("%s: No keyboard register found\n", __func__); + return -1; + } + + /* Decode the keyboard matrix information (16 rows, 8 columns) */ + if (key_matrix_init(&config.matrix, 16, 8)) { + debug("%s: Could not init key matrix\n", __func__); + return -1; + } + if (key_matrix_decode_fdt(&config.matrix, gd->fdt_blob, node)) { + debug("%s: Could not decode key matrix from fdt\n", __func__); + return -1; + } + if (config.matrix.fn_keycode) { + if (input_add_table(&config.input, KEY_FN, -1, + config.matrix.fn_keycode, + config.matrix.key_count)) + return -1; + } +#else +#error "Tegra keyboard driver requires FDT definitions" +#endif + + /* Set up pin mux and enable the clock */ + funcmux_select(PERIPH_ID_KBC, FUNCMUX_DEFAULT); + clock_enable(PERIPH_ID_KBC); + config_kbc_gpio(config.kbc); + + tegra_kbc_open(); + debug("%s: Tegra keyboard ready\n", __func__); + + return 0; +} + +int drv_keyboard_init(void) +{ + struct stdio_dev dev; + + if (input_init(&config.input, 0, KBC_REPEAT_DELAY_MS, + KBC_REPEAT_RATE_MS)) { + debug("%s: Cannot set up input\n", __func__); + return -1; + } + config.input.read_keys = tegra_kbc_check; + + memset(&dev, '\0', sizeof(dev)); + strcpy(dev.name, "tegra-kbc"); + dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + dev.getc = kbd_getc; + dev.tstc = kbd_tstc; + dev.start = init_tegra_keyboard; + + /* Register the device. init_tegra_keyboard() will be called soon */ + return input_stdio_register(&dev); +} diff --git a/include/fdtdec.h b/include/fdtdec.h index b6db0278bdc..fab577ed32f 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -62,6 +62,7 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra2 dvc (really just i2c) */ COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra2 memory controller */ COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra2 memory timing table */ + COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra2 Keyboard */ COMPAT_COUNT, }; diff --git a/include/tegra-kbc.h b/include/tegra-kbc.h new file mode 100644 index 00000000000..f331c79c9d5 --- /dev/null +++ b/include/tegra-kbc.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __include_tegra_kbc_h__ +#define __include_tegra_kbc_h__ + +#include + +#define KEY_IS_MODIFIER(key) ((key) >= KEY_FIRST_MODIFIER) + +struct kbc_tegra { + u32 control; + u32 interrupt; + u32 row_cfg[4]; + u32 col_cfg[3]; + u32 timeout_dly; + u32 init_dly; + u32 rpt_dly; + u32 kp_ent[2]; + u32 row_mask[16]; +}; + +#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +extern int overwrite_console(void); +#define OVERWRITE_CONSOLE overwrite_console() +#else +#define OVERWRITE_CONSOLE 0 +#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */ + +#endif /* __include_tegra_kbc_h__ */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index ba5c591489a..cc09e06c730 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -42,6 +42,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"), COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"), COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"), + COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- cgit v1.3.1 From 4120c271c3efa0c224fe02046ee7ae4b818d8044 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 17 Apr 2012 09:01:36 +0000 Subject: tegra: Switch on console mux and use environment for console All tegra boards will use these options by default. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra2-common.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index c5870dd4be2..068ce8855ff 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -132,11 +132,18 @@ #define CONFIG_SYS_NO_FLASH -/* Environment information */ +/* Environment information, boards can override if required */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define TEGRA2_DEVICE_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttyS0,115200n8\0" \ "mem=" TEGRA2_SYSMEM "\0" \ "smpflag=smp\0" \ + TEGRA2_DEVICE_SETTINGS #define CONFIG_LOADADDR 0x408000 /* def. location for kernel */ #define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ -- cgit v1.3.1 From 2cacf516df84228f03a1a67bbea387d76cdd34d0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 17 Apr 2012 09:01:37 +0000 Subject: tegra: Enable keyboard for Seaboard This enables the standard keyboard on Seaboard. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/seaboard.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 7e7c38ea852..46d42281b78 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -100,4 +100,12 @@ #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB +/* Enable keyboard */ +#define CONFIG_TEGRA2_KEYBOARD +#define CONFIG_KEYBOARD + +#undef TEGRA2_DEVICE_SETTINGS +#define TEGRA2_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \ + "stdout=serial\0" \ + "stderr=serial\0" #endif /* __CONFIG_H */ -- cgit v1.3.1 From 1b8ec016cd8865c2efe089c043caf8c4f084f1fc Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 25 Apr 2012 02:33:50 +0000 Subject: igep00x0: enable the use of a plain text file Based on commit cf073e49bc3502be1b48a0e3faf0cde9edbb89db for beagleboard Using the new env import command it is possible to use plain text files instead of script-images. Plain text files are much easier to handle. E.g. If your boot.scr contains the following: ----------------------------------- setenv dvimode 1024x768-16@60 run loaduimage run mmcboot ----------------------------------- you could create a file named uEnv.txt and use that instead of boot.scr: ----------------------------------- dvimode=1024x768-16@60 uenvcmd=run loaduimage; run mmcboot ----------------------------------- The variable uenvcmd (if existent) will be executed (using run) after uEnv.txt was loaded. If uenvcmd doesn't exist the default boot sequence will be started, therefore you could just use ----------------------------------- dvimode=1024x768-16@60 ----------------------------------- as uEnv.txt because loaduimage and mmcboot is part of the default boot sequence Signed-off-by: Enric Balletbo i Serra Signed-off-by: Anatolij Gustschin --- include/configs/igep00x0.h | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index d2b4b849290..31ddabc0f52 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -161,9 +161,9 @@ "omapdss.def_disp=${defaultdisplay} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ @@ -175,15 +175,19 @@ #define CONFIG_BOOTCOMMAND \ "if mmc rescan ${mmcdev}; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loaduimage; then " \ + "run mmcboot;" \ + "fi;" \ + "fi;" \ + "run nandboot;" \ #define CONFIG_AUTO_COMPLETE 1 -- cgit v1.3.1 From f1e445c3c94aaab910b4588ec4c8934fd9edd86a Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 25 Apr 2012 02:34:31 +0000 Subject: igep00x0: change mpurate from 500 to auto This patch changes the default mpurate variable from 500 to auto on all IGEP boards, with this the default rate is autoselected. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Anatolij Gustschin --- include/configs/igep00x0.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 31ddabc0f52..a99f332a856 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -136,7 +136,7 @@ "loadaddr=0x82000000\0" \ "usbtty=cdc_acm\0" \ "console=ttyS2,115200n8\0" \ - "mpurate=500\0" \ + "mpurate=auto\0" \ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ "defaultdisplay=dvi\0" \ -- cgit v1.3.1 From c176dd0442c40d4e98c86848091f628707f9c50a Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 1 May 2012 10:05:08 +0000 Subject: OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device Tree For OMAP4 boards, such as the panda-es, that have 1GB of memory the linux kernel fails to locate the device tree blob on boot. The reason being is that u-boot is copying the DT blob to the upper part of RAM when booting the kernel and the kernel is unable to access the blob. By setting the fdt_high variable to either 0xffffffff (to prevent the copy) or 0xac000000 (704MB boundary of memory for OMAP4) the kernel is able to locate the DT blob and boot. Based upon following patch by Dirk Behme set the fdt_high variable to allow booting with device tree on OMAP4 boards. "7e9603e i.mx6q: configs: Add fdt_high and initrd_high variables" Cc: Sricharan R Cc: Sandeep Paulraj Cc: Tom Rini Signed-off-by: Jon Hunter --- include/configs/omap4_common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 5507c8f4c64..072e17bab8f 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -149,6 +149,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyO2,115200n8\0" \ + "fdt_high=0xffffffff\0" \ "usbtty=cdc_acm\0" \ "vram=16M\0" \ "mmcdev=0\0" \ -- cgit v1.3.1 From e0820ccc38315d88192c19e98ea9b59d3ec7d4c8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 8 May 2012 07:29:31 +0000 Subject: ARM: omap3: Set SPL stack size to 8KB, image to 54KB. With older toolchains it is possible to not fit entirely into the 45KB that we had assigned to SPL. Adjust to allow for 8KB of stack (which should be more than required) and 54KB of text/data. Cc: Vaibhav Hiremath Cc: Nagendra T S Cc: Thomas Weber Cc: Ilya Yanok Cc: Steve Sakoman Cc: Stefano Babic Signed-off-by: Tom Rini Acked-by: Stefano Babic Acked-by: Vaibhav Hiremath --- doc/SPL/README.omap3 | 4 ++-- include/configs/am3517_crane.h | 2 +- include/configs/am3517_evm.h | 2 +- include/configs/devkit8000.h | 2 +- include/configs/mcx.h | 2 +- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm_common.h | 2 +- include/configs/omap3_overo.h | 2 +- include/configs/tam3517-common.h | 2 +- include/configs/tricorder.h | 2 +- 10 files changed, 11 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/doc/SPL/README.omap3 b/doc/SPL/README.omap3 index cc5d5c09ad7..a543e65d39b 100644 --- a/doc/SPL/README.omap3 +++ b/doc/SPL/README.omap3 @@ -34,14 +34,14 @@ DDR1: 0x80000000 - 0xBFFFFFFF Option 1 (SPL only): 0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata -0x4020BC00 - 0x4020FFFC: Area for the SPL stack. +0x4020E000 - 0x4020FFFC: Area for the SPL stack. 0x80000000 - 0x8007FFFF: Area for the SPL BSS. 0x80100000: CONFIG_SYS_TEXT_BASE of U-Boot 0x80208000 - 0x80307FFF: malloc() pool available to SPL. Option 2 (SPL or X-Loader): 0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata -0x4020BC00 - 0x4020FFFC: Area for the SPL stack. +0x4020E000 - 0x4020FFFC: Area for the SPL stack. 0x80008000: CONFIG_SYS_TEXT_BASE of U-Boot 0x87000000 - 0x8707FFFF: Area for the SPL BSS. 0x87080000 - 0x870FFFFF: malloc() pool available to SPL. diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 71321f339e8..1233985aa6d 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -325,7 +325,7 @@ #define CONFIG_SPL #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (45 * 1024) +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index bbd19def5d5..ff8d1b01392 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -324,7 +324,7 @@ #define CONFIG_SPL #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (45 * 1024) +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index eb7c376780d..248a5b2fa36 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -324,7 +324,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ -#define CONFIG_SPL_MAX_SIZE 0xB400 /* 45 K */ +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ diff --git a/include/configs/mcx.h b/include/configs/mcx.h index e190e3e02d7..f6a83a8505e 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -325,7 +325,7 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ -#define CONFIG_SPL_MAX_SIZE (45 << 10) +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK /* move malloc and bss high to prevent clashing with the main image */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index ddeb4146f75..6bdc2c38949 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -399,7 +399,7 @@ #define CONFIG_SPL #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (45 * 1024) +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 4910ddaa83b..47ebbefb9e2 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -282,7 +282,7 @@ /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (45 * 1024) /* 45 KB */ +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 64adc7455c5..b0d144fc4db 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -303,7 +303,7 @@ #define CONFIG_SPL #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (45 * 1024) +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK /* move malloc and bss high to prevent clashing with the main image */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 37eb87bf0a3..3fc2c443490 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -257,7 +257,7 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ -#define CONFIG_SPL_MAX_SIZE (45 << 10) /* 45 K */ +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 801a24fd889..ab911aae12b 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -293,7 +293,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ -#define CONFIG_SPL_MAX_SIZE 0xB400 /* 45 K */ +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ -- cgit v1.3.1 From 49175c49bae743a80c9fa2e264ccee7befa0b7a4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 8 May 2012 07:29:32 +0000 Subject: ARM: omap3: Add CONFIG_SPL_BOARD_INIT for CONFIG_SPL_MMC_SUPPORT As originally reported against beagleboard we currently have the following error message reported in SPL: U-Boot SPL 2012.04-00020-gb8310b9-dirty (Apr 25 2012 - 18:49:57) Texas Instruments Revision detection unimplemented OMAP SD/MMC: 0 timed out in wait_for_bb: I2C_STAT=1000 reading u-boot.img .... The reason for above message is that when booting from MMC, I2C needs to be initialized to talk with the TWL4030. On OMAP3 I2C is only initalized in SPL if CONFIG_SPL_BOARD_INIT is set. Cc: Thomas Weber Cc: Steve Sakoman Original patch for Beagleboard is: Signed-off-by: Peter Meerwald Extended to cover all other boards: Signed-off-by: Tom Rini --- include/configs/omap3_beagle.h | 1 + include/configs/omap3_evm_common.h | 1 + include/configs/omap3_overo.h | 1 + include/configs/tricorder.h | 1 + 4 files changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 6bdc2c38949..b891ee49255 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -410,6 +410,7 @@ #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_I2C_SUPPORT diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 47ebbefb9e2..7b21a5c8c4b 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -288,6 +288,7 @@ #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_I2C_SUPPORT diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index b0d144fc4db..a0a7a1c42ae 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -317,6 +317,7 @@ #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_I2C_SUPPORT diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index ab911aae12b..9955fca4768 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -278,6 +278,7 @@ #define CONFIG_SPL #define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_I2C_SUPPORT -- cgit v1.3.1