From ca1c292d2ee6bcb06be71400d25ae37e9dc2c1aa Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 21 Apr 2026 09:54:31 +0200 Subject: string: fix prototype of memdup() It doesn't make sense to restrict memdup() to only return char* pointers, especially when it is already defined to accept void*. This makes it uglier to use to e.g. duplicate a struct. Make it return void*, just as kmemdup() does in the kernel (and which our kmemdup() in fact also does). While in here, make a small optimization: memcpy() is defined to return the destination register, so we write this in a way that the compiler may do a tail call. Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- include/linux/string.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/string.h b/include/linux/string.h index d943fcce690..9e47fe01c16 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -142,7 +142,7 @@ void *memchr_inv(const void *, int, size_t); * memory is available * */ -char *memdup(const void *src, size_t len); +void *memdup(const void *src, size_t len); unsigned long ustrtoul(const char *cp, char **endp, unsigned int base); unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base); -- cgit v1.3.1 From 719cacb92e039308e23cbd6b653275e939a5aca5 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 21 Apr 2026 09:54:32 +0200 Subject: stdio: drop stdio_clone The helper stdio_clone only has a single caller, so it certainly doesn't need to be public. But in fact, it is merely an open-coded memdup() - which for some reason uses calloc() even if the whole allocation is obviously immediately overwritten. Drop it and just use memdup() directly. Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- common/stdio.c | 18 +----------------- include/stdio_dev.h | 1 - 2 files changed, 1 insertion(+), 18 deletions(-) (limited to 'include') diff --git a/common/stdio.c b/common/stdio.c index fc965944209..038e576147b 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -217,27 +217,11 @@ struct stdio_dev *stdio_get_by_name(const char *name) return NULL; } -struct stdio_dev *stdio_clone(struct stdio_dev *dev) -{ - struct stdio_dev *_dev; - - if (!dev) - return NULL; - - _dev = calloc(1, sizeof(struct stdio_dev)); - if (!_dev) - return NULL; - - memcpy(_dev, dev, sizeof(struct stdio_dev)); - - return _dev; -} - int stdio_register_dev(struct stdio_dev *dev, struct stdio_dev **devp) { struct stdio_dev *_dev; - _dev = stdio_clone(dev); + _dev = memdup(dev, sizeof(*dev)); if (!_dev) return -ENODEV; list_add_tail(&_dev->list, &devs.list); diff --git a/include/stdio_dev.h b/include/stdio_dev.h index f7f9c10199e..d93604331ff 100644 --- a/include/stdio_dev.h +++ b/include/stdio_dev.h @@ -96,7 +96,6 @@ int stdio_add_devices(void); int stdio_deregister_dev(struct stdio_dev *dev, int force); struct list_head *stdio_get_list(void); struct stdio_dev *stdio_get_by_name(const char *name); -struct stdio_dev *stdio_clone(struct stdio_dev *dev); int drv_lcd_init(void); int drv_video_init(void); -- cgit v1.3.1 From 349d148f16d83da3b1e3475be0e43bfda4f4ab71 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 21 Apr 2026 09:54:33 +0200 Subject: lib/string.c: drop pointless __HAVE_ARCH_STRDUP There has never been an arch-specific optimized implementation of str[n]dup, nor is there likely to ever be one, because unlike their cousins strlen(), strcpy() and similar that simply read/write the src/dst, the dup functions by definition involve memory allocation. So drop this irrelevant cpp guard. Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- include/linux/string.h | 3 +-- lib/string.c | 2 -- 2 files changed, 1 insertion(+), 4 deletions(-) (limited to 'include') diff --git a/include/linux/string.h b/include/linux/string.h index 9e47fe01c16..a28150fa578 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -101,10 +101,9 @@ size_t strcspn(const char *s, const char *reject); # define strndup sandbox_strndup #endif -#ifndef __HAVE_ARCH_STRDUP extern char * strdup(const char *); extern char * strndup(const char *, size_t); -#endif + #ifndef __HAVE_ARCH_STRSWAB extern char * strswab(const char *); #endif diff --git a/lib/string.c b/lib/string.c index c2813e0f854..2c1baa568b9 100644 --- a/lib/string.c +++ b/lib/string.c @@ -343,7 +343,6 @@ size_t strcspn(const char *s, const char *reject) } #endif -#ifndef __HAVE_ARCH_STRDUP char * strdup(const char *s) { char *new; @@ -379,7 +378,6 @@ char * strndup(const char *s, size_t n) return new; } -#endif #ifndef __HAVE_ARCH_STRSPN /** -- cgit v1.3.1 From 8c664d2135723a110a60b792a8614c4864ad82a3 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 21 Apr 2026 09:54:34 +0200 Subject: lib/string.c: introduce memdup_nul() helper This is completely analogous to the linux kernel's kmemdup_nul() helper, apart from the lack of the gfp_t argument: Allocate a buffer of size {len}+1, copy {len} bytes from the given buffer, and add a final nul byte. This pattern exists in a number of places, so this helper can reduce some boilerplate code. Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- include/linux/string.h | 13 +++++++++++++ lib/string.c | 15 +++++++++++++++ 2 files changed, 28 insertions(+) (limited to 'include') diff --git a/include/linux/string.h b/include/linux/string.h index a28150fa578..b2e38ecf26e 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -143,6 +143,19 @@ void *memchr_inv(const void *, int, size_t); */ void *memdup(const void *src, size_t len); +/** + * memdup_nul() - allocate a buffer and copy in the contents, appending a nul byte + * + * Note that this returns a valid pointer even if @len is 0 + * + * @src: data to copy in + * @len: number of bytes to copy + * Return: allocated buffer with the copied contents and an extra nul byte, + * or NULL if not enough memory is available + * + */ +void *memdup_nul(const void *src, size_t len); + unsigned long ustrtoul(const char *cp, char **endp, unsigned int base); unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base); diff --git a/lib/string.c b/lib/string.c index 2c1baa568b9..3923cce5561 100644 --- a/lib/string.c +++ b/lib/string.c @@ -343,6 +343,21 @@ size_t strcspn(const char *s, const char *reject) } #endif +void *memdup_nul(const void *src, size_t len) +{ + char *dst; + + if (len + 1 < len) + return NULL; + + dst = malloc(len + 1); + if (!dst) + return NULL; + + dst[len] = '\0'; + return memcpy(dst, src, len); +} + char * strdup(const char *s) { char *new; -- cgit v1.3.1 From 825f8ee2fcf64ef5875a0bc0a3e2d8650acdc298 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 3 May 2026 14:49:20 -0600 Subject: ti: Quote board_init in ti_common.env bootcmd_ti_mmc skips a per-board init hook with: if test -n ${board_init}; then run board_init; fi; The default case is "no board override", i.e. board_init unset. The expression then expands to 'test -n' with no operand and relies on a U-Boot 'test' quirk that treats a missing operand as false to skip the run. Quote the variable so an unset board_init expands to 'test -n ""' and the emptiness check is explicit. Fixes: 8b0619579b22 ("cmd: test: fix handling of single-argument form of test") Signed-off-by: Simon Glass --- include/env/ti/ti_common.env | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/env/ti/ti_common.env b/include/env/ti/ti_common.env index 62b93eb25c4..e6ceaa17adc 100644 --- a/include/env/ti/ti_common.env +++ b/include/env/ti/ti_common.env @@ -24,7 +24,7 @@ get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile} run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring} bootcmd_ti_mmc= run init_${boot}; - if test -n ${board_init}; then + if test -n "${board_init}"; then echo Running board_init ...; run board_init; fi; -- cgit v1.3.1 From 6b109a1304a03b35ad489e551964737ad80f6a82 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 3 May 2026 14:49:21 -0600 Subject: siemens: Quote A/B flags in env tests The Siemens am33x-common, env-common and draco-etamin headers gate boot-partition selection logic on: if test -n ${A}; then ... if test -n ${B}; then ... A and B are flags that the upgrade machinery sets to mark "the other partition just became active". The default state is unset, in which case the expression expands to 'test -n' with no operand and relies on a U-Boot 'test' quirk that treats a missing operand as false to skip the branch. Quote each variable so an unset A or B expands to 'test -n ""' and the emptiness check is explicit. Fixes: 8b0619579b22 ("cmd: test: fix handling of single-argument form of test") Signed-off-by: Simon Glass --- include/configs/draco-etamin.h | 4 ++-- include/configs/siemens-am33x-common.h | 12 ++++++------ include/configs/siemens-env-common.h | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/configs/draco-etamin.h b/include/configs/draco-etamin.h index 6ae85b575b7..b1b403980b1 100644 --- a/include/configs/draco-etamin.h +++ b/include/configs/draco-etamin.h @@ -99,10 +99,10 @@ "nand_args=run bootargs_defaults;" \ "mtdparts default;" \ "setenv ${partitionset_active} true;" \ - "if test -n ${A}; then " \ + "if test -n \"${A}\"; then " \ "setenv nand_active_ubi_vol ${rootfs_name}_a;" \ "fi;" \ - "if test -n ${B}; then " \ + "if test -n \"${B}\"; then " \ "setenv nand_active_ubi_vol ${rootfs_name}_b;" \ "fi;" \ "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index a918dc1350c..da822556909 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -104,11 +104,11 @@ "then " \ "setenv upgrade_available 0;" \ "setenv ${partitionset_active} true;" \ - "if test -n ${A}; then " \ + "if test -n \"${A}\"; then " \ "setenv partitionset_active B; " \ "env delete A; " \ "fi;" \ - "if test -n ${B}; then " \ + "if test -n \"${B}\"; then " \ "setenv partitionset_active A; " \ "env delete B; " \ "fi;" \ @@ -205,11 +205,11 @@ "nand_args=run bootargs_defaults;" \ "mtdparts default;" \ "setenv ${partitionset_active} true;" \ - "if test -n ${A}; then " \ + "if test -n \"${A}\"; then " \ "setenv nand_active_ubi_vol ${nand_active_ubi_vol_A};" \ "setenv nand_src_addr ${nand_src_addr_A};" \ "fi;" \ - "if test -n ${B}; then " \ + "if test -n \"${B}\"; then " \ "setenv nand_active_ubi_vol ${nand_active_ubi_vol_B};" \ "setenv nand_src_addr ${nand_src_addr_B};" \ "fi;" \ @@ -279,10 +279,10 @@ "nand_args=run bootargs_defaults;" \ "mtdparts default;" \ "setenv ${partitionset_active} true;" \ - "if test -n ${A}; then " \ + "if test -n \"${A}\"; then " \ "setenv nand_active_ubi_vol ${rootfs_name}_a;" \ "fi;" \ - "if test -n ${B}; then " \ + "if test -n \"${B}\"; then " \ "setenv nand_active_ubi_vol ${rootfs_name}_b;" \ "fi;" \ "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ diff --git a/include/configs/siemens-env-common.h b/include/configs/siemens-env-common.h index c028823e1eb..8ced77cc5e2 100644 --- a/include/configs/siemens-env-common.h +++ b/include/configs/siemens-env-common.h @@ -81,12 +81,12 @@ */ #define ENV_FCT_TOGGLE_PARTITION "toggle_partition="\ "setenv ${partitionset_active} true;" \ - "if test -n ${A}; " \ + "if test -n \"${A}\"; " \ "then " \ "setenv partitionset_active B; " \ "env delete A; " \ "fi;" \ - "if test -n ${B}; "\ + "if test -n \"${B}\"; "\ "then " \ "setenv partitionset_active A; " \ "env delete B; " \ @@ -103,11 +103,11 @@ */ #define ENV_EMMC_FCT_SET_ACTIVE_PARTITION "set_partition=" \ "setenv ${partitionset_active} true;" \ - "if test -n ${A}; " \ + "if test -n \"${A}\"; " \ "then " \ "setenv mmc_part_nr 1;" \ "fi;" \ - "if test -n ${B}; " \ + "if test -n \"${B}\"; " \ "then " \ "setenv mmc_part_nr 2;" \ "fi;" \ -- cgit v1.3.1 From 2120834c25d525b754a8473565d4e0f9c158d806 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 3 May 2026 14:49:22 -0600 Subject: beaglev_fire: Quote no_of_overlays in design test On beaglev_fire, design_overlays gates an overlay-application loop on: if test -n ${no_of_overlays}; then ... The default state is "no overlays", i.e. no_of_overlays unset. The expression then expands to 'test -n' with no operand and relies on a U-Boot 'test' quirk that treats a missing operand as false to skip the loop. Quote the variable so an unset no_of_overlays expands to 'test -n ""' and the emptiness check is explicit. Fixes: 8b0619579b22 ("cmd: test: fix handling of single-argument form of test") Signed-off-by: Simon Glass --- include/configs/beaglev_fire.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/beaglev_fire.h b/include/configs/beaglev_fire.h index e3ee0f02f2d..8724a71504c 100644 --- a/include/configs/beaglev_fire.h +++ b/include/configs/beaglev_fire.h @@ -30,7 +30,7 @@ #define BOOTENV_DESIGN_OVERLAYS \ "design_overlays=" \ - "if test -n ${no_of_overlays}; then " \ + "if test -n \"${no_of_overlays}\"; then " \ "setenv inc 1; " \ "setenv idx 0; " \ "fdt resize ${dtbo_size}; " \ -- cgit v1.3.1 From 9458e39c6595e2e00a1d0a645676eaf935e783c7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 3 May 2026 14:49:23 -0600 Subject: mccmon6: Quote recovery_status in bootcmd test MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mccmon6 bootcmd starts with: if test -n ${recovery_status}; then run boot_recovery; ... The default state is "no recovery requested", i.e. recovery_status unset. The expression then expands to 'test -n' with no operand and relies on a U-Boot 'test' quirk that treats a missing operand as false to skip recovery. Quote the variable so an unset recovery_status expands to 'test -n ""' and the emptiness check is explicit. Fixes: 8b0619579b22 ("cmd: test: fix handling of single-argument form of test") Signed-off-by: Simon Glass Reviewed-by: Łukasz Majewski --- include/configs/mccmon6.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 9f401718bfb..0cf62d6bda8 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -88,7 +88,7 @@ "bootm $loadaddr};reset;" \ "fi\0" \ "bootcmd=" \ - "if test -n ${recovery_status}; then " \ + "if test -n \"${recovery_status}\"; then " \ "run boot_recovery;" \ "else " \ "if test ! -n ${boot_medium}; then " \ -- cgit v1.3.1 From 93d7dc20e80e33ace9b871de44877548642f86cb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 3 May 2026 14:49:24 -0600 Subject: aristainetos2: Quote rescue_reason in rescueboot test The rescueboot script optionally runs a per-board rescue_reason hook with: if test -n ${rescue_reason}; then run rescue_reason; fi; The default state is "no rescue reason script", i.e. rescue_reason unset. The expression then expands to 'test -n' with no operand and relies on a U-Boot 'test' quirk that treats a missing operand as false to skip the run. Quote the variable so an unset rescue_reason expands to 'test -n ""' and the emptiness check is explicit. Fixes: 8b0619579b22 ("cmd: test: fix handling of single-argument form of test") Signed-off-by: Simon Glass Reviewed-by: Heiko Schocher --- include/configs/aristainetos2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 8a66b1275df..2078ebc5282 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -211,7 +211,7 @@ "${pubkey}\0" \ "rescueboot=echo Booting rescue system ...; " \ "run addmtd addmisc;" \ - "if test -n ${rescue_reason}; then run rescue_reason;fi;" \ + "if test -n \"${rescue_reason}\"; then run rescue_reason;fi;" \ "run boot_board_type;" \ "if bootm ${fit_addr_r}; then ; " \ "else " \ -- cgit v1.3.1 From 368255a9a0a6076f88c7124f4d002485cc6ac059 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 7 May 2026 18:42:59 +0200 Subject: clk: sunxi: Drop the extern The struct clk_ops sunxi_clk_ops is private to the clock driver and there are no external users, no need to expose it this way. Drop the extern. Signed-off-by: Marek Vasut --- include/clk/sunxi.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/clk/sunxi.h b/include/clk/sunxi.h index c298195c51e..09cc7a4fc46 100644 --- a/include/clk/sunxi.h +++ b/include/clk/sunxi.h @@ -85,6 +85,4 @@ struct ccu_plat { const struct ccu_desc *desc; }; -extern struct clk_ops sunxi_clk_ops; - #endif /* _CLK_SUNXI_H */ -- cgit v1.3.1 From 009cd5b56dbc2d0f7675e4262347a1a6b6a55cb2 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Sat, 16 May 2026 16:39:58 +0900 Subject: virtio: mmio: Allow instantiation via platform data The m68k QEMU virt machine doesn't use devicetree, yet, so allow it to create virtio-mmio instances via platform data. Reviewed-by: Simon Glass Reviewed-by: Kuan-Wei Chiu Reviewed-by: Angelo Dureghello Signed-off-by: Daniel Palmer --- drivers/virtio/virtio_mmio.c | 27 ++++++++++++++++++--------- include/virtio_mmio.h | 12 ++++++++++++ 2 files changed, 30 insertions(+), 9 deletions(-) create mode 100644 include/virtio_mmio.h (limited to 'include') diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index d90d8309f99..975f98cd9e5 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -335,21 +336,28 @@ static int virtio_mmio_notify(struct udevice *udev, struct virtqueue *vq) static int virtio_mmio_of_to_plat(struct udevice *udev) { - struct virtio_mmio_priv *priv = dev_get_priv(udev); + struct virtio_mmio_plat *plat = dev_get_plat(udev); + fdt_addr_t addr; + + addr = dev_read_addr(udev); - priv->base = (void __iomem *)(ulong)dev_read_addr(udev); - if (priv->base == (void __iomem *)FDT_ADDR_T_NONE) + if (addr == FDT_ADDR_T_NONE) return -EINVAL; + plat->base = addr; + return 0; } static int virtio_mmio_probe(struct udevice *udev) { + struct virtio_mmio_plat *plat = dev_get_plat(udev); struct virtio_mmio_priv *priv = dev_get_priv(udev); struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); u32 magic; + priv->base = (void __iomem *)(uintptr_t)plat->base; + /* Check magic value */ magic = readl(priv->base + VIRTIO_MMIO_MAGIC_VALUE); if (magic != ('v' | 'i' << 8 | 'r' << 16 | 't' << 24)) { @@ -405,11 +413,12 @@ static const struct udevice_id virtio_mmio_ids[] = { }; U_BOOT_DRIVER(virtio_mmio) = { - .name = "virtio-mmio", - .id = UCLASS_VIRTIO, - .of_match = virtio_mmio_ids, - .ops = &virtio_mmio_ops, - .probe = virtio_mmio_probe, + .name = "virtio-mmio", + .id = UCLASS_VIRTIO, + .of_match = virtio_mmio_ids, + .ops = &virtio_mmio_ops, + .probe = virtio_mmio_probe, .of_to_plat = virtio_mmio_of_to_plat, - .priv_auto = sizeof(struct virtio_mmio_priv), + .priv_auto = sizeof(struct virtio_mmio_priv), + .plat_auto = sizeof(struct virtio_mmio_plat), }; diff --git a/include/virtio_mmio.h b/include/virtio_mmio.h new file mode 100644 index 00000000000..8c072826db5 --- /dev/null +++ b/include/virtio_mmio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __VIRTIO_MMIO_H__ +#define __VIRTIO_MMIO_H__ + +#include + +struct virtio_mmio_plat { + phys_addr_t base; +}; + +#endif /* __VIRTIO_MMIO_H__ */ -- cgit v1.3.1 From ddba15ab72df5a01fd483a0f4fc40f9ae4d2475c Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Sat, 16 May 2026 16:40:00 +0900 Subject: virtio: blk: Fix converting the vendor id to a string Currently we are trying to work out if the vendor id is from a virtio-mmio device and then casting a u32 to a char* and using it as a C-string. By chance there is usually a zero after the u32 and it works. Since the vendor id we are trying to convert to a string is QEMU's just define a value for the QEMU vendor id, check if the vendor id matches and then use a predefined string for "QEMU". I don't think we should have been assumming all virtio-mmio vendor ids are printable ASCII chars in the first place so do this special casing just for QEMU. If the vendor id isn't QEMU print the hex value of it. Reviewed-by: Simon Glass Reviewed-by: Kuan-Wei Chiu Signed-off-by: Daniel Palmer --- drivers/virtio/virtio_blk.c | 11 ++++------- include/virtio.h | 3 +++ 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/drivers/virtio/virtio_blk.c b/drivers/virtio/virtio_blk.c index 45fb596a330..94968ef1c75 100644 --- a/drivers/virtio/virtio_blk.c +++ b/drivers/virtio/virtio_blk.c @@ -231,14 +231,11 @@ static int virtio_blk_bind(struct udevice *dev) return devnum; desc->devnum = devnum; desc->part_type = PART_TYPE_UNKNOWN; - /* - * virtio mmio transport supplies string identification for us, - * while pci trnasport uses a 2-byte subvendor value. - */ - if (uc_priv->vendor >> 16) - sprintf(desc->vendor, "%s", (char *)&uc_priv->vendor); + + if (uc_priv->vendor == VIRTIO_VENDOR_QEMU) + strcpy(desc->vendor, "QEMU"); else - sprintf(desc->vendor, "%04x", uc_priv->vendor); + sprintf(desc->vendor, "%08x", uc_priv->vendor); desc->bdev = dev; /* Indicate what driver features we support */ diff --git a/include/virtio.h b/include/virtio.h index 17f894a79e3..3edf023463d 100644 --- a/include/virtio.h +++ b/include/virtio.h @@ -25,6 +25,9 @@ #include #include #include + +#define VIRTIO_VENDOR_QEMU 0x554d4551 + #define VIRTIO_ID_NET 1 /* virtio net */ #define VIRTIO_ID_BLOCK 2 /* virtio block */ #define VIRTIO_ID_RNG 4 /* virtio rng */ -- cgit v1.3.1 From a219f64c2794135b44ab9aa9b808c5c25d18262c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 8 May 2026 10:22:32 -0600 Subject: cros_ec: Sync ec_commands.h from upstream Chrome OS EC Sync include/ec_commands.h from upstream commit 4f3d17aa34 ("skywalker: set SLEEP_TIMEOUT_MS to 50 seconds"). The new file makes two build assumptions that do not hold for U-Boot. It hides '' from __KERNEL__ builds, leaving UINT16_MAX (used by EC_RES_MAX) undefined for U-Boot; widen the gate to '!defined(__KERNEL__) || defined(__UBOOT__)' It gates '' on '#ifdef __KERNEL__'; the matching '#else' branch defines BIT()/BIT_ULL()/GENMASK()/GENMASK_ULL() locally, assuming kernel headers provide those macros otherwise. U-Boot defines __KERNEL__ too but has no . Nest a '!defined(__UBOOT__)' check around the include so the __UBOOT__ path stays in the __KERNEL__ branch (no local BIT/GENMASK defines), which avoids redefinition warnings against U-Boot's linux/bitops.h. Pull in linux/bitops.h up front for U-Boot so the file's own BIT() and GENMASK() uses still resolve. Adapt callers to two interface changes. The 'ec_current_image' enum tag is now 'ec_image' (EC_IMAGE_* constants unchanged); rename it in affected files to match. The VBNV-context interface was dropped upstream, but it still used in lab Chromebooks; keep those constants and structs in cros_ec.h Likewise, MEC_EMI_BASE and MEC_EMI_SIZE are a U-Boot-local addition to ec_commands.h that the upstream sync removes; preserve them in cros_ec.h next to the VBNV block, and switch the only consumer (arch/x86/cpu/apollolake/cpu_spl.c) to include cros_ec.h Signed-off-by: Simon Glass --- arch/x86/cpu/apollolake/cpu_spl.c | 2 +- cmd/cros_ec.c | 4 +- drivers/misc/cros_ec.c | 2 +- drivers/misc/cros_ec_sandbox.c | 2 +- include/cros_ec.h | 36 +- include/ec_commands.h | 7784 +++++++++++++++++++++++++++++-------- 6 files changed, 6299 insertions(+), 1531 deletions(-) (limited to 'include') diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c index 8198667fa50..080c5a58575 100644 --- a/arch/x86/cpu/apollolake/cpu_spl.c +++ b/arch/x86/cpu/apollolake/cpu_spl.c @@ -6,7 +6,7 @@ */ #include -#include +#include #include #include #include diff --git a/cmd/cros_ec.c b/cmd/cros_ec.c index 7b60e415b6c..66a5f6d5210 100644 --- a/cmd/cros_ec.c +++ b/cmd/cros_ec.c @@ -13,7 +13,7 @@ #include #include -/* Note: depends on enum ec_current_image */ +/* Note: depends on enum ec_image */ static const char * const ec_current_image_name[] = {"unknown", "RO", "RW"}; /** @@ -312,7 +312,7 @@ static int do_cros_ec(struct cmd_tbl *cmdtp, int flag, int argc, if (ret) printf("Error: %d\n", ret); } else if (0 == strcmp("curimage", cmd)) { - enum ec_current_image image; + enum ec_image image; if (cros_ec_read_current_image(dev, &image)) { debug("%s: Could not read KBC image\n", __func__); diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index fabe4964a33..c3e647edfac 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -487,7 +487,7 @@ int cros_ec_read_build_info(struct udevice *dev, char **strp) } int cros_ec_read_current_image(struct udevice *dev, - enum ec_current_image *image) + enum ec_image *image) { struct ec_response_get_version *r; diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index 5b9c6354bef..9fedca4e6b6 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -100,7 +100,7 @@ struct ec_state { struct fdt_cros_ec ec_config; uint8_t *flash_data; int flash_data_len; - enum ec_current_image current_image; + enum ec_image current_image; int matrix_count; struct ec_keymatrix_entry *matrix; /* the key matrix info */ uint8_t keyscan[KEYBOARD_COLS]; diff --git a/include/cros_ec.h b/include/cros_ec.h index 94c988a7d65..4ef34815e35 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -14,6 +14,40 @@ #include #include +/* + * Verified-boot NVRAM context interface the EC exposes via + * EC_CMD_VBNV_CONTEXT. Upstream cros_ec_commands.h dropped the + * whole vbnvcontext machinery, so keep the constants and request / + * response structs here for U-Boot. Both 'cros_ec vbnvcontext' and + * cros_ec_{read,write}_vbnvcontext() depend on these. + */ +#define EC_CMD_VBNV_CONTEXT 0x0017 +#define EC_VER_VBNV_CONTEXT 1 +#define EC_VBNV_BLOCK_SIZE 16 +#define EC_VBNV_BLOCK_SIZE_V2 64 + +enum ec_vbnvcontext_op { + EC_VBNV_CONTEXT_OP_READ, + EC_VBNV_CONTEXT_OP_WRITE, +}; + +struct __ec_align4 ec_params_vbnvcontext { + uint32_t op; + uint8_t block[EC_VBNV_BLOCK_SIZE_V2]; +}; + +struct __ec_align4 ec_response_vbnvcontext { + uint8_t block[EC_VBNV_BLOCK_SIZE_V2]; +}; + +/* + * EMI register window used by Microchip MEC-style EC LPC interfaces. + * Upstream cros_ec_commands.h does not carry these, but apollolake's + * SPL needs them to set up the EC ioport range. + */ +#define MEC_EMI_BASE 0x800 +#define MEC_EMI_SIZE 8 + /* Our configuration information */ struct cros_ec_dev { struct udevice *dev; /* Transport device */ @@ -101,7 +135,7 @@ int cros_ec_get_next_event(struct udevice *dev, * Return: 0 if ok, <0 on error */ int cros_ec_read_current_image(struct udevice *dev, - enum ec_current_image *image); + enum ec_image *image); /** * Read the hash of the CROS-EC device firmware. diff --git a/include/ec_commands.h b/include/ec_commands.h index 23597d28b2c..cedc34dd0fc 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -1,31 +1,97 @@ -/* Copyright (c) 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Host communication command constants for Chrome EC */ -#ifndef __CROS_EC_COMMANDS_H -#define __CROS_EC_COMMANDS_H +#ifndef __CROS_EC_EC_COMMANDS_H +#define __CROS_EC_EC_COMMANDS_H +#if !defined(__ACPI__) && (!defined(__KERNEL__) || defined(__UBOOT__)) +#include +#endif + +#ifdef __UBOOT__ +#include +#endif + +#ifdef CHROMIUM_EC /* - * Protocol overview - * - * request: CMD [ P0 P1 P2 ... Pn S ] - * response: ERR [ P0 P1 P2 ... Pn S ] - * - * where the bytes are defined as follow : - * - CMD is the command code. (defined by EC_CMD_ constants) - * - ERR is the error code. (defined by EC_RES_ constants) - * - Px is the optional payload. - * it is not sent if the error code is not success. - * (defined by ec_params_ and ec_response_ structures) - * - S is the checksum which is the sum of all payload bytes. - * - * On LPC, CMD and ERR are sent/received at EC_LPC_ADDR_KERNEL|USER_CMD - * and the payloads are sent/received at EC_LPC_ADDR_KERNEL|USER_PARAM. - * On I2C, all bytes are sent serially in the same message. + * CHROMIUM_EC is defined by the Makefile system of Chromium EC repository. + * It is used to not include macros that may cause conflicts in foreign + * projects (refer to crbug.com/984623). + */ + +/* + * Include common.h for CONFIG_HOSTCMD_ALIGNED, if it's defined. This + * generates more efficient code for accessing request/response structures on + * ARM Cortex-M if the structures are guaranteed 32-bit aligned. + */ +#include "common.h" +#include "compile_time_macros.h" + +#else +/* If BUILD_ASSERT isn't already defined, make it a no-op */ +#ifndef BUILD_ASSERT +#define BUILD_ASSERT(_cond) +#endif /* !BUILD_ASSERT */ +#endif /* CHROMIUM_EC */ + +#if defined(__KERNEL__) +#if !defined(__UBOOT__) +#include +#endif +#else +/* + * Defines macros that may be needed but are for sure defined by the linux + * kernel. This section is removed when cros_ec_commands.h is generated (by + * util/make_linux_ec_commands_h.sh). + * cros_ec_commands.h looks more integrated to the kernel. + */ + +#ifndef BIT +#define BIT(nr) (1UL << (nr)) +#endif + +#ifndef BIT_ULL +#define BIT_ULL(nr) (1ULL << (nr)) +#endif + +/* + * When building Zephyr, this file ends up being included before Zephyr's + * include/sys/util.h so causes a warning there. We don't want to add an #ifdef + * in that file since it won't be accepted upstream. So work around it here. + */ +#ifndef CONFIG_ZEPHYR +#ifndef GENMASK +#define GENMASK(h, l) (((BIT(h) << 1) - 1) ^ (BIT(l) - 1)) +#endif + +#ifndef GENMASK_ULL +#define GENMASK_ULL(h, l) (((BIT_ULL(h) << 1) - 1) ^ (BIT_ULL(l) - 1)) +#endif +#endif + +#endif /* __KERNEL__ */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Constant for creation of flexible array members that work in both C and + * C++. Flexible array members were added in C99 and are not part of the C++ + * standard. However, clang++ supports them for C++. + * When compiling with gcc, flexible array members are not allowed to appear + * in an otherwise empty struct, so we use the GCC zero-length array + * extension that works with both clang/gcc/g++. */ +#if defined(__cplusplus) && defined(__clang__) +#define FLEXIBLE_ARRAY_MEMBER_SIZE +#else +#define FLEXIBLE_ARRAY_MEMBER_SIZE 0 +#endif /* * Current version of this protocol @@ -34,91 +100,111 @@ * determined in other ways. Remove this once the kernel code no longer * depends on it. */ -#define EC_PROTO_VERSION 0x00000002 +#define EC_PROTO_VERSION 0x00000002 /* Command version mask */ -#define EC_VER_MASK(version) (1UL << (version)) +#define EC_VER_MASK(version) BIT(version) /* I/O addresses for ACPI commands */ -#define EC_LPC_ADDR_ACPI_DATA 0x62 -#define EC_LPC_ADDR_ACPI_CMD 0x66 +#define EC_LPC_ADDR_ACPI_DATA 0x62 +#define EC_LPC_ADDR_ACPI_CMD 0x66 /* I/O addresses for host command */ -#define EC_LPC_ADDR_HOST_DATA 0x200 -#define EC_LPC_ADDR_HOST_CMD 0x204 +#define EC_LPC_ADDR_HOST_DATA 0x200 +#define EC_LPC_ADDR_HOST_CMD 0x204 /* I/O addresses for host command args and params */ /* Protocol version 2 */ -#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ -#define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is - * EC_PROTO2_MAX_PARAM_SIZE */ +#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ +/* For version 2 params; size is EC_PROTO2_MAX_PARAM_SIZE */ +#define EC_LPC_ADDR_HOST_PARAM 0x804 + /* Protocol version 3 */ -#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ -#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ +#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ +#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ -/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff - * and they tell the kernel that so we have to think of it as two parts. */ -#define EC_HOST_CMD_REGION0 0x800 -#define EC_HOST_CMD_REGION1 0x880 +/* + * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff + * and they tell the kernel that so we have to think of it as two parts. + * + * Other BIOSes report only the I/O port region spanned by the Microchip + * MEC series EC; an attempt to address a larger region may fail. + */ +#define EC_HOST_CMD_REGION0 0x800 +#define EC_HOST_CMD_REGION1 0x880 #define EC_HOST_CMD_REGION_SIZE 0x80 +#define EC_HOST_CMD_MEC_REGION_SIZE 0x8 /* EC command register bit functions */ -#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */ -#define EC_LPC_CMDR_PENDING (1 << 1) /* Write pending to EC */ -#define EC_LPC_CMDR_BUSY (1 << 2) /* EC is busy processing a command */ -#define EC_LPC_CMDR_CMD (1 << 3) /* Last host write was a command */ -#define EC_LPC_CMDR_ACPI_BRST (1 << 4) /* Burst mode (not used) */ -#define EC_LPC_CMDR_SCI (1 << 5) /* SCI event is pending */ -#define EC_LPC_CMDR_SMI (1 << 6) /* SMI event is pending */ - -/* MEC uses 0x800/0x804 as register/index pair, thus an 8-byte resource */ -#define MEC_EMI_BASE 0x800 -#define MEC_EMI_SIZE 8 - -#define EC_LPC_ADDR_MEMMAP 0x900 -#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ -#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */ +#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */ +#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */ +#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */ +#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */ +#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */ +#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */ +#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */ + +#define EC_LPC_ADDR_MEMMAP 0x900 +#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ +#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */ + +#define EC_LPC_ADDR_MEMMAP_INDEXED_IO 0x380 /* The offset address of each type of data in mapped memory. */ -#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */ -#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */ -#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */ -#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */ -#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ -#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ -#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ +#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */ +#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */ +#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */ +#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */ +#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ +#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ +#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ #define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */ -#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ -#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */ +#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ +#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */ /* Unused 0x28 - 0x2f */ -#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */ +#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */ /* Unused 0x31 - 0x33 */ -#define EC_MEMMAP_HOST_EVENTS 0x34 /* 32 bits */ -/* Reserve 0x38 - 0x3f for additional host event-related stuff */ -/* Battery values are all 32 bits */ -#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ -#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ -#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ -#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, defined below */ -#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */ -#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ -#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ -#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ +#define EC_MEMMAP_HOST_EVENTS 0x34 /* 64 bits */ +/* Battery values are all 32 bits, unless otherwise noted. */ +#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ +#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ +#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ +#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, see below (8-bit) */ +#define EC_MEMMAP_BATT_COUNT 0x4d /* Battery Count (8-bit) */ +#define EC_MEMMAP_BATT_INDEX 0x4e /* Current Battery Data Index (8-bit) */ +/* Unused 0x4f */ +#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */ +#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ +#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ +#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ /* Strings are all 8 bytes (EC_MEMMAP_TEXT_MAX) */ -#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ -#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ -#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ -#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ -#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */ +#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ +#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ +#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ +#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ +#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */ /* Unused 0x84 - 0x8f */ -#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/ +#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/ /* Unused 0x91 */ -#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */ +#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */ /* 0x92: Lid Angle if available, LID_ANGLE_UNRELIABLE otherwise */ /* 0x94 - 0x99: 1st Accelerometer */ /* 0x9a - 0x9f: 2nd Accelerometer */ -#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ -/* Unused 0xa6 - 0xdf */ + +#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ +#define EC_MEMMAP_GPU 0xa6 /* GPU-specific, 8 bits */ + +/* + * Bit fields for EC_MEMMAP_GPU + * 0:2: D-Notify level (0:D1, ... 4:D5) + * 3: Over temperature + */ +#define EC_MEMMAP_GPU_D_NOTIFY_MASK GENMASK(2, 0) +#define EC_MEMMAP_GPU_OVERT_BIT BIT(3) + +/* Power Participant related components */ +#define EC_MEMMAP_PWR_SRC 0xa7 /* Power source (8-bit) */ +/* Unused 0xa8 - 0xdf */ /* * ACPI is unable to access memory mapped data at or above this offset due to @@ -128,76 +214,101 @@ #define EC_MEMMAP_NO_ACPI 0xe0 /* Define the format of the accelerometer mapped memory status byte. */ -#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f -#define EC_MEMMAP_ACC_STATUS_BUSY_BIT (1 << 4) -#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT (1 << 7) +#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f +#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4) +#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7) /* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */ -#define EC_TEMP_SENSOR_ENTRIES 16 +#define EC_TEMP_SENSOR_ENTRIES 16 /* * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B. * * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2. */ -#define EC_TEMP_SENSOR_B_ENTRIES 8 +#define EC_TEMP_SENSOR_B_ENTRIES 8 + +/* Max temp sensor entries for host commands */ +#define EC_MAX_TEMP_SENSOR_ENTRIES \ + (EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES) /* Special values for mapped temperature sensors */ -#define EC_TEMP_SENSOR_NOT_PRESENT 0xff -#define EC_TEMP_SENSOR_ERROR 0xfe -#define EC_TEMP_SENSOR_NOT_POWERED 0xfd +#define EC_TEMP_SENSOR_NOT_PRESENT 0xff +#define EC_TEMP_SENSOR_ERROR 0xfe +#define EC_TEMP_SENSOR_NOT_POWERED 0xfd #define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc /* * The offset of temperature value stored in mapped memory. This allows * reporting a temperature range of 200K to 454K = -73C to 181C. */ -#define EC_TEMP_SENSOR_OFFSET 200 +#define EC_TEMP_SENSOR_OFFSET 200 /* * Number of ALS readings at EC_MEMMAP_ALS */ -#define EC_ALS_ENTRIES 2 +#define EC_ALS_ENTRIES 2 /* * The default value a temperature sensor will return when it is present but * has not been read this boot. This is a reasonable number to avoid * triggering alarms on the host. */ -#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET) +#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET) -#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ -#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ -#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */ +#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ +#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ + +/* Report 0 for fan stalled so userspace applications can take + * an appropriate action based on this value to control the fan. + */ +#define EC_FAN_SPEED_STALLED 0x0 +/* This should be used only for ectool to support old ECs. */ +#define EC_FAN_SPEED_STALLED_DEPRECATED 0xfffe /* Battery bit flags at EC_MEMMAP_BATT_FLAG. */ -#define EC_BATT_FLAG_AC_PRESENT 0x01 +#define EC_BATT_FLAG_AC_PRESENT 0x01 #define EC_BATT_FLAG_BATT_PRESENT 0x02 -#define EC_BATT_FLAG_DISCHARGING 0x04 -#define EC_BATT_FLAG_CHARGING 0x08 +#define EC_BATT_FLAG_DISCHARGING 0x04 +#define EC_BATT_FLAG_CHARGING 0x08 #define EC_BATT_FLAG_LEVEL_CRITICAL 0x10 +/* Set if some of the static/dynamic data is invalid (or outdated). */ +#define EC_BATT_FLAG_INVALID_DATA 0x20 +#define EC_BATT_FLAG_CUT_OFF 0x40 + +/* + * Value written to EC_MEMMAP_BATT_DCAP, EC_MEMMAP_BATT_DVLT, EC_MEMMAP_CCNT, + * EC_MEMMAP_BATT_VOLT, EC_MEMMAP_BATT_RATE, EC_MEMMAP_BATT_CAP, and + * EC_MEMMAP_BATT_LFCC if the actual value is unknown. + * + * This corresponds with the unknown value specified by ACPI release 6.5 + * Section 10.2.2 (and earlier versions), to match expectations of ACPI + * firmware. + */ +#define EC_MEMMAP_BATT_UNKNOWN_VALUE (-1) /* Switch flags at EC_MEMMAP_SWITCHES */ -#define EC_SWITCH_LID_OPEN 0x01 -#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 -#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04 +#define EC_SWITCH_LID_OPEN 0x01 +#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 +/* Was write protect disabled; now unused. */ +#define EC_SWITCH_IGNORE2 0x04 /* Was recovery requested via keyboard; now unused. */ -#define EC_SWITCH_IGNORE1 0x08 +#define EC_SWITCH_IGNORE1 0x08 /* Recovery requested via dedicated signal (from servo board) */ -#define EC_SWITCH_DEDICATED_RECOVERY 0x10 +#define EC_SWITCH_DEDICATED_RECOVERY 0x10 /* Was fake developer mode switch; now unused. Remove in next refactor. */ -#define EC_SWITCH_IGNORE0 0x20 +#define EC_SWITCH_IGNORE0 0x20 /* Host command interface flags */ /* Host command interface supports LPC args (LPC interface only) */ -#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 +#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 /* Host command interface supports version 3 protocol */ -#define EC_HOST_CMD_FLAG_VERSION_3 0x02 +#define EC_HOST_CMD_FLAG_VERSION_3 0x02 /* Wireless switch flags */ -#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */ -#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */ -#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */ -#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */ -#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */ +#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */ +#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */ +#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */ +#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */ +#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */ /*****************************************************************************/ /* @@ -265,19 +376,19 @@ /* Valid addresses in ACPI memory space, for read/write commands */ /* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */ -#define EC_ACPI_MEM_VERSION 0x00 +#define EC_ACPI_MEM_VERSION 0x00 /* * Test location; writing value here updates test compliment byte to (0xff - * value). */ -#define EC_ACPI_MEM_TEST 0x01 +#define EC_ACPI_MEM_TEST 0x01 /* Test compliment; writes here are ignored. */ -#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 +#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 /* Keyboard backlight brightness percent (0 - 100) */ #define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03 /* DPTF Target Fan Duty (0-100, 0xff for auto/none) */ -#define EC_ACPI_MEM_FAN_DUTY 0x04 +#define EC_ACPI_MEM_FAN_DUTY 0x04 /* * DPTF temp thresholds. Any of the EC's temp sensors can have up to two @@ -294,17 +405,17 @@ * have tripped". Setting or enabling the thresholds for a sensor will clear * the unread event count for that sensor. */ -#define EC_ACPI_MEM_TEMP_ID 0x05 -#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06 -#define EC_ACPI_MEM_TEMP_COMMIT 0x07 +#define EC_ACPI_MEM_TEMP_ID 0x05 +#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06 +#define EC_ACPI_MEM_TEMP_COMMIT 0x07 /* * Here are the bits for the COMMIT register: * bit 0 selects the threshold index for the chosen sensor (0/1) * bit 1 enables/disables the selected threshold (0 = off, 1 = on) * Each write to the commit register affects one threshold. */ -#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK (1 << 0) -#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK (1 << 1) +#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK BIT(0) +#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK BIT(1) /* * Example: * @@ -321,26 +432,179 @@ */ /* DPTF battery charging current limit */ -#define EC_ACPI_MEM_CHARGING_LIMIT 0x08 +#define EC_ACPI_MEM_CHARGING_LIMIT 0x08 /* Charging limit is specified in 64 mA steps */ -#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64 +#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64 /* Value to disable DPTF battery charging limit */ -#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff +#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff /* * Report device orientation - * bit 0 device is tablet mode + * Bits Definition + * 4 Off Body/On Body status: 0 = Off Body. + * 3:1 Device DPTF Profile Number (DDPN) + * 0 = Reserved for backward compatibility (indicates no valid + * profile number. Host should fall back to using TBMD). + * 1..7 = DPTF Profile number to indicate to host which table needs + * to be loaded. + * 0 Tablet Mode Device Indicator (TBMD) */ #define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09 -#define EC_ACPI_MEM_DEVICE_TABLET_MODE 0x01 +#define EC_ACPI_MEM_TBMD_SHIFT 0 +#define EC_ACPI_MEM_TBMD_MASK 0x1 +#define EC_ACPI_MEM_DDPN_SHIFT 1 +#define EC_ACPI_MEM_DDPN_MASK 0x7 +#define EC_ACPI_MEM_STTB_SHIFT 4 +#define EC_ACPI_MEM_STTB_MASK 0x1 + +/* + * Report device features. Uses the same format as the host command, except: + * + * bit 0 (EC_FEATURE_LIMITED) changes meaning from "EC code has a limited set + * of features", which is of limited interest when the system is already + * interpreting ACPI bytecode, to "EC_FEATURES[0-7] is not supported". Since + * these are supported, it defaults to 0. + * This allows detecting the presence of this field since older versions of + * the EC codebase would simply return 0xff to that unknown address. Check + * FEATURES0 != 0xff (or FEATURES0[0] == 0) to make sure that the other bits + * are valid. + */ +#define EC_ACPI_MEM_DEVICE_FEATURES0 0x0a +#define EC_ACPI_MEM_DEVICE_FEATURES1 0x0b +#define EC_ACPI_MEM_DEVICE_FEATURES2 0x0c +#define EC_ACPI_MEM_DEVICE_FEATURES3 0x0d +#define EC_ACPI_MEM_DEVICE_FEATURES4 0x0e +#define EC_ACPI_MEM_DEVICE_FEATURES5 0x0f +#define EC_ACPI_MEM_DEVICE_FEATURES6 0x10 +#define EC_ACPI_MEM_DEVICE_FEATURES7 0x11 + +#define EC_ACPI_MEM_BATTERY_INDEX 0x12 + +/* + * USB Port Power. Each bit indicates whether the corresponding USB ports' power + * is enabled (1) or disabled (0). + * bit 0 USB port ID 0 + * ... + * bit 7 USB port ID 7 + */ +#define EC_ACPI_MEM_USB_PORT_POWER 0x13 + +/* + * USB Retimer firmware update. + * Read: + * Result of last operation AP requested + * Write: + * bits[3:0]: USB-C port number + * bits[7:4]: Operation requested by AP + * + * NDA (no device attached) case: + * To update retimer firmware, AP needs set up TBT Alt mode. + * AP requests operations in this sequence: + * 1. Get port information about which ports support retimer firmware update. + * In the query result, each bit represents one port. + * 2. Get current MUX mode, it's NDA. + * 3. Suspend specified PD port's task. + * 4. AP requests EC to enter USB mode -> enter Safe mode -> enter TBT mode -> + * update firmware -> disconnect MUX -> resume PD task. + * + * DA (device attached) cases: + * Retimer firmware update is not supported in DA cases. + * 1. Get port information about which ports support retimer firmware update + * 2. Get current MUX mode, it's DA. + * 3. AP continues. No more retimer firmware update activities. + * + */ +#define EC_ACPI_MEM_USB_RETIMER_FW_UPDATE 0x14 + +#define USB_RETIMER_FW_UPDATE_OP_SHIFT 4 +#define USB_RETIMER_FW_UPDATE_ERR 0xfe +#define USB_RETIMER_FW_UPDATE_INVALID_MUX 0xff +/* Mask to clear unused MUX bits in retimer firmware update */ +#define USB_RETIMER_FW_UPDATE_MUX_MASK \ + (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \ + USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \ + USB_PD_MUX_USB4_ENABLED) + +/* Retimer firmware update operations */ +#define USB_RETIMER_FW_UPDATE_QUERY_PORT 0 /* Which ports has retimer */ +#define USB_RETIMER_FW_UPDATE_SUSPEND_PD 1 /* Suspend PD port */ +#define USB_RETIMER_FW_UPDATE_RESUME_PD 2 /* Resume PD port */ +#define USB_RETIMER_FW_UPDATE_GET_MUX 3 /* Read current USB MUX */ +#define USB_RETIMER_FW_UPDATE_SET_USB 4 /* Set MUX to USB mode */ +#define USB_RETIMER_FW_UPDATE_SET_SAFE 5 /* Set MUX to Safe mode */ +#define USB_RETIMER_FW_UPDATE_SET_TBT 6 /* Set MUX to TBT mode */ +#define USB_RETIMER_FW_UPDATE_DISCONNECT 7 /* Set MUX to disconnect */ + +#define EC_ACPI_MEM_USB_RETIMER_PORT(x) ((x) & 0x0f) +#define EC_ACPI_MEM_USB_RETIMER_OP(x) \ + (((x) & 0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT) + +/* + * Offset 0x15 is reserved for PBOK, added to coreboot in + * https://crrev.com/c/3840943 and proposed for inclusion here + * in https://crrev.com/c/3547317. + */ + +/* + * Get extended strings from the EC. + * Write: + * String index, or 0 to probe for EC support. + * Read: + * String bytes, following by repeating null bytes. + * + * Writing a byte (EC_ACPI_MEM_STRINGS_FIFO_ID_*) selects a string, and the + * following reads return the non-null bytes of the string in sequence until + * the end of the string is reached. After the end of the string, reads 0 until + * another byte is written. This interface allows ACPI firmware to read longer + * strings from the EC than can reasonably fit into the shared memory region. + * + * To probe for EC support, write FIFO_ID_VERSION and read will return at least + * one nonzero (MEM_STRINGS_FIFO_V1 for example) if MEM_STRINGS_FIFO is + * supported. Returned values will indicate which strings are supported. If the + * first byte is 0xff, the strings FIFO is unsupported. + */ +#define EC_ACPI_MEM_STRINGS_FIFO 0x16 + +/* String index to probe EC support. */ +#define EC_ACPI_MEM_STRINGS_FIFO_ID_VERSION 0 +#define EC_ACPI_MEM_STRINGS_FIFO_V1 1 +/* + * 0xff is the value the EC returns for unimplemented reads, indicating + * the current EC firmware does not implement this command. + */ +#define EC_ACPI_MEM_STRINGS_FIFO_UNSUPPORTED 0xff + +/* + * Battery model number for the selected battery. Supported since V1. + * Presents the same data as EC_MEMMAP_BATT_MODEL, but can provide more + * than 8 bytes. + * + * This and the other FIFO_ID_BATTERY strings can select one of multiple + * batteries by changing the value at EC_MEMMAP_BATT_INDEX. Once that index + * is changed, reads of these strings will return information for the + * corresponding battery, if present. + */ +#define EC_ACPI_MEM_STRINGS_FIFO_ID_BATTERY_MODEL 1 +/* + * Battery serial number for the selected battery. Supported since V1. + * Presents the same data as EC_MEMMAP_BATT_SERIAL, but can provide more + * than 8 bytes. + */ +#define EC_ACPI_MEM_STRINGS_FIFO_ID_BATTERY_SERIAL 2 +/* + * Battery manufacturer for the selected battery. Supported since V1. + * Presents the same data as EC_MEMMAP_BATT_MFGR, but can provide more + * than 8 bytes. + */ +#define EC_ACPI_MEM_STRINGS_FIFO_ID_BATTERY_MANUFACTURER 3 /* * ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf. This data * is read-only from the AP. Added in EC_ACPI_MEM_VERSION 2. */ -#define EC_ACPI_MEM_MAPPED_BEGIN 0x20 -#define EC_ACPI_MEM_MAPPED_SIZE 0xe0 +#define EC_ACPI_MEM_MAPPED_BEGIN 0x20 +#define EC_ACPI_MEM_MAPPED_SIZE 0xe0 /* Current version of ACPI memory address space */ #define EC_ACPI_MEM_VERSION_CURRENT 2 @@ -352,6 +616,7 @@ */ #ifndef __ACPI__ +#ifndef __KERNEL__ /* * Define __packed if someone hasn't beat us to it. Linux kernel style * checking prefers __packed over __attribute__((packed)). @@ -363,6 +628,7 @@ #ifndef __aligned #define __aligned(x) __attribute__((aligned(x))) #endif +#endif /* __KERNEL__ */ /* * Attributes for EC request and response packets. Just defining __packed @@ -376,7 +642,7 @@ * parent structure that the alignment will still be true given the packing of * the parent structure. This is particularly important if the sub-structure * will be passed as a pointer to another function, since that function will - * not know about the misaligment caused by the parent structure's packing. + * not know about the misalignment caused by the parent structure's packing. * * Also be very careful using __packed - particularly when nesting non-packed * structures inside packed ones. In fact, DO NOT use __packed directly; @@ -429,7 +695,7 @@ #define __ec_todo_packed __packed #define __ec_todo_unpacked -#else /* !CONFIG_HOSTCMD_ALIGNED */ +#else /* !CONFIG_HOSTCMD_ALIGNED */ /* * Packed structures make no assumption about alignment, so they do inefficient @@ -444,25 +710,25 @@ #define __ec_todo_packed __packed #define __ec_todo_unpacked -#endif /* !CONFIG_HOSTCMD_ALIGNED */ +#endif /* !CONFIG_HOSTCMD_ALIGNED */ /* LPC command status byte masks */ /* EC has written a byte in the data register and host hasn't read it yet */ -#define EC_LPC_STATUS_TO_HOST 0x01 +#define EC_LPC_STATUS_TO_HOST 0x01 /* Host has written a command/data byte and the EC hasn't read it yet */ -#define EC_LPC_STATUS_FROM_HOST 0x02 +#define EC_LPC_STATUS_FROM_HOST 0x02 /* EC is processing a command */ -#define EC_LPC_STATUS_PROCESSING 0x04 +#define EC_LPC_STATUS_PROCESSING 0x04 /* Last write to EC was a command, not data */ -#define EC_LPC_STATUS_LAST_CMD 0x08 +#define EC_LPC_STATUS_LAST_CMD 0x08 /* EC is in burst mode */ -#define EC_LPC_STATUS_BURST_MODE 0x10 +#define EC_LPC_STATUS_BURST_MODE 0x10 /* SCI event is pending (requesting SCI query) */ #define EC_LPC_STATUS_SCI_PENDING 0x20 /* SMI event is pending (requesting SMI query) */ #define EC_LPC_STATUS_SMI_PENDING 0x40 /* (reserved) */ -#define EC_LPC_STATUS_RESERVED 0x80 +#define EC_LPC_STATUS_RESERVED 0x80 /* * EC is busy. This covers both the EC processing a command, and the host has @@ -471,8 +737,8 @@ #define EC_LPC_STATUS_BUSY_MASK \ (EC_LPC_STATUS_FROM_HOST | EC_LPC_STATUS_PROCESSING) -/* Host command response codes (16-bit). Note that response codes should be - * stored in a uint16_t rather than directly in a value of this type. +/* + * Host command response codes (16-bit). */ enum ec_status { EC_RES_SUCCESS = 0, @@ -483,25 +749,112 @@ enum ec_status { EC_RES_INVALID_RESPONSE = 5, EC_RES_INVALID_VERSION = 6, EC_RES_INVALID_CHECKSUM = 7, - EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */ - EC_RES_UNAVAILABLE = 9, /* No response available */ - EC_RES_TIMEOUT = 10, /* We got a timeout */ - EC_RES_OVERFLOW = 11, /* Table / data overflow */ - EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ - EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ - EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */ - EC_RES_BUS_ERROR = 15, /* Communications bus error */ - EC_RES_BUSY = 16 /* Up but too busy. Should retry */ -}; + EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */ + EC_RES_UNAVAILABLE = 9, /* No response available */ + EC_RES_TIMEOUT = 10, /* We got a timeout */ + EC_RES_OVERFLOW = 11, /* Table / data overflow */ + EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ + EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ + EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */ + EC_RES_BUS_ERROR = 15, /* Communications bus error */ + EC_RES_BUSY = 16, /* Up but too busy. Should retry */ + EC_RES_INVALID_HEADER_VERSION = 17, /* Header version invalid */ + EC_RES_INVALID_HEADER_CRC = 18, /* Header CRC invalid */ + EC_RES_INVALID_DATA_CRC = 19, /* Data CRC invalid */ + EC_RES_DUP_UNAVAILABLE = 20, /* Can't resend response */ + + EC_RES_COUNT, + + EC_RES_MAX = UINT16_MAX, /**< Force enum to be 16 bits */ +} __packed; +BUILD_ASSERT(sizeof(enum ec_status) == sizeof(uint16_t)); +#ifdef CONFIG_EC_HOST_CMD +#ifdef CONFIG_ZEPHYR +/* + * Make sure Zephyre uses the same status codes. + */ +#include +#endif + +BUILD_ASSERT((uint16_t)EC_RES_SUCCESS == (uint16_t)EC_HOST_CMD_SUCCESS); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_COMMAND == + (uint16_t)EC_HOST_CMD_INVALID_COMMAND); +BUILD_ASSERT((uint16_t)EC_RES_ERROR == (uint16_t)EC_HOST_CMD_ERROR); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_PARAM == + (uint16_t)EC_HOST_CMD_INVALID_PARAM); +BUILD_ASSERT((uint16_t)EC_RES_ACCESS_DENIED == + (uint16_t)EC_HOST_CMD_ACCESS_DENIED); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_RESPONSE == + (uint16_t)EC_HOST_CMD_INVALID_RESPONSE); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_VERSION == + (uint16_t)EC_HOST_CMD_INVALID_VERSION); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_CHECKSUM == + (uint16_t)EC_HOST_CMD_INVALID_CHECKSUM); +BUILD_ASSERT((uint16_t)EC_RES_IN_PROGRESS == (uint16_t)EC_HOST_CMD_IN_PROGRESS); +BUILD_ASSERT((uint16_t)EC_RES_UNAVAILABLE == (uint16_t)EC_HOST_CMD_UNAVAILABLE); +BUILD_ASSERT((uint16_t)EC_RES_TIMEOUT == (uint16_t)EC_HOST_CMD_TIMEOUT); +BUILD_ASSERT((uint16_t)EC_RES_OVERFLOW == (uint16_t)EC_HOST_CMD_OVERFLOW); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_HEADER == + (uint16_t)EC_HOST_CMD_INVALID_HEADER); +BUILD_ASSERT((uint16_t)EC_RES_REQUEST_TRUNCATED == + (uint16_t)EC_HOST_CMD_REQUEST_TRUNCATED); +BUILD_ASSERT((uint16_t)EC_RES_RESPONSE_TOO_BIG == + (uint16_t)EC_HOST_CMD_RESPONSE_TOO_BIG); +BUILD_ASSERT((uint16_t)EC_RES_BUS_ERROR == (uint16_t)EC_HOST_CMD_BUS_ERROR); +BUILD_ASSERT((uint16_t)EC_RES_BUSY == (uint16_t)EC_HOST_CMD_BUSY); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_HEADER_VERSION == + (uint16_t)EC_HOST_CMD_INVALID_HEADER_VERSION); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_HEADER_CRC == + (uint16_t)EC_HOST_CMD_INVALID_HEADER_CRC); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_DATA_CRC == + (uint16_t)EC_HOST_CMD_INVALID_DATA_CRC); +BUILD_ASSERT((uint16_t)EC_RES_DUP_UNAVAILABLE == + (uint16_t)EC_HOST_CMD_DUP_UNAVAILABLE); +BUILD_ASSERT((uint16_t)EC_RES_MAX == (uint16_t)EC_HOST_CMD_MAX); + +#endif + +/* clang-format off */ +#define EC_STATUS_TEXT \ + { \ + EC_MAP_ITEM(EC_RES_SUCCESS, SUCCESS), \ + EC_MAP_ITEM(EC_RES_INVALID_COMMAND, INVALID_COMMAND), \ + EC_MAP_ITEM(EC_RES_ERROR, ERROR), \ + EC_MAP_ITEM(EC_RES_INVALID_PARAM, INVALID_PARAM), \ + EC_MAP_ITEM(EC_RES_ACCESS_DENIED, ACCESS_DENIED), \ + EC_MAP_ITEM(EC_RES_INVALID_RESPONSE, INVALID_RESPONSE), \ + EC_MAP_ITEM(EC_RES_INVALID_VERSION, INVALID_VERSION), \ + EC_MAP_ITEM(EC_RES_INVALID_CHECKSUM, INVALID_CHECKSUM), \ + EC_MAP_ITEM(EC_RES_IN_PROGRESS, IN_PROGRESS), \ + EC_MAP_ITEM(EC_RES_UNAVAILABLE, UNAVAILABLE), \ + EC_MAP_ITEM(EC_RES_TIMEOUT, TIMEOUT), \ + EC_MAP_ITEM(EC_RES_OVERFLOW, OVERFLOW), \ + EC_MAP_ITEM(EC_RES_INVALID_HEADER, INVALID_HEADER), \ + EC_MAP_ITEM(EC_RES_REQUEST_TRUNCATED, REQUEST_TRUNCATED), \ + EC_MAP_ITEM(EC_RES_RESPONSE_TOO_BIG, RESPONSE_TOO_BIG), \ + EC_MAP_ITEM(EC_RES_BUS_ERROR, BUS_ERROR), \ + EC_MAP_ITEM(EC_RES_BUSY, BUSY), \ + EC_MAP_ITEM(EC_RES_INVALID_HEADER_VERSION, INVALID_HEADER_VERSION), \ + EC_MAP_ITEM(EC_RES_INVALID_HEADER_CRC, INVALID_HEADER_CRC), \ + EC_MAP_ITEM(EC_RES_INVALID_DATA_CRC, INVALID_DATA_CRC), \ + EC_MAP_ITEM(EC_RES_DUP_UNAVAILABLE, DUP_UNAVAILABLE), \ + } +/* clang-format on */ + +#ifndef __cplusplus +#define EC_MAP_ITEM(k, v) [k] = #v +BUILD_ASSERT(ARRAY_SIZE(((const char *[])EC_STATUS_TEXT)) == EC_RES_COUNT); +#undef EC_MAP_ITEM +#endif /* - * Host event codes. Note these are 1-based, not 0-based, because ACPI query - * EC command uses code 0 to mean "no event pending". We explicitly specify - * each value in the enum listing so they won't change if we delete/insert an - * item or rearrange the list (it needs to be stable across platforms, not - * just within a single compiled instance). + * Host event codes. ACPI query EC command uses code 0 to mean "no event + * pending". We explicitly specify each value in the enum listing so they won't + * change if we delete/insert an item or rearrange the list (it needs to be + * stable across platforms, not just within a single compiled instance). */ enum host_event_code { + EC_HOST_EVENT_NONE = 0, EC_HOST_EVENT_LID_CLOSED = 1, EC_HOST_EVENT_LID_OPEN = 2, EC_HOST_EVENT_POWER_BUTTON = 3, @@ -514,7 +867,8 @@ enum host_event_code { /* Event generated by a device attached to the EC */ EC_HOST_EVENT_DEVICE = 10, EC_HOST_EVENT_THERMAL = 11, - EC_HOST_EVENT_USB_CHARGER = 12, + /* GPU related event. Formerly named EC_HOST_EVENT_USB_CHARGER. */ + EC_HOST_EVENT_GPU = 12, EC_HOST_EVENT_KEY_PRESSED = 13, /* * EC has finished initializing the host interface. The host can check @@ -561,17 +915,20 @@ enum host_event_code { /* EC desires to change state of host-controlled USB mux */ EC_HOST_EVENT_USB_MUX = 28, - /* TABLET/LAPTOP mode event*/ + /* + * The device has changed "modes". This can be one of the following: + * + * - TABLET/LAPTOP mode + * - detachable base attach/detach event + * - on body/off body transition event + */ EC_HOST_EVENT_MODE_CHANGE = 29, /* Keyboard recovery combo with hardware reinitialization */ EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT = 30, - /* - * Reserve this last bit to indicate that at least one bit in a - * secondary host event word is set. See crbug.com/633646. - */ - EC_HOST_EVENT_EXTENDED = 31, + /* WoV */ + EC_HOST_EVENT_WOV = 31, /* * The high bit of the event mask is not used as a host event code. If @@ -580,22 +937,79 @@ enum host_event_code { * raw event status via EC_MEMMAP_HOST_EVENTS but the LPC interface is * not initialized on the EC, or improperly configured on the host. */ - EC_HOST_EVENT_INVALID = 32 + EC_HOST_EVENT_INVALID = 32, + + /* Body detect (lap/desk) change event */ + EC_HOST_EVENT_BODY_DETECT_CHANGE = 33, + + /* New console logs since last snapshot */ + EC_HOST_EVENT_CONSOLE_LOGS = 34, + + /* + * Only 64 host events are supported. This enum uses 1-based counting so + * it can skip 0 (NONE), so the last legal host event number is 64. + */ }; -/* Host event mask */ -#define EC_HOST_EVENT_MASK(event_code) (1ULL << ((event_code) - 1)) -/* Arguments at EC_LPC_ADDR_HOST_ARGS */ -struct __ec_align4 ec_lpc_host_args { +/* Host event mask */ +#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1) + +/* clang-format off */ +#define HOST_EVENT_TEXT \ + { \ + [EC_HOST_EVENT_NONE] = "NONE", \ + [EC_HOST_EVENT_LID_CLOSED] = "LID_CLOSED", \ + [EC_HOST_EVENT_LID_OPEN] = "LID_OPEN", \ + [EC_HOST_EVENT_POWER_BUTTON] = "POWER_BUTTON", \ + [EC_HOST_EVENT_AC_CONNECTED] = "AC_CONNECTED", \ + [EC_HOST_EVENT_AC_DISCONNECTED] = "AC_DISCONNECTED", \ + [EC_HOST_EVENT_BATTERY_LOW] = "BATTERY_LOW", \ + [EC_HOST_EVENT_BATTERY_CRITICAL] = "BATTERY_CRITICAL", \ + [EC_HOST_EVENT_BATTERY] = "BATTERY", \ + [EC_HOST_EVENT_THERMAL_THRESHOLD] = "THERMAL_THRESHOLD", \ + [EC_HOST_EVENT_DEVICE] = "DEVICE", \ + [EC_HOST_EVENT_THERMAL] = "THERMAL", \ + [EC_HOST_EVENT_GPU] = "GPU", \ + [EC_HOST_EVENT_KEY_PRESSED] = "KEY_PRESSED", \ + [EC_HOST_EVENT_INTERFACE_READY] = "INTERFACE_READY", \ + [EC_HOST_EVENT_KEYBOARD_RECOVERY] = "KEYBOARD_RECOVERY", \ + [EC_HOST_EVENT_THERMAL_SHUTDOWN] = "THERMAL_SHUTDOWN", \ + [EC_HOST_EVENT_BATTERY_SHUTDOWN] = "BATTERY_SHUTDOWN", \ + [EC_HOST_EVENT_THROTTLE_START] = "THROTTLE_START", \ + [EC_HOST_EVENT_THROTTLE_STOP] = "THROTTLE_STOP", \ + [EC_HOST_EVENT_HANG_DETECT] = "HANG_DETECT", \ + [EC_HOST_EVENT_HANG_REBOOT] = "HANG_REBOOT", \ + [EC_HOST_EVENT_PD_MCU] = "PD_MCU", \ + [EC_HOST_EVENT_BATTERY_STATUS] = "BATTERY_STATUS", \ + [EC_HOST_EVENT_PANIC] = "PANIC", \ + [EC_HOST_EVENT_KEYBOARD_FASTBOOT] = "KEYBOARD_FASTBOOT", \ + [EC_HOST_EVENT_RTC] = "RTC", \ + [EC_HOST_EVENT_MKBP] = "MKBP", \ + [EC_HOST_EVENT_USB_MUX] = "USB_MUX", \ + [EC_HOST_EVENT_MODE_CHANGE] = "MODE_CHANGE", \ + [EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT] = \ + "KEYBOARD_RECOVERY_HW_REINIT", \ + [EC_HOST_EVENT_WOV] = "WOV", \ + [EC_HOST_EVENT_INVALID] = "INVALID", \ + [EC_HOST_EVENT_BODY_DETECT_CHANGE] = "BODY_DETECT_CHANGE", \ + [EC_HOST_EVENT_CONSOLE_LOGS] = "CONSOLE_LOGS", \ + } +/* clang-format on */ + +/** + * struct ec_lpc_host_args - Arguments at EC_LPC_ADDR_HOST_ARGS + * @flags: The host argument flags. + * @command_version: Command version. + * @data_size: The length of data. + * @checksum: Checksum; sum of command + flags + command_version + data_size + + * all params/response data bytes. + */ +struct ec_lpc_host_args { uint8_t flags; uint8_t command_version; uint8_t data_size; - /* - * Checksum; sum of command + flags + command_version + data_size + - * all params/response data bytes. - */ uint8_t checksum; -}; +} __ec_align4; /* Flags for ec_lpc_host_args.flags */ /* @@ -615,7 +1029,7 @@ struct __ec_align4 ec_lpc_host_args { * response. Command version is 0 and response data from EC is at * EC_LPC_ADDR_OLD_PARAM with unknown length. */ -#define EC_HOST_ARGS_FLAG_TO_HOST 0x02 +#define EC_HOST_ARGS_FLAG_TO_HOST 0x02 /*****************************************************************************/ /* @@ -657,48 +1071,52 @@ struct __ec_align4 ec_lpc_host_args { * request, the AP will clock in bytes until it sees the framing byte, then * clock in the response packet. */ -#define EC_SPI_FRAME_START 0xec +#define EC_SPI_FRAME_START 0xec /* * Padding bytes which are clocked out after the end of a response packet. */ -#define EC_SPI_PAST_END 0xed +#define EC_SPI_PAST_END 0xed /* - * EC is ready to receive, and has ignored the byte sent by the AP. EC expects + * EC is ready to receive, and has ignored the byte sent by the AP. EC expects * that the AP will send a valid packet header (starting with * EC_COMMAND_PROTOCOL_3) in the next 32 bytes. + * + * NOTE: Some SPI configurations place the Most Significant Bit on SDO when + * CS goes low. This macro has the Most Significant Bit set to zero, + * so SDO will not be driven high when CS goes low. */ -#define EC_SPI_RX_READY 0xf8 +#define EC_SPI_RX_READY 0x78 /* * EC has started receiving the request from the AP, but hasn't started * processing it yet. */ -#define EC_SPI_RECEIVING 0xf9 +#define EC_SPI_RECEIVING 0xf9 /* EC has received the entire request from the AP and is processing it. */ -#define EC_SPI_PROCESSING 0xfa +#define EC_SPI_PROCESSING 0xfa /* * EC received bad data from the AP, such as a packet header with an invalid * length. EC will ignore all data until chip select deasserts. */ -#define EC_SPI_RX_BAD_DATA 0xfb +#define EC_SPI_RX_BAD_DATA 0xfb /* * EC received data from the AP before it was ready. That is, the AP asserted * chip select and started clocking data before the EC was ready to receive it. * EC will ignore all data until chip select deasserts. */ -#define EC_SPI_NOT_READY 0xfc +#define EC_SPI_NOT_READY 0xfc /* * EC was ready to receive a request from the AP. EC has treated the byte sent * by the AP as part of a request packet, or (for old-style ECs) is processing * a fully received packet but is not ready to respond yet. */ -#define EC_SPI_OLD_READY 0xfd +#define EC_SPI_OLD_READY 0xfd /*****************************************************************************/ @@ -720,22 +1138,22 @@ struct __ec_align4 ec_lpc_host_args { */ #define EC_PROTO2_REQUEST_HEADER_BYTES 3 #define EC_PROTO2_REQUEST_TRAILER_BYTES 1 -#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \ - EC_PROTO2_REQUEST_TRAILER_BYTES) +#define EC_PROTO2_REQUEST_OVERHEAD \ + (EC_PROTO2_REQUEST_HEADER_BYTES + EC_PROTO2_REQUEST_TRAILER_BYTES) #define EC_PROTO2_RESPONSE_HEADER_BYTES 2 #define EC_PROTO2_RESPONSE_TRAILER_BYTES 1 -#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \ - EC_PROTO2_RESPONSE_TRAILER_BYTES) +#define EC_PROTO2_RESPONSE_OVERHEAD \ + (EC_PROTO2_RESPONSE_HEADER_BYTES + EC_PROTO2_RESPONSE_TRAILER_BYTES) /* Parameter length was limited by the LPC interface */ #define EC_PROTO2_MAX_PARAM_SIZE 0xfc /* Maximum request and response packet sizes for protocol version 2 */ -#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \ - EC_PROTO2_MAX_PARAM_SIZE) -#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \ - EC_PROTO2_MAX_PARAM_SIZE) +#define EC_PROTO2_MAX_REQUEST_SIZE \ + (EC_PROTO2_REQUEST_OVERHEAD + EC_PROTO2_MAX_PARAM_SIZE) +#define EC_PROTO2_MAX_RESPONSE_SIZE \ + (EC_PROTO2_RESPONSE_OVERHEAD + EC_PROTO2_MAX_PARAM_SIZE) /*****************************************************************************/ @@ -747,56 +1165,175 @@ struct __ec_align4 ec_lpc_host_args { #define EC_HOST_REQUEST_VERSION 3 -/* Version 3 request from host */ -struct __ec_align4 ec_host_request { - /* Structure version (=3) - * - * EC will return EC_RES_INVALID_HEADER if it receives a header with a - * version it doesn't know how to parse. - */ +/** + * struct ec_host_request - Version 3 request from host. + * @struct_version: Should be 3. The EC will return EC_RES_INVALID_HEADER if it + * receives a header with a version it doesn't know how to + * parse. + * @checksum: Checksum of request and data; sum of all bytes including checksum + * should total to 0. + * @command: Command to send (EC_CMD_...) + * @command_version: Command version. + * @reserved: Unused byte in current protocol version; set to 0. + * @data_len: Length of data which follows this header. + */ +struct ec_host_request { uint8_t struct_version; + uint8_t checksum; + uint16_t command; + uint8_t command_version; + uint8_t reserved; + uint16_t data_len; +} __ec_align4; + +#define EC_HOST_RESPONSE_VERSION 3 + +/** + * struct ec_host_response - Version 3 response from EC. + * @struct_version: Struct version (=3). + * @checksum: Checksum of response and data; sum of all bytes including + * checksum should total to 0. + * @result: EC's response to the command (separate from communication failure) + * @data_len: Length of data which follows this header. + * @reserved: Unused bytes in current protocol version; set to 0. + */ +struct ec_host_response { + uint8_t struct_version; + uint8_t checksum; + uint16_t result; + uint16_t data_len; + uint16_t reserved; +} __ec_align4; +/*****************************************************************************/ + +/* + * Host command protocol V4. + * + * Packets always start with a request or response header. They are followed + * by data_len bytes of data. If the data_crc_present flag is set, the data + * bytes are followed by a CRC-8 of that data, using x^8 + x^2 + x + 1 + * polynomial. + * + * Host algorithm when sending a request q: + * + * 101) tries_left=(some value, e.g. 3); + * 102) q.seq_num++ + * 103) q.seq_dup=0 + * 104) Calculate q.header_crc. + * 105) Send request q to EC. + * 106) Wait for response r. Go to 201 if received or 301 if timeout. + * + * 201) If r.struct_version != 4, go to 301. + * 202) If r.header_crc mismatches calculated CRC for r header, go to 301. + * 203) If r.data_crc_present and r.data_crc mismatches, go to 301. + * 204) If r.seq_num != q.seq_num, go to 301. + * 205) If r.seq_dup == q.seq_dup, return success. + * 207) If r.seq_dup == 1, go to 301. + * 208) Return error. + * + * 301) If --tries_left <= 0, return error. + * 302) If q.seq_dup == 1, go to 105. + * 303) q.seq_dup = 1 + * 304) Go to 104. + * + * EC algorithm when receiving a request q. + * EC has response buffer r, error buffer e. + * + * 101) If q.struct_version != 4, set e.result = EC_RES_INVALID_HEADER_VERSION + * and go to 301 + * 102) If q.header_crc mismatches calculated CRC, set e.result = + * EC_RES_INVALID_HEADER_CRC and go to 301 + * 103) If q.data_crc_present, calculate data CRC. If that mismatches the CRC + * byte at the end of the packet, set e.result = EC_RES_INVALID_DATA_CRC + * and go to 301. + * 104) If q.seq_dup == 0, go to 201. + * 105) If q.seq_num != r.seq_num, go to 201. + * 106) If q.seq_dup == r.seq_dup, go to 205, else go to 203. + * + * 201) Process request q into response r. + * 202) r.seq_num = q.seq_num + * 203) r.seq_dup = q.seq_dup + * 204) Calculate r.header_crc + * 205) If r.data_len > 0 and data is no longer available, set e.result = + * EC_RES_DUP_UNAVAILABLE and go to 301. + * 206) Send response r. + * + * 301) e.seq_num = q.seq_num + * 302) e.seq_dup = q.seq_dup + * 303) Calculate e.header_crc. + * 304) Send error response e. + */ + +/* Version 4 request from host */ +struct ec_host_request4 { /* - * Checksum of request and data; sum of all bytes including checksum - * should total to 0. + * bits 0-3: struct_version: Structure version (=4) + * bit 4: is_response: Is response (=0) + * bits 5-6: seq_num: Sequence number + * bit 7: seq_dup: Sequence duplicate flag */ - uint8_t checksum; + uint8_t fields0; + + /* + * bits 0-4: command_version: Command version + * bits 5-6: Reserved (set 0, ignore on read) + * bit 7: data_crc_present: Is data CRC present after data + */ + uint8_t fields1; - /* Command code */ + /* Command code (EC_CMD_*) */ uint16_t command; - /* Command version */ - uint8_t command_version; + /* Length of data which follows this header (not including data CRC) */ + uint16_t data_len; - /* Unused byte in current protocol version; set to 0 */ + /* Reserved (set 0, ignore on read) */ uint8_t reserved; - /* Length of data which follows this header */ - uint16_t data_len; -}; - -#define EC_HOST_RESPONSE_VERSION 3 + /* CRC-8 of above fields, using x^8 + x^2 + x + 1 polynomial */ + uint8_t header_crc; +} __ec_align4; -/* Version 3 response from EC */ -struct __ec_align4 ec_host_response { - /* Structure version (=3) */ - uint8_t struct_version; +/* Version 4 response from EC */ +struct ec_host_response4 { + /* + * bits 0-3: struct_version: Structure version (=4) + * bit 4: is_response: Is response (=1) + * bits 5-6: seq_num: Sequence number + * bit 7: seq_dup: Sequence duplicate flag + */ + uint8_t fields0; /* - * Checksum of response and data; sum of all bytes including checksum - * should total to 0. + * bits 0-6: Reserved (set 0, ignore on read) + * bit 7: data_crc_present: Is data CRC present after data */ - uint8_t checksum; + uint8_t fields1; /* Result code (EC_RES_*) */ uint16_t result; - /* Length of data which follows this header */ + /* Length of data which follows this header (not including data CRC) */ uint16_t data_len; - /* Unused bytes in current protocol version; set to 0 */ - uint16_t reserved; -}; + /* Reserved (set 0, ignore on read) */ + uint8_t reserved; + + /* CRC-8 of above fields, using x^8 + x^2 + x + 1 polynomial */ + uint8_t header_crc; +} __ec_align4; + +/* Fields in fields0 byte */ +#define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f +#define EC_PACKET4_0_IS_RESPONSE_MASK 0x10 +#define EC_PACKET4_0_SEQ_NUM_SHIFT 5 +#define EC_PACKET4_0_SEQ_NUM_MASK 0x60 +#define EC_PACKET4_0_SEQ_DUP_MASK 0x80 + +/* Fields in fields1 byte */ +#define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f /* (request only) */ +#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80 /*****************************************************************************/ /* @@ -822,9 +1359,13 @@ struct __ec_align4 ec_host_response { */ #define EC_CMD_PROTO_VERSION 0x0000 -struct __ec_align4 ec_response_proto_version { +/** + * struct ec_response_proto_version - Response to the proto version command. + * @version: The protocol version. + */ +struct ec_response_proto_version { uint32_t version; -}; +} __ec_align4; /* * Hello. This is a simple command to test the EC is responsive to @@ -832,43 +1373,72 @@ struct __ec_align4 ec_response_proto_version { */ #define EC_CMD_HELLO 0x0001 -struct __ec_align4 ec_params_hello { - uint32_t in_data; /* Pass anything here */ -}; +/** + * struct ec_params_hello - Parameters to the hello command. + * @in_data: Pass anything here. + */ +struct ec_params_hello { + uint32_t in_data; +} __ec_align4; -struct __ec_align4 ec_response_hello { - uint32_t out_data; /* Output will be in_data + 0x01020304 */ -}; +/** + * struct ec_response_hello - Response to the hello command. + * @out_data: Output will be in_data + 0x01020304. + */ +struct ec_response_hello { + uint32_t out_data; +} __ec_align4; /* Get version number */ #define EC_CMD_GET_VERSION 0x0002 -enum ec_current_image { +enum ec_image { EC_IMAGE_UNKNOWN = 0, EC_IMAGE_RO, - EC_IMAGE_RW -}; + EC_IMAGE_RW, + EC_IMAGE_RW_A = EC_IMAGE_RW, + EC_IMAGE_RO_B, + EC_IMAGE_RW_B, +}; + +/** + * struct ec_response_get_version - Response to the v0 get version command. + * @version_string_ro: Null-terminated RO firmware version string. + * @version_string_rw: Null-terminated RW firmware version string. + * @reserved: Unused bytes; was previously RW-B firmware version string. + * @current_image: One of ec_image. + */ +struct ec_response_get_version { + char version_string_ro[32]; + char version_string_rw[32]; + char reserved[32]; /* Changed to cros_fwid_ro in version 1 */ + uint32_t current_image; +} __ec_align4; -struct __ec_align4 ec_response_get_version { - /* Null-terminated version strings for RO, RW */ +/** + * struct ec_response_get_version_v1 - Response to the v1 get version command. + * + * ec_response_get_version_v1 is a strict superset of ec_response_get_version. + * The v1 response changes the semantics of one field (reserved to cros_fwid_ro) + * and adds one additional field (cros_fwid_rw). + * + * @version_string_ro: Null-terminated RO firmware version string. + * @version_string_rw: Null-terminated RW firmware version string. + * @cros_fwid_ro: Null-terminated RO CrOS FWID string. + * @current_image: One of ec_image. + * @cros_fwid_rw: Null-terminated RW CrOS FWID string. + */ +struct ec_response_get_version_v1 { char version_string_ro[32]; char version_string_rw[32]; - char reserved[32]; /* Was previously RW-B string */ - uint32_t current_image; /* One of ec_current_image */ -}; + char cros_fwid_ro[32]; /* Added in version 1 (Used to be reserved) */ + uint32_t current_image; + char cros_fwid_rw[32]; /* Added in version 1 */ +} __ec_align4; -/* Read test */ +/* Read test - OBSOLETE */ #define EC_CMD_READ_TEST 0x0003 -struct __ec_align4 ec_params_read_test { - uint32_t offset; /* Starting value for read buffer */ - uint32_t size; /* Size to read in bytes */ -}; - -struct __ec_align4 ec_response_read_test { - uint32_t data[32]; -}; - /* * Get build information * @@ -879,19 +1449,28 @@ struct __ec_align4 ec_response_read_test { /* Get chip info */ #define EC_CMD_GET_CHIP_INFO 0x0005 -struct __ec_align4 ec_response_get_chip_info { - /* Null-terminated strings */ +/** + * struct ec_response_get_chip_info - Response to the get chip info command. + * @vendor: Null-terminated string for chip vendor. + * @name: Null-terminated string for chip name. + * @revision: Null-terminated string for chip mask version. + */ +struct ec_response_get_chip_info { char vendor[32]; char name[32]; - char revision[32]; /* Mask version */ -}; + char revision[32]; +} __ec_align4; /* Get board HW version */ #define EC_CMD_GET_BOARD_VERSION 0x0006 -struct __ec_align2 ec_response_board_version { - uint16_t board_version; /* A monotonously incrementing number. */ -}; +/** + * struct ec_response_board_version - Response to the board version command. + * @board_version: A monotonously incrementing number. + */ +struct ec_response_board_version { + uint16_t board_version; +} __ec_align2; /* * Read memory-mapped data. @@ -903,29 +1482,44 @@ struct __ec_align2 ec_response_board_version { */ #define EC_CMD_READ_MEMMAP 0x0007 -struct __ec_align1 ec_params_read_memmap { - uint8_t offset; /* Offset in memmap (EC_MEMMAP_*) */ - uint8_t size; /* Size to read in bytes */ -}; +/** + * struct ec_params_read_memmap - Parameters for the read memory map command. + * @offset: Offset in memmap (EC_MEMMAP_*). + * @size: Size to read in bytes. + */ +struct ec_params_read_memmap { + uint8_t offset; + uint8_t size; +} __ec_align1; /* Read versions supported for a command */ #define EC_CMD_GET_CMD_VERSIONS 0x0008 -struct __ec_align1 ec_params_get_cmd_versions { - uint8_t cmd; /* Command to check */ -}; - -struct __ec_align2 ec_params_get_cmd_versions_v1 { - uint16_t cmd; /* Command to check */ -}; +/** + * struct ec_params_get_cmd_versions - Parameters for the get command versions. + * @cmd: Command to check. + */ +struct ec_params_get_cmd_versions { + uint8_t cmd; +} __ec_align1; -struct __ec_align4 ec_response_get_cmd_versions { - /* - * Mask of supported versions; use EC_VER_MASK() to compare with a - * desired version. - */ +/** + * struct ec_params_get_cmd_versions_v1 - Parameters for the get command + * versions (v1) + * @cmd: Command to check. + */ +struct ec_params_get_cmd_versions_v1 { + uint16_t cmd; +} __ec_align2; + +/** + * struct ec_response_get_cmd_version - Response to the get command versions. + * @version_mask: Mask of supported versions; use EC_VER_MASK() to compare with + * a desired version. + */ +struct ec_response_get_cmd_versions { uint32_t version_mask; -}; +} __ec_align4; /* * Check EC communications status (busy). This is needed on i2c/spi but not @@ -934,81 +1528,88 @@ struct __ec_align4 ec_response_get_cmd_versions { * lpc must read the status from the command register. Attempting this on * lpc will overwrite the args/parameter space and corrupt its data. */ -#define EC_CMD_GET_COMMS_STATUS 0x0009 +#define EC_CMD_GET_COMMS_STATUS 0x0009 /* Avoid using ec_status which is for return values */ enum ec_comms_status { - EC_COMMS_STATUS_PROCESSING = 1 << 0, /* Processing cmd */ + EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */ }; -struct __ec_align4 ec_response_get_comms_status { - uint32_t flags; /* Mask of enum ec_comms_status */ -}; +/** + * struct ec_response_get_comms_status - Response to the get comms status + * command. + * @flags: Mask of enum ec_comms_status. + */ +struct ec_response_get_comms_status { + uint32_t flags; /* Mask of enum ec_comms_status */ +} __ec_align4; /* Fake a variety of responses, purely for testing purposes. */ -#define EC_CMD_TEST_PROTOCOL 0x000A +#define EC_CMD_TEST_PROTOCOL 0x000A /* Tell the EC what to send back to us. */ -struct __ec_align4 ec_params_test_protocol { +struct ec_params_test_protocol { uint32_t ec_result; uint32_t ret_len; uint8_t buf[32]; -}; +} __ec_align4; /* Here it comes... */ -struct __ec_align4 ec_response_test_protocol { +struct ec_response_test_protocol { uint8_t buf[32]; -}; +} __ec_align4; /* Get protocol information */ -#define EC_CMD_GET_PROTOCOL_INFO 0x000B +#define EC_CMD_GET_PROTOCOL_INFO 0x000B /* Flags for ec_response_get_protocol_info.flags */ /* EC_RES_IN_PROGRESS may be returned if a command is slow */ -#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0) - -struct __ec_align4 ec_response_get_protocol_info { +#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED BIT(0) + +/** + * struct ec_response_get_protocol_info - Response to the get protocol info. + * @protocol_versions: Bitmask of protocol versions supported (1 << n means + * version n). + * @max_request_packet_size: Maximum request packet size in bytes. + * @max_response_packet_size: Maximum response packet size in bytes. + * @flags: see EC_PROTOCOL_INFO_* + */ +struct ec_response_get_protocol_info { /* Fields which exist if at least protocol version 3 supported */ - - /* Bitmask of protocol versions supported (1 << n means version n)*/ uint32_t protocol_versions; - - /* Maximum request packet size, in bytes */ uint16_t max_request_packet_size; - - /* Maximum response packet size, in bytes */ uint16_t max_response_packet_size; - - /* Flags; see EC_PROTOCOL_INFO_* */ uint32_t flags; -}; +} __ec_align4; /*****************************************************************************/ /* Get/Set miscellaneous values */ /* The upper byte of .flags tells what to do (nothing means "get") */ -#define EC_GSV_SET 0x80000000 +#define EC_GSV_SET 0x80000000 -/* The lower three bytes of .flags identifies the parameter, if that has - meaning for an individual command. */ +/* + * The lower three bytes of .flags identifies the parameter, if that has + * meaning for an individual command. + */ #define EC_GSV_PARAM_MASK 0x00ffffff -struct __ec_align4 ec_params_get_set_value { +struct ec_params_get_set_value { uint32_t flags; uint32_t value; -}; +} __ec_align4; -struct __ec_align4 ec_response_get_set_value { +struct ec_response_get_set_value { uint32_t flags; uint32_t value; -}; +} __ec_align4; /* More than one command can use these structs to get/set parameters. */ -#define EC_CMD_GSV_PAUSE_IN_S5 0x000C +#define EC_CMD_GSV_PAUSE_IN_S5 0x000C /*****************************************************************************/ /* List the features supported by the firmware */ -#define EC_CMD_GET_FEATURES 0x000D +#define EC_CMD_GET_FEATURES 0x000D /* Supported features */ enum ec_feature_code { @@ -1135,66 +1736,143 @@ enum ec_feature_code { * mux. */ EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43, -}; - -#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) -#define EC_FEATURE_MASK_1(event_code) BIT(event_code - 32) - -struct ec_response_get_features { - uint32_t flags[2]; -} __ec_align4; - -/*****************************************************************************/ -/* Get the board's SKU ID from EC */ -#define EC_CMD_GET_SKU_ID 0x000E - -/* Set SKU ID from AP */ -#define EC_CMD_SET_SKU_ID 0x000F - -struct __ec_align4 ec_sku_id_info { - uint32_t sku_id; -}; - -/*****************************************************************************/ -/* Flash commands */ - -/* Get flash info */ -#define EC_CMD_FLASH_INFO 0x0010 -#define EC_VER_FLASH_INFO 2 - -/* Version 0 returns these fields */ -struct __ec_align4 ec_response_flash_info { - /* Usable flash size, in bytes */ - uint32_t flash_size; /* - * Write block size. Write offset and size must be a multiple - * of this. + * The EC supports entering and residing in S4. */ - uint32_t write_block_size; + EC_FEATURE_S4_RESIDENCY = 44, /* - * Erase block size. Erase offset and size must be a multiple - * of this. + * The EC supports the AP directing mux sets for the board. */ - uint32_t erase_block_size; + EC_FEATURE_TYPEC_AP_MUX_SET = 45, /* - * Protection block size. Protection offset and size must be a - * multiple of this. + * The EC supports the AP composing VDMs for us to send. */ - uint32_t protect_block_size; + EC_FEATURE_TYPEC_AP_VDM_SEND = 46, + /* + * The EC supports system safe mode panic recovery. + */ + EC_FEATURE_SYSTEM_SAFE_MODE = 47, + /* + * The EC will reboot on runtime assertion failures. + */ + EC_FEATURE_ASSERT_REBOOTS = 48, + /* + * The EC image is built with tokenized logging enabled. + */ + EC_FEATURE_TOKENIZED_LOGGING = 49, + /* + * The EC supports triggering an STB dump. + */ + EC_FEATURE_AMD_STB_DUMP = 50, + /* + * The EC supports memory dump commands. + */ + EC_FEATURE_MEMORY_DUMP = 51, + /* + * The EC supports DP2.1 capability + */ + EC_FEATURE_TYPEC_DP2_1 = 52, + /* + * The MCU is System Companion Processor Core 1 + */ + EC_FEATURE_SCP_C1 = 53, + /* + * The EC supports UCSI PPM. + */ + EC_FEATURE_UCSI_PPM = 54, + /* + * The EC supports Strauss keyboard. + */ + EC_FEATURE_STRAUSS = 55, + /* + * The EC supports PoE. + */ + EC_FEATURE_POE = 56, + /* + * The EC supports a hybrid boost charger + */ + EC_FEATURE_CHARGER_HYBRID_POWER_BOOST = 57, + /* + * Support signaling new console logs via host event + */ + EC_FEATURE_CONSOLE_LOG_EVENT = 58, }; -/* Flags for version 1+ flash info command */ -/* EC flash erases bits to 0 instead of 1 */ -#define EC_FLASH_INFO_ERASE_TO_0 (1 << 0) +#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) +#define EC_FEATURE_MASK_1(event_code) BIT(event_code - 32) + +struct ec_response_get_features { + uint32_t flags[2]; +} __ec_align4; + +/*****************************************************************************/ +/* Get the board's SKU ID from EC */ +#define EC_CMD_GET_SKU_ID 0x000E + +/* Set SKU ID from AP */ +#define EC_CMD_SET_SKU_ID 0x000F + +struct ec_sku_id_info { + uint32_t sku_id; +} __ec_align4; + +/*****************************************************************************/ +/* Flash commands */ + +/* Get flash info */ +#define EC_CMD_FLASH_INFO 0x0010 +#define EC_VER_FLASH_INFO 2 + +/** + * struct ec_response_flash_info - Response to the flash info command. + * @flash_size: Usable flash size in bytes. + * @write_block_size: Write block size. Write offset and size must be a + * multiple of this. + * @erase_block_size: Erase block size. Erase offset and size must be a + * multiple of this. + * @protect_block_size: Protection block size. Protection offset and size + * must be a multiple of this. + * + * Version 0 returns these fields. + */ +struct ec_response_flash_info { + uint32_t flash_size; + uint32_t write_block_size; + uint32_t erase_block_size; + uint32_t protect_block_size; +} __ec_align4; + +/* + * Flags for version 1+ flash info command + * EC flash erases bits to 0 instead of 1. + */ +#define EC_FLASH_INFO_ERASE_TO_0 BIT(0) -/* Flash must be selected for read/write/erase operations to succeed. This may +/* + * Flash must be selected for read/write/erase operations to succeed. This may * be necessary on a chip where write/erase can be corrupted by other board * activity, or where the chip needs to enable some sort of programming voltage, * or where the read/write/erase operations require cleanly suspending other - * chip functionality. */ -#define EC_FLASH_INFO_SELECT_REQUIRED (1 << 1) - -/* + * chip functionality. + */ +#define EC_FLASH_INFO_SELECT_REQUIRED BIT(1) + +/** + * struct ec_response_flash_info_1 - Response to the flash info v1 command. + * @flash_size: Usable flash size in bytes. + * @write_block_size: Write block size. Write offset and size must be a + * multiple of this. + * @erase_block_size: Erase block size. Erase offset and size must be a + * multiple of this. + * @protect_block_size: Protection block size. Protection offset and size + * must be a multiple of this. + * @write_ideal_size: Ideal write size in bytes. Writes will be fastest if + * size is exactly this and offset is a multiple of this. + * For example, an EC may have a write buffer which can do + * half-page operations if data is aligned, and a slower + * word-at-a-time write mode. + * @flags: Flags; see EC_FLASH_INFO_* + * * Version 1 returns the same initial fields as version 0, with additional * fields following. * @@ -1208,7 +1886,7 @@ struct __ec_align4 ec_response_flash_info { * The EC returns the number of banks describing the flash memory. * It adds banks descriptions up to num_banks_desc. */ -struct __ec_align4 ec_response_flash_info_1 { +struct ec_response_flash_info_1 { /* Version 0 fields; see above for description */ uint32_t flash_size; uint32_t write_block_size; @@ -1216,24 +1894,16 @@ struct __ec_align4 ec_response_flash_info_1 { uint32_t protect_block_size; /* Version 1 adds these fields: */ - /* - * Ideal write size in bytes. Writes will be fastest if size is - * exactly this and offset is a multiple of this. For example, an EC - * may have a write buffer which can do half-page operations if data is - * aligned, and a slower word-at-a-time write mode. - */ uint32_t write_ideal_size; - - /* Flags; see EC_FLASH_INFO_* */ uint32_t flags; -}; +} __ec_align4; -struct __ec_align4 ec_params_flash_info_2 { +struct ec_params_flash_info_2 { /* Number of banks to describe */ uint16_t num_banks_desc; /* Reserved; set 0; ignore on read */ uint8_t reserved[2]; -}; +} __ec_align4; struct ec_flash_bank { /* Number of sector is in this bank. */ @@ -1250,7 +1920,7 @@ struct ec_flash_bank { uint8_t reserved[2]; }; -struct __ec_align4 ec_response_flash_info_2 { +struct ec_response_flash_info_2 { /* Total flash in the EC. */ uint32_t flash_size; /* Flags; see EC_FLASH_INFO_* */ @@ -1261,8 +1931,8 @@ struct __ec_align4 ec_response_flash_info_2 { uint16_t num_banks_total; /* Number of banks described in banks array. */ uint16_t num_banks_desc; - struct ec_flash_bank banks[0]; -}; + struct ec_flash_bank banks[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; /* * Read flash @@ -1271,10 +1941,15 @@ struct __ec_align4 ec_response_flash_info_2 { */ #define EC_CMD_FLASH_READ 0x0011 -struct __ec_align4 ec_params_flash_read { - uint32_t offset; /* Byte offset to read */ - uint32_t size; /* Size to read in bytes */ -}; +/** + * struct ec_params_flash_read - Parameters for the flash read command. + * @offset: Byte offset to read. + * @size: Size to read in bytes. + */ +struct ec_params_flash_read { + uint32_t offset; + uint32_t size; +} __ec_align4; /* Write flash */ #define EC_CMD_FLASH_WRITE 0x0012 @@ -1283,23 +1958,42 @@ struct __ec_align4 ec_params_flash_read { /* Version 0 of the flash command supported only 64 bytes of data */ #define EC_FLASH_WRITE_VER0_SIZE 64 -struct __ec_align4 ec_params_flash_write { - uint32_t offset; /* Byte offset to write */ - uint32_t size; /* Size to write in bytes */ - /* Followed by data to write */ -}; +/** + * struct ec_params_flash_write - Parameters for the flash write command. + * @offset: Byte offset to write. + * @size: Size to write in bytes. + * @data: Data to write. + * @data.words32: uint32_t data to write. + * @data.bytes: uint8_t data to write. + */ +struct ec_params_flash_write { + uint32_t offset; + uint32_t size; + /* Followed by data to write. This union allows accessing an + * underlying buffer as uint32s or uint8s for convenience. + */ + union { + uint32_t words32[FLEXIBLE_ARRAY_MEMBER_SIZE]; + uint8_t bytes[FLEXIBLE_ARRAY_MEMBER_SIZE]; + } data; +} __ec_align4; +BUILD_ASSERT(member_size(struct ec_params_flash_write, data) == 0); /* Erase flash */ #define EC_CMD_FLASH_ERASE 0x0013 -/* v0 */ -struct __ec_align4 ec_params_flash_erase { - uint32_t offset; /* Byte offset to erase */ - uint32_t size; /* Size to erase in bytes */ -}; +/** + * struct ec_params_flash_erase - Parameters for the flash erase command, v0. + * @offset: Byte offset to erase. + * @size: Size to erase in bytes. + */ +struct ec_params_flash_erase { + uint32_t offset; + uint32_t size; +} __ec_align4; -#define EC_VER_FLASH_WRITE 1 -/* v1 add async erase: +/* + * v1 add async erase: * subcommands can returns: * EC_RES_SUCCESS : erased (see ERASE_SECTOR_ASYNC case below). * EC_RES_INVALID_PARAM : offset/size are not aligned on a erase boundary. @@ -1316,21 +2010,24 @@ struct __ec_align4 ec_params_flash_erase { * permitted while erasing. (For instance, STM32F4). */ enum ec_flash_erase_cmd { - FLASH_ERASE_SECTOR, /* Erase and wait for result */ - FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */ - FLASH_ERASE_GET_RESULT, /* Ask for last erase result */ + FLASH_ERASE_SECTOR, /* Erase and wait for result */ + FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */ + FLASH_ERASE_GET_RESULT, /* Ask for last erase result */ }; -struct __ec_align4 ec_params_flash_erase_v1 { - /* One of ec_flash_erase_cmd. */ - uint8_t cmd; - /* Pad byte; currently always contains 0 */ - uint8_t reserved; - /* No flags defined yet; set to 0 */ +/** + * struct ec_params_flash_erase_v1 - Parameters for the flash erase command, v1. + * @cmd: One of ec_flash_erase_cmd. + * @reserved: Pad byte; currently always contains 0. + * @flag: No flags defined yet; set to 0. + * @params: Same as v0 parameters. + */ +struct ec_params_flash_erase_v1 { + uint8_t cmd; + uint8_t reserved; uint16_t flag; - /* Same as v0 parameters. */ struct ec_params_flash_erase params; -}; +} __ec_align4; /* * Get/set flash protection. @@ -1343,56 +2040,78 @@ struct __ec_align4 ec_params_flash_erase_v1 { * If mask=0, simply returns the current flags state. */ #define EC_CMD_FLASH_PROTECT 0x0015 -#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */ +#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */ /* Flags for flash protection */ /* RO flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RO_AT_BOOT (1 << 0) +#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0) /* * RO flash code protected now. If this bit is set, at-boot status cannot * be changed. */ -#define EC_FLASH_PROTECT_RO_NOW (1 << 1) +#define EC_FLASH_PROTECT_RO_NOW BIT(1) /* Entire flash code protected now, until reboot. */ -#define EC_FLASH_PROTECT_ALL_NOW (1 << 2) +#define EC_FLASH_PROTECT_ALL_NOW BIT(2) /* Flash write protect GPIO is asserted now */ -#define EC_FLASH_PROTECT_GPIO_ASSERTED (1 << 3) +#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3) /* Error - at least one bank of flash is stuck locked, and cannot be unlocked */ -#define EC_FLASH_PROTECT_ERROR_STUCK (1 << 4) +#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4) /* * Error - flash protection is in inconsistent state. At least one bank of * flash which should be protected is not protected. Usually fixed by * re-requesting the desired flags, or by a hard reset if that fails. */ -#define EC_FLASH_PROTECT_ERROR_INCONSISTENT (1 << 5) +#define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5) /* Entire flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_ALL_AT_BOOT (1 << 6) +#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6) /* RW flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RW_AT_BOOT (1 << 7) +#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7) /* RW flash code protected now. */ -#define EC_FLASH_PROTECT_RW_NOW (1 << 8) +#define EC_FLASH_PROTECT_RW_NOW BIT(8) /* Rollback information flash region protected when the EC boots */ -#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT (1 << 9) +#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9) /* Rollback information flash region protected now */ -#define EC_FLASH_PROTECT_ROLLBACK_NOW (1 << 10) +#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10) +/* Error - Unknown error */ +#define EC_FLASH_PROTECT_ERROR_UNKNOWN BIT(11) + +/** + * struct ec_params_flash_protect - Parameters for the flash protect command. + * @mask: Bits in flags to apply. + * @flags: New flags to apply. + */ +struct ec_params_flash_protect { + uint32_t mask; + uint32_t flags; +} __ec_align4; -struct __ec_align4 ec_params_flash_protect { - uint32_t mask; /* Bits in flags to apply */ - uint32_t flags; /* New flags to apply */ +enum flash_protect_action { + FLASH_PROTECT_ASYNC = 0, + FLASH_PROTECT_GET_RESULT = 1, }; -struct __ec_align4 ec_response_flash_protect { - /* Current value of flash protect flags */ +/* Version 2 of the command is "asynchronous". */ +struct ec_params_flash_protect_v2 { + uint8_t action; /**< enum flash_protect_action */ + uint8_t reserved[3]; /**< padding for alignment */ + uint32_t mask; + uint32_t flags; +} __ec_align4; + +/** + * struct ec_response_flash_protect - Response to the flash protect command. + * @flags: Current value of flash protect flags. + * @valid_flags: Flags which are valid on this platform. This allows the + * caller to distinguish between flags which aren't set vs. flags + * which can't be set on this platform. + * @writable_flags: Flags which can be changed given the current protection + * state. + */ +struct ec_response_flash_protect { uint32_t flags; - /* - * Flags which are valid on this platform. This allows the caller - * to distinguish between flags which aren't set vs. flags which can't - * be set on this platform. - */ uint32_t valid_flags; - /* Flags which can be changed given the current protection state */ uint32_t writable_flags; -}; +} __ec_align4; /* * Note: commands 0x14 - 0x19 version 0 were old commands to get/set flash @@ -1406,52 +2125,50 @@ struct __ec_align4 ec_response_flash_protect { enum ec_flash_region { /* Region which holds read-only EC image */ EC_FLASH_REGION_RO = 0, - /* Region which holds active rewritable EC image */ + /* + * Region which holds active RW image. 'Active' is different from + * 'running'. Active means 'scheduled-to-run'. Since RO image always + * scheduled to run, active/non-active applies only to RW images (for + * the same reason 'update' applies only to RW images. It's a state of + * an image on a flash. Running image can be RO, RW_A, RW_B but active + * image can only be RW_A or RW_B. In recovery mode, an active RW image + * doesn't enter 'running' state but it's still active on a flash. + */ EC_FLASH_REGION_ACTIVE, /* * Region which should be write-protected in the factory (a superset of * EC_FLASH_REGION_RO) */ EC_FLASH_REGION_WP_RO, - /* Region which holds updatable image */ + /* Region which holds updatable (non-active) RW image */ EC_FLASH_REGION_UPDATE, /* Number of regions */ EC_FLASH_REGION_COUNT, }; +/* + * 'RW' is vague if there are multiple RW images; we mean the active one, + * so the old constant is deprecated. + */ +#define EC_FLASH_REGION_RW EC_FLASH_REGION_ACTIVE -struct __ec_align4 ec_params_flash_region_info { - uint32_t region; /* enum ec_flash_region */ -}; +/** + * struct ec_params_flash_region_info - Parameters for the flash region info + * command. + * @region: Flash region; see EC_FLASH_REGION_* + */ +struct ec_params_flash_region_info { + uint32_t region; +} __ec_align4; -struct __ec_align4 ec_response_flash_region_info { +struct ec_response_flash_region_info { uint32_t offset; uint32_t size; -}; - -/* Read/write VbNvContext */ -#define EC_CMD_VBNV_CONTEXT 0x0017 -#define EC_VER_VBNV_CONTEXT 1 -#define EC_VBNV_BLOCK_SIZE 16 -#define EC_VBNV_BLOCK_SIZE_V2 64 - -enum ec_vbnvcontext_op { - EC_VBNV_CONTEXT_OP_READ, - EC_VBNV_CONTEXT_OP_WRITE, -}; - -struct __ec_align4 ec_params_vbnvcontext { - uint32_t op; - uint8_t block[EC_VBNV_BLOCK_SIZE_V2]; -}; - -struct __ec_align4 ec_response_vbnvcontext { - uint8_t block[EC_VBNV_BLOCK_SIZE_V2]; -}; +} __ec_align4; /* Get SPI flash information */ #define EC_CMD_FLASH_SPI_INFO 0x0018 -struct __ec_align1 ec_response_flash_spi_info { +struct ec_response_flash_spi_info { /* JEDEC info from command 0x9F (manufacturer, memory type, size) */ uint8_t jedec[3]; @@ -1463,70 +2180,163 @@ struct __ec_align1 ec_response_flash_spi_info { /* Status registers from command 0x05 and 0x35 */ uint8_t sr1, sr2; -}; +} __ec_align1; /* Select flash during flash operations */ #define EC_CMD_FLASH_SELECT 0x0019 -struct __ec_align4 ec_params_flash_select { - /* 1 to select flash, 0 to deselect flash */ +/** + * struct ec_params_flash_select - Parameters for the flash select command. + * @select: 1 to select flash, 0 to deselect flash + */ +struct ec_params_flash_select { uint8_t select; +} __ec_align4; + +/** + * Request random numbers to be generated and returned. + * Can be used to test the random number generator is truly random. + * See https://csrc.nist.gov/publications/detail/sp/800-22/rev-1a/final and + * https://webhome.phy.duke.edu/~rgb/General/dieharder.php. + */ +#define EC_CMD_RAND_NUM 0x001A +#define EC_VER_RAND_NUM 0 + +struct ec_params_rand_num { + uint16_t num_rand_bytes; /**< num random bytes to generate */ +} __ec_align4; + +struct ec_response_rand_num { + /** + * generated random numbers in the range of 1 to EC_MAX_INSIZE. The true + * size of rand is determined by ec_params_rand_num's num_rand_bytes. + */ + uint8_t rand[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align1; +BUILD_ASSERT(sizeof(struct ec_response_rand_num) == 0); + +/** + * Get information about the key used to sign the RW firmware. + * For more details on the fields, see "struct vb21_packed_key". + */ +#define EC_CMD_RWSIG_INFO 0x001B +#define EC_VER_RWSIG_INFO 0 + +#define VBOOT2_KEY_ID_BYTES 20 + +#ifdef CHROMIUM_EC +/* Don't force external projects to depend on the vboot headers. */ +#include "vb21_struct.h" +BUILD_ASSERT(sizeof(struct vb2_id) == VBOOT2_KEY_ID_BYTES); +#endif + +struct ec_response_rwsig_info { + /** + * Signature algorithm used by the key + * (enum vb2_signature_algorithm). + */ + uint16_t sig_alg; + + /** + * Hash digest algorithm used with the key + * (enum vb2_hash_algorithm). + */ + uint16_t hash_alg; + + /** Key version. */ + uint32_t key_version; + + /** Key ID (struct vb2_id). */ + uint8_t key_id[VBOOT2_KEY_ID_BYTES]; + + uint8_t key_is_valid; + + /** Alignment padding. */ + uint8_t reserved[3]; +} __ec_align4; + +BUILD_ASSERT(sizeof(struct ec_response_rwsig_info) == 32); + +/** + * Get information about the system, such as reset flags, locked state, etc. + */ +#define EC_CMD_SYSINFO 0x001C +#define EC_VER_SYSINFO 0 + +enum sysinfo_flags { + SYSTEM_IS_LOCKED = BIT(0), + SYSTEM_IS_FORCE_LOCKED = BIT(1), + SYSTEM_JUMP_ENABLED = BIT(2), + SYSTEM_JUMPED_TO_CURRENT_IMAGE = BIT(3), + SYSTEM_REBOOT_AT_SHUTDOWN = BIT(4), + /* + * Used internally. It's set when EC_HOST_EVENT_KEYBOARD_RECOVERY is + * set and cleared when the system shuts down (not when the host event + * flag is cleared). + */ + SYSTEM_IN_MANUAL_RECOVERY = BIT(5), }; +struct ec_response_sysinfo { + uint32_t reset_flags; /**< EC_RESET_FLAG_* flags */ + uint32_t current_image; /**< enum ec_image */ + uint32_t flags; /**< enum sysinfo_flags */ +} __ec_align4; + /*****************************************************************************/ /* PWM commands */ /* Get fan target RPM */ #define EC_CMD_PWM_GET_FAN_TARGET_RPM 0x0020 -struct __ec_align4 ec_response_pwm_get_fan_rpm { +struct ec_response_pwm_get_fan_rpm { uint32_t rpm; -}; +} __ec_align4; /* Set target fan RPM */ #define EC_CMD_PWM_SET_FAN_TARGET_RPM 0x0021 /* Version 0 of input params */ -struct __ec_align4 ec_params_pwm_set_fan_target_rpm_v0 { +struct ec_params_pwm_set_fan_target_rpm_v0 { uint32_t rpm; -}; +} __ec_align4; /* Version 1 of input params */ -struct __ec_align_size1 ec_params_pwm_set_fan_target_rpm_v1 { +struct ec_params_pwm_set_fan_target_rpm_v1 { uint32_t rpm; uint8_t fan_idx; -}; +} __ec_align_size1; /* Get keyboard backlight */ /* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ #define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x0022 -struct __ec_align1 ec_response_pwm_get_keyboard_backlight { +struct ec_response_pwm_get_keyboard_backlight { uint8_t percent; uint8_t enabled; -}; +} __ec_align1; /* Set keyboard backlight */ /* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ #define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x0023 -struct __ec_align1 ec_params_pwm_set_keyboard_backlight { +struct ec_params_pwm_set_keyboard_backlight { uint8_t percent; -}; +} __ec_align1; /* Set target fan PWM duty cycle */ #define EC_CMD_PWM_SET_FAN_DUTY 0x0024 /* Version 0 of input params */ -struct __ec_align4 ec_params_pwm_set_fan_duty_v0 { +struct ec_params_pwm_set_fan_duty_v0 { uint32_t percent; -}; +} __ec_align4; /* Version 1 of input params */ -struct __ec_align_size1 ec_params_pwm_set_fan_duty_v1 { +struct ec_params_pwm_set_fan_duty_v1 { uint32_t percent; uint8_t fan_idx; -}; +} __ec_align_size1; #define EC_CMD_PWM_SET_DUTY 0x0025 /* 16 bit duty cycle, 0xffff = 100% */ @@ -1542,22 +2352,32 @@ enum ec_pwm_type { EC_PWM_TYPE_COUNT, }; -struct __ec_align4 ec_params_pwm_set_duty { - uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ - uint8_t pwm_type; /* ec_pwm_type */ - uint8_t index; /* Type-specific index, or 0 if unique */ -}; +struct ec_params_pwm_set_duty { + uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ + uint8_t pwm_type; /* ec_pwm_type */ + uint8_t index; /* Type-specific index, or 0 if unique */ +} __ec_align4; #define EC_CMD_PWM_GET_DUTY 0x0026 -struct __ec_align1 ec_params_pwm_get_duty { - uint8_t pwm_type; /* ec_pwm_type */ - uint8_t index; /* Type-specific index, or 0 if unique */ -}; +struct ec_params_pwm_get_duty { + uint8_t pwm_type; /* ec_pwm_type */ + uint8_t index; /* Type-specific index, or 0 if unique */ +} __ec_align1; -struct __ec_align2 ec_response_pwm_get_duty { - uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ -}; +struct ec_response_pwm_get_duty { + uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ +} __ec_align2; + +#define EC_CMD_PWM_GET_FAN_DUTY 0x0027 + +struct ec_params_pwm_get_fan_duty { + uint8_t fan_idx; +} __ec_align1; + +struct ec_response_pwm_get_fan_duty { + uint32_t percent; /* Percentage of duty cycle, ranging from 0 ~ 100 */ +} __ec_align4; /*****************************************************************************/ /* @@ -1568,21 +2388,23 @@ struct __ec_align2 ec_response_pwm_get_duty { */ #define EC_CMD_LIGHTBAR_CMD 0x0028 -struct __ec_todo_unpacked rgb_s { +struct rgb_s { uint8_t r, g, b; -}; +} __ec_todo_unpacked; #define LB_BATTERY_LEVELS 4 -/* List of tweakable parameters. NOTE: It's __packed so it can be sent in a + +/* + * List of tweakable parameters. NOTE: It's __packed so it can be sent in a * host command, but the alignment is the same regardless. Keep it that way. */ -struct __ec_todo_packed lightbar_params_v0 { +struct lightbar_params_v0 { /* Timing */ int32_t google_ramp_up; int32_t google_ramp_down; int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ int32_t s0s3_ramp_down; int32_t s3_sleep_for; int32_t s3_ramp_up; @@ -1590,33 +2412,33 @@ struct __ec_todo_packed lightbar_params_v0 { /* Oscillation */ uint8_t new_s0; - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ /* Battery level thresholds */ uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ -}; + struct rgb_s color[8]; /* 0-3 are Google colors */ +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v1 { +struct lightbar_params_v1 { /* Timing */ int32_t google_ramp_up; int32_t google_ramp_down; int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ int32_t s0s3_ramp_down; int32_t s3_sleep_for; int32_t s3_ramp_up; @@ -1636,28 +2458,28 @@ struct __ec_todo_packed lightbar_params_v1 { uint8_t tap_idx[3]; /* Oscillation */ - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ /* Battery level thresholds */ uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ /* s5: single color pulse on inhibited power-up */ uint8_t s5_idx; /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ -}; + struct rgb_s color[8]; /* 0-3 are Google colors */ +} __ec_todo_packed; /* Lightbar command params v2 * crbug.com/467716 @@ -1668,13 +2490,13 @@ struct __ec_todo_packed lightbar_params_v1 { * NOTE: Each of these groups must be less than 120 bytes. */ -struct __ec_todo_packed lightbar_params_v2_timing { +struct lightbar_params_v2_timing { /* Timing */ int32_t google_ramp_up; int32_t google_ramp_down; int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ int32_t s0s3_ramp_down; int32_t s3_sleep_for; int32_t s3_ramp_up; @@ -1684,9 +2506,9 @@ struct __ec_todo_packed lightbar_params_v2_timing { int32_t tap_tick_delay; int32_t tap_gate_delay; int32_t tap_display_time; -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_tap { +struct lightbar_params_v2_tap { /* Tap-for-battery params */ uint8_t tap_pct_red; uint8_t tap_pct_green; @@ -1694,56 +2516,79 @@ struct __ec_todo_packed lightbar_params_v2_tap { uint8_t tap_seg_max_on; uint8_t tap_seg_osc; uint8_t tap_idx[3]; -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_oscillation { +struct lightbar_params_v2_oscillation { /* Oscillation */ - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ -}; + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_brightness { +struct lightbar_params_v2_brightness { /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ -}; + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_thresholds { +struct lightbar_params_v2_thresholds { /* Battery level thresholds */ uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_colors { +struct lightbar_params_v2_colors { /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ /* s5: single color pulse on inhibited power-up */ uint8_t s5_idx; /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ -}; + struct rgb_s color[8]; /* 0-3 are Google colors */ +} __ec_todo_packed; + +struct lightbar_params_v3 { + /* + * Number of LEDs reported by the EC. + * May be less than the actual number of LEDs in the lightbar. + */ + uint8_t reported_led_num; +} __ec_todo_packed; -/* Lightbyte program. */ +/* Lightbar program. */ #define EC_LB_PROG_LEN 192 -struct __ec_todo_unpacked lightbar_program { +struct lightbar_program { uint8_t size; uint8_t data[EC_LB_PROG_LEN]; -}; +} __ec_todo_unpacked; + +/* + * Lightbar program for large sequences. Sequences are sent in pieces, with + * increasing offset. The sequences are still limited by the amount reserved in + * EC RAM. + */ +struct lightbar_program_ex { + uint8_t size; + uint16_t offset; + uint8_t data[0]; +} __ec_todo_packed; -struct __ec_todo_packed ec_params_lightbar { - uint8_t cmd; /* Command (see enum lightbar_command) */ +struct ec_params_lightbar { + uint8_t cmd; /* Command (see enum lightbar_command) */ union { - struct __ec_todo_unpacked { - /* no args */ - } dump, off, on, init, get_seq, get_params_v0, get_params_v1, - version, get_brightness, get_demo, suspend, resume, - get_params_v2_timing, get_params_v2_tap, - get_params_v2_osc, get_params_v2_bright, - get_params_v2_thlds, get_params_v2_colors; + /* + * The following commands have no args: + * + * dump, off, on, init, get_seq, get_params_v0, get_params_v1, + * version, get_brightness, get_demo, suspend, resume, + * get_params_v2_timing, get_params_v2_tap, get_params_v2_osc, + * get_params_v2_bright, get_params_v2_thlds, + * get_params_v2_colors + * + * Don't use an empty struct, because C++ hates that. + */ struct __ec_todo_unpacked { uint8_t num; @@ -1776,10 +2621,11 @@ struct __ec_todo_packed ec_params_lightbar { struct lightbar_params_v2_colors set_v2par_colors; struct lightbar_program set_program; + struct lightbar_program_ex set_program_ex; }; -}; +} __ec_todo_packed; -struct __ec_todo_packed ec_response_lightbar { +struct ec_response_lightbar { union { struct __ec_todo_unpacked { struct __ec_todo_unpacked { @@ -1803,6 +2649,8 @@ struct __ec_todo_packed ec_response_lightbar { struct lightbar_params_v2_thresholds get_params_v2_thlds; struct lightbar_params_v2_colors get_params_v2_colors; + struct lightbar_params_v3 get_params_v3; + struct __ec_todo_unpacked { uint32_t num; uint32_t flags; @@ -1812,16 +2660,17 @@ struct __ec_todo_packed ec_response_lightbar { uint8_t red, green, blue; } get_rgb; - struct __ec_todo_unpacked { - /* no return params */ - } off, on, init, set_brightness, seq, reg, set_rgb, - demo, set_params_v0, set_params_v1, - set_program, manual_suspend_ctrl, suspend, resume, - set_v2par_timing, set_v2par_tap, - set_v2par_osc, set_v2par_bright, set_v2par_thlds, - set_v2par_colors; + /* + * The following commands have no response: + * + * off, on, init, set_brightness, seq, reg, set_rgb, demo, + * set_params_v0, set_params_v1, set_program, + * manual_suspend_ctrl, suspend, resume, set_v2par_timing, + * set_v2par_tap, set_v2par_osc, set_v2par_bright, + * set_v2par_thlds, set_v2par_colors + */ }; -}; +} __ec_todo_packed; /* Lightbar commands */ enum lightbar_command { @@ -1859,7 +2708,9 @@ enum lightbar_command { LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31, LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32, LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33, - LIGHTBAR_NUM_CMDS + LIGHTBAR_CMD_GET_PARAMS_V3 = 34, + LIGHTBAR_CMD_SET_PROGRAM_EX = 35, + LIGHTBAR_NUM_CMDS, }; /*****************************************************************************/ @@ -1885,33 +2736,37 @@ enum ec_led_id { EC_LED_ID_RECOVERY_HW_REINIT_LED, /* LED to indicate sysrq debug mode. */ EC_LED_ID_SYSRQ_DEBUG_LED, + /* LED strip for advanced patterns. */ + EC_LED_ID_LIGHTBAR_LED, - EC_LED_ID_COUNT + EC_LED_ID_COUNT, }; /* LED control flags */ -#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */ -#define EC_LED_FLAGS_AUTO (1 << 1) /* Switch LED back to automatic control */ +#define EC_LED_FLAGS_QUERY BIT(0) /* Query LED capability only */ +#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */ enum ec_led_colors { + EC_LED_COLOR_INVALID = -1, EC_LED_COLOR_RED = 0, EC_LED_COLOR_GREEN, EC_LED_COLOR_BLUE, EC_LED_COLOR_YELLOW, EC_LED_COLOR_WHITE, EC_LED_COLOR_AMBER, + EC_LED_COLOR_MAGENTA, - EC_LED_COLOR_COUNT + EC_LED_COLOR_COUNT, }; -struct __ec_align1 ec_params_led_control { - uint8_t led_id; /* Which LED to control */ - uint8_t flags; /* Control flags */ +struct ec_params_led_control { + uint8_t led_id; /* Which LED to control */ + uint8_t flags; /* Control flags */ uint8_t brightness[EC_LED_COLOR_COUNT]; -}; +} __ec_align1; -struct __ec_align1 ec_response_led_control { +struct ec_response_led_control { /* * Available brightness value range. * @@ -1920,7 +2775,7 @@ struct __ec_align1 ec_response_led_control { * Other values means the LED is control by PWM. */ uint8_t brightness_range[EC_LED_COLOR_COUNT]; -}; +} __ec_align1; /*****************************************************************************/ /* Verified boot commands */ @@ -1933,31 +2788,31 @@ struct __ec_align1 ec_response_led_control { /* Verified boot hash command */ #define EC_CMD_VBOOT_HASH 0x002A -struct __ec_align4 ec_params_vboot_hash { - uint8_t cmd; /* enum ec_vboot_hash_cmd */ - uint8_t hash_type; /* enum ec_vboot_hash_type */ - uint8_t nonce_size; /* Nonce size; may be 0 */ - uint8_t reserved0; /* Reserved; set 0 */ - uint32_t offset; /* Offset in flash to hash */ - uint32_t size; /* Number of bytes to hash */ - uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */ -}; - -struct __ec_align4 ec_response_vboot_hash { - uint8_t status; /* enum ec_vboot_hash_status */ - uint8_t hash_type; /* enum ec_vboot_hash_type */ - uint8_t digest_size; /* Size of hash digest in bytes */ - uint8_t reserved0; /* Ignore; will be 0 */ - uint32_t offset; /* Offset in flash which was hashed */ - uint32_t size; /* Number of bytes hashed */ +struct ec_params_vboot_hash { + uint8_t cmd; /* enum ec_vboot_hash_cmd */ + uint8_t hash_type; /* enum ec_vboot_hash_type */ + uint8_t nonce_size; /* Nonce size; may be 0 */ + uint8_t reserved0; /* Reserved; set 0 */ + uint32_t offset; /* Offset in flash to hash */ + uint32_t size; /* Number of bytes to hash */ + uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */ +} __ec_align4; + +struct ec_response_vboot_hash { + uint8_t status; /* enum ec_vboot_hash_status */ + uint8_t hash_type; /* enum ec_vboot_hash_type */ + uint8_t digest_size; /* Size of hash digest in bytes */ + uint8_t reserved0; /* Ignore; will be 0 */ + uint32_t offset; /* Offset in flash which was hashed */ + uint32_t size; /* Number of bytes hashed */ uint8_t hash_digest[64]; /* Hash digest data */ -}; +} __ec_align4; enum ec_vboot_hash_cmd { - EC_VBOOT_HASH_GET = 0, /* Get current hash status */ - EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */ - EC_VBOOT_HASH_START = 2, /* Start computing a new hash */ - EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */ + EC_VBOOT_HASH_GET = 0, /* Get current hash status */ + EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */ + EC_VBOOT_HASH_START = 2, /* Start computing a new hash */ + EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */ }; enum ec_vboot_hash_type { @@ -1975,9 +2830,15 @@ enum ec_vboot_hash_status { * If one of these is specified, the EC will automatically update offset and * size to the correct values for the specified image (RO or RW). */ -#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe -#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd -#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc +#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe +#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd +#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc + +/* + * 'RW' is vague if there are multiple RW images; we mean the active one, + * so the old constant is deprecated. + */ +#define EC_VBOOT_HASH_OFFSET_RW EC_VBOOT_HASH_OFFSET_ACTIVE /*****************************************************************************/ /* @@ -2063,7 +2924,7 @@ enum motionsense_command { /* * Sensor Offset command is a setter/getter command for the offset - * used for calibration. + * used for factory calibration. * The offsets can be calculated by the host, or via * PERFORM_CALIB command. */ @@ -2099,8 +2960,28 @@ enum motionsense_command { */ MOTIONSENSE_CMD_SPOOF = 16, + /* Set lid angle for tablet mode detection. */ + MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE = 17, + + /* + * Sensor Scale command is a setter/getter command for the calibration + * scale. + */ + MOTIONSENSE_CMD_SENSOR_SCALE = 18, + + /* + * Read the current online calibration values (if available). + */ + MOTIONSENSE_CMD_ONLINE_CALIB_READ = 19, + + /* + * Activity management + * Retrieve current status of given activity. + */ + MOTIONSENSE_CMD_GET_ACTIVITY = 20, + /* Number of motionsense sub-commands. */ - MOTIONSENSE_NUM_CMDS + MOTIONSENSE_NUM_CMDS, }; /* List of motion sensor types. */ @@ -2112,6 +2993,8 @@ enum motionsensor_type { MOTIONSENSE_TYPE_LIGHT = 4, MOTIONSENSE_TYPE_ACTIVITY = 5, MOTIONSENSE_TYPE_BARO = 6, + MOTIONSENSE_TYPE_SYNC = 7, + MOTIONSENSE_TYPE_LIGHT_RGB = 8, MOTIONSENSE_TYPE_MAX, }; @@ -2119,6 +3002,7 @@ enum motionsensor_type { enum motionsensor_location { MOTIONSENSE_LOC_BASE = 0, MOTIONSENSE_LOC_LID = 1, + MOTIONSENSE_LOC_CAMERA = 2, MOTIONSENSE_LOC_MAX, }; @@ -2135,76 +3019,127 @@ enum motionsensor_chip { MOTIONSENSE_CHIP_BMA255 = 8, MOTIONSENSE_CHIP_BMP280 = 9, MOTIONSENSE_CHIP_OPT3001 = 10, -}; + MOTIONSENSE_CHIP_BH1730 = 11, + MOTIONSENSE_CHIP_GPIO = 12, + MOTIONSENSE_CHIP_LIS2DH = 13, + MOTIONSENSE_CHIP_LSM6DSM = 14, + MOTIONSENSE_CHIP_LIS2DE = 15, + MOTIONSENSE_CHIP_LIS2MDL = 16, + MOTIONSENSE_CHIP_LSM6DS3 = 17, + MOTIONSENSE_CHIP_LSM6DSO = 18, + MOTIONSENSE_CHIP_LNG2DM = 19, + MOTIONSENSE_CHIP_TCS3400 = 20, + MOTIONSENSE_CHIP_LIS2DW12 = 21, + MOTIONSENSE_CHIP_LIS2DWL = 22, + MOTIONSENSE_CHIP_LIS2DS = 23, + MOTIONSENSE_CHIP_BMI260 = 24, + MOTIONSENSE_CHIP_ICM426XX = 25, + MOTIONSENSE_CHIP_ICM42607 = 26, + MOTIONSENSE_CHIP_BMA422 = 27, + MOTIONSENSE_CHIP_BMI323 = 28, + MOTIONSENSE_CHIP_BMI220 = 29, + MOTIONSENSE_CHIP_CM32183 = 30, + MOTIONSENSE_CHIP_VEML3328 = 31, + MOTIONSENSE_CHIP_CM36781 = 32, + MOTIONSENSE_CHIP_MAX, +}; + +/* List of orientation positions */ +enum motionsensor_orientation { + MOTIONSENSE_ORIENTATION_LANDSCAPE = 0, + MOTIONSENSE_ORIENTATION_PORTRAIT = 1, + MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_PORTRAIT = 2, + MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE = 3, + MOTIONSENSE_ORIENTATION_UNKNOWN = 4, +}; + +struct ec_response_activity_data { + uint8_t activity; /* motionsensor_activity */ + uint8_t state; +} __ec_todo_packed; -struct __ec_todo_packed ec_response_motion_sensor_data { +struct ec_response_motion_sensor_data { /* Flags for each sensor. */ uint8_t flags; - /* sensor number the data comes from */ + /* Sensor number the data comes from. */ uint8_t sensor_num; /* Each sensor is up to 3-axis. */ union { - int16_t data[3]; + int16_t data[3]; + /* for sensors using unsigned data */ + uint16_t udata[3]; struct __ec_todo_packed { - uint16_t reserved; - uint32_t timestamp; + uint16_t reserved; + uint32_t timestamp; }; struct __ec_todo_unpacked { - uint8_t activity; /* motionsensor_activity */ - uint8_t state; - int16_t add_info[2]; + struct ec_response_activity_data activity_data; + int16_t add_info[2]; }; }; +} __ec_todo_packed; + +/* Response to AP reporting calibration data for a given sensor. */ +struct ec_response_online_calibration_data { + /** The calibration values. */ + int16_t data[3]; }; /* Note: used in ec_response_get_next_data */ -struct __ec_todo_packed ec_response_motion_sense_fifo_info { +struct ec_response_motion_sense_fifo_info { /* Size of the fifo */ uint16_t size; /* Amount of space used in the fifo */ uint16_t count; - /* Timestamp recorded in us */ + /* Timestamp recorded in us. + * aka accurate timestamp when host event was triggered. + */ uint32_t timestamp; /* Total amount of vector lost */ uint16_t total_lost; /* Lost events since the last fifo_info, per sensors */ uint16_t lost[0]; -}; +} __ec_todo_packed; -struct __ec_todo_packed ec_response_motion_sense_fifo_data { +struct ec_response_motion_sense_fifo_data { uint32_t number_data; struct ec_response_motion_sensor_data data[0]; -}; +} __ec_todo_packed; /* List supported activity recognition */ enum motionsensor_activity { MOTIONSENSE_ACTIVITY_RESERVED = 0, MOTIONSENSE_ACTIVITY_SIG_MOTION = 1, MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2, + MOTIONSENSE_ACTIVITY_ORIENTATION = 3, + MOTIONSENSE_ACTIVITY_BODY_DETECTION = 4, }; -struct __ec_todo_unpacked ec_motion_sense_activity { +struct ec_motion_sense_activity { uint8_t sensor_num; uint8_t activity; /* one of enum motionsensor_activity */ - uint8_t enable; /* 1: enable, 0: disable */ + uint8_t enable; /* 1: enable, 0: disable */ uint8_t reserved; - uint16_t parameters[3]; /* activity dependent parameters */ -}; + uint16_t parameters[4]; /* activity dependent parameters */ +} __ec_todo_packed; /* Module flag masks used for the dump sub-command. */ -#define MOTIONSENSE_MODULE_FLAG_ACTIVE (1<<0) +#define MOTIONSENSE_MODULE_FLAG_ACTIVE BIT(0) /* Sensor flag masks used for the dump sub-command. */ -#define MOTIONSENSE_SENSOR_FLAG_PRESENT (1<<0) +#define MOTIONSENSE_SENSOR_FLAG_PRESENT BIT(0) /* * Flush entry for synchronization. * data contains time stamp */ -#define MOTIONSENSE_SENSOR_FLAG_FLUSH (1<<0) -#define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP (1<<1) -#define MOTIONSENSE_SENSOR_FLAG_WAKEUP (1<<2) -#define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE (1<<3) +#define MOTIONSENSE_SENSOR_FLAG_FLUSH BIT(0) +#define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP BIT(1) +#define MOTIONSENSE_SENSOR_FLAG_WAKEUP BIT(2) +#define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE BIT(3) +#define MOTIONSENSE_SENSOR_FLAG_ODR BIT(4) + +#define MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO BIT(7) /* * Send this value for the data element to only perform a read. If you @@ -2213,11 +3148,14 @@ struct __ec_todo_unpacked ec_motion_sense_activity { */ #define EC_MOTION_SENSE_NO_VALUE -1 -#define EC_MOTION_SENSE_INVALID_CALIB_TEMP 0x8000 +#define EC_MOTION_SENSE_INVALID_CALIB_TEMP INT16_MIN /* MOTIONSENSE_CMD_SENSOR_OFFSET subcommand flag */ /* Set Calibration information */ -#define MOTION_SENSE_SET_OFFSET 1 +#define MOTION_SENSE_SET_OFFSET BIT(0) + +/* Default Scale value, factor 1. */ +#define MOTION_SENSE_DEFAULT_SCALE BIT(15) #define LID_ANGLE_UNRELIABLE 500 @@ -2235,10 +3173,10 @@ enum motionsense_spoof_mode { MOTIONSENSE_SPOOF_MODE_QUERY, }; -struct __ec_todo_packed ec_params_motion_sense { +struct ec_params_motion_sense { uint8_t cmd; union { - /* Used for MOTIONSENSE_CMD_DUMP */ + /* Used for MOTIONSENSE_CMD_DUMP. */ struct __ec_todo_unpacked { /* * Maximal number of sensor the host is expecting. @@ -2253,17 +3191,26 @@ struct __ec_todo_packed ec_params_motion_sense { */ struct __ec_todo_unpacked { /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. - * kb_wake_angle: angle to wakup AP. + * kb_wake_angle: angle to wakeup AP. */ int16_t data; } kb_wake_angle; - /* Used for MOTIONSENSE_CMD_INFO, MOTIONSENSE_CMD_DATA - * and MOTIONSENSE_CMD_PERFORM_CALIB. */ + /* + * Used for MOTIONSENSE_CMD_INFO, MOTIONSENSE_CMD_DATA + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + } info, info_3, info_4, data, fifo_flush, list_activities; + + /* + * Used for MOTIONSENSE_CMD_PERFORM_CALIB: + * Allow entering/exiting the calibration mode. + */ struct __ec_todo_unpacked { uint8_t sensor_num; - } info, info_3, data, fifo_flush, perform_calib, - list_activities; + uint8_t enable; + } perform_calib; /* * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR @@ -2310,24 +3257,52 @@ struct __ec_todo_packed ec_params_motion_sense { int16_t offset[3]; } sensor_offset; - /* Used for MOTIONSENSE_CMD_FIFO_INFO */ - struct __ec_todo_unpacked { - } fifo_info; + /* Used for MOTIONSENSE_CMD_SENSOR_SCALE */ + struct __ec_todo_packed { + uint8_t sensor_num; - /* Used for MOTIONSENSE_CMD_FIFO_READ */ - struct __ec_todo_unpacked { /* - * Number of expected vector to return. - * EC may return less or 0 if none available. - */ + * bit 0: If set (MOTION_SENSE_SET_OFFSET), set + * the calibration information in the EC. + * If unset, just retrieve calibration information. + */ + uint16_t flags; + + /* + * Temperature at calibration, in units of 0.01 C + * 0x8000: invalid / unknown. + * 0x0: 0C + * 0x7fff: +327.67C + */ + int16_t temp; + + /* + * Scale for calibration: + * By default scale is 1, it is encoded on 16bits: + * 1 = BIT(15) + * ~2 = 0xFFFF + * ~0 = 0. + */ + uint16_t scale[3]; + } sensor_scale; + + /* Used for MOTIONSENSE_CMD_FIFO_INFO */ + /* (no params) */ + + /* Used for MOTIONSENSE_CMD_FIFO_READ */ + struct __ec_todo_unpacked { + /* + * Number of expected vector to return. + * EC may return less or 0 if none available. + */ uint32_t max_data_vector; } fifo_read; + /* Used for MOTIONSENSE_CMD_SET_ACTIVITY */ struct ec_motion_sense_activity set_activity; /* Used for MOTIONSENSE_CMD_LID_ANGLE */ - struct __ec_todo_unpacked { - } lid_angle; + /* (no params) */ /* Used for MOTIONSENSE_CMD_FIFO_INT_ENABLE */ struct __ec_todo_unpacked { @@ -2348,24 +3323,74 @@ struct __ec_todo_packed ec_params_motion_sense { /* Ignored, used for alignment. */ uint8_t reserved; - /* Individual component values to spoof. */ - int16_t components[3]; + union { + /* Individual component values to spoof. */ + int16_t components[3]; + + /* Used when spoofing an activity */ + struct { + /* enum motionsensor_activity */ + uint8_t activity_num; + + /* spoof activity state */ + uint8_t activity_state; + }; + } __ec_todo_packed; } spoof; - }; + + /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ + struct __ec_todo_unpacked { + /* + * Lid angle threshold for switching between tablet and + * clamshell mode. + */ + int16_t lid_angle; + + /* + * Hysteresis degree to prevent fluctuations between + * clamshell and tablet mode if lid angle keeps + * changing around the threshold. Lid motion driver will + * use lid_angle + hys_degree to trigger tablet mode and + * lid_angle - hys_degree to trigger clamshell mode. + */ + int16_t hys_degree; + } tablet_mode_threshold; + + /* + * Used for MOTIONSENSE_CMD_ONLINE_CALIB_READ: + * Allow reading a single sensor's online calibration value. + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + } online_calib_read; + + /* + * Used for MOTIONSENSE_CMD_GET_ACTIVITY. + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + uint8_t activity; /* enum motionsensor_activity */ + } get_activity; + } __ec_todo_packed; +} __ec_todo_packed; + +enum motion_sense_cmd_info_flags { + /* The sensor supports online calibration */ + MOTION_SENSE_CMD_INFO_FLAG_ONLINE_CALIB = BIT(0), }; -struct __ec_todo_packed ec_response_motion_sense { +struct ec_response_motion_sense { union { /* Used for MOTIONSENSE_CMD_DUMP */ struct __ec_todo_unpacked { /* Flags representing the motion sensor module. */ uint8_t module_flags; - /* Number of sensors managed directly by the EC */ + /* Number of sensors managed directly by the EC. */ uint8_t sensor_count; /* - * sensor data is truncated if response_max is too small + * Sensor data is truncated if response_max is too small * for holding all the data. */ struct ec_response_motion_sensor_data sensor[0]; @@ -2404,6 +3429,33 @@ struct __ec_todo_packed ec_response_motion_sense { uint32_t fifo_max_event_count; } info_3; + /* Used for MOTIONSENSE_CMD_INFO version 4 */ + struct __ec_align4 { + /* Should be element of enum motionsensor_type. */ + uint8_t type; + + /* Should be element of enum motionsensor_location. */ + uint8_t location; + + /* Should be element of enum motionsensor_chip. */ + uint8_t chip; + + /* Minimum sensor sampling frequency */ + uint32_t min_frequency; + + /* Maximum sensor sampling frequency */ + uint32_t max_frequency; + + /* Max number of sensor events that could be in fifo */ + uint32_t fifo_max_event_count; + + /* + * Should be elements of + * enum motion_sense_cmd_info_flags + */ + uint32_t flags; + } info_4; + /* Used for MOTIONSENSE_CMD_DATA */ struct ec_response_motion_sensor_data data; @@ -2418,26 +3470,36 @@ struct __ec_todo_packed ec_response_motion_sense { /* Current value of the parameter queried. */ int32_t ret; } ec_rate, sensor_odr, sensor_range, kb_wake_angle, - fifo_int_enable, spoof; + fifo_int_enable, spoof; - /* Used for MOTIONSENSE_CMD_SENSOR_OFFSET */ - struct __ec_todo_unpacked { + /* + * Used for MOTIONSENSE_CMD_SENSOR_OFFSET, + * PERFORM_CALIB. + */ + struct __ec_todo_unpacked { int16_t temp; int16_t offset[3]; } sensor_offset, perform_calib; + /* Used for MOTIONSENSE_CMD_SENSOR_SCALE */ + struct __ec_todo_unpacked { + int16_t temp; + uint16_t scale[3]; + } sensor_scale; + struct ec_response_motion_sense_fifo_info fifo_info, fifo_flush; struct ec_response_motion_sense_fifo_data fifo_read; + struct ec_response_online_calibration_data online_calib_read; + struct __ec_todo_packed { uint16_t reserved; uint32_t enabled; uint32_t disabled; } list_activities; - struct __ec_todo_unpacked { - } set_activity; + /* No params for set activity */ /* Used for MOTIONSENSE_CMD_LID_ANGLE */ struct __ec_todo_unpacked { @@ -2447,8 +3509,25 @@ struct __ec_todo_packed ec_response_motion_sense { */ uint16_t value; } lid_angle; + + /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ + struct __ec_todo_unpacked { + /* + * Lid angle threshold for switching between tablet and + * clamshell mode. + */ + uint16_t lid_angle; + + /* Hysteresis degree. */ + uint16_t hys_degree; + } tablet_mode_threshold; + + /* USED for MOTIONSENSE_CMD_GET_ACTIVITY. */ + struct __ec_todo_unpacked { + uint8_t state; + } get_activity; }; -}; +} __ec_todo_packed; /*****************************************************************************/ /* Force lid open command */ @@ -2456,9 +3535,9 @@ struct __ec_todo_packed ec_response_motion_sense { /* Make lid event always open */ #define EC_CMD_FORCE_LID_OPEN 0x002C -struct __ec_align1 ec_params_force_lid_open { +struct ec_params_force_lid_open { uint8_t enabled; -}; +} __ec_align1; /*****************************************************************************/ /* Configure the behavior of the power button */ @@ -2466,13 +3545,13 @@ struct __ec_align1 ec_params_force_lid_open { enum ec_config_power_button_flags { /* Enable/Disable power button pulses for x86 devices */ - EC_POWER_BUTTON_ENABLE_PULSE = (1 << 0), + EC_POWER_BUTTON_ENABLE_PULSE = BIT(0), }; -struct __ec_align1 ec_params_config_power_button { +struct ec_params_config_power_button { /* See enum ec_config_power_button_flags */ uint8_t flags; -}; +} __ec_align1; /*****************************************************************************/ /* USB charging control commands */ @@ -2480,11 +3559,52 @@ struct __ec_align1 ec_params_config_power_button { /* Set USB port charging mode */ #define EC_CMD_USB_CHARGE_SET_MODE 0x0030 -struct __ec_align1 ec_params_usb_charge_set_mode { +enum usb_charge_mode { + /* Disable USB port. */ + USB_CHARGE_MODE_DISABLED, + /* Set USB port to Standard Downstream Port, USB 2.0 mode. */ + USB_CHARGE_MODE_SDP2, + /* Set USB port to Charging Downstream Port, BC 1.2. */ + USB_CHARGE_MODE_CDP, + /* Set USB port to Dedicated Charging Port, BC 1.2. */ + USB_CHARGE_MODE_DCP_SHORT, + /* Enable USB port (for dumb ports). */ + USB_CHARGE_MODE_ENABLED, + /* Set USB port to CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE. */ + USB_CHARGE_MODE_DEFAULT, + + USB_CHARGE_MODE_COUNT, +}; + +enum usb_suspend_charge { + /* Enable charging in suspend */ + USB_ALLOW_SUSPEND_CHARGE, + /* Disable charging in suspend */ + USB_DISALLOW_SUSPEND_CHARGE, +}; + +struct ec_params_usb_charge_set_mode { uint8_t usb_port_id; - uint8_t mode; + uint8_t mode : 7; /* enum usb_charge_mode */ + uint8_t inhibit_charge : 1; /* enum usb_suspend_charge */ +} __ec_align1; + +/*****************************************************************************/ +/* Tablet mode commands */ + +/* Set tablet mode */ +#define EC_CMD_SET_TABLET_MODE 0x0031 + +enum tablet_mode_override { + TABLET_MODE_DEFAULT, + TABLET_MODE_FORCE_TABLET, + TABLET_MODE_FORCE_CLAMSHELL, }; +struct ec_params_set_tablet_mode { + uint8_t tablet_mode; /* enum tablet_mode_override */ +} __ec_align1; + /*****************************************************************************/ /* Persistent storage for host */ @@ -2494,12 +3614,12 @@ struct __ec_align1 ec_params_usb_charge_set_mode { /* Get persistent storage info */ #define EC_CMD_PSTORE_INFO 0x0040 -struct __ec_align4 ec_response_pstore_info { +struct ec_response_pstore_info { /* Persistent storage size, in bytes */ uint32_t pstore_size; /* Access size; read/write offset and size must be a multiple of this */ uint32_t access_size; -}; +} __ec_align4; /* * Read persistent storage @@ -2508,31 +3628,31 @@ struct __ec_align4 ec_response_pstore_info { */ #define EC_CMD_PSTORE_READ 0x0041 -struct __ec_align4 ec_params_pstore_read { - uint32_t offset; /* Byte offset to read */ - uint32_t size; /* Size to read in bytes */ -}; +struct ec_params_pstore_read { + uint32_t offset; /* Byte offset to read */ + uint32_t size; /* Size to read in bytes */ +} __ec_align4; /* Write persistent storage */ #define EC_CMD_PSTORE_WRITE 0x0042 -struct __ec_align4 ec_params_pstore_write { - uint32_t offset; /* Byte offset to write */ - uint32_t size; /* Size to write in bytes */ +struct ec_params_pstore_write { + uint32_t offset; /* Byte offset to write */ + uint32_t size; /* Size to write in bytes */ uint8_t data[EC_PSTORE_SIZE_MAX]; -}; +} __ec_align4; /*****************************************************************************/ /* Real-time clock */ /* RTC params and response structures */ -struct __ec_align4 ec_params_rtc { +struct ec_params_rtc { uint32_t time; -}; +} __ec_align4; -struct __ec_align4 ec_response_rtc { +struct ec_response_rtc { uint32_t time; -}; +} __ec_align4; /* These use ec_response_rtc */ #define EC_CMD_RTC_GET_VALUE 0x0044 @@ -2560,17 +3680,17 @@ enum ec_port80_subcmd { EC_PORT80_READ_BUFFER, }; -struct __ec_todo_packed ec_params_port80_read { +struct ec_params_port80_read { uint16_t subcmd; union { struct __ec_todo_unpacked { uint32_t offset; uint32_t num_entries; } read_buffer; - }; -}; + } __ec_todo_packed; +} __ec_todo_packed; -struct __ec_todo_packed ec_response_port80_read { +struct ec_response_port80_read { union { struct __ec_todo_unpacked { uint32_t writes; @@ -2581,11 +3701,11 @@ struct __ec_todo_packed ec_response_port80_read { uint16_t codes[EC_PORT80_SIZE_MAX]; } data; }; -}; +} __ec_todo_packed; -struct __ec_align2 ec_response_port80_last_boot { +struct ec_response_port80_last_boot { uint16_t code; -}; +} __ec_align2; /*****************************************************************************/ /* Temporary secure storage for host verified boot use */ @@ -2598,12 +3718,12 @@ struct __ec_align2 ec_response_port80_last_boot { /* Get persistent storage info */ #define EC_CMD_VSTORE_INFO 0x0049 -struct __ec_align_size1 ec_response_vstore_info { +struct ec_response_vstore_info { /* Indicates which slots are locked */ uint32_t slot_locked; /* Total number of slots available */ uint8_t slot_count; -}; +} __ec_align_size1; /* * Read temporary secure storage @@ -2612,23 +3732,23 @@ struct __ec_align_size1 ec_response_vstore_info { */ #define EC_CMD_VSTORE_READ 0x004A -struct __ec_align1 ec_params_vstore_read { +struct ec_params_vstore_read { uint8_t slot; /* Slot to read from */ -}; +} __ec_align1; -struct __ec_align1 ec_response_vstore_read { +struct ec_response_vstore_read { uint8_t data[EC_VSTORE_SLOT_SIZE]; -}; +} __ec_align1; /* * Write temporary secure storage and lock it. */ #define EC_CMD_VSTORE_WRITE 0x004B -struct __ec_align1 ec_params_vstore_write { +struct ec_params_vstore_write { uint8_t slot; /* Slot to write to */ uint8_t data[EC_VSTORE_SLOT_SIZE]; -}; +} __ec_align1; /*****************************************************************************/ /* Thermal engine commands. Note that there are two implementations. We'll @@ -2645,21 +3765,21 @@ struct __ec_align1 ec_params_vstore_write { */ /* Version 0 - set */ -struct __ec_align2 ec_params_thermal_set_threshold { +struct ec_params_thermal_set_threshold { uint8_t sensor_type; uint8_t threshold_id; uint16_t value; -}; +} __ec_align2; /* Version 0 - get */ -struct __ec_align1 ec_params_thermal_get_threshold { +struct ec_params_thermal_get_threshold { uint8_t sensor_type; uint8_t threshold_id; -}; +} __ec_align1; -struct __ec_align2 ec_response_thermal_get_threshold { +struct ec_response_thermal_get_threshold { uint16_t value; -}; +} __ec_align2; /* The version 1 structs are visible. */ enum ec_temp_thresholds { @@ -2667,45 +3787,80 @@ enum ec_temp_thresholds { EC_TEMP_THRESH_HIGH, EC_TEMP_THRESH_HALT, - EC_TEMP_THRESH_COUNT + EC_TEMP_THRESH_COUNT, }; /* * Thermal configuration for one temperature sensor. Temps are in degrees K. * Zero values will be silently ignored by the thermal task. * + * Set 'temp_host' value allows thermal task to trigger some event with 1 degree + * hysteresis. + * For example, + * temp_host[EC_TEMP_THRESH_HIGH] = 300 K + * temp_host_release[EC_TEMP_THRESH_HIGH] = 0 K + * EC will throttle ap when temperature >= 301 K, and release throttling when + * temperature <= 299 K. + * + * Set 'temp_host_release' value allows thermal task has a custom hysteresis. + * For example, + * temp_host[EC_TEMP_THRESH_HIGH] = 300 K + * temp_host_release[EC_TEMP_THRESH_HIGH] = 295 K + * EC will throttle ap when temperature >= 301 K, and release throttling when + * temperature <= 294 K. + * * Note that this structure is a sub-structure of * ec_params_thermal_set_threshold_v1, but maintains its alignment there. */ -struct __ec_align4 ec_thermal_config { +struct ec_thermal_config { uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */ - uint32_t temp_fan_off; /* no active cooling needed */ - uint32_t temp_fan_max; /* max active cooling needed */ -}; + uint32_t temp_host_release[EC_TEMP_THRESH_COUNT]; /* release levels */ + uint32_t temp_fan_off; /* no active cooling needed */ + uint32_t temp_fan_max; /* max active cooling needed */ +} __ec_align4; /* Version 1 - get config for one sensor. */ -struct __ec_align4 ec_params_thermal_get_threshold_v1 { +struct ec_params_thermal_get_threshold_v1 { uint32_t sensor_num; -}; +} __ec_align4; /* This returns a struct ec_thermal_config */ -/* Version 1 - set config for one sensor. - * Use read-modify-write for best results! */ -struct __ec_align4 ec_params_thermal_set_threshold_v1 { +/* + * Version 1 - set config for one sensor. + * Use read-modify-write for best results! + */ +struct ec_params_thermal_set_threshold_v1 { uint32_t sensor_num; struct ec_thermal_config cfg; -}; +} __ec_align4; /* This returns no data */ /****************************************************************************/ -/* Toggle automatic fan control */ +/* Set or get fan control mode */ #define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x0052 +enum ec_auto_fan_ctrl_cmd { + EC_AUTO_FAN_CONTROL_CMD_SET = 0, + EC_AUTO_FAN_CONTROL_CMD_GET, +}; + /* Version 1 of input params */ -struct __ec_align1 ec_params_auto_fan_ctrl_v1 { +struct ec_params_auto_fan_ctrl_v1 { uint8_t fan_idx; -}; +} __ec_align1; + +/* Version 2 of input params */ +struct ec_params_auto_fan_ctrl_v2 { + uint8_t fan_idx; + uint8_t cmd; /* enum ec_auto_fan_ctrl_cmd */ + uint8_t set_auto; /* only used with EC_AUTO_FAN_CONTROL_CMD_SET - bool + */ +} __ec_align4; + +struct ec_response_auto_fan_control { + uint8_t is_auto; /* bool */ +} __ec_align1; /* Get/Set TMP006 calibration data */ #define EC_CMD_TMP006_GET_CALIBRATION 0x0053 @@ -2721,54 +3876,54 @@ struct __ec_align1 ec_params_auto_fan_ctrl_v1 { */ /* This is the same struct for both v0 and v1. */ -struct __ec_align1 ec_params_tmp006_get_calibration { +struct ec_params_tmp006_get_calibration { uint8_t index; -}; +} __ec_align1; /* Version 0 */ -struct __ec_align4 ec_response_tmp006_get_calibration_v0 { +struct ec_response_tmp006_get_calibration_v0 { float s0; float b0; float b1; float b2; -}; +} __ec_align4; -struct __ec_align4 ec_params_tmp006_set_calibration_v0 { +struct ec_params_tmp006_set_calibration_v0 { uint8_t index; uint8_t reserved[3]; float s0; float b0; float b1; float b2; -}; +} __ec_align4; /* Version 1 */ -struct __ec_align4 ec_response_tmp006_get_calibration_v1 { +struct ec_response_tmp006_get_calibration_v1 { uint8_t algorithm; uint8_t num_params; uint8_t reserved[2]; - float val[0]; -}; + float val[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; -struct __ec_align4 ec_params_tmp006_set_calibration_v1 { +struct ec_params_tmp006_set_calibration_v1 { uint8_t index; uint8_t algorithm; uint8_t num_params; uint8_t reserved; - float val[0]; -}; + float val[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; /* Read raw TMP006 data */ #define EC_CMD_TMP006_GET_RAW 0x0055 -struct __ec_align1 ec_params_tmp006_get_raw { +struct ec_params_tmp006_get_raw { uint8_t index; -}; +} __ec_align1; -struct __ec_align4 ec_response_tmp006_get_raw { - int32_t t; /* In 1/100 K */ - int32_t v; /* In nV */ -}; +struct ec_response_tmp006_get_raw { + int32_t t; /* In 1/100 K */ + int32_t v; /* In nV */ +} __ec_align4; /*****************************************************************************/ /* MKBP - Matrix KeyBoard Protocol */ @@ -2790,17 +3945,17 @@ struct __ec_align4 ec_response_tmp006_get_raw { */ #define EC_CMD_MKBP_INFO 0x0061 -struct __ec_align_size1 ec_response_mkbp_info { +struct ec_response_mkbp_info { uint32_t rows; uint32_t cols; /* Formerly "switches", which was 0. */ uint8_t reserved; -}; +} __ec_align_size1; -struct __ec_align1 ec_params_mkbp_info { +struct ec_params_mkbp_info { uint8_t info_type; uint8_t event_type; -}; +} __ec_align1; enum ec_mkbp_info_type { /* @@ -2844,11 +3999,11 @@ enum ec_mkbp_info_type { /* Simulate key press */ #define EC_CMD_MKBP_SIMULATE_KEY 0x0062 -struct __ec_align1 ec_params_mkbp_simulate_key { +struct ec_params_mkbp_simulate_key { uint8_t col; uint8_t row; uint8_t pressed; -}; +} __ec_align1; /* Configure keyboard scanning */ #define EC_CMD_MKBP_SET_CONFIG 0x0064 @@ -2856,17 +4011,17 @@ struct __ec_align1 ec_params_mkbp_simulate_key { /* flags */ enum mkbp_config_flags { - EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ + EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ }; enum mkbp_config_valid { - EC_MKBP_VALID_SCAN_PERIOD = 1 << 0, - EC_MKBP_VALID_POLL_TIMEOUT = 1 << 1, - EC_MKBP_VALID_MIN_POST_SCAN_DELAY = 1 << 3, - EC_MKBP_VALID_OUTPUT_SETTLE = 1 << 4, - EC_MKBP_VALID_DEBOUNCE_DOWN = 1 << 5, - EC_MKBP_VALID_DEBOUNCE_UP = 1 << 6, - EC_MKBP_VALID_FIFO_MAX_DEPTH = 1 << 7, + EC_MKBP_VALID_SCAN_PERIOD = BIT(0), + EC_MKBP_VALID_POLL_TIMEOUT = BIT(1), + EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3), + EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4), + EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5), + EC_MKBP_VALID_DEBOUNCE_UP = BIT(6), + EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7), }; /* @@ -2875,11 +4030,11 @@ enum mkbp_config_valid { * Note that this is used as a sub-structure of * ec_{params/response}_mkbp_get_config. */ -struct __ec_align_size1 ec_mkbp_config { - uint32_t valid_mask; /* valid fields */ - uint8_t flags; /* some flags (enum mkbp_config_flags) */ - uint8_t valid_flags; /* which flags are valid */ - uint16_t scan_period_us; /* period between start of scans */ +struct ec_mkbp_config { + uint32_t valid_mask; /* valid fields */ + uint8_t flags; /* some flags (enum mkbp_config_flags) */ + uint8_t valid_flags; /* which flags are valid */ + uint16_t scan_period_us; /* period between start of scans */ /* revert to interrupt mode after no activity for this long */ uint32_t poll_timeout_us; /* @@ -2890,29 +4045,29 @@ struct __ec_align_size1 ec_mkbp_config { uint16_t min_post_scan_delay_us; /* delay between setting up output and waiting for it to settle */ uint16_t output_settle_us; - uint16_t debounce_down_us; /* time for debounce on key down */ - uint16_t debounce_up_us; /* time for debounce on key up */ + uint16_t debounce_down_us; /* time for debounce on key down */ + uint16_t debounce_up_us; /* time for debounce on key up */ /* maximum depth to allow for fifo (0 = no keyscan output) */ uint8_t fifo_max_depth; -}; +} __ec_align_size1; -struct __ec_align_size1 ec_params_mkbp_set_config { +struct ec_params_mkbp_set_config { struct ec_mkbp_config config; -}; +} __ec_align_size1; -struct __ec_align_size1 ec_response_mkbp_get_config { +struct ec_response_mkbp_get_config { struct ec_mkbp_config config; -}; +} __ec_align_size1; /* Run the key scan emulation */ #define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066 enum ec_keyscan_seq_cmd { - EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */ - EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */ - EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */ - EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */ - EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */ + EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */ + EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */ + EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */ + EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */ + EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */ }; enum ec_collect_flags { @@ -2920,19 +4075,19 @@ enum ec_collect_flags { * Indicates this scan was processed by the EC. Due to timing, some * scans may be skipped. */ - EC_KEYSCAN_SEQ_FLAG_DONE = 1 << 0, + EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0), }; -struct __ec_align1 ec_collect_item { - uint8_t flags; /* some flags (enum ec_collect_flags) */ -}; +struct ec_collect_item { + uint8_t flags; /* some flags (enum ec_collect_flags) */ +} __ec_align1; -struct __ec_todo_packed ec_params_keyscan_seq_ctrl { - uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */ +struct ec_params_keyscan_seq_ctrl { + uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */ union { struct __ec_align1 { - uint8_t active; /* still active */ - uint8_t num_items; /* number of items */ + uint8_t active; /* still active */ + uint8_t num_items; /* number of items */ /* Current item being presented */ uint8_t cur_item; } status; @@ -2942,32 +4097,49 @@ struct __ec_todo_packed ec_params_keyscan_seq_ctrl { * start of the sequence. */ uint32_t time_us; - uint8_t scan[0]; /* keyscan data */ + /* keyscan data */ + uint8_t scan[FLEXIBLE_ARRAY_MEMBER_SIZE]; } add; struct __ec_align1 { - uint8_t start_item; /* First item to return */ - uint8_t num_items; /* Number of items to return */ + uint8_t start_item; /* First item to return */ + uint8_t num_items; /* Number of items to return */ } collect; }; -}; +} __ec_todo_packed; -struct __ec_todo_packed ec_result_keyscan_seq_ctrl { +struct ec_result_keyscan_seq_ctrl { union { struct __ec_todo_unpacked { - uint8_t num_items; /* Number of items */ + uint8_t num_items; /* Number of items */ /* Data for each item */ - struct ec_collect_item item[0]; + struct ec_collect_item item[FLEXIBLE_ARRAY_MEMBER_SIZE]; } collect; }; -}; +} __ec_todo_packed; /* * Get the next pending MKBP event. * * Returns EC_RES_UNAVAILABLE if there is no event pending. + * + * V0: ec_response_get_next_data + * V1: ec_response_get_next_data_v1. Increased key_matrix size from 13 -> 16. + * V2: Added EC_MKBP_HAS_MORE_EVENTS. + * V3: ec_response_get_next_data_v3. Increased key_matrix size from 16 -> 18. */ #define EC_CMD_GET_NEXT_EVENT 0x0067 +#define EC_MKBP_HAS_MORE_EVENTS_SHIFT 7 + +/* + * We use the most significant bit of the event type to indicate to the host + * that the EC has more MKBP events available to provide. + */ +#define EC_MKBP_HAS_MORE_EVENTS BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) + +/* The mask to apply to get the raw event type */ +#define EC_MKBP_EVENT_TYPE_MASK (BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) - 1) + enum ec_mkbp_event { /* Keyboard matrix changed. The event data is the new matrix state. */ EC_MKBP_EVENT_KEY_MATRIX = 0, @@ -2993,15 +4165,110 @@ enum ec_mkbp_event { */ EC_MKBP_EVENT_SYSRQ = 6, + /* + * New 64-bit host event. + * The event data is 8 bytes of host event flags. + */ + EC_MKBP_EVENT_HOST_EVENT64 = 7, + + /* Notify the AP that something happened on CEC */ + EC_MKBP_EVENT_CEC_EVENT = 8, + + /* Send an incoming CEC message to the AP */ + EC_MKBP_EVENT_CEC_MESSAGE = 9, + + /* We have entered DisplayPort Alternate Mode on a Type-C port. */ + EC_MKBP_EVENT_DP_ALT_MODE_ENTERED = 10, + + /* New online calibration values are available. */ + EC_MKBP_EVENT_ONLINE_CALIBRATION = 11, + + /* Peripheral device charger event */ + EC_MKBP_EVENT_PCHG = 12, + /* Number of MKBP events */ EC_MKBP_EVENT_COUNT, }; +BUILD_ASSERT(EC_MKBP_EVENT_COUNT <= EC_MKBP_EVENT_TYPE_MASK); + +/* clang-format off */ +#define EC_MKBP_EVENT_TEXT \ + { \ + [EC_MKBP_EVENT_KEY_MATRIX] = "KEY_MATRIX", \ + [EC_MKBP_EVENT_HOST_EVENT] = "HOST_EVENT", \ + [EC_MKBP_EVENT_SENSOR_FIFO] = "SENSOR_FIFO", \ + [EC_MKBP_EVENT_BUTTON] = "BUTTON", \ + [EC_MKBP_EVENT_SWITCH] = "SWITCH", \ + [EC_MKBP_EVENT_FINGERPRINT] = "FINGERPRINT", \ + [EC_MKBP_EVENT_SYSRQ] = "SYSRQ", \ + [EC_MKBP_EVENT_HOST_EVENT64] = "HOST_EVENT64", \ + [EC_MKBP_EVENT_CEC_EVENT] = "CEC_EVENT", \ + [EC_MKBP_EVENT_CEC_MESSAGE] = "CEC_MESSAGE", \ + [EC_MKBP_EVENT_DP_ALT_MODE_ENTERED] = "DP_ALT_MODE_ENTERED", \ + [EC_MKBP_EVENT_ONLINE_CALIBRATION] = "ONLINE_CALIBRATION", \ + [EC_MKBP_EVENT_PCHG] = "PCHG", \ + } +/* clang-format on */ union __ec_align_offset1 ec_response_get_next_data { uint8_t key_matrix[13]; /* Unaligned */ uint32_t host_event; + uint64_t host_event64; + + struct __ec_todo_unpacked { + /* For aligning the fifo_info */ + uint8_t reserved[3]; + struct ec_response_motion_sense_fifo_info info; + } sensor_fifo; + + uint32_t buttons; + + uint32_t switches; + + uint32_t fp_events; + + uint32_t sysrq; + + /* CEC events from enum mkbp_cec_event */ + uint32_t cec_events; +}; + +union __ec_align_offset1 ec_response_get_next_data_v1 { + uint8_t key_matrix[16]; + + /* Unaligned */ + uint32_t host_event; + uint64_t host_event64; + + struct __ec_todo_unpacked { + /* For aligning the fifo_info */ + uint8_t reserved[3]; + struct ec_response_motion_sense_fifo_info info; + } sensor_fifo; + + uint32_t buttons; + + uint32_t switches; + + uint32_t fp_events; + + uint32_t sysrq; + + /* CEC events from enum mkbp_cec_event */ + uint32_t cec_events; + + uint8_t cec_message[16]; +}; +BUILD_ASSERT(sizeof(union ec_response_get_next_data_v1) == 16); + +union __ec_align_offset1 ec_response_get_next_data_v3 { + uint8_t key_matrix[18]; + + /* Unaligned */ + uint32_t host_event; + uint64_t host_event64; struct __ec_todo_unpacked { /* For aligning the fifo_info */ @@ -3016,37 +4283,136 @@ union __ec_align_offset1 ec_response_get_next_data { uint32_t fp_events; uint32_t sysrq; + + /* CEC events from enum mkbp_cec_event */ + uint32_t cec_events; + + uint8_t cec_message[16]; }; +BUILD_ASSERT(sizeof(union ec_response_get_next_data_v3) == 18); -struct __ec_align1 ec_response_get_next_event { +struct ec_response_get_next_event { uint8_t event_type; /* Followed by event data if any */ union ec_response_get_next_data data; -}; +} __ec_align1; + +struct ec_response_get_next_event_v1 { + uint8_t event_type; + /* Followed by event data if any */ + union ec_response_get_next_data_v1 data; +} __ec_align1; + +struct ec_response_get_next_event_v3 { + uint8_t event_type; + /* Followed by event data if any */ + union ec_response_get_next_data_v3 data; +} __ec_align1; /* Bit indices for buttons and switches.*/ /* Buttons */ -#define EC_MKBP_POWER_BUTTON 0 -#define EC_MKBP_VOL_UP 1 -#define EC_MKBP_VOL_DOWN 2 -#define EC_MKBP_RECOVERY 3 +#define EC_MKBP_POWER_BUTTON 0 +#define EC_MKBP_VOL_UP 1 +#define EC_MKBP_VOL_DOWN 2 +#define EC_MKBP_RECOVERY 3 /* Switches */ -#define EC_MKBP_LID_OPEN 0 -#define EC_MKBP_TABLET_MODE 1 +#define EC_MKBP_LID_OPEN 0 +#define EC_MKBP_TABLET_MODE 1 +#define EC_MKBP_BASE_ATTACHED 2 +#define EC_MKBP_FRONT_PROXIMITY 3 /* Run keyboard factory test scanning */ #define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068 -struct __ec_align2 ec_response_keyboard_factory_test { - uint16_t shorted; /* Keyboard pins are shorted */ -}; +struct ec_response_keyboard_factory_test { + uint16_t shorted; /* Keyboard pins are shorted */ +} __ec_align2; /* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */ #define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF) -#define EC_MKBP_FP_FINGER_DOWN (1 << 29) -#define EC_MKBP_FP_FINGER_UP (1 << 30) -#define EC_MKBP_FP_IMAGE_READY (1 << 31) +#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events) & 0x0000000F) +#define EC_MKBP_FP_ENROLL_PROGRESS_OFFSET 4 +#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) \ + (((fpe) & 0x00000FF0) >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET) +#define EC_MKBP_FP_MATCH_IDX_OFFSET 12 +#define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000 +#define EC_MKBP_FP_MATCH_IDX(fpe) \ + (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) >> EC_MKBP_FP_MATCH_IDX_OFFSET) +#define EC_MKBP_FP_ENROLL BIT(27) +#define EC_MKBP_FP_MATCH BIT(28) +#define EC_MKBP_FP_FINGER_DOWN BIT(29) +#define EC_MKBP_FP_FINGER_UP BIT(30) +#define EC_MKBP_FP_IMAGE_READY BIT(31) +/* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_ENROLL is set */ +#define EC_MKBP_FP_ERR_ENROLL_OK 0 +#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1 +#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2 +#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3 +#define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5 +/* Can be used to detect if image was usable for enrollment or not. */ +#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1 +/* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_MATCH is set */ +#define EC_MKBP_FP_ERR_MATCH_NO 0 +#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6 +#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7 +#define EC_MKBP_FP_ERR_MATCH_NO_AUTH_FAIL 8 +#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2 +#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4 +#define EC_MKBP_FP_ERR_MATCH_YES 1 +#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3 +#define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5 + +#define EC_CMD_MKBP_WAKE_MASK 0x0069 +enum ec_mkbp_event_mask_action { + /* Retrieve the value of a wake mask. */ + GET_WAKE_MASK = 0, + + /* Set the value of a wake mask. */ + SET_WAKE_MASK, +}; + +enum ec_mkbp_mask_type { + /* + * These are host events sent via MKBP. + * + * Some examples are: + * EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) + * EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) + * + * The only things that should be in this mask are: + * EC_HOST_EVENT_MASK(EC_HOST_EVENT_*) + */ + EC_MKBP_HOST_EVENT_WAKE_MASK = 0, + + /* + * These are MKBP events. Some examples are: + * + * EC_MKBP_EVENT_KEY_MATRIX + * EC_MKBP_EVENT_SWITCH + * + * The only things that should be in this mask are EC_MKBP_EVENT_*. + */ + EC_MKBP_EVENT_WAKE_MASK, +}; + +struct ec_params_mkbp_event_wake_mask { + /* One of enum ec_mkbp_event_mask_action */ + uint8_t action; + + /* + * Which MKBP mask are you interested in acting upon? This is one of + * ec_mkbp_mask_type. + */ + uint8_t mask_type; + + /* If setting a new wake mask, this contains the mask to set. */ + uint32_t new_wake_mask; +}; + +struct ec_response_mkbp_event_wake_mask { + uint32_t wake_mask; +}; /*****************************************************************************/ /* Temperature sensor commands */ @@ -3054,14 +4420,14 @@ struct __ec_align2 ec_response_keyboard_factory_test { /* Read temperature sensor info */ #define EC_CMD_TEMP_SENSOR_GET_INFO 0x0070 -struct __ec_align1 ec_params_temp_sensor_get_info { +struct ec_params_temp_sensor_get_info { uint8_t id; -}; +} __ec_align1; -struct __ec_align1 ec_response_temp_sensor_get_info { +struct ec_response_temp_sensor_get_info { char sensor_name[32]; uint8_t sensor_type; -}; +} __ec_align1; /*****************************************************************************/ @@ -3074,39 +4440,42 @@ struct __ec_align1 ec_response_temp_sensor_get_info { /*****************************************************************************/ /* Host event commands */ -/* Obsolete. New implementation should use EC_CMD_PROGRAM_HOST_EVENT instead */ +/* Obsolete. New implementation should use EC_CMD_HOST_EVENT instead */ /* * Host event mask params and response structures, shared by all of the host * event commands below. */ -struct __ec_align4 ec_params_host_event_mask { +struct ec_params_host_event_mask { uint32_t mask; -}; +} __ec_align4; -struct __ec_align4 ec_response_host_event_mask { +struct ec_response_host_event_mask { uint32_t mask; -}; +} __ec_align4; /* These all use ec_response_host_event_mask */ -#define EC_CMD_HOST_EVENT_GET_B 0x0087 -#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088 -#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089 +#define EC_CMD_HOST_EVENT_GET_B 0x0087 +#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088 +#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089 #define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x008D /* These all use ec_params_host_event_mask */ -#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A -#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B -#define EC_CMD_HOST_EVENT_CLEAR 0x008C +#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A +#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B +#define EC_CMD_HOST_EVENT_CLEAR 0x008C #define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x008E -#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F +#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F /* * Unified host event programming interface - Should be used by newer versions * of BIOS/OS to program host events and masks + * + * EC returns: + * - EC_RES_INVALID_PARAM: Action or mask type is unknown. + * - EC_RES_ACCESS_DENIED: Action is prohibited for specified mask type. */ -struct __ec_align4 ec_params_host_event { - +struct ec_params_host_event { /* Action requested by host - one of enum ec_host_event_action. */ uint8_t action; @@ -3121,18 +4490,17 @@ struct __ec_align4 ec_params_host_event { /* Value to be used in case of set operations. */ uint64_t value; -}; +} __ec_align4; /* * Response structure returned by EC_CMD_HOST_EVENT. * Update the value on a GET request. Set to 0 on GET/CLEAR */ -struct __ec_align4 ec_response_host_event { - +struct ec_response_host_event { /* Mask value in case of get operation */ uint64_t value; -}; +} __ec_align4; enum ec_host_event_action { /* @@ -3178,7 +4546,7 @@ enum ec_host_event_mask_type { EC_HOST_EVENT_LAZY_WAKE_MASK_S5, }; -#define EC_CMD_HOST_EVENT 0x00A4 +#define EC_CMD_HOST_EVENT 0x00A4 /*****************************************************************************/ /* Switch commands */ @@ -3186,21 +4554,21 @@ enum ec_host_event_mask_type { /* Enable/disable LCD backlight */ #define EC_CMD_SWITCH_ENABLE_BKLIGHT 0x0090 -struct __ec_align1 ec_params_switch_enable_backlight { +struct ec_params_switch_enable_backlight { uint8_t enabled; -}; +} __ec_align1; /* Enable/disable WLAN/Bluetooth */ #define EC_CMD_SWITCH_ENABLE_WIRELESS 0x0091 #define EC_VER_SWITCH_ENABLE_WIRELESS 1 /* Version 0 params; no response */ -struct __ec_align1 ec_params_switch_enable_wireless_v0 { +struct ec_params_switch_enable_wireless_v0 { uint8_t enabled; -}; +} __ec_align1; /* Version 1 params */ -struct __ec_align1 ec_params_switch_enable_wireless_v1 { +struct ec_params_switch_enable_wireless_v1 { /* Flags to enable now */ uint8_t now_flags; @@ -3216,16 +4584,16 @@ struct __ec_align1 ec_params_switch_enable_wireless_v1 { /* Which flags to copy from suspend_flags */ uint8_t suspend_mask; -}; +} __ec_align1; /* Version 1 response */ -struct __ec_align1 ec_response_switch_enable_wireless_v1 { +struct ec_response_switch_enable_wireless_v1 { /* Flags to enable now */ uint8_t now_flags; /* Flags to leave enabled in S3 */ uint8_t suspend_flags; -}; +} __ec_align1; /*****************************************************************************/ /* GPIO commands. Only available on EC if write protect has been disabled. */ @@ -3233,25 +4601,25 @@ struct __ec_align1 ec_response_switch_enable_wireless_v1 { /* Set GPIO output value */ #define EC_CMD_GPIO_SET 0x0092 -struct __ec_align1 ec_params_gpio_set { +struct ec_params_gpio_set { char name[32]; uint8_t val; -}; +} __ec_align1; /* Get GPIO value */ #define EC_CMD_GPIO_GET 0x0093 /* Version 0 of input params and response */ -struct __ec_align1 ec_params_gpio_get { +struct ec_params_gpio_get { char name[32]; -}; +} __ec_align1; -struct __ec_align1 ec_response_gpio_get { +struct ec_response_gpio_get { uint8_t val; -}; +} __ec_align1; /* Version 1 of input params and response */ -struct __ec_align1 ec_params_gpio_get_v1 { +struct ec_params_gpio_get_v1 { uint8_t subcmd; union { struct __ec_align1 { @@ -3261,9 +4629,9 @@ struct __ec_align1 ec_params_gpio_get_v1 { uint8_t index; } get_info; }; -}; +} __ec_align1; -struct __ec_todo_packed ec_response_gpio_get_v1 { +struct ec_response_gpio_get_v1 { union { struct __ec_align1 { uint8_t val; @@ -3274,7 +4642,7 @@ struct __ec_todo_packed ec_response_gpio_get_v1 { uint32_t flags; } get_info; }; -}; +} __ec_todo_packed; enum gpio_get_subcmd { EC_GPIO_GET_BY_NAME = 0, @@ -3295,27 +4663,27 @@ enum gpio_get_subcmd { /* Read I2C bus */ #define EC_CMD_I2C_READ 0x0094 -struct __ec_align_size1 ec_params_i2c_read { +struct ec_params_i2c_read { uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ uint8_t read_size; /* Either 8 or 16. */ uint8_t port; uint8_t offset; -}; +} __ec_align_size1; -struct __ec_align2 ec_response_i2c_read { +struct ec_response_i2c_read { uint16_t data; -}; +} __ec_align2; /* Write I2C bus */ #define EC_CMD_I2C_WRITE 0x0095 -struct __ec_align_size1 ec_params_i2c_write { +struct ec_params_i2c_write { uint16_t data; uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ uint8_t write_size; /* Either 8 or 16. */ uint8_t port; uint8_t offset; -}; +} __ec_align_size1; /*****************************************************************************/ /* Charge state commands. Only available when flash write protect unlocked. */ @@ -3324,20 +4692,64 @@ struct __ec_align_size1 ec_params_i2c_write { * discharge the battery. */ #define EC_CMD_CHARGE_CONTROL 0x0096 -#define EC_VER_CHARGE_CONTROL 1 +#define EC_VER_CHARGE_CONTROL 3 enum ec_charge_control_mode { CHARGE_CONTROL_NORMAL = 0, CHARGE_CONTROL_IDLE, CHARGE_CONTROL_DISCHARGE, + /* Add no more entry below. */ + CHARGE_CONTROL_COUNT, +}; + +#define EC_CHARGE_MODE_TEXT \ + { \ + [CHARGE_CONTROL_NORMAL] = "NORMAL", \ + [CHARGE_CONTROL_IDLE] = "IDLE", \ + [CHARGE_CONTROL_DISCHARGE] = "DISCHARGE", \ + } + +enum ec_charge_control_cmd { + EC_CHARGE_CONTROL_CMD_SET = 0, + EC_CHARGE_CONTROL_CMD_GET, }; -struct __ec_align4 ec_params_charge_control { - uint32_t mode; /* enum charge_control_mode */ +enum ec_charge_control_flag { + EC_CHARGE_CONTROL_FLAG_NO_IDLE = BIT(0), }; +struct ec_params_charge_control { + uint32_t mode; /* enum charge_control_mode */ + + /* Below are the fields added in V2. */ + uint8_t cmd; /* enum ec_charge_control_cmd. */ + uint8_t flags; /* enum ec_charge_control_flag (v3+) */ + /* + * Lower and upper thresholds for battery sustainer. This struct isn't + * named to avoid tainting foreign projects' name spaces. + * + * If charge mode is explicitly set (e.g. DISCHARGE), battery sustainer + * will be disabled. To disable battery sustainer, set mode=NORMAL, + * lower=-1, upper=-1. + */ + struct { + int8_t lower; /* Display SoC in percentage. */ + int8_t upper; /* Display SoC in percentage. */ + } sustain_soc; +} __ec_align4; + +/* Added in v2 */ +struct ec_response_charge_control { + uint32_t mode; /* enum charge_control_mode */ + struct { /* Battery sustainer thresholds */ + int8_t lower; + int8_t upper; + } sustain_soc; + uint8_t flags; /* enum ec_charge_control_flag (v3+) */ + uint8_t reserved; +} __ec_align4; + /*****************************************************************************/ -/* Console commands. Only available when flash write protect is unlocked. */ /* Snapshot console output buffer for use by EC_CMD_CONSOLE_READ. */ #define EC_CMD_CONSOLE_SNAPSHOT 0x0097 @@ -3358,12 +4770,15 @@ struct __ec_align4 ec_params_charge_control { enum ec_console_read_subcmd { CONSOLE_READ_NEXT = 0, - CONSOLE_READ_RECENT + CONSOLE_READ_RECENT, }; -struct __ec_align1 ec_params_console_read_v1 { +struct ec_params_console_read_v1 { uint8_t subcmd; /* enum ec_console_read_subcmd */ -}; +} __ec_align1; + +/* Print directly to EC console from host. */ +#define EC_CMD_CONSOLE_PRINT 0x00AC /*****************************************************************************/ @@ -3376,11 +4791,11 @@ struct __ec_align1 ec_params_console_read_v1 { */ #define EC_CMD_BATTERY_CUT_OFF 0x0099 -#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN (1 << 0) +#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0) -struct __ec_align1 ec_params_battery_cutoff { +struct ec_params_battery_cutoff { uint8_t flags; -}; +} __ec_align1; /*****************************************************************************/ /* USB port mux control. */ @@ -3390,16 +4805,16 @@ struct __ec_align1 ec_params_battery_cutoff { */ #define EC_CMD_USB_MUX 0x009A -struct __ec_align1 ec_params_usb_mux { +struct ec_params_usb_mux { uint8_t mux; -}; +} __ec_align1; /*****************************************************************************/ /* LDOs / FETs control. */ enum ec_ldo_state { - EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */ - EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */ + EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */ + EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */ }; /* @@ -3407,39 +4822,92 @@ enum ec_ldo_state { */ #define EC_CMD_LDO_SET 0x009B -struct __ec_align1 ec_params_ldo_set { +struct ec_params_ldo_set { uint8_t index; uint8_t state; -}; +} __ec_align1; /* * Get LDO state. */ #define EC_CMD_LDO_GET 0x009C -struct __ec_align1 ec_params_ldo_get { +struct ec_params_ldo_get { uint8_t index; -}; +} __ec_align1; -struct __ec_align1 ec_response_ldo_get { +struct ec_response_ldo_get { uint8_t state; -}; +} __ec_align1; /*****************************************************************************/ /* Power info. */ /* * Get power info. + * + * Note: v0 of this command is deprecated */ #define EC_CMD_POWER_INFO 0x009D -struct __ec_align4 ec_response_power_info { - uint32_t usb_dev_type; - uint16_t voltage_ac; - uint16_t voltage_system; - uint16_t current_system; - uint16_t usb_current_limit; -}; +/* + * v1 of EC_CMD_POWER_INFO + */ +enum system_power_source { + /* + * Haven't established which power source is used yet, + * or no presence signals are available + */ + POWER_SOURCE_UNKNOWN = 0, + /* System is running on battery alone */ + POWER_SOURCE_BATTERY = 1, + /* System is running on A/C alone */ + POWER_SOURCE_AC = 2, + /* System is running on A/C and battery */ + POWER_SOURCE_AC_BATTERY = 3, +}; + +struct ec_response_power_info_v1 { + /* enum system_power_source */ + uint8_t system_power_source; + /* Battery state-of-charge, 0-100, 0 if not present */ + uint8_t battery_soc; + /* AC Adapter 100% rating, Watts */ + uint8_t ac_adapter_100pct; + /* AC Adapter 10ms rating, Watts */ + uint8_t ac_adapter_10ms; + /* Battery 1C rating, derated */ + uint8_t battery_1cd; + /* Rest of Platform average, Watts */ + uint8_t rop_avg; + /* Rest of Platform peak, Watts */ + uint8_t rop_peak; + /* Nominal charger efficiency, % */ + uint8_t nominal_charger_eff; + /* Rest of Platform VR Average Efficiency, % */ + uint8_t rop_avg_eff; + /* Rest of Platform VR Peak Efficiency, % */ + uint8_t rop_peak_eff; + /* SoC VR Efficiency at Average level, % */ + uint8_t soc_avg_eff; + /* SoC VR Efficiency at Peak level, % */ + uint8_t soc_peak_eff; + /* Intel-specific items */ + struct { + /* Battery's level of DBPT support: 0, 2 */ + uint8_t batt_dbpt_support_level; + /* + * Maximum peak power from battery (10ms), Watts + * If DBPT is not supported, this is 0 + */ + uint8_t batt_dbpt_max_peak_power; + /* + * Sustained peak power from battery, Watts + * If DBPT is not supported, this is 0 + */ + uint8_t batt_dbpt_sus_peak_power; + } intel; +} __ec_align1; /*****************************************************************************/ /* I2C passthru command */ @@ -3447,90 +4915,81 @@ struct __ec_align4 ec_response_power_info { #define EC_CMD_I2C_PASSTHRU 0x009E /* Read data; if not present, message is a write */ -#define EC_I2C_FLAG_READ (1 << 15) +#define EC_I2C_FLAG_READ BIT(15) /* Mask for address */ -#define EC_I2C_ADDR_MASK 0x3ff +#define EC_I2C_ADDR_MASK 0x3ff -#define EC_I2C_STATUS_NAK (1 << 0) /* Transfer was not acknowledged */ -#define EC_I2C_STATUS_TIMEOUT (1 << 1) /* Timeout during transfer */ +#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */ +#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */ /* Any error */ -#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) +#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) -struct __ec_align2 ec_params_i2c_passthru_msg { - uint16_t addr_flags; /* I2C slave address (7 or 10 bits) and flags */ - uint16_t len; /* Number of bytes to read or write */ -}; +struct ec_params_i2c_passthru_msg { + uint16_t addr_flags; /* I2C peripheral address and flags */ + uint16_t len; /* Number of bytes to read or write */ +} __ec_align2; -struct __ec_align2 ec_params_i2c_passthru { - uint8_t port; /* I2C port number */ - uint8_t num_msgs; /* Number of messages */ - struct ec_params_i2c_passthru_msg msg[]; +struct ec_params_i2c_passthru { + uint8_t port; /* I2C port number */ + uint8_t num_msgs; /* Number of messages */ + struct ec_params_i2c_passthru_msg msg[FLEXIBLE_ARRAY_MEMBER_SIZE]; /* Data to write for all messages is concatenated here */ -}; +} __ec_align2; -struct __ec_align1 ec_response_i2c_passthru { - uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ - uint8_t num_msgs; /* Number of messages processed */ - uint8_t data[]; /* Data read by messages concatenated here */ -}; +struct ec_response_i2c_passthru { + uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ + uint8_t num_msgs; /* Number of messages processed */ + /* Data read by messages concatenated here */ + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align1; /*****************************************************************************/ -/* Power button hang detect */ - +/* AP hang detect */ #define EC_CMD_HANG_DETECT 0x009F -/* Reasons to start hang detection timer */ -/* Power button pressed */ -#define EC_HANG_START_ON_POWER_PRESS (1 << 0) - -/* Lid closed */ -#define EC_HANG_START_ON_LID_CLOSE (1 << 1) +#define EC_HANG_DETECT_MIN_TIMEOUT 5 - /* Lid opened */ -#define EC_HANG_START_ON_LID_OPEN (1 << 2) +/* EC hang detect commands */ +enum ec_hang_detect_cmds { + /* Reload AP hang detect timer. */ + EC_HANG_DETECT_CMD_RELOAD = 0x0, -/* Start of AP S3->S0 transition (booting or resuming from suspend) */ -#define EC_HANG_START_ON_RESUME (1 << 3) + /* Stop AP hang detect timer. */ + EC_HANG_DETECT_CMD_CANCEL = 0x1, -/* Reasons to cancel hang detection */ - -/* Power button released */ -#define EC_HANG_STOP_ON_POWER_RELEASE (1 << 8) + /* Configure watchdog with given reboot timeout and + * cancel currently running AP hand detect timer. + */ + EC_HANG_DETECT_CMD_SET_TIMEOUT = 0x2, -/* Any host command from AP received */ -#define EC_HANG_STOP_ON_HOST_COMMAND (1 << 9) + /* Get last hang status - whether the AP boot was clear or not */ + EC_HANG_DETECT_CMD_GET_STATUS = 0x3, -/* Stop on end of AP S0->S3 transition (suspending or shutting down) */ -#define EC_HANG_STOP_ON_SUSPEND (1 << 10) + /* Clear last hang status. Called when AP is rebooting/shutting down + * gracefully. + */ + EC_HANG_DETECT_CMD_CLEAR_STATUS = 0x4 +}; -/* - * If this flag is set, all the other fields are ignored, and the hang detect - * timer is started. This provides the AP a way to start the hang timer - * without reconfiguring any of the other hang detect settings. Note that - * you must previously have configured the timeouts. - */ -#define EC_HANG_START_NOW (1 << 30) +struct ec_params_hang_detect { + uint16_t command; /* enum ec_hang_detect_cmds */ + /* Timeout in seconds before generating reboot */ + uint16_t reboot_timeout_sec; +} __ec_align2; -/* - * If this flag is set, all the other fields are ignored (including - * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer - * without reconfiguring any of the other hang detect settings. +/* Status codes that describe whether AP has boot normally or the hang has been + * detected and EC has reset AP */ -#define EC_HANG_STOP_NOW (1 << 31) - -struct __ec_align4 ec_params_hang_detect { - /* Flags; see EC_HANG_* */ - uint32_t flags; - - /* Timeout in msec before generating host event, if enabled */ - uint16_t host_event_timeout_msec; - - /* Timeout in msec before generating warm reboot, if enabled */ - uint16_t warm_reboot_timeout_msec; -}; - +enum ec_hang_detect_status { + EC_HANG_DETECT_AP_BOOT_NORMAL = 0x0, + EC_HANG_DETECT_AP_BOOT_EC_WDT = 0x1, + EC_HANG_DETECT_AP_BOOT_COUNT, +}; +struct ec_response_hang_detect { + uint8_t status; /* enum ec_hang_detect_status */ +} __ec_align1; /*****************************************************************************/ /* Commands for battery charging */ @@ -3545,7 +5004,7 @@ enum charge_state_command { CHARGE_STATE_CMD_GET_STATE, CHARGE_STATE_CMD_GET_PARAM, CHARGE_STATE_CMD_SET_PARAM, - CHARGE_STATE_NUM_CMDS + CHARGE_STATE_NUM_CMDS, }; /* @@ -3553,16 +5012,62 @@ enum charge_state_command { * params, which are handled by the particular implementations. */ enum charge_state_params { - CS_PARAM_CHG_VOLTAGE, /* charger voltage limit */ - CS_PARAM_CHG_CURRENT, /* charger current limit */ - CS_PARAM_CHG_INPUT_CURRENT, /* charger input current limit */ - CS_PARAM_CHG_STATUS, /* charger-specific status */ - CS_PARAM_CHG_OPTION, /* charger-specific options */ - CS_PARAM_LIMIT_POWER, /* - * Check if power is limited due to - * low battery and / or a weak external - * charger. READ ONLY. - */ + /* charger voltage limit */ + CS_PARAM_CHG_VOLTAGE, + + /* charger current limit */ + CS_PARAM_CHG_CURRENT, + + /* charger input current limit */ + CS_PARAM_CHG_INPUT_CURRENT, + + /* charger-specific status */ + CS_PARAM_CHG_STATUS, + + /* charger-specific options */ + CS_PARAM_CHG_OPTION, + + /* + * Check if power is limited due to low battery and / or a + * weak external charger. READ ONLY. + */ + CS_PARAM_LIMIT_POWER, + + /* min value of charger voltage limit (READ ONLY) */ + CS_PARAM_CHG_VOLTAGE_MIN, + + /* max value of charger voltage limit (READ ONLY) */ + CS_PARAM_CHG_VOLTAGE_MAX, + + /* step value of charger voltage limit (READ ONLY) */ + CS_PARAM_CHG_VOLTAGE_STEP, + + /* min value of charger current limit (READ ONLY) */ + CS_PARAM_CHG_CURRENT_MIN, + + /* max value of charger current limit (READ ONLY) */ + CS_PARAM_CHG_CURRENT_MAX, + + /* step value of charger current limit (READ ONLY) */ + CS_PARAM_CHG_CURRENT_STEP, + + /* min value of charger input current limit (READ ONLY) */ + CS_PARAM_CHG_INPUT_CURRENT_MIN, + + /* max value of charger input current limit (READ ONLY) */ + CS_PARAM_CHG_INPUT_CURRENT_MAX, + + /* step value of charger input current limit (READ ONLY) */ + CS_PARAM_CHG_INPUT_CURRENT_STEP, + + /* Minimum required voltage for hybrid boost chargers (READ ONLY) */ + CS_PARAM_CHG_MIN_REQUIRED_MV, + + /* For hybrid boost chargers returns !=0 when attached charger is + * capable of charging the battery + */ + CS_PARAM_CHG_IS_ADAPTER_SUFFICIENT, + /* How many so far? */ CS_NUM_BASE_PARAMS, @@ -3570,28 +5075,38 @@ enum charge_state_params { CS_PARAM_CUSTOM_PROFILE_MIN = 0x10000, CS_PARAM_CUSTOM_PROFILE_MAX = 0x1ffff, + /* Range for CONFIG_CHARGE_STATE_DEBUG params */ + CS_PARAM_DEBUG_MIN = 0x20000, + CS_PARAM_DEBUG_CTL_MODE = 0x20000, + CS_PARAM_DEBUG_MANUAL_MODE, + CS_PARAM_DEBUG_SEEMS_DEAD, + CS_PARAM_DEBUG_SEEMS_DISCONNECTED, + CS_PARAM_DEBUG_BATT_REMOVED, /* Deprecated */ + CS_PARAM_DEBUG_MANUAL_CURRENT, + CS_PARAM_DEBUG_MANUAL_VOLTAGE, + CS_PARAM_DEBUG_MAX = 0x2ffff, + /* Other custom param ranges go here... */ }; -struct __ec_todo_packed ec_params_charge_state { - uint8_t cmd; /* enum charge_state_command */ +struct ec_params_charge_state { + uint8_t cmd; /* enum charge_state_command */ union { - struct __ec_align1 { - /* no args */ - } get_state; + /* get_state has no args */ struct __ec_todo_unpacked { - uint32_t param; /* enum charge_state_param */ + uint32_t param; /* enum charge_state_param */ } get_param; struct __ec_todo_unpacked { - uint32_t param; /* param to set */ - uint32_t value; /* value to set */ + uint32_t param; /* param to set */ + uint32_t value; /* value to set */ } set_param; - }; -}; + } __ec_todo_packed; + uint8_t chgnum; /* Version 1 supports chgnum */ +} __ec_todo_packed; -struct __ec_align4 ec_response_charge_state { +struct ec_response_charge_state { union { struct __ec_align4 { int ac; @@ -3604,20 +5119,30 @@ struct __ec_align4 ec_response_charge_state { struct __ec_align4 { uint32_t value; } get_param; - struct __ec_align4 { - /* no return values */ - } set_param; + + /* set_param returns no args */ }; -}; +} __ec_align4; /* * Set maximum battery charging current. */ #define EC_CMD_CHARGE_CURRENT_LIMIT 0x00A1 +#define EC_VER_CHARGE_CURRENT_LIMIT 1 -struct __ec_align4 ec_params_current_limit { +struct ec_params_current_limit { uint32_t limit; /* in mA */ -}; +} __ec_align4; + +struct ec_params_current_limit_v1 { + uint32_t limit; /* in mA */ + /* + * Battery state of charge is the minimum charge percentage at which + * the battery charge current limit will apply. + * When not set, the limit will apply regardless of state of charge. + */ + uint8_t battery_soc; /* battery state of charge, 0-100 */ +} __ec_align4; /* * Set maximum external voltage / current. @@ -3625,10 +5150,10 @@ struct __ec_align4 ec_params_current_limit { #define EC_CMD_EXTERNAL_POWER_LIMIT 0x00A2 /* Command v0 is used only on Spring and is obsolete + unsupported */ -struct __ec_align2 ec_params_external_power_limit_v1 { +struct ec_params_external_power_limit_v1 { uint16_t current_lim; /* in mA, or EC_POWER_LIMIT_NONE to clear limit */ uint16_t voltage_lim; /* in mV, or EC_POWER_LIMIT_NONE to clear limit */ -}; +} __ec_align2; #define EC_POWER_LIMIT_NONE 0xffff @@ -3637,9 +5162,42 @@ struct __ec_align2 ec_params_external_power_limit_v1 { */ #define EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT 0x00A3 -struct __ec_align2 ec_params_dedicated_charger_limit { +struct ec_params_dedicated_charger_limit { uint16_t current_lim; /* in mA */ uint16_t voltage_lim; /* in mV */ +} __ec_align2; + +/* + * Get and set charging splashscreen variables + */ +#define EC_CMD_CHARGESPLASH 0x00A5 + +enum ec_chargesplash_cmd { + /* Get the current state variables */ + EC_CHARGESPLASH_GET_STATE = 0, + + /* Indicate initialization of the display loop */ + EC_CHARGESPLASH_DISPLAY_READY, + + /* Manually put the EC into the requested state */ + EC_CHARGESPLASH_REQUEST, + + /* Reset all state variables */ + EC_CHARGESPLASH_RESET, + + /* Manually trigger a lockout */ + EC_CHARGESPLASH_LOCKOUT, +}; + +struct __ec_align1 ec_params_chargesplash { + /* enum ec_chargesplash_cmd */ + uint8_t cmd; +}; + +struct __ec_align1 ec_response_chargesplash { + uint8_t requested; + uint8_t display_initialized; + uint8_t locked_out; }; /*****************************************************************************/ @@ -3648,15 +5206,15 @@ struct __ec_align2 ec_params_dedicated_charger_limit { /* Set the delay before going into hibernation. */ #define EC_CMD_HIBERNATION_DELAY 0x00A8 -struct __ec_align4 ec_params_hibernation_delay { +struct ec_params_hibernation_delay { /* * Seconds to wait in G3 before hibernate. Pass in 0 to read the * current settings without changing them. */ uint32_t seconds; -}; +} __ec_align4; -struct __ec_align4 ec_response_hibernation_delay { +struct ec_response_hibernation_delay { /* * The current time in seconds in which the system has been in the G3 * state. This value is reset if the EC transitions out of G3. @@ -3674,21 +5232,80 @@ struct __ec_align4 ec_response_hibernation_delay { * hibernating. */ uint32_t hibernate_delay; -}; +} __ec_align4; /* Inform the EC when entering a sleep state */ #define EC_CMD_HOST_SLEEP_EVENT 0x00A9 enum host_sleep_event { - HOST_SLEEP_EVENT_S3_SUSPEND = 1, - HOST_SLEEP_EVENT_S3_RESUME = 2, + HOST_SLEEP_EVENT_S3_SUSPEND = 1, + HOST_SLEEP_EVENT_S3_RESUME = 2, HOST_SLEEP_EVENT_S0IX_SUSPEND = 3, - HOST_SLEEP_EVENT_S0IX_RESUME = 4 + HOST_SLEEP_EVENT_S0IX_RESUME = 4, + /* S3 suspend with additional enabled wake sources */ + HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5, }; -struct __ec_align1 ec_params_host_sleep_event { +struct ec_params_host_sleep_event { uint8_t sleep_event; -}; +} __ec_align1; + +/* + * Use a default timeout value (CONFIG_SLEEP_TIMEOUT_MS) for detecting sleep + * transition failures + */ +#define EC_HOST_SLEEP_TIMEOUT_DEFAULT 0 + +/* Disable timeout detection for this sleep transition */ +#define EC_HOST_SLEEP_TIMEOUT_INFINITE 0xFFFF + +struct ec_params_host_sleep_event_v1 { + /* The type of sleep being entered or exited. */ + uint8_t sleep_event; + + /* Padding */ + uint8_t reserved; + union { + /* Parameters that apply for suspend messages. */ + struct { + /* + * The timeout in milliseconds between when this message + * is received and when the EC will declare sleep + * transition failure if the sleep signal is not + * asserted. + */ + uint16_t sleep_timeout_ms; + } suspend_params; + + /* No parameters for non-suspend messages. */ + }; +} __ec_align2; + +/* A timeout occurred when this bit is set */ +#define EC_HOST_RESUME_SLEEP_TIMEOUT 0x80000000 + +/* + * The mask defining which bits correspond to the number of sleep transitions, + * as well as the maximum number of suspend line transitions that will be + * reported back to the host. + */ +#define EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK 0x7FFFFFFF + +struct ec_response_host_sleep_event_v1 { + union { + /* Response fields that apply for resume messages. */ + struct { + /* + * The number of sleep power signal transitions that + * occurred since the suspend message. The high bit + * indicates a timeout occurred. + */ + uint32_t sleep_transitions; + } resume_response; + + /* No response fields for non-resume messages. */ + }; +} __ec_align4; /*****************************************************************************/ /* Device events */ @@ -3698,6 +5315,7 @@ enum ec_device_event { EC_DEVICE_EVENT_TRACKPAD, EC_DEVICE_EVENT_DSP, EC_DEVICE_EVENT_WIFI, + EC_DEVICE_EVENT_WLC, }; enum ec_device_event_param { @@ -3709,51 +5327,57 @@ enum ec_device_event_param { EC_DEVICE_EVENT_PARAM_SET_ENABLED_EVENTS, }; -#define EC_DEVICE_EVENT_MASK(event_code) (1UL << (event_code % 32)) +#define EC_DEVICE_EVENT_MASK(event_code) BIT(event_code % 32) -struct __ec_align_size1 ec_params_device_event { +struct ec_params_device_event { uint32_t event_mask; uint8_t param; -}; +} __ec_align_size1; -struct __ec_align4 ec_response_device_event { +struct ec_response_device_event { uint32_t event_mask; -}; +} __ec_align4; /*****************************************************************************/ -/* Smart battery pass-through */ +/* Get s0ix counter */ +#define EC_CMD_GET_S0IX_COUNTER 0x00AB -/* Get / Set 16-bit smart battery registers */ -#define EC_CMD_SB_READ_WORD 0x00B0 -#define EC_CMD_SB_WRITE_WORD 0x00B1 +/* Flag use to reset the counter */ +#define EC_S0IX_COUNTER_RESET 0x1 -/* Get / Set string smart battery parameters - * formatted as SMBUS "block". - */ -#define EC_CMD_SB_READ_BLOCK 0x00B2 -#define EC_CMD_SB_WRITE_BLOCK 0x00B3 +struct ec_params_s0ix_cnt { + /* If EC_S0IX_COUNTER_RESET then reset otherwise get the counter */ + uint32_t flags; +} __ec_align4; -struct __ec_align1 ec_params_sb_rd { - uint8_t reg; -}; +struct ec_response_s0ix_cnt { + /* Value of the s0ix_counter */ + uint32_t s0ix_counter; +} __ec_align4; -struct __ec_align2 ec_response_sb_rd_word { - uint16_t value; -}; +/*****************************************************************************/ +/* Ask the EC for sleep_signal_transitions without needing to send a + * HOST_SLEEP_EVENT command, which this command is related to. + * Note: EC_CMD_CONSOLE_PRINT has value 0x00AC, so skip over it. + */ +#define EC_CMD_HOST_SLEEP_SIGNAL_TRANSITIONS 0x00AD -struct __ec_align1 ec_params_sb_wr_word { - uint8_t reg; - uint16_t value; -}; +struct ec_response_host_sleep_signal_transitions { + uint32_t sleep_signal_transitions; +} __ec_align4; -struct __ec_align1 ec_response_sb_rd_block { - uint8_t data[32]; -}; +/*****************************************************************************/ +/* Smart battery pass-through */ -struct __ec_align1 ec_params_sb_wr_block { - uint8_t reg; - uint16_t data[32]; -}; +/* Get / Set 16-bit smart battery registers - OBSOLETE */ +#define EC_CMD_SB_READ_WORD 0x00B0 +#define EC_CMD_SB_WRITE_WORD 0x00B1 + +/* Get / Set string smart battery parameters + * formatted as SMBUS "block". - OBSOLETE + */ +#define EC_CMD_SB_READ_BLOCK 0x00B2 +#define EC_CMD_SB_WRITE_BLOCK 0x00B3 /*****************************************************************************/ /* Battery vendor parameters @@ -3771,90 +5395,39 @@ enum ec_battery_vendor_param_mode { BATTERY_VENDOR_PARAM_MODE_SET, }; -struct __ec_align_size1 ec_params_battery_vendor_param { +struct ec_params_battery_vendor_param { uint32_t param; uint32_t value; uint8_t mode; -}; +} __ec_align_size1; -struct __ec_align4 ec_response_battery_vendor_param { +struct ec_response_battery_vendor_param { uint32_t value; -}; +} __ec_align4; /*****************************************************************************/ /* - * Smart Battery Firmware Update Commands + * Smart Battery Firmware Update Command - OBSOLETE */ #define EC_CMD_SB_FW_UPDATE 0x00B5 -enum ec_sb_fw_update_subcmd { - EC_SB_FW_UPDATE_PREPARE = 0x0, - EC_SB_FW_UPDATE_INFO = 0x1, /*query sb info */ - EC_SB_FW_UPDATE_BEGIN = 0x2, /*check if protected */ - EC_SB_FW_UPDATE_WRITE = 0x3, /*check if protected */ - EC_SB_FW_UPDATE_END = 0x4, - EC_SB_FW_UPDATE_STATUS = 0x5, - EC_SB_FW_UPDATE_PROTECT = 0x6, - EC_SB_FW_UPDATE_MAX = 0x7, -}; - -#define SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE 32 -#define SB_FW_UPDATE_CMD_STATUS_SIZE 2 -#define SB_FW_UPDATE_CMD_INFO_SIZE 8 - -struct __ec_align4 ec_sb_fw_update_header { - uint16_t subcmd; /* enum ec_sb_fw_update_subcmd */ - uint16_t fw_id; /* firmware id */ -}; - -struct __ec_align4 ec_params_sb_fw_update { - struct ec_sb_fw_update_header hdr; - union { - /* EC_SB_FW_UPDATE_PREPARE = 0x0 */ - /* EC_SB_FW_UPDATE_INFO = 0x1 */ - /* EC_SB_FW_UPDATE_BEGIN = 0x2 */ - /* EC_SB_FW_UPDATE_END = 0x4 */ - /* EC_SB_FW_UPDATE_STATUS = 0x5 */ - /* EC_SB_FW_UPDATE_PROTECT = 0x6 */ - struct __ec_align4 { - /* no args */ - } dummy; - - /* EC_SB_FW_UPDATE_WRITE = 0x3 */ - struct __ec_align4 { - uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE]; - } write; - }; -}; - -struct __ec_align1 ec_response_sb_fw_update { - union { - /* EC_SB_FW_UPDATE_INFO = 0x1 */ - struct __ec_align1 { - uint8_t data[SB_FW_UPDATE_CMD_INFO_SIZE]; - } info; - - /* EC_SB_FW_UPDATE_STATUS = 0x5 */ - struct __ec_align1 { - uint8_t data[SB_FW_UPDATE_CMD_STATUS_SIZE]; - } status; - }; -}; - /* * Entering Verified Boot Mode Command * Default mode is VBOOT_MODE_NORMAL if EC did not receive this command. * Valid Modes are: normal, developer, and recovery. + * + * EC no longer needs to know what mode vboot has entered, + * so this command is deprecated. (See chromium:1014379.) */ #define EC_CMD_ENTERING_MODE 0x00B6 -struct __ec_align4 ec_params_entering_mode { +struct ec_params_entering_mode { int vboot_mode; -}; +} __ec_align4; -#define VBOOT_MODE_NORMAL 0 +#define VBOOT_MODE_NORMAL 0 #define VBOOT_MODE_DEVELOPER 1 -#define VBOOT_MODE_RECOVERY 2 +#define VBOOT_MODE_RECOVERY 2 /*****************************************************************************/ /* @@ -3864,578 +5437,2978 @@ struct __ec_align4 ec_params_entering_mode { #define EC_CMD_I2C_PASSTHRU_PROTECT 0x00B7 enum ec_i2c_passthru_protect_subcmd { - EC_CMD_I2C_PASSTHRU_PROTECT_STATUS = 0x0, - EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 0x1, + EC_CMD_I2C_PASSTHRU_PROTECT_STATUS = 0, + EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 1, + EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE_TCPCS = 2, }; -struct __ec_align1 ec_params_i2c_passthru_protect { +struct ec_params_i2c_passthru_protect { uint8_t subcmd; - uint8_t port; /* I2C port number */ -}; + uint8_t port; /* I2C port number */ +} __ec_align1; -struct __ec_align1 ec_response_i2c_passthru_protect { - uint8_t status; /* Status flags (0: unlocked, 1: locked) */ -}; +struct ec_response_i2c_passthru_protect { + uint8_t status; /* Status flags (0: unlocked, 1: locked) */ +} __ec_align1; /*****************************************************************************/ -/* System commands */ - /* - * TODO(crosbug.com/p/23747): This is a confusing name, since it doesn't - * necessarily reboot the EC. Rename to "image" or something similar? + * HDMI CEC commands + * + * These commands are for sending and receiving message via HDMI CEC */ -#define EC_CMD_REBOOT_EC 0x00D2 - -/* Command */ -enum ec_reboot_cmd { - EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */ - EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */ - EC_REBOOT_JUMP_RW = 2, /* Jump to RW without rebooting */ - /* (command 3 was jump to RW-B) */ - EC_REBOOT_COLD = 4, /* Cold-reboot */ - EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ - EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ - EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_OFF flag */ -}; -/* Flags for ec_params_reboot_ec.reboot_flags */ -#define EC_REBOOT_FLAG_RESERVED0 (1 << 0) /* Was recovery request */ -#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN (1 << 1) /* Reboot after AP shutdown */ -#define EC_REBOOT_FLAG_SWITCH_RW_SLOT (1 << 2) /* Switch RW slot */ +#define EC_CEC_MAX_PORTS 16 -struct __ec_align1 ec_params_reboot_ec { - uint8_t cmd; /* enum ec_reboot_cmd */ - uint8_t flags; /* See EC_REBOOT_FLAG_* */ -}; +#define MAX_CEC_MSG_LEN 16 /* - * Get information on last EC panic. - * - * Returns variable-length platform-dependent panic information. See panic.h - * for details. + * Helper macros for packing/unpacking cec_events. + * bits[27:0] : bitmask of events from enum mkbp_cec_event + * bits[31:28]: port number */ -#define EC_CMD_GET_PANIC_INFO 0x00D3 +#define EC_MKBP_EVENT_CEC_PACK(events, port) \ + (((events) & GENMASK(27, 0)) | (((port) & 0xf) << 28)) +#define EC_MKBP_EVENT_CEC_GET_EVENTS(event) ((event) & GENMASK(27, 0)) +#define EC_MKBP_EVENT_CEC_GET_PORT(event) (((event) >> 28) & 0xf) -/*****************************************************************************/ -/* - * Special commands - * - * These do not follow the normal rules for commands. See each command for - * details. +/* CEC message from the AP to be written on the CEC bus */ +#define EC_CMD_CEC_WRITE_MSG 0x00B8 + +/** + * struct ec_params_cec_write - Message to write to the CEC bus + * @msg: message content to write to the CEC bus + */ +struct ec_params_cec_write { + uint8_t msg[MAX_CEC_MSG_LEN]; +} __ec_align1; + +/** + * struct ec_params_cec_write_v1 - Message to write to the CEC bus + * @port: CEC port to write the message on + * @msg_len: length of msg in bytes + * @msg: message content to write to the CEC bus */ +struct ec_params_cec_write_v1 { + uint8_t port; + uint8_t msg_len; + uint8_t msg[MAX_CEC_MSG_LEN]; +} __ec_align1; -/* - * Reboot NOW - * - * This command will work even when the EC LPC interface is busy, because the - * reboot command is processed at interrupt level. Note that when the EC - * reboots, the host will reboot too, so there is no response to this command. - * - * Use EC_CMD_REBOOT_EC to reboot the EC more politely. +/* CEC message read from a CEC bus reported back to the AP */ +#define EC_CMD_CEC_READ_MSG 0x00B9 + +/** + * struct ec_params_cec_read - Read a message from the CEC bus + * @port: CEC port to read a message on */ -#define EC_CMD_REBOOT 0x00D1 /* Think "die" */ +struct ec_params_cec_read { + uint8_t port; +} __ec_align1; -/* - * Resend last response (not supported on LPC). - * - * Returns EC_RES_UNAVAILABLE if there is no response available - for example, - * there was no previous command, or the previous command's response was too - * big to save. +/** + * struct ec_response_cec_read - Message read from the CEC bus + * @msg_len: length of msg in bytes + * @msg: message content read from the CEC bus */ -#define EC_CMD_RESEND_RESPONSE 0x00DB +struct ec_response_cec_read { + uint8_t msg_len; + uint8_t msg[MAX_CEC_MSG_LEN]; +} __ec_align1; + +/* Set various CEC parameters */ +#define EC_CMD_CEC_SET 0x00BA + +/** + * struct ec_params_cec_set - CEC parameters set + * @cmd: parameter type, can be CEC_CMD_ENABLE or CEC_CMD_LOGICAL_ADDRESS + * @port: CEC port to set the parameter on + * @val: in case cmd is CEC_CMD_ENABLE, this field can be 0 to disable CEC + * or 1 to enable CEC functionality, in case cmd is + * CEC_CMD_LOGICAL_ADDRESS, this field encodes the requested logical + * address between 0 and 15 or 0xff to unregister + */ +struct ec_params_cec_set { + uint8_t cmd : 4; /* enum cec_command */ + uint8_t port : 4; + uint8_t val; +} __ec_align1; -/* - * This header byte on a command indicate version 0. Any header byte less - * than this means that we are talking to an old EC which doesn't support - * versioning. In that case, we assume version 0. - * - * Header bytes greater than this indicate a later version. For example, - * EC_CMD_VERSION0 + 1 means we are using version 1. - * - * The old EC interface must not use commands 0xdc or higher. +/* Read various CEC parameters */ +#define EC_CMD_CEC_GET 0x00BB + +/** + * struct ec_params_cec_get - CEC parameters get + * @cmd: parameter type, can be CEC_CMD_ENABLE or CEC_CMD_LOGICAL_ADDRESS + * @port: CEC port to get the parameter on */ -#define EC_CMD_VERSION0 0x00DC +struct ec_params_cec_get { + uint8_t cmd : 4; /* enum cec_command */ + uint8_t port : 4; +} __ec_align1; + +/** + * struct ec_response_cec_get - CEC parameters get response + * @val: in case cmd was CEC_CMD_ENABLE, this field will 0 if CEC is + * disabled or 1 if CEC functionality is enabled, + * in case cmd was CEC_CMD_LOGICAL_ADDRESS, this will encode the + * configured logical address between 0 and 15 or 0xff if unregistered + */ +struct ec_response_cec_get { + uint8_t val; +} __ec_align1; -/*****************************************************************************/ -/* - * PD commands - * - * These commands are for PD MCU communication. - */ +/* Get the number of CEC ports */ +#define EC_CMD_CEC_PORT_COUNT 0x00C1 -/* EC to PD MCU exchange status command */ -#define EC_CMD_PD_EXCHANGE_STATUS 0x0100 -#define EC_VER_PD_EXCHANGE_STATUS 2 +/** + * struct ec_response_cec_port_count - CEC port count response + * @port_count: number of CEC ports + */ +struct ec_response_cec_port_count { + uint8_t port_count; +} __ec_align1; -enum pd_charge_state { - PD_CHARGE_NO_CHANGE = 0, /* Don't change charge state */ - PD_CHARGE_NONE, /* No charging allowed */ - PD_CHARGE_5V, /* 5V charging only */ - PD_CHARGE_MAX /* Charge at max voltage */ +/* CEC parameters command */ +enum cec_command { + /* CEC reading, writing and events enable */ + CEC_CMD_ENABLE, + /* CEC logical address */ + CEC_CMD_LOGICAL_ADDRESS, }; -/* Status of EC being sent to PD */ -#define EC_STATUS_HIBERNATING (1 << 0) - -struct __ec_align1 ec_params_pd_status { - uint8_t status; /* EC status */ - int8_t batt_soc; /* battery state of charge */ - uint8_t charge_state; /* charging state (from enum pd_charge_state) */ +/* Events from CEC to AP */ +enum mkbp_cec_event { + /* Outgoing message was acknowledged by a follower */ + EC_MKBP_CEC_SEND_OK = BIT(0), + /* Outgoing message was not acknowledged */ + EC_MKBP_CEC_SEND_FAILED = BIT(1), + /* Incoming message can be read out by AP */ + EC_MKBP_CEC_HAVE_DATA = BIT(2), }; -/* Status of PD being sent back to EC */ -#define PD_STATUS_HOST_EVENT (1 << 0) /* Forward host event to AP */ -#define PD_STATUS_IN_RW (1 << 1) /* Running RW image */ -#define PD_STATUS_JUMPED_TO_IMAGE (1 << 2) /* Current image was jumped to */ -#define PD_STATUS_TCPC_ALERT_0 (1 << 3) /* Alert active in port 0 TCPC */ -#define PD_STATUS_TCPC_ALERT_1 (1 << 4) /* Alert active in port 1 TCPC */ -#define PD_STATUS_TCPC_ALERT_2 (1 << 5) /* Alert active in port 2 TCPC */ -#define PD_STATUS_TCPC_ALERT_3 (1 << 6) /* Alert active in port 3 TCPC */ -#define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \ - PD_STATUS_TCPC_ALERT_1 | \ - PD_STATUS_HOST_EVENT) -struct __ec_align_size1 ec_response_pd_status { - uint32_t curr_lim_ma; /* input current limit */ - uint16_t status; /* PD MCU status */ - int8_t active_charge_port; /* active charging port */ -}; +/*****************************************************************************/ -/* AP to PD MCU host event status command, cleared on read */ -#define EC_CMD_PD_HOST_EVENT_STATUS 0x0104 +/* Commands for audio codec. */ +#define EC_CMD_EC_CODEC 0x00BC -/* PD MCU host event status bits */ -#define PD_EVENT_UPDATE_DEVICE (1 << 0) -#define PD_EVENT_POWER_CHANGE (1 << 1) -#define PD_EVENT_IDENTITY_RECEIVED (1 << 2) -#define PD_EVENT_DATA_SWAP (1 << 3) -struct __ec_align4 ec_response_host_event_status { - uint32_t status; /* PD MCU host event status */ +enum ec_codec_subcmd { + EC_CODEC_GET_CAPABILITIES = 0x0, + EC_CODEC_GET_SHM_ADDR = 0x1, + EC_CODEC_SET_SHM_ADDR = 0x2, + EC_CODEC_SUBCMD_COUNT, }; -/* Set USB type-C port role and muxes */ -#define EC_CMD_USB_PD_CONTROL 0x0101 - -enum usb_pd_control_role { - USB_PD_CTRL_ROLE_NO_CHANGE = 0, - USB_PD_CTRL_ROLE_TOGGLE_ON = 1, /* == AUTO */ - USB_PD_CTRL_ROLE_TOGGLE_OFF = 2, - USB_PD_CTRL_ROLE_FORCE_SINK = 3, - USB_PD_CTRL_ROLE_FORCE_SOURCE = 4, - USB_PD_CTRL_ROLE_COUNT +enum ec_codec_cap { + EC_CODEC_CAP_WOV_AUDIO_SHM = 0, + EC_CODEC_CAP_WOV_LANG_SHM = 1, + EC_CODEC_CAP_LAST = 32, }; -enum usb_pd_control_mux { - USB_PD_CTRL_MUX_NO_CHANGE = 0, - USB_PD_CTRL_MUX_NONE = 1, - USB_PD_CTRL_MUX_USB = 2, - USB_PD_CTRL_MUX_DP = 3, - USB_PD_CTRL_MUX_DOCK = 4, - USB_PD_CTRL_MUX_AUTO = 5, - USB_PD_CTRL_MUX_COUNT +enum ec_codec_shm_id { + EC_CODEC_SHM_ID_WOV_AUDIO = 0x0, + EC_CODEC_SHM_ID_WOV_LANG = 0x1, + EC_CODEC_SHM_ID_LAST, }; -enum usb_pd_control_swap { - USB_PD_CTRL_SWAP_NONE = 0, - USB_PD_CTRL_SWAP_DATA = 1, - USB_PD_CTRL_SWAP_POWER = 2, - USB_PD_CTRL_SWAP_VCONN = 3, - USB_PD_CTRL_SWAP_COUNT +enum ec_codec_shm_type { + EC_CODEC_SHM_TYPE_EC_RAM = 0x0, + EC_CODEC_SHM_TYPE_SYSTEM_RAM = 0x1, }; -struct __ec_align1 ec_params_usb_pd_control { - uint8_t port; - uint8_t role; - uint8_t mux; - uint8_t swap; +struct __ec_align1 ec_param_ec_codec_get_shm_addr { + uint8_t shm_id; + uint8_t reserved[3]; }; -#define PD_CTRL_RESP_ENABLED_COMMS (1 << 0) /* Communication enabled */ -#define PD_CTRL_RESP_ENABLED_CONNECTED (1 << 1) /* Device connected */ -#define PD_CTRL_RESP_ENABLED_PD_CAPABLE (1 << 2) /* Partner is PD capable */ +struct __ec_align4 ec_param_ec_codec_set_shm_addr { + uint64_t phys_addr; + uint32_t len; + uint8_t shm_id; + uint8_t reserved[3]; +}; -#define PD_CTRL_RESP_ROLE_POWER (1 << 0) /* 0=SNK/1=SRC */ -#define PD_CTRL_RESP_ROLE_DATA (1 << 1) /* 0=UFP/1=DFP */ -#define PD_CTRL_RESP_ROLE_VCONN (1 << 2) /* Vconn status */ -#define PD_CTRL_RESP_ROLE_DR_POWER (1 << 3) /* Partner is dualrole power */ -#define PD_CTRL_RESP_ROLE_DR_DATA (1 << 4) /* Partner is dualrole data */ -#define PD_CTRL_RESP_ROLE_USB_COMM (1 << 5) /* Partner USB comm capable */ -#define PD_CTRL_RESP_ROLE_EXT_POWERED (1 << 6) /* Partner externally powerd */ +struct __ec_align4 ec_param_ec_codec { + uint8_t cmd; /* enum ec_codec_subcmd */ + uint8_t reserved[3]; -struct __ec_align1 ec_response_usb_pd_control { - uint8_t enabled; - uint8_t role; - uint8_t polarity; - uint8_t state; + union { + struct ec_param_ec_codec_get_shm_addr get_shm_addr_param; + struct ec_param_ec_codec_set_shm_addr set_shm_addr_param; + }; }; -struct __ec_align1 ec_response_usb_pd_control_v1 { - uint8_t enabled; - uint8_t role; - uint8_t polarity; - char state[32]; +struct __ec_align4 ec_response_ec_codec_get_capabilities { + uint32_t capabilities; }; -#define EC_CMD_USB_PD_PORTS 0x0102 - -/* Maximum number of PD ports on a device, num_ports will be <= this */ -#define EC_USB_PD_MAX_PORTS 8 - -struct __ec_align1 ec_response_usb_pd_ports { - uint8_t num_ports; +struct __ec_align4 ec_response_ec_codec_get_shm_addr { + uint64_t phys_addr; + uint32_t len; + uint8_t type; + uint8_t reserved[3]; }; -#define EC_CMD_USB_PD_POWER_INFO 0x0103 +/*****************************************************************************/ -#define PD_POWER_CHARGING_PORT 0xff -struct __ec_align1 ec_params_usb_pd_power_info { - uint8_t port; -}; +/* Commands for DMIC on audio codec. */ +#define EC_CMD_EC_CODEC_DMIC 0x00BD -enum usb_chg_type { - USB_CHG_TYPE_NONE, - USB_CHG_TYPE_PD, - USB_CHG_TYPE_C, - USB_CHG_TYPE_PROPRIETARY, - USB_CHG_TYPE_BC12_DCP, - USB_CHG_TYPE_BC12_CDP, - USB_CHG_TYPE_BC12_SDP, - USB_CHG_TYPE_OTHER, - USB_CHG_TYPE_VBUS, - USB_CHG_TYPE_UNKNOWN, +enum ec_codec_dmic_subcmd { + EC_CODEC_DMIC_GET_MAX_GAIN = 0x0, + EC_CODEC_DMIC_SET_GAIN_IDX = 0x1, + EC_CODEC_DMIC_GET_GAIN_IDX = 0x2, + EC_CODEC_DMIC_SUBCMD_COUNT, }; -enum usb_power_roles { - USB_PD_PORT_POWER_DISCONNECTED, - USB_PD_PORT_POWER_SOURCE, - USB_PD_PORT_POWER_SINK, - USB_PD_PORT_POWER_SINK_NOT_CHARGING, + +enum ec_codec_dmic_channel { + EC_CODEC_DMIC_CHANNEL_0 = 0x0, + EC_CODEC_DMIC_CHANNEL_1 = 0x1, + EC_CODEC_DMIC_CHANNEL_2 = 0x2, + EC_CODEC_DMIC_CHANNEL_3 = 0x3, + EC_CODEC_DMIC_CHANNEL_4 = 0x4, + EC_CODEC_DMIC_CHANNEL_5 = 0x5, + EC_CODEC_DMIC_CHANNEL_6 = 0x6, + EC_CODEC_DMIC_CHANNEL_7 = 0x7, + EC_CODEC_DMIC_CHANNEL_COUNT, }; -struct __ec_align2 usb_chg_measures { - uint16_t voltage_max; - uint16_t voltage_now; - uint16_t current_max; - uint16_t current_lim; +struct __ec_align1 ec_param_ec_codec_dmic_set_gain_idx { + uint8_t channel; /* enum ec_codec_dmic_channel */ + uint8_t gain; + uint8_t reserved[2]; }; -struct __ec_align4 ec_response_usb_pd_power_info { - uint8_t role; - uint8_t type; - uint8_t dualrole; - uint8_t reserved1; - struct usb_chg_measures meas; - uint32_t max_power; +struct __ec_align1 ec_param_ec_codec_dmic_get_gain_idx { + uint8_t channel; /* enum ec_codec_dmic_channel */ + uint8_t reserved[3]; }; -/* Write USB-PD device FW */ -#define EC_CMD_USB_PD_FW_UPDATE 0x0110 +struct __ec_align4 ec_param_ec_codec_dmic { + uint8_t cmd; /* enum ec_codec_dmic_subcmd */ + uint8_t reserved[3]; -enum usb_pd_fw_update_cmds { - USB_PD_FW_REBOOT, - USB_PD_FW_FLASH_ERASE, - USB_PD_FW_FLASH_WRITE, - USB_PD_FW_ERASE_SIG, + union { + struct ec_param_ec_codec_dmic_set_gain_idx set_gain_idx_param; + struct ec_param_ec_codec_dmic_get_gain_idx get_gain_idx_param; + }; }; -struct __ec_align4 ec_params_usb_pd_fw_update { - uint16_t dev_id; - uint8_t cmd; - uint8_t port; - uint32_t size; /* Size to write in bytes */ - /* Followed by data to write */ +struct __ec_align1 ec_response_ec_codec_dmic_get_max_gain { + uint8_t max_gain; }; -/* Write USB-PD Accessory RW_HASH table entry */ -#define EC_CMD_USB_PD_RW_HASH_ENTRY 0x0111 -/* RW hash is first 20 bytes of SHA-256 of RW section */ -#define PD_RW_HASH_SIZE 20 -struct __ec_align1 ec_params_usb_pd_rw_hash_entry { - uint16_t dev_id; - uint8_t dev_rw_hash[PD_RW_HASH_SIZE]; - uint8_t reserved; /* For alignment of current_image - * TODO(rspangler) but it's not aligned! - * Should have been reserved[2]. */ - uint32_t current_image; /* One of ec_current_image */ +struct __ec_align1 ec_response_ec_codec_dmic_get_gain_idx { + uint8_t gain; }; -/* Read USB-PD Accessory info */ -#define EC_CMD_USB_PD_DEV_INFO 0x0112 +/*****************************************************************************/ -struct __ec_align1 ec_params_usb_pd_info_request { - uint8_t port; +/* Commands for I2S RX on audio codec. */ + +#define EC_CMD_EC_CODEC_I2S_RX 0x00BE + +enum ec_codec_i2s_rx_subcmd { + EC_CODEC_I2S_RX_ENABLE = 0x0, + EC_CODEC_I2S_RX_DISABLE = 0x1, + EC_CODEC_I2S_RX_SET_SAMPLE_DEPTH = 0x2, + EC_CODEC_I2S_RX_SET_DAIFMT = 0x3, + EC_CODEC_I2S_RX_SET_BCLK = 0x4, + EC_CODEC_I2S_RX_RESET = 0x5, + EC_CODEC_I2S_RX_SUBCMD_COUNT, }; -/* Read USB-PD Device discovery info */ -#define EC_CMD_USB_PD_DISCOVERY 0x0113 -struct __ec_align_size1 ec_params_usb_pd_discovery_entry { - uint16_t vid; /* USB-IF VID */ - uint16_t pid; /* USB-IF PID */ - uint8_t ptype; /* product type (hub,periph,cable,ama) */ +enum ec_codec_i2s_rx_sample_depth { + EC_CODEC_I2S_RX_SAMPLE_DEPTH_16 = 0x0, + EC_CODEC_I2S_RX_SAMPLE_DEPTH_24 = 0x1, + EC_CODEC_I2S_RX_SAMPLE_DEPTH_COUNT, }; -/* Override default charge behavior */ -#define EC_CMD_PD_CHARGE_PORT_OVERRIDE 0x0114 +enum ec_codec_i2s_rx_daifmt { + EC_CODEC_I2S_RX_DAIFMT_I2S = 0x0, + EC_CODEC_I2S_RX_DAIFMT_RIGHT_J = 0x1, + EC_CODEC_I2S_RX_DAIFMT_LEFT_J = 0x2, + EC_CODEC_I2S_RX_DAIFMT_COUNT, +}; -/* Negative port parameters have special meaning */ -enum usb_pd_override_ports { - OVERRIDE_DONT_CHARGE = -2, - OVERRIDE_OFF = -1, - /* [0, CONFIG_USB_PD_PORT_COUNT): Port# */ +struct __ec_align1 ec_param_ec_codec_i2s_rx_set_sample_depth { + uint8_t depth; + uint8_t reserved[3]; }; -struct __ec_align2 ec_params_charge_port_override { - int16_t override_port; /* Override port# */ +struct __ec_align1 ec_param_ec_codec_i2s_rx_set_gain { + uint8_t left; + uint8_t right; + uint8_t reserved[2]; }; -/* Read (and delete) one entry of PD event log */ -#define EC_CMD_PD_GET_LOG_ENTRY 0x0115 +struct __ec_align1 ec_param_ec_codec_i2s_rx_set_daifmt { + uint8_t daifmt; + uint8_t reserved[3]; +}; -struct __ec_align4 ec_response_pd_log { - uint32_t timestamp; /* relative timestamp in milliseconds */ - uint8_t type; /* event type : see PD_EVENT_xx below */ - uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */ - uint16_t data; /* type-defined data payload */ - uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */ +struct __ec_align4 ec_param_ec_codec_i2s_rx_set_bclk { + uint32_t bclk; }; -/* The timestamp is the microsecond counter shifted to get about a ms. */ -#define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */ +struct __ec_align4 ec_param_ec_codec_i2s_rx { + uint8_t cmd; /* enum ec_codec_i2s_rx_subcmd */ + uint8_t reserved[3]; -#define PD_LOG_SIZE_MASK 0x1f -#define PD_LOG_PORT_MASK 0xe0 -#define PD_LOG_PORT_SHIFT 5 -#define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \ - ((size) & PD_LOG_SIZE_MASK)) -#define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT) -#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK) + union { + struct ec_param_ec_codec_i2s_rx_set_sample_depth + set_sample_depth_param; + struct ec_param_ec_codec_i2s_rx_set_daifmt set_daifmt_param; + struct ec_param_ec_codec_i2s_rx_set_bclk set_bclk_param; + }; +}; -/* PD event log : entry types */ -/* PD MCU events */ -#define PD_EVENT_MCU_BASE 0x00 -#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE+0) -#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE+1) -/* Reserved for custom board event */ -#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE+2) -/* PD generic accessory events */ -#define PD_EVENT_ACC_BASE 0x20 -#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE+0) -#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE+1) -/* PD power supply events */ -#define PD_EVENT_PS_BASE 0x40 -#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE+0) -/* PD video dongles events */ -#define PD_EVENT_VIDEO_BASE 0x60 -#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0) -#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE+1) -/* Returned in the "type" field, when there is no entry available */ -#define PD_EVENT_NO_ENTRY 0xff +/*****************************************************************************/ +/* Commands for WoV on audio codec. */ -/* - * PD_EVENT_MCU_CHARGE event definition : - * the payload is "struct usb_chg_measures" - * the data field contains the port state flags as defined below : - */ -/* Port partner is a dual role device */ -#define CHARGE_FLAGS_DUAL_ROLE (1 << 15) -/* Port is the pending override port */ -#define CHARGE_FLAGS_DELAYED_OVERRIDE (1 << 14) -/* Port is the override port */ -#define CHARGE_FLAGS_OVERRIDE (1 << 13) -/* Charger type */ -#define CHARGE_FLAGS_TYPE_SHIFT 3 -#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT) -/* Power delivery role */ -#define CHARGE_FLAGS_ROLE_MASK (7 << 0) +#define EC_CMD_EC_CODEC_WOV 0x00BF -/* - * PD_EVENT_PS_FAULT data field flags definition : - */ -#define PS_FAULT_OCP 1 -#define PS_FAULT_FAST_OCP 2 -#define PS_FAULT_OVP 3 -#define PS_FAULT_DISCH 4 +enum ec_codec_wov_subcmd { + EC_CODEC_WOV_SET_LANG = 0x0, + EC_CODEC_WOV_SET_LANG_SHM = 0x1, + EC_CODEC_WOV_GET_LANG = 0x2, + EC_CODEC_WOV_ENABLE = 0x3, + EC_CODEC_WOV_DISABLE = 0x4, + EC_CODEC_WOV_READ_AUDIO = 0x5, + EC_CODEC_WOV_READ_AUDIO_SHM = 0x6, + EC_CODEC_WOV_SUBCMD_COUNT, +}; /* - * PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info". + * @hash is SHA256 of the whole language model. + * @total_len indicates the length of whole language model. + * @offset is the cursor from the beginning of the model. + * @buf is the packet buffer. + * @len denotes how many bytes in the buf. */ -struct __ec_align4 mcdp_version { - uint8_t major; - uint8_t minor; - uint16_t build; +struct __ec_align4 ec_param_ec_codec_wov_set_lang { + uint8_t hash[32]; + uint32_t total_len; + uint32_t offset; + uint8_t buf[128]; + uint32_t len; }; -struct __ec_align4 mcdp_info { - uint8_t family[2]; - uint8_t chipid[2]; - struct mcdp_version irom; - struct mcdp_version fw; +struct __ec_align4 ec_param_ec_codec_wov_set_lang_shm { + uint8_t hash[32]; + uint32_t total_len; }; -/* struct mcdp_info field decoding */ -#define MCDP_CHIPID(chipid) ((chipid[0] << 8) | chipid[1]) -#define MCDP_FAMILY(family) ((family[0] << 8) | family[1]) +struct __ec_align4 ec_param_ec_codec_wov { + uint8_t cmd; /* enum ec_codec_wov_subcmd */ + uint8_t reserved[3]; -/* Get/Set USB-PD Alternate mode info */ -#define EC_CMD_USB_PD_GET_AMODE 0x0116 -struct __ec_align_size1 ec_params_usb_pd_get_mode_request { - uint16_t svid_idx; /* SVID index to get */ - uint8_t port; /* port */ + union { + struct ec_param_ec_codec_wov_set_lang set_lang_param; + struct ec_param_ec_codec_wov_set_lang_shm set_lang_shm_param; + }; }; -struct __ec_align4 ec_params_usb_pd_get_mode_response { - uint16_t svid; /* SVID */ - uint16_t opos; /* Object Position */ - uint32_t vdo[6]; /* Mode VDOs */ +struct __ec_align4 ec_response_ec_codec_wov_get_lang { + uint8_t hash[32]; }; -#define EC_CMD_USB_PD_SET_AMODE 0x0117 - -enum pd_mode_cmd { - PD_EXIT_MODE = 0, - PD_ENTER_MODE = 1, - /* Not a command. Do NOT remove. */ - PD_MODE_CMD_COUNT, +struct __ec_align4 ec_response_ec_codec_wov_read_audio { + uint8_t buf[128]; + uint32_t len; }; -struct __ec_align4 ec_params_usb_pd_set_mode_request { - uint32_t cmd; /* enum pd_mode_cmd */ - uint16_t svid; /* SVID to set */ - uint8_t opos; /* Object Position */ - uint8_t port; /* port */ +struct __ec_align4 ec_response_ec_codec_wov_read_audio_shm { + uint32_t offset; + uint32_t len; }; -/* Ask the PD MCU to record a log of a requested type */ -#define EC_CMD_PD_WRITE_LOG_ENTRY 0x0118 - -struct __ec_align1 ec_params_pd_write_log_entry { - uint8_t type; /* event type : see PD_EVENT_xx above */ - uint8_t port; /* port#, or 0 for events unrelated to a given port */ -}; +/*****************************************************************************/ +/* Commands for PoE PSE controller */ -/* Control USB-PD chip */ -#define EC_CMD_PD_CONTROL 0x0119 +#define EC_CMD_PSE 0x00C0 -enum ec_pd_control_cmd { - PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */ - PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */ - PD_RESET, /* Force reset the PD chip */ - PD_CONTROL_DISABLE /* Disable further calls to this command */ +enum ec_pse_subcmd { + EC_PSE_STATUS = 0x0, + EC_PSE_ENABLE = 0x1, + EC_PSE_DISABLE = 0x2, + EC_PSE_SUBCMD_COUNT, }; -struct __ec_align1 ec_params_pd_control { - uint8_t chip; /* chip id (should be 0) */ - uint8_t subcmd; +struct __ec_align1 ec_params_pse { + uint8_t cmd; /* enum ec_pse_subcmd */ + uint8_t port; /* PSE port */ }; -/* Get info about USB-C SS muxes */ -#define EC_CMD_USB_PD_MUX_INFO 0x011A - -struct __ec_align1 ec_params_usb_pd_mux_info { - uint8_t port; /* USB-C port number */ +enum ec_pse_status { + EC_PSE_STATUS_DISABLED = 0x0, + EC_PSE_STATUS_ENABLED = 0x1, + EC_PSE_STATUS_POWERED = 0x2, }; -/* Flags representing mux state */ -#define USB_PD_MUX_USB_ENABLED (1 << 0) -#define USB_PD_MUX_DP_ENABLED (1 << 1) -#define USB_PD_MUX_POLARITY_INVERTED (1 << 2) -#define USB_PD_MUX_HPD_IRQ (1 << 3) - -struct __ec_align1 ec_response_usb_pd_mux_info { - uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ +struct __ec_align1 ec_response_pse_status { + uint8_t status; /* enum ec_pse_status */ }; -#define EC_CMD_PD_CHIP_INFO 0x011B +/*****************************************************************************/ +/* System commands */ -struct __ec_align1 ec_params_pd_chip_info { - uint8_t port; /* USB-C port number */ - uint8_t renew; /* Force renewal */ -}; +/* + * TODO(crosbug.com/p/23747): This is a confusing name, since it doesn't + * necessarily reboot the EC. Rename to "image" or something similar? + */ +#define EC_CMD_REBOOT_EC 0x00D2 -struct __ec_align2 ec_response_pd_chip_info { - uint16_t vendor_id; - uint16_t product_id; - uint16_t device_id; - union { - uint8_t fw_version_string[8]; - uint64_t fw_version_number; - }; +/* Command */ +enum ec_reboot_cmd { + EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */ + EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */ + EC_REBOOT_JUMP_RW = 2, /* Jump to active RW without rebooting */ + /* (command 3 was jump to RW-B) */ + EC_REBOOT_COLD = 4, /* Cold-reboot */ + EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ + EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ + /* + * DEPRECATED: Hibernate EC and clears AP_IDLE flag. + * Use EC_REBOOT_HIBERNATE and EC_REBOOT_FLAG_CLEAR_AP_IDLE, instead. + */ + EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, + EC_REBOOT_COLD_AP_OFF = 8, /* Cold-reboot and don't boot AP */ + EC_REBOOT_NO_OP = 9, /* Do nothing but apply the flags. */ }; -/* Run RW signature verification and get status */ -#define EC_CMD_RWSIG_CHECK_STATUS 0x011C - -struct __ec_align4 ec_response_rwsig_check_status { - uint32_t status; -}; +/* Flags for ec_params_reboot_ec.reboot_flags */ +#define EC_REBOOT_FLAG_IMMEDIATE 0 /* Trigger Cold Reset */ +#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */ +#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */ +#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */ +#define EC_REBOOT_FLAG_CLEAR_AP_IDLE BIT(3) /* Clear AP_IDLE flag */ -/* For controlling RWSIG task */ -#define EC_CMD_RWSIG_ACTION 0x011D +struct ec_params_reboot_ec { + uint8_t cmd; /* enum ec_reboot_cmd */ + uint8_t flags; /* See EC_REBOOT_FLAG_* */ +} __ec_align1; -enum rwsig_action { - RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */ - RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */ -}; +/* + * Get information on last EC panic. + * + * Returns variable-length platform-dependent panic information. See panic.h + * for details. + */ +#define EC_CMD_GET_PANIC_INFO 0x00D3 -struct __ec_align4 ec_params_rwsig_action { - uint32_t action; -}; +struct ec_params_get_panic_info_v1 { + /* Do not modify PANIC_DATA_FLAG_OLD_HOSTCMD when reading panic info */ + uint8_t preserve_old_hostcmd_flag; +} __ec_align1; -/* Run verification on a slot */ -#define EC_CMD_EFS_VERIFY 0x011E +struct ec_params_get_panic_info_v2 { + /* Do not modify PANIC_DATA_FLAG_OLD_HOSTCMD when reading panic info */ + uint8_t preserve_old_hostcmd_flag; -struct __ec_align1 ec_params_efs_verify { - uint8_t region; /* enum ec_flash_region */ -}; + /* Read panic_data struct from this offset. + * Signal end of data with empty success. + */ + uint16_t read_offset; +} __ec_align1; + +/*****************************************************************************/ +/* + * Special commands + * + * These do not follow the normal rules for commands. See each command for + * details. + */ + +/* + * Reboot NOW + * + * This command will work even when the EC LPC interface is busy, because the + * reboot command is processed at interrupt level. Note that when the EC + * reboots, the host will reboot too, so there is no response to this command. + * + * Use EC_CMD_REBOOT_EC to reboot the EC more politely. + */ +#define EC_CMD_REBOOT 0x00D1 /* Think "die" */ + +/* + * Resend last response (not supported on LPC). + * + * Returns EC_RES_UNAVAILABLE if there is no response available - for example, + * there was no previous command, or the previous command's response was too + * big to save. + */ +#define EC_CMD_RESEND_RESPONSE 0x00DB + +/* + * This header byte on a command indicate version 0. Any header byte less + * than this means that we are talking to an old EC which doesn't support + * versioning. In that case, we assume version 0. + * + * Header bytes greater than this indicate a later version. For example, + * EC_CMD_VERSION0 + 1 means we are using version 1. + * + * The old EC interface must not use commands 0xdc or higher. + */ +#define EC_CMD_VERSION0 0x00DC + +/* + * Memory Dump Commands + * + * Since the HOSTCMD response size is limited, depending on the + * protocol, retrieving a memory dump is split into 3 commands. + * + * 1. EC_CMD_MEMORY_DUMP_GET_METADATA returns the number of memory dump entries, + * and the total dump size. + * 2. EC_CMD_MEMORY_DUMP_GET_ENTRY_INFO returns the address and size for a given + * memory dump entry index. + * 3. EC_CMD_MEMORY_DUMP_READ_MEMORY returns the actual memory at a given + * address. The address and size must be within the bounds of the given + * memory dump entry index. Each response is limited to the max response size + * of the host protocol, so this may need to be called repeatedly to retrieve + * the entire memory dump entry. + * + * Memory entries may overlap and may be out of order. + * The host should check for overlaps to optimize transfer rate. + */ +#define EC_CMD_MEMORY_DUMP_GET_METADATA 0x00DD +struct ec_response_memory_dump_get_metadata { + uint16_t memory_dump_entry_count; + uint32_t memory_dump_total_size; +} __ec_align4; + +#define EC_CMD_MEMORY_DUMP_GET_ENTRY_INFO 0x00DE +struct ec_params_memory_dump_get_entry_info { + uint16_t memory_dump_entry_index; +} __ec_align4; + +struct ec_response_memory_dump_get_entry_info { + uint32_t address; + uint32_t size; +} __ec_align4; + +#define EC_CMD_MEMORY_DUMP_READ_MEMORY 0x00DF + +struct ec_params_memory_dump_read_memory { + uint16_t memory_dump_entry_index; + uint32_t address; + uint32_t size; +} __ec_align4; + +#define EC_CMD_PANIC_LOG_INFO 0x00E0 + +/* + * Parameters for configuring the panic log. + * Freeze and unfreeze are mutually exclusive. + */ +struct ec_params_panic_log_info { + /* Reset panic log */ + uint8_t reset; + /* Freeze panic log */ + uint8_t freeze; + /* Unfreeze panic log */ + uint8_t unfreeze; +} __ec_align1; + +/* + * Returns the panic log info before applying the configuration + * in ec_params_panic_log_info. + */ +struct ec_response_panic_log_info { + uint32_t version; + uint32_t capacity; + uint32_t length; + uint8_t valid; + uint8_t frozen; +} __ec_align4; + +#define EC_CMD_PANIC_LOG_READ 0x00E1 + +/* + * Read from panic log at given byte offset. Will read up to the end of the + * panic log or response max. Use EC_CMD_PANIC_LOG_INFO command to freeze + * the log and get the length before reading. + */ +struct ec_params_panic_log_read { + uint32_t offset; +} __ec_align4; + +/* + * EC_CMD_MEMORY_DUMP_READ_MEMORY response buffer is written directly into + * host_cmd_handler_args.response and host_cmd_handler_args.response_size. + */ + +/* + * Enter bootloader mode + * + * This command requests EC to enter bootloader mode. + */ +#define EC_CMD_ENTER_BOOTLOADER 0x00E2 + +struct ec_params_enter_bootloader { + /* Mode to enter bootloader. Chip specific value. Can be unused. */ + uint8_t mode; +} __ec_align1; + +#define EC_CMD_HOSTCMD_WATCHDOG_INFO 0x00E3 + +struct ec_params_hostcmd_watchdog_info { + uint8_t reset_stats; +} __ec_align1; + +struct ec_response_hostcmd_watchdog_info { + /* Static watchdog info */ + int32_t watchdog_period_ms; + int32_t watchdog_warning_period_ms; + int32_t watchdog_reload_period_nominal_ms; + /* Dynamic watchdog stats */ + int32_t watchdog_reload_period_max_ms; + int64_t watchdog_reload_period_max_ts_ms; + uint32_t watchdog_reload_count; + int64_t watchdog_stats_elapsed_ms; +} __ec_align4; + +/*****************************************************************************/ +/* + * PD commands + * + * These commands are for PD MCU communication. + */ + +/* EC to PD MCU exchange status command */ +#define EC_CMD_PD_EXCHANGE_STATUS 0x0100 +#define EC_VER_PD_EXCHANGE_STATUS 2 + +enum pd_charge_state { + /* Don't change charge state */ + PD_CHARGE_NO_CHANGE = 0, + + /* No charging allowed */ + PD_CHARGE_NONE, + + /* 5V charging only */ + PD_CHARGE_5V, + + /* Charge at max voltage */ + PD_CHARGE_MAX, +}; + +/* Status of EC being sent to PD */ +#define EC_STATUS_HIBERNATING BIT(0) + +struct ec_params_pd_status { + /* EC status */ + uint8_t status; + + /* battery state of charge */ + int8_t batt_soc; + + /* charging state (from enum pd_charge_state) */ + uint8_t charge_state; +} __ec_align1; + +/* Status of PD being sent back to EC */ +#define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */ +#define PD_STATUS_IN_RW BIT(1) /* Running RW image */ +#define PD_STATUS_JUMPED_TO_IMAGE BIT(2) /* Current image was jumped to */ +#define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */ +#define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */ +#define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */ +#define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */ +#define PD_STATUS_EC_INT_ACTIVE \ + (PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_1 | PD_STATUS_HOST_EVENT) +struct ec_response_pd_status { + /* input current limit */ + uint32_t curr_lim_ma; + + /* PD MCU status */ + uint16_t status; + + /* active charging port */ + int8_t active_charge_port; +} __ec_align_size1; + +/* AP to PD MCU host event status command, cleared on read */ +#define EC_CMD_PD_HOST_EVENT_STATUS 0x0104 + +/* PD MCU host event status bits */ +#define PD_EVENT_UPDATE_DEVICE BIT(0) +#define PD_EVENT_POWER_CHANGE BIT(1) +#define PD_EVENT_IDENTITY_RECEIVED BIT(2) +#define PD_EVENT_DATA_SWAP BIT(3) +#define PD_EVENT_TYPEC BIT(4) +#define PD_EVENT_PPM BIT(5) +#define PD_EVENT_INIT BIT(6) + +struct ec_response_host_event_status { + uint32_t status; /* PD MCU host event status */ +} __ec_align4; + +/* + * Set USB type-C port role and muxes + * + * Deprecated in favor of TYPEC_STATUS and TYPEC_CONTROL commands. + * + * TODO(b/169771803): TCPMv2: Remove EC_CMD_USB_PD_CONTROL + */ +#define EC_CMD_USB_PD_CONTROL 0x0101 + +enum usb_pd_control_role { + USB_PD_CTRL_ROLE_NO_CHANGE = 0, + USB_PD_CTRL_ROLE_TOGGLE_ON = 1, /* == AUTO */ + USB_PD_CTRL_ROLE_TOGGLE_OFF = 2, + USB_PD_CTRL_ROLE_FORCE_SINK = 3, + USB_PD_CTRL_ROLE_FORCE_SOURCE = 4, + USB_PD_CTRL_ROLE_FREEZE = 5, + USB_PD_CTRL_ROLE_COUNT, +}; + +enum usb_pd_control_mux { + USB_PD_CTRL_MUX_NO_CHANGE = 0, + USB_PD_CTRL_MUX_NONE = 1, + USB_PD_CTRL_MUX_USB = 2, + USB_PD_CTRL_MUX_DP = 3, + USB_PD_CTRL_MUX_DOCK = 4, + USB_PD_CTRL_MUX_AUTO = 5, + USB_PD_CTRL_MUX_COUNT, +}; + +enum usb_pd_control_swap { + USB_PD_CTRL_SWAP_NONE = 0, + USB_PD_CTRL_SWAP_DATA = 1, + USB_PD_CTRL_SWAP_POWER = 2, + USB_PD_CTRL_SWAP_VCONN = 3, + USB_PD_CTRL_SWAP_COUNT, +}; + +struct ec_params_usb_pd_control { + uint8_t port; + uint8_t role; + uint8_t mux; + uint8_t swap; +} __ec_align1; + +#define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */ +#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */ +#define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2) /* Partner is PD capable */ + +#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */ +#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */ +#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */ +#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */ +#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */ +#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */ +/* Partner unconstrained power */ +#define PD_CTRL_RESP_ROLE_UNCONSTRAINED BIT(6) + +struct ec_response_usb_pd_control { + uint8_t enabled; + uint8_t role; + uint8_t polarity; + uint8_t state; +} __ec_align1; + +struct ec_response_usb_pd_control_v1 { + uint8_t enabled; + uint8_t role; + uint8_t polarity; + char state[32]; +} __ec_align1; + +/* Possible port partner connections based on CC line states */ +enum pd_cc_states { + PD_CC_NONE = 0, /* No port partner attached */ + + /* From DFP perspective */ + PD_CC_UFP_NONE = 1, /* No UFP accessory connected */ + PD_CC_UFP_AUDIO_ACC = 2, /* UFP Audio accessory connected */ + PD_CC_UFP_DEBUG_ACC = 3, /* UFP Debug accessory connected */ + PD_CC_UFP_ATTACHED = 4, /* Plain UFP attached */ + + /* From UFP perspective */ + PD_CC_DFP_ATTACHED = 5, /* Plain DFP attached */ + PD_CC_DFP_DEBUG_ACC = 6, /* DFP debug accessory connected */ +}; + +/* Active/Passive Cable */ +#define USB_PD_CTRL_ACTIVE_CABLE BIT(0) +/* Optical/Non-optical cable */ +#define USB_PD_CTRL_OPTICAL_CABLE BIT(1) +/* 3rd Gen TBT device (or AMA)/2nd gen tbt Adapter */ +#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2) +/* Active Link Uni-Direction */ +#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) +/* Retimer/Redriver cable */ +#define USB_PD_CTRL_RETIMER_CABLE BIT(4) + +struct ec_response_usb_pd_control_v2 { + uint8_t enabled; + uint8_t role; + uint8_t polarity; + char state[32]; + uint8_t cc_state; /* enum pd_cc_states representing cc state */ + uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ + uint8_t reserved; /* Reserved for future use */ + uint8_t control_flags; /* USB_PD_CTRL_*flags */ + uint8_t cable_speed; /* TBT_SS_* cable speed */ + uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ +} __ec_align1; + +#define EC_CMD_USB_PD_PORTS 0x0102 + +/* Maximum number of PD ports on a device, num_ports will be <= this */ +#define EC_USB_PD_MAX_PORTS 8 + +struct ec_response_usb_pd_ports { + uint8_t num_ports; +} __ec_align1; + +#define EC_CMD_USB_PD_POWER_INFO 0x0103 + +#define PD_POWER_CHARGING_PORT 0xff +struct ec_params_usb_pd_power_info { + uint8_t port; +} __ec_align1; + +enum usb_chg_type { + USB_CHG_TYPE_NONE, + USB_CHG_TYPE_PD, + USB_CHG_TYPE_C, + USB_CHG_TYPE_PROPRIETARY, + USB_CHG_TYPE_BC12_DCP, + USB_CHG_TYPE_BC12_CDP, + USB_CHG_TYPE_BC12_SDP, + USB_CHG_TYPE_OTHER, + USB_CHG_TYPE_VBUS, + USB_CHG_TYPE_UNKNOWN, + USB_CHG_TYPE_DEDICATED, +}; +enum usb_power_roles { + USB_PD_PORT_POWER_DISCONNECTED, + USB_PD_PORT_POWER_SOURCE, + USB_PD_PORT_POWER_SINK, + USB_PD_PORT_POWER_SINK_NOT_CHARGING, +}; + +struct usb_chg_measures { + uint16_t voltage_max; + uint16_t voltage_now; + uint16_t current_max; + uint16_t current_lim; +} __ec_align2; + +struct ec_response_usb_pd_power_info { + uint8_t role; + uint8_t type; + uint8_t dualrole; + uint8_t reserved1; + struct usb_chg_measures meas; + uint32_t max_power; +} __ec_align4; + +/* + * This command will return the number of USB PD charge port + the number + * of dedicated port present. + * EC_CMD_USB_PD_PORTS does NOT include the dedicated ports + */ +#define EC_CMD_CHARGE_PORT_COUNT 0x0105 +struct ec_response_charge_port_count { + uint8_t port_count; +} __ec_align1; + +/* + * This command enable/disable dynamic PDO selection. + */ +#define EC_CMD_USB_PD_DPS_CONTROL 0x0106 + +struct ec_params_usb_pd_dps_control { + uint8_t enable; +} __ec_align1; + +/* + * This command return the status of dynamic PDO selection. + */ +#define EC_CMD_USB_PD_DPS_STATUS 0x0107 + +struct ec_response_usb_pd_dps_status { + int32_t is_enabled; + int32_t port; + int32_t requested_voltage; + int32_t requested_current; + int32_t input_power; + int32_t input_voltage; + int32_t input_current; + int32_t efficient_voltage; + int32_t battery_voltage; + int32_t max_voltage; +} __ec_align4; + +/* Write USB-PD device FW */ +#define EC_CMD_USB_PD_FW_UPDATE 0x0110 + +enum usb_pd_fw_update_cmds { + USB_PD_FW_REBOOT, + USB_PD_FW_FLASH_ERASE, + USB_PD_FW_FLASH_WRITE, + USB_PD_FW_ERASE_SIG, +}; + +struct ec_params_usb_pd_fw_update { + uint16_t dev_id; + uint8_t cmd; + uint8_t port; + + /* Size to write in bytes */ + uint32_t size; + + /* Followed by data to write */ +} __ec_align4; + +/* Write USB-PD Accessory RW_HASH table entry */ +#define EC_CMD_USB_PD_RW_HASH_ENTRY 0x0111 +/* RW hash is first 20 bytes of SHA-256 of RW section */ +#define PD_RW_HASH_SIZE 20 +struct ec_params_usb_pd_rw_hash_entry { + uint16_t dev_id; + uint8_t dev_rw_hash[PD_RW_HASH_SIZE]; + + /* + * Reserved for alignment of current_image + * TODO(rspangler) but it's not aligned! + * Should have been reserved[2]. + */ + uint8_t reserved; + + /* One of ec_image */ + uint32_t current_image; +} __ec_align1; + +/* Read USB-PD Accessory info */ +#define EC_CMD_USB_PD_DEV_INFO 0x0112 + +struct ec_params_usb_pd_info_request { + uint8_t port; +} __ec_align1; + +/* Read USB-PD Device discovery info */ +#define EC_CMD_USB_PD_DISCOVERY 0x0113 +struct ec_params_usb_pd_discovery_entry { + uint16_t vid; /* USB-IF VID */ + uint16_t pid; /* USB-IF PID */ + uint8_t ptype; /* product type (hub,periph,cable,ama) */ +} __ec_align_size1; + +/* Override default charge behavior */ +#define EC_CMD_PD_CHARGE_PORT_OVERRIDE 0x0114 + +/* Negative port parameters have special meaning */ +enum usb_pd_override_ports { + /* + * DONT_CHARGE is for all ports. Thus it's persistent across plug-in + * or plug-out. + */ + OVERRIDE_DONT_CHARGE = -2, + OVERRIDE_OFF = -1, + /* [0, CONFIG_USB_PD_PORT_MAX_COUNT): Port# */ +}; + +struct ec_params_charge_port_override { + int16_t override_port; /* Override port# */ +} __ec_align2; + +/* + * Read (and delete) one entry of PD event log. + * TODO(crbug.com/751742): Make this host command more generic to accommodate + * future non-PD logs that use the same internal EC event_log. + */ +#define EC_CMD_PD_GET_LOG_ENTRY 0x0115 + +struct ec_response_pd_log { + uint32_t timestamp; /* relative timestamp in milliseconds */ + uint8_t type; /* event type : see PD_EVENT_xx below */ + uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */ + uint16_t data; /* type-defined data payload */ + /* optional additional data payload: 0..16 bytes */ + uint8_t payload[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; + +/* The timestamp is the microsecond counter shifted to get about a ms. */ +#define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */ + +#define PD_LOG_SIZE_MASK 0x1f +#define PD_LOG_PORT_MASK 0xe0 +#define PD_LOG_PORT_SHIFT 5 +#define PD_LOG_PORT_SIZE(port, size) \ + (((port) << PD_LOG_PORT_SHIFT) | ((size) & PD_LOG_SIZE_MASK)) +#define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT) +#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK) + +/* PD event log : entry types */ +/* PD MCU events */ +#define PD_EVENT_MCU_BASE 0x00 +#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE + 0) +#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE + 1) +/* Reserved for custom board event */ +#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE + 2) +/* PD generic accessory events */ +#define PD_EVENT_ACC_BASE 0x20 +#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE + 0) +#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE + 1) +/* PD power supply events */ +#define PD_EVENT_PS_BASE 0x40 +#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE + 0) +/* PD video dongles events */ +#define PD_EVENT_VIDEO_BASE 0x60 +#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE + 0) +#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE + 1) +/* Returned in the "type" field, when there is no entry available */ +#define PD_EVENT_NO_ENTRY 0xff + +/* + * PD_EVENT_MCU_CHARGE event definition : + * the payload is "struct usb_chg_measures" + * the data field contains the port state flags as defined below : + */ +/* Port partner is a dual role device */ +#define CHARGE_FLAGS_DUAL_ROLE BIT(15) +/* Port is the pending override port */ +#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14) +/* Port is the override port */ +#define CHARGE_FLAGS_OVERRIDE BIT(13) +/* Charger type */ +#define CHARGE_FLAGS_TYPE_SHIFT 3 +#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT) +/* Power delivery role */ +#define CHARGE_FLAGS_ROLE_MASK (7 << 0) + +/* + * PD_EVENT_PS_FAULT data field flags definition : + */ +#define PS_FAULT_OCP 1 +#define PS_FAULT_FAST_OCP 2 +#define PS_FAULT_OVP 3 +#define PS_FAULT_DISCH 4 + +/* + * PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info". + */ +struct mcdp_version { + uint8_t major; + uint8_t minor; + uint16_t build; +} __ec_align4; + +struct mcdp_info { + uint8_t family[2]; + uint8_t chipid[2]; + struct mcdp_version irom; + struct mcdp_version fw; +} __ec_align4; + +/* struct mcdp_info field decoding */ +#define MCDP_CHIPID(chipid) ((chipid[0] << 8) | chipid[1]) +#define MCDP_FAMILY(family) ((family[0] << 8) | family[1]) + +/* Get/Set USB-PD Alternate mode info */ +#define EC_CMD_USB_PD_GET_AMODE 0x0116 +struct ec_params_usb_pd_get_mode_request { + uint16_t svid_idx; /* SVID index to get */ + uint8_t port; /* port */ +} __ec_align_size1; + +#define VDO_MAX_SIZE 7 +/* Max number of VDM data objects without VDM header */ +#define VDO_MAX_OBJECTS (VDO_MAX_SIZE - 1) + +struct ec_params_usb_pd_get_mode_response { + uint16_t svid; /* SVID */ + uint16_t opos; /* Object Position */ + uint32_t vdo[VDO_MAX_OBJECTS]; /* Mode VDOs */ +} __ec_align4; + +#define EC_CMD_USB_PD_SET_AMODE 0x0117 + +enum pd_mode_cmd { + PD_EXIT_MODE = 0, + PD_ENTER_MODE = 1, + /* Not a command. Do NOT remove. */ + PD_MODE_CMD_COUNT, +}; + +struct ec_params_usb_pd_set_mode_request { + uint32_t cmd; /* enum pd_mode_cmd */ + uint16_t svid; /* SVID to set */ + uint8_t opos; /* Object Position */ + uint8_t port; /* port */ +} __ec_align4; + +/* Ask the PD MCU to record a log of a requested type */ +#define EC_CMD_PD_WRITE_LOG_ENTRY 0x0118 + +struct ec_params_pd_write_log_entry { + uint8_t type; /* event type : see PD_EVENT_xx above */ + uint8_t port; /* port#, or 0 for events unrelated to a given port */ +} __ec_align1; + +/* Control USB-PD chip */ +#define EC_CMD_PD_CONTROL 0x0119 + +enum ec_pd_control_cmd { + PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */ + PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */ + PD_RESET, /* Force reset the PD chip */ + PD_CONTROL_DISABLE, /* Disable further calls to this command */ + PD_CHIP_ON, /* Power on the PD chip */ +}; + +struct ec_params_pd_control { + uint8_t chip; /* chip id */ + uint8_t subcmd; +} __ec_align1; + +/* Get info about USB-C SS muxes */ +#define EC_CMD_USB_PD_MUX_INFO 0x011A + +struct ec_params_usb_pd_mux_info { + uint8_t port; /* USB-C port number */ +} __ec_align1; + +/* Flags representing mux state */ +#define USB_PD_MUX_NONE 0 /* Open switch */ +#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ +#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ +#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ +#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ +#define USB_PD_MUX_HPD_IRQ_DEASSERTED 0 /* HPD IRQ is deasserted */ +#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ +#define USB_PD_MUX_HPD_LVL_DEASSERTED 0 /* HPD level is deasserted */ +#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */ +#define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */ +#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */ + +/* USB-C Dock connected */ +#define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED) + +struct ec_response_usb_pd_mux_info { + uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ +} __ec_align1; + +#define EC_CMD_PD_CHIP_INFO 0x011B + +struct ec_params_pd_chip_info { + uint8_t port; /* USB-C port number */ + /* + * Fetch the live chip info or hard-coded + cached chip info + * 0: hardcoded value for VID/PID, cached value for FW version + * 1: live chip value for VID/PID/FW Version + */ + uint8_t live; +} __ec_align1; + +struct ec_response_pd_chip_info { + uint16_t vendor_id; + uint16_t product_id; + uint16_t device_id; + union { + uint8_t fw_version_string[8]; + uint64_t fw_version_number; + } __ec_align2; +} __ec_align2; + +struct ec_response_pd_chip_info_v1 { + uint16_t vendor_id; + uint16_t product_id; + uint16_t device_id; + union { + uint8_t fw_version_string[8]; + uint64_t fw_version_number; + } __ec_align2; + union { + uint8_t min_req_fw_version_string[8]; + uint64_t min_req_fw_version_number; + } __ec_align2; +} __ec_align2; + +/** Indicates the chip should NOT receive a firmware update, if set. This is + * useful when multiple ports are serviced by a single chip, to avoid + * performing redundant updates. The host command implementation shall ensure + * only one port out of each physical chip has FW updates active. + */ +#define USB_PD_CHIP_INFO_FWUP_FLAG_NO_UPDATE BIT(0) + +/** Maximum length of a project name embedded in a PDC FW image. This length + * does NOT include a NUL-terminator. + */ +#define USB_PD_CHIP_INFO_PROJECT_NAME_LEN 12 + +struct ec_response_pd_chip_info_v2 { + uint16_t vendor_id; + uint16_t product_id; + uint16_t device_id; + union { + uint8_t fw_version_string[8]; + uint64_t fw_version_number; + } __ec_align2; + union { + uint8_t min_req_fw_version_string[8]; + uint64_t min_req_fw_version_number; + } __ec_align2; + /** Flag to control the FW update process for this chip. */ + uint16_t fw_update_flags; + /** Project name string associated with the chip's FW. Add an extra + * byte for a NUL-terminator. + */ + char fw_name_str[USB_PD_CHIP_INFO_PROJECT_NAME_LEN + 1]; +} __ec_align2; + +/** Maximum length of a driver/chip name reported in the pd_chip_info + * response + */ +#define USB_PD_CHIP_INFO_DRIVER_NAME_LEN 24 + +struct ec_response_pd_chip_info_v3 { + uint16_t vendor_id; + uint16_t product_id; + uint16_t device_id; + union { + uint8_t fw_version_string[8]; + uint64_t fw_version_number; + } __ec_align2; + union { + uint8_t min_req_fw_version_string[8]; + uint64_t min_req_fw_version_number; + } __ec_align2; + /** Flag to control the FW update process for this chip. */ + uint16_t fw_update_flags; + /** Project name string associated with the chip's FW. Add an extra + * byte for a NUL-terminator. + */ + char fw_name_str[USB_PD_CHIP_INFO_PROJECT_NAME_LEN + 1]; + /** Driver/chip string, plus room for a NUL-terminator */ + char driver_name[USB_PD_CHIP_INFO_DRIVER_NAME_LEN + 1]; +} __ec_align2; + +/* Run RW signature verification and get status */ +#define EC_CMD_RWSIG_CHECK_STATUS 0x011C + +struct ec_response_rwsig_check_status { + uint32_t status; +} __ec_align4; + +/* For controlling RWSIG task */ +#define EC_CMD_RWSIG_ACTION 0x011D + +enum rwsig_action { + RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */ + RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */ +}; + +struct ec_params_rwsig_action { + uint32_t action; +} __ec_align4; + +/* Run verification on a slot */ +#define EC_CMD_EFS_VERIFY 0x011E + +struct ec_params_efs_verify { + uint8_t region; /* enum ec_flash_region */ +} __ec_align1; + +/* + * Retrieve info from Cros Board Info store. Response is based on the data + * type. Integers return a uint32. Strings return a string, using the response + * size to determine how big it is. + */ +#define EC_CMD_GET_CROS_BOARD_INFO 0x011F +/* + * Write info into Cros Board Info on EEPROM. Write fails if the board has + * hardware write-protect enabled. + */ +#define EC_CMD_SET_CROS_BOARD_INFO 0x0120 + +enum cbi_data_tag { + CBI_TAG_BOARD_VERSION = 0, /* uint32_t or smaller */ + CBI_TAG_OEM_ID = 1, /* uint32_t or smaller */ + CBI_TAG_SKU_ID = 2, /* uint32_t or smaller */ + CBI_TAG_DRAM_PART_NUM = 3, /* variable length ascii, nul terminated. */ + CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */ + CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ + CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */ + CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */ + /* Second Source Factory Cache */ + CBI_TAG_SSFC = 8, /* uint32_t bit field */ + CBI_TAG_REWORK_ID = 9, /* uint64_t or smaller */ + CBI_TAG_FACTORY_CALIBRATION_DATA = 10, /* Deprecated */ + CBI_TAG_COMMON_CONTROL = 11, /* Deprecated */ + /* struct board_batt_params */ + CBI_TAG_BATTERY_CONFIG = 12, + /* CBI_TAG_BATTERY_CONFIG_1 ~ 15 will use 13 ~ 27. */ + CBI_TAG_BATTERY_CONFIG_15 = 27, + + /* CBI_TAG_PROVISION_MATRIX_VERSION + * Version of the current provision matrix + */ + CBI_TAG_PROVISION_MATRIX_VERSION = 28, /* uint32_t bit field */ + + /* Unified Firmware and Second-source Config: + * A fixed-size array of 4 uint32_t values. + */ + CBI_TAG_UFSC = 29, + + /* Last entry */ + CBI_TAG_COUNT, +}; + +#define CBI_UFSC_DATA_COUNT 4 + +/* Unified Firmware and Second-source Config (UFSC) data structure */ +struct cbi_ufsc { + uint32_t data[CBI_UFSC_DATA_COUNT]; +}; + +/* + * Flags to control read operation + * + * RELOAD: Invalidate cache and read data from EEPROM. Useful to verify + * write was successful without reboot. + */ +#define CBI_GET_RELOAD BIT(0) + +struct ec_params_get_cbi { + uint32_t tag; /* enum cbi_data_tag */ + uint32_t flag; /* CBI_GET_* */ +} __ec_align4; + +/* + * Flags to control write behavior. + * + * NO_SYNC: Makes EC update data in RAM but skip writing to EEPROM. It's + * useful when writing multiple fields in a row. + * INIT: Need to be set when creating a new CBI from scratch. All fields + * will be initialized to zero first. + */ +#define CBI_SET_NO_SYNC BIT(0) +#define CBI_SET_INIT BIT(1) + +struct ec_params_set_cbi { + uint32_t tag; /* enum cbi_data_tag */ + uint32_t flag; /* CBI_SET_* */ + uint32_t size; /* Data size */ + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; /* For string and raw data */ +} __ec_align1; + +/* + * Retrieve binary from CrOS Board Info primary memory source. + */ +#define EC_CMD_CBI_BIN_READ 0x0504 +/* + * Write binary into CrOS Board Info temporary buffer and then commit it to + * permanent storage once complete. Write fails if the board has hardware + * write-protect enabled. + */ +#define EC_CMD_CBI_BIN_WRITE 0x0505 + +/* + * CBI binary read/write flags + * The default write behavior is to always append any data to the buffer. + * If 'CLEAR' flag is set, buffer is cleared then data is appended. + * If 'WRITE' flag is set, data is appended then buffer is written to memory. + */ +#define EC_CBI_BIN_BUFFER_CLEAR BIT(0) +#define EC_CBI_BIN_BUFFER_WRITE BIT(1) + +struct ec_params_get_cbi_bin { + uint32_t offset; /* Data offset */ + uint32_t size; /* Data size */ +} __ec_align4; + +struct ec_params_set_cbi_bin { + uint32_t offset; /* Data offset */ + uint32_t size; /* Data size */ + uint8_t flags; /* bit field for EC_CBI_BIN_COMMIT_FLAG_* */ + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; /* For string and raw data */ +} __ec_align1; + +/* + * Information about resets of the AP by the EC and the EC's own uptime. + */ +#define EC_CMD_GET_UPTIME_INFO 0x0121 + +/* EC reset causes */ +#define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */ +#define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */ +#define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */ +#define EC_RESET_FLAG_POWER_ON BIT(3) /* Power-on reset */ +#define EC_RESET_FLAG_WATCHDOG BIT(4) /* Watchdog timer reset */ +#define EC_RESET_FLAG_SOFT BIT(5) /* Soft reset trigger by core */ +#define EC_RESET_FLAG_HIBERNATE BIT(6) /* Wake from hibernate */ +#define EC_RESET_FLAG_RTC_ALARM BIT(7) /* RTC alarm wake */ +#define EC_RESET_FLAG_WAKE_PIN BIT(8) /* Wake pin triggered wake */ +#define EC_RESET_FLAG_LOW_BATTERY BIT(9) /* Low battery triggered wake */ +#define EC_RESET_FLAG_SYSJUMP BIT(10) /* Jumped directly to this image */ +#define EC_RESET_FLAG_HARD BIT(11) /* Hard reset from software */ +#define EC_RESET_FLAG_AP_OFF BIT(12) /* Do not power on AP */ +/* Some reset flags preserved from previous boot */ +#define EC_RESET_FLAG_PRESERVED BIT(13) +#define EC_RESET_FLAG_USB_RESUME BIT(14) /* USB resume triggered wake */ +#define EC_RESET_FLAG_RDD BIT(15) /* USB Type-C debug cable */ +#define EC_RESET_FLAG_RBOX BIT(16) /* Fixed Reset Functionality */ +#define EC_RESET_FLAG_SECURITY BIT(17) /* Security threat */ +/* AP experienced a watchdog reset */ +#define EC_RESET_FLAG_AP_WATCHDOG BIT(18) +/* Do not select RW in EFS. This enables PD in RO for Chromebox. */ +#define EC_RESET_FLAG_STAY_IN_RO BIT(19) +#define EC_RESET_FLAG_EFS BIT(20) /* Jumped to this image by EFS */ +#define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */ +#define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */ + +/* + * Reason codes used by the AP after a shutdown to figure out why it was reset + * by the EC. These are sent in EC commands. Therefore, to maintain protocol + * compatibility: + * - New entries must be inserted prior to the _COUNT field + * - If an existing entry is no longer in service, it must be replaced with a + * RESERVED entry instead. + * - The semantic meaning of an entry should not change. + * - Do not exceed 2^15 - 1 for reset reasons or 2^16 - 1 for shutdown reasons. + */ +enum chipset_shutdown_reason { + /* + * Beginning of reset reasons. + */ + CHIPSET_RESET_BEGIN = 0, + CHIPSET_RESET_UNKNOWN = CHIPSET_RESET_BEGIN, + /* Custom reason defined by a board.c or baseboard.c file */ + CHIPSET_RESET_BOARD_CUSTOM, + /* Believe that the AP has hung */ + CHIPSET_RESET_HANG_REBOOT, + /* Reset by EC console command */ + CHIPSET_RESET_CONSOLE_CMD, + /* Reset by EC host command */ + CHIPSET_RESET_HOST_CMD, + /* Keyboard module reset key combination */ + CHIPSET_RESET_KB_SYSRESET, + /* Keyboard module warm reboot */ + CHIPSET_RESET_KB_WARM_REBOOT, + /* Debug module warm reboot */ + CHIPSET_RESET_DBG_WARM_REBOOT, + /* I cannot self-terminate. You must lower me into the steel. */ + CHIPSET_RESET_AP_REQ, + /* Reset as side-effect of startup sequence */ + CHIPSET_RESET_INIT, + /* EC detected an AP watchdog event. */ + CHIPSET_RESET_AP_WATCHDOG, + + CHIPSET_RESET_COUNT, /* End of reset reasons. */ + + /* + * Beginning of shutdown reasons. + */ + CHIPSET_SHUTDOWN_BEGIN = BIT(15), + CHIPSET_SHUTDOWN_POWERFAIL = CHIPSET_SHUTDOWN_BEGIN, + /* Forcing a shutdown as part of EC initialization */ + CHIPSET_SHUTDOWN_INIT, + /* Custom reason on a per-board basis. */ + CHIPSET_SHUTDOWN_BOARD_CUSTOM, + /* This is a reason to inhibit startup, not cause shut down. */ + CHIPSET_SHUTDOWN_BATTERY_INHIBIT, + /* A power_wait_signal is being asserted */ + CHIPSET_SHUTDOWN_WAIT, + /* Critical battery level. */ + CHIPSET_SHUTDOWN_BATTERY_CRIT, + /* Because you told me to. */ + CHIPSET_SHUTDOWN_CONSOLE_CMD, + /* Forcing a shutdown to effect entry to G3. */ + CHIPSET_SHUTDOWN_G3, + /* Force shutdown due to over-temperature. */ + CHIPSET_SHUTDOWN_THERMAL, + /* Force a chipset shutdown from the power button through EC */ + CHIPSET_SHUTDOWN_BUTTON, + /* Force a chipset shutdown, because the AP wants to. */ + CHIPSET_SHUTDOWN_HOST_CMD, + + CHIPSET_SHUTDOWN_COUNT, /* End of shutdown reasons. */ +}; + +struct ec_response_uptime_info { + /* + * Number of milliseconds since the last EC boot. Sysjump resets + * typically do not restart the EC's time_since_boot epoch. + * + * WARNING: The EC's sense of time is much less accurate than the AP's + * sense of time, in both phase and frequency. This timebase is similar + * to CLOCK_MONOTONIC_RAW, but with 1% or more frequency error. + */ + uint32_t time_since_ec_boot_ms; + + /* + * Number of times the AP was reset by the EC since the last EC boot. + * Note that the AP may be held in reset by the EC during the initial + * boot sequence, such that the very first AP boot may count as more + * than one here. + */ + uint32_t ap_resets_since_ec_boot; + + /* + * The set of flags which describe the EC's most recent reset. + * See EC_RESET_FLAG_* for details. + */ + uint32_t ec_reset_flags; + + /* Empty log entries have both the cause and timestamp set to zero. */ + struct ap_reset_log_entry { + /* See enum chipset_{reset,shutdown}_reason for details. */ + uint16_t reset_cause; + + /* Reserved for protocol growth. */ + uint16_t reserved; + + /* + * The time of the reset's assertion, in milliseconds since the + * last EC boot, in the same epoch as time_since_ec_boot_ms. + * Set to zero if the log entry is empty. + */ + uint32_t reset_time_ms; + } recent_ap_reset[4]; +} __ec_align4; + +/* + * Add entropy to the device secret (stored in the rollback region). + * + * Depending on the chip, the operation may take a long time (e.g. to erase + * flash), so the commands are asynchronous. + */ +#define EC_CMD_ADD_ENTROPY 0x0122 + +enum add_entropy_action { + /* Add entropy to the current secret. */ + ADD_ENTROPY_ASYNC = 0, + /* + * Add entropy, and also make sure that the previous secret is erased. + * (this can be implemented by adding entropy multiple times until + * all rolback blocks have been overwritten). + */ + ADD_ENTROPY_RESET_ASYNC = 1, + /* Read back result from the previous operation. */ + ADD_ENTROPY_GET_RESULT = 2, +}; + +struct ec_params_rollback_add_entropy { + uint8_t action; +} __ec_align1; + +/* + * Perform a single read of a given ADC channel. + */ +#define EC_CMD_ADC_READ 0x0123 + +struct ec_params_adc_read { + uint8_t adc_channel; +} __ec_align1; + +struct ec_response_adc_read { + int32_t adc_value; +} __ec_align4; + +/* + * Read back rollback info + */ +#define EC_CMD_ROLLBACK_INFO 0x0124 + +struct ec_response_rollback_info { + int32_t id; /* Incrementing number to indicate which region to use. */ + int32_t rollback_min_version; + int32_t rw_rollback_version; +} __ec_align4; + +struct ec_response_rollback_info_v1 { + int32_t id; /* Incrementing number to indicate which region to use. */ + int32_t rollback_min_version; + int32_t rw_rollback_version; + uint8_t is_secret_inited; + uint8_t reserved[3]; +} __ec_align4; + +/* Issue AP reset */ +#define EC_CMD_AP_RESET 0x0125 + +/*****************************************************************************/ +/* Locate peripheral chips + * + * Return values: + * EC_RES_UNAVAILABLE: The chip type is supported but not found on system. + * EC_RES_INVALID_PARAM: The chip type was unrecognized. + * EC_RES_OVERFLOW: The index number exceeded the number of chip instances. + */ +#define EC_CMD_LOCATE_CHIP 0x0126 + +enum ec_chip_type { + EC_CHIP_TYPE_CBI_EEPROM = 0, + EC_CHIP_TYPE_TCPC = 1, + EC_CHIP_TYPE_PDC = 2, + EC_CHIP_TYPE_COUNT, + EC_CHIP_TYPE_MAX = 0xFF, +}; + +enum ec_bus_type { + EC_BUS_TYPE_I2C = 0, + EC_BUS_TYPE_EMBEDDED = 1, + EC_BUS_TYPE_COUNT, + EC_BUS_TYPE_MAX = 0xFF, +}; + +struct ec_i2c_info { + uint16_t port; /* Physical port for device */ + uint16_t addr_flags; /* 7-bit (or 10-bit) address */ +}; + +struct ec_params_locate_chip { + uint8_t type; /* enum ec_chip_type */ + uint8_t index; /* Specifies one instance of chip type */ + /* Used for type specific parameters in future */ + union { + uint16_t reserved; + }; +} __ec_align2; + +struct ec_response_locate_chip { + uint8_t bus_type; /* enum ec_bus_type */ + uint8_t reserved; /* Aligning the following union to 2 bytes */ + union { + struct ec_i2c_info i2c_info; + }; +} __ec_align2; + +/* + * Reboot AP on G3 + * + * This command is used for validation purpose, where the AP needs to be + * returned back to S0 state from G3 state without using the servo to trigger + * wake events. + * - With command version 0: + * AP reboots immediately from G3 + * command usage: ectool reboot_ap_on_g3 && shutdown -h now + * - With command version 1: + * AP reboots after the user specified delay + * command usage: ectool reboot_ap_on_g3 [] && shutdown -h now + */ +#define EC_CMD_REBOOT_AP_ON_G3 0x0127 + +struct ec_params_reboot_ap_on_g3_v1 { + /* configurable delay in seconds in G3 state */ + uint32_t reboot_ap_at_g3_delay; +} __ec_align4; + +/*****************************************************************************/ +/* Get PD port capabilities + * + * Returns the following static *capabilities* of the given port: + * 1) Power role: source, sink, or dual. It is not anticipated that + * future CrOS devices would ever be only a source, so the options are + * sink or dual. + * 2) Try-power role: source, sink, or none (practically speaking, I don't + * believe any CrOS device would support Try.SNK, so this would be source + * or none). + * 3) Data role: dfp, ufp, or dual. This will probably only be DFP or dual + * for CrOS devices. + */ +#define EC_CMD_GET_PD_PORT_CAPS 0x0128 + +enum ec_pd_power_role_caps { + EC_PD_POWER_ROLE_SOURCE = 0, + EC_PD_POWER_ROLE_SINK = 1, + EC_PD_POWER_ROLE_DUAL = 2, +}; + +enum ec_pd_try_power_role_caps { + EC_PD_TRY_POWER_ROLE_NONE = 0, + EC_PD_TRY_POWER_ROLE_SINK = 1, + EC_PD_TRY_POWER_ROLE_SOURCE = 2, +}; + +enum ec_pd_data_role_caps { + EC_PD_DATA_ROLE_DFP = 0, + EC_PD_DATA_ROLE_UFP = 1, + EC_PD_DATA_ROLE_DUAL = 2, +}; + +/* From: power_manager/power_supply_properties.proto */ +enum ec_pd_port_location { + /* The location of the port is unknown, or there's only one port. */ + EC_PD_PORT_LOCATION_UNKNOWN = 0, + + /* + * Various positions on the device. The first word describes the side of + * the device where the port is located while the second clarifies the + * position. For example, LEFT_BACK means the farthest-back port on the + * left side, while BACK_LEFT means the leftmost port on the back of the + * device. + */ + EC_PD_PORT_LOCATION_LEFT = 1, + EC_PD_PORT_LOCATION_RIGHT = 2, + EC_PD_PORT_LOCATION_BACK = 3, + EC_PD_PORT_LOCATION_FRONT = 4, + EC_PD_PORT_LOCATION_LEFT_FRONT = 5, + EC_PD_PORT_LOCATION_LEFT_BACK = 6, + EC_PD_PORT_LOCATION_RIGHT_FRONT = 7, + EC_PD_PORT_LOCATION_RIGHT_BACK = 8, + EC_PD_PORT_LOCATION_BACK_LEFT = 9, + EC_PD_PORT_LOCATION_BACK_RIGHT = 10, +}; + +struct ec_params_get_pd_port_caps { + uint8_t port; /* Which port to interrogate */ +} __ec_align1; + +struct ec_response_get_pd_port_caps { + uint8_t pd_power_role_cap; /* enum ec_pd_power_role_caps */ + uint8_t pd_try_power_role_cap; /* enum ec_pd_try_power_role_caps */ + uint8_t pd_data_role_cap; /* enum ec_pd_data_role_caps */ + uint8_t pd_port_location; /* enum ec_pd_port_location */ +} __ec_align1; + +/*****************************************************************************/ +/* + * Button press simulation + * + * This command is used to simulate a button press. + * Supported commands are vup(volume up) vdown(volume down) & rec(recovery) + * Time duration for which button needs to be pressed is an optional parameter. + * + * NOTE: This is only available on unlocked devices for testing purposes only. + */ +#define EC_CMD_BUTTON 0x0129 + +struct ec_params_button { + /* Button mask aligned to enum keyboard_button_type */ + uint32_t btn_mask; + + /* Duration in milliseconds button needs to be pressed */ + uint32_t press_ms; +} __ec_align1; + +enum keyboard_button_type { + KEYBOARD_BUTTON_POWER = 0, + KEYBOARD_BUTTON_VOLUME_DOWN = 1, + KEYBOARD_BUTTON_VOLUME_UP = 2, + KEYBOARD_BUTTON_RECOVERY = 3, + KEYBOARD_BUTTON_CAPSENSE_1 = 4, + KEYBOARD_BUTTON_CAPSENSE_2 = 5, + KEYBOARD_BUTTON_CAPSENSE_3 = 6, + KEYBOARD_BUTTON_CAPSENSE_4 = 7, + KEYBOARD_BUTTON_CAPSENSE_5 = 8, + KEYBOARD_BUTTON_CAPSENSE_6 = 9, + KEYBOARD_BUTTON_CAPSENSE_7 = 10, + KEYBOARD_BUTTON_CAPSENSE_8 = 11, + + KEYBOARD_BUTTON_COUNT, +}; + +/*****************************************************************************/ +/* + * "Get the Keyboard Config". An EC implementing this command is expected to be + * vivaldi capable, i.e. can send action codes for the top row keys. + * Additionally, capability to send function codes for the same keys is + * optional and acceptable. + * + * Note: If the top row can generate both function and action codes by + * using a dedicated Fn key, it does not matter whether the key sends + * "function" or "action" codes by default. In both cases, the response + * for this command will look the same. + */ +#define EC_CMD_GET_KEYBD_CONFIG 0x012A + +/* Possible values for the top row keys */ +enum action_key { + TK_ABSENT = 0, + TK_BACK = 1, + TK_FORWARD = 2, + TK_REFRESH = 3, + TK_FULLSCREEN = 4, + TK_OVERVIEW = 5, + TK_BRIGHTNESS_DOWN = 6, + TK_BRIGHTNESS_UP = 7, + TK_VOL_MUTE = 8, + TK_VOL_DOWN = 9, + TK_VOL_UP = 10, + TK_SNAPSHOT = 11, + TK_PRIVACY_SCRN_TOGGLE = 12, + TK_KBD_BKLIGHT_DOWN = 13, + TK_KBD_BKLIGHT_UP = 14, + TK_PLAY_PAUSE = 15, + TK_NEXT_TRACK = 16, + TK_PREV_TRACK = 17, + TK_KBD_BKLIGHT_TOGGLE = 18, + TK_MICMUTE = 19, + TK_MENU = 20, + TK_DICTATE = 21, + TK_ACCESSIBILITY = 22, + TK_DONOTDISTURB = 23, + TK_HOME = 24, + + TK_COUNT +}; + +/* + * Max & Min number of top row keys, excluding Esc and Screenlock keys. + * If this needs to change, please create a new version of the command. + */ +#define MAX_TOP_ROW_KEYS 15 +#define MIN_TOP_ROW_KEYS 10 + +/* + * Is the keyboard capable of sending function keys *in addition to* + * action keys. This is possible for e.g. if the keyboard has a + * dedicated Fn key. + */ +#define KEYBD_CAP_FUNCTION_KEYS BIT(0) +/* + * Whether the keyboard has a dedicated numeric keyboard. + */ +#define KEYBD_CAP_NUMERIC_KEYPAD BIT(1) +/* + * Whether the keyboard has a screenlock key. + */ +#define KEYBD_CAP_SCRNLOCK_KEY BIT(2) + +/* + * Whether the keyboard has an assistant key. + */ +#define KEYBD_CAP_ASSISTANT_KEY BIT(3) + +struct ec_response_keybd_config { + /* + * Number of top row keys, excluding Esc and Screenlock. + * If this is 0, all Vivaldi keyboard code is disabled. + * (i.e. does not expose any tables to the kernel). + */ + uint8_t num_top_row_keys; + + /* + * The action keys in the top row, in order from left to right. + * The values are filled from enum action_key. Esc and Screenlock + * keys are not considered part of top row keys. + */ + uint8_t action_keys[MAX_TOP_ROW_KEYS]; + + /* Capability flags */ + uint8_t capabilities; + +} __ec_align1; + +/* + * Configure smart discharge + */ +#define EC_CMD_SMART_DISCHARGE 0x012B + +#define EC_SMART_DISCHARGE_FLAGS_SET BIT(0) + +/* Discharge rates when the system is in cutoff or hibernation. */ +struct discharge_rate { + uint16_t cutoff; /* Discharge rate (uA) in cutoff */ + uint16_t hibern; /* Discharge rate (uA) in hibernation */ +}; + +struct smart_discharge_zone { + /* When the capacity (mAh) goes below this, EC cuts off the battery. */ + int cutoff; + /* When the capacity (mAh) is below this, EC stays up. */ + int stayup; +}; + +struct ec_params_smart_discharge { + uint8_t flags; /* EC_SMART_DISCHARGE_FLAGS_* */ + /* + * Desired hours for the battery to survive before reaching 0%. Set to + * zero to disable smart discharging. That is, the system hibernates as + * soon as the G3 idle timer expires. + */ + uint16_t hours_to_zero; + /* Set both to zero to keep the current rates. */ + struct discharge_rate drate; +}; + +struct ec_response_smart_discharge { + uint16_t hours_to_zero; + struct discharge_rate drate; + struct smart_discharge_zone dzone; +}; + +/*****************************************************************************/ +/* Voltage regulator controls */ + +/* + * Get basic info of voltage regulator for given index. + * + * Returns the regulator name and supported voltage list in mV. + */ +#define EC_CMD_REGULATOR_GET_INFO 0x012C + +/* Maximum length of regulator name */ +#define EC_REGULATOR_NAME_MAX_LEN 16 + +/* Maximum length of the supported voltage list. */ +#define EC_REGULATOR_VOLTAGE_MAX_COUNT 16 + +struct ec_params_regulator_get_info { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_get_info { + char name[EC_REGULATOR_NAME_MAX_LEN]; + uint16_t num_voltages; + uint16_t voltages_mv[EC_REGULATOR_VOLTAGE_MAX_COUNT]; +} __ec_align2; + +/* + * Configure the regulator as enabled / disabled. + */ +#define EC_CMD_REGULATOR_ENABLE 0x012D + +struct ec_params_regulator_enable { + uint32_t index; + uint8_t enable; +} __ec_align4; + +/* + * Query if the regulator is enabled. + * + * Returns 1 if the regulator is enabled, 0 if not. + */ +#define EC_CMD_REGULATOR_IS_ENABLED 0x012E + +struct ec_params_regulator_is_enabled { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_is_enabled { + uint8_t enabled; +} __ec_align1; /* - * Retrieve info from Cros Board Info store. Response is based on the data - * type. Integers return a uint32. Strings return a string, using the response - * size to determine how big it is. + * Set voltage for the voltage regulator within the range specified. + * + * The driver should select the voltage in range closest to min_mv. + * + * Also note that this might be called before the regulator is enabled, and the + * setting should be in effect after the regulator is enabled. */ -#define EC_CMD_GET_CROS_BOARD_INFO 0x011F +#define EC_CMD_REGULATOR_SET_VOLTAGE 0x012F + +struct ec_params_regulator_set_voltage { + uint32_t index; + uint32_t min_mv; + uint32_t max_mv; +} __ec_align4; + /* - * Write info into Cros Board Info on EEPROM. Write fails if the board has - * hardware write-protect enabled. + * Get the currently configured voltage for the voltage regulator. + * + * Note that this might be called before the regulator is enabled, and this + * should return the configured output voltage if the regulator is enabled. */ -#define EC_CMD_SET_CROS_BOARD_INFO 0x0120 +#define EC_CMD_REGULATOR_GET_VOLTAGE 0x0130 -enum cbi_data_tag { - CBI_TAG_BOARD_VERSION = 0, /* uint16_t or uint8_t[] = {minor,major} */ - CBI_TAG_OEM_ID = 1, /* uint8_t */ - CBI_TAG_SKU_ID = 2, /* uint8_t */ - CBI_TAG_COUNT, +struct ec_params_regulator_get_voltage { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_get_voltage { + uint32_t voltage_mv; +} __ec_align4; + +/* + * Gather all discovery information for the given port and partner type. + * + * Note that if discovery has not yet completed, only the currently completed + * responses will be filled in. If the discovery data structures are changed + * in the process of the command running, BUSY will be returned. + * + * VDO field sizes are set to the maximum possible number of VDOs a VDM may + * contain, while the number of SVIDs here is selected to fit within the PROTO2 + * maximum parameter size. + */ +#define EC_CMD_TYPEC_DISCOVERY 0x0131 + +enum typec_partner_type { + TYPEC_PARTNER_SOP = 0, + TYPEC_PARTNER_SOP_PRIME = 1, + TYPEC_PARTNER_SOP_PRIME_PRIME = 2, +}; + +struct ec_params_typec_discovery { + uint8_t port; + uint8_t partner_type; /* enum typec_partner_type */ +} __ec_align1; + +struct svid_mode_info { + uint16_t svid; + uint16_t mode_count; /* Number of modes partner sent */ + uint32_t mode_vdo[VDO_MAX_OBJECTS]; +}; + +struct ec_response_typec_discovery { + uint8_t identity_count; /* Number of identity VDOs partner sent */ + uint8_t svid_count; /* Number of SVIDs partner sent */ + uint16_t reserved; + uint32_t discovery_vdo[VDO_MAX_OBJECTS]; + struct svid_mode_info svids[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align1; + +/* USB Type-C commands for AP-controlled device policy. */ +#define EC_CMD_TYPEC_CONTROL 0x0132 + +enum typec_control_command { + TYPEC_CONTROL_COMMAND_EXIT_MODES, + TYPEC_CONTROL_COMMAND_CLEAR_EVENTS, + TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_CONTROL_COMMAND_TBT_UFP_REPLY, + TYPEC_CONTROL_COMMAND_USB_MUX_SET, + TYPEC_CONTROL_COMMAND_BIST_SHARE_MODE, + TYPEC_CONTROL_COMMAND_SEND_VDM_REQ, }; +/* Modes (USB or alternate) that a type-C port may enter. */ +enum typec_mode { + TYPEC_MODE_DP, + TYPEC_MODE_TBT, + TYPEC_MODE_USB4, +}; + +/* Replies the AP may specify to the TBT EnterMode command as a UFP */ +enum typec_tbt_ufp_reply { + TYPEC_TBT_UFP_REPLY_NAK, + TYPEC_TBT_UFP_REPLY_ACK, +}; + +#define TYPEC_USB_MUX_SET_ALL_CHIPS 0xFF + +struct typec_usb_mux_set { + /* Index of the mux to set in the chain */ + uint8_t mux_index; + + /* USB_PD_MUX_*-encoded USB mux state to set */ + uint8_t mux_flags; +} __ec_align1; + +struct typec_vdm_req { + /* VDM data, including VDM header */ + uint32_t vdm_data[VDO_MAX_SIZE]; + /* Number of 32-bit fields filled in */ + uint8_t vdm_data_objects; + /* Partner to address - see enum typec_partner_type */ + uint8_t partner_type; +} __ec_align1; + +struct ec_params_typec_control { + uint8_t port; + uint8_t command; /* enum typec_control_command */ + uint16_t reserved; + + /* + * This section will be interpreted based on |command|. Define a + * placeholder structure to avoid having to increase the size and bump + * the command version when adding new sub-commands. + */ + union { + /* Used for CLEAR_EVENTS */ + uint32_t clear_events_mask; + /* Used for ENTER_MODE - enum typec_mode */ + uint8_t mode_to_enter; + /* Used for TBT_UFP_REPLY - enum typec_tbt_ufp_reply */ + uint8_t tbt_ufp_reply; + /* Used for USB_MUX_SET */ + struct typec_usb_mux_set mux_params; + /* Used for BIST_SHARE_MODE */ + uint8_t bist_share_mode; + /* Used for VMD_REQ */ + struct typec_vdm_req vdm_req_params; + uint8_t placeholder[128]; + }; +} __ec_align1; + /* - * Flags to control read operation + * Gather all status information for a port. * - * RELOAD: Invalidate cache and read data from EEPROM. Useful to verify - * write was successful without reboot. + * Note: this covers many of the return fields from the deprecated + * EC_CMD_USB_PD_CONTROL command, except those that are redundant with the + * discovery data. The "enum pd_cc_states" is defined with the deprecated + * EC_CMD_USB_PD_CONTROL command. + * + * This also combines in the EC_CMD_USB_PD_MUX_INFO flags. + */ +#define EC_CMD_TYPEC_STATUS 0x0133 + +/* + * Power role. + * + * Note this is also used for PD header creation, and values align to those in + * the Power Delivery Specification Revision 3.0 (See + * 6.2.1.1.4 Port Power Role). + */ +enum pd_power_role { + PD_ROLE_SINK = 0, + PD_ROLE_SOURCE = 1, +}; + +/* + * Data role. + * + * Note this is also used for PD header creation, and the first two values + * align to those in the Power Delivery Specification Revision 3.0 (See + * 6.2.1.1.6 Port Data Role). + */ +enum pd_data_role { + PD_ROLE_UFP = 0, + PD_ROLE_DFP = 1, + PD_ROLE_DISCONNECTED = 2, +}; + +enum pd_vconn_role { + PD_ROLE_VCONN_OFF = 0, + PD_ROLE_VCONN_SRC = 1, +}; + +/* + * Note: BIT(0) may be used to determine whether the polarity is CC1 or CC2, + * regardless of whether a debug accessory is connected. + */ +enum tcpc_cc_polarity { + /* + * _CCx: is used to indicate the polarity while not connected to + * a Debug Accessory. Only one CC line will assert a resistor and + * the other will be open. + */ + POLARITY_CC1 = 0, + POLARITY_CC2 = 1, + + /* + * _CCx_DTS is used to indicate the polarity while connected to a + * SRC Debug Accessory. Assert resistors on both lines. + */ + POLARITY_CC1_DTS = 2, + POLARITY_CC2_DTS = 3, + + /* + * The current TCPC code relies on these specific POLARITY values. + * Adding in a check to verify if the list grows for any reason + * that this will give a hint that other places need to be + * adjusted. + */ + POLARITY_COUNT, +}; + +#define MODE_DP_PIN_A BIT(0) +#define MODE_DP_PIN_B BIT(1) +#define MODE_DP_PIN_C BIT(2) +#define MODE_DP_PIN_D BIT(3) +#define MODE_DP_PIN_E BIT(4) +#define MODE_DP_PIN_F BIT(5) +#define MODE_DP_PIN_ALL GENMASK(5, 0) + +#define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) +#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) +#define PD_STATUS_EVENT_HARD_RESET BIT(2) +#define PD_STATUS_EVENT_DISCONNECTED BIT(3) +#define PD_STATUS_EVENT_MUX_0_SET_DONE BIT(4) +#define PD_STATUS_EVENT_MUX_1_SET_DONE BIT(5) +#define PD_STATUS_EVENT_VDM_REQ_REPLY BIT(6) +#define PD_STATUS_EVENT_VDM_REQ_FAILED BIT(7) +#define PD_STATUS_EVENT_VDM_ATTENTION BIT(8) +#define PD_STATUS_EVENT_COUNT 9 + +/* + * Encode and decode for BCD revision response + * + * Note: the major revision set is written assuming that the value given is the + * Specification Revision from the PD header, which currently only maps to PD + * 1.0-3.0 with the major revision being one greater than the binary value. + */ +#define PD_STATUS_REV_SET_MAJOR(r) ((r + 1) << 12) +#define PD_STATUS_REV_GET_MAJOR(r) ((r >> 12) & 0xF) +#define PD_STATUS_REV_GET_MINOR(r) ((r >> 8) & 0xF) + +/* + * Encode revision from partner RMDO + * + * Unlike the specification revision given in the PD header, specification and + * version information returned in the revision message data object (RMDO) is + * not offset. + */ +#define PD_STATUS_RMDO_REV_SET_MAJOR(r) (r << 12) +#define PD_STATUS_RMDO_REV_SET_MINOR(r) (r << 8) +#define PD_STATUS_RMDO_VER_SET_MAJOR(r) (r << 4) +#define PD_STATUS_RMDO_VER_SET_MINOR(r) (r) + +/* + * Decode helpers for Source and Sink Capability PDOs + * + * Note: The Power Delivery Specification should be considered the ultimate + * source of truth on the decoding of these PDOs + */ +#define PDO_TYPE_FIXED (0 << 30) +#define PDO_TYPE_BATTERY (1 << 30) +#define PDO_TYPE_VARIABLE (2 << 30) +#define PDO_TYPE_AUGMENTED (3 << 30) +#define PDO_TYPE_MASK (3 << 30) + +/* + * From Table 6-9 and Table 6-14 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Fixed Supply + * <29> : Dual-Role Power + * <28> : SNK/SRC dependent + * <27> : Unconstrained Power + * <26> : USB Communications Capable + * <25> : Dual-Role Data + * <24:20> : SNK/SRC dependent + * <19:10> : Voltage in 50mV Units + * <9:0> : Maximum Current in 10mA units + */ +#define PDO_FIXED_DUAL_ROLE BIT(29) +#define PDO_FIXED_UNCONSTRAINED BIT(27) +#define PDO_FIXED_COMM_CAP BIT(26) +#define PDO_FIXED_DATA_SWAP BIT(25) +#define PDO_FIXED_FRS_CURR_MASK GENMASK(24, 23) /* Sink Cap only */ +#define PDO_FIXED_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_FIXED_CURRENT(p) ((p & 0x3FF) * 10) + +/* + * From Table 6-12 and Table 6-16 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Battery + * <29:20> : Maximum Voltage in 50mV units + * <19:10> : Minimum Voltage in 50mV units + * <9:0> : Maximum Allowable Power in 250mW units + */ +#define PDO_BATT_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_BATT_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_BATT_MAX_POWER(p) ((p & 0x3FF) * 250) + +/* + * From Table 6-11 and Table 6-15 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Variable Supply (non-Battery) + * <29:20> : Maximum Voltage in 50mV units + * <19:10> : Minimum Voltage in 50mV units + * <9:0> : Operational Current in 10mA units + */ +#define PDO_VAR_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_VAR_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_VAR_MAX_CURRENT(p) ((p & 0x3FF) * 10) + +/* + * From Table 6-13 and Table 6-17 PD Rev 3.0 Ver 2.0 + * + * Note this type is reserved in PD 2.0, and only one type of APDO is + * supported as of the cited version. + * + * <31:30> : Augmented Power Data Object + * <29:28> : Programmable Power Supply + * <27> : PPS Power Limited + * <26:25> : Reserved + * <24:17> : Maximum Voltage in 100mV increments + * <16> : Reserved + * <15:8> : Minimum Voltage in 100mV increments + * <7> : Reserved + * <6:0> : Maximum Current in 50mA increments + */ +#define PDO_AUG_MAX_VOLTAGE(p) ((p >> 17 & 0xFF) * 100) +#define PDO_AUG_MIN_VOLTAGE(p) ((p >> 8 & 0xFF) * 100) +#define PDO_AUG_MAX_CURRENT(p) ((p & 0x7F) * 50) + +struct ec_params_typec_status { + uint8_t port; +} __ec_align1; + +/* + * ec_response_typec_status is deprecated. Use ec_response_typec_status_v1. + * If you need to support old ECs who speak only v0, use + * ec_response_typec_status_v0 instead. They're binary-compatible. + */ +struct ec_response_typec_status /* DEPRECATED */ { + uint8_t pd_enabled; /* PD communication enabled - bool */ + uint8_t dev_connected; /* Device connected - bool */ + uint8_t sop_connected; /* Device is SOP PD capable - bool */ + uint8_t source_cap_count; /* Number of Source Cap PDOs */ + + uint8_t power_role; /* enum pd_power_role */ + uint8_t data_role; /* enum pd_data_role */ + uint8_t vconn_role; /* enum pd_vconn_role */ + uint8_t sink_cap_count; /* Number of Sink Cap PDOs */ + + uint8_t polarity; /* enum tcpc_cc_polarity */ + uint8_t cc_state; /* enum pd_cc_states */ + uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ + uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */ + + char tc_state[32]; /* TC state name */ + + uint32_t events; /* PD_STATUS_EVENT bitmask */ + + /* + * BCD PD revisions for partners + * + * The format has the PD major revision in the upper nibble, and the PD + * minor revision in the next nibble. The following two nibbles hold the + * major and minor specification version. If a partner does not support + * the Revision message, only the major revision will be given. + * ex. PD Revision 3.2 Version 1.9 would map to 0x3219 + * + * PD revision/version will be 0 if no PD device is connected. + */ + uint16_t sop_revision; + uint16_t sop_prime_revision; + + uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */ + + uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */ +} __ec_align1; + +struct cros_ec_typec_status { + uint8_t pd_enabled; /* PD communication enabled - bool */ + uint8_t dev_connected; /* Device connected - bool */ + uint8_t sop_connected; /* Device is SOP PD capable - bool */ + uint8_t source_cap_count; /* Number of Source Cap PDOs */ + + uint8_t power_role; /* enum pd_power_role */ + uint8_t data_role; /* enum pd_data_role */ + uint8_t vconn_role; /* enum pd_vconn_role */ + uint8_t sink_cap_count; /* Number of Sink Cap PDOs */ + + uint8_t polarity; /* enum tcpc_cc_polarity */ + uint8_t cc_state; /* enum pd_cc_states */ + uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ + uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */ + + char tc_state[32]; /* TC state name */ + + uint32_t events; /* PD_STATUS_EVENT bitmask */ + + /* + * BCD PD revisions for partners + * + * The format has the PD major revision in the upper nibble, and the PD + * minor revision in the next nibble. The following two nibbles hold the + * major and minor specification version. If a partner does not support + * the Revision message, only the major revision will be given. + * ex. PD Revision 3.2 Version 1.9 would map to 0x3219 + * + * PD revision/version will be 0 if no PD device is connected. + */ + uint16_t sop_revision; + uint16_t sop_prime_revision; +} __ec_align1; + +struct ec_response_typec_status_v0 { + struct cros_ec_typec_status typec_status; + uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */ + uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */ +} __ec_align1; + +struct ec_response_typec_status_v1 { + struct cros_ec_typec_status typec_status; + uint32_t source_cap_pdos[11]; /* Max 11 PDOs can be present */ + uint32_t sink_cap_pdos[11]; /* Max 11 PDOs can be present */ +} __ec_align1; + +/** + * Get the number of peripheral charge ports + */ +#define EC_CMD_PCHG_COUNT 0x0134 + +#define EC_PCHG_MAX_PORTS 8 + +struct ec_response_pchg_count { + uint8_t port_count; +} __ec_align1; + +/** + * Get the status of a peripheral charge port + */ +#define EC_CMD_PCHG 0x0135 + +/* For v1 and v2 */ +struct ec_params_pchg { + uint8_t port; +} __ec_align1; + +struct ec_params_pchg_v3 { + uint8_t port; + /* Below are new in v3. */ + uint8_t reserved1; + uint8_t reserved2; + uint8_t reserved3; + /* Errors acked by the host (thus to be cleared) */ + uint32_t error; +} __ec_align1; + +/* For v1 */ +struct ec_response_pchg { + uint32_t error; /* enum pchg_error */ + uint8_t state; /* enum pchg_state state */ + uint8_t battery_percentage; + uint8_t unused0; + uint8_t unused1; + /* Fields added in version 1 */ + uint32_t fw_version; + uint32_t dropped_event_count; +} __ec_align4; + +/* For v2 and v3 */ +struct ec_response_pchg_v2 { + uint32_t error; /* enum pchg_error */ + uint8_t state; /* enum pchg_state state */ + uint8_t battery_percentage; + uint8_t unused0; + uint8_t unused1; + /* Fields added in version 1 */ + uint32_t fw_version; + uint32_t dropped_event_count; + /* Fields added in version 2 */ + uint32_t dropped_host_event_count; +} __ec_align4; + +enum pchg_state { + /* Charger is reset and not initialized. */ + PCHG_STATE_RESET = 0, + /* Charger is initialized or disabled. */ + PCHG_STATE_INITIALIZED, + /* Charger is enabled and ready to detect a device. */ + PCHG_STATE_ENABLED, + /* Device is in proximity. */ + PCHG_STATE_DETECTED, + /* Device is being charged. */ + PCHG_STATE_CHARGING, + /* Device is fully charged. It implies DETECTED (& not charging). */ + PCHG_STATE_FULL, + /* In download (a.k.a. firmware update) mode */ + PCHG_STATE_DOWNLOAD, + /* In download mode. Ready for receiving data. */ + PCHG_STATE_DOWNLOADING, + /* Device is ready for data communication. */ + PCHG_STATE_CONNECTED, + /* Charger is in Built-In Self Test mode. */ + PCHG_STATE_BIST, + /* Put no more entry below */ + PCHG_STATE_COUNT, +}; + +/* clang-format off */ +#define EC_PCHG_STATE_TEXT \ + { \ + [PCHG_STATE_RESET] = "RESET", \ + [PCHG_STATE_INITIALIZED] = "INITIALIZED", \ + [PCHG_STATE_ENABLED] = "ENABLED", \ + [PCHG_STATE_DETECTED] = "DETECTED", \ + [PCHG_STATE_CHARGING] = "CHARGING", \ + [PCHG_STATE_FULL] = "FULL", \ + [PCHG_STATE_DOWNLOAD] = "DOWNLOAD", \ + [PCHG_STATE_DOWNLOADING] = "DOWNLOADING", \ + [PCHG_STATE_CONNECTED] = "CONNECTED", \ + [PCHG_STATE_BIST] = "BIST", \ + } +/* clang-format on */ + +/** + * Update firmware of peripheral chip + */ +#define EC_CMD_PCHG_UPDATE 0x0136 + +/* Port number is encoded in bit[28:31]. */ +#define EC_MKBP_PCHG_PORT_SHIFT 28 +/* Utility macros for converting MKBP event <-> port number. */ +#define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf) +#define EC_MKBP_PCHG_PORT_TO_EVENT(p) ((p) << EC_MKBP_PCHG_PORT_SHIFT) +/* Utility macro for extracting event bits. */ +#define EC_MKBP_PCHG_EVENT_MASK(e) \ + ((e) & GENMASK(EC_MKBP_PCHG_PORT_SHIFT - 1, 0)) + +#define EC_MKBP_PCHG_UPDATE_OPENED BIT(0) +#define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1) +#define EC_MKBP_PCHG_UPDATE_CLOSED BIT(2) +#define EC_MKBP_PCHG_UPDATE_ERROR BIT(3) +#define EC_MKBP_PCHG_DEVICE_EVENT BIT(4) + +enum ec_pchg_update_cmd { + /* Reset chip to normal mode. */ + EC_PCHG_UPDATE_CMD_RESET_TO_NORMAL = 0, + /* Reset and put a chip in update (a.k.a. download) mode. */ + EC_PCHG_UPDATE_CMD_OPEN, + /* Write a block of data containing FW image. */ + EC_PCHG_UPDATE_CMD_WRITE, + /* Close update session. */ + EC_PCHG_UPDATE_CMD_CLOSE, + /* Reset chip (without mode change). */ + EC_PCHG_UPDATE_CMD_RESET, + /* Enable pass-through mode. */ + EC_PCHG_UPDATE_CMD_ENABLE_PASSTHRU, + /* End of commands */ + EC_PCHG_UPDATE_CMD_COUNT, +}; + +struct ec_params_pchg_update { + /* PCHG port number */ + uint8_t port; + /* enum ec_pchg_update_cmd */ + uint8_t cmd; + /* Padding */ + uint8_t reserved0; + uint8_t reserved1; + /* Version of new firmware */ + uint32_t version; + /* CRC32 of new firmware */ + uint32_t crc32; + /* Address in chip memory where is written to */ + uint32_t addr; + /* Size of */ + uint32_t size; + /* Partial data of new firmware */ + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; + +BUILD_ASSERT(EC_PCHG_UPDATE_CMD_COUNT < + BIT(sizeof(((struct ec_params_pchg_update *)0)->cmd) * 8)); + +struct ec_response_pchg_update { + /* Block size */ + uint32_t block_size; +} __ec_align4; + +#define EC_CMD_DISPLAY_SOC 0x0137 + +struct ec_response_display_soc { + /* Display charge in 10ths of a % (1000=100.0%) */ + int16_t display_soc; + /* Full factor in 10ths of a % (1000=100.0%) */ + int16_t full_factor; + /* Shutdown SoC in 10ths of a % (1000=100.0%) */ + int16_t shutdown_soc; +} __ec_align2; + +#define EC_CMD_SET_BASE_STATE 0x0138 + +struct ec_params_set_base_state { + uint8_t cmd; /* enum ec_set_base_state_cmd */ +} __ec_align1; + +enum ec_set_base_state_cmd { + EC_SET_BASE_STATE_DETACH = 0, + EC_SET_BASE_STATE_ATTACH, + EC_SET_BASE_STATE_RESET, +}; + +#define EC_CMD_I2C_CONTROL 0x0139 + +/* Subcommands for I2C control */ + +enum ec_i2c_control_command { + EC_I2C_CONTROL_GET_SPEED, + EC_I2C_CONTROL_SET_SPEED, +}; + +#define EC_I2C_CONTROL_SPEED_UNKNOWN 0 + +struct ec_params_i2c_control { + uint8_t port; /* I2C port number */ + uint8_t cmd; /* enum ec_i2c_control_command */ + union { + uint16_t speed_khz; + } cmd_params; +} __ec_align_size1; + +struct ec_response_i2c_control { + union { + uint16_t speed_khz; + } cmd_response; +} __ec_align_size1; + +#define EC_CMD_RGBKBD_SET_COLOR 0x013A +#define EC_CMD_RGBKBD 0x013B + +#define EC_RGBKBD_MAX_KEY_COUNT 128 +#define EC_RGBKBD_MAX_RGB_COLOR 0xFFFFFF +#define EC_RGBKBD_MAX_SCALE 0xFF + +enum rgbkbd_state { + /* RGB keyboard is reset and not initialized. */ + RGBKBD_STATE_RESET = 0, + /* RGB keyboard is initialized but not enabled. */ + RGBKBD_STATE_INITIALIZED, + /* RGB keyboard is disabled. */ + RGBKBD_STATE_DISABLED, + /* RGB keyboard is enabled and ready to receive a command. */ + RGBKBD_STATE_ENABLED, + + /* Put no more entry below */ + RGBKBD_STATE_COUNT, +}; + +enum ec_rgbkbd_subcmd { + EC_RGBKBD_SUBCMD_CLEAR = 1, + EC_RGBKBD_SUBCMD_DEMO = 2, + EC_RGBKBD_SUBCMD_SET_SCALE = 3, + EC_RGBKBD_SUBCMD_GET_CONFIG = 4, + EC_RGBKBD_SUBCMD_COUNT +}; + +enum ec_rgbkbd_demo { + EC_RGBKBD_DEMO_OFF = 0, + EC_RGBKBD_DEMO_FLOW = 1, + EC_RGBKBD_DEMO_DOT = 2, + EC_RGBKBD_DEMO_COUNT, +}; + +BUILD_ASSERT(EC_RGBKBD_DEMO_COUNT <= 255); + +enum ec_rgbkbd_type { + EC_RGBKBD_TYPE_UNKNOWN = 0, + EC_RGBKBD_TYPE_PER_KEY = 1, /* e.g. Vell */ + EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS = 2, /* e.g. Taniks */ + EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS = 3, /* e.g. Osiris */ + EC_RGBKBD_TYPE_FOUR_ZONES_4_LEDS = 4, /* e.g. Mithrax */ + EC_RGBKBD_TYPE_COUNT, +}; + +struct ec_rgbkbd_set_scale { + uint8_t key; + struct rgb_s scale; +}; + +struct ec_params_rgbkbd { + uint8_t subcmd; /* Sub-command (enum ec_rgbkbd_subcmd) */ + union { + struct rgb_s color; /* EC_RGBKBD_SUBCMD_CLEAR */ + uint8_t demo; /* EC_RGBKBD_SUBCMD_DEMO */ + struct ec_rgbkbd_set_scale set_scale; + }; +} __ec_align1; + +struct ec_response_rgbkbd { + /* + * RGBKBD type supported by the device. + */ + + uint8_t rgbkbd_type; /* enum ec_rgbkbd_type */ +} __ec_align1; + +struct ec_params_rgbkbd_set_color { + /* Specifies the starting key ID whose color is being changed. */ + uint8_t start_key; + /* Specifies # of elements in . */ + uint8_t length; + /* RGB color data array of length up to MAX_KEY_COUNT. */ + struct rgb_s color[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align1; + +/* + * Gather the response to the most recent VDM REQ from the AP, as well + * as popping the oldest VDM:Attention from the DPM queue + */ +#define EC_CMD_TYPEC_VDM_RESPONSE 0x013C + +struct ec_params_typec_vdm_response { + uint8_t port; +} __ec_align1; + +struct ec_response_typec_vdm_response { + /* Number of 32-bit fields filled in */ + uint8_t vdm_data_objects; + /* Partner to address - see enum typec_partner_type */ + uint8_t partner_type; + /* enum ec_status describing VDM response */ + uint16_t vdm_response_err; + /* VDM data, including VDM header */ + uint32_t vdm_response[VDO_MAX_SIZE]; + /* Number of 32-bit Attention fields filled in */ + uint8_t vdm_attention_objects; + /* Number of remaining messages to consume */ + uint8_t vdm_attention_left; + /* Reserved */ + uint16_t reserved1; + /* VDM:Attention contents */ + uint32_t vdm_attention[2]; +} __ec_align1; + +/* + * Get an active battery config from the EC. + */ +#define EC_CMD_BATTERY_CONFIG 0x013D + +/* Version of struct batt_conf_header and its internals. */ +#define EC_BATTERY_CONFIG_STRUCT_VERSION 0x00 + +/* Number of writes needed to invoke battery cutoff command */ +#define SHIP_MODE_WRITES 2 + +struct ship_mode_info { + uint8_t reg_addr; + uint8_t reserved; + uint16_t reg_data[SHIP_MODE_WRITES]; +} __packed __aligned(2); + +struct sleep_mode_info { + uint8_t reg_addr; + uint8_t reserved; + uint16_t reg_data; +} __packed __aligned(2); + +struct fet_info { + uint8_t reg_addr; + uint8_t reserved; + uint16_t reg_mask; + uint16_t disconnect_val; + uint16_t cfet_mask; /* CHG FET status mask */ + uint16_t cfet_off_val; +} __packed __aligned(2); + +enum fuel_gauge_flags { + /* + * Write Block Support. If enabled, we use a i2c write block command + * instead of a 16-bit write. The effective difference is the i2c + * transaction will prefix the length (2). + */ + FUEL_GAUGE_FLAG_WRITE_BLOCK = BIT(0), + /* Sleep command support. fuel_gauge_info.sleep_mode must be defined. */ + FUEL_GAUGE_FLAG_SLEEP_MODE = BIT(1), + /* + * Manufacturer access command support. If enabled, FET status is read + * from the OperationStatus (0x54) register using the + * ManufacturerBlockAccess (0x44). + */ + FUEL_GAUGE_FLAG_MFGACC = BIT(2), + /* + * SMB block protocol support in manufacturer access command. If + * enabled, FET status is read from the OperationStatus (0x54) register + * using the ManufacturerBlockAccess (0x44). + */ + FUEL_GAUGE_FLAG_MFGACC_SMB_BLOCK = BIT(3), +}; + +struct fuel_gauge_info { + uint32_t flags; + uint32_t board_flags; + struct ship_mode_info ship_mode; + struct sleep_mode_info sleep_mode; + struct fet_info fet; +} __packed __aligned(4); + +/* Battery constants */ +struct battery_info { + /* Operation voltage in mV */ + uint16_t voltage_max; + uint16_t voltage_normal; + uint16_t voltage_min; + /* (TODO(chromium:756700): add desired_charging_current */ + /** + * Pre-charge to fast charge threshold in mV, + * default to voltage_min if not specified. + * This option is only available on isl923x and rt946x. + */ + uint16_t precharge_voltage; + /* Pre-charge current in mA */ + uint16_t precharge_current; + /* Working temperature ranges in degrees C */ + int8_t start_charging_min_c; + int8_t start_charging_max_c; + int8_t charging_min_c; + int8_t charging_max_c; + int8_t discharging_min_c; + int8_t discharging_max_c; + /* Used only if CONFIG_BATTERY_VENDOR_PARAM is defined. */ + uint8_t vendor_param_start; + uint8_t reserved; +} __packed __aligned(2); + +/* + * The 'config' of a battery. + */ +struct board_batt_params { + struct fuel_gauge_info fuel_gauge; + struct battery_info batt_info; +} __packed __aligned(4); + +/* + * The SBS defines a string object as a block of chars, 32 byte maximum, where + * the first byte indicates the number of chars in the block (excluding the + * first byte). + * + * Thus, the actual string length (i.e. the value strlen returns) is limited to + * 31 (=SBS_MAX_STR_SIZE). + * + * SBS_MAX_STR_OBJ_SIZE can be used as the size of a buffer for an SBS string + * object but also as a buffer for a c-lang string because the null terminating + * char also takes one byte. + */ +#define SBS_MAX_STR_SIZE 31 +#define SBS_MAX_STR_OBJ_SIZE (SBS_MAX_STR_SIZE + 1) + +/* + * Header describing a battery config stored in CBI. Only struct_version has + * size and position independent of struct_version. The rest varies as + * struct_version changes. + * + * Version 0 + * Layout: + * +-------------+ + * | header | + * +-------------+ + * | | ^ + * | manuf_name | | manuf_name_size + * | | v + * +-------------+ + * | device_name | ^ + * | | | device_name_size + * | | v + * +-------------+ + * | config | ^ + * | | | + * | | | cbi data size + * | | | - (header_size+manuf_name_size+device_name_size) + * | | | + * | | v + * +-------------+ + * Note: + * - manuf_name and device_name are not null-terminated. + * - The config isn't aligned. It should be copied to struct board_batt_params + * before its contents are accessed. + */ +struct batt_conf_header { + /* Version independent field. It's always here as a uint8_t. */ + uint8_t struct_version; + /* Version 0 members */ + uint8_t manuf_name_size; + uint8_t device_name_size; + uint8_t reserved; + /* manuf_name, device_name, board_batt_params follow after this. */ +} __packed; + +#define BATT_CONF_MAX_SIZE \ + (sizeof(struct batt_conf_header) + SBS_MAX_STR_OBJ_SIZE * 2 + \ + sizeof(struct board_batt_params)) + +/* + * Record the current AP firmware state. This is used to help testing, such as + * with FAFT (Fully-Automated Firmware Test), which likes to know which firmware + * screen is currently displayed. + */ + +#define EC_CMD_AP_FW_STATE 0x013E + +struct ec_params_ap_fw_state { + /* + * Value which indicates the state. This is not decoded by the EC, so + * its meaning is entirely outside this code base. + */ + uint32_t state; +} __ec_align1; + +/* + * UCSI OPM-PPM commands + * + * These commands are used for communication between OPM and PPM. + * Only UCSI3.0 is tested. + */ + +#define EC_CMD_UCSI_PPM_SET 0x0140 + +/* The data size is stored in the host command protocol header. */ +struct ec_params_ucsi_ppm_set { + uint16_t offset; + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align2; + +#define EC_CMD_UCSI_PPM_GET 0x0141 + +/* For 'GET' sub-commands, data will be returned as a raw payload. */ +struct ec_params_ucsi_ppm_get { + uint16_t offset; + uint8_t size; +} __ec_align2; + +#define EC_CMD_SET_ALARM_SLP_S0_DBG 0x0142 + +/* RTC params and response structures */ +struct ec_params_set_alarm_slp_s0_dbg { + uint32_t time; +} __ec_align2; + +/* + * Control PDC tracing. + * EC_PDC_TRACE_MSG_PORT_NONE disable tracing + * EC_PDC_TRACE_MSG_PORT_ALL enable tracing on all ports + * else, enable tracing on a specific port. */ -#define CBI_GET_RELOAD (1 << 0) -struct __ec_align4 ec_params_get_cbi { - uint32_t type; /* enum cbi_data_tag */ - uint32_t flag; /* CBI_GET_* */ +#define EC_CMD_PDC_TRACE_MSG_ENABLE 0x0143 + +#define EC_PDC_TRACE_MSG_PORT_NONE 0xff +#define EC_PDC_TRACE_MSG_PORT_ALL 0xfe + +struct ec_params_pdc_trace_msg_enable { + uint8_t port; }; +struct ec_response_pdc_trace_msg_enable { + /* Previous port value. */ + uint8_t port; + uint8_t reserved; + /* Number of free bytes in FIFO. */ + uint16_t fifo_free; + /* Running total of dropped messages (may wrap). */ + uint32_t dropped_count; +} __ec_align4; + /* - * Flags to control write behavior. + * Fetch multiple PDC trace entries. * - * NO_SYNC: Makes EC update data in RAM but skip writing to EEPROM. It's - * useful when writing multiple fields in a row. - * INIT: Needs to be set when creating a new CBI from scratch. All fields - * will be initialized to zero first. + * If no entries are available, pl_size is 0. + * At most MAX_HC_PDC_TRACE_MSG_GET_PAYLOAD bytes worth of entries + * are returned. Only whole entries are returned. */ -#define CBI_SET_NO_SYNC (1 << 0) -#define CBI_SET_INIT (1 << 1) -struct __ec_align1 ec_params_set_cbi { - uint32_t tag; /* enum cbi_data_tag */ - uint32_t flag; /* CBI_SET_* */ - uint32_t size; /* Data size */ - uint8_t data[]; /* For string and raw data */ +#define EC_CMD_PDC_TRACE_MSG_GET_ENTRIES 0x0144 +#define MAX_HC_PDC_TRACE_MSG_GET_PAYLOAD 240 + +struct ec_response_pdc_trace_msg_get_entries { + /* Total bytes of payload. */ + uint16_t pl_size; + /* Packed array of pdc_trace_msg_entry structs. */ + uint8_t payload[FLEXIBLE_ARRAY_MEMBER_SIZE]; +}; + +enum pdc_trace_msg_direction { + PDC_TRACE_MSG_DIR_IN = 0, + PDC_TRACE_MSG_DIR_OUT = 1, }; +struct pdc_trace_msg_entry { + /* + * Timestamp - least significant 32 bits of EC epoch time + * (microseconds, will wrap around). + */ + uint32_t time32_us; + /* Entry sequence number (wraps around). */ + uint16_t seq_num; + /* Port number associated with this entry. */ + uint8_t port_num; + /* Direction of message (enum pdc_trace_msg_direction) */ + uint8_t direction; + /* Format of pdc_data (PDC chip identifier). */ + uint8_t msg_type; + /* Bytes in pdc_data. */ + uint8_t pdc_data_size; + /* Captured PDC message. */ + uint8_t pdc_data[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align1; + +/* Enable/disable Ethernet POE power */ +#define EC_CMD_SWITCH_ENABLE_POE 0x0145 + +struct ec_params_switch_enable_poe { + uint8_t enabled; +} __ec_align1; + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ @@ -4449,61 +8422,151 @@ struct __ec_align1 ec_params_set_cbi { /*****************************************************************************/ /* Fingerprint MCU commands: range 0x0400-0x040x */ -/* Fingerprint SPI sensor passthru command: prototyping ONLY */ +/* + * Fingerprint SPI sensor passthru command + * + * This command was used for prototyping and it's now deprecated. + */ #define EC_CMD_FP_PASSTHRU 0x0400 #define EC_FP_FLAG_NOT_COMPLETE 0x1 -struct __ec_align2 ec_params_fp_passthru { - uint16_t len; /* Number of bytes to write then read */ - uint16_t flags; /* EC_FP_FLAG_xxx */ - uint8_t data[]; /* Data to send */ -}; - -/* Fingerprint sensor configuration command: prototyping ONLY */ -#define EC_CMD_FP_SENSOR_CONFIG 0x0401 - -#define EC_FP_SENSOR_CONFIG_MAX_REGS 16 - -struct __ec_align2 ec_params_fp_sensor_config { - uint8_t count; /* Number of setup registers */ - /* - * the value to send to each of the 'count' setup registers - * is stored in the 'data' array for 'len' bytes just after - * the previous one. - */ - uint8_t len[EC_FP_SENSOR_CONFIG_MAX_REGS]; - uint8_t data[]; -}; +struct ec_params_fp_passthru { + uint16_t len; /* Number of bytes to write then read */ + uint16_t flags; /* EC_FP_FLAG_xxx */ + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; /* Data to send */ +} __ec_align2; /* Configure the Fingerprint MCU behavior */ #define EC_CMD_FP_MODE 0x0402 /* Put the sensor in its lowest power mode */ -#define FP_MODE_DEEPSLEEP (1<<0) +#define FP_MODE_DEEPSLEEP BIT(0) /* Wait to see a finger on the sensor */ -#define FP_MODE_FINGER_DOWN (1<<1) +#define FP_MODE_FINGER_DOWN BIT(1) /* Poll until the finger has left the sensor */ -#define FP_MODE_FINGER_UP (1<<2) +#define FP_MODE_FINGER_UP BIT(2) /* Capture the current finger image */ -#define FP_MODE_CAPTURE (1<<3) +#define FP_MODE_CAPTURE BIT(3) +/* Finger enrollment session on-going */ +#define FP_MODE_ENROLL_SESSION BIT(4) +/* Enroll the current finger image */ +#define FP_MODE_ENROLL_IMAGE BIT(5) +/* Try to match the current finger image */ +#define FP_MODE_MATCH BIT(6) +/* Reset and re-initialize the sensor. */ +#define FP_MODE_RESET_SENSOR BIT(7) +/* Sensor maintenance for dead pixels. */ +#define FP_MODE_SENSOR_MAINTENANCE BIT(8) +/* Encrypt template. */ +#define FP_MODE_ENCRYPT_TEMPLATE BIT(9) +/* Decrypt template. */ +#define FP_MODE_DECRYPT_TEMPLATE BIT(10) +/* Disable template update. */ +#define FP_MODE_MATCH_NO_TEMPLATE_UPDATE BIT(11) /* special value: don't change anything just read back current mode */ -#define FP_MODE_DONT_CHANGE (1<<31) +#define FP_MODE_DONT_CHANGE BIT(31) + +#define FP_VALID_MODES \ + (FP_MODE_DEEPSLEEP | FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP | \ + FP_MODE_CAPTURE | FP_MODE_ENROLL_SESSION | FP_MODE_ENROLL_IMAGE | \ + FP_MODE_MATCH | FP_MODE_RESET_SENSOR | FP_MODE_SENSOR_MAINTENANCE | \ + FP_MODE_ENCRYPT_TEMPLATE | FP_MODE_DECRYPT_TEMPLATE | \ + FP_MODE_MATCH_NO_TEMPLATE_UPDATE | FP_MODE_DONT_CHANGE) + +#define FP_MODES_WITH_AUTHENTICATION (FP_MODE_ENROLL_SESSION | FP_MODE_MATCH) +#define FP_MODES_CRYPTO_IN_PROGRESS \ + (FP_MODE_ENCRYPT_TEMPLATE | FP_MODE_DECRYPT_TEMPLATE) +#define FP_MODES_TEMPLATE_OPERATION \ + (FP_MODE_ENROLL_SESSION | FP_MODE_ENROLL_IMAGE | FP_MODE_MATCH | \ + FP_MODE_RESET_SENSOR | FP_MODE_ENCRYPT_TEMPLATE | \ + FP_MODE_DECRYPT_TEMPLATE) + +/* Capture types defined in bits [30..26] */ +#define FP_MODE_CAPTURE_TYPE_SHIFT 26 +#define FP_MODE_CAPTURE_TYPE_MASK (0x1F << FP_MODE_CAPTURE_TYPE_SHIFT) +/** + * enum fp_capture_type - Specifies the "mode" when capturing images. + * + * @FP_CAPTURE_TYPE_INVALID: an invalid capture type + * @FP_CAPTURE_VENDOR_FORMAT: Capture 1-3 images and choose the best quality + * image (produces 'frame_size' bytes) + * @FP_CAPTURE_SIMPLE_IMAGE: Simple raw image capture (produces width x height x + * bpp bits) + * @FP_CAPTURE_DEFECT_PXL_TEST: Capture for check defect pixel test + * @FP_CAPTURE_ABNORMAL_TEST: Capture for check abnormal pixel test + * @FP_CAPTURE_NOISE_TEST: Capture for check noise test + * @FP_CAPTURE_PATTERN0: Self test pattern (e.g. checkerboard) + * @FP_CAPTURE_PATTERN1: Self test pattern (e.g. inverted checkerboard) + * @FP_CAPTURE_QUALITY_TEST: Capture for Quality test with fixed contrast + * @FP_CAPTURE_RESET_TEST: Capture for pixel reset value test + * @FP_CAPTURE_TYPE_MAX: End of enum + * + * @note This enum must remain ordered, if you add new values you must ensure + * that FP_CAPTURE_TYPE_MAX is still the last one. + */ +/* LINT.IfChange */ +enum fp_capture_type { + FP_CAPTURE_TYPE_INVALID = -1, + FP_CAPTURE_VENDOR_FORMAT = 0, + FP_CAPTURE_DEFECT_PXL_TEST = 1, + FP_CAPTURE_ABNORMAL_TEST = 2, + FP_CAPTURE_NOISE_TEST = 3, + FP_CAPTURE_SIMPLE_IMAGE = 4, + FP_CAPTURE_PATTERN0 = 8, + FP_CAPTURE_PATTERN1 = 12, + FP_CAPTURE_QUALITY_TEST = 16, + FP_CAPTURE_RESET_TEST = 20, + FP_CAPTURE_TYPE_MAX, +}; +/* LINT.ThenChange(/test/fpsensor_utils.cc, + * /zephyr/test/fingerprint/task/src/fpsensor_debug.cc) + */ + +/* The maximum number of capture types in enum fp_capture_type */ +#define FP_MAX_CAPTURE_TYPES 9 -struct __ec_align4 ec_params_fp_mode { +/* Extracts the capture type from the sensor 'mode' word */ +#define FP_CAPTURE_TYPE(mode) \ + (enum fp_capture_type)(((mode) & FP_MODE_CAPTURE_TYPE_MASK) >> \ + FP_MODE_CAPTURE_TYPE_SHIFT) + +#define FP_MAC_LENGTH 32 + +struct ec_params_fp_mode { uint32_t mode; /* as defined by FP_MODE_ constants */ - /* TBD */ -}; +} __ec_align4; -struct __ec_align4 ec_response_fp_mode { +struct ec_params_fp_mode_v1 { uint32_t mode; /* as defined by FP_MODE_ constants */ - /* TBD */ -}; + uint8_t mac[FP_MAC_LENGTH]; +} __ec_align4; + +struct ec_response_fp_mode { + uint32_t mode; /* as defined by FP_MODE_ constants */ +} __ec_align4; /* Retrieve Fingerprint sensor information */ #define EC_CMD_FP_INFO 0x0403 -struct __ec_align2 ec_response_fp_info { +/* Mask for dead pixels */ +#define FP_ERROR_DEAD_PIXELS_MASK 0x3FF +/* Maximum number of dead pixels */ +#define FP_ERROR_DEAD_PIXELS_MAX (FP_ERROR_DEAD_PIXELS_MASK - 1) +/* Number of dead pixels detected on the last maintenance */ +#define FP_ERROR_DEAD_PIXELS(errors) ((errors) & FP_ERROR_DEAD_PIXELS_MASK) +/* Unknown number of dead pixels detected on the last maintenance */ +#define FP_ERROR_DEAD_PIXELS_UNKNOWN (FP_ERROR_DEAD_PIXELS_MASK) +/* No interrupt from the sensor */ +#define FP_ERROR_NO_IRQ BIT(12) +/* SPI communication error */ +#define FP_ERROR_SPI_COMM BIT(13) +/* Invalid sensor Hardware ID */ +#define FP_ERROR_BAD_HWID BIT(14) +/* Sensor initialization failed */ +#define FP_ERROR_INIT_FAIL BIT(15) + +struct ec_response_fp_info_v0 { /* Sensor identification */ uint32_t vendor_id; uint32_t product_id; @@ -4515,16 +8578,449 @@ struct __ec_align2 ec_response_fp_info { uint16_t width; uint16_t height; uint16_t bpp; -}; + uint16_t errors; /* see FP_ERROR_ flags above */ +} __ec_align4; + +struct ec_response_fp_info { + /* Sensor identification */ + uint32_t vendor_id; + uint32_t product_id; + uint32_t model_id; + uint32_t version; + /* Image frame characteristics */ + uint32_t frame_size; + uint32_t pixel_format; /* using V4L2_PIX_FMT_ */ + uint16_t width; + uint16_t height; + uint16_t bpp; + uint16_t errors; /* see FP_ERROR_ flags above */ + /* Template/finger current information */ + uint32_t template_size; /* max template size in bytes */ + uint16_t template_max; /* maximum number of fingers/templates */ + uint16_t template_valid; /* number of valid fingers/templates */ + uint32_t template_dirty; /* bitmap of templates with MCU side changes */ + uint32_t template_version; /* version of the template format */ +} __ec_align4; + +struct fp_sensor_info { + /* Sensor identification */ + uint32_t vendor_id; + uint32_t product_id; + uint32_t model_id; + uint32_t version; + uint16_t num_capture_types; /* number of image capture types */ + uint16_t errors; /* see FP_ERROR_ flags above */ +} __ec_align4; +BUILD_ASSERT(sizeof(struct fp_sensor_info) == 20); + +struct fp_template_info { + /* Template/finger current information */ + uint32_t template_size; /* max template size in bytes */ + uint16_t template_max; /* maximum number of fingers/templates */ + uint16_t template_valid; /* number of valid fingers/templates */ + uint32_t template_dirty; /* bitmap of templates with MCU side changes */ + uint32_t template_version; /* version of the template format */ +} __ec_align4; +BUILD_ASSERT(sizeof(struct fp_template_info) == 16); + +struct fp_image_frame_params { + /* Image frame characteristics */ + uint32_t frame_size; + uint32_t pixel_format; /* using V4L2_PIX_FMT_ */ + uint16_t width; + uint16_t height; + uint16_t bpp; + /** Type of image capture from enum fp_capture_type. */ + uint8_t fp_capture_type; + uint8_t reserved; /**< padding for alignment */ +} __ec_align4; +BUILD_ASSERT(sizeof(struct fp_image_frame_params) == 16); + +struct ec_response_fp_info_v2 { + /* Sensor identification */ + struct fp_sensor_info sensor_info; + /* Template/finger current information */ + struct fp_template_info template_info; + /* fingerprint image frame parameters */ + struct fp_image_frame_params + image_frame_params[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; +BUILD_ASSERT(sizeof(struct ec_response_fp_info_v2) == 36); + +struct fp_image_frame_params_v2 { + /* Image frame characteristics */ + uint32_t frame_size; + uint32_t image_data_offset_bytes; /**< Byte offset of image buffer */ + uint32_t pixel_format; /* using V4L2_PIX_FMT_ */ + uint16_t width; + uint16_t height; + uint16_t bpp; + /** Type of image capture from enum fp_capture_type. */ + uint8_t fp_capture_type; + uint8_t reserved; /**< padding for alignment */ +} __ec_align4; +BUILD_ASSERT(sizeof(struct fp_image_frame_params_v2) == 20); + +struct ec_response_fp_info_v3 { + /* Sensor identification */ + struct fp_sensor_info sensor_info; + /* Template/finger current information */ + struct fp_template_info template_info; + /* fingerprint image frame parameters */ + struct fp_image_frame_params_v2 + image_frame_params[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; +BUILD_ASSERT(sizeof(struct ec_response_fp_info_v3) == 36); -/* Get the last captured finger frame: TODO: will be AES-encrypted */ +/* Get the last captured finger frame or a template content */ #define EC_CMD_FP_FRAME 0x0404 -struct __ec_align4 ec_params_fp_frame { +/* constants defining the 'offset' field which also contains the frame index */ +#define FP_FRAME_INDEX_SHIFT 28 +/* Frame buffer where the captured image is stored */ +#define FP_FRAME_INDEX_RAW_IMAGE 0 +/* First frame buffer holding a template */ +#define FP_FRAME_INDEX_TEMPLATE 1 +#define FP_FRAME_GET_BUFFER_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT) +#define FP_FRAME_OFFSET_MASK 0x0FFFFFFF + +/* Version of the format of the encrypted templates. */ +#define FP_TEMPLATE_FORMAT_VERSION 4 + +/* Constants for encryption parameters */ +#define FP_CONTEXT_NONCE_BYTES 12 +#define FP_CONTEXT_USERID_BYTES 32 +#define FP_CONTEXT_USERID_WORDS (FP_CONTEXT_USERID_BYTES / sizeof(uint32_t)) +#define FP_CONTEXT_TAG_BYTES 16 +#define FP_CONTEXT_ENCRYPTION_SALT_BYTES 16 +#define FP_CONTEXT_TPM_BYTES 32 + +/* Constants for positive match parameters. */ +#define FP_POSITIVE_MATCH_SALT_BYTES 16 + +struct ec_fp_template_encryption_metadata { + /* + * Version of the structure format (N=3). + */ + uint16_t struct_version; + /* Reserved bytes, set to 0. */ + uint16_t reserved; + /* + * The salt is *only* ever used for key derivation. The nonce is unique, + * a different one is used for every message. + */ + uint8_t nonce[FP_CONTEXT_NONCE_BYTES]; + uint8_t encryption_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES]; + uint8_t tag[FP_CONTEXT_TAG_BYTES]; +}; + +struct ec_params_fp_frame { + /* + * The offset contains the template index or FP_FRAME_INDEX_RAW_IMAGE + * in the high nibble, and the real offset within the frame in + * FP_FRAME_OFFSET_MASK. + */ + uint32_t offset; + uint32_t size; +} __ec_align4; + +/* + * FP_FRAME commands: + * + * - FP_FRAME_GET_RAW_IMAGE command can be used to get raw image from sensor. + * This command works only when the system is not locked. The template index + * is ignored. + * - FP_FRAME_ENCRYPT_TEMPLATE command is used to request encryption of the + * template with provided template index. Offset and size are ignored. + * The encryption process is considered as started only after EC_SUCCESS + * was returned. + * - FP_FRAME_GET_ENCRYPTED_TEMPLATE command is used to obtain the encrypted + * template. + */ +enum fp_frame_cmd { + FP_FRAME_GET_RAW_IMAGE = 0, + FP_FRAME_ENCRYPT_TEMPLATE = 1, + FP_FRAME_GET_ENCRYPTED_TEMPLATE = 2, +}; + +struct ec_params_fp_frame_v1 { + uint8_t cmd; + uint8_t reserved; + uint16_t index; + uint32_t offset; + uint32_t size; +} __ec_align4; + +/* Load a template into the MCU */ +#define EC_CMD_FP_TEMPLATE 0x0405 + +/* Flag in the 'size' field indicating that the full template has been sent */ +#define FP_TEMPLATE_COMMIT 0x80000000 + +struct ec_params_fp_template { + uint32_t offset; + uint32_t size; + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; + +/* + * FP_TEMPLATE commands: + * + * - FP_TEMPLATE_LOAD command is used to copy part of the template to FPMCU + * buffer. + * - FP_TEMPLATE_DECRYPT command starts template decryption. + * - FP_TEMPLATE_GET_RESULT command is used to check decryption result. + */ +enum fp_template_cmd { + FP_TEMPLATE_LOAD = 0, + FP_TEMPLATE_DECRYPT = 1, + FP_TEMPLATE_GET_RESULT = 2, +}; + +struct ec_params_fp_template_v1 { uint32_t offset; uint32_t size; + uint8_t cmd; + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; + +/* Clear the current fingerprint user context and set a new one */ +#define EC_CMD_FP_CONTEXT 0x0406 + +struct ec_params_fp_context { + uint32_t userid[FP_CONTEXT_USERID_WORDS]; +} __ec_align4; + +enum fp_context_action { + FP_CONTEXT_ASYNC = 0, + FP_CONTEXT_GET_RESULT = 1, }; +/* Version 1 of the command is "asynchronous". */ +struct ec_params_fp_context_v1 { + uint8_t action; /**< enum fp_context_action */ + uint8_t reserved[3]; /**< padding for alignment */ + uint32_t userid[FP_CONTEXT_USERID_WORDS]; +} __ec_align4; + +#define EC_CMD_FP_STATS 0x0407 + +#define FPSTATS_CAPTURE_INV BIT(0) +#define FPSTATS_MATCHING_INV BIT(1) + +struct ec_response_fp_stats { + uint32_t capture_time_us; + uint32_t matching_time_us; + uint32_t overall_time_us; + struct { + uint32_t lo; + uint32_t hi; + } overall_t0; + uint8_t timestamps_invalid; + int8_t template_matched; +} __ec_align2; + +#define EC_CMD_FP_SEED 0x0408 +struct ec_params_fp_seed { + /* + * Version of the structure format (N=3). + */ + uint16_t struct_version; + /* Reserved bytes, set to 0. */ + uint16_t reserved; + /* Seed from the TPM. */ + uint8_t seed[FP_CONTEXT_TPM_BYTES]; +} __ec_align4; + +#define EC_CMD_FP_ENC_STATUS 0x0409 + +/* FP TPM seed has been set or not */ +#define FP_ENC_STATUS_SEED_SET BIT(0) +/* Session was established or not */ +#define FP_CONTEXT_STATUS_SESSION_ESTABLISHED BIT(1) +/* FP session_nonce had been set or not*/ +#define FP_CONTEXT_SESSION_NONCE_SET BIT(2) +/* FP user_id had been set or not*/ +#define FP_CONTEXT_USER_ID_SET BIT(3) +/* The operation authentication challenge was generated */ +#define FP_AUTH_CHALLENGE_SET BIT(4) +/* Encrypted template is available */ +#define FP_ENCRYPTED_TEMPLATE_READY BIT(5) + +struct ec_response_fp_encryption_status { + /* Used bits in encryption engine status */ + uint32_t valid_flags; + /* Encryption engine status */ + uint32_t status; +} __ec_align4; + +#define EC_CMD_FP_READ_MATCH_SECRET 0x040A +struct ec_params_fp_read_match_secret { + uint16_t fgr; +} __ec_align4; + +/* + * Fingerprint vendor defined command. + * + * A custom per fingerprint vendor host command. It can be used to fetch some + * custom data during testing, manufacturing etc. + * + * This command should be handled only if the system is unlocked. + */ +#define EC_CMD_FP_VENDOR 0x040B +struct ec_params_fp_vendor { + /* Parameter to be used by FP vendors. */ + uint32_t param1; +} __ec_align4; + +/* The positive match secret has the length of the SHA256 digest. */ +#define FP_POSITIVE_MATCH_SECRET_BYTES 32 +struct ec_response_fp_read_match_secret { + uint8_t positive_match_secret[FP_POSITIVE_MATCH_SECRET_BYTES]; +} __ec_align4; + +#define FP_ELLIPTIC_CURVE_PUBLIC_KEY_POINT_LEN 32 + +struct fp_elliptic_curve_public_key { + uint8_t x[FP_ELLIPTIC_CURVE_PUBLIC_KEY_POINT_LEN]; + uint8_t y[FP_ELLIPTIC_CURVE_PUBLIC_KEY_POINT_LEN]; +} __ec_align4; + +#define FP_AES_KEY_ENC_METADATA_VERSION 1 +#define FP_AES_KEY_NONCE_BYTES 12 +#define FP_AES_KEY_ENCRYPTION_SALT_BYTES 16 +#define FP_AES_KEY_TAG_BYTES 16 + +struct fp_auth_command_encryption_metadata { + /* Version of the structure format */ + uint16_t struct_version; + /* Reserved bytes, set to 0. */ + uint16_t reserved; + /* + * The salt is *only* ever used for key derivation. The nonce is unique, + * a different one is used for every message. + */ + uint8_t nonce[FP_AES_KEY_NONCE_BYTES]; + uint8_t encryption_salt[FP_AES_KEY_ENCRYPTION_SALT_BYTES]; + uint8_t tag[FP_AES_KEY_TAG_BYTES]; +} __ec_align4; + +#define FP_ELLIPTIC_CURVE_PRIVATE_KEY_LEN 32 +#define FP_ELLIPTIC_CURVE_PUBLIC_KEY_IV_LEN 16 + +struct fp_encrypted_private_key { + struct fp_auth_command_encryption_metadata info; + uint8_t data[FP_ELLIPTIC_CURVE_PRIVATE_KEY_LEN]; +} __ec_align4; + +#define EC_CMD_FP_ESTABLISH_PAIRING_KEY_KEYGEN 0x0410 + +struct ec_response_fp_establish_pairing_key_keygen { + struct fp_elliptic_curve_public_key pubkey; +} __ec_align4; + +#define FP_PAIRING_KEY_LEN 32 + +struct ec_fp_encrypted_pairing_key { + struct fp_auth_command_encryption_metadata info; + uint8_t data[FP_PAIRING_KEY_LEN]; +} __ec_align4; + +#define EC_CMD_FP_ESTABLISH_PAIRING_KEY_WRAP 0x0411 + +struct ec_params_fp_establish_pairing_key_wrap { + struct fp_elliptic_curve_public_key peers_pubkey; +} __ec_align4; + +struct ec_response_fp_establish_pairing_key_wrap { + struct ec_fp_encrypted_pairing_key encrypted_pairing_key; +} __ec_align4; + +#define EC_CMD_FP_LOAD_PAIRING_KEY 0x0412 + +typedef struct ec_response_fp_establish_pairing_key_wrap + ec_params_fp_load_pairing_key; + +#define FP_CK_SESSION_NONCE_LEN 32 + +#define EC_CMD_FP_GENERATE_NONCE 0x0413 +struct ec_response_fp_generate_nonce { + uint8_t nonce[FP_CK_SESSION_NONCE_LEN]; +} __ec_align4; + +#define EC_CMD_FP_ESTABLISH_SESSION 0x0414 +struct ec_params_fp_establish_session { + uint8_t peer_nonce[FP_CK_SESSION_NONCE_LEN]; + uint8_t enc_tpm_seed[FP_CONTEXT_TPM_BYTES]; + uint8_t nonce[FP_AES_KEY_NONCE_BYTES]; + uint8_t tag[FP_AES_KEY_TAG_BYTES]; +} __ec_align4; + +#define FP_CHALLENGE_SIZE 32 + +#define EC_CMD_FP_GENERATE_CHALLENGE 0x0415 +struct ec_response_fp_generate_challenge { + uint8_t challenge[FP_CHALLENGE_SIZE]; +} __ec_align4; + +#define EC_CMD_FP_CONFIRM_TEMPLATE 0x0416 +struct ec_params_fp_confirm_template { + uint8_t mac[FP_MAC_LENGTH]; +} __ec_align4; + +#define EC_CMD_FP_SIGN_MATCH 0x0417 +struct ec_params_fp_sign_match { + uint8_t challenge[FP_CHALLENGE_SIZE]; +} __ec_align4; + +struct ec_response_fp_sign_match { + uint8_t signature[FP_MAC_LENGTH]; +} __ec_align4; + +/* + * Fingerprint ASCP claim command. + * + */ +#define EC_CMD_FP_ASCP_CLAIM 0x0420 + +/* + * ECC public key with no point compression as defined in + * ANSI X9.62 section 4.3.6 (0x04||x||y), P256v1 curve. + */ +#define FP_ASCP_KEY_SIZE 65 +/* ECC signature, P256v1 curve, P1363 encoding (r||s) */ +#define FP_ASCP_SIGNATURE_SIZE 64 +/* SHA256 */ +#define FP_ASCP_HASH_SIZE 32 + +struct ec_response_fp_ascp_claim { + /* Model public key. */ + uint8_t pk_m[FP_ASCP_KEY_SIZE]; + /* Model public key signature. */ + uint8_t s_goog[FP_ASCP_SIGNATURE_SIZE]; + /* Device public key. */ + uint8_t pk_d[FP_ASCP_KEY_SIZE]; + /* Device public key signature (signed using model key). */ + uint8_t s_m[FP_ASCP_SIGNATURE_SIZE]; + /* Ephemeral public key used in ECDH procedure. */ + uint8_t pk_f[FP_ASCP_KEY_SIZE]; + /* SHA256 hash of the firmware. */ + uint8_t h_f[FP_ASCP_HASH_SIZE]; + /* Signature of the SHA256( 0xC001 || h_f || pk_f) using device key. */ + uint8_t s_d[FP_ASCP_SIGNATURE_SIZE]; +} __ec_align4; + +/* + * Fingerprint ASCP establish command. + * + */ +#define EC_CMD_FP_ASCP_ESTABLISH 0x0421 + +struct ec_params_fp_ascp_establish { + /* TA's ephemeral public key. */ + uint8_t pk_g[FP_ASCP_KEY_SIZE]; +} __ec_align4; + /*****************************************************************************/ /* Touchpad MCU commands: range 0x0500-0x05FF */ @@ -4534,10 +9030,10 @@ struct __ec_align4 ec_params_fp_frame { /* Get number of frame types, and the size of each type */ #define EC_CMD_TP_FRAME_INFO 0x0501 -struct __ec_align4 ec_response_tp_frame_info { +struct ec_response_tp_frame_info { uint32_t n_frames; - uint32_t frame_sizes[0]; -}; + uint32_t frame_sizes[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; /* Create a snapshot of current frame readings */ #define EC_CMD_TP_FRAME_SNAPSHOT 0x0502 @@ -4545,12 +9041,246 @@ struct __ec_align4 ec_response_tp_frame_info { /* Read the frame */ #define EC_CMD_TP_FRAME_GET 0x0503 -struct __ec_align4 ec_params_tp_frame_get { +struct ec_params_tp_frame_get { uint32_t frame_index; uint32_t offset; uint32_t size; +} __ec_align4; + +/*****************************************************************************/ +/* EC-EC communication commands: range 0x0600-0x06FF */ + +#define EC_COMM_TEXT_MAX 8 + +/* + * Get battery static information, i.e. information that never changes, or + * very infrequently. + */ +#define EC_CMD_BATTERY_GET_STATIC 0x0600 + +/** + * struct ec_params_battery_static_info - Battery static info parameters + * @index: Battery index. + */ +struct ec_params_battery_static_info { + uint8_t index; +} __ec_align_size1; + +/** + * struct ec_response_battery_static_info - Battery static info response + * @design_capacity: Battery Design Capacity (mAh) + * @design_voltage: Battery Design Voltage (mV) + * @manufacturer: Battery Manufacturer String + * @model: Battery Model Number String + * @serial: Battery Serial Number String + * @type: Battery Type String + * @cycle_count: Battery Cycle Count + */ +struct ec_response_battery_static_info { + uint16_t design_capacity; + uint16_t design_voltage; + char manufacturer[EC_COMM_TEXT_MAX]; + char model[EC_COMM_TEXT_MAX]; + char serial[EC_COMM_TEXT_MAX]; + char type[EC_COMM_TEXT_MAX]; + /* TODO(crbug.com/795991): Consider moving to dynamic structure. */ + uint32_t cycle_count; +} __ec_align4; + +/** + * struct ec_response_battery_static_info_v1 - hostcmd v1 battery static info + * Equivalent to struct ec_response_battery_static_info, but with longer + * strings. + * @design_capacity: battery design capacity (in mAh) + * @design_voltage: battery design voltage (in mV) + * @cycle_count: battery cycle count + * @manufacturer_ext: battery manufacturer string + * @model_ext: battery model string + * @serial_ext: battery serial number string + * @type_ext: battery type string + */ +struct ec_response_battery_static_info_v1 { + uint16_t design_capacity; + uint16_t design_voltage; + uint32_t cycle_count; + char manufacturer_ext[12]; + char model_ext[12]; + char serial_ext[12]; + char type_ext[12]; +} __ec_align4; + +/** + * struct ec_response_battery_static_info_v2 - hostcmd v2 battery static info + * + * Equivalent to struct ec_response_battery_static_info, but with strings + * further lengthened (relative to v1) to accommodate the maximum string length + * permitted by the Smart Battery Data Specification revision 1.1 and fields + * renamed to better match that specification. + * + * @design_capacity: battery design capacity (in mAh) + * @design_voltage: battery design voltage (in mV) + * @cycle_count: battery cycle count + * @manufacturer: battery manufacturer string + * @device_name: battery model string + * @serial: battery serial number string + * @chemistry: battery type string + */ +struct ec_response_battery_static_info_v2 { + uint16_t design_capacity; + uint16_t design_voltage; + uint32_t cycle_count; + char manufacturer[SBS_MAX_STR_OBJ_SIZE]; + char device_name[SBS_MAX_STR_OBJ_SIZE]; + char serial[SBS_MAX_STR_OBJ_SIZE]; + char chemistry[SBS_MAX_STR_OBJ_SIZE]; +} __ec_align4; + +/** + * struct ec_response_battery_static_info_v3 - hostcmd v3 battery static info + * + * Extends struct ec_response_battery_static_info_v2 with + * manuf_info. + * + * @design_capacity: battery design capacity (in mAh) + * @design_voltage: battery design voltage (in mV) + * @cycle_count: battery cycle count + * @manufacturer: battery manufacturer string + * @device_name: battery model string + * @serial: battery serial number string + * @chemistry: battery type string + * @manuf_info: battery manufacture info string (vendor specific) + * @manuf_year: battery manufacture year + * @manuf_month: battery manufacture month + * @manuf_day: battery manufacture day + */ +struct ec_response_battery_static_info_v3 { + uint16_t design_capacity; + uint16_t design_voltage; + uint32_t cycle_count; + char manufacturer[SBS_MAX_STR_OBJ_SIZE]; + char device_name[SBS_MAX_STR_OBJ_SIZE]; + char serial[SBS_MAX_STR_OBJ_SIZE]; + char chemistry[SBS_MAX_STR_OBJ_SIZE]; + char manuf_info[SBS_MAX_STR_OBJ_SIZE]; + uint16_t manuf_year; + uint8_t manuf_month; + uint8_t manuf_day; +} __ec_align4; + +/* + * Get battery dynamic information, i.e. information that is likely to change + * every time it is read. + */ +#define EC_CMD_BATTERY_GET_DYNAMIC 0x0601 + +/** + * struct ec_params_battery_dynamic_info - Battery dynamic info parameters + * @index: Battery index. + */ +struct ec_params_battery_dynamic_info { + uint8_t index; +} __ec_align_size1; + +/** + * struct ec_response_battery_dynamic_info - Battery dynamic info response + * @actual_voltage: Battery voltage (mV) + * @actual_current: Battery current (mA); negative=discharging + * @remaining_capacity: Remaining capacity (mAh) + * @full_capacity: Capacity (mAh, might change occasionally) + * @flags: Flags, see EC_BATT_FLAG_* + * @desired_voltage: Charging voltage desired by battery (mV) + * @desired_current: Charging current desired by battery (mA) + */ +struct ec_response_battery_dynamic_info { + int16_t actual_voltage; + int16_t actual_current; + int16_t remaining_capacity; + int16_t full_capacity; + int16_t flags; + int16_t desired_voltage; + int16_t desired_current; +} __ec_align2; + +/** + * struct ec_response_battery_dynamic_info_v1 - Battery dynamic info response + * (v1) + * @actual_voltage: Battery voltage (mV) + * @actual_current: Battery current (mA); negative=discharging + * @remaining_capacity: Remaining capacity (mAh) + * @full_capacity: Capacity (mAh, might change occasionally) + * @flags: Flags, see EC_BATT_FLAG_* + * @desired_voltage: Charging voltage desired by battery (mV) + * @desired_current: Charging current desired by battery (mA) + * @temperature: Battery temperature (dK) + */ +struct ec_response_battery_dynamic_info_v1 { + int16_t actual_voltage; + int16_t actual_current; + int16_t remaining_capacity; + int16_t full_capacity; + int16_t flags; + int16_t desired_voltage; + int16_t desired_current; + uint16_t temperature; +} __ec_align2; + +/* + * Control charger chip. Used to control charger chip on the peripheral. + */ +#define EC_CMD_CHARGER_CONTROL 0x0602 + +/** + * struct ec_params_charger_control - Charger control parameters + * @max_current: Charger current (mA). Positive to allow base to draw up to + * max_current and (possibly) charge battery, negative to request current + * from base (OTG). + * @otg_voltage: Voltage (mV) to use in OTG mode, ignored if max_current is + * >= 0. + * @allow_charging: Allow base battery charging (only makes sense if + * max_current > 0). + */ +struct ec_params_charger_control { + int16_t max_current; + uint16_t otg_voltage; + uint8_t allow_charging; +} __ec_align_size1; + +/* Get ACK from the USB-C SS muxes */ +#define EC_CMD_USB_PD_MUX_ACK 0x0603 + +struct ec_params_usb_pd_mux_ack { + uint8_t port; /* USB-C port number */ +} __ec_align1; + +/* Get boot time */ +#define EC_CMD_GET_BOOT_TIME 0x0604 + +enum boot_time_param { + ARAIL = 0, + RSMRST, + ESPIRST, + PLTRST_LOW, + PLTRST_HIGH, + EC_CUR_TIME, + RESET_CNT, }; +struct ec_response_get_boot_time { + uint64_t timestamp[RESET_CNT]; + uint16_t cnt; +} __ec_align4; + +/* Issue AP shutdown */ +#define EC_CMD_AP_SHUTDOWN 0x0605 + +/** + * Issue AP shutdown using heartbeat wake. + * The AP calls this to enter the low-power G3 state for off-mode charging. + * The EC then monitors battery SoC and wakes the AP when discharged by a + * configured threshold. + */ +#define EC_CMD_ENABLE_OFFMODE_HEARTBEAT 0x0606 + /*****************************************************************************/ /* * Reserve a range of host commands for board-specific, experimental, or @@ -4621,10 +9351,14 @@ struct __ec_align4 ec_params_tp_frame_get { * switch to the new names soon, as the old names may not be carried forward * forever. */ -#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE -#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1 -#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE +#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE +#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1 +#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE -#endif /* !__ACPI__ && !__KERNEL__ */ +#endif /* !__ACPI__ */ + +#ifdef __cplusplus +} +#endif -#endif /* __CROS_EC_COMMANDS_H */ +#endif /* __CROS_EC_EC_COMMANDS_H */ -- cgit v1.3.1 From 5e41a5deb4b843808f3c892f2f54f1b9c76b3da1 Mon Sep 17 00:00:00 2001 From: James Hilliard Date: Mon, 11 May 2026 12:20:25 -0600 Subject: env: migrate static flags list to Kconfig Environment callbacks can already be configured from Kconfig with CONFIG_ENV_CALLBACK_LIST_STATIC, but static environment flags still require board headers to define CFG_ENV_FLAGS_LIST_STATIC. Add CONFIG_ENV_FLAGS_LIST_STATIC and use it as the only board-provided static environment flags list. Convert the remaining default-config users from CFG_ENV_FLAGS_LIST_STATIC to defconfig settings and drop the legacy header macro from ENV_FLAGS_LIST_STATIC. Move the environment flags format documentation out of README and into the developer environment documentation. Include the format in the Kconfig help as well. This lets boards configure writeable-list policy and type validation from defconfig without adding a config header solely for env flags. This preserves the behavior of default configs. Header-only cases that were inactive in upstream defconfigs are not converted into defconfig entries: iot2050 can add its list when enabling ENV_WRITEABLE_LIST, and smegw01 can add mmcdev:dw support if the unlocked SYS_BOOT_LOCKED=n configuration is needed. Signed-off-by: James Hilliard Reviewed-by: Tom Rini Reviewed-by: Simon Glass Reviewed-by: Alexander Sverdlin Reviewed-by: Walter Schweizer --- README | 45 +----------------------------------- configs/aristainetos2c_defconfig | 1 + configs/aristainetos2ccslb_defconfig | 1 + configs/hmibsc_defconfig | 1 + configs/imx6q_bosch_acc_defconfig | 1 + configs/imx8qxp_capricorn.config | 1 + configs/smegw01_defconfig | 1 + configs/socrates_defconfig | 1 + doc/develop/environment.rst | 40 ++++++++++++++++++++++++++++++++ env/Kconfig | 23 ++++++++++++++++++ include/configs/aristainetos2.h | 3 --- include/configs/capricorn-common.h | 13 ----------- include/configs/hmibsc.h | 4 ---- include/configs/imx6q-bosch-acc.h | 12 ---------- include/configs/iot2050.h | 8 ------- include/configs/smegw01.h | 15 ------------ include/configs/socrates.h | 2 -- include/env_flags.h | 6 +---- 18 files changed, 72 insertions(+), 106 deletions(-) (limited to 'include') diff --git a/README b/README index 6836a917c79..664d88a5505 100644 --- a/README +++ b/README @@ -799,7 +799,7 @@ The following options need to be configured: The same can be accomplished in a more flexible way for any variable by configuring the type of access to allow for those variables in the ".flags" variable - or define CFG_ENV_FLAGS_LIST_STATIC. + or by setting CONFIG_ENV_FLAGS_LIST_STATIC. - Protected RAM: CFG_PRAM @@ -1106,49 +1106,6 @@ Configuration Settings: - CONFIG_SYS_FLASH_USE_BUFFER_WRITE Use buffered writes to flash. -- CONFIG_ENV_FLAGS_LIST_DEFAULT -- CFG_ENV_FLAGS_LIST_STATIC - Enable validation of the values given to environment variables when - calling env set. Variables can be restricted to only decimal, - hexadecimal, or boolean. If CONFIG_CMD_NET is also defined, - the variables can also be restricted to IP address or MAC address. - - The format of the list is: - type_attribute = [s|d|x|b|i|m] - access_attribute = [a|r|o|c] - attributes = type_attribute[access_attribute] - entry = variable_name[:attributes] - list = entry[,list] - - The type attributes are: - s - String (default) - d - Decimal - x - Hexadecimal - b - Boolean ([1yYtT|0nNfF]) - i - IP address - m - MAC address - - The access attributes are: - a - Any (default) - r - Read-only - o - Write-once - c - Change-default - - - CONFIG_ENV_FLAGS_LIST_DEFAULT - Define this to a list (string) to define the ".flags" - environment variable in the default or embedded environment. - - - CFG_ENV_FLAGS_LIST_STATIC - Define this to a list (string) to define validation that - should be done if an entry is not found in the ".flags" - environment variable. To override a setting in the static - list, simply add an entry for the same variable name to the - ".flags" variable. - - If CONFIG_REGEX is defined, the variable_name above is evaluated as a - regular expression. This allows multiple variables to define the same - flags without explicitly listing them for each variable. - The following definitions that deal with the placement and management of environment data (variable area); in general, we support the following configurations: diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 6923d27f79a..6c44e670cbc 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -56,6 +56,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_FLAGS_LIST_STATIC="ethaddr:mw,serial#:sw,board_type:sw,sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index 3ffebb15375..5016646ef87 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -56,6 +56,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_FLAGS_LIST_STATIC="ethaddr:mw,serial#:sw,board_type:sw,sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y diff --git a/configs/hmibsc_defconfig b/configs/hmibsc_defconfig index 1e3d744193d..c8fad154e31 100644 --- a/configs/hmibsc_defconfig +++ b/configs/hmibsc_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y # CONFIG_OF_UPSTREAM is not set +CONFIG_ENV_FLAGS_LIST_STATIC="BOOT_A_LEFT:dw,BOOT_B_LEFT:dw,BOOT_ORDER:sw" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig index 6f0ef2eaee3..87cf676ed4c 100644 --- a/configs/imx6q_bosch_acc_defconfig +++ b/configs/imx6q_bosch_acc_defconfig @@ -74,6 +74,7 @@ CONFIG_EFI_PARTITION=y CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent" +CONFIG_ENV_FLAGS_LIST_STATIC="bootset:bw,clone_pending:bw,endurance_test:bw,env_persisted:bw,factory_reset:bw,fdtcontroladdr:xw,fitpart:dw,mmcpart:dw,production:bw,ustate:dw" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y diff --git a/configs/imx8qxp_capricorn.config b/configs/imx8qxp_capricorn.config index 2bae5b1a862..91da5554db0 100644 --- a/configs/imx8qxp_capricorn.config +++ b/configs/imx8qxp_capricorn.config @@ -92,6 +92,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_FLAGS_LIST_STATIC="bootcount:dw,bootdelay:sw,bootlimit:dw,partitionset_active:sw,rastate:dw,sig_a:sw,sig_b:sw,target_env:sw,upgrade_available:dw,ustate:dw" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig index 529836e7bdd..e5d4014d640 100644 --- a/configs/smegw01_defconfig +++ b/configs/smegw01_defconfig @@ -48,6 +48,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_SQUASHFS=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_ENV_FLAGS_LIST_STATIC="mmcpart:dw,mmcpart_committed:dw,ustate:dw,bootcount:dw,bootlimit:dw,upgrade_available:dw" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 217141cceda..79e40268c6b 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -66,6 +66,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=fe000000.nor_flash,nand0=socrates_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe000000.nor_flash:13312k(system1),13312k(system2),5120k(data),128k(env),128k(env-red),768k(u-boot);socrates_nand:256M(ubi-data1),-(ubi-data2)" # CONFIG_CMD_IRQ is not set CONFIG_OF_CONTROL=y +CONFIG_ENV_FLAGS_LIST_STATIC="ethaddr:mw,eth1addr:mw,system1_addr:xw,serial#:sw,ethact:sw,ethprime:sw" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xFFF00000 diff --git a/doc/develop/environment.rst b/doc/develop/environment.rst index e46cd39d601..a7ed4aab0a5 100644 --- a/doc/develop/environment.rst +++ b/doc/develop/environment.rst @@ -49,3 +49,43 @@ The signature of the callback functions is:: include/search.h The return value is 0 if the variable change is accepted and 1 otherwise. + +Flags for environment variables +------------------------------- + +Environment flags validate the values given to environment variables and +restrict how environment variables can be changed. + +The static list is configured with CONFIG_ENV_FLAGS_LIST_STATIC. The list +must be in the following format:: + + type_attribute = [s|d|x|b|i|m] + access_attribute = [a|r|o|c|w] + attributes = type_attribute[access_attribute] + entry = variable_name[:attributes] + list = entry[,list] + +The type attributes are: + +* s - String (default) +* d - Decimal +* x - Hexadecimal +* b - Boolean ([1yYtT|0nNfF]) +* i - IP address, if networking is enabled +* m - MAC address, if networking is enabled + +The access attributes are: + +* a - Any (default) +* r - Read-only +* o - Write-once +* c - Change-default +* w - Writeable, if CONFIG_ENV_WRITEABLE_LIST is enabled + +CONFIG_ENV_FLAGS_LIST_DEFAULT defines the ``.flags`` variable in the +default or embedded environment. Any association in ``.flags`` overrides +an association in the static list. + +If CONFIG_REGEX is defined, the variable name is evaluated as a regular +expression. This allows multiple variables to define the same flags without +explicitly listing them all. diff --git a/env/Kconfig b/env/Kconfig index 7abd82ab6f3..3c9aaeb1f16 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -34,6 +34,29 @@ config ENV_CALLBACK_LIST_STATIC If the callback name is not specified, then the callback is deleted. Spaces are also allowed anywhere in the list. +config ENV_FLAGS_LIST_STATIC + string "Static flags list" + default "" + help + The environment flags are associated with variables in a static + list. Define this list in the following format: + + type_attribute = [s|d|x|b|i|m] + access_attribute = [a|r|o|c|w] + attributes = type_attribute[access_attribute] + entry = variable_name[:attributes] + list = entry[,list] + + The type attributes are s for string, d for decimal, x for + hexadecimal and b for boolean. If networking is enabled, i can + be used for IP addresses and m for MAC addresses. + + The access attributes are a for any, r for read-only, o for + write-once and c for change-default. When CONFIG_ENV_WRITEABLE_LIST + is enabled, w can be used to mark variables as writable. + + Spaces are also allowed anywhere in the list. + config SAVEENV def_bool y if CMD_SAVEENV diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 8a66b1275df..c0e5c72764e 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -413,7 +413,4 @@ /* UBI support */ -#define CFG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ - "sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" - #endif /* __ARISTAINETOS2_CONFIG_H */ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index ee13d2ab950..7120a44d186 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -38,19 +38,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ AHAB_ENV -#ifdef CONFIG_ENV_WRITEABLE_LIST -#define CFG_ENV_FLAGS_LIST_STATIC \ - "bootcount:dw," \ - "bootdelay:sw," \ - "bootlimit:dw," \ - "partitionset_active:sw," \ - "rastate:dw," \ - "sig_a:sw,sig_b:sw," \ - "target_env:sw," \ - "upgrade_available:dw," \ - "ustate:dw" -#endif - /* Default location for tftp and bootm */ /* On CCP board, USDHC1 is for eMMC */ diff --git a/include/configs/hmibsc.h b/include/configs/hmibsc.h index 950ec8b190d..ea9762ee448 100644 --- a/include/configs/hmibsc.h +++ b/include/configs/hmibsc.h @@ -8,8 +8,4 @@ #ifndef __CONFIGS_HMIBSC_H #define __CONFIGS_HMIBSC_H -/* PHY needs a longer aneg time */ - -#define CFG_ENV_FLAGS_LIST_STATIC "BOOT_A_LEFT:dw,BOOT_B_LEFT:dw,BOOT_ORDER:sw" - #endif diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 84da8250684..e00cddfdac0 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -44,18 +44,6 @@ "then env set env_persisted 1; run save_env; fi;\0" \ "save_env=env save; env save\0" -#define CFG_ENV_FLAGS_LIST_STATIC \ - "bootset:bw," \ - "clone_pending:bw," \ - "endurance_test:bw," \ - "env_persisted:bw," \ - "factory_reset:bw," \ - "fdtcontroladdr:xw," \ - "fitpart:dw," \ - "mmcpart:dw," \ - "production:bw," \ - "ustate:dw" - #else /* SD Card boot */ #define ENV_EXTRA \ diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h index 5c58c7bbaab..fac4bbcd4ed 100644 --- a/include/configs/iot2050.h +++ b/include/configs/iot2050.h @@ -38,12 +38,4 @@ func(MMC, mmc, 0) \ BOOT_TARGET_USB(func) -#ifdef CONFIG_ENV_WRITEABLE_LIST -#define CFG_ENV_FLAGS_LIST_STATIC \ - "board_uuid:sw,board_name:sw,board_serial:sw,board_a5e:sw," \ - "mlfb:sw,fw_version:sw,seboot_version:sw," \ - "m2_manual_config:sw," \ - "eth1addr:mw,eth2addr:mw,watchdog_timeout_ms:dw,boot_targets:sw" -#endif - #endif /* __CONFIG_IOT2050_H */ diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index 0aa25f9e2ea..c0ca5a7db2f 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -22,21 +22,6 @@ #define EXTRA_BOOTPARAMS #endif -#ifdef CONFIG_SYS_BOOT_LOCKED -#define EXTRA_ENV_FLAGS -#else -#define EXTRA_ENV_FLAGS "mmcdev:dw," -#endif - -#define CFG_ENV_FLAGS_LIST_STATIC \ - "mmcpart:dw," \ - "mmcpart_committed:dw," \ - "ustate:dw," \ - "bootcount:dw," \ - "bootlimit:dw," \ - "upgrade_available:dw," \ - EXTRA_ENV_FLAGS - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 006d649f6ed..68d177d4ca3 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -108,8 +108,6 @@ */ #define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -#define CFG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,eth1addr:mw,system1_addr:xw,serial#:sw,ethact:sw,ethprime:sw" - /* pass open firmware flat tree */ #endif /* __CONFIG_H */ diff --git a/include/env_flags.h b/include/env_flags.h index 123fdbcb0ba..245dfdbd564 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -37,10 +37,6 @@ enum env_flags_varaccess { #define ENV_FLAGS_VARTYPE_LOC 0 #define ENV_FLAGS_VARACCESS_LOC 1 -#ifndef CFG_ENV_FLAGS_LIST_STATIC -#define CFG_ENV_FLAGS_LIST_STATIC "" -#endif - #if CONFIG_IS_ENABLED(NET) #ifdef CONFIG_REGEX #define ETHADDR_WILDCARD "\\d*" @@ -89,7 +85,7 @@ enum env_flags_varaccess { NET_FLAGS \ NET6_FLAGS \ SERIAL_FLAGS \ - CFG_ENV_FLAGS_LIST_STATIC + CONFIG_ENV_FLAGS_LIST_STATIC #ifdef CONFIG_CMD_ENV_FLAGS /* -- cgit v1.3.1 From d3eee4d3b120f2fe30932b2f29d935cc9ac9ddb3 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 16 May 2026 00:37:43 +0100 Subject: image: fit: add dm-verity property name constants Add FIT_VERITY_NODENAME and the complete set of FIT_VERITY_*_PROP constants for the dm-verity child node of filesystem-type images, plus the five optional boolean error-handling property names aligned with the flat-image-tree specification. Signed-off-by: Daniel Golle Reviewed-by: Simon Glass Reviewed-by: Tom Rini --- include/image.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'include') diff --git a/include/image.h b/include/image.h index 34efac6056d..482446a8115 100644 --- a/include/image.h +++ b/include/image.h @@ -1079,6 +1079,23 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, #define FIT_CIPHER_NODENAME "cipher" #define FIT_ALGO_PROP "algo" +/* dm-verity node */ +#define FIT_VERITY_NODENAME "dm-verity" +#define FIT_VERITY_ALGO_PROP "algo" +#define FIT_VERITY_DBS_PROP "data-block-size" +#define FIT_VERITY_HBS_PROP "hash-block-size" +#define FIT_VERITY_NBLK_PROP "num-data-blocks" +#define FIT_VERITY_HBLK_PROP "hash-start-block" +#define FIT_VERITY_DIGEST_PROP "digest" +#define FIT_VERITY_SALT_PROP "salt" + +/* dm-verity error-handling modes (optional boolean property names) */ +#define FIT_VERITY_OPT_RESTART "restart-on-corruption" +#define FIT_VERITY_OPT_PANIC "panic-on-corruption" +#define FIT_VERITY_OPT_RERR "restart-on-error" +#define FIT_VERITY_OPT_PERR "panic-on-error" +#define FIT_VERITY_OPT_ONCE "check-at-most-once" + /* image node */ #define FIT_DATA_PROP "data" #define FIT_DATA_POSITION_PROP "data-position" -- cgit v1.3.1 From cafe3d6e90e661bd9d42b19f1e2d891da48f3fce Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 16 May 2026 00:37:52 +0100 Subject: boot: fit: support generating DM verity cmdline parameters Add fit_verity_build_cmdline(): when a FILESYSTEM loadable carries a dm-verity subnode, construct the dm-mod.create= kernel cmdline parameter from the verity metadata (block-size, data-blocks, algo, root-hash, salt) and append it to bootargs. Also add dm-mod.waitfor=/dev/fit0[,/dev/fitN] for each dm-verity device so the kernel waits for the underlying FIT block device to appear before setting up device-mapper targets. This is needed when the block driver probes late, e.g. because it depends on NVMEM calibration data. The dm-verity target references /dev/fitN where N is the loadable's index in the configuration -- matching the order Linux's FIT block driver assigns block devices. hash-start-block is read directly from the FIT dm-verity node; mkimage ensures its value equals num-data-blocks by invoking veritysetup with --no-superblock. Signed-off-by: Daniel Golle Reviewed-by: Simon Glass --- boot/Kconfig | 20 ++++ boot/bootm.c | 13 +++ boot/image-board.c | 5 + boot/image-fit.c | 337 +++++++++++++++++++++++++++++++++++++++++++++++++++++ include/image.h | 80 ++++++++++++- 5 files changed, 454 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/boot/Kconfig b/boot/Kconfig index ae6f09a6ede..e1114aea843 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -142,6 +142,26 @@ config FIT_CIPHER Enable the feature of data ciphering/unciphering in the tool mkimage and in the u-boot support of the FIT image. +config FIT_VERITY + bool "dm-verity boot parameter generation from FIT metadata" + depends on FIT && OF_LIBFDT + help + When a FIT configuration contains loadable sub-images of type + IH_TYPE_FILESYSTEM with a dm-verity subnode, this option enables + building the dm-mod.create= and dm-mod.waitfor= kernel + command-line parameters from the verity metadata + (data-block-size, hash-block-size, num-data-blocks, + hash-start-block, algorithm, digest, salt) stored in the FIT. + + The generated parameters reference /dev/fitN block devices that + Linux's uImage.FIT block driver assigns to loadable sub-images. + + During FIT parsing (BOOTM_STATE_FINDOTHER), verity cmdline + fragments are stored in struct bootm_headers and automatically + appended to the bootargs environment variable during + BOOTM_STATE_OS_PREP. This works from both the bootm command + and BOOTSTD bootmeths. + config FIT_VERBOSE bool "Show verbose messages when FIT images fail" help diff --git a/boot/bootm.c b/boot/bootm.c index 4836d6b2d41..ec74873b503 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -243,6 +243,13 @@ static int boot_get_kernel(const char *addr_fit, struct bootm_headers *images, static int bootm_start(void) { + /* + * Free dm-verity allocations from a prior boot attempt before + * zeroing the structure. The pointers are guaranteed to be valid + * or NULL: .bss is zero-initialised, and memset() below zeroes + * them again after every boot. + */ + fit_verity_free(&images); memset((void *)&images, 0, sizeof(images)); images.verify = env_get_yesno("verify"); @@ -1071,6 +1078,12 @@ int bootm_run_states(struct bootm_info *bmi, int states) /* For Linux OS do all substitutions at console processing */ if (images->os.os == IH_OS_LINUX) flags = BOOTM_CL_ALL; + ret = fit_verity_apply_bootargs(images); + if (ret) { + printf("dm-verity bootargs failed (err=%d)\n", ret); + ret = CMD_RET_FAILURE; + goto err; + } ret = bootm_process_cmdline_env(flags); if (ret) { printf("Cmdline setup failed (err=%d)\n", ret); diff --git a/boot/image-board.c b/boot/image-board.c index 005d60caf5c..265f29d44ff 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -810,6 +810,11 @@ int boot_get_loadable(struct bootm_headers *images) fit_loadable_process(img_type, img_data, img_len); } + + fit_img_result = fit_verity_build_cmdline(buf, conf_noffset, + images); + if (fit_img_result < 0) + return fit_img_result; break; default: printf("The given image format is not supported (corrupt?)\n"); diff --git a/boot/image-fit.c b/boot/image-fit.c index b0fcaf6e17f..d3d68579ea1 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -21,8 +21,11 @@ extern void *aligned_alloc(size_t alignment, size_t size); #else #include +#include #include +#include #include +#include #include #include #include @@ -243,6 +246,39 @@ static void fit_image_print_data(const void *fit, int noffset, const char *p, } } +static __maybe_unused void fit_image_print_dm_verity(const void *fit, + int noffset, + const char *p) +{ +#if defined(USE_HOSTCC) || CONFIG_IS_ENABLED(FIT_VERITY) + const char *algo; + const uint8_t *bin; + int len, i; + + algo = fdt_getprop(fit, noffset, FIT_VERITY_ALGO_PROP, NULL); + if (algo) + printf("%s Verity algo: %s\n", p, algo); + + bin = fdt_getprop(fit, noffset, FIT_VERITY_DIGEST_PROP, + &len); + if (bin && len > 0) { + printf("%s Verity hash: ", p); + for (i = 0; i < len; i++) + printf("%02x", bin[i]); + printf("\n"); + } + + bin = fdt_getprop(fit, noffset, FIT_VERITY_SALT_PROP, + &len); + if (bin && len > 0) { + printf("%s Verity salt: ", p); + for (i = 0; i < len; i++) + printf("%02x", bin[i]); + printf("\n"); + } +#endif +} + /** * fit_image_print_verification_data() - prints out the hash/signature details * @fit: pointer to the FIT format image header @@ -271,6 +307,11 @@ static void fit_image_print_verification_data(const void *fit, int noffset, strlen(FIT_SIG_NODENAME))) { fit_image_print_data(fit, noffset, p, "Sign"); } +#if defined(USE_HOSTCC) || CONFIG_IS_ENABLED(FIT_VERITY) + else if (!strcmp(name, FIT_VERITY_NODENAME)) { + fit_image_print_dm_verity(fit, noffset, p); + } +#endif } /** @@ -2642,3 +2683,299 @@ out: return fdt_noffset; } #endif + +#if !defined(USE_HOSTCC) && CONFIG_IS_ENABLED(FIT_VERITY) + +static const char *const verity_opt_props[] = { + FIT_VERITY_OPT_RESTART, + FIT_VERITY_OPT_PANIC, + FIT_VERITY_OPT_RERR, + FIT_VERITY_OPT_PERR, + FIT_VERITY_OPT_ONCE, +}; + +/** + * fit_verity_build_target() - build one dm-verity target specification + * @fit: pointer to the FIT blob + * @img_noffset: image node offset containing the dm-verity subnode + * @loadable_idx: index of this loadable (for /dev/fitN) + * @uname: unit name of the image + * @separator: true if a ";" prefix is needed (not the first target) + * @buf: output buffer, or NULL to measure only + * @bufsize: size of @buf (ignored when @buf is NULL) + * + * Parses all dm-verity properties from the image's ``dm-verity`` child + * node and writes (or measures) a dm target specification string of the + * form used by the ``dm-mod.create`` kernel parameter. + * + * Return: number of characters that would be written (excluding '\0'), + * or -ve errno on error (e.g. missing mandatory property) + */ +static int fit_verity_build_target(const void *fit, int img_noffset, + int loadable_idx, const char *uname, + bool separator, char *buf, int bufsize) +{ + const char *algorithm; + const u8 *digest_raw, *salt_raw; + const fdt32_t *val; + char *digest_hex = NULL, *salt_hex = NULL, *opt_buf = NULL; + int verity_node; + unsigned int data_block_size, hash_block_size; + int num_data_blocks, hash_start_block; + u64 data_sectors; + int digest_len, salt_len; + int opt_count, opt_off, opt_buf_size; + int len; + int i; + + verity_node = fdt_subnode_offset(fit, img_noffset, FIT_VERITY_NODENAME); + if (verity_node < 0) + return -ENOENT; + + /* Mandatory u32 properties */ + val = fdt_getprop(fit, verity_node, FIT_VERITY_DBS_PROP, NULL); + if (!val) + return -EINVAL; + data_block_size = fdt32_to_cpu(*val); + + val = fdt_getprop(fit, verity_node, FIT_VERITY_HBS_PROP, NULL); + if (!val) + return -EINVAL; + hash_block_size = fdt32_to_cpu(*val); + + val = fdt_getprop(fit, verity_node, FIT_VERITY_NBLK_PROP, NULL); + if (!val) + return -EINVAL; + num_data_blocks = fdt32_to_cpu(*val); + + val = fdt_getprop(fit, verity_node, FIT_VERITY_HBLK_PROP, NULL); + if (!val) + return -EINVAL; + hash_start_block = fdt32_to_cpu(*val); + + if (data_block_size < 512U || !is_power_of_2(data_block_size) || + hash_block_size < 512U || !is_power_of_2(hash_block_size) || + !num_data_blocks) + return -EINVAL; + + /* Mandatory string */ + algorithm = fdt_getprop(fit, verity_node, FIT_VERITY_ALGO_PROP, NULL); + if (!algorithm) + return -EINVAL; + + /* Mandatory byte arrays */ + digest_raw = fdt_getprop(fit, verity_node, FIT_VERITY_DIGEST_PROP, + &digest_len); + if (!digest_raw || digest_len <= 0) + return -EINVAL; + + salt_raw = fdt_getprop(fit, verity_node, FIT_VERITY_SALT_PROP, + &salt_len); + if (!salt_raw || salt_len <= 0) + return -EINVAL; + + /* Hex-encode digest and salt into dynamically sized buffers */ + digest_hex = malloc(digest_len * 2 + 1); + salt_hex = malloc(salt_len * 2 + 1); + if (!digest_hex || !salt_hex) { + len = -ENOMEM; + goto out; + } + *bin2hex(digest_hex, digest_raw, digest_len) = '\0'; + *bin2hex(salt_hex, salt_raw, salt_len) = '\0'; + + data_sectors = (u64)num_data_blocks * ((u64)data_block_size / 512); + + /* Compute space needed for optional boolean properties */ + opt_buf_size = 1; /* NUL terminator */ + for (i = 0; i < ARRAY_SIZE(verity_opt_props); i++) + opt_buf_size += strlen(verity_opt_props[i]) + 1; + opt_buf = malloc(opt_buf_size); + if (!opt_buf) { + len = -ENOMEM; + goto out; + } + + /* Collect optional boolean properties */ + opt_count = 0; + opt_off = 0; + opt_buf[0] = '\0'; + for (i = 0; i < ARRAY_SIZE(verity_opt_props); i++) { + if (fdt_getprop(fit, verity_node, + verity_opt_props[i], NULL)) { + const char *s = verity_opt_props[i]; + int slen = strlen(s); + + if (opt_off) + opt_buf[opt_off++] = ' '; + /* Copy with hyphen-to-underscore conversion */ + while (slen-- > 0) { + opt_buf[opt_off++] = + (*s == '-') ? '_' : *s; + s++; + } + opt_buf[opt_off] = '\0'; + opt_count++; + } + } + + /* Emit (or measure) the target spec */ + len = snprintf(buf, buf ? bufsize : 0, + "%s%s,,, ro,0 %llu verity 1 /dev/fit%d /dev/fit%d %u %u %d %d %s %s %s", + separator ? ";" : "", uname, + (unsigned long long)data_sectors, loadable_idx, loadable_idx, + data_block_size, hash_block_size, + num_data_blocks, hash_start_block, + algorithm, digest_hex, salt_hex); + if (opt_count) { + int extra = snprintf(buf ? buf + len : NULL, + buf ? bufsize - len : 0, + " %d %s", opt_count, opt_buf); + len += extra; + } + +out: + free(digest_hex); + free(salt_hex); + free(opt_buf); + return len; +} + +int fit_verity_build_cmdline(const void *fit, int conf_noffset, + struct bootm_headers *images) +{ + int images_noffset; + int dm_create_len = 0, dm_waitfor_len = 0; + char *dm_create = NULL, *dm_waitfor = NULL; + const char *uname; + int loadable_idx; + int found = 0; + int ret = 0; + + images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH); + if (images_noffset < 0) + return 0; + + for (loadable_idx = 0; + (uname = fdt_stringlist_get(fit, conf_noffset, + FIT_LOADABLE_PROP, + loadable_idx, NULL)); + loadable_idx++) { + int img_noffset, need; + u8 img_type; + char *tmp; + + img_noffset = fdt_subnode_offset(fit, images_noffset, uname); + if (img_noffset < 0) + continue; + + if (fit_image_get_type(fit, img_noffset, &img_type) || + img_type != IH_TYPE_FILESYSTEM) + continue; + + /* Measure first, then allocate and write */ + need = fit_verity_build_target(fit, img_noffset, + loadable_idx, uname, + found > 0, NULL, 0); + if (need == -ENOENT) + continue; /* no dm-verity subnode -- fine */ + if (need < 0) { + log_err("FIT: broken dm-verity metadata in '%s'\n", + uname); + ret = need; + goto err; + } + + tmp = realloc(dm_create, dm_create_len + need + 1); + if (!tmp) { + ret = -ENOMEM; + goto err; + } + dm_create = tmp; + fit_verity_build_target(fit, img_noffset, loadable_idx, + uname, found > 0, + dm_create + dm_create_len, + need + 1); + dm_create_len += need; + + /* Grow dm_waitfor buffer */ + need = snprintf(NULL, 0, "%s/dev/fit%d", + dm_waitfor_len ? "," : "", + loadable_idx); + tmp = realloc(dm_waitfor, dm_waitfor_len + need + 1); + if (!tmp) { + ret = -ENOMEM; + goto err; + } + dm_waitfor = tmp; + sprintf(dm_waitfor + dm_waitfor_len, "%s/dev/fit%d", + dm_waitfor_len ? "," : "", + loadable_idx); + dm_waitfor_len += need; + + found++; + } + + if (found) { + /* Transfer ownership to the bootm_headers */ + images->dm_mod_create = dm_create; + images->dm_mod_waitfor = dm_waitfor; + } else { + free(dm_create); + free(dm_waitfor); + } + + return 0; + +err: + free(dm_create); + free(dm_waitfor); + return ret; +} + +/** + * fmt used by both the measurement and the actual write of bootargs. + * Shared to guarantee they stay in sync. + */ +#define VERITY_BOOTARGS_FMT "%s%sdm-mod.create=\"%s\" dm-mod.waitfor=\"%s\"" + +int fit_verity_apply_bootargs(const struct bootm_headers *images) +{ + const char *existing; + char *newargs; + int len; + + if (!images->dm_mod_create) + return 0; + + existing = env_get("bootargs"); + if (!existing) + existing = ""; + + /* Measure */ + len = snprintf(NULL, 0, VERITY_BOOTARGS_FMT, + existing, existing[0] ? " " : "", + images->dm_mod_create, images->dm_mod_waitfor); + + newargs = malloc(len + 1); + if (!newargs) + return -ENOMEM; + + snprintf(newargs, len + 1, VERITY_BOOTARGS_FMT, + existing, existing[0] ? " " : "", + images->dm_mod_create, images->dm_mod_waitfor); + + env_set("bootargs", newargs); + free(newargs); + + return 0; +} + +void fit_verity_free(struct bootm_headers *images) +{ + free(images->dm_mod_create); + free(images->dm_mod_waitfor); + images->dm_mod_create = NULL; + images->dm_mod_waitfor = NULL; +} +#endif /* FIT_VERITY */ diff --git a/include/image.h b/include/image.h index 482446a8115..fe2361a667e 100644 --- a/include/image.h +++ b/include/image.h @@ -396,7 +396,19 @@ struct bootm_headers { ulong cmdline_start; ulong cmdline_end; struct bd_info *kbd; -#endif + +#if CONFIG_IS_ENABLED(FIT_VERITY) + /* + * dm-verity kernel command-line fragments, populated during FIT + * parsing by fit_verity_build_cmdline(). Bootmeths can check + * fit_verity_active() between bootm states, and + * fit_verity_apply_bootargs() appends these to the "bootargs" + * env var during BOOTM_STATE_OS_PREP. + */ + char *dm_mod_create; + char *dm_mod_waitfor; +#endif /* FIT_VERITY */ +#endif /* !USE_HOSTCC */ int verify; /* env_get("verify")[0] != 'n' */ @@ -756,6 +768,72 @@ int fit_image_load(struct bootm_headers *images, ulong addr, int arch, int image_ph_type, int bootstage_id, enum fit_load_op load_op, ulong *datap, ulong *lenp); +#if !defined(USE_HOSTCC) && CONFIG_IS_ENABLED(FIT_VERITY) +/** + * fit_verity_build_cmdline() - build dm-verity cmdline from FIT metadata + * @fit: pointer to the FIT blob + * @conf_noffset: configuration node offset in @fit + * @images: bootm headers; dm_mod_create / dm_mod_waitfor are + * populated on success + * + * Called automatically from boot_get_loadable() during FIT parsing. + * For each IH_TYPE_FILESYSTEM loadable with a dm-verity subnode, + * builds the corresponding dm target specification. + * + * Return: 0 on success, -ve errno on error + */ +int fit_verity_build_cmdline(const void *fit, int conf_noffset, + struct bootm_headers *images); + +/** + * fit_verity_apply_bootargs() - append dm-verity params to bootargs env + * @images: bootm headers with dm-verity cmdline fragments + * + * Called from BOOTM_STATE_OS_PREP before bootm_process_cmdline_env(). + * + * Return: 0 on success, -ve errno on error + */ +int fit_verity_apply_bootargs(const struct bootm_headers *images); + +/** + * fit_verity_active() - check whether dm-verity targets were found + * @images: bootm headers + * + * Return: true if at least one dm-verity target was built + */ +static inline bool fit_verity_active(const struct bootm_headers *images) +{ + return !!images->dm_mod_create; +} + +/** + * fit_verity_free() - free dm-verity cmdline allocations + * @images: bootm headers + */ +void fit_verity_free(struct bootm_headers *images); + +#else /* !FIT_VERITY */ + +static inline int fit_verity_build_cmdline(const void *fit, int conf_noffset, + struct bootm_headers *images) +{ + return 0; +} + +static inline int fit_verity_apply_bootargs(const struct bootm_headers *images) +{ + return 0; +} + +static inline bool fit_verity_active(const struct bootm_headers *images) +{ + return false; +} + +static inline void fit_verity_free(struct bootm_headers *images) {} + +#endif /* FIT_VERITY */ + /** * image_locate_script() - Locate the raw script in an image * -- cgit v1.3.1 From 96e180d354de563ce6dc68cbcac26d67f326940d Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 16 May 2026 00:37:59 +0100 Subject: include: hexdump: make hex2bin() usable from host tools Make hexdump.h work in host-tool builds by using 'uint8_t' instead of 'u8', and including either user-space libc for host-tools or when building U-Boot itself. Signed-off-by: Daniel Golle Reviewed-by: Simon Glass --- include/hexdump.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/hexdump.h b/include/hexdump.h index f2ca4793d69..5cb48d79efe 100644 --- a/include/hexdump.h +++ b/include/hexdump.h @@ -7,7 +7,11 @@ #ifndef HEXDUMP_H #define HEXDUMP_H +#ifdef USE_HOSTCC +#include +#else #include +#endif #include enum dump_prefix_t { @@ -20,7 +24,7 @@ extern const char hex_asc[]; #define hex_asc_lo(x) hex_asc[((x) & 0x0f)] #define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4] -static inline char *hex_byte_pack(char *buf, u8 byte) +static inline char *hex_byte_pack(char *buf, uint8_t byte) { *buf++ = hex_asc_hi(byte); *buf++ = hex_asc_lo(byte); @@ -52,7 +56,7 @@ static inline int hex_to_bin(char ch) * * Return 0 on success, -1 in case of bad input. */ -static inline int hex2bin(u8 *dst, const char *src, size_t count) +static inline int hex2bin(uint8_t *dst, const char *src, size_t count) { while (count--) { int hi = hex_to_bin(*src++); -- cgit v1.3.1 From 1e4829855234d8dc91c2840a79e9a64a2e8bf3a6 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 16 May 2026 00:38:07 +0100 Subject: tools: mkimage: add dm-verity Merkle-tree generation When mkimage encounters a dm-verity subnode inside a component image node it now automatically invokes veritysetup(8) with --no-superblock to generate the Merkle hash tree, screen-scrapes the Root hash and Salt from the tool output, and writes the computed properties back into the FIT blob. The user only needs to specify algorithm, data-block-size, and hash-block-size in the ITS; mkimage fills in digest, salt, num-data-blocks, and hash-start-block. Because --no-superblock is used, hash-start-block equals num-data-blocks with no off-by-one. The image data property is replaced with the expanded content (original data followed directly by the hash tree) so that subsequent hash and signature subnodes operate on the complete image. fit_image_add_verification_data() is restructured into two passes: dm-verity first (may grow data), then hashes and signatures. Signed-off-by: Daniel Golle Reviewed-by: Simon Glass --- include/image.h | 18 +++ tools/fit_image.c | 91 +++++++++++- tools/image-host.c | 414 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 514 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/image.h b/include/image.h index fe2361a667e..7b16284257a 100644 --- a/include/image.h +++ b/include/image.h @@ -1427,6 +1427,24 @@ int fit_add_verification_data(const char *keydir, const char *keyfile, const char *cmdname, const char *algo_name, struct image_summary *summary); +#ifdef USE_HOSTCC +/** + * fit_verity_get_expanded() - look up the cached dm-verity expanded buffer + * + * After mkimage has run veritysetup on a FILESYSTEM image, the original + * data concatenated with the Merkle hash tree is cached in memory keyed + * by image name. fit_extract_data() retrieves it to write the external + * data section without having to re-read a temporary file from disk. + * + * @name: image unit name (FDT node name under /images) + * @data: output -- pointer to cached buffer (do NOT free; lifetime + * ends when mkimage exits) + * @size: output -- size of @data in bytes + * Return: 0 if a cache entry exists for @name, -ENOENT otherwise + */ +int fit_verity_get_expanded(const char *name, const void **data, size_t *size); +#endif /* USE_HOSTCC */ + /** * fit_image_verify_with_data() - Verify an image with given data * diff --git a/tools/fit_image.c b/tools/fit_image.c index 1dbc14c63e4..b53088bf783 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -40,10 +40,10 @@ static int fit_estimate_hash_sig_size(struct image_tool_params *params, const ch return -EIO; /* - * Walk the FIT image, looking for nodes named hash* and - * signature*. Since the interesting nodes are subnodes of an - * image or configuration node, we are only interested in - * those at depth exactly 3. + * Walk the FIT image, looking for nodes named hash*, + * signature*, and dm-verity. Since the interesting nodes are + * subnodes of an image or configuration node, we are only + * interested in those at depth exactly 3. * * The estimate for a hash node is based on a sha512 digest * being 64 bytes, with another 64 bytes added to account for @@ -55,6 +55,10 @@ static int fit_estimate_hash_sig_size(struct image_tool_params *params, const ch * account for fdt overhead and the various other properties * (hashed-nodes etc.) that will also be filled in. * + * For a dm-verity node the small metadata properties (digest, + * salt, two u32s and a temp-file path) are written into the + * FDT by fit_image_process_verity(). + * * One could try to be more precise in the estimates by * looking at the "algo" property and, in the case of * configuration signatures, the sign-images property. Also, @@ -76,6 +80,18 @@ static int fit_estimate_hash_sig_size(struct image_tool_params *params, const ch if (signing && !strncmp(name, FIT_SIG_NODENAME, strlen(FIT_SIG_NODENAME))) estimate += 1024; + + if (!strcmp(name, FIT_VERITY_NODENAME)) { + if (!params->external_data) { + fprintf(stderr, + "%s: dm-verity requires external data (-E)\n", + params->cmdname); + munmap(fdt, sbuf.st_size); + close(fd); + return -EINVAL; + } + estimate += 256; + } } munmap(fdt, sbuf.st_size); @@ -470,6 +486,41 @@ static int fit_write_images(struct image_tool_params *params, char *fdt) return 0; } +/** + * fit_copy_image_data() - copy image data, using cached verity expansion + * @fdt: FIT blob + * @node: image node offset + * @buf: destination buffer + * @buf_ptr: write offset within @buf + * @data: embedded image data (used when no dm-verity expansion exists) + * @lenp: in/out: on entry, length of @data; on exit, bytes written + * + * When fit_image_process_verity() has run, the expanded image data + * (original + hash tree) is cached in memory. Look it up by image name + * and copy from the cached buffer rather than the embedded ``data`` + * property; fall back to @data otherwise. + * + * Return: 0 on success + */ +static int fit_copy_image_data(void *fdt, int node, void *buf, + int buf_ptr, const void *data, int *lenp) +{ + const char *image_name = fdt_get_name(fdt, node, NULL); + const void *vdata; + size_t vsize; + + if (image_name && + !fit_verity_get_expanded(image_name, &vdata, &vsize)) { + memcpy(buf + buf_ptr, vdata, vsize); + *lenp = vsize; + return 0; + } + + memcpy(buf + buf_ptr, data, *lenp); + + return 0; +} + /** * fit_write_configs() - Write out a list of configurations to the FIT * @@ -653,6 +704,8 @@ static int fit_extract_data(struct image_tool_params *params, const char *fname) int node; int align_size = 0; int len = 0; + int verity_extra = 0; + int orig_len; fd = mmap_fdt(params->cmdname, fname, 0, &fdt, &sbuf, false, false); if (fd < 0) @@ -686,11 +739,34 @@ static int fit_extract_data(struct image_tool_params *params, const char *fname) align_size += 4; } + /* + * When dm-verity is active the external data for an image is + * larger than the embedded data property (original + hash tree). + * Walk images once more and consult the in-memory cache for the + * actual expanded size. + */ + fdt_for_each_subnode(node, fdt, images) { + const char *image_name; + const void *vdata; + size_t vsize; + + orig_len = 0; + if (fdt_subnode_offset(fdt, node, FIT_VERITY_NODENAME) < 0) + continue; + image_name = fdt_get_name(fdt, node, NULL); + if (!image_name || + fit_verity_get_expanded(image_name, &vdata, &vsize)) + continue; + fdt_getprop(fdt, node, FIT_DATA_PROP, &orig_len); + if ((int)vsize > orig_len) + verity_extra += (int)vsize - orig_len; + } + /* * Allocate space to hold the image data we will extract, * extral space allocate for image alignment to prevent overflow. */ - buf = calloc(1, fit_size + align_size); + buf = calloc(1, fit_size + align_size + verity_extra); if (!buf) { ret = -ENOMEM; goto err_munmap; @@ -721,7 +797,10 @@ static int fit_extract_data(struct image_tool_params *params, const char *fname) data = fdt_getprop(fdt, node, FIT_DATA_PROP, &len); if (!data) continue; - memcpy(buf + buf_ptr, data, len); + + ret = fit_copy_image_data(fdt, node, buf, buf_ptr, data, &len); + if (ret) + goto err_munmap; debug("Extracting data size %x\n", len); ret = fdt_delprop(fdt, node, FIT_DATA_PROP); diff --git a/tools/image-host.c b/tools/image-host.c index 8b550af0dc1..8f1e7be4066 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -12,8 +12,12 @@ #include #include #include +#include #include +#include +#include + #if CONFIG_IS_ENABLED(FIT_SIGNATURE) #include #include @@ -626,6 +630,376 @@ int fit_image_cipher_data(const char *keydir, void *keydest, image_noffset, cipher_node_offset, data, size, cmdname); } +/* + * In-memory cache of dm-verity expanded buffers (original data followed + * by the Merkle hash tree), keyed by image unit name. Populated by + * fit_image_process_verity() and consumed by fit_extract_data() / + * fit_copy_image_data() so that the expanded content never leaves the + * mkimage process address space. + */ +struct fit_verity_blob { + char *name; + void *data; + size_t size; + struct fit_verity_blob *next; +}; + +static struct fit_verity_blob *fit_verity_blobs; + +/* Stash a malloc'd expanded buffer; takes ownership of @data on success. */ +static int fit_verity_stash(const char *name, void *data, size_t size) +{ + struct fit_verity_blob *b; + + b = calloc(1, sizeof(*b)); + if (!b) + return -ENOMEM; + b->name = strdup(name); + if (!b->name) { + free(b); + return -ENOMEM; + } + b->data = data; + b->size = size; + b->next = fit_verity_blobs; + fit_verity_blobs = b; + + return 0; +} + +int fit_verity_get_expanded(const char *name, const void **data, size_t *size) +{ + struct fit_verity_blob *b; + + for (b = fit_verity_blobs; b; b = b->next) { + if (!strcmp(b->name, name)) { + *data = b->data; + *size = b->size; + return 0; + } + } + + return -ENOENT; +} + +/** + * fit_image_process_verity() - Run veritysetup and fill dm-verity properties + * + * Extracts the embedded image data to a temporary file, runs + * ``veritysetup format`` to generate the Merkle hash tree (appended to the + * same file), parses Root hash / Salt from its stdout, and writes the + * computed properties (digest, salt, num-data-blocks, hash-start-block) + * back into the FIT dm-verity subnode. + * + * The expanded data (original data + hash tree) is read back into a + * malloc'd buffer and stashed in an in-memory cache keyed by @image_name + * via fit_verity_stash(). The same buffer is returned through + * @expanded_data / @expanded_size so that hash and signature subnodes + * can be computed over the complete image; the returned pointer is a + * *view* of the cached buffer and must not be freed by the caller. + * fit_extract_data() later retrieves the same buffer via + * fit_verity_get_expanded() to write the external data section. + * + * @fit: FIT blob (read-write) + * @image_name: image unit name (for diagnostics) + * @verity_noffset: dm-verity subnode offset + * @data: embedded image data + * @data_size: size of @data in bytes + * @expanded_data: output -- malloc'd buffer with expanded content + * @expanded_size: output -- size of @expanded_data + * Return: 0 on success, -ve on error (-ENOSPC when the FIT blob is full) + */ +static int fit_image_process_verity(void *fit, const char *image_name, + int verity_noffset, + const void *data, size_t data_size, + void **expanded_data, size_t *expanded_size) +{ + const char *algo_prop; + char algo[64]; + const fdt32_t *val; + unsigned int data_block_size, hash_block_size; + uint32_t num_data_blocks; + size_t hash_offset; + uint32_t hash_start_block; + char tmpfile[] = "/tmp/mkimage-verity-XXXXXX"; + char dbs_arg[32], hbs_arg[32], algo_arg[80], hoff_arg[40]; + int pipefd[2]; + pid_t pid; + FILE *fp; + char line[256]; + char *colon, *value, *end; + char root_hash_hex[256] = {0}; + char salt_hex[256] = {0}; + uint8_t digest_bin[FIT_MAX_HASH_LEN]; + uint8_t salt_bin[FIT_MAX_HASH_LEN]; + int digest_len = 0, salt_len = 0; + void *expanded = NULL; + struct stat st; + int fd, ret; + + *expanded_data = NULL; + *expanded_size = 0; + + algo_prop = fdt_getprop(fit, verity_noffset, FIT_VERITY_ALGO_PROP, + NULL); + if (!algo_prop) { + fprintf(stderr, + "Missing '%s' in dm-verity node of '%s'\n", + FIT_VERITY_ALGO_PROP, image_name); + return -EINVAL; + } + /* Local copy -- the FDT pointer goes stale after fdt_setprop(). */ + snprintf(algo, sizeof(algo), "%s", algo_prop); + + val = fdt_getprop(fit, verity_noffset, FIT_VERITY_DBS_PROP, NULL); + if (!val) { + fprintf(stderr, + "Missing '%s' in dm-verity node of '%s'\n", + FIT_VERITY_DBS_PROP, image_name); + return -EINVAL; + } + data_block_size = fdt32_to_cpu(*val); + + val = fdt_getprop(fit, verity_noffset, FIT_VERITY_HBS_PROP, NULL); + if (!val) { + fprintf(stderr, + "Missing '%s' in dm-verity node of '%s'\n", + FIT_VERITY_HBS_PROP, image_name); + return -EINVAL; + } + hash_block_size = fdt32_to_cpu(*val); + + if (data_block_size < 512 || (data_block_size & (data_block_size - 1)) || + hash_block_size < 512 || (hash_block_size & (hash_block_size - 1))) { + fprintf(stderr, + "Block sizes must be >= 512 and a power of two in dm-verity node of '%s'\n", + image_name); + return -EINVAL; + } + + if (data_size % data_block_size) { + fprintf(stderr, + "Image '%s' size %zu not a multiple of data-block-size %d\n", + image_name, data_size, data_block_size); + return -EINVAL; + } + + if (data_size / data_block_size > UINT32_MAX || + data_size / hash_block_size > UINT32_MAX) { + fprintf(stderr, + "Image '%s' too large for dm-verity (> 2^32 blocks)\n", + image_name); + return -EINVAL; + } + num_data_blocks = data_size / data_block_size; + hash_offset = data_size; + + fd = mkstemp(tmpfile); + if (fd < 0) { + fprintf(stderr, "Can't create temp file: %s\n", + strerror(errno)); + return -EIO; + } + + if (write(fd, data, data_size) != (ssize_t)data_size) { + fprintf(stderr, "Can't write temp file: %s\n", + strerror(errno)); + ret = -EIO; + goto err_unlink; + } + close(fd); + fd = -1; + + /* + * Invoke veritysetup via fork/execvp -- no shell, so each argument + * goes verbatim to the binary and the algo string cannot inject + * additional commands no matter how crafted the .its is. + */ + snprintf(algo_arg, sizeof(algo_arg), "--hash=%s", algo); + snprintf(dbs_arg, sizeof(dbs_arg), "--data-block-size=%u", + data_block_size); + snprintf(hbs_arg, sizeof(hbs_arg), "--hash-block-size=%u", + hash_block_size); + snprintf(hoff_arg, sizeof(hoff_arg), "--hash-offset=%zu", hash_offset); + + if (pipe(pipefd) < 0) { + fprintf(stderr, "Can't create pipe: %s\n", strerror(errno)); + ret = -EIO; + goto err_unlink; + } + + pid = fork(); + if (pid < 0) { + fprintf(stderr, "Can't fork: %s\n", strerror(errno)); + close(pipefd[0]); + close(pipefd[1]); + ret = -EIO; + goto err_unlink; + } + + if (pid == 0) { + /* child: redirect stdout+stderr to pipe write-end, then exec */ + char *argv[] = { + "veritysetup", "format", tmpfile, tmpfile, + "--no-superblock", algo_arg, dbs_arg, hbs_arg, + hoff_arg, NULL, + }; + + close(pipefd[0]); + if (dup2(pipefd[1], STDOUT_FILENO) < 0 || + dup2(pipefd[1], STDERR_FILENO) < 0) + _exit(127); + close(pipefd[1]); + execvp(argv[0], argv); + fprintf(stderr, "Can't exec veritysetup: %s\n", + strerror(errno)); + _exit(127); + } + + /* parent: parse key: value lines from veritysetup stdout */ + close(pipefd[1]); + fp = fdopen(pipefd[0], "r"); + if (!fp) { + fprintf(stderr, "Can't fdopen veritysetup pipe: %s\n", + strerror(errno)); + close(pipefd[0]); + waitpid(pid, NULL, 0); + ret = -EIO; + goto err_unlink; + } + + while (fgets(line, sizeof(line), fp)) { + colon = strchr(line, ':'); + if (!colon) + continue; + value = colon + 1; + while (*value == ' ' || *value == '\t') + value++; + end = value + strlen(value) - 1; + while (end > value && (*end == '\n' || *end == '\r' || + *end == ' ')) + *end-- = '\0'; + + if (!strncmp(line, "Root hash:", 10)) + snprintf(root_hash_hex, sizeof(root_hash_hex), + "%s", value); + else if (!strncmp(line, "Salt:", 5)) + snprintf(salt_hex, sizeof(salt_hex), "%s", value); + } + fclose(fp); + + if (waitpid(pid, &ret, 0) < 0 || !WIFEXITED(ret) || + WEXITSTATUS(ret) != 0) { + fprintf(stderr, "veritysetup failed for '%s'\n", image_name); + ret = -EIO; + goto err_unlink; + } + + if (!root_hash_hex[0] || !salt_hex[0]) { + fprintf(stderr, "Failed to parse veritysetup output for '%s'\n", + image_name); + ret = -EIO; + goto err_unlink; + } + + digest_len = strlen(root_hash_hex) / 2; + salt_len = strlen(salt_hex) / 2; + + if (digest_len > (int)sizeof(digest_bin) || + salt_len > (int)sizeof(salt_bin)) { + fprintf(stderr, "Hash/salt too long for '%s'\n", image_name); + ret = -EINVAL; + goto err_unlink; + } + + if (hex2bin(digest_bin, root_hash_hex, digest_len) || + hex2bin(salt_bin, salt_hex, salt_len)) { + fprintf(stderr, "Invalid hex in veritysetup output for '%s'\n", + image_name); + ret = -EINVAL; + goto err_unlink; + } + + if (stat(tmpfile, &st)) { + fprintf(stderr, "Can't stat temp file: %s\n", + strerror(errno)); + ret = -EIO; + goto err_unlink; + } + + expanded = malloc(st.st_size); + if (!expanded) { + ret = -ENOMEM; + goto err_unlink; + } + + fd = open(tmpfile, O_RDONLY); + if (fd < 0 || read(fd, expanded, st.st_size) != st.st_size) { + fprintf(stderr, "Can't read back temp file: %s\n", + strerror(errno)); + ret = -EIO; + goto err_free; + } + close(fd); + fd = -1; + + /* Temp file is no longer needed -- expanded buffer lives in memory. */ + unlink(tmpfile); + + /* hash tree starts immediately after data (no superblock) */ + hash_start_block = hash_offset / hash_block_size; + + ret = fdt_setprop(fit, verity_noffset, FIT_VERITY_DIGEST_PROP, + digest_bin, digest_len); + if (ret) { + ret = (ret == -FDT_ERR_NOSPACE) ? -ENOSPC : -EIO; + goto err_free; + } + + ret = fdt_setprop(fit, verity_noffset, FIT_VERITY_SALT_PROP, + salt_bin, salt_len); + if (ret) { + ret = (ret == -FDT_ERR_NOSPACE) ? -ENOSPC : -EIO; + goto err_free; + } + + ret = fdt_setprop_u32(fit, verity_noffset, FIT_VERITY_NBLK_PROP, + num_data_blocks); + if (ret) { + ret = (ret == -FDT_ERR_NOSPACE) ? -ENOSPC : -EIO; + goto err_free; + } + + ret = fdt_setprop_u32(fit, verity_noffset, FIT_VERITY_HBLK_PROP, + hash_start_block); + if (ret) { + ret = (ret == -FDT_ERR_NOSPACE) ? -ENOSPC : -EIO; + goto err_free; + } + + /* + * Stash the expanded buffer in the in-process cache; fit_extract_data() + * looks it up via fit_verity_get_expanded() to populate the external + * data section. On success the cache takes ownership of @expanded. + */ + ret = fit_verity_stash(image_name, expanded, st.st_size); + if (ret) + goto err_free; + + *expanded_data = expanded; + *expanded_size = st.st_size; + + return 0; + +err_free: + free(expanded); +err_unlink: + if (fd >= 0) + close(fd); + unlink(tmpfile); + return ret; +} + /** * fit_image_add_verification_data() - calculate/set verig. data for image node * @@ -652,6 +1026,8 @@ int fit_image_cipher_data(const char *keydir, void *keydest, * * For signature details, please see doc/usage/fit/signature.rst * + * For dm-verity details, please see doc/usage/fit/dm-verity.rst + * * @keydir Directory containing *.key and *.crt files (or NULL) * @keydest FDT Blob to write public keys into (NULL if none) * @fit: Pointer to the FIT format image header @@ -667,9 +1043,16 @@ int fit_image_add_verification_data(const char *keydir, const char *keyfile, const char *cmdname, const char* algo_name) { const char *image_name; + const char *node_name; const void *data; size_t size; + /* + * View pointer into the dm-verity cache (owned by image-host.c). + * Do not free; the cache lives until mkimage exits. + */ + void *verity_data = NULL; int noffset; + int ret; /* Get image data and data length */ if (fit_image_get_emb_data(fit, image_noffset, &data, &size)) { @@ -679,13 +1062,38 @@ int fit_image_add_verification_data(const char *keydir, const char *keyfile, image_name = fit_get_name(fit, image_noffset, NULL); - /* Process all hash subnodes of the component image node */ + /* + * Pass 1 -- dm-verity: run veritysetup to produce the Merkle + * hash tree and fill in computed metadata. The expanded + * content (original data + hash tree) is returned in + * verity_data so that pass 2 hashes the complete image. + */ for (noffset = fdt_first_subnode(fit, image_noffset); noffset >= 0; noffset = fdt_next_subnode(fit, noffset)) { - const char *node_name; - int ret = 0; + if (!strcmp(fit_get_name(fit, noffset, NULL), + FIT_VERITY_NODENAME)) { + ret = fit_image_process_verity(fit, image_name, + noffset, + data, size, + &verity_data, + &size); + if (ret) + return ret; + if (verity_data) + data = verity_data; + break; + } + } + /* + * Pass 2 -- hashes and signatures: compute over the (possibly + * expanded) image data. + */ + for (noffset = fdt_first_subnode(fit, image_noffset); + noffset >= 0; + noffset = fdt_next_subnode(fit, noffset)) { + ret = 0; /* * Check subnode name, must be equal to "hash" or "signature". * Multiple hash nodes require unique unit node -- cgit v1.3.1 From 2b6d243be22885e6f54eb79724c9d54db1ad03b4 Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Mon, 18 May 2026 13:52:52 +0530 Subject: env: ti: k3_dfu: load only the next stage binary In the TI's K3 bootflow of tiboot3.bin -> tispl.bin -> u-boot.img: (R5 SPL) (A53 SPL) We currently provide a common dfu_alt_info_ram for both R5 SPL and A53 SPL which is not intuitive in a regular bootflow where each binary should only request it's immediate next stage. This patch updates dfu_alt_info_ram such that the R5 SPL would only request for tispl.bin and A53 SPL would only request u-boot.img. Signed-off-by: Anshul Dalal --- board/ti/am62x/am6254atl.env | 5 ++++- include/env/ti/k3_dfu.env | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/ti/am62x/am6254atl.env b/board/ti/am62x/am6254atl.env index ea5a33d8cc3..dabc77245d4 100644 --- a/board/ti/am62x/am6254atl.env +++ b/board/ti/am62x/am6254atl.env @@ -28,8 +28,11 @@ splashpos=m,m splashsource=sf dfu_alt_info_ram= - tispl.bin ram 0x82000000 0x200000; +#if CONFIG_ARM64 u-boot.img ram 0x82f80000 0x400000 +#else + tispl.bin ram 0x82000000 0x200000 +#endif #if CONFIG_BOOTMETH_ANDROID #include diff --git a/include/env/ti/k3_dfu.env b/include/env/ti/k3_dfu.env index b42cf21d986..0f82a8afb42 100644 --- a/include/env/ti/k3_dfu.env +++ b/include/env/ti/k3_dfu.env @@ -25,6 +25,9 @@ dfu_alt_info_ospi= rootfs raw 0x800000 0x3800000 dfu_alt_info_ram= - tispl.bin ram 0x80080000 0x200000; +#if CONFIG_ARM64 u-boot.img ram 0x81000000 0x400000 +#else + tispl.bin ram 0x80080000 0x200000 +#endif -- cgit v1.3.1 From 1ea8b3e8e2d6c80469b5f082cc5f2b9287a7ddf5 Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Mon, 18 May 2026 13:52:53 +0530 Subject: env: ti: k3_dfu: use Kconfig options for addresses The load addresses for DFU download binaries were hardcoded for K3 devices which required redefinition of such env for boards that deviated from the expected K3 memory map (such as AM6254atl EMV). This patch replaces the hardcoded addresses with their corresponding Kconfig options making the k3_dfu.env more general. Signed-off-by: Anshul Dalal --- board/ti/am62x/am6254atl.env | 7 ------- include/env/ti/k3_dfu.env | 4 ++-- 2 files changed, 2 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/board/ti/am62x/am6254atl.env b/board/ti/am62x/am6254atl.env index dabc77245d4..a9187c2b1aa 100644 --- a/board/ti/am62x/am6254atl.env +++ b/board/ti/am62x/am6254atl.env @@ -27,13 +27,6 @@ splashimage=0x82180000 splashpos=m,m splashsource=sf -dfu_alt_info_ram= -#if CONFIG_ARM64 - u-boot.img ram 0x82f80000 0x400000 -#else - tispl.bin ram 0x82000000 0x200000 -#endif - #if CONFIG_BOOTMETH_ANDROID #include adtb_idx=0 diff --git a/include/env/ti/k3_dfu.env b/include/env/ti/k3_dfu.env index 0f82a8afb42..1ae9ae6ae15 100644 --- a/include/env/ti/k3_dfu.env +++ b/include/env/ti/k3_dfu.env @@ -26,8 +26,8 @@ dfu_alt_info_ospi= dfu_alt_info_ram= #if CONFIG_ARM64 - u-boot.img ram 0x81000000 0x400000 + u-boot.img ram CONFIG_SPL_LOAD_FIT_ADDRESS 0x400000 #else - tispl.bin ram 0x80080000 0x200000 + tispl.bin ram CONFIG_SPL_LOAD_FIT_ADDRESS 0x200000 #endif -- cgit v1.3.1 From ef5b4a7eae278afd2fa173f886159983a81db096 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 13 May 2026 09:19:02 +0200 Subject: include: env: phytec: Drop legacy RAUC boot logic RAUC slot selection is now handled by the RAUC bootmeth, which all phytec K3 boards use. Remove the unused env-based logic. Signed-off-by: Wadim Egorov Reviewed-by: Martin Schwan --- include/env/phytec/k3_mmc.env | 4 +--- include/env/phytec/rauc.env | 52 ------------------------------------------- 2 files changed, 1 insertion(+), 55 deletions(-) delete mode 100644 include/env/phytec/rauc.env (limited to 'include') diff --git a/include/env/phytec/k3_mmc.env b/include/env/phytec/k3_mmc.env index 95d0204b6da..8129b35ea5e 100644 --- a/include/env/phytec/k3_mmc.env +++ b/include/env/phytec/k3_mmc.env @@ -7,15 +7,13 @@ /* Logic for TI K3 based SoCs to boot from a MMC device. */ #include -#include mmcargs=setenv bootargs console=${console} earlycon=${earlycon} - root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw + root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw ${optargs} mmcloadimage=load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} Image mmcloadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} mmcboot=echo DEPRECATION WARNING: mmcboot will be removed in future versions. Use standard boot instead.; - if test ${doraucboot} = 1; then run raucinit; fi; run mmcargs; mmc dev ${mmcdev}; mmc rescan; diff --git a/include/env/phytec/rauc.env b/include/env/phytec/rauc.env deleted file mode 100644 index 89e17ff70ec..00000000000 --- a/include/env/phytec/rauc.env +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -/* Logic to select a boot partition based on environment variables and switch - * to the other if the boot fails. */ - -doraucboot=0 - -raucbootpart0=1 -raucrootpart0=5 -raucbootpart1=2 -raucrootpart1=6 - -raucinit= - echo Booting RAUC A/B system; - test -n "${BOOT_ORDER}" || env set BOOT_ORDER "system0 system1"; - test -n "${BOOT_system0_LEFT}" || env set BOOT_system0_LEFT 3; - test -n "${BOOT_system1_LEFT}" || env set BOOT_system1_LEFT 3; - env set raucstatus; - for BOOT_SLOT in "${BOOT_ORDER}"; do - if test "x${raucstatus}" != "x"; then - echo Skipping remaing slots!; - elif test "x${BOOT_SLOT}" = "xsystem0"; then - if test ${BOOT_system0_LEFT} -gt 0; then - echo Found valid slot A, ${BOOT_system0_LEFT} attempts remaining; - setexpr BOOT_system0_LEFT ${BOOT_system0_LEFT} - 1; - env set mmcpart ${raucbootpart0}; - env set mmcroot ${raucrootpart0}; - env set raucargs rauc.slot=system0; - env set raucstatus success; - fi; - elif test "x${BOOT_SLOT}" = "xsystem1"; then - if test ${BOOT_system1_LEFT} -gt 0; then - echo Found valid slot B, ${BOOT_system1_LEFT} attempts remaining; - setexpr BOOT_system1_LEFT ${BOOT_system1_LEFT} - 1; - env set mmcpart ${raucbootpart1}; - env set mmcroot ${raucrootpart1}; - env set raucargs rauc.slot=system1; - env set raucstatus success; - fi; - fi; - done; - if test -n "${raucstatus}"; then - env delete raucstatus; - env save; - else - echo WARN: No valid slot found; - env set BOOT_system0_LEFT 3; - env set BOOT_system1_LEFT 3; - env delete raucstatus; - env save; - reset; - fi; -- cgit v1.3.1 From 5cf4b1428485048bed4b53ed600c17bae016dd8c Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Tue, 12 May 2026 23:31:50 +0400 Subject: video console: add 6x8 console font from linux Small screens on the order of 256x144 pixels can't fit much text at 8x16, and 4x6 is virtually illegible, so add an in-between 6x8 font from Linux. Font data obtained from lib/fonts/font_6x8.c in the Linux kernel at commit db65872b38dc ("lib/fonts: Remove internal symbols and macros from public header file") Link: https://github.com/torvalds/linux/blob/db65872b38dc9f18a62669d6ae1e4ec7868a85a9/lib/fonts/font_6x8.c Signed-off-by: Alexey Charkov --- drivers/video/Kconfig | 7 + include/video_font.h | 6 + include/video_font_6x8.h | 2578 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 2591 insertions(+) create mode 100644 include/video_font_6x8.h (limited to 'include') diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 25475ef8fd7..5a0dfb159c4 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -29,6 +29,13 @@ config VIDEO_FONT_4X6 Provides character bitmap data in header file. When selecting multiple fonts, you may want to enable CMD_SELECT_FONT too. +config VIDEO_FONT_6X8 + bool "6 x 8 font size" + help + Font for video console driver, 6 x 8 pixels. + Provides character bitmap data in header file. + When selecting multiple fonts, you may want to enable CMD_SELECT_FONT too. + config VIDEO_FONT_8X16 bool "8 x 16 font size" default y diff --git a/include/video_font.h b/include/video_font.h index 05d3f989a77..4bfb00eb80f 100644 --- a/include/video_font.h +++ b/include/video_font.h @@ -12,6 +12,9 @@ #if defined(CONFIG_VIDEO_FONT_4X6) #include #endif +#if defined(CONFIG_VIDEO_FONT_6X8) +#include +#endif #if defined(CONFIG_VIDEO_FONT_8X16) #include #endif @@ -29,6 +32,9 @@ static struct video_fontdata __maybe_unused fonts[] = { #if defined(CONFIG_VIDEO_FONT_4X6) FONT_ENTRY(4, 6, 4x6), #endif +#if defined(CONFIG_VIDEO_FONT_6X8) + FONT_ENTRY(6, 8, 6x8), +#endif #if defined(CONFIG_VIDEO_FONT_SUN12X22) FONT_ENTRY(12, 22, 12x22), #endif diff --git a/include/video_font_6x8.h b/include/video_font_6x8.h new file mode 100644 index 00000000000..db5ec4cbe5e --- /dev/null +++ b/include/video_font_6x8.h @@ -0,0 +1,2578 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * 6x8 bitmap font from the Linux kernel adapted for U-boot video console + * + * Original Linux file at lib/fonts/font_6x8.c retrieved at Linux commit + * db65872b38dc ("lib/fonts: Remove internal symbols and macros from public + * header file") + */ + +#ifndef _VIDEO_FONT_6X8_ +#define _VIDEO_FONT_6X8_ + +#include + +static unsigned char video_fontdata_6x8[VIDEO_FONT_SIZE(256, 6, 8)] = { + /* 0 0x00 '^@' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 1 0x01 '^A' */ + 0x78, /* 011110 */ + 0x84, /* 100001 */ + 0xCC, /* 110011 */ + 0x84, /* 100001 */ + 0xCC, /* 110011 */ + 0xB4, /* 101101 */ + 0x78, /* 011110 */ + 0x00, /* 000000 */ + + /* 2 0x02 '^B' */ + 0x78, /* 011110 */ + 0xFC, /* 111111 */ + 0xB4, /* 101101 */ + 0xFC, /* 111111 */ + 0xB4, /* 101101 */ + 0xCC, /* 110011 */ + 0x78, /* 011110 */ + 0x00, /* 000000 */ + + /* 3 0x03 '^C' */ + 0x00, /* 000000 */ + 0x28, /* 001010 */ + 0x7C, /* 011111 */ + 0x7C, /* 011111 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 4 0x04 '^D' */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x7C, /* 011111 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 5 0x05 '^E' */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x6C, /* 011011 */ + 0x6C, /* 011011 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 6 0x06 '^F' */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x7C, /* 011111 */ + 0x7C, /* 011111 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 7 0x07 '^G' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x78, /* 011110 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 8 0x08 '^H' */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xCC, /* 110011 */ + 0x84, /* 100001 */ + 0xCC, /* 110011 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + + /* 9 0x09 '^I' */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x48, /* 010010 */ + 0x84, /* 100001 */ + 0x48, /* 010010 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 10 0x0A '^J' */ + 0xFC, /* 111111 */ + 0xCC, /* 110011 */ + 0xB4, /* 101101 */ + 0x78, /* 011110 */ + 0xB4, /* 101101 */ + 0xCC, /* 110011 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + + /* 11 0x0B '^K' */ + 0x3C, /* 001111 */ + 0x14, /* 000101 */ + 0x20, /* 001000 */ + 0x78, /* 011110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 12 0x0C '^L' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 13 0x0D '^M' */ + 0x18, /* 000110 */ + 0x14, /* 000101 */ + 0x14, /* 000101 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x70, /* 011100 */ + 0x60, /* 011000 */ + 0x00, /* 000000 */ + + /* 14 0x0E '^N' */ + 0x3C, /* 001111 */ + 0x24, /* 001001 */ + 0x3C, /* 001111 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x6C, /* 011011 */ + 0x6C, /* 011011 */ + 0x00, /* 000000 */ + + /* 15 0x0F '^O' */ + 0x10, /* 000100 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x6C, /* 011011 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 16 0x10 '^P' */ + 0x40, /* 010000 */ + 0x60, /* 011000 */ + 0x70, /* 011100 */ + 0x78, /* 011110 */ + 0x70, /* 011100 */ + 0x60, /* 011000 */ + 0x40, /* 010000 */ + 0x00, /* 000000 */ + + /* 17 0x11 '^Q' */ + 0x04, /* 000001 */ + 0x0C, /* 000011 */ + 0x1C, /* 000111 */ + 0x3C, /* 001111 */ + 0x1C, /* 000111 */ + 0x0C, /* 000011 */ + 0x04, /* 000001 */ + 0x00, /* 000000 */ + + /* 18 0x12 '^R' */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x10, /* 000100 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 19 0x13 '^S' */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x00, /* 000000 */ + 0x48, /* 010010 */ + 0x00, /* 000000 */ + + /* 20 0x14 '^T' */ + 0x3C, /* 001111 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x3C, /* 001111 */ + 0x14, /* 000101 */ + 0x14, /* 000101 */ + 0x14, /* 000101 */ + 0x00, /* 000000 */ + + /* 21 0x15 '^U' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x30, /* 001100 */ + 0x28, /* 001010 */ + 0x14, /* 000101 */ + 0x0C, /* 000011 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + + /* 22 0x16 '^V' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xF8, /* 111110 */ + 0xF8, /* 111110 */ + 0xF8, /* 111110 */ + 0x00, /* 000000 */ + + /* 23 0x17 '^W' */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x10, /* 000100 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x7C, /* 011111 */ + + /* 24 0x18 '^X' */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 25 0x19 '^Y' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 26 0x1A '^Z' */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x7C, /* 011111 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 27 0x1B '^[' */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x7C, /* 011111 */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 28 0x1C '^\' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x78, /* 011110 */ + 0x00, /* 000000 */ + + /* 29 0x1D '^]' */ + 0x00, /* 000000 */ + 0x48, /* 010010 */ + 0x84, /* 100001 */ + 0xFC, /* 111111 */ + 0x84, /* 100001 */ + 0x48, /* 010010 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 30 0x1E '^^' */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x7C, /* 011111 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 31 0x1F '^_' */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x7C, /* 011111 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 32 0x20 ' ' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 33 0x21 '!' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 34 0x22 '"' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 35 0x23 '#' */ + 0x00, /* 000000 */ + 0x28, /* 001010 */ + 0x7C, /* 011111 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x7C, /* 011111 */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + + /* 36 0x24 '$' */ + 0x10, /* 000000 */ + 0x38, /* 001000 */ + 0x40, /* 010000 */ + 0x30, /* 001000 */ + 0x08, /* 000000 */ + 0x70, /* 011000 */ + 0x20, /* 001000 */ + 0x00, /* 000000 */ + + /* 37 0x25 '%' */ + 0x64, /* 011001 */ + 0x64, /* 011001 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x4C, /* 010011 */ + 0x4C, /* 010011 */ + 0x00, /* 000000 */ + + /* 38 0x26 '&' */ + 0x30, /* 001100 */ + 0x48, /* 010010 */ + 0x50, /* 010100 */ + 0x20, /* 001000 */ + 0x54, /* 010101 */ + 0x48, /* 010010 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 39 0x27 ''' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 40 0x28 '(' */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x20, /* 001000 */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x00, /* 000000 */ + + /* 41 0x29 ')' */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x00, /* 000000 */ + + /* 42 0x2A '*' */ + 0x10, /* 000100 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 43 0x2B '+' */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x7C, /* 011111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 44 0x2C ',' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x30, /* 001100 */ + 0x20, /* 001000 */ + + /* 45 0x2D '-' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 46 0x2E '.' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x18, /* 000110 */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + + /* 47 0x2F '/' */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x20, /* 001000 */ + 0x40, /* 010000 */ + + /* 48 0x30 '0' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x54, /* 010101 */ + 0x64, /* 011001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 49 0x31 '1' */ + 0x10, /* 000100 */ + 0x30, /* 001100 */ + 0x50, /* 010100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 50 0x32 '2' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 51 0x33 '3' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x04, /* 000001 */ + 0x18, /* 000110 */ + 0x04, /* 000001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 52 0x34 '4' */ + 0x08, /* 000010 */ + 0x18, /* 000110 */ + 0x28, /* 001010 */ + 0x48, /* 010010 */ + 0x7C, /* 011111 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x00, /* 000000 */ + + /* 53 0x35 '5' */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x78, /* 011110 */ + 0x04, /* 000001 */ + 0x04, /* 000001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 54 0x36 '6' */ + 0x18, /* 000110 */ + 0x20, /* 001000 */ + 0x40, /* 010000 */ + 0x78, /* 011110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 55 0x37 '7' */ + 0x7C, /* 011111 */ + 0x04, /* 000001 */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 56 0x38 '8' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 57 0x39 '9' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + + /* 58 0x3A ':' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x18, /* 000110 */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x18, /* 000110 */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + + /* 59 0x3B ';' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x30, /* 001100 */ + 0x20, /* 001000 */ + + /* 60 0x3C '<' */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x04, /* 000001 */ + 0x00, /* 000000 */ + + /* 61 0x3D '=' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 62 0x3E '>' */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x00, /* 000000 */ + + /* 63 0x3F '?' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 64 0x40 '@' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x5C, /* 010111 */ + 0x54, /* 010101 */ + 0x5C, /* 010111 */ + 0x40, /* 010000 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 65 0x41 'A' */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 66 0x42 'B' */ + 0x78, /* 011110 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x38, /* 001110 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x78, /* 011110 */ + 0x00, /* 000000 */ + + /* 67 0x43 'C' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 68 0x44 'D' */ + 0x78, /* 011110 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x78, /* 011110 */ + 0x00, /* 000000 */ + + /* 69 0x45 'E' */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x78, /* 011110 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 70 0x46 'F' */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x78, /* 011110 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x00, /* 000000 */ + + /* 71 0x47 'G' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x40, /* 010000 */ + 0x5C, /* 010111 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 72 0x48 'H' */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 73 0x49 'I' */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 74 0x4A 'J' */ + 0x1C, /* 000111 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + + /* 75 0x4B 'K' */ + 0x44, /* 010001 */ + 0x48, /* 010010 */ + 0x50, /* 010100 */ + 0x60, /* 011000 */ + 0x50, /* 010100 */ + 0x48, /* 010010 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 76 0x4C 'L' */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 77 0x4D 'M' */ + 0x44, /* 010001 */ + 0x6C, /* 011011 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 78 0x4E 'N' */ + 0x44, /* 010001 */ + 0x64, /* 011001 */ + 0x54, /* 010101 */ + 0x4C, /* 010011 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 79 0x4F 'O' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 80 0x50 'P' */ + 0x78, /* 011110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x78, /* 011110 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x00, /* 000000 */ + + /* 81 0x51 'Q' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x54, /* 010101 */ + 0x48, /* 010010 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 82 0x52 'R' */ + 0x78, /* 011110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x78, /* 011110 */ + 0x50, /* 010100 */ + 0x48, /* 010010 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 83 0x53 'S' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x40, /* 010000 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 84 0x54 'T' */ + 0x7C, /* 011111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 85 0x55 'U' */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 86 0x56 'V' */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x28, /* 001010 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 87 0x57 'W' */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x6C, /* 011011 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 88 0x58 'X' */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x28, /* 001010 */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 89 0x59 'Y' */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x28, /* 001010 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 90 0x5A 'Z' */ + 0x7C, /* 011111 */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x40, /* 010000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 91 0x5B '[' */ + 0x18, /* 000110 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + + /* 92 0x5C '\' */ + 0x40, /* 010000 */ + 0x20, /* 001000 */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x04, /* 000001 */ + + /* 93 0x5D ']' */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + + /* 94 0x5E '^' */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 95 0x5F '_' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + + /* 96 0x60 '`' */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 97 0x61 'a' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 98 0x62 'b' */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x58, /* 010110 */ + 0x64, /* 011001 */ + 0x44, /* 010001 */ + 0x64, /* 011001 */ + 0x58, /* 010110 */ + 0x00, /* 000000 */ + + /* 99 0x63 'c' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x40, /* 010000 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 100 0x64 'd' */ + 0x04, /* 000001 */ + 0x04, /* 000001 */ + 0x34, /* 001101 */ + 0x4C, /* 010011 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 101 0x65 'e' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 102 0x66 'f' */ + 0x0C, /* 000011 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 103 0x67 'g' */ + 0x00, /* 000000 */ + 0x34, /* 001101 */ + 0x4C, /* 010011 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x04, /* 000001 */ + 0x38, /* 001110 */ + + /* 104 0x68 'h' */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x78, /* 011110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 105 0x69 'i' */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 106 0x6A 'j' */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x60, /* 011000 */ + + /* 107 0x6B 'k' */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x48, /* 010010 */ + 0x50, /* 010100 */ + 0x70, /* 011100 */ + 0x48, /* 010010 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 108 0x6C 'l' */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 109 0x6D 'm' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x68, /* 011010 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x00, /* 000000 */ + + /* 110 0x6E 'n' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x58, /* 010110 */ + 0x64, /* 011001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 111 0x6F 'o' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 112 0x70 'p' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x78, /* 011110 */ + 0x44, /* 010001 */ + 0x64, /* 011001 */ + 0x58, /* 010110 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + + /* 113 0x71 'q' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x04, /* 000001 */ + 0x04, /* 000001 */ + + /* 114 0x72 'r' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x58, /* 010110 */ + 0x64, /* 011001 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x00, /* 000000 */ + + /* 115 0x73 's' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x3C, /* 001111 */ + 0x40, /* 010000 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x78, /* 011110 */ + 0x00, /* 000000 */ + + /* 116 0x74 't' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x0C, /* 000011 */ + 0x00, /* 000000 */ + + /* 117 0x75 'u' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 118 0x76 'v' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x28, /* 001010 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 119 0x77 'w' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + + /* 120 0x78 'x' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x28, /* 001010 */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 121 0x79 'y' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x04, /* 000001 */ + 0x38, /* 001110 */ + + /* 122 0x7A 'z' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 123 0x7B '{' */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x00, /* 000000 */ + + /* 124 0x7C '|' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 125 0x7D '}' */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x00, /* 000000 */ + + /* 126 0x7E '~' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x20, /* 001000 */ + 0x54, /* 010101 */ + 0x08, /* 000010 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 127 0x7F 'DEL' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 128 0x80 '\200' */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x40, /* 010000 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + + /* 129 0x81 '\201' */ + 0x00, /* 000000 */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 130 0x82 '\202' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 131 0x83 '\203' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 132 0x84 '\204' */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 133 0x85 '\205' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 134 0x86 '\206' */ + 0x3C, /* 001111 */ + 0x18, /* 000110 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 135 0x87 '\207' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x40, /* 010000 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + + /* 136 0x88 '\210' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 137 0x89 '\211' */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 138 0x8A '\212' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 139 0x8B '\213' */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 140 0x8C '\214' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 141 0x8D '\215' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 142 0x8E '\216' */ + 0x44, /* 010001 */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 143 0x8F '\217' */ + 0x30, /* 001100 */ + 0x48, /* 010010 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 144 0x90 '\220' */ + 0x10, /* 000100 */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x78, /* 011110 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 145 0x91 '\221' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x78, /* 011110 */ + 0x14, /* 000101 */ + 0x7C, /* 011111 */ + 0x50, /* 010100 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 146 0x92 '\222' */ + 0x3C, /* 001111 */ + 0x50, /* 010100 */ + 0x50, /* 010100 */ + 0x78, /* 011110 */ + 0x50, /* 010100 */ + 0x50, /* 010100 */ + 0x5C, /* 010111 */ + 0x00, /* 000000 */ + + /* 147 0x93 '\223' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 148 0x94 '\224' */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 149 0x95 '\225' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 150 0x96 '\226' */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 151 0x97 '\227' */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 152 0x98 '\230' */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x04, /* 000001 */ + 0x38, /* 001110 */ + + /* 153 0x99 '\231' */ + 0x84, /* 100001 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 154 0x9A '\232' */ + 0x88, /* 100010 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 155 0x9B '\233' */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x50, /* 010100 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 156 0x9C '\234' */ + 0x30, /* 001100 */ + 0x48, /* 010010 */ + 0x40, /* 010000 */ + 0x70, /* 011100 */ + 0x40, /* 010000 */ + 0x44, /* 010001 */ + 0x78, /* 011110 */ + 0x00, /* 000000 */ + + /* 157 0x9D '\235' */ + 0x44, /* 010001 */ + 0x28, /* 001010 */ + 0x7C, /* 011111 */ + 0x10, /* 000100 */ + 0x7C, /* 011111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 158 0x9E '\236' */ + 0x70, /* 011100 */ + 0x48, /* 010010 */ + 0x70, /* 011100 */ + 0x48, /* 010010 */ + 0x5C, /* 010111 */ + 0x48, /* 010010 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 159 0x9F '\237' */ + 0x0C, /* 000011 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x60, /* 011000 */ + 0x00, /* 000000 */ + + /* 160 0xA0 '\240' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 161 0xA1 '\241' */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 162 0xA2 '\242' */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 163 0xA3 '\243' */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 164 0xA4 '\244' */ + 0x34, /* 001101 */ + 0x58, /* 010110 */ + 0x00, /* 000000 */ + 0x58, /* 010110 */ + 0x64, /* 011001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 165 0xA5 '\245' */ + 0x58, /* 010110 */ + 0x44, /* 010001 */ + 0x64, /* 011001 */ + 0x54, /* 010101 */ + 0x4C, /* 010011 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 166 0xA6 '\246' */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 167 0xA7 '\247' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 168 0xA8 '\250' */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x40, /* 010000 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 169 0xA9 '\251' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 170 0xAA '\252' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x04, /* 000001 */ + 0x04, /* 000001 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 171 0xAB '\253' */ + 0x20, /* 001000 */ + 0x24, /* 001001 */ + 0x28, /* 001010 */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x44, /* 010001 */ + 0x08, /* 000010 */ + 0x1C, /* 000111 */ + + /* 172 0xAC '\254' */ + 0x20, /* 001000 */ + 0x24, /* 001001 */ + 0x28, /* 001010 */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x58, /* 010110 */ + 0x3C, /* 001111 */ + 0x08, /* 000010 */ + + /* 173 0xAD '\255' */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 174 0xAE '\256' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x24, /* 001001 */ + 0x48, /* 010010 */ + 0x90, /* 100100 */ + 0x48, /* 010010 */ + 0x24, /* 001001 */ + 0x00, /* 000000 */ + + /* 175 0xAF '\257' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x90, /* 100100 */ + 0x48, /* 010010 */ + 0x24, /* 001001 */ + 0x48, /* 010010 */ + 0x90, /* 100100 */ + 0x00, /* 000000 */ + + /* 176 0xB0 '\260' */ + 0x10, /* 000100 */ + 0x44, /* 010001 */ + 0x10, /* 000100 */ + 0x44, /* 010001 */ + 0x10, /* 000100 */ + 0x44, /* 010001 */ + 0x10, /* 000100 */ + 0x44, /* 010001 */ + + /* 177 0xB1 '\261' */ + 0xA8, /* 101010 */ + 0x54, /* 010101 */ + 0xA8, /* 101010 */ + 0x54, /* 010101 */ + 0xA8, /* 101010 */ + 0x54, /* 010101 */ + 0xA8, /* 101010 */ + 0x54, /* 010101 */ + + /* 178 0xB2 '\262' */ + 0xDC, /* 110111 */ + 0x74, /* 011101 */ + 0xDC, /* 110111 */ + 0x74, /* 011101 */ + 0xDC, /* 110111 */ + 0x74, /* 011101 */ + 0xDC, /* 110111 */ + 0x74, /* 011101 */ + + /* 179 0xB3 '\263' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 180 0xB4 '\264' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xF0, /* 111100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 181 0xB5 '\265' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xF0, /* 111100 */ + 0x10, /* 000100 */ + 0xF0, /* 111100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 182 0xB6 '\266' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xE8, /* 111010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 183 0xB7 '\267' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xF8, /* 111110 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 184 0xB8 '\270' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xF0, /* 111100 */ + 0x10, /* 000100 */ + 0xF0, /* 111100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 185 0xB9 '\271' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xE8, /* 111010 */ + 0x08, /* 000010 */ + 0xE8, /* 111010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 186 0xBA '\272' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 187 0xBB '\273' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xF8, /* 111110 */ + 0x08, /* 000010 */ + 0xE8, /* 111010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 188 0xBC '\274' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xE8, /* 111010 */ + 0x08, /* 000010 */ + 0xF8, /* 111110 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 189 0xBD '\275' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xF8, /* 111110 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 190 0xBE '\276' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xF0, /* 111100 */ + 0x10, /* 000100 */ + 0xF0, /* 111100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 191 0xBF '\277' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xF0, /* 111100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 192 0xC0 '\300' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x1C, /* 000111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 193 0xC1 '\301' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 194 0xC2 '\302' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 195 0xC3 '\303' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x1C, /* 000111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 196 0xC4 '\304' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 197 0xC5 '\305' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xFC, /* 111111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 198 0xC6 '\306' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x1C, /* 000111 */ + 0x10, /* 000100 */ + 0x1C, /* 000111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 199 0xC7 '\307' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x2C, /* 001011 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 200 0xC8 '\310' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x2C, /* 001011 */ + 0x20, /* 001000 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 201 0xC9 '\311' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x3C, /* 001111 */ + 0x20, /* 001000 */ + 0x2C, /* 001011 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 202 0xCA '\312' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xEC, /* 111011 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 203 0xCB '\313' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0xEC, /* 111011 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 204 0xCC '\314' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x2C, /* 001011 */ + 0x20, /* 001000 */ + 0x2C, /* 001011 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 205 0xCD '\315' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 206 0xCE '\316' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xEC, /* 111011 */ + 0x00, /* 000000 */ + 0xEC, /* 111011 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 207 0xCF '\317' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 208 0xD0 '\320' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 209 0xD1 '\321' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 210 0xD2 '\322' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 211 0xD3 '\323' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 212 0xD4 '\324' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x1C, /* 000111 */ + 0x10, /* 000100 */ + 0x1C, /* 000111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 213 0xD5 '\325' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x1C, /* 000111 */ + 0x10, /* 000100 */ + 0x1C, /* 000111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 214 0xD6 '\326' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x3C, /* 001111 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 215 0xD7 '\327' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xFC, /* 111111 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 216 0xD8 '\330' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xFC, /* 111111 */ + 0x10, /* 000100 */ + 0xFC, /* 111111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 217 0xD9 '\331' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xF0, /* 111100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 218 0xDA '\332' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x1C, /* 000111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 219 0xDB '\333' */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + + /* 220 0xDC '\334' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + + /* 221 0xDD '\335' */ + 0xE0, /* 111000 */ + 0xE0, /* 111000 */ + 0xE0, /* 111000 */ + 0xE0, /* 111000 */ + 0xE0, /* 111000 */ + 0xE0, /* 111000 */ + 0xE0, /* 111000 */ + 0xE0, /* 111000 */ + + /* 222 0xDE '\336' */ + 0x1C, /* 000111 */ + 0x1C, /* 000111 */ + 0x1C, /* 000111 */ + 0x1C, /* 000111 */ + 0x1C, /* 000111 */ + 0x1C, /* 000111 */ + 0x1C, /* 000111 */ + 0x1C, /* 000111 */ + + /* 223 0xDF '\337' */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 224 0xE0 '\340' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x34, /* 001101 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 225 0xE1 '\341' */ + 0x24, /* 001001 */ + 0x44, /* 010001 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x58, /* 010110 */ + 0x40, /* 010000 */ + + /* 226 0xE2 '\342' */ + 0x7C, /* 011111 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x00, /* 000000 */ + + /* 227 0xE3 '\343' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + + /* 228 0xE4 '\344' */ + 0x7C, /* 011111 */ + 0x24, /* 001001 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x24, /* 001001 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 229 0xE5 '\345' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x3C, /* 001111 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + + /* 230 0xE6 '\346' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x74, /* 011101 */ + 0x40, /* 010000 */ + + /* 231 0xE7 '\347' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x0C, /* 000011 */ + 0x00, /* 000000 */ + + /* 232 0xE8 '\350' */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 233 0xE9 '\351' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 234 0xEA '\352' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x28, /* 001010 */ + 0x6C, /* 011011 */ + 0x00, /* 000000 */ + + /* 235 0xEB '\353' */ + 0x18, /* 000110 */ + 0x20, /* 001000 */ + 0x18, /* 000110 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + + /* 236 0xEC '\354' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 237 0xED '\355' */ + 0x00, /* 000000 */ + 0x04, /* 000001 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x40, /* 010000 */ + 0x00, /* 000000 */ + + /* 238 0xEE '\356' */ + 0x3C, /* 001111 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x38, /* 001110 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 239 0xEF '\357' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 240 0xF0 '\360' */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 241 0xF1 '\361' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x7C, /* 011111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 242 0xF2 '\362' */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 243 0xF3 '\363' */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 244 0xF4 '\364' */ + 0x0C, /* 000011 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 245 0xF5 '\365' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x60, /* 011000 */ + + /* 246 0xF6 '\366' */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 247 0xF7 '\367' */ + 0x00, /* 000000 */ + 0x20, /* 001000 */ + 0x54, /* 010101 */ + 0x08, /* 000010 */ + 0x20, /* 001000 */ + 0x54, /* 010101 */ + 0x08, /* 000010 */ + 0x00, /* 000000 */ + + /* 248 0xF8 '\370' */ + 0x30, /* 001100 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 249 0xF9 '\371' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 250 0xFA '\372' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 251 0xFB '\373' */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x50, /* 010100 */ + 0x50, /* 010100 */ + 0x20, /* 001000 */ + 0x20, /* 001000 */ + 0x00, /* 000000 */ + + /* 252 0xFC '\374' */ + 0x60, /* 011000 */ + 0x50, /* 010100 */ + 0x50, /* 010100 */ + 0x50, /* 010100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 253 0xFD '\375' */ + 0x60, /* 011000 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x70, /* 011100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 254 0xFE '\376' */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 255 0xFF '\377' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ +}; + +#endif /* _VIDEO_FONT_6X8_ */ + -- cgit v1.3.1 From 5ab1600213608129ea63fc3046f46349515821d6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 19 May 2026 10:20:56 -0600 Subject: bloblist: Rework bloblist_init and bloblist_maybe_init With bloblist, we need to both see if one already exists as well as create one if it does not. However, the current implementation leads to odd cases where we attempt to create a bloblist before this is possible and have things be overly complicated when we are given one to work with. This reworks things to instead have a bloblist_exists function, which as the name implies checks for an existing bloblist. This is used in the case of booting, to see if we have one and in turn if we have a device tree there as well as in the bloblist_init function to see if we need to do anything. In practical details, we move the logic from bloblist_init that was checking for a bloblist to the new bloblist_exists function and then can clarify the logic as it is much easier to state when we know we do not have one rather than all the ways we might have one. Then we have the locations that set gd->bloblist now also set the GD_FLG_BLOBLIST_READY flag. Reviewed-by: Raymond Mao Tested-by: Alexander Stein Signed-off-by: Tom Rini --- common/bloblist.c | 144 +++++++++++++++++++++++++++-------------------------- common/board_f.c | 4 +- include/bloblist.h | 32 ++++++------ lib/fdtdec.c | 15 ++---- 4 files changed, 96 insertions(+), 99 deletions(-) (limited to 'include') diff --git a/common/bloblist.c b/common/bloblist.c index 09afdd1f96b..51ae9cc50a5 100644 --- a/common/bloblist.c +++ b/common/bloblist.c @@ -448,6 +448,7 @@ int bloblist_new(ulong addr, uint size, uint flags, uint align_log2) hdr->align_log2 = align_log2 ? align_log2 : BLOBLIST_BLOB_ALIGN_LOG2; hdr->chksum = 0; gd->bloblist = hdr; + gd->flags |= GD_FLG_BLOBLIST_READY; return 0; } @@ -475,6 +476,7 @@ int bloblist_check(ulong addr, uint size) return log_msg_ret("Bad checksum", -EIO); } gd->bloblist = hdr; + gd->flags |= GD_FLG_BLOBLIST_READY; return 0; } @@ -576,90 +578,88 @@ int __weak xferlist_from_boot_arg(ulong __always_unused *addr) return -ENOENT; } -int bloblist_init(void) +bool bloblist_exists(void) { - bool fixed = IS_ENABLED(CONFIG_BLOBLIST_FIXED); - int ret = 0; - ulong addr = 0, size; + int ret; + ulong addr = 0; /* Check if a valid transfer list passed in */ - if (!xferlist_from_boot_arg(&addr)) { - size = bloblist_get_total_size(); - } else { - /* - * If U-Boot is not in the first phase, an existing bloblist must - * be at a fixed address. - */ - bool from_addr = fixed && !xpl_is_first_phase(); - - /* - * If Firmware Handoff is mandatory but no transfer list is - * observed, report it as an error. - */ - if (IS_ENABLED(CONFIG_BLOBLIST_PASSAGE_MANDATORY)) - return -ENOENT; - - ret = -ENOENT; - - if (xpl_prev_phase() == PHASE_TPL && - !IS_ENABLED(CONFIG_TPL_BLOBLIST)) - from_addr = false; - if (fixed) - addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED, - CONFIG_BLOBLIST_ADDR); - size = CONFIG_BLOBLIST_SIZE; - - if (from_addr) - ret = bloblist_check(addr, size); + if (!xferlist_from_boot_arg(&addr)) + goto found; - if (ret) - log_debug("Bloblist at %lx not found (err=%d)\n", - addr, ret); - else - /* Get the real size */ - size = gd->bloblist->total_size; - } + /* + * If Firmware Handoff is mandatory but no transfer list is + * observed, report it as an error. + */ + if (IS_ENABLED(CONFIG_BLOBLIST_PASSAGE_MANDATORY)) + return false; - if (ret) { - /* - * If we don't have a bloblist from a fixed address, or the one - * in the fixed address is not valid. we must allocate the - * memory for it now. - */ - if (CONFIG_IS_ENABLED(BLOBLIST_ALLOC)) { - void *ptr = memalign(BLOBLIST_ALIGN, size); - - if (!ptr) - return log_msg_ret("alloc", -ENOMEM); - addr = map_to_sysmem(ptr); - } else if (!fixed) { - return log_msg_ret("BLOBLIST_FIXED is not enabled", - ret); - } - log_debug("Creating new bloblist size %lx at %lx\n", size, - addr); - ret = bloblist_new(addr, size, 0, 0); - } else { - log_debug("Found existing bloblist size %lx at %lx\n", size, - addr); - } + /* + * We have checked for a valid transfer list being passed. At this + * point, if we do not have a fixed address for the bloblist, we cannot + * be provided with one. + */ + if (xpl_is_first_phase() || !IS_ENABLED(CONFIG_BLOBLIST_FIXED)) + return false; - if (ret) - return log_msg_ret("ini", ret); - gd->flags |= GD_FLG_BLOBLIST_READY; + /* + * Check for a valid list as the configured address. + */ + addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED, + CONFIG_BLOBLIST_ADDR); + ret = bloblist_check(addr, CONFIG_BLOBLIST_SIZE); + if (!ret) + goto found; + + log_debug("Bloblist at %lx not found (err=%d)\n", addr, ret); + return false; +found: #ifdef DEBUG bloblist_show_stats(); bloblist_show_list(); #endif - - return 0; + return true; } -int bloblist_maybe_init(void) +int bloblist_init(void) { - if (CONFIG_IS_ENABLED(BLOBLIST) && !(gd->flags & GD_FLG_BLOBLIST_READY)) - return bloblist_init(); + int ret; + ulong addr = 0, size = CONFIG_BLOBLIST_SIZE; + + if (gd->flags & GD_FLG_BLOBLIST_READY) { + log_debug("Found existing bloblist size %x at %p\n", + gd->bloblist->total_size, gd->bloblist); + return 0; + } + + /* + * If Firmware Handoff is mandatory but no transfer list has been + * observed by fdtdec_setup, report it as an error. + */ + if (IS_ENABLED(CONFIG_BLOBLIST_PASSAGE_MANDATORY)) + return -ENOENT; + + /* + * If we don't have an existing bloblist, we either need + * to allocate one now, or initialize the fixed address + * space as a bloblist. + */ + if (CONFIG_IS_ENABLED(BLOBLIST_ALLOC)) { + void *ptr = memalign(BLOBLIST_ALIGN, size); + + if (!ptr) + return log_msg_ret("alloc", -ENOMEM); + addr = map_to_sysmem(ptr); + } else + addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED, + CONFIG_BLOBLIST_ADDR); + + log_debug("Creating new bloblist size %lx at %lx\n", size, + addr); + ret = bloblist_new(addr, size, 0, 0); + if (ret) + return log_msg_ret("ini", ret); return 0; } @@ -687,7 +687,9 @@ int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig, ulong xlist) return ret; if (rfdt != (ulong)bloblist_find(BLOBLISTT_CONTROL_FDT, 0)) { - gd->bloblist = NULL; /* Reset the gd bloblist pointer */ + /* Remove this bloblist from gd */ + gd->bloblist = NULL; + gd->flags &= ~GD_FLG_BLOBLIST_READY; return -EIO; } diff --git a/common/board_f.c b/common/board_f.c index ce87c619e68..c39e3b940d3 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -894,7 +894,9 @@ static void initcall_run_f(void) INITCALL(log_init); INITCALL(initf_bootstage); /* uses its own timer, so does not need DM */ INITCALL(event_init); - INITCALL(bloblist_maybe_init); +#if CONFIG_IS_ENABLED(BLOBLIST) + INITCALL(bloblist_init); +#endif INITCALL(setup_spl_handoff); #if CONFIG_IS_ENABLED(CONSOLE_RECORD_INIT_F) INITCALL(console_record_init); diff --git a/include/bloblist.h b/include/bloblist.h index e67b2a76358..4c578772965 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -488,10 +488,24 @@ const char *bloblist_tag_name(enum bloblist_tag_t tag); */ int bloblist_reloc(void *to, uint to_size); +/** + * bloblist_exists() - Check for the prior existence of a bloblist + * + * This will check for a transfer list having been passed via standard + * convention. If CONFIG_BLOBLIST_PASSAGE_MANDATORY is selected and one is not + * found, we return false. + * + * If CONFIG_BLOBLIST_FIXED is selected, it uses CONFIG_BLOBLIST_ADDR and + * CONFIG_BLOBLIST_SIZE to check for a bloblist. + * + * Return: true if found, false if not + */ +bool bloblist_exists(void); + /** * bloblist_init() - Init the bloblist system with a single bloblist * - * This locates and sets up the blocklist for use. + * This creates a bloblist for use, if not already found. * * If CONFIG_BLOBLIST_FIXED is selected, it uses CONFIG_BLOBLIST_ADDR and * CONFIG_BLOBLIST_SIZE to set up a bloblist for use by U-Boot. @@ -508,22 +522,6 @@ int bloblist_reloc(void *to, uint to_size); */ int bloblist_init(void); -#if CONFIG_IS_ENABLED(BLOBLIST) -/** - * bloblist_maybe_init() - Init the bloblist system if not already done - * - * Calls bloblist_init() if the GD_FLG_BLOBLIST_READY flag is not set - * - * Return: 0 if OK, -ve on error - */ -int bloblist_maybe_init(void); -#else -static inline int bloblist_maybe_init(void) -{ - return 0; -} -#endif /* BLOBLIST */ - /** * bloblist_check_reg_conv() - Check whether the bloblist is compliant to * the register conventions according to the diff --git a/lib/fdtdec.c b/lib/fdtdec.c index c67b6e8c133..d0a84b5034b 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1822,17 +1822,12 @@ int fdtdec_setup(void) int ret = -ENOENT; /* - * If allowing a bloblist, check that first. There was discussion about - * adding an OF_BLOBLIST Kconfig, but this was rejected. - * - * The necessary test is whether the previous phase passed a bloblist, - * not whether this phase creates one. + * If allowing a bloblist, check that first. The necessary test is + * whether the previous phase passed a bloblist, not whether this phase + * creates one. */ - if (CONFIG_IS_ENABLED(BLOBLIST) && - (xpl_prev_phase() != PHASE_TPL || - IS_ENABLED(CONFIG_TPL_BLOBLIST))) { - ret = bloblist_maybe_init(); - if (!ret) { + if (CONFIG_IS_ENABLED(BLOBLIST) && (xpl_phase() > PHASE_TPL)) { + if (bloblist_exists()) { gd->fdt_blob = bloblist_find(BLOBLISTT_CONTROL_FDT, 0); if (gd->fdt_blob) { gd->fdt_src = FDTSRC_BLOBLIST; -- cgit v1.3.1 From 987b5eabc35f3924fd10c66bb1be64a60c6feb23 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 7 May 2026 12:37:10 +0200 Subject: net: tsec: make tsec_private a private structure Move the definition of tsec_private within the only file that makes use of it. This adds the benefit of include/tsec.h not referencing PKTBUFSRX (which is set to CONFIG_SYS_RX_ETH_BUFFER, which we're trying to move to be under CONFIG_NET dependency) anymore. Considering drivers/net/tsec.c is only built if CONFIG_NET=y, this is fine. Reviewed-by: Simon Glass Signed-off-by: Quentin Schulz --- drivers/net/tsec.c | 17 +++++++++++++++++ include/tsec.h | 17 ----------------- 2 files changed, 17 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index bd4ebdd745a..d03368b9408 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -37,6 +37,23 @@ ) #endif /* CFG_TSEC_TBICR_SETTINGS */ +struct tsec_private { + struct txbd8 __iomem txbd[TX_BUF_CNT]; + struct rxbd8 __iomem rxbd[PKTBUFSRX]; + struct tsec __iomem *regs; + struct tsec_mii_mng __iomem *phyregs_sgmii; + struct phy_device *phydev; + phy_interface_t interface; + struct mii_dev *bus; + uint phyaddr; + uint tbiaddr; + char mii_devname[16]; + u32 flags; + uint rx_idx; /* index of the current RX buffer */ + uint tx_idx; /* index of the current TX buffer */ + struct udevice *dev; +}; + /* Configure the TBI for SGMII operation */ static void tsec_configure_serdes(struct tsec_private *priv) { diff --git a/include/tsec.h b/include/tsec.h index 153337837a9..f5ced38f3fc 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -350,23 +350,6 @@ struct tsec_data { u32 mdio_regs_off; }; -struct tsec_private { - struct txbd8 __iomem txbd[TX_BUF_CNT]; - struct rxbd8 __iomem rxbd[PKTBUFSRX]; - struct tsec __iomem *regs; - struct tsec_mii_mng __iomem *phyregs_sgmii; - struct phy_device *phydev; - phy_interface_t interface; - struct mii_dev *bus; - uint phyaddr; - uint tbiaddr; - char mii_devname[16]; - u32 flags; - uint rx_idx; /* index of the current RX buffer */ - uint tx_idx; /* index of the current TX buffer */ - struct udevice *dev; -}; - struct tsec_info_struct { struct tsec __iomem *regs; struct tsec_mii_mng __iomem *miiregs_sgmii; -- cgit v1.3.1 From 77cc22b8095cee92e5bd63b57b13fa7cf8ac8190 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 7 May 2026 12:37:11 +0200 Subject: net: guard SYS_RX_ETH_BUFFER with NET SYS_RX_ETH_BUFFER represents the number of Ethernet receive packet buffers. It therefore doesn't make sense it's reachable if NET isn't enabled. Direct users of SYS_RX_ETH_BUFFER are: - drivers/net/rtl8169.c, only compiled if CONFIG_RTL8169=y, depends on CONFIG_NETDEVICES=y, depends on CONFIG_NET=y, - drivers/net/fsl_enetc.h, via ENETC_BD_CNT, included in drivers/net/{fsl_enetc.c,fsl_enetc_mdio.c,mscc_eswitch/felix_switch.c} First two only compiled if CONFIG_FSL_ENETC=y, latter with CONFIG_MSCC_FELIX_SWITCH=y. Both symbols depends on CONFIG_NETDEVICES=y, depends on CONFIG_NET=y. - include/net-common.h via PKTBUFSRX, Indirect users via PKTBUFSRX: - arch/sandbox/include/asm/eth.h - according to ./tools/qconfig.py -l -f CONFIG_SANDBOX CONFIG_NO_NET, all sandbox defconfigs have network enabled so ignore this for now, - drivers/dma/ti/k3-udma.c - sets UDMA_RX_DESC_NUM to that if defined, else 4. PKTBUFSRX is CONFIG_SYS_RX_ETH_BUFFER which defaults to 4. According to ./tools/qconfig.py -l -f CONFIG_TI_K3_NAVSS_UDMA '~CONFIG_SYS_RX_ETH_BUFFER=4' no defconfig enabling this DMA driver sets CONFIG_SYS_RX_ETH_BUFFER to anything but the default of 4, so regardless of NET being built UDMA_RX_DESC_NUM will always be 4 with current defconfigs. - drivers/net/{airoha_eth.c,bcm6348-eth.c,bcm6368-eth.c,cortina_ni.c, dc2114x.c,eepro100.c,essedma.c,ethoc.c,ftgmac100.c,ftmac100.c, hifemac.c,mcffec.c,mpc8xx_fec.c,pic32_eth.c,sandbox.c,sni_ave.c, sni_netsec.c,ti/am65-cpsw-nuss.c,ti/cpsw.c,ti/icssg_prueth.c, tsec.c} all depends on CONFIG_NETDEVICES=y, depends on CONFIG_NET=y, - net/lwip/net-lwip.c, only compiled if CONFIG_NET_LWIP=y, depends on CONFIG_NET=y, - net/{net.c,tcp.c}, only compiled if CONFIG_NET_LEGACY=y, depends on CONFIG_NET=y, - net/net-common.c, only compiled if CONFIG_NET=y, - test/cmd/wget.c, only compiled if CONFIG_NET_LEGACY=y, depends on CONFIG_NET=y, - test/image/spl_load_net.c, only compiled if CONFIG_SPL_UT_LOAD_NET=y, depends on CONFIG_SPL_ETH=y, depends on CONFIG_SPL_NET=y, depends on CONFIG_NET_LEGACY=y, depends on CONFIG_NET=y, Indirect users via net_rx_packets[PKTBUFSRX]. This array is only externally defined in net/net-common.c which is only compiled if CONFIG_NET=y. Users of net_rx_packets are: - drivers/net/{airoha_eth.c,bcm6348-eth.c,bcm6368-eth.c,cortina_ni.c, dc2114x.c,dm9000x.c,essedma.c,ethoc.c,fsl_enetc.c,ftgmac100.c, ftmac100.c,hifemac.c,ks8851_mll.c,macb.c,mcffec.c,mpc8xx_fec.c, mscc_eswitch/jr2_switch.c,mscc_eswitch/luton_switch.c, mscc_eswitch/ocelot_switch.c,mscc_eswitch/serval_switch.c, mscc_eswitch/servalt_switch.c,pic32_eth.c,sandbox-raw.c, sandbox.c,smc911x.c,sni_ave.c,sni_netsec.c,ti/am65-cpsw-nuss.c, ti/cpsw.c,ti/icssg_prueth.c,tsec.c,xilinx_axi_mrmac.c} all depends on CONFIG_NETDEVICES=y, depends on CONFIG_NET=y, - drivers/usb/gadget/ether.c only built if CONFIG_$(PHASE_)USB_ETHER=y, depends on CONFIG_NET=y/CONFIG_SPL_NET=y, - net/lwip/net-lwip.c only compiled if CONFIG_NET_LWIP=y, depends on CONFIG_NET=y, - net/net.c, only compiled if CONFIG_NET_LEGACY=y, depends on CONFIG_NET=y, - net/net-common.c, only compiled if CONFIG_NET=y, Reviewed-by: Simon Glass Signed-off-by: Quentin Schulz --- include/net-common.h | 4 ++++ net/Kconfig | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/net-common.h b/include/net-common.h index 69b6316c1ec..0c260873c2c 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -20,7 +20,9 @@ * alignment in memory. * */ +#if CONFIG_IS_ENABLED(NET) #define PKTBUFSRX CONFIG_SYS_RX_ETH_BUFFER +#endif #define PKTALIGN ARCH_DMA_MINALIGN /* IPv4 addresses are always 32 bits in size */ @@ -132,7 +134,9 @@ static inline void net_set_state(enum net_loop_state state) } extern int net_restart_wrap; /* Tried all network devices */ +#if CONFIG_IS_ENABLED(NET) extern uchar *net_rx_packets[PKTBUFSRX]; /* Receive packets */ +#endif extern const u8 net_bcast_ethaddr[ARP_HLEN]; /* Ethernet broadcast address */ extern struct in_addr net_ip; /* Our IP addr (0 = unknown) */ /* Indicates whether the pxe path prefix / config file was specified in dhcp option */ diff --git a/net/Kconfig b/net/Kconfig index e712a0dd2ac..171a88f8ed2 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -279,8 +279,6 @@ config TFTP_BLOCKSIZE almost-MTU block sizes. You can also activate CONFIG_IP_DEFRAG to set a larger block. -endif # if NET - config SYS_RX_ETH_BUFFER int "Number of receive packet buffers" default 4 @@ -289,3 +287,5 @@ config SYS_RX_ETH_BUFFER controllers it is recommended to set this value to 8 or even higher, since all buffers can be full shortly after enabling the interface on high Ethernet traffic. + +endif # if NET -- cgit v1.3.1 From 77c79a2c60fddb0a394289d436e21148371260b4 Mon Sep 17 00:00:00 2001 From: Caleb Ethridge Date: Thu, 21 May 2026 09:53:13 -0400 Subject: mach-sc5xx: Remove update commands from default environment Remove the update_spi family of commands from the U-Boot environment. These commands are not standard in U-Boot, and boot media programming has moved to Linux, so the commands can be safely removed. Additionally, this commit removes the adi_stage2_offset, adi_rfs_offset, imagefile, jffs2file, and init_ethernet variables that were consumed by the update commands as they are no longer needed. CONFIG_SC5XX_UBOOT_OFFSET and CONFIG_SC5XX_ROOTFS_OFFSET are also removed. Signed-off-by: Caleb Ethridge --- board/adi/sc573-ezkit/sc573-ezkit.env | 3 -- board/adi/sc584-ezkit/sc584-ezkit.env | 3 -- board/adi/sc589-ezkit/sc589-ezkit.env | 3 -- board/adi/sc589-mini/sc589-mini.env | 3 -- board/adi/sc594-som-ezkit/sc594-som-ezkit.env | 3 -- board/adi/sc594-som-ezlite/sc594-som-ezlite.env | 3 -- board/adi/sc598-som-ezkit/sc598-som-ezkit.env | 3 -- board/adi/sc598-som-ezlite/sc598-som-ezlite.env | 3 -- configs/sc573-ezkit_defconfig | 2 - configs/sc584-ezkit_defconfig | 2 - configs/sc589-ezkit_defconfig | 2 - configs/sc589-mini_defconfig | 2 - include/env/adi/adi_boot.env | 54 ------------------------- 13 files changed, 86 deletions(-) (limited to 'include') diff --git a/board/adi/sc573-ezkit/sc573-ezkit.env b/board/adi/sc573-ezkit/sc573-ezkit.env index 8b03a3d5da9..83cbe808efa 100644 --- a/board/adi/sc573-ezkit/sc573-ezkit.env +++ b/board/adi/sc573-ezkit/sc573-ezkit.env @@ -3,10 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc573-ezkit.jffs2 loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS diff --git a/board/adi/sc584-ezkit/sc584-ezkit.env b/board/adi/sc584-ezkit/sc584-ezkit.env index 8a6f7edd5e8..2640d97bab2 100644 --- a/board/adi/sc584-ezkit/sc584-ezkit.env +++ b/board/adi/sc584-ezkit/sc584-ezkit.env @@ -3,10 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc584-ezkit.jffs2 loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS diff --git a/board/adi/sc589-ezkit/sc589-ezkit.env b/board/adi/sc589-ezkit/sc589-ezkit.env index b8206e85179..a098f0b9c2c 100644 --- a/board/adi/sc589-ezkit/sc589-ezkit.env +++ b/board/adi/sc589-ezkit/sc589-ezkit.env @@ -3,10 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc589-ezkit.jffs2 loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS diff --git a/board/adi/sc589-mini/sc589-mini.env b/board/adi/sc589-mini/sc589-mini.env index f7628b0b335..bed2ddc944d 100644 --- a/board/adi/sc589-mini/sc589-mini.env +++ b/board/adi/sc589-mini/sc589-mini.env @@ -3,10 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc589-mini.jffs2 loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS diff --git a/board/adi/sc594-som-ezkit/sc594-som-ezkit.env b/board/adi/sc594-som-ezkit/sc594-som-ezkit.env index 069edc717da..f629f7f2cff 100644 --- a/board/adi/sc594-som-ezkit/sc594-som-ezkit.env +++ b/board/adi/sc594-som-ezkit/sc594-som-ezkit.env @@ -3,10 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc594-som-ezkit.jffs2 loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS diff --git a/board/adi/sc594-som-ezlite/sc594-som-ezlite.env b/board/adi/sc594-som-ezlite/sc594-som-ezlite.env index e5382b67c81..f629f7f2cff 100644 --- a/board/adi/sc594-som-ezlite/sc594-som-ezlite.env +++ b/board/adi/sc594-som-ezlite/sc594-som-ezlite.env @@ -3,10 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc594-som-ezlite.jffs2 loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS diff --git a/board/adi/sc598-som-ezkit/sc598-som-ezkit.env b/board/adi/sc598-som-ezkit/sc598-som-ezkit.env index 2cb475e1001..f629f7f2cff 100644 --- a/board/adi/sc598-som-ezkit/sc598-som-ezkit.env +++ b/board/adi/sc598-som-ezkit/sc598-som-ezkit.env @@ -3,10 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc598-som-ezkit.jffs2 loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS diff --git a/board/adi/sc598-som-ezlite/sc598-som-ezlite.env b/board/adi/sc598-som-ezlite/sc598-som-ezlite.env index 1d9ea6d188b..7b13d6fc32b 100644 --- a/board/adi/sc598-som-ezlite/sc598-som-ezlite.env +++ b/board/adi/sc598-som-ezlite/sc598-som-ezlite.env @@ -3,10 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET loadaddr=CONFIG_SC5XX_LOADADDR -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc598-som-ezlite.jffs2 #include diff --git a/configs/sc573-ezkit_defconfig b/configs/sc573-ezkit_defconfig index 976d8e0306a..7a0c7d04e84 100644 --- a/configs/sc573-ezkit_defconfig +++ b/configs/sc573-ezkit_defconfig @@ -6,9 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_DM_GPIO=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_SERIAL=y -CONFIG_SC5XX_UBOOT_OFFSET=0x20000 CONFIG_SC5XX_FITIMAGE_OFFSET=0xE0000 -CONFIG_SC5XX_ROOTFS_OFFSET=0x6E0000 CONFIG_SC5XX_LOADADDR=0x83000000 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_CGU0_CLKOUTSEL=7 diff --git a/configs/sc584-ezkit_defconfig b/configs/sc584-ezkit_defconfig index 27f55804199..7975a610ca3 100644 --- a/configs/sc584-ezkit_defconfig +++ b/configs/sc584-ezkit_defconfig @@ -10,9 +10,7 @@ CONFIG_SPL_STACK=0x200C0000 CONFIG_SPL_BSS_START_ADDR=0x200A0000 CONFIG_SPL_BSS_MAX_SIZE=0x8000 CONFIG_SC58X=y -CONFIG_SC5XX_UBOOT_OFFSET=0x20000 CONFIG_SC5XX_FITIMAGE_OFFSET=0xE0000 -CONFIG_SC5XX_ROOTFS_OFFSET=0x6E0000 CONFIG_SC5XX_LOADADDR=0x89300000 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_ADI_BUG_EZKHW21=y diff --git a/configs/sc589-ezkit_defconfig b/configs/sc589-ezkit_defconfig index 180b6904d95..0ceb57f1f42 100644 --- a/configs/sc589-ezkit_defconfig +++ b/configs/sc589-ezkit_defconfig @@ -13,9 +13,7 @@ CONFIG_SPL_BSS_START_ADDR=0x200A0000 CONFIG_SPL_BSS_MAX_SIZE=0x8000 CONFIG_SC58X=y CONFIG_TARGET_SC589_EZKIT=y -CONFIG_SC5XX_UBOOT_OFFSET=0x20000 CONFIG_SC5XX_FITIMAGE_OFFSET=0xE0000 -CONFIG_SC5XX_ROOTFS_OFFSET=0x6E0000 CONFIG_SC5XX_LOADADDR=0xC3000000 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_ADI_USE_DMC1=y diff --git a/configs/sc589-mini_defconfig b/configs/sc589-mini_defconfig index 92c2741f701..32678b63a9f 100644 --- a/configs/sc589-mini_defconfig +++ b/configs/sc589-mini_defconfig @@ -12,9 +12,7 @@ CONFIG_SPL_BSS_START_ADDR=0x200A0000 CONFIG_SPL_BSS_MAX_SIZE=0x8000 CONFIG_SC58X=y CONFIG_TARGET_SC589_MINI=y -CONFIG_SC5XX_UBOOT_OFFSET=0x20000 CONFIG_SC5XX_FITIMAGE_OFFSET=0xE0000 -CONFIG_SC5XX_ROOTFS_OFFSET=0x8E0000 CONFIG_SC5XX_LOADADDR=0xC3000000 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_ADI_USE_DMC1=y diff --git a/include/env/adi/adi_boot.env b/include/env/adi/adi_boot.env index db4148b1af9..42f33ed83af 100644 --- a/include/env/adi/adi_boot.env +++ b/include/env/adi/adi_boot.env @@ -1,11 +1,8 @@ /* * A target board needs to set these variables for the commands below to work: * - * - adi_stage2_offset, the location of stage2-boot.ldr on the SPI flash * - adi_image_offset, location of the fitImage on the SPI flash - * - adi_rfs_offset, location of the RFS on the SPI flash * - loadaddr, where you want to load things - * - jffs2file, name of the jffs2 file for update, ex adsp-sc5xx-tiny-adsp-sc573.jffs2 */ #ifdef CONFIG_SC59X_64 @@ -15,7 +12,6 @@ #endif /* Config options */ -imagefile=fitImage ethaddr=02:80:ad:20:31:e8 eth1addr=02:80:ad:20:31:e9 uart_console=CONFIG_UART_CONSOLE @@ -25,11 +21,6 @@ initrd_high=0xffffffffffffffff initrd_high=0xffffffff #endif -/* Helper routines */ -init_ethernet=mii info; - dhcp; - setenv serverip ${tftpserverip} - /* Args for each boot mode */ adi_bootargs=EARLY_PRINTK console=ttySC0,CONFIG_BAUDRATE vmalloc=512M ramargs=setenv bootargs ${adi_bootargs} @@ -73,48 +64,3 @@ ramboot=run init_ethernet; run ramargs; bootm ${loadaddr} #endif - -/* Update commands */ -stage1file=stage1-boot.ldr -stage2file=stage2-boot.ldr - -#if defined(USE_SPI) || defined(USE_OSPI) -update_spi_uboot_stage1=tftp ${loadaddr} ${tftp_dir_prefix}${stage1file}; - sf probe ${sfdev}; - sf update ${loadaddr} 0x0 ${filesize} -update_spi_uboot_stage2=tftp ${loadaddr} ${tftp_dir_prefix}${stage2file}; - sf probe ${sfdev}; - sf update ${loadaddr} ${adi_stage2_offset} ${filesize} -update_spi_uboot=run update_spi_uboot_stage1; - run update_spi_uboot_stage2; -update_spi_fit=tftp ${loadaddr} ${tftp_dir_prefix}${imagefile}; - sf probe ${sfdev}; - sf update ${loadaddr} ${adi_image_offset} ${filesize}; - setenv imagesize ${filesize} -update_spi_rfs=tftp ${loadaddr} ${tftp_dir_prefix}${jffs2file}; - sf probe ${sfdev}; - sf update ${loadaddr} ${adi_rfs_offset} ${filesize} - -start_update_spi=run init_ethernet; - run update_spi_uboot; - run update_spi_fit; - run update_spi_rfs; -start_update_spi_uboot_only=run init_ethernet; - run update_spi_uboot; -#endif - -#if defined(USE_SPI) -update_spi=setenv sfdev CONFIG_SC_BOOT_SPI_BUS:CONFIG_SC_BOOT_SPI_SSEL; - setenv bootcmd run spiboot; - setenv argscmd spiargs; - run start_update_spi; - saveenv -#endif - -#if defined(USE_OSPI) -update_ospi=setenv sfdev CONFIG_SC_BOOT_OSPI_BUS:CONFIG_SC_BOOT_OSPI_SSEL; - setenv bootcmd run ospiboot; - setenv argscmd spiargs; - run start_update_spi; - saveenv -#endif -- cgit v1.3.1 From c1fcf76863700270ce10dceefeb72017e991d627 Mon Sep 17 00:00:00 2001 From: Caleb Ethridge Date: Thu, 21 May 2026 09:53:15 -0400 Subject: mach-sc5xx: Update boot commands Update the default boot commands to match the expected bootargs in Linux and new SPI partitioning scheme. Because the environment is no longer stored in the SPI flash, imagesize has been removed and replaced with a fixed length read to load from the SPI. Additionally the partitions of the mmc have been updated. The first partition holds the fitImage at /fitImage, and the second partition contains the rootfs. With this change, the imagefile environment variable has also been eliminated, the image in the first partition is expected to always be named fitImage. Signed-off-by: Caleb Ethridge --- board/adi/sc573-ezkit/sc573-ezkit.env | 2 +- board/adi/sc584-ezkit/sc584-ezkit.env | 2 +- board/adi/sc589-ezkit/sc589-ezkit.env | 2 +- board/adi/sc589-mini/sc589-mini.env | 2 +- board/adi/sc594-som-ezkit/sc594-som-ezkit.env | 2 +- board/adi/sc594-som-ezlite/sc594-som-ezlite.env | 2 +- board/adi/sc598-som-ezkit/sc598-som-ezkit.env | 2 +- board/adi/sc598-som-ezlite/sc598-som-ezlite.env | 2 +- configs/sc573-ezkit_defconfig | 1 - configs/sc584-ezkit_defconfig | 1 - configs/sc589-ezkit_defconfig | 1 - configs/sc589-mini_defconfig | 1 - include/env/adi/adi_boot.env | 16 ++++++++++------ 13 files changed, 18 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/board/adi/sc573-ezkit/sc573-ezkit.env b/board/adi/sc573-ezkit/sc573-ezkit.env index 83cbe808efa..61381edab26 100644 --- a/board/adi/sc573-ezkit/sc573-ezkit.env +++ b/board/adi/sc573-ezkit/sc573-ezkit.env @@ -3,7 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET +adi_image_offset=0xe0000 loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS diff --git a/board/adi/sc584-ezkit/sc584-ezkit.env b/board/adi/sc584-ezkit/sc584-ezkit.env index 2640d97bab2..f676343a272 100644 --- a/board/adi/sc584-ezkit/sc584-ezkit.env +++ b/board/adi/sc584-ezkit/sc584-ezkit.env @@ -3,7 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET +adi_image_offset=0xe0000 loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS diff --git a/board/adi/sc589-ezkit/sc589-ezkit.env b/board/adi/sc589-ezkit/sc589-ezkit.env index a098f0b9c2c..8a1b9a6e92a 100644 --- a/board/adi/sc589-ezkit/sc589-ezkit.env +++ b/board/adi/sc589-ezkit/sc589-ezkit.env @@ -3,7 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET +adi_image_offset=0xe0000 loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS diff --git a/board/adi/sc589-mini/sc589-mini.env b/board/adi/sc589-mini/sc589-mini.env index bed2ddc944d..39ee0c54da0 100644 --- a/board/adi/sc589-mini/sc589-mini.env +++ b/board/adi/sc589-mini/sc589-mini.env @@ -3,7 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET +adi_image_offset=0xe0000 loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS diff --git a/board/adi/sc594-som-ezkit/sc594-som-ezkit.env b/board/adi/sc594-som-ezkit/sc594-som-ezkit.env index f629f7f2cff..12980f71ba2 100644 --- a/board/adi/sc594-som-ezkit/sc594-som-ezkit.env +++ b/board/adi/sc594-som-ezkit/sc594-som-ezkit.env @@ -3,7 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET +adi_image_offset=0x110000 loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS diff --git a/board/adi/sc594-som-ezlite/sc594-som-ezlite.env b/board/adi/sc594-som-ezlite/sc594-som-ezlite.env index f629f7f2cff..12980f71ba2 100644 --- a/board/adi/sc594-som-ezlite/sc594-som-ezlite.env +++ b/board/adi/sc594-som-ezlite/sc594-som-ezlite.env @@ -3,7 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET +adi_image_offset=0x110000 loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS diff --git a/board/adi/sc598-som-ezkit/sc598-som-ezkit.env b/board/adi/sc598-som-ezkit/sc598-som-ezkit.env index f629f7f2cff..12980f71ba2 100644 --- a/board/adi/sc598-som-ezkit/sc598-som-ezkit.env +++ b/board/adi/sc598-som-ezkit/sc598-som-ezkit.env @@ -3,7 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET +adi_image_offset=0x110000 loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS diff --git a/board/adi/sc598-som-ezlite/sc598-som-ezlite.env b/board/adi/sc598-som-ezlite/sc598-som-ezlite.env index 7b13d6fc32b..d5364df1613 100644 --- a/board/adi/sc598-som-ezlite/sc598-som-ezlite.env +++ b/board/adi/sc598-som-ezlite/sc598-som-ezlite.env @@ -3,7 +3,7 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET +adi_image_offset=0x100000 loadaddr=CONFIG_SC5XX_LOADADDR #include diff --git a/configs/sc573-ezkit_defconfig b/configs/sc573-ezkit_defconfig index 7a0c7d04e84..4320c73fd39 100644 --- a/configs/sc573-ezkit_defconfig +++ b/configs/sc573-ezkit_defconfig @@ -6,7 +6,6 @@ CONFIG_SPL_GPIO=y CONFIG_DM_GPIO=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_SERIAL=y -CONFIG_SC5XX_FITIMAGE_OFFSET=0xE0000 CONFIG_SC5XX_LOADADDR=0x83000000 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_CGU0_CLKOUTSEL=7 diff --git a/configs/sc584-ezkit_defconfig b/configs/sc584-ezkit_defconfig index 7975a610ca3..52ab7c9337b 100644 --- a/configs/sc584-ezkit_defconfig +++ b/configs/sc584-ezkit_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_STACK=0x200C0000 CONFIG_SPL_BSS_START_ADDR=0x200A0000 CONFIG_SPL_BSS_MAX_SIZE=0x8000 CONFIG_SC58X=y -CONFIG_SC5XX_FITIMAGE_OFFSET=0xE0000 CONFIG_SC5XX_LOADADDR=0x89300000 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_ADI_BUG_EZKHW21=y diff --git a/configs/sc589-ezkit_defconfig b/configs/sc589-ezkit_defconfig index 0ceb57f1f42..a249fe8df7b 100644 --- a/configs/sc589-ezkit_defconfig +++ b/configs/sc589-ezkit_defconfig @@ -13,7 +13,6 @@ CONFIG_SPL_BSS_START_ADDR=0x200A0000 CONFIG_SPL_BSS_MAX_SIZE=0x8000 CONFIG_SC58X=y CONFIG_TARGET_SC589_EZKIT=y -CONFIG_SC5XX_FITIMAGE_OFFSET=0xE0000 CONFIG_SC5XX_LOADADDR=0xC3000000 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_ADI_USE_DMC1=y diff --git a/configs/sc589-mini_defconfig b/configs/sc589-mini_defconfig index 32678b63a9f..25285695367 100644 --- a/configs/sc589-mini_defconfig +++ b/configs/sc589-mini_defconfig @@ -12,7 +12,6 @@ CONFIG_SPL_BSS_START_ADDR=0x200A0000 CONFIG_SPL_BSS_MAX_SIZE=0x8000 CONFIG_SC58X=y CONFIG_TARGET_SC589_MINI=y -CONFIG_SC5XX_FITIMAGE_OFFSET=0xE0000 CONFIG_SC5XX_LOADADDR=0xC3000000 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_ADI_USE_DMC1=y diff --git a/include/env/adi/adi_boot.env b/include/env/adi/adi_boot.env index 42f33ed83af..b4b725247f7 100644 --- a/include/env/adi/adi_boot.env +++ b/include/env/adi/adi_boot.env @@ -39,23 +39,27 @@ nfsboot=run init_ethernet; #endif #if defined(USE_MMC) -mmcargs=setenv bootargs root=/dev/mmcblk0p1 rw rootfstype=ext4 rootwait ${adi_bootargs} +mmcargs=setenv bootargs root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait ${adi_bootargs} mmcboot=mmc rescan; - ext4load mmc 0:1 ${loadaddr} /boot/${imagefile}; + ext4load mmc 0:1 ${loadaddr} /fitImage; run mmcargs; bootm ${loadaddr} #endif -#if defined(USE_SPI) || defined(USE_OSPI) -spiargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2 ${adi_bootargs} +#if defined(USE_SPI) +spiargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2 ${adi_bootargs}; setenv sfdev CONFIG_SC_BOOT_SPI_BUS:CONFIG_SC_BOOT_SPI_SSEL spiboot=run spiargs; sf probe ${sfdev}; - sf read ${loadaddr} ${adi_image_offset} ${imagesize}; + sf read ${loadaddr} ${adi_image_offset} 0xf00000; bootm ${loadaddr} #endif #if defined(USE_OSPI) -ospiboot=run spiboot +ospiargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2 ${adi_bootargs}; setenv sfdev CONFIG_SC_BOOT_OSPI_BUS:CONFIG_SC_BOOT_OSPI_SSEL +ospiboot=run ospiargs; + sf probe ${sfdev}; + sf read ${loadaddr} ${adi_image_offset} 0xf00000; + bootm ${loadaddr} #endif #if defined(USE_RAM) -- cgit v1.3.1 From 3b9b94ef68c6f3a1466a49ff4c482060923aea1b Mon Sep 17 00:00:00 2001 From: Caleb Ethridge Date: Thu, 21 May 2026 09:53:16 -0400 Subject: mach-sc5xx: Switch from tftp to wget Switch the nfsboot and other relevant commands to use wget instead of tftp. This also includes the addition of the httpdstp variable for selecting the wget port. There is no longer any automatic DHCP configuration. Before running a command with wget, either 'dhcp' must be run or the 'ipaddr' and 'serverip' variables must be set. Additionally, the nfsboot command looks for the file named 'fitImage' on the server to use to boot. The default port is set to 8000 instead of the usual 80 to allow for use with an unprivileged web server. Signed-off-by: Caleb Ethridge Reviewed-by: Simon Glass --- include/env/adi/adi_boot.env | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/env/adi/adi_boot.env b/include/env/adi/adi_boot.env index b4b725247f7..be4d8521ac9 100644 --- a/include/env/adi/adi_boot.env +++ b/include/env/adi/adi_boot.env @@ -14,6 +14,7 @@ /* Config options */ ethaddr=02:80:ad:20:31:e8 eth1addr=02:80:ad:20:31:e9 +httpdstp=8000 uart_console=CONFIG_UART_CONSOLE #ifdef CONFIG_SC59X_64 initrd_high=0xffffffffffffffff @@ -26,15 +27,14 @@ adi_bootargs=EARLY_PRINTK console=ttySC0,CONFIG_BAUDRATE vmalloc=512M ramargs=setenv bootargs ${adi_bootargs} addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off +rootpath=/romfs /* Boot modes are selectable and should be defined in the board env before including */ #if defined(USE_NFS) -// rootpath is set by CONFIG_ROOTPATH nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath},tcp,nfsvers=3 ${adi_bootargs} -nfsboot=run init_ethernet; - tftp ${loadaddr} ${tftp_dir_prefix}${imagefile}; - run nfsargs; +nfsboot=run nfsargs; run addip; + wget ${loadaddr} ${serverip}:/fitImage; bootm ${loadaddr} #endif @@ -63,8 +63,7 @@ ospiboot=run ospiargs; #endif #if defined(USE_RAM) -ramboot=run init_ethernet; - tftp ${loadaddr} ${tfpt_dir_prefix}${imagefile}; +ramboot=wget ${loadaddr} ${serverip}:/fitImage; run ramargs; bootm ${loadaddr} #endif -- cgit v1.3.1 From a29a895bdce9e64f4e0b68ecad44b48927c5ca86 Mon Sep 17 00:00:00 2001 From: Caleb Ethridge Date: Thu, 21 May 2026 09:53:17 -0400 Subject: mach-sc5xx: Add USB boot command Add the USB boot command to the environments of the boards that support it. Signed-off-by: Caleb Ethridge --- board/adi/sc573-ezkit/sc573-ezkit.env | 1 + board/adi/sc584-ezkit/sc584-ezkit.env | 1 + board/adi/sc589-ezkit/sc589-ezkit.env | 1 + board/adi/sc589-mini/sc589-mini.env | 1 + board/adi/sc594-som-ezkit/sc594-som-ezkit.env | 1 + board/adi/sc594-som-ezlite/sc594-som-ezlite.env | 1 + board/adi/sc598-som-ezkit/sc598-som-ezkit.env | 1 + include/env/adi/adi_boot.env | 8 ++++++++ 8 files changed, 15 insertions(+) (limited to 'include') diff --git a/board/adi/sc573-ezkit/sc573-ezkit.env b/board/adi/sc573-ezkit/sc573-ezkit.env index 61381edab26..e1ad4f3716f 100644 --- a/board/adi/sc573-ezkit/sc573-ezkit.env +++ b/board/adi/sc573-ezkit/sc573-ezkit.env @@ -10,5 +10,6 @@ loadaddr=CONFIG_SC5XX_LOADADDR #define USE_SPI #define USE_RAM #define USE_MMC +#define USE_USB #include diff --git a/board/adi/sc584-ezkit/sc584-ezkit.env b/board/adi/sc584-ezkit/sc584-ezkit.env index f676343a272..7e70f5e200a 100644 --- a/board/adi/sc584-ezkit/sc584-ezkit.env +++ b/board/adi/sc584-ezkit/sc584-ezkit.env @@ -9,5 +9,6 @@ loadaddr=CONFIG_SC5XX_LOADADDR #define USE_NFS #define USE_SPI #define USE_RAM +#define USE_USB #include diff --git a/board/adi/sc589-ezkit/sc589-ezkit.env b/board/adi/sc589-ezkit/sc589-ezkit.env index 8a1b9a6e92a..b8d9b1ef362 100644 --- a/board/adi/sc589-ezkit/sc589-ezkit.env +++ b/board/adi/sc589-ezkit/sc589-ezkit.env @@ -10,5 +10,6 @@ loadaddr=CONFIG_SC5XX_LOADADDR #define USE_RAM #define USE_MMC #define USE_SPI +#define USE_USB #include diff --git a/board/adi/sc589-mini/sc589-mini.env b/board/adi/sc589-mini/sc589-mini.env index 39ee0c54da0..560efeeceeb 100644 --- a/board/adi/sc589-mini/sc589-mini.env +++ b/board/adi/sc589-mini/sc589-mini.env @@ -10,5 +10,6 @@ loadaddr=CONFIG_SC5XX_LOADADDR #define USE_RAM #define USE_SPI #define USE_MMC +#define USE_USB #include diff --git a/board/adi/sc594-som-ezkit/sc594-som-ezkit.env b/board/adi/sc594-som-ezkit/sc594-som-ezkit.env index 12980f71ba2..ef47640320d 100644 --- a/board/adi/sc594-som-ezkit/sc594-som-ezkit.env +++ b/board/adi/sc594-som-ezkit/sc594-som-ezkit.env @@ -11,5 +11,6 @@ loadaddr=CONFIG_SC5XX_LOADADDR #define USE_OSPI #define USE_RAM #define USE_MMC +#define USE_USB #include diff --git a/board/adi/sc594-som-ezlite/sc594-som-ezlite.env b/board/adi/sc594-som-ezlite/sc594-som-ezlite.env index 12980f71ba2..ef47640320d 100644 --- a/board/adi/sc594-som-ezlite/sc594-som-ezlite.env +++ b/board/adi/sc594-som-ezlite/sc594-som-ezlite.env @@ -11,5 +11,6 @@ loadaddr=CONFIG_SC5XX_LOADADDR #define USE_OSPI #define USE_RAM #define USE_MMC +#define USE_USB #include diff --git a/board/adi/sc598-som-ezkit/sc598-som-ezkit.env b/board/adi/sc598-som-ezkit/sc598-som-ezkit.env index 12980f71ba2..ef47640320d 100644 --- a/board/adi/sc598-som-ezkit/sc598-som-ezkit.env +++ b/board/adi/sc598-som-ezkit/sc598-som-ezkit.env @@ -11,5 +11,6 @@ loadaddr=CONFIG_SC5XX_LOADADDR #define USE_OSPI #define USE_RAM #define USE_MMC +#define USE_USB #include diff --git a/include/env/adi/adi_boot.env b/include/env/adi/adi_boot.env index be4d8521ac9..00757fe7c99 100644 --- a/include/env/adi/adi_boot.env +++ b/include/env/adi/adi_boot.env @@ -67,3 +67,11 @@ ramboot=wget ${loadaddr} ${serverip}:/fitImage; run ramargs; bootm ${loadaddr} #endif + +#if defined(USE_USB) +usbargs=setenv bootargs root=/dev/sda2 rw rootfstype=ext4 rootwait ${adi_bootargs} +usbboot=usb start; + run usbargs; + ext4load usb 0:1 ${loadaddr} /fitImage; + bootm ${loadaddr} +#endif -- cgit v1.3.1 From 87ea6e67959099804faf4eb85d93a41f18db71c9 Mon Sep 17 00:00:00 2001 From: Caleb Ethridge Date: Thu, 21 May 2026 09:53:20 -0400 Subject: mach-sc5xx: sc573: Rename EZKIT board to EZLITE Rename the SC573 EZKIT board to EZLITE across the device tree, defconfig, board file, and related Kconfig/Makefile entries to match with release naming. EZKIT was used internally before the official product release. Signed-off-by: Caleb Ethridge Reviewed-by: Simon Glass --- arch/arm/dts/Makefile | 2 +- arch/arm/dts/sc573-ezkit.dts | 253 ------------------------ arch/arm/dts/sc573-ezlite.dts | 253 ++++++++++++++++++++++++ arch/arm/mach-sc5xx/Kconfig | 8 +- arch/arm/mach-sc5xx/init/dmcinit.c | 2 +- board/adi/sc573-ezkit/Kconfig | 116 ----------- board/adi/sc573-ezkit/Makefile | 6 - board/adi/sc573-ezkit/sc573-ezkit.c | 21 -- board/adi/sc573-ezkit/sc573-ezkit.env | 15 -- board/adi/sc573-ezlite/Kconfig | 116 +++++++++++ board/adi/sc573-ezlite/Makefile | 6 + board/adi/sc573-ezlite/sc573-ezlite.c | 21 ++ board/adi/sc573-ezlite/sc573-ezlite.env | 15 ++ configs/sc573-ezkit_defconfig | 85 -------- configs/sc573-ezlite_defconfig | 85 ++++++++ doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml | 2 +- include/configs/sc573-ezkit.h | 18 -- include/configs/sc573-ezlite.h | 18 ++ 18 files changed, 521 insertions(+), 521 deletions(-) delete mode 100644 arch/arm/dts/sc573-ezkit.dts create mode 100644 arch/arm/dts/sc573-ezlite.dts delete mode 100644 board/adi/sc573-ezkit/Kconfig delete mode 100644 board/adi/sc573-ezkit/Makefile delete mode 100644 board/adi/sc573-ezkit/sc573-ezkit.c delete mode 100644 board/adi/sc573-ezkit/sc573-ezkit.env create mode 100644 board/adi/sc573-ezlite/Kconfig create mode 100644 board/adi/sc573-ezlite/Makefile create mode 100644 board/adi/sc573-ezlite/sc573-ezlite.c create mode 100644 board/adi/sc573-ezlite/sc573-ezlite.env delete mode 100644 configs/sc573-ezkit_defconfig create mode 100644 configs/sc573-ezlite_defconfig delete mode 100644 include/configs/sc573-ezkit.h create mode 100644 include/configs/sc573-ezlite.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d5dd0867622..1e8676284b7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1178,7 +1178,7 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb \ imx8mm-cl-iot-gate-ied-tpm0.dtbo \ imx8mm-cl-iot-gate-ied-tpm1.dtbo -dtb-$(CONFIG_TARGET_SC573_EZKIT) += sc573-ezkit.dtb +dtb-$(CONFIG_TARGET_SC573_EZLITE) += sc573-ezlite.dtb dtb-$(CONFIG_TARGET_SC584_EZKIT) += sc584-ezkit.dtb dtb-$(CONFIG_TARGET_SC589_MINI) += sc589-mini.dtb dtb-$(CONFIG_TARGET_SC589_EZKIT) += sc589-ezkit.dtb diff --git a/arch/arm/dts/sc573-ezkit.dts b/arch/arm/dts/sc573-ezkit.dts deleted file mode 100644 index 4a3d1ed5c56..00000000000 --- a/arch/arm/dts/sc573-ezkit.dts +++ /dev/null @@ -1,253 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2024 - Analog Devices, Inc. - */ - -/dts-v1/; - -#include "sc5xx.dtsi" -#include "sc57x.dtsi" - -/ { - model = "ADI SC573-EZKIT"; - compatible = "adi,sc573-ezkit", "adi,sc57x"; -}; - -&i2c0 { - gpio_expander0: mcp23017@21 { - compatible = "microchip,mcp23017"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - bootph-pre-ram; - - eeprom { - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - output-low; - line-name = "eeprom-en"; - bootph-pre-ram; - }; - - uart0-flow-en { - gpio-hog; - gpios = <1 GPIO_ACTIVE_LOW>; - output-low; - line-name = "uart0-flow-en"; - bootph-pre-ram; - }; - - mlb { - gpio-hog; - gpios = <5 GPIO_ACTIVE_LOW>; - output-low; - line-name = "mlb-en"; - bootph-pre-ram; - }; - - can0 { - gpio-hog; - gpios = <6 GPIO_ACTIVE_LOW>; - output-low; - line-name = "can0-en"; - bootph-pre-ram; - }; - - can1 { - gpio-hog; - gpios = <7 GPIO_ACTIVE_LOW>; - output-low; - line-name = "can1-en"; - bootph-pre-ram; - }; - - adau1962 { - gpio-hog; - gpios = <8 GPIO_ACTIVE_LOW>; - output-high; - line-name = "adau1962-en"; - bootph-pre-ram; - }; - - adau1979 { - gpio-hog; - gpios = <9 GPIO_ACTIVE_LOW>; - output-high; - line-name = "adau1979-en"; - bootph-pre-ram; - }; - - sd-wp-en { - gpio-hog; - gpios = <11 GPIO_ACTIVE_LOW>; - output-low; - line-name = "sd-wp-en"; - bootph-pre-ram; - }; - - spi2flash-cs { - gpio-hog; - gpios = <12 GPIO_ACTIVE_LOW>; - output-high; - line-name = "spi2flash-cs"; - bootph-pre-ram; - }; - - spi2d2-d3 { - gpio-hog; - gpios = <13 GPIO_ACTIVE_LOW>; - output-high; - line-name = "spi2d2-d3-en"; - bootph-pre-ram; - }; - - spdif-opt { - gpio-hog; - gpios = <14 GPIO_ACTIVE_LOW>; - output-low; - line-name = "spdif-optical-en"; - bootph-pre-ram; - }; - - spdif-dig { - gpio-hog; - gpios = <15 GPIO_ACTIVE_LOW>; - output-low; - line-name = "spdif-digital-en"; - bootph-pre-ram; - }; - }; - - gpio_expander1: mcp23017@22 { - compatible = "microchip,mcp23017"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - bootph-pre-ram; - - pushbutton3 { - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pushbutton3-en"; - bootph-pre-ram; - }; - - pushbutton2 { - gpio-hog; - gpios = <1 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pushbutton2-en"; - bootph-pre-ram; - }; - - pushbutton1 { - gpio-hog; - gpios = <2 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pushbutton1-en"; - bootph-pre-ram; - }; - - leds { - gpio-hog; - gpios = <3 GPIO_ACTIVE_LOW>; - output-low; - line-name = "leds-en"; - bootph-pre-ram; - }; - - flg0 { - gpio-hog; - gpios = <4 GPIO_ACTIVE_LOW>; - output-low; - line-name = "flg0_loop"; - bootph-pre-ram; - }; - - flg1 { - gpio-hog; - gpios = <5 GPIO_ACTIVE_LOW>; - output-low; - line-name = "flg1_loop"; - bootph-pre-ram; - }; - - flg2 { - gpio-hog; - gpios = <6 GPIO_ACTIVE_LOW>; - output-low; - line-name = "flg2_loop"; - bootph-pre-ram; - }; - - flg3 { - gpio-hog; - gpios = <7 GPIO_ACTIVE_LOW>; - output-low; - line-name = "flg3_loop"; - bootph-pre-ram; - }; - - adau1977 { - gpio-hog; - gpios = <8 GPIO_ACTIVE_LOW>; - output-low; - line-name = "adau1977_en"; - bootph-pre-ram; - }; - - adau1977_fault_rst { - gpio-hog; - gpios = <9 GPIO_ACTIVE_LOW>; - output-low; - line-name = "adau1977_fault_rst_en"; - bootph-pre-ram; - }; - - thumbwheel { - gpio-hog; - gpios = <10 GPIO_ACTIVE_LOW>; - output-low; - line-name = "thumbwheel_oe"; - bootph-pre-ram; - }; - - engine_rpm { - gpio-hog; - gpios = <11 GPIO_ACTIVE_LOW>; - output-low; - line-name = "engine_rpm_oe"; - bootph-pre-ram; - }; - }; -}; - -ð0 { - snps,reset-gpio = <&gpio0 ADI_ADSP_PIN('A', 5) GPIO_ACTIVE_LOW>; -}; - -&gpio0 { - emac0_phy_pwdn { - gpio-hog; - output-high; - gpios = ; - }; -}; - -&mmc { - status = "okay"; -}; - -&spi2 { - flash1: is25lp512@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor", "is25lp512"; - reg = <1>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-max-frequency = <10000000>; - bootph-pre-ram; - }; -}; diff --git a/arch/arm/dts/sc573-ezlite.dts b/arch/arm/dts/sc573-ezlite.dts new file mode 100644 index 00000000000..57604d707f7 --- /dev/null +++ b/arch/arm/dts/sc573-ezlite.dts @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2024 - Analog Devices, Inc. + */ + +/dts-v1/; + +#include "sc5xx.dtsi" +#include "sc57x.dtsi" + +/ { + model = "ADI SC573-EZLITE"; + compatible = "adi,sc573-ezlite", "adi,sc57x"; +}; + +&i2c0 { + gpio_expander0: mcp23017@21 { + compatible = "microchip,mcp23017"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + bootph-pre-ram; + + eeprom { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-low; + line-name = "eeprom-en"; + bootph-pre-ram; + }; + + uart0-flow-en { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "uart0-flow-en"; + bootph-pre-ram; + }; + + mlb { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "mlb-en"; + bootph-pre-ram; + }; + + can0 { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "can0-en"; + bootph-pre-ram; + }; + + can1 { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-low; + line-name = "can1-en"; + bootph-pre-ram; + }; + + adau1962 { + gpio-hog; + gpios = <8 GPIO_ACTIVE_LOW>; + output-high; + line-name = "adau1962-en"; + bootph-pre-ram; + }; + + adau1979 { + gpio-hog; + gpios = <9 GPIO_ACTIVE_LOW>; + output-high; + line-name = "adau1979-en"; + bootph-pre-ram; + }; + + sd-wp-en { + gpio-hog; + gpios = <11 GPIO_ACTIVE_LOW>; + output-low; + line-name = "sd-wp-en"; + bootph-pre-ram; + }; + + spi2flash-cs { + gpio-hog; + gpios = <12 GPIO_ACTIVE_LOW>; + output-high; + line-name = "spi2flash-cs"; + bootph-pre-ram; + }; + + spi2d2-d3 { + gpio-hog; + gpios = <13 GPIO_ACTIVE_LOW>; + output-high; + line-name = "spi2d2-d3-en"; + bootph-pre-ram; + }; + + spdif-opt { + gpio-hog; + gpios = <14 GPIO_ACTIVE_LOW>; + output-low; + line-name = "spdif-optical-en"; + bootph-pre-ram; + }; + + spdif-dig { + gpio-hog; + gpios = <15 GPIO_ACTIVE_LOW>; + output-low; + line-name = "spdif-digital-en"; + bootph-pre-ram; + }; + }; + + gpio_expander1: mcp23017@22 { + compatible = "microchip,mcp23017"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + bootph-pre-ram; + + pushbutton3 { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pushbutton3-en"; + bootph-pre-ram; + }; + + pushbutton2 { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pushbutton2-en"; + bootph-pre-ram; + }; + + pushbutton1 { + gpio-hog; + gpios = <2 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pushbutton1-en"; + bootph-pre-ram; + }; + + leds { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-low; + line-name = "leds-en"; + bootph-pre-ram; + }; + + flg0 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "flg0_loop"; + bootph-pre-ram; + }; + + flg1 { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "flg1_loop"; + bootph-pre-ram; + }; + + flg2 { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "flg2_loop"; + bootph-pre-ram; + }; + + flg3 { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-low; + line-name = "flg3_loop"; + bootph-pre-ram; + }; + + adau1977 { + gpio-hog; + gpios = <8 GPIO_ACTIVE_LOW>; + output-low; + line-name = "adau1977_en"; + bootph-pre-ram; + }; + + adau1977_fault_rst { + gpio-hog; + gpios = <9 GPIO_ACTIVE_LOW>; + output-low; + line-name = "adau1977_fault_rst_en"; + bootph-pre-ram; + }; + + thumbwheel { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-low; + line-name = "thumbwheel_oe"; + bootph-pre-ram; + }; + + engine_rpm { + gpio-hog; + gpios = <11 GPIO_ACTIVE_LOW>; + output-low; + line-name = "engine_rpm_oe"; + bootph-pre-ram; + }; + }; +}; + +ð0 { + snps,reset-gpio = <&gpio0 ADI_ADSP_PIN('A', 5) GPIO_ACTIVE_LOW>; +}; + +&gpio0 { + emac0_phy_pwdn { + gpio-hog; + output-high; + gpios = ; + }; +}; + +&mmc { + status = "okay"; +}; + +&spi2 { + flash1: is25lp512@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "is25lp512"; + reg = <1>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <10000000>; + bootph-pre-ram; + }; +}; diff --git a/arch/arm/mach-sc5xx/Kconfig b/arch/arm/mach-sc5xx/Kconfig index 70fab57fb3c..e311a8adf9a 100644 --- a/arch/arm/mach-sc5xx/Kconfig +++ b/arch/arm/mach-sc5xx/Kconfig @@ -25,7 +25,7 @@ config SC57X bool "SC57x series" select COMMON_CLK_ADI_SC57X select CPU_V7A - select TARGET_SC573_EZKIT + select TARGET_SC573_EZLITE config SC58X bool "SC58x series" @@ -51,8 +51,8 @@ endchoice if SC57X -config TARGET_SC573_EZKIT - bool "Support SC573-EZKIT" +config TARGET_SC573_EZLITE + bool "Support SC573-EZLITE" endif @@ -600,6 +600,6 @@ source "board/adi/sc594-som-ezlite/Kconfig" source "board/adi/sc589-ezkit/Kconfig" source "board/adi/sc589-mini/Kconfig" source "board/adi/sc584-ezkit/Kconfig" -source "board/adi/sc573-ezkit/Kconfig" +source "board/adi/sc573-ezlite/Kconfig" endif diff --git a/arch/arm/mach-sc5xx/init/dmcinit.c b/arch/arm/mach-sc5xx/init/dmcinit.c index 12052613feb..2026735cc21 100644 --- a/arch/arm/mach-sc5xx/init/dmcinit.c +++ b/arch/arm/mach-sc5xx/init/dmcinit.c @@ -101,7 +101,7 @@ #ifdef CONFIG_TARGET_SC584_EZKIT #define DMC_PADCTL2_VALUE 0x0078283C -#elif CONFIG_TARGET_SC573_EZKIT +#elif CONFIG_TARGET_SC573_EZLITE #define DMC_PADCTL2_VALUE 0x00782828 #elif CONFIG_TARGET_SC589_MINI || CONFIG_TARGET_SC589_EZKIT #define DMC_PADCTL2_VALUE 0x00783C3C diff --git a/board/adi/sc573-ezkit/Kconfig b/board/adi/sc573-ezkit/Kconfig deleted file mode 100644 index 328563c1296..00000000000 --- a/board/adi/sc573-ezkit/Kconfig +++ /dev/null @@ -1,116 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# -# (C) Copyright 2024 - Analog Devices, Inc. - -if TARGET_SC573_EZKIT - -config SYS_BOARD - default "sc573-ezkit" - -config SYS_CONFIG_NAME - default "sc573-ezkit" - -config LDR_CPU - default "ADSP-SC573-0.0" - -config DEFAULT_DEVICE_TREE - default "sc573-ezkit" - -config ADI_IMAGE - default "tiny" - -config CUSTOM_SYS_INIT_SP_ADDR - default 0x8203f000 - -# SPI Flash - -config SF_DEFAULT_BUS - default 2 - -config SF_DEFAULT_CS - default 1 - -config SF_DEFAULT_SPEED - default 10000000 - -# Clocks - -config CGU0_DF_DIV - default 0 - -config CGU0_VCO_MULT - default 18 - -config CGU0_CCLK_DIV - default 1 - -config CGU0_SCLK_DIV - default 2 - -config CGU0_SCLK0_DIV - default 2 - -config CGU0_SCLK1_DIV - default 2 - -config CGU0_DCLK_DIV - default 2 - -config CGU0_OCLK_DIV - default 3 - -config CGU1_VCO_MULT - default 5 - -config CGU1_DF_DIV - default 0 - -config CGU1_CCLK_DIV - default 1 - -config CGU1_SCLK_DIV - default 2 - -config CGU1_SCLK0_DIV - default 2 - -config CGU1_SCLK1_DIV - default 2 - -config CGU1_DCLK_DIV - default 2 - -config CGU1_OCLK_DIV - default 3 - -config CDU0_CLKO0 - default 1 - -config CDU0_CLKO1 - default 1 - -config CDU0_CLKO2 - default 1 - -config CDU0_CLKO3 - default 1 - -config CDU0_CLKO4 - default 1 - -config CDU0_CLKO5 - default 1 - -config CDU0_CLKO6 - default 1 - -config CDU0_CLKO7 - default 5 - -config CDU0_CLKO8 - default 1 - -config CDU0_CLKO9 - default 1 - -endif diff --git a/board/adi/sc573-ezkit/Makefile b/board/adi/sc573-ezkit/Makefile deleted file mode 100644 index 0ea725b992b..00000000000 --- a/board/adi/sc573-ezkit/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# -# (C) Copyright 2025 - Analog Devices, Inc. -# - -obj-y += sc573-ezkit.o diff --git a/board/adi/sc573-ezkit/sc573-ezkit.c b/board/adi/sc573-ezkit/sc573-ezkit.c deleted file mode 100644 index 464142b27a5..00000000000 --- a/board/adi/sc573-ezkit/sc573-ezkit.c +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2025 - Analog Devices, Inc. - */ - -#include -#include -#include -#include - -int board_phy_config(struct phy_device *phydev) -{ - fixup_dp83867_phy(phydev); - return 0; -} - -int board_init(void) -{ - sc5xx_enable_rgmii(); - return 0; -} diff --git a/board/adi/sc573-ezkit/sc573-ezkit.env b/board/adi/sc573-ezkit/sc573-ezkit.env deleted file mode 100644 index e1ad4f3716f..00000000000 --- a/board/adi/sc573-ezkit/sc573-ezkit.env +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later+ */ -/* - * (C) Copyright 2024 - Analog Devices, Inc. - */ - -adi_image_offset=0xe0000 -loadaddr=CONFIG_SC5XX_LOADADDR - -#define USE_NFS -#define USE_SPI -#define USE_RAM -#define USE_MMC -#define USE_USB - -#include diff --git a/board/adi/sc573-ezlite/Kconfig b/board/adi/sc573-ezlite/Kconfig new file mode 100644 index 00000000000..f3b848ef0f7 --- /dev/null +++ b/board/adi/sc573-ezlite/Kconfig @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2024 - Analog Devices, Inc. + +if TARGET_SC573_EZLITE + +config SYS_BOARD + default "sc573-ezlite" + +config SYS_CONFIG_NAME + default "sc573-ezlite" + +config LDR_CPU + default "ADSP-SC573-0.0" + +config DEFAULT_DEVICE_TREE + default "sc573-ezlite" + +config ADI_IMAGE + default "tiny" + +config CUSTOM_SYS_INIT_SP_ADDR + default 0x8203f000 + +# SPI Flash + +config SF_DEFAULT_BUS + default 2 + +config SF_DEFAULT_CS + default 1 + +config SF_DEFAULT_SPEED + default 10000000 + +# Clocks + +config CGU0_DF_DIV + default 0 + +config CGU0_VCO_MULT + default 18 + +config CGU0_CCLK_DIV + default 1 + +config CGU0_SCLK_DIV + default 2 + +config CGU0_SCLK0_DIV + default 2 + +config CGU0_SCLK1_DIV + default 2 + +config CGU0_DCLK_DIV + default 2 + +config CGU0_OCLK_DIV + default 3 + +config CGU1_VCO_MULT + default 5 + +config CGU1_DF_DIV + default 0 + +config CGU1_CCLK_DIV + default 1 + +config CGU1_SCLK_DIV + default 2 + +config CGU1_SCLK0_DIV + default 2 + +config CGU1_SCLK1_DIV + default 2 + +config CGU1_DCLK_DIV + default 2 + +config CGU1_OCLK_DIV + default 3 + +config CDU0_CLKO0 + default 1 + +config CDU0_CLKO1 + default 1 + +config CDU0_CLKO2 + default 1 + +config CDU0_CLKO3 + default 1 + +config CDU0_CLKO4 + default 1 + +config CDU0_CLKO5 + default 1 + +config CDU0_CLKO6 + default 1 + +config CDU0_CLKO7 + default 5 + +config CDU0_CLKO8 + default 1 + +config CDU0_CLKO9 + default 1 + +endif diff --git a/board/adi/sc573-ezlite/Makefile b/board/adi/sc573-ezlite/Makefile new file mode 100644 index 00000000000..77c55af6240 --- /dev/null +++ b/board/adi/sc573-ezlite/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2025 - Analog Devices, Inc. +# + +obj-y += sc573-ezlite.o diff --git a/board/adi/sc573-ezlite/sc573-ezlite.c b/board/adi/sc573-ezlite/sc573-ezlite.c new file mode 100644 index 00000000000..464142b27a5 --- /dev/null +++ b/board/adi/sc573-ezlite/sc573-ezlite.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2025 - Analog Devices, Inc. + */ + +#include +#include +#include +#include + +int board_phy_config(struct phy_device *phydev) +{ + fixup_dp83867_phy(phydev); + return 0; +} + +int board_init(void) +{ + sc5xx_enable_rgmii(); + return 0; +} diff --git a/board/adi/sc573-ezlite/sc573-ezlite.env b/board/adi/sc573-ezlite/sc573-ezlite.env new file mode 100644 index 00000000000..e1ad4f3716f --- /dev/null +++ b/board/adi/sc573-ezlite/sc573-ezlite.env @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later+ */ +/* + * (C) Copyright 2024 - Analog Devices, Inc. + */ + +adi_image_offset=0xe0000 +loadaddr=CONFIG_SC5XX_LOADADDR + +#define USE_NFS +#define USE_SPI +#define USE_RAM +#define USE_MMC +#define USE_USB + +#include diff --git a/configs/sc573-ezkit_defconfig b/configs/sc573-ezkit_defconfig deleted file mode 100644 index 4320c73fd39..00000000000 --- a/configs/sc573-ezkit_defconfig +++ /dev/null @@ -1,85 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_ARM_CACHE_WRITETHROUGH=y -CONFIG_ARCH_SC5XX=y -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SPL_GPIO=y -CONFIG_DM_GPIO=y -CONFIG_SPL_SYS_MALLOC_F_LEN=0x10000 -CONFIG_SPL_SERIAL=y -CONFIG_SC5XX_LOADADDR=0x83000000 -CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 -CONFIG_CGU0_CLKOUTSEL=7 -# CONFIG_EFI_LOADER is not set -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run ramboot" -CONFIG_SYS_CBSIZE=512 -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_I2C=y -CONFIG_CMD_BOOTZ=y -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -# CONFIG_CMD_ELF is not set -CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_MTD=y -# CONFIG_CMD_PINMUX is not set -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_SYS_DISABLE_AUTOLOAD=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_DNS=y -CONFIG_CMD_MII=y -# CONFIG_CMD_MDIO is not set -CONFIG_CMD_PING=y -CONFIG_CMD_WGET=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y -CONFIG_ENV_OVERWRITE=y -CONFIG_USE_HOSTNAME=y -CONFIG_HOSTNAME="sc573-ezkit" -CONFIG_NET_RETRY_COUNT=20 -CONFIG_IP_DEFRAG=y -CONFIG_SPL_CLK=y -CONFIG_SPL_CLK_CCF=y -CONFIG_GPIO_HOG=y -CONFIG_SPL_GPIO_HOG=y -CONFIG_DM_GPIO_LOOKUP_LABEL=y -CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y -CONFIG_MCP230XX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_DM_I2C_GPIO=y -CONFIG_SYS_I2C_ADI=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_SNPS=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_DW_ALTDESCRIPTOR=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_GENERIC is not set -CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_GENERIC is not set -CONFIG_SPECIFY_CONSOLE_INDEX=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_ADI_SPI3=y -CONFIG_SPL_TIMER=y -CONFIG_USB=y -CONFIG_USB_MUSB_HOST=y -CONFIG_USB_MUSB_SC5XX=y -CONFIG_USB_MUSB_PIO_ONLY=y -CONFIG_USB_STORAGE=y -CONFIG_FAT_WRITE=y -# CONFIG_REGEX is not set diff --git a/configs/sc573-ezlite_defconfig b/configs/sc573-ezlite_defconfig new file mode 100644 index 00000000000..f6305451c27 --- /dev/null +++ b/configs/sc573-ezlite_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_SYS_ARM_CACHE_WRITETHROUGH=y +CONFIG_ARCH_SC5XX=y +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SPL_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_SERIAL=y +CONFIG_SC5XX_LOADADDR=0x83000000 +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 +CONFIG_CGU0_CLKOUTSEL=7 +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ramboot" +CONFIG_SYS_CBSIZE=512 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_I2C=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +# CONFIG_CMD_PINMUX is not set +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_SYS_DISABLE_AUTOLOAD=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_MII=y +# CONFIG_CMD_MDIO is not set +CONFIG_CMD_PING=y +CONFIG_CMD_WGET=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_ENV_OVERWRITE=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="sc573-ezlite" +CONFIG_NET_RETRY_COUNT=20 +CONFIG_IP_DEFRAG=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y +CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y +CONFIG_MCP230XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_ADI=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_SNPS=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ADI_SPI3=y +CONFIG_SPL_TIMER=y +CONFIG_USB=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_MUSB_SC5XX=y +CONFIG_USB_MUSB_PIO_ONLY=y +CONFIG_USB_STORAGE=y +CONFIG_FAT_WRITE=y +# CONFIG_REGEX is not set diff --git a/doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml b/doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml index df976c7ae73..ae3b5e6092a 100644 --- a/doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml +++ b/doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml @@ -18,7 +18,7 @@ properties: oneOf: - description: SC57X Series Boards items: - - const: adi,sc573-ezkit + - const: adi,sc573-ezlite - const: adi,sc57x - description: SC58X Series Boards diff --git a/include/configs/sc573-ezkit.h b/include/configs/sc573-ezkit.h deleted file mode 100644 index 42e42f8150b..00000000000 --- a/include/configs/sc573-ezkit.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * (C) Copyright 2024 - Analog Devices, Inc. - */ - -#ifndef __CONFIG_SC573_EZKIT_H -#define __CONFIG_SC573_EZKIT_H - -/* - * Memory Settings - */ -#define MEM_MT41K128M16JT -#define MEM_DMC0 - -#define CFG_SYS_SDRAM_BASE 0x82000000 -#define CFG_SYS_SDRAM_SIZE 0xe000000 - -#endif diff --git a/include/configs/sc573-ezlite.h b/include/configs/sc573-ezlite.h new file mode 100644 index 00000000000..590a8f06fb5 --- /dev/null +++ b/include/configs/sc573-ezlite.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2024 - Analog Devices, Inc. + */ + +#ifndef __CONFIG_SC573_EZLITE_H +#define __CONFIG_SC573_EZLITE_H + +/* + * Memory Settings + */ +#define MEM_MT41K128M16JT +#define MEM_DMC0 + +#define CFG_SYS_SDRAM_BASE 0x82000000 +#define CFG_SYS_SDRAM_SIZE 0xe000000 + +#endif -- cgit v1.3.1 From a6438a10267e52898448711281ae631945b87e84 Mon Sep 17 00:00:00 2001 From: Caleb Ethridge Date: Thu, 21 May 2026 09:53:22 -0400 Subject: mach-sc5xx: Update SPI bootargs for ubifs Update the bootargs used in SPI/OSPI bootmode to reflect change from jffs2 to ubifs for the SPI's filesystem, and remove the jffs2file variable from the environment as it is now unused. Signed-off-by: Caleb Ethridge --- include/env/adi/adi_boot.env | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/env/adi/adi_boot.env b/include/env/adi/adi_boot.env index 00757fe7c99..b75baabdca6 100644 --- a/include/env/adi/adi_boot.env +++ b/include/env/adi/adi_boot.env @@ -47,7 +47,7 @@ mmcboot=mmc rescan; #endif #if defined(USE_SPI) -spiargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2 ${adi_bootargs}; setenv sfdev CONFIG_SC_BOOT_SPI_BUS:CONFIG_SC_BOOT_SPI_SSEL +spiargs=setenv bootargs rootfstype=ubifs root=ubi0:rootfs ubi.mtd=3 rw ${adi_bootargs}; setenv sfdev CONFIG_SC_BOOT_SPI_BUS:CONFIG_SC_BOOT_SPI_SSEL spiboot=run spiargs; sf probe ${sfdev}; sf read ${loadaddr} ${adi_image_offset} 0xf00000; @@ -55,7 +55,7 @@ spiboot=run spiargs; #endif #if defined(USE_OSPI) -ospiargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2 ${adi_bootargs}; setenv sfdev CONFIG_SC_BOOT_OSPI_BUS:CONFIG_SC_BOOT_OSPI_SSEL +ospiargs=setenv bootargs rootfstype=ubifs root=ubi0:rootfs ubi.mtd=3 rw ${adi_bootargs}; setenv sfdev CONFIG_SC_BOOT_OSPI_BUS:CONFIG_SC_BOOT_OSPI_SSEL ospiboot=run ospiargs; sf probe ${sfdev}; sf read ${loadaddr} ${adi_image_offset} 0xf00000; -- cgit v1.3.1 From c6796425da45f63661459e31cb7809f517080417 Mon Sep 17 00:00:00 2001 From: Caleb Ethridge Date: Thu, 21 May 2026 09:53:24 -0400 Subject: arm: sc5xx: Remove SC5XX_LOADADDR Remove the SC5XX_LOADADDR Kconfig option, replace its users with CONFIG_SYS_LOAD_ADDR, and update the ADI boot environment to use `loadaddr`. SC5XX_LOADADDR was an ADI-specific duplicate of standard U-Boot load address handling. U-Boot already uses CONFIG_SYS_LOAD_ADDR for the default load address and `loadaddr` for boot commands, so keeping separate SC5XX-specific names is redundant. Signed-off-by: Ozan Durgut Signed-off-by: Caleb Ethridge --- arch/arm/mach-sc5xx/Kconfig | 6 ------ board/adi/sc584-ezkit/sc584-ezkit.env | 3 --- board/adi/sc589-ezkit/sc589-ezkit.env | 3 --- board/adi/sc589-mini/sc589-mini.env | 3 --- board/adi/sc594-som-ezkit/sc594-som-ezkit.env | 3 --- board/adi/sc594-som-ezlite/sc594-som-ezlite.env | 3 --- board/adi/sc598-som-ezkit/sc598-som-ezkit.env | 3 --- board/adi/sc598-som-ezlite/sc598-som-ezlite.env | 2 -- configs/sc573-ezlite_defconfig | 2 +- configs/sc584-ezkit_defconfig | 2 +- configs/sc589-ezkit_defconfig | 2 +- configs/sc589-mini_defconfig | 2 +- configs/sc594-som-ezkit-spl_defconfig | 2 +- configs/sc594-som-ezlite-spl_defconfig | 2 +- configs/sc598-som-ezkit-spl_defconfig | 2 +- configs/sc598-som-ezlite-spl_defconfig | 2 +- include/env/adi/adi_boot.env | 18 ++++++++---------- 17 files changed, 16 insertions(+), 44 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-sc5xx/Kconfig b/arch/arm/mach-sc5xx/Kconfig index e311a8adf9a..44402b2568d 100644 --- a/arch/arm/mach-sc5xx/Kconfig +++ b/arch/arm/mach-sc5xx/Kconfig @@ -140,12 +140,6 @@ config SC5XX_ROOTFS_OFFSET help The default offset where the rootfs is located. -config SC5XX_LOADADDR - hex "Load address" - default 0x90000000 - help - The default load address for u-boot. - config ADI_IMAGE string "ADI fitImage type" help diff --git a/board/adi/sc584-ezkit/sc584-ezkit.env b/board/adi/sc584-ezkit/sc584-ezkit.env index 905523fb151..0b8035ca6b1 100644 --- a/board/adi/sc584-ezkit/sc584-ezkit.env +++ b/board/adi/sc584-ezkit/sc584-ezkit.env @@ -3,9 +3,6 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=0xd0000 -loadaddr=CONFIG_SC5XX_LOADADDR - #define USE_NFS #define USE_SPI #define USE_RAM diff --git a/board/adi/sc589-ezkit/sc589-ezkit.env b/board/adi/sc589-ezkit/sc589-ezkit.env index 02567830c16..00f90c7942e 100644 --- a/board/adi/sc589-ezkit/sc589-ezkit.env +++ b/board/adi/sc589-ezkit/sc589-ezkit.env @@ -3,9 +3,6 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=0xd0000 -loadaddr=CONFIG_SC5XX_LOADADDR - #define USE_NFS #define USE_RAM #define USE_MMC diff --git a/board/adi/sc589-mini/sc589-mini.env b/board/adi/sc589-mini/sc589-mini.env index 661c130b835..13079ed7527 100644 --- a/board/adi/sc589-mini/sc589-mini.env +++ b/board/adi/sc589-mini/sc589-mini.env @@ -3,9 +3,6 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=0xd0000 -loadaddr=CONFIG_SC5XX_LOADADDR - #define USE_NFS #define USE_RAM #define USE_SPI diff --git a/board/adi/sc594-som-ezkit/sc594-som-ezkit.env b/board/adi/sc594-som-ezkit/sc594-som-ezkit.env index f787d972339..324bfae4571 100644 --- a/board/adi/sc594-som-ezkit/sc594-som-ezkit.env +++ b/board/adi/sc594-som-ezkit/sc594-som-ezkit.env @@ -3,9 +3,6 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=0x100000 -loadaddr=CONFIG_SC5XX_LOADADDR - #define USE_NFS #define USE_SPI #define USE_OSPI diff --git a/board/adi/sc594-som-ezlite/sc594-som-ezlite.env b/board/adi/sc594-som-ezlite/sc594-som-ezlite.env index f787d972339..324bfae4571 100644 --- a/board/adi/sc594-som-ezlite/sc594-som-ezlite.env +++ b/board/adi/sc594-som-ezlite/sc594-som-ezlite.env @@ -3,9 +3,6 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=0x100000 -loadaddr=CONFIG_SC5XX_LOADADDR - #define USE_NFS #define USE_SPI #define USE_OSPI diff --git a/board/adi/sc598-som-ezkit/sc598-som-ezkit.env b/board/adi/sc598-som-ezkit/sc598-som-ezkit.env index f787d972339..324bfae4571 100644 --- a/board/adi/sc598-som-ezkit/sc598-som-ezkit.env +++ b/board/adi/sc598-som-ezkit/sc598-som-ezkit.env @@ -3,9 +3,6 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=0x100000 -loadaddr=CONFIG_SC5XX_LOADADDR - #define USE_NFS #define USE_SPI #define USE_OSPI diff --git a/board/adi/sc598-som-ezlite/sc598-som-ezlite.env b/board/adi/sc598-som-ezlite/sc598-som-ezlite.env index d5364df1613..fbb0565dac4 100644 --- a/board/adi/sc598-som-ezlite/sc598-som-ezlite.env +++ b/board/adi/sc598-som-ezlite/sc598-som-ezlite.env @@ -3,7 +3,5 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_image_offset=0x100000 -loadaddr=CONFIG_SC5XX_LOADADDR #include diff --git a/configs/sc573-ezlite_defconfig b/configs/sc573-ezlite_defconfig index f6305451c27..cbf24234cc3 100644 --- a/configs/sc573-ezlite_defconfig +++ b/configs/sc573-ezlite_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_DM_GPIO=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_SERIAL=y -CONFIG_SC5XX_LOADADDR=0x83000000 +CONFIG_SYS_LOAD_ADDR=0x83000000 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_CGU0_CLKOUTSEL=7 # CONFIG_EFI_LOADER is not set diff --git a/configs/sc584-ezkit_defconfig b/configs/sc584-ezkit_defconfig index 52ab7c9337b..bb24b31b2c0 100644 --- a/configs/sc584-ezkit_defconfig +++ b/configs/sc584-ezkit_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_STACK=0x200C0000 CONFIG_SPL_BSS_START_ADDR=0x200A0000 CONFIG_SPL_BSS_MAX_SIZE=0x8000 CONFIG_SC58X=y -CONFIG_SC5XX_LOADADDR=0x89300000 +CONFIG_SYS_LOAD_ADDR=0x89300000 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_ADI_BUG_EZKHW21=y CONFIG_CGU0_CLKOUTSEL=7 diff --git a/configs/sc589-ezkit_defconfig b/configs/sc589-ezkit_defconfig index d8982f62d82..d3f0380bfed 100644 --- a/configs/sc589-ezkit_defconfig +++ b/configs/sc589-ezkit_defconfig @@ -13,7 +13,7 @@ CONFIG_SPL_BSS_START_ADDR=0x200A0000 CONFIG_SPL_BSS_MAX_SIZE=0x8000 CONFIG_SC58X=y CONFIG_TARGET_SC589_EZKIT=y -CONFIG_SC5XX_LOADADDR=0xC3000000 +CONFIG_SYS_LOAD_ADDR=0xC3000000 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_ADI_USE_DMC1=y CONFIG_CGU0_CLKOUTSEL=7 diff --git a/configs/sc589-mini_defconfig b/configs/sc589-mini_defconfig index 78b39b6dd73..1bdede4b739 100644 --- a/configs/sc589-mini_defconfig +++ b/configs/sc589-mini_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL_BSS_START_ADDR=0x200A0000 CONFIG_SPL_BSS_MAX_SIZE=0x8000 CONFIG_SC58X=y CONFIG_TARGET_SC589_MINI=y -CONFIG_SC5XX_LOADADDR=0xC3000000 +CONFIG_SYS_LOAD_ADDR=0xC3000000 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_ADI_USE_DMC1=y # CONFIG_EFI_LOADER is not set diff --git a/configs/sc594-som-ezkit-spl_defconfig b/configs/sc594-som-ezkit-spl_defconfig index 23951d0b5f1..4f8be110ee4 100644 --- a/configs/sc594-som-ezkit-spl_defconfig +++ b/configs/sc594-som-ezkit-spl_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_SERIAL=y CONFIG_SC59X=y CONFIG_TARGET_SC594_SOM_EZKIT=y +CONFIG_SYS_LOAD_ADDR=0xA2000000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y @@ -74,4 +75,3 @@ CONFIG_SPL_TIMER=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y -CONFIG_SC5XX_LOADADDR=0xA2000000 diff --git a/configs/sc594-som-ezlite-spl_defconfig b/configs/sc594-som-ezlite-spl_defconfig index b4e71b5d2eb..c045c67569b 100644 --- a/configs/sc594-som-ezlite-spl_defconfig +++ b/configs/sc594-som-ezlite-spl_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x200E4000 CONFIG_SC59X=y +CONFIG_SYS_LOAD_ADDR=0xA2000000 CONFIG_CGU1_DIV_S1SELEX=16 CONFIG_CDU0_CLKO10=5 CONFIG_SF_DEFAULT_BUS=0 @@ -83,4 +84,3 @@ CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y # CONFIG_SPL_CRC8 is not set # CONFIG_TOOLS_MKEFICAPSULE is not set -CONFIG_SC5XX_LOADADDR=0xA2000000 diff --git a/configs/sc598-som-ezkit-spl_defconfig b/configs/sc598-som-ezkit-spl_defconfig index cd1bafd7486..e2fee0d0be8 100644 --- a/configs/sc598-som-ezkit-spl_defconfig +++ b/configs/sc598-som-ezkit-spl_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SC59X_64=y CONFIG_TARGET_SC598_SOM_EZKIT=y CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_CGU1_PLL3_DDRCLK=y CONFIG_CGU1_PLL3_VCO_MSEL=64 CONFIG_CGU1_PLL3_DCLK_DIV=2 @@ -107,4 +108,3 @@ CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y # CONFIG_SPL_CRC8 is not set # CONFIG_TOOLS_MKEFICAPSULE is not set -CONFIG_SC5XX_LOADADDR=0x90000000 diff --git a/configs/sc598-som-ezlite-spl_defconfig b/configs/sc598-som-ezlite-spl_defconfig index e4a975eedfc..9afe5c0789a 100644 --- a/configs/sc598-som-ezlite-spl_defconfig +++ b/configs/sc598-som-ezlite-spl_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x200E4000 CONFIG_SC59X_64=y CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_CGU1_PLL3_DDRCLK=y CONFIG_CGU1_PLL3_VCO_MSEL=64 CONFIG_CGU1_PLL3_DCLK_DIV=2 @@ -105,4 +106,3 @@ CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y # CONFIG_SPL_CRC8 is not set # CONFIG_TOOLS_MKEFICAPSULE is not set -CONFIG_SC5XX_LOADADDR=0x90000000 diff --git a/include/env/adi/adi_boot.env b/include/env/adi/adi_boot.env index b75baabdca6..3c83826cf9a 100644 --- a/include/env/adi/adi_boot.env +++ b/include/env/adi/adi_boot.env @@ -1,10 +1,3 @@ -/* - * A target board needs to set these variables for the commands below to work: - * - * - adi_image_offset, location of the fitImage on the SPI flash - * - loadaddr, where you want to load things - */ - #ifdef CONFIG_SC59X_64 #define EARLY_PRINTK earlycon=adi_uart,0x31003000 #else @@ -21,6 +14,11 @@ initrd_high=0xffffffffffffffff #else initrd_high=0xffffffff #endif +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) +adi_image_offset=0x100000 +#else +adi_image_offset=0xd0000 +#endif /* Args for each boot mode */ adi_bootargs=EARLY_PRINTK console=ttySC0,CONFIG_BAUDRATE vmalloc=512M @@ -35,7 +33,7 @@ nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath},tcp,nfs nfsboot=run nfsargs; run addip; wget ${loadaddr} ${serverip}:/fitImage; - bootm ${loadaddr} + bootm #endif #if defined(USE_MMC) @@ -43,7 +41,7 @@ mmcargs=setenv bootargs root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait ${adi_bo mmcboot=mmc rescan; ext4load mmc 0:1 ${loadaddr} /fitImage; run mmcargs; - bootm ${loadaddr} + bootm #endif #if defined(USE_SPI) @@ -65,7 +63,7 @@ ospiboot=run ospiargs; #if defined(USE_RAM) ramboot=wget ${loadaddr} ${serverip}:/fitImage; run ramargs; - bootm ${loadaddr} + bootm #endif #if defined(USE_USB) -- cgit v1.3.1 From 4355a9a5f0065b31e19178a377bc5f0a7968768d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 19 May 2026 18:09:53 -0600 Subject: linker_lists: Do not set "unused" attribute Whenever we declare something to be in a linker list, we want it to be included. This is why all of our linker scripts have a line similar to: KEEP(*(SORT(__u_boot_list*))); to ensure that any linker list found in any of the archives we are linking together makes it to the final object. Remove the places where we set an attribute saying that it is unused, or maybe_unused. Signed-off-by: Tom Rini --- include/linker_lists.h | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/linker_lists.h b/include/linker_lists.h index 4425fcb6785..a8b7e2c9f2b 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -69,7 +69,6 @@ */ #define ll_entry_declare(_type, _name, _list) \ _type _u_boot_list_2_##_list##_2_##_name __aligned(4) \ - __attribute__((unused)) \ __section("__u_boot_list_2_"#_list"_2_"#_name) /** @@ -92,7 +91,6 @@ */ #define ll_entry_declare_list(_type, _name, _list) \ _type _u_boot_list_2_##_list##_2_##_name[] __aligned(4) \ - __attribute__((unused)) \ __section("__u_boot_list_2_"#_list"_2_"#_name) /* @@ -125,7 +123,6 @@ #define ll_entry_start(_type, _list) \ ({ \ static char start[0] __aligned(CONFIG_LINKER_LIST_ALIGN) \ - __attribute__((unused)) \ __section("__u_boot_list_2_"#_list"_1"); \ _type * tmp = (_type *)&start; \ asm("":"+r"(tmp)); \ @@ -167,7 +164,7 @@ */ #define ll_entry_end(_type, _list) \ ({ \ - static char end[0] __aligned(1) __attribute__((unused)) \ + static char end[0] __aligned(1) \ __section("__u_boot_list_2_"#_list"_3"); \ _type * tmp = (_type *)&end; \ asm("":"+r"(tmp)); \ @@ -251,7 +248,7 @@ */ #define ll_start_decl(_sym, _type, _list) \ static _type _sym[0] __aligned(CONFIG_LINKER_LIST_ALIGN) \ - __maybe_unused __section("__u_boot_list_2_" #_list "_1") + __section("__u_boot_list_2_" #_list "_1") /* * ll_end_decl uses __aligned(1) to avoid padding before the end marker. @@ -259,7 +256,7 @@ */ #define ll_end_decl(_sym, _type, _list) \ static _type _sym[0] __aligned(1) \ - __maybe_unused __section("__u_boot_list_2_" #_list "_3") + __section("__u_boot_list_2_" #_list "_3") /** * ll_entry_get() - Retrieve entry from linker-generated array by name -- cgit v1.3.1 From 6e73890c739378776fe53f231471f202200bc79c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 19 May 2026 18:09:54 -0600 Subject: event: Remove obsolete comment and __used attributes Now that we have both resolved the problem on sandbox that lead to a comment about linker list entries being omitted as well as made linker lists never list themselves as unused, we can update the event header file. Remove the now obsolete comment and "__used" attribute marker. Reviewed-by: Simon Glass Signed-off-by: Tom Rini --- include/event.h | 35 ++--------------------------------- 1 file changed, 2 insertions(+), 33 deletions(-) (limited to 'include') diff --git a/include/event.h b/include/event.h index 3ce5f992b04..450281f666a 100644 --- a/include/event.h +++ b/include/event.h @@ -308,44 +308,13 @@ static inline const char *event_spy_id(struct evspy_info *spy) #endif } -/* - * It seems that LTO will drop list entries if it decides they are not used, - * although the conditions that cause this are unclear. - * - * The example found is the following: - * - * static int sandbox_misc_init_f(void *ctx, struct event *event) - * { - * return sandbox_early_getopt_check(); - * } - * EVENT_SPY_FULL(EVT_MISC_INIT_F, sandbox_misc_init_f); - * - * where EVENT_SPY_FULL uses ll_entry_declare() - * - * In this case, LTO decides to drop the sandbox_misc_init_f() function - * (which is fine) but then drops the linker-list entry too. This means - * that the code no longer works, in this case sandbox no-longer checks its - * command-line arguments properly. - * - * Without LTO, the KEEP() command in the .lds file is enough to keep the - * entry around. But with LTO it seems that the entry has already been - * dropped before the link script is considered. - * - * The only solution I can think of is to mark linker-list entries as 'used' - * using an attribute. This should be safe, since we don't actually want to drop - * any of these. However this does slightly limit LTO's optimisation choices. - * - * Another issue has come up, only with clang: using 'static' makes it throw - * away the linker-list entry sometimes, e.g. with the EVT_FT_FIXUP entry in - * vbe_simple.c - so for now, make it global. - */ #define EVENT_SPY_FULL(_type, _func) \ - __used ll_entry_declare(struct evspy_info, _type ## _3_ ## _func, \ + ll_entry_declare(struct evspy_info, _type ## _3_ ## _func, \ evspy_info) = _ESPY_REC(_type, _func) /* Simple spy with no function arguments */ #define EVENT_SPY_SIMPLE(_type, _func) \ - __used ll_entry_declare(struct evspy_info_simple, \ + ll_entry_declare(struct evspy_info_simple, \ _type ## _3_ ## _func, \ evspy_info) = _ESPY_REC_SIMPLE(_type, _func) -- cgit v1.3.1 From 4f8d6c8f417cbaf32585f2969bdccb0be480c18d Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Tue, 19 May 2026 14:22:08 +0800 Subject: imx: Remove hardcoded watchdog base address macros The watchdog base addresses are now obtained from the devicetree via ofnode_* functions. Remove the hardcoded macro definitions as they are no longer needed. Signed-off-by: Alice Guo Reviewed-by: Peng Fan --- arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 2 -- arch/arm/include/asm/arch-imx9/imx-regs.h | 9 --------- include/configs/imx8ulp_evk.h | 2 -- include/configs/imx91_evk.h | 2 -- include/configs/imx91_frdm.h | 2 -- include/configs/imx93_evk.h | 3 --- include/configs/imx93_frdm.h | 3 --- include/configs/imx93_qsb.h | 2 -- include/configs/imx93_var_som.h | 3 --- include/configs/imx94_evk.h | 3 --- include/configs/imx95_evk.h | 2 -- include/configs/kontron-osm-s-mx93.h | 2 -- include/configs/mx7ulp_com.h | 3 --- include/configs/mx7ulp_evk.h | 3 --- include/configs/phycore_imx91_93.h | 3 --- include/configs/toradex-smarc-imx95.h | 2 -- 16 files changed, 46 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h index a038cc1df33..f9c5e21c14f 100644 --- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h @@ -20,8 +20,6 @@ #define SIM1_BASE_ADDR 0x29290000 -#define WDG3_RBASE 0x292a0000UL - #define SIM_SEC_BASE_ADDR 0x2802B000 #define CGC1_SOSCDIV_ADDR 0x292C0108 diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h index 2d084e5227a..fbf2e6a2b01 100644 --- a/arch/arm/include/asm/arch-imx9/imx-regs.h +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -17,15 +17,6 @@ #define ANATOP_BASE_ADDR 0x44480000UL -#ifdef CONFIG_IMX94 -#define WDG3_BASE_ADDR 0x49220000UL -#define WDG4_BASE_ADDR 0x49230000UL -#else -#define WDG3_BASE_ADDR 0x42490000UL -#define WDG4_BASE_ADDR 0x424a0000UL -#endif -#define WDG5_BASE_ADDR 0x424b0000UL - #define GPIO2_BASE_ADDR 0x43810000UL #define GPIO3_BASE_ADDR 0x43820000UL #define GPIO4_BASE_ADDR 0x43840000UL diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index edfd6f70815..b4f80fb944b 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -30,6 +30,4 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG3_RBASE #endif diff --git a/include/configs/imx91_evk.h b/include/configs/imx91_evk.h index 9c5014fd0a5..13918e2b873 100644 --- a/include/configs/imx91_evk.h +++ b/include/configs/imx91_evk.h @@ -16,6 +16,4 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/imx91_frdm.h b/include/configs/imx91_frdm.h index 6d051ed88a5..480b3fb477a 100644 --- a/include/configs/imx91_frdm.h +++ b/include/configs/imx91_frdm.h @@ -20,6 +20,4 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index ffd72a38bcb..67774f54790 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -26,7 +26,4 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/imx93_frdm.h b/include/configs/imx93_frdm.h index c98c10774cb..bcea360b399 100644 --- a/include/configs/imx93_frdm.h +++ b/include/configs/imx93_frdm.h @@ -20,7 +20,4 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/imx93_qsb.h b/include/configs/imx93_qsb.h index a7b94f7ab57..350f094c2a6 100644 --- a/include/configs/imx93_qsb.h +++ b/include/configs/imx93_qsb.h @@ -16,6 +16,4 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/imx93_var_som.h b/include/configs/imx93_var_som.h index 9dc10aea407..6a425e6d1ea 100644 --- a/include/configs/imx93_var_som.h +++ b/include/configs/imx93_var_som.h @@ -38,7 +38,4 @@ #define CFG_SYS_FSL_USDHC_NUM 2 -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/imx94_evk.h b/include/configs/imx94_evk.h index f93c3c4e4a8..2623c13db06 100644 --- a/include/configs/imx94_evk.h +++ b/include/configs/imx94_evk.h @@ -18,7 +18,4 @@ #define PHYS_SDRAM_SIZE 0x70000000UL /* 2GB - 256MB DDR */ #define PHYS_SDRAM_2_SIZE 0x180000000 /* 8GB */ -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/imx95_evk.h b/include/configs/imx95_evk.h index 3d22740b3f4..1fdc9ce21ef 100644 --- a/include/configs/imx95_evk.h +++ b/include/configs/imx95_evk.h @@ -23,6 +23,4 @@ #define PHYS_SDRAM_2_SIZE 0x380000000 /* 14GB (Totally 16GB) */ #endif -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif diff --git a/include/configs/kontron-osm-s-mx93.h b/include/configs/kontron-osm-s-mx93.h index ab2b42298c8..fed75e6fa12 100644 --- a/include/configs/kontron-osm-s-mx93.h +++ b/include/configs/kontron-osm-s-mx93.h @@ -25,6 +25,4 @@ #define CFG_MXC_USB_FLAGS 0 #endif -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif /* __KONTRON_MX93_CONFIG_H */ diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index d27e9d2eaa1..501c3059cc3 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -15,9 +15,6 @@ #include "imx7ulp_spl.h" #endif -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG1_RBASE - #define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */ /* UART */ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index ace1eee70cf..21dbec837f0 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -11,9 +11,6 @@ #include #include -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG1_RBASE - #define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ /* UART */ diff --git a/include/configs/phycore_imx91_93.h b/include/configs/phycore_imx91_93.h index 02fa1d9b274..d1bf086546f 100644 --- a/include/configs/phycore_imx91_93.h +++ b/include/configs/phycore_imx91_93.h @@ -22,7 +22,4 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif /* __PHYCORE_IMX91_93_H */ diff --git a/include/configs/toradex-smarc-imx95.h b/include/configs/toradex-smarc-imx95.h index e1aebd70af2..8a880b96503 100644 --- a/include/configs/toradex-smarc-imx95.h +++ b/include/configs/toradex-smarc-imx95.h @@ -19,6 +19,4 @@ #define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M) #define PHYS_SDRAM_2_SIZE SZ_6G -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - #endif -- cgit v1.3.1 From 0b9897e7a41cb6d035956b5c7ca004be84feaa17 Mon Sep 17 00:00:00 2001 From: Nora Schiffer Date: Tue, 19 May 2026 14:24:06 +0200 Subject: board: tq: add TQMa6UL[L]x[L] SOM and MBa6ULx baseboard The TQMa6UL[L]x is a family of SoMs based on the i.MX6UL[L] SoCs. They are available either with board connectors or as LGA packages with solder balls. Add Support for the SoM and its combination with our MBa6ULx carrier board. For use with the MBa6ULx carrier board, the LGA variant is soldered onto an adapter board. Signed-off-by: Nora Schiffer Signed-off-by: Max Merchel --- arch/arm/mach-imx/mx6/Kconfig | 21 ++++ board/tq/MAINTAINERS | 2 +- board/tq/tqma6ul/Kconfig | 114 ++++++++++++++++++++ board/tq/tqma6ul/Makefile | 16 +++ board/tq/tqma6ul/spl.c | 128 +++++++++++++++++++++++ board/tq/tqma6ul/spl_mba6ul.c | 177 +++++++++++++++++++++++++++++++ board/tq/tqma6ul/spl_tqma6ul_ram.c | 209 +++++++++++++++++++++++++++++++++++++ board/tq/tqma6ul/tqma6ul.c | 184 ++++++++++++++++++++++++++++++++ board/tq/tqma6ul/tqma6ul.cfg | 23 ++++ board/tq/tqma6ul/tqma6ul.env | 47 +++++++++ board/tq/tqma6ul/tqma6ul.h | 25 +++++ board/tq/tqma6ul/tqma6ul_mba6ul.c | 138 ++++++++++++++++++++++++ doc/board/tq/index.rst | 1 + doc/board/tq/tqma6ul.rst | 105 +++++++++++++++++++ include/configs/tqma6ul.h | 53 ++++++++++ include/configs/tqma6ul_mba6ul.h | 19 ++++ 16 files changed, 1261 insertions(+), 1 deletion(-) create mode 100644 board/tq/tqma6ul/Kconfig create mode 100644 board/tq/tqma6ul/Makefile create mode 100644 board/tq/tqma6ul/spl.c create mode 100644 board/tq/tqma6ul/spl_mba6ul.c create mode 100644 board/tq/tqma6ul/spl_tqma6ul_ram.c create mode 100644 board/tq/tqma6ul/tqma6ul.c create mode 100644 board/tq/tqma6ul/tqma6ul.cfg create mode 100644 board/tq/tqma6ul/tqma6ul.env create mode 100644 board/tq/tqma6ul/tqma6ul.h create mode 100644 board/tq/tqma6ul/tqma6ul_mba6ul.c create mode 100644 doc/board/tq/tqma6ul.rst create mode 100644 include/configs/tqma6ul.h create mode 100644 include/configs/tqma6ul_mba6ul.h (limited to 'include') diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index d198d9932f4..7ed4b24b751 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -633,6 +633,26 @@ config TARGET_TQMA6 imply CMD_SF imply CMD_DM +config TARGET_TQMA6UL + bool "TQ-Systems TQMa6UL[L]x" + depends on MX6UL || MX6ULL + select TQ_COMMON_SOM + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select OF_SYSTEM_SETUP + select DM + select DM_I2C + select SUPPORT_SPL + select SPL_SEPARATE_BSS if SPL + imply DM_GPIO + imply DM_MMC + imply DM_SPI if SPI + imply DM_SPI_FLASH if SPI + imply SPI + help + TQMa6UL[L]x is a TQ SoM with i.MX6UL/i.MX6ULL CPU + The SoM can be used on various baseboards. + config TARGET_UDOO bool "udoo" depends on MX6QDL @@ -739,6 +759,7 @@ source "board/technexion/pico-imx6/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tq/tqma6/Kconfig" +source "board/tq/tqma6ul/Kconfig" source "board/toradex/apalis_imx6/Kconfig" source "board/toradex/colibri_imx6/Kconfig" source "board/toradex/colibri-imx6ull/Kconfig" diff --git a/board/tq/MAINTAINERS b/board/tq/MAINTAINERS index b31c5793432..a04a36ba415 100644 --- a/board/tq/MAINTAINERS +++ b/board/tq/MAINTAINERS @@ -1,4 +1,4 @@ -TQMA6 +TQMA6 / TQMA6UL / TQMA6ULxL / TQMA6ULL / TQMA6ULLxL M: Max Merchel L: u-boot@ew.tq-group.com S: Maintained diff --git a/board/tq/tqma6ul/Kconfig b/board/tq/tqma6ul/Kconfig new file mode 100644 index 00000000000..5d85c68b359 --- /dev/null +++ b/board/tq/tqma6ul/Kconfig @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2016-2026 TQ-Systems GmbH , +# D-82229 Seefeld, Germany. +# Author: Marco Felsch, Markus Niebel, Max Merchel +# + +if TARGET_TQMA6UL + +config SYS_BOARD + default "tqma6ul" + +config SYS_VENDOR + default "tq" + +config SYS_CONFIG_NAME + default "tqma6ul_mba6ul" if MBA6UL + +choice + prompt "TQMa6UL module variant" + default TQMA6UL_VARIANT_STANDARD + help + Select the variant of the TQMa6UL SoM module being used. + By default, the variant with board-to-board connectors is used. + +config TQMA6UL_VARIANT_STANDARD + bool "standard module with board connector" + help + Select for SoM variant connector + with board to board connectors + +config TQMA6UL_VARIANT_LGA + bool "LGA module with solder balls" + help + Select for SoM variant LGA + with solder balls + +endchoice + +config TQMA6UL_RAM_256M + bool + +config TQMA6UL_RAM_512M + bool + +choice + prompt "TQMa6UL RAM configuration" + default TQMA6UL_RAM_MULTI + help + Select RAM configuration. Normally use default here but for + specific setup it is possible to use a single RAM size. + +config TQMA6UL_RAM_MULTI + bool "TQMa6ULx with 256/512 MB RAM - Single image" + select TQMA6UL_RAM_256M + select TQMA6UL_RAM_512M + help + Build a single U-Boot solely for variants + with 256/512 MB RAM. + +config TQMA6UL_RAM_SINGLE_256M + bool "TQMa6UL with 256 MB RAM" + select TQMA6UL_RAM_256M + help + Build U-Boot solely for variants + with 256 MB RAM. + +config TQMA6UL_RAM_SINGLE_512M + bool "TQMa6UL with 512 MB RAM" + select TQMA6UL_RAM_512M + help + Build U-Boot solely for variants + with 512 MB RAM. + +endchoice + +choice + prompt "TQMa6UL base board variant" + default MBA6UL + help + Select the baseboard variant for the TQMa6UL module. + By default the MBA6UL starterkit is used. + +config MBA6UL + bool "TQMa6UL on MBa6ULx Starterkit" + select TQ_COMMON_BB + select TQ_COMMON_SDMMC + select SYSINFO + select SYSINFO_TQ_EEPROM + select I2C_EEPROM + select MISC + select MXC_UART + imply DM_ETH + imply DM_GPIO + imply DM_MMC + imply DM_SERIAL + imply DM_SPI + imply OF_UPSTREAM + imply PHYLIB + imply PHY_SMSC + imply USB + imply USB_STORAGE + help + Select the MBa6ULx starterkit. + This is the default base board. + +endchoice + +config IMX_CONFIG + default "board/tq/tqma6ul/tqma6ul.cfg" + +source "board/tq/common/Kconfig" + +endif diff --git a/board/tq/tqma6ul/Makefile b/board/tq/tqma6ul/Makefile new file mode 100644 index 00000000000..f45ed4a15f6 --- /dev/null +++ b/board/tq/tqma6ul/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2021-2026 TQ-Systems GmbH , +# D-82229 Seefeld, Germany. +# Author: Markus Niebel, Matthias Schiffer, Max Merchel +# + +obj-y := tqma6ul.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += spl_tqma6ul_ram.o +obj-$(CONFIG_MBA6UL) += spl_mba6ul.o +else +obj-$(CONFIG_MBA6UL) += tqma6ul_mba6ul.o +endif diff --git a/board/tq/tqma6ul/spl.c b/board/tq/tqma6ul/spl.c new file mode 100644 index 00000000000..71c5134c4f6 --- /dev/null +++ b/board/tq/tqma6ul/spl.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tq_bb.h" +#include "../common/tq_som.h" + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); +} + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +/* eMMC on USDHC2 */ +static const iomux_v3_cfg_t tqma6ul_usdhc2_pads[] = { + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg tqma6ul_usdhc2_cfg = { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 8, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + /* eMMC/uSDHC2 is always present */ + ret = 1; + else + ret = tq_bb_board_mmc_getcd(mmc); + + return ret; +} + +int board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + /* eMMC/uSDHC2 is never WP */ + ret = 0; + else + ret = tq_bb_board_mmc_getwp(mmc); + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(tqma6ul_usdhc2_pads, + ARRAY_SIZE(tqma6ul_usdhc2_pads)); + tqma6ul_usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + if (fsl_esdhc_initialize(bis, &tqma6ul_usdhc2_cfg)) + printf("Warning: failed to initialize eMMC dev\n"); + + tq_bb_board_mmc_init(bis); + + return 0; +} + +void board_init_f(ulong dummy) +{ + /* setup clock gating */ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* setup AXI */ + gpr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + tq_som_ram_init(); +} diff --git a/board/tq/tqma6ul/spl_mba6ul.c b/board/tq/tqma6ul/spl_mba6ul.c new file mode 100644 index 00000000000..55beeac8fc9 --- /dev/null +++ b/board/tq/tqma6ul/spl_mba6ul.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tq_bb.h" +#include "tqma6ul.h" + +#define GPIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static const iomux_v3_cfg_t mba6ul_uart_pads[] = { + NEW_PAD_CTRL(MX6_PAD_UART1_TX_DATA__UART1_DCE_TX, UART_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_UART1_RX_DATA__UART1_DCE_RX, UART_PAD_CTRL), +}; + +static void mba6ul_setup_iomuxc_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(mba6ul_uart_pads, + ARRAY_SIZE(mba6ul_uart_pads)); +} + +/* SD card on USDHC1 */ +static const iomux_v3_cfg_t mba6ul_usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* WP */ + MX6_PAD_UART1_CTS_B__GPIO1_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) +#define USDHC1_WP_GPIO IMX_GPIO_NR(1, 18) + +static struct fsl_esdhc_cfg mba6ul_usdhc1_cfg = { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, +}; + +int tq_bb_board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC1_BASE_ADDR) + ret = !gpio_get_value(USDHC1_CD_GPIO); + + return ret; +} + +int tq_bb_board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC1_BASE_ADDR) + ret = gpio_get_value(USDHC1_WP_GPIO); + + return ret; +} + +int tq_bb_board_mmc_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(mba6ul_usdhc1_pads, + ARRAY_SIZE(mba6ul_usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1-cd"); + gpio_request(USDHC1_WP_GPIO, "usdhc1-wp"); + gpio_direction_input(USDHC1_CD_GPIO); + gpio_direction_input(USDHC1_WP_GPIO); + + mba6ul_usdhc1_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + if (fsl_esdhc_initialize(bis, &mba6ul_usdhc1_cfg)) + puts("Warning: failed to initialize SD card\n"); + + return 0; +} + +int board_early_init_f(void) +{ + tq_bb_board_early_init_f(); + + mba6ul_setup_iomuxc_uart(); + + return 0; +} + +/* + * This is done per baseboard to allow different implementations + */ +void board_boot_order(u32 *spl_boot_list) +{ + u32 bmode = imx6_src_get_boot_mode(); + u8 imx6_bmode = (bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT; + + /* USB boot */ + if (spl_boot_device() == BOOT_DEVICE_BOARD) { + printf("USB\n"); + spl_boot_list[0] = BOOT_DEVICE_BOARD; + return; + } + + switch (imx6_bmode) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + /* SD/eSD - BOOT_DEVICE_MMC2 */ + printf("SD\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC2; + break; + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + /* MMC/eMMC - BOOT_DEVICE_MMC1 */ + printf("eMMC\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + case IMX6_BMODE_QSPI: + /* QSPI - BOOT_DEVICE_SPI */ + printf("QSPI\n"); + spl_boot_list[0] = BOOT_DEVICE_NOR; + break; + case IMX6_BMODE_SERIAL_ROM: + /* SERIAL_ROM - BOOT_DEVICE_BOARD */ + printf("Serial ROM\n"); + spl_boot_list[0] = BOOT_DEVICE_BOARD; + break; + default: + printf("WARNING: unknown boot device, fallback to eMMC\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + } +} + +int board_fit_config_name_match(const char *name) +{ + /* Longest FDT name */ + char dt[] = "imx6ull-tqma6ull2l-mba6ulx"; + enum tqma6ul_som_type somtype; + + somtype = set_tqma6ul_dt_name(dt, sizeof(dt), "mba6ulx"); + if (somtype == tqma6ul_som_type_unknown) + return -EINVAL; + + if (!strcmp(name, dt)) + return -EINVAL; + + printf("Device tree: %s\n", name); + return 0; +} diff --git a/board/tq/tqma6ul/spl_tqma6ul_ram.c b/board/tq/tqma6ul/spl_tqma6ul_ram.c new file mode 100644 index 00000000000..c5d50890702 --- /dev/null +++ b/board/tq/tqma6ul/spl_tqma6ul_ram.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tq_som.h" + +static void tqma6ul_init_ddr_controller(u32 size) +{ + /* TQMa6ul DDR config */ + + /* reset DDR via Chip Select 0*/ + tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x03180000); + tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x83180000); + + debug("SPL: tqma6ul ddr iomux ....\n"); + + /* DDR IO TYPE: */ + tq_som_init_write_reg(MX6_IOM_GRP_DDR_TYPE, 0x000C0000); + tq_som_init_write_reg(MX6_IOM_GRP_DDRPKE, 0x00000000); + /* CLOCK: */ + tq_som_init_write_reg(MX6_IOM_DRAM_SDCLK_0, 0x00000030); + /* Control: */ + tq_som_init_write_reg(MX6_IOM_DRAM_CAS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_RAS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_GRP_ADDDS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_RESET, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_SDBA2, 0x00000000); + tq_som_init_write_reg(MX6_IOM_DRAM_SDODT0, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_SDODT1, 0x00000030); + tq_som_init_write_reg(MX6_IOM_GRP_CTLDS, 0x00000030); + /* Data Strobes: */ + tq_som_init_write_reg(MX6_IOM_DDRMODE_CTL, 0x00020000); + tq_som_init_write_reg(MX6_IOM_DRAM_SDQS0, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_SDQS1, 0x00000030); + /* Data: */ + tq_som_init_write_reg(MX6_IOM_GRP_DDRMODE, 0x00020000); + tq_som_init_write_reg(MX6_IOM_GRP_B0DS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_GRP_B1DS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_DQM0, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_DQM1, 0x00000030); + + debug("tqma6ul ddr controller registers ....\n"); + + /* MMDC_MDSCR - MMDC Core Special Command Register */ + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008000); + + debug("tqma6ul ddr calibrations ....\n"); + + /* DDR_PHY_P0_MPZQHWCTRL , enable both one-time & periodic HW ZQ calibration. */ + tq_som_init_write_reg(MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003); + + switch (size) { + case SZ_512M: + if (IS_ENABLED(CONFIG_MX6UL)) { + debug("tqma6ul ddr calibration standard variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00000000); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41580150); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40404E52); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E4A); + + } else if (IS_ENABLED(CONFIG_MX6ULL)) { + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) { + debug("tqma6ull ddr calibration standard variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00090009); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x4140013C); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40403A3E); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40402E26); + + } else if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) { + debug("tqma6ull ddr calibration lga variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00050009); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41340130); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40403A3E); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40402E28); + + } else { + pr_err("invalid/unsupported SoM variant ....\n"); + hang(); + } /* IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD) */ + } else { + pr_err("ERROR: invalid/unsupported CPU variant ....\n"); + hang(); + } /* IS_ENABLED(CONFIG_MX6UL) */ + break; + case SZ_256M: + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) { + debug("tqma6ul ddr calibration standard variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00000000); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41480144); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40404E54); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E48); + + } else if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) { + debug("tqma6ul ddr calibration lga variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00130003); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41540154); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40405050); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E4C); + + } else { + pr_err("ERROR: invalid/unsupported SoM variant ....\n"); + hang(); + } /* IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD) */ + break; + default: + pr_err("ERROR: invalid/unsupported RAM size ....\n"); + hang(); + break; + } + + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333); + + tq_som_init_write_reg(0x021B082C, 0xf3333333); /* MMDC_MPWRDQBY0DL */ + tq_som_init_write_reg(0x021B0830, 0xf3333333); /* MMDC_MPWRDQBY1DL */ + tq_som_init_write_reg(0x021B08C0, 0x00921012); /* MMDC_MPDCCR */ + + /* + * Complete calibration by forced measurement: + */ + tq_som_init_write_reg(MX6_MMDC_P0_MPMUR0, 0x00000800); + tq_som_init_write_reg(MX6_MMDC_P0_MDPDC, 0x0002002D); + + debug("tqma6ul ddr mmdc ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MDOTC, 0x00333030); + tq_som_init_write_reg(MX6_MMDC_P0_MDCFG0, 0x676B52F3); + tq_som_init_write_reg(MX6_MMDC_P0_MDCFG1, 0xB66D8B63); + tq_som_init_write_reg(MX6_MMDC_P0_MDCFG2, 0x01FF00DB); + tq_som_init_write_reg(MX6_MMDC_P0_MDMISC, 0x00201740); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008000); + tq_som_init_write_reg(MX6_MMDC_P0_MDRWD, 0x000026D2); + tq_som_init_write_reg(MX6_MMDC_P0_MDOR, 0x006B1023); + + switch (size) { + case SZ_512M: + tq_som_init_write_reg(MX6_MMDC_P0_MDASP, 0x0000004F); + tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x84180000); + break; + case SZ_256M: + tq_som_init_write_reg(MX6_MMDC_P0_MDASP, 0x00000047); + tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x83180000); + break; + default: + hang(); + break; + } + + debug("tqma6ul ddr cs0 ....\n"); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x02008032); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008033); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00048031); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x15208030); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x04008040); + tq_som_init_write_reg(MX6_MMDC_P0_MDREF, 0x00000800); + tq_som_init_write_reg(MX6_MMDC_P0_MPODTCTRL, 0x00000227); + tq_som_init_write_reg(MX6_MMDC_P0_MDPDC, 0x0002552D); + tq_som_init_write_reg(MX6_MMDC_P0_MAPSR, 0x00011006); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00000000); +} + +void tq_som_ram_init(void) +{ + int i; + /* RAM sizes need to be in descending order */ + static const u32 ram_sizes[] = { +#if IS_ENABLED(CONFIG_TQMA6UL_RAM_512M) + SZ_512M, +#endif +#if IS_ENABLED(CONFIG_TQMA6UL_RAM_256M) + SZ_256M, +#endif + }; + + if (!is_mx6ul() && !is_mx6ull()) { + pr_err("ERROR: Not running on TQMa6UL[L]\n"); + hang(); + } + + for (i = 0; i < ARRAY_SIZE(ram_sizes); i++) { + tqma6ul_init_ddr_controller(ram_sizes[i]); + if (tq_som_ram_check_size(ram_sizes[i])) + break; + } + + if (i < ARRAY_SIZE(ram_sizes)) { + debug("SPL: tqma6ul ddr init done ...\n"); + } else { + pr_err("ERROR: Invalid DDR RAM size\n"); + hang(); + } +} diff --git a/board/tq/tqma6ul/tqma6ul.c b/board/tq/tqma6ul/tqma6ul.c new file mode 100644 index 00000000000..999396f573d --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Marco Felsch, Nora Schiffer + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tq_bb.h" +#include "tqma6ul.h" + +int tq_bb_board_early_init_f(void) +{ + if (CONFIG_IS_ENABLED(FSL_QSPI)) + enable_qspi_clk(0); + + return 0; +} + +/** + * Checks if CPU (imx6ul or ima6ull) matches the one set for the image. + */ +static const char *check_cpu_variant(void) +{ + const char *cpu; + + if (is_mx6ul()) { + cpu = "ul"; + if (!IS_ENABLED(CONFIG_MX6UL)) + printf("*** ERROR: image not compiled for i.MX6UL!\n"); + } else if (is_mx6ull()) { + cpu = "ull"; + if (!IS_ENABLED(CONFIG_MX6ULL)) + printf("*** ERROR: image not compiled for i.MX6ULL!\n"); + } else { + printf("unknown CPU\n"); + return NULL; + } + + return cpu; +} + +/** + * Checks configuration for TQMa6UL SoM module variant. + */ +enum tqma6ul_som_type check_tqma6ul_variant(void) +{ + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) + return tqma6ul_som_type_ca; + + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) + return tqma6ul_som_type_lga; + + printf("unknown SoM variant\n"); + + return tqma6ul_som_type_unknown; +} + +/** + * Adjusts device tree name based on CPU variant. + */ +enum tqma6ul_som_type set_tqma6ul_dt_name(char *dt, size_t dtsize, const char *mb) +{ + const char *tqma6ul_cpu, *tqma6ul_variant; + enum tqma6ul_som_type somtype; + u8 mx6ul_variant; + + tqma6ul_cpu = check_cpu_variant(); + if (!tqma6ul_cpu) + return tqma6ul_som_type_unknown; + + /* MX6UL1 vs MX6UL2 */ + mx6ul_variant = check_module_fused(MODULE_ENET2) ? 1 : 2; + + somtype = check_tqma6ul_variant(); + switch (somtype) { + case tqma6ul_som_type_ca: + tqma6ul_variant = ""; + break; + case tqma6ul_som_type_lga: + tqma6ul_variant = "l"; + break; + default: + return tqma6ul_som_type_unknown; + } + + snprintf(dt, dtsize, "imx6%s-tqma6%s%u%s-%s", + tqma6ul_cpu, tqma6ul_cpu, mx6ul_variant, tqma6ul_variant, mb); + + return somtype; +} + +#if !IS_ENABLED(CONFIG_SPL_BUILD) +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +const char *tq_som_get_modulename(void) +{ + if (is_mx6ul()) { + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) + return "TQMa6ULx"; + + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) + return "TQMa6ULxL"; + } + + if (is_mx6ull()) { + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) + return "TQMa6ULLx"; + + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) + return "TQMa6ULLxL"; + } + + return "Unknown"; +} + +int checkboard(void) +{ + printf("Board: %s on %s\n", tq_som_get_modulename(), + tq_bb_get_boardname()); + + return tq_bb_checkboard(); +} + +#if IS_ENABLED(CONFIG_CMD_BMODE) +static const struct boot_mode tqma6ul_board_boot_modes[] = { + /* 4 bit bus width */ + {"sd", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"qspi", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int tq_bb_board_late_init(void) +{ + if (IS_ENABLED(CONFIG_CMD_BMODE)) + add_board_boot_modes(tqma6ul_board_boot_modes); + + env_set_runtime("board_name", tq_som_get_modulename()); + + return 0; +} + +int tq_bb_checkboard(void) +{ + if (is_mx6ul()) { + if (!IS_ENABLED(CONFIG_MX6UL)) + printf("*** ERROR: image not compiled for i.MX6UL!\n"); + } else if (is_mx6ull()) { + if (!IS_ENABLED(CONFIG_MX6ULL)) + printf("*** ERROR: image not compiled for i.MX6ULL!\n"); + } else { + printf("*** ERROR: unknown CPU variant!\n"); + } + + return 0; +} + +/* + * Device Tree Support + */ +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) +int tq_bb_ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */ + +#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */ diff --git a/board/tq/tqma6ul/tqma6ul.cfg b/board/tq/tqma6ul/tqma6ul.cfg new file mode 100644 index 00000000000..42821ae5c7a --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul.cfg @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +#if IS_ENABLED(CONFIG_QSPI_BOOT) +BOOT_FROM qspi +#else +BOOT_FROM sd +#endif + +#if IS_ENABLED(CONFIG_IMX_HAB) +CSF CONFIG_CSF_SIZE +#endif diff --git a/board/tq/tqma6ul/tqma6ul.env b/board/tq/tqma6ul/tqma6ul.env new file mode 100644 index 00000000000..fa172caca23 --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul.env @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * TQMa6UL environment + */ + +#include + +board=tqma6ul +boot_os=bootz "${kernel_addr_r}" - "${fdt_addr_r}" +emmc_bootp_start=TQMA6UL_MMC_UBOOT_SECTOR_START +emmc_dev=0 +fdt_addr_r=TQMA6UL_FDT_ADDRESS +fdtoverlay_addr_r=TQMA6UL_FDT_OVERLAY_ADDR +image=zImage +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +mmcautodetect=yes +mmcblkdev=0 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +netdev=eth1 +pxefile_addr_r=CONFIG_SYS_LOAD_ADDR +ramdisk_addr_r=TQMA6UL_INITRD_ADDRESS +sd_dev=1 +uboot=u-boot-with-spl.imx +uboot_mmc_start=TQMA6UL_MMC_UBOOT_SECTOR_START +uboot_mmc_size=TQMA6UL_MMC_UBOOT_SECTOR_COUNT +uboot_spi_sector_size=TQMA6UL_SPI_FLASH_SECTOR_SIZE +uboot_spi_start=TQMA6UL_SPI_UBOOT_START +uboot_spi_size=TQMA6UL_SPI_UBOOT_SIZE + +#ifdef CONFIG_USB_FUNCTION_FASTBOOT + +/* 0=user 1=boot1 2=boot2 */ +fastboot_mmc_boot_partition = 1 + +fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV :0 + +fastboot_raw_partition_bootloader= + TQMA6UL_MMC_UBOOT_SECTOR_START TQMA6UL_MMC_UBOOT_SECTOR_COUNT mmcpart + "${fastboot_mmc_boot_partition}" + +fastbootcmd=fastboot usb 0 + +#endif /* CONFIG_USB_FUNCTION_FASTBOOT */ diff --git a/board/tq/tqma6ul/tqma6ul.h b/board/tq/tqma6ul/tqma6ul.h new file mode 100644 index 00000000000..595edc89e19 --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +enum tqma6ul_som_type { + /* unknown */ + tqma6ul_som_type_unknown, + /* connector module */ + tqma6ul_som_type_ca, + /* LGA Variant */ + tqma6ul_som_type_lga, +}; + +/** + * Checks configuration for TQMa6UL SoM module variant + */ +enum tqma6ul_som_type check_tqma6ul_variant(void); + +/** + * Adjusts device tree name based on CPU variant. + */ +enum tqma6ul_som_type set_tqma6ul_dt_name(char *dt, size_t dtsize, const char *mb); diff --git a/board/tq/tqma6ul/tqma6ul_mba6ul.c b/board/tq/tqma6ul/tqma6ul_mba6ul.c new file mode 100644 index 00000000000..be78060cbda --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul_mba6ul.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Marco Felsch, Nora Schiffer + */ + +#include +#include +#include +#include +#include +#include + +#include "../common/tq_bb.h" +#include "tqma6ul.h" + +const char *tq_bb_get_boardname(void) +{ + return "MBa6ULx"; +} + +int board_early_init_f(void) +{ + return tq_bb_board_early_init_f(); +} + +static void mba6ul_setup_eth(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + if (check_module_fused(MODULE_ENET1)) { + printf("FEC1: disabled by fuses\n"); + } else { + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17] + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + enable_fec_anatop_clock(0, ENET_50MHZ); + } + + if (check_module_fused(MODULE_ENET2)) { + printf("FEC2: disabled by fuses\n"); + } else { + /* + * Use 50M anatop loopback REF_CLK1 for ENET2, + * clear gpr1[14], set gpr1[18] + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + + enable_fec_anatop_clock(1, ENET_50MHZ); + } + + enable_enet_clk(1); +} + +int board_init(void) +{ + return 0; +} + +static void mba6ul_set_fdt_file(void) +{ + /* Longest FDT name */ + char dt[] = "imx6ull-tqma6ull2l-mba6ulx.dtb"; + enum tqma6ul_som_type somtype; + + if (!env_get("fdtfile")) { + somtype = set_tqma6ul_dt_name(dt, sizeof(dt), "mba6ulx.dtb"); + if (somtype == tqma6ul_som_type_unknown) + return; + + env_set_runtime("fdtfile", dt); + } +} + +int board_late_init(void) +{ + unsigned int bmode = + (imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT; + + tq_bb_board_late_init(); + + printf("Boot: "); + + switch (bmode) { + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + printf("eMMC\n"); + env_set_runtime("boot_dev", "mmc"); + board_late_mmc_env_init(); + break; + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + printf("SD\n"); + env_set_runtime("boot_dev", "mmc"); + board_late_mmc_env_init(); + break; + case IMX6_BMODE_QSPI: + case IMX6_BMODE_NOR: + printf("QSPI\n"); + env_set_runtime("boot_dev", "qspi"); + break; + default: + printf("unhandled boot device %u\n", bmode); + } + + mba6ul_set_fdt_file(); + mba6ul_setup_eth(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + unsigned int port = (imx6_src_get_boot_mode() >> 11) & 0x3; + + switch (port) { + case 0: + /* SDHC1 - SD card on MBa6ULx */ + return 1; + + default: + /* Return eMMC device otherwise */ + return 0; + } +} + +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return tq_bb_ft_board_setup(blob, bd); +} +#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */ diff --git a/doc/board/tq/index.rst b/doc/board/tq/index.rst index d6dc6101c2c..775957474e7 100644 --- a/doc/board/tq/index.rst +++ b/doc/board/tq/index.rst @@ -9,4 +9,5 @@ TQ-Systems .. toctree:: :maxdepth: 2 + tqma6ul tqma7 diff --git a/doc/board/tq/tqma6ul.rst b/doc/board/tq/tqma6ul.rst new file mode 100644 index 00000000000..2b346715642 --- /dev/null +++ b/doc/board/tq/tqma6ul.rst @@ -0,0 +1,105 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later or CC-BY-4.0 + +.. Copyright (c) 2017-2025 TQ-Systems GmbH , +.. D-82229 Seefeld, Germany. + +######################################## +U-Boot for the TQ-Systems TQMa6x modules +######################################## + +The following hardware revisions are supported: + +Modules: + ++------------+----------+ +| TQMa6ULx | REV.030x | ++------------+----------+ +| TQMa6ULLx | REV.030x | ++------------+----------+ +| TQMa6ULxL | REV.030x | ++------------+----------+ +| TQMa6ULLxL | REV.030x | ++------------+----------+ + +Mainboards: + ++----------+----------+ +| MBa6ULx | REV.020x | ++----------+----------+ + +Hardware on modules TQMa6ULx, TQMa6ULxL, TQMa6ULLx and TQMa6ULLxL + +- eMMC +- RTC +- PMIC +- SPI-NOR (optional) +- EEPROM +- Temperature sensor +- RAM (256 MiB / 512 MiB) + +Supported hardware on Starterkit MBa6ULx: + +- 2 Ethernet PHY connected to FEC0 / FEC1 (usage depends on CPU) +- SD-card slot +- UART +- USB + +Note: To change the Ethernet port to use for networking functionality, use the +U-Boot generic environment variable ``ethact``. + +.. code-block:: bash + + setenv ethact + +*********** +Boot source +*********** + +- SD/eMMC +- USB/SDP (with NXP UUU tool) +- SPI NOR (functional but requires additional prepended NXP header. + Not supported in U-Boot.) + +******** +Building +******** + +To build U-Boot for the TQ-Systems TQMa6L modules: + +.. code-block:: bash + + make ___defconfig + make + + +**som** is a placeholder for the module base variant: + ++------------+------------+----------------+ +| tqma6ulx | TQMa6ULx | i.MX6UL | ++------------+------------+----------------+ +| tqma6ullx | TQMa6ULLx | i.MX6ULL | ++------------+------------+----------------+ +| tqma6ulxl | TQMa6ULxL | i.MX6UL (lga) | ++------------+------------+----------------+ +| tqma6ullxl | TQMa6ULLxL | i.MX6ULL (lga) | ++------------+------------+----------------+ + +**baseboard** is a placeholder for the mainboard to compile for: + ++----------+----------+ +| mba6ul | MBa6ULx | ++----------+----------+ + +**boot** is a placeholder for the boot device: + ++------+---------+ +| mmc | SD/eMMC | ++------+---------+ +| spi | SPI-NOR | ++------+---------+ + +************ +Support Wiki +************ + +See `TQ Embedded Wiki for TQMa6ulx `_. diff --git a/include/configs/tqma6ul.h b/include/configs/tqma6ul.h new file mode 100644 index 00000000000..89bd8102500 --- /dev/null +++ b/include/configs/tqma6ul.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Marco Felsch, Nora Schiffer, Max Merchel + * + * Configuration settings for the TQ-Systems TQMa6UL[L]x[L] SOM family. + */ + +#ifndef __TQMA6UL_CONFIG_H +#define __TQMA6UL_CONFIG_H + +#include + +#include "mx6_common.h" + +#define TQMA6UL_MMC_UBOOT_SECTOR_START 0x2 +#define TQMA6UL_MMC_UBOOT_SECTOR_COUNT 0x7fe + +#define TQMA6UL_SPI_FLASH_SECTOR_SIZE SZ_64K +#define TQMA6UL_SPI_UBOOT_START SZ_4K +#define TQMA6UL_SPI_UBOOT_SIZE 0xf0000 + +/* 128 MiB offset as suggested in ARM related Linux docs */ +#define TQMA6UL_FDT_ADDRESS 0x88000000 + +/* 256KiB above TQMA6UL_FDT_ADDRESS (TQMA6UL_FDT_ADDRESS + SZ_256K) */ +#define TQMA6UL_FDT_OVERLAY_ADDR 0x88040000 + +/* 16MiB above TQMA6UL_FDT_ADDRESS (TQMA6UL_FDT_ADDRESS + SZ_16M) */ +#define TQMA6UL_INITRD_ADDRESS 0x89000000 + +#ifndef __ASSEMBLY__ +static_assert(TQMA6UL_FDT_OVERLAY_ADDR == (TQMA6UL_FDT_ADDRESS + SZ_256K)); +static_assert(TQMA6UL_INITRD_ADDRESS == (TQMA6UL_FDT_ADDRESS + SZ_16M)); +#endif + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE + +/* u-boot.img base address for SPI-NOR boot */ +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + SZ_4K + CONFIG_SPL_PAD_TO) + +#define CFG_SYS_INIT_SP_OFFSET \ + (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_ADDR \ + (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET) + +#endif /* __TQMA6UL_CONFIG_H */ diff --git a/include/configs/tqma6ul_mba6ul.h b/include/configs/tqma6ul_mba6ul.h new file mode 100644 index 00000000000..b7a31b5ce26 --- /dev/null +++ b/include/configs/tqma6ul_mba6ul.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel, Nora Schiffer, Max Merchel + * + * Configuration settings for the TQ-Systems MBa6ULx carrier board for + * TQMa6UL[L]x[L] SOM family. + */ + +#ifndef __CONFIG_TQMA6UL_MBA6UL_H +#define __CONFIG_TQMA6UL_MBA6UL_H + +#include "tqma6ul.h" + +#define CFG_MXC_UART_BASE UART1_BASE +#define CFG_SYS_FSL_ESDHC_ADDR 0 + +#endif /* __CONFIG_TQMA6UL_MBA6UL_H */ -- cgit v1.3.1 From 0ef21dd37dc1779293a101413a7ce32bd63870bb Mon Sep 17 00:00:00 2001 From: Nora Schiffer Date: Tue, 2 Jun 2026 13:57:50 +0200 Subject: sysinfo: add sysinfo_get_and_detect() helper sysinfo_detect() is commonly called after sysinfo_get(). Make the API a bit more convenient to use by introducing a helper. Signed-off-by: Nora Schiffer Signed-off-by: Alexander Feilke Reviewed-by: Simon Glass --- drivers/sysinfo/sysinfo-uclass.c | 10 ++++++++++ include/sysinfo.h | 17 +++++++++++++++++ test/dm/sysinfo.c | 16 ++++++++++++++++ 3 files changed, 43 insertions(+) (limited to 'include') diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c index bf0f664e8dc..d18a168614e 100644 --- a/drivers/sysinfo/sysinfo-uclass.c +++ b/drivers/sysinfo/sysinfo-uclass.c @@ -42,6 +42,16 @@ int sysinfo_detect(struct udevice *dev) return ret; } +int sysinfo_get_and_detect(struct udevice **devp) +{ + int ret = sysinfo_get(devp); + + if (!ret) + ret = sysinfo_detect(*devp); + + return ret; +} + int sysinfo_get_fit_loadable(struct udevice *dev, int index, const char *type, const char **strp) { diff --git a/include/sysinfo.h b/include/sysinfo.h index 54eb64a204a..7ca396b2ee4 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -373,6 +373,18 @@ int sysinfo_get_data_by_index(struct udevice *dev, int id, int index, */ int sysinfo_get(struct udevice **devp); +/** + * sysinfo_get_and_detect() - Get the sysinfo device and detect it. + * + * @devp: Pointer to structure to receive the sysinfo device. + * + * This is a convenience wrapper around sysinfo_get() followed by + * sysinfo_detect() + * + * Return: 0 if OK, -ve on error. + */ +int sysinfo_get_and_detect(struct udevice **devp); + /** * sysinfo_get_fit_loadable - Get the name of an image to load from FIT * This function can be used to provide the image names based on runtime @@ -438,6 +450,11 @@ static inline int sysinfo_get(struct udevice **devp) return -ENOSYS; } +static inline int sysinfo_get_and_detect(struct udevice **devp) +{ + return -ENOSYS; +} + static inline int sysinfo_get_fit_loadable(struct udevice *dev, int index, const char *type, const char **strp) { diff --git a/test/dm/sysinfo.c b/test/dm/sysinfo.c index 14ebe6b42e7..611f2e98d14 100644 --- a/test/dm/sysinfo.c +++ b/test/dm/sysinfo.c @@ -66,3 +66,19 @@ static int dm_test_sysinfo(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_sysinfo, UTF_SCAN_PDATA | UTF_SCAN_FDT); + +static int dm_test_sysinfo_get_and_detect(struct unit_test_state *uts) +{ + struct udevice *sysinfo; + bool called_detect = false; + + ut_assertok(sysinfo_get_and_detect(&sysinfo)); + ut_assert(sysinfo); + + ut_assertok(sysinfo_get_bool(sysinfo, BOOL_CALLED_DETECT, + &called_detect)); + ut_assert(called_detect); + + return 0; +} +DM_TEST(dm_test_sysinfo_get_and_detect, UTF_SCAN_PDATA | UTF_SCAN_FDT); -- cgit v1.3.1 From a30556bc4249b4154f86c9460da740ff86d30807 Mon Sep 17 00:00:00 2001 From: Nora Schiffer Date: Tue, 2 Jun 2026 13:57:51 +0200 Subject: sysinfo: tq_eeprom: new driver Introduce a sysinfo driver that can be instantiated from the device, which will provide information from the EEPROM found on all TQ-Systems SoMs. Signed-off-by: Nora Schiffer Signed-off-by: Max Merchel Reviewed-by: Simon Glass Signed-off-by: Alexander Feilke --- MAINTAINERS | 1 + configs/tqma7_common.config | 1 + .../sysinfo/tq,eeprom-sysinfo.txt | 36 ++++ drivers/sysinfo/Kconfig | 8 + drivers/sysinfo/Makefile | 1 + drivers/sysinfo/tq_eeprom.c | 203 +++++++++++++++++++++ include/sysinfo/tq_eeprom.h | 24 +++ 7 files changed, 274 insertions(+) create mode 100644 doc/device-tree-bindings/sysinfo/tq,eeprom-sysinfo.txt create mode 100644 drivers/sysinfo/tq_eeprom.c create mode 100644 include/sysinfo/tq_eeprom.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index a55742a0baf..ec7217f39f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1865,6 +1865,7 @@ S: Maintained W: https://www.tq-group.com/en/products/tq-embedded/ F: board/tq/* F: doc/board/tq/* +F: drivers/sysinfo/tq_eeprom.c F: include/configs/tq*.h F: include/env/tq/* diff --git a/configs/tqma7_common.config b/configs/tqma7_common.config index 7e5e31a14ab..9b055849ad1 100644 --- a/configs/tqma7_common.config +++ b/configs/tqma7_common.config @@ -77,6 +77,7 @@ CONFIG_I2C_DEFAULT_BUS_NUMBER=0x3 CONFIG_SYS_I2C_MXC=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_NVMEM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y diff --git a/doc/device-tree-bindings/sysinfo/tq,eeprom-sysinfo.txt b/doc/device-tree-bindings/sysinfo/tq,eeprom-sysinfo.txt new file mode 100644 index 00000000000..678fff0e812 --- /dev/null +++ b/doc/device-tree-bindings/sysinfo/tq,eeprom-sysinfo.txt @@ -0,0 +1,36 @@ +TQ EEPROM Sysinfo Driver +------------------------ + +This binding describes a sysinfo provider which retrieves system +identification information from an I2C EEPROM device. + +Required properties: + +- compatible: "tq,eeprom-sysinfo" +- nvmem-cells: phandle referencing the nvmem cell +- nvmem-cell-names: string, should be "device_info" + +Example: + +&i2c1 { + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + module_info: module-info@20 { + reg = <0x20 0x60>; + }; + }; + }; +}; + +sysinfo { + compatible = "tq,eeprom-sysinfo"; + nvmem-cells = <&module_info>; + nvmem-cell-names = "device_info"; +}; diff --git a/drivers/sysinfo/Kconfig b/drivers/sysinfo/Kconfig index df83df69ffb..6922dac9170 100644 --- a/drivers/sysinfo/Kconfig +++ b/drivers/sysinfo/Kconfig @@ -59,4 +59,12 @@ config SYSINFO_GPIO This ternary number is then mapped to a board revision name using device tree properties. +config SYSINFO_TQ_EEPROM + bool "Enable TQ-Systems EEPROM sysinfo driver" + depends on I2C_EEPROM + depends on SPL_I2C_EEPROM || !SPL_SYSINFO + help + Support querying EEPROM of TQ-Systems SOMs to determine board + information. + endif diff --git a/drivers/sysinfo/Makefile b/drivers/sysinfo/Makefile index 26ca3150999..d21fb3c2270 100644 --- a/drivers/sysinfo/Makefile +++ b/drivers/sysinfo/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_SYSINFO_IOT2050) += iot2050.o obj-$(CONFIG_SYSINFO_RCAR3) += rcar3.o obj-$(CONFIG_SYSINFO_SANDBOX) += sandbox.o obj-$(CONFIG_SYSINFO_SMBIOS) += smbios.o +obj-$(CONFIG_SYSINFO_TQ_EEPROM) += tq_eeprom.o diff --git a/drivers/sysinfo/tq_eeprom.c b/drivers/sysinfo/tq_eeprom.c new file mode 100644 index 00000000000..63be07b664e --- /dev/null +++ b/drivers/sysinfo/tq_eeprom.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Nora Schiffer + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define TQ_EE_RSV1_BYTES 10 +#define TQ_EE_SERIAL_BYTES 8 +#define TQ_EE_RSV2_BYTES 8 +#define TQ_EE_BDID_BYTES 0x40 + +struct tq_eeprom_data { + u8 mac[ETH_ALEN]; /* 0x20 ... 0x25 */ + u8 rsv1[TQ_EE_RSV1_BYTES]; + u8 serial[TQ_EE_SERIAL_BYTES]; /* 0x30 ... 0x37 */ + u8 rsv2[TQ_EE_RSV2_BYTES]; + u8 id[TQ_EE_BDID_BYTES]; /* 0x40 ... 0x7f */ +}; + +static_assert(sizeof(struct tq_eeprom_data) == 0x60, + "struct tq_eeprom_data has incorrect size"); + +/** + * struct sysinfo_tq_eeprom_priv - sysinfo private data + */ +struct sysinfo_tq_eeprom_priv { + struct nvmem_cell device_info_cell; + + /* Reserve extra space for \0 in id and serial */ + char id[TQ_EE_BDID_BYTES + 1]; + char serial[TQ_EE_SERIAL_BYTES + 1]; + u8 mac[ETH_ALEN]; +}; + +static void tq_eeprom_parse_id(struct udevice *dev, const struct tq_eeprom_data *data) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < sizeof(data->id); i++) { + if (!(isprint(data->id[i]) && isascii(data->id[i]))) + break; + } + + if (i == 0) + dev_warn(dev, "no valid model name in EEPROM\n"); + + snprintf(priv->id, sizeof(priv->id), "%.*s", i, data->id); +} + +static int tq_eeprom_serial_len(const struct tq_eeprom_data *data, bool allow_upper) +{ + int i; + + for (i = 0; i < sizeof(data->serial); i++) { + if (!(isdigit(data->serial[i]) || (allow_upper && isupper(data->serial[i])))) + break; + } + + return i; +} + +static void tq_eeprom_parse_serial(struct udevice *dev, const struct tq_eeprom_data *data) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + bool use_new_format; + int len; + + use_new_format = data->serial[0] == 'T' && data->serial[1] == 'Q'; + + len = tq_eeprom_serial_len(data, use_new_format); + + /* For now, only serial numbers with the exact size of the field are accepted */ + if (len != sizeof(data->serial)) { + dev_warn(dev, "no valid serial number in EEPROM\n"); + len = 0; + } + + snprintf(priv->serial, sizeof(priv->serial), "%.*s", len, data->serial); +} + +static int tq_eeprom_dump(const struct sysinfo_tq_eeprom_priv *priv) +{ + printf("TQ EEPROM:\n"); + printf(" ID: %s\n", priv->id[0] ? priv->id : ""); + printf(" SN: %s\n", priv->serial[0] ? priv->serial : ""); + printf(" MAC: "); + if (is_valid_ethaddr(priv->mac)) + printf("%pM\n", priv->mac); + else + printf("\n"); + + return 0; +} + +static int sysinfo_tq_eeprom_detect(struct udevice *dev) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + struct tq_eeprom_data data; + int ret; + + ret = nvmem_cell_read(&priv->device_info_cell, (u8 *)&data, sizeof(data)); + if (ret < 0) { + dev_err(dev, "EEPROM read failed: %d\n", ret); + return ret; + } + + tq_eeprom_parse_id(dev, &data); + tq_eeprom_parse_serial(dev, &data); + memcpy(priv->mac, data.mac, ETH_ALEN); + + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + tq_eeprom_dump(priv); + + return 0; +} + +static int sysinfo_tq_eeprom_get_str(struct udevice *dev, int id, size_t size, char *val) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + + switch (id) { + case SYSID_TQ_MODEL: + if (!priv->id[0]) + return -ENODATA; + + strlcpy(val, priv->id, size); + return 0; + + case SYSID_TQ_SERIAL: + if (!priv->serial[0]) + return -ENODATA; + + strlcpy(val, priv->serial, size); + return 0; + + default: + return -EINVAL; + } +} + +static int sysinfo_tq_eeprom_get_data(struct udevice *dev, int id, void **data, size_t *size) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + + switch (id) { + case SYSID_TQ_MAC_ADDR: + if (!is_valid_ethaddr(priv->mac)) + return -ENODATA; + + *data = priv->mac; + *size = sizeof(priv->mac); + + return 0; + + default: + return -EINVAL; + } +} + +static const struct sysinfo_ops sysinfo_tq_eeprom_ops = { + .detect = sysinfo_tq_eeprom_detect, + .get_str = sysinfo_tq_eeprom_get_str, + .get_data = sysinfo_tq_eeprom_get_data, +}; + +static int sysinfo_tq_eeprom_probe(struct udevice *dev) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + int ret; + + ret = nvmem_cell_get_by_name(dev, "device_info", &priv->device_info_cell); + if (ret) { + dev_err(dev, "device_info not found: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct udevice_id sysinfo_tq_eeprom_ids[] = { + { .compatible = "tq,eeprom-sysinfo" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sysinfo_tq_eeprom) = { + .name = "sysinfo_tq_eeprom", + .id = UCLASS_SYSINFO, + .of_match = sysinfo_tq_eeprom_ids, + .ops = &sysinfo_tq_eeprom_ops, + .priv_auto = sizeof(struct sysinfo_tq_eeprom_priv), + .probe = sysinfo_tq_eeprom_probe, +}; diff --git a/include/sysinfo/tq_eeprom.h b/include/sysinfo/tq_eeprom.h new file mode 100644 index 00000000000..6b1bddd7ce0 --- /dev/null +++ b/include/sysinfo/tq_eeprom.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Nora Schiffer + */ + +#ifndef __SYSINFO_TQ_EEPROM_H__ +#define __SYSINFO_TQ_EEPROM_H__ + +#include + +enum { + /* Model string of TQ-Systems SOM. This is different from BOARD_MODEL, + * which usually combines SOM and baseboard names for TQ hardware + */ + SYSID_TQ_MODEL = SYSID_USER, + /* SOM serial number */ + SYSID_TQ_SERIAL, + /* MAC address */ + SYSID_TQ_MAC_ADDR, +}; + +#endif /* __SYSINFO_TQ_EEPROM_H__ */ -- cgit v1.3.1 From f2390069d45b3490cfd87de6d6bac6e646796b6b Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Thu, 14 May 2026 15:52:19 +0530 Subject: firmware: zynqmp: Add PMC PGGS register read API Add zynqmp_pm_get_pmc_global_pggs_reg() to read PMC Global PGGS3 and PGGS4 registers via firmware IOCTL. Supports IOCTL_READ_PGGS as the preferred path and falls back to IOCTL_READ_REG for older PLM firmware versions that do not support IOCTL_READ_PGGS. Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260514102601.1759779-3-padmarao.begari@amd.com --- drivers/firmware/firmware-zynqmp.c | 54 +++++++++++++++++++++++++++++++++++++- include/zynqmp_firmware.h | 4 +++ 2 files changed, 57 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index fb583580ebe..ea14ed4ef95 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -3,7 +3,7 @@ * Xilinx Zynq MPSoC Firmware driver * * Copyright (C) 2018-2019 Xilinx, Inc. - * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. */ #include @@ -197,6 +197,58 @@ int zynqmp_pm_ufs_cal_reg(u32 *value) *value = readl(PMXC_EFUSE_CACHE_BASE_ADDRESS + PMXC_UFS_CAL_1_OFFSET); return 0; } +#endif /* CONFIG_ARCH_VERSAL2 */ + +#if defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL2) +u32 zynqmp_pm_get_pmc_global_pggs_reg(u32 reg_addr) +{ + int ret; + u32 value = 0; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + if (reg_addr == PMC_GLOBAL_PGGS3_REG) { + value = 0; + } else if (reg_addr == PMC_GLOBAL_PGGS4_REG) { + value = 1; + } else { + printf("%s: not supported pggs register 0x%x\n", + __func__, reg_addr); + return 0; + } + + ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_PGGS); + if (ret) { + ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_REG); + if (ret) { + printf("%s: IOCTL_READ_REG is not supported : %d\n" + , __func__, ret); + return 0; + } + + /* find node ID from the pggs3 offset */ + value = PM_REG_PGGS3 + value; + + ret = xilinx_pm_request(PM_IOCTL, value, + IOCTL_READ_REG, 0, 0, 0, 0, + ret_payload); + if (ret) { + printf("%s: node 0x%x get pggs register failed\n", + __func__, value); + return 0; + } + } else { + ret = xilinx_pm_request(PM_IOCTL, PMC_GLOBAL_PGGS3_REG_NODE, + IOCTL_READ_PGGS, value, 0, 0, 0, + ret_payload); + if (ret) { + printf("%s: node 0x%x get pggs register failed\n", + __func__, PMC_GLOBAL_PGGS3_REG_NODE); + return 0; + } + } + + return ret_payload[1]; +} #endif int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value) diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index f5e72625e53..0e545e3db1b 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -470,6 +470,7 @@ int zynqmp_pm_ufs_sram_csr_read(u32 *value); int zynqmp_pm_ufs_sram_csr_write(u32 *value); int zynqmp_pm_ufs_cal_reg(u32 *value); u32 zynqmp_pm_get_pmc_multi_boot_reg(void); +u32 zynqmp_pm_get_pmc_global_pggs_reg(u32 reg_addr); /* Type of Config Object */ #define PM_CONFIG_OBJECT_TYPE_BASE 0x1U @@ -534,4 +535,7 @@ extern smc_call_handler_t __data smc_call_handler; #define PM_DEV_OSPI (0x1822402aU) +#define PM_REG_PGGS3 0x30004003 +#define PMC_GLOBAL_PGGS3_REG_NODE 0x1824C005 + #endif /* _ZYNQMP_FIRMWARE_H_ */ -- cgit v1.3.1 From 818c06faa119f3101c9df24c0ef1b815c2abd929 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Thu, 14 May 2026 15:52:21 +0530 Subject: board: amd: Add capsule and FWU support Add configure_capsule_updates() supporting MMC, SD and QSPI/OSPI boot modes for DFU string generation. Add set_dfu_alt_info() for FWU multi-bank mode to generate DFU alt info from NOR flash MTD partitions. Add XILINX_BOOT_IMAGE_GUID for the capsule updatable firmware image. Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260514102601.1759779-5-padmarao.begari@amd.com --- board/amd/versal2/board.c | 131 +++++++++++++++++++++++++++++++++++++++++- include/configs/amd_versal2.h | 5 ++ 2 files changed, 135 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index 81daba1c5ef..ec28e60c410 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -1,17 +1,24 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2021 - 2022, Xilinx, Inc. - * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ #include +#include +#include +#include #include +#include #include #include #include #include +#include +#include +#include #include #include #include @@ -26,6 +33,7 @@ #include "../../xilinx/common/board.h" #include +#include #include #include #include @@ -348,6 +356,10 @@ int board_late_init(void) int ret; u32 multiboot; + if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && + !IS_ENABLED(CONFIG_FWU_MULTI_BANK_UPDATE)) + configure_capsule_updates(); + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { debug("Saved variables - Skipping\n"); return 0; @@ -476,3 +488,120 @@ enum env_location env_get_location(enum env_operation op, int prio) } } #endif + +#define DFU_ALT_BUF_LEN SZ_1K + +#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && \ + !defined(CONFIG_FWU_MULTI_BANK_UPDATE) +static void mtd_found_part(u32 *base, u32 *size) +{ + struct mtd_info *part, *mtd; + + mtd_probe_devices(); + + mtd = get_mtd_device_nm("nor0"); + if (!IS_ERR_OR_NULL(mtd)) { + list_for_each_entry(part, &mtd->partitions, node) { + debug("0x%012llx-0x%012llx : \"%s\"\n", + part->offset, part->offset + part->size, + part->name); + + if (*base >= part->offset && + *base < part->offset + part->size) { + debug("Found my partition: %d/%s\n", + part->index, part->name); + *base = part->offset; + *size = part->size; + break; + } + } + } +} + +void configure_capsule_updates(void) +{ + int bootseq = 0, len = 0; + u32 multiboot = versal2_multi_boot(); + u32 bootmode = versal2_get_bootmode(); + + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + + memset(buf, 0, DFU_ALT_BUF_LEN); + + multiboot = env_get_hex("multiboot", multiboot); + + switch (bootmode) { + case EMMC_MODE: + case SD_MODE: + case SD1_LSHFT_MODE: + case SD_MODE1: + bootseq = mmc_get_env_dev(); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, "mmc %d=boot", + bootseq); + + if (multiboot) + len += snprintf(buf + len, DFU_ALT_BUF_LEN, + "%04d", multiboot); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1", + bootseq); + break; + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + case OSPI_MODE: + { + u32 base = multiboot * SZ_32K; + u32 size = 0x1500000; + u32 limit = size; + + mtd_found_part(&base, &limit); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, + "sf 0:0=boot.bin raw 0x%x 0x%x", + base, limit); + } + break; + default: + return; + } + + update_info.dfu_string = strdup(buf); + debug("Capsule DFU: %s\n", update_info.dfu_string); +} +#endif + +#if defined(CONFIG_FWU_MULTI_BANK_UPDATE) + +/* Generate dfu_alt_info from partitions */ +void set_dfu_alt_info(char *interface, char *devstr) +{ + int ret; + struct mtd_info *mtd; + + /* + * It is called multiple times for every image + * per bank that's why enough to set it up once. + */ + if (env_get("dfu_alt_info")) + return; + + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + memset(buf, 0, DFU_ALT_BUF_LEN); + + mtd_probe_devices(); + + mtd = get_mtd_device_nm("nor0"); + if (IS_ERR_OR_NULL(mtd)) + return; + + ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd); + if (ret < 0) { + log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret); + return; + } + log_debug("Make dfu_alt_info: '%s'\n", buf); + + env_set("dfu_alt_info", buf); +} +#endif diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h index fccc786219f..a07e12bd146 100644 --- a/include/configs/amd_versal2.h +++ b/include/configs/amd_versal2.h @@ -23,6 +23,11 @@ #define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } +/* GUID for capsule updatable firmware image */ +#define XILINX_BOOT_IMAGE_GUID \ + EFI_GUID(0xed9e7fcf, 0x47b3, 0x40cd, 0xb6, 0xe3, \ + 0x56, 0x5f, 0x14, 0x67, 0x6d, 0x82) + #if defined(CONFIG_CMD_DFU) #define DFU_DEFAULT_POLL_TIMEOUT 300 #define DFU_ALT_INFO_RAM \ -- cgit v1.3.1 From 19f7def2646f2ec2926e8a0fcff50d4b754eec92 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 25 May 2026 13:45:42 +0200 Subject: reset: Add reset_reset() and reset_reset_bulk() API Add reset_reset() and reset_reset_bulk() functions to the reset controller API. These functions assert and then deassert reset signals in a single call, providing a convenient way to pulse/toggle a reset line. This mimics the Linux kernel's reset_control_reset() and reset_control_bulk_reset() APIs. The new functions are useful for drivers that need to cycle a reset line during initialization or error recovery but with also passing delay parameter. If a driver implements the rst_reset op, it will be called directly with the delay parameter. Otherwise, the reset core performs reset_assert(), optional udelay(), and reset_deassert() as fallback. Reviewed-by: Simon Glass Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/55ddd313c9e7b2d4dc79ab36bdd0040f871610f6.1779709539.git.michal.simek@amd.com --- drivers/reset/reset-uclass.c | 34 ++++++++++++++++++++++++++++++ include/reset-uclass.h | 19 +++++++++++++++++ include/reset.h | 49 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 102 insertions(+) (limited to 'include') diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c index fe4cebf54f1..c199e3e5da7 100644 --- a/drivers/reset/reset-uclass.c +++ b/drivers/reset/reset-uclass.c @@ -13,6 +13,7 @@ #include #include #include +#include static inline struct reset_ops *reset_dev_ops(struct udevice *dev) { @@ -225,6 +226,39 @@ int reset_deassert_bulk(struct reset_ctl_bulk *bulk) return 0; } +int reset_reset(struct reset_ctl *reset_ctl, ulong delay_us) +{ + struct reset_ops *ops = reset_dev_ops(reset_ctl->dev); + int ret; + + debug("%s(reset_ctl=%p, delay_us=%lu)\n", __func__, reset_ctl, + delay_us); + + if (ops->rst_reset) + return ops->rst_reset(reset_ctl, delay_us); + + ret = reset_assert(reset_ctl); + if (ret < 0) + return ret; + + udelay(delay_us); + + return reset_deassert(reset_ctl); +} + +int reset_reset_bulk(struct reset_ctl_bulk *bulk, ulong delay_us) +{ + int i, ret; + + for (i = 0; i < bulk->count; i++) { + ret = reset_reset(&bulk->resets[i], delay_us); + if (ret < 0) + return ret; + } + + return 0; +} + int reset_status(struct reset_ctl *reset_ctl) { struct reset_ops *ops = reset_dev_ops(reset_ctl->dev); diff --git a/include/reset-uclass.h b/include/reset-uclass.h index 9a0696dd1e3..7af090b60b5 100644 --- a/include/reset-uclass.h +++ b/include/reset-uclass.h @@ -76,6 +76,25 @@ struct reset_ops { * @return 0 if OK, or a negative error code. */ int (*rst_deassert)(struct reset_ctl *reset_ctl); + /** + * rst_reset - Reset a HW module. + * + * This optional function triggers a reset pulse on the reset line. + * If not implemented, reset_reset() falls back to rst_assert(), + * udelay(@delay_us), then rst_deassert(); that delay is therefore + * observed only on the fallback path. + * + * When rst_reset is provided, @delay_us is controller-specific: the + * implementation should honour it if the hardware needs a minimum + * assertion time before release. It may ignore @delay_us when the + * pulse shape is fixed elsewhere (for example a firmware pulse). + * + * @reset_ctl: The reset signal to pulse. + * @delay_us: Minimum delay in microseconds between assert and + * deassert where applicable; see above. + * @return 0 if OK, or a negative error code. + */ + int (*rst_reset)(struct reset_ctl *reset_ctl, ulong delay_us); /** * rst_status - Check reset signal status. * diff --git a/include/reset.h b/include/reset.h index 036a786d2ac..58574b983f6 100644 --- a/include/reset.h +++ b/include/reset.h @@ -320,6 +320,45 @@ int reset_deassert(struct reset_ctl *reset_ctl); */ int reset_deassert_bulk(struct reset_ctl_bulk *bulk); +/** + * reset_reset - Reset a HW module by asserting and deasserting a reset signal. + * + * This function will assert and then deassert the specified reset signal, + * thus resetting the affected HW module. This is a convenience function + * that combines reset_assert() and reset_deassert(). + * + * If the controller implements struct reset_ops.rst_reset, that callback + * is used and @delay_us is interpreted as documented there. Otherwise the + * core performs reset_assert(), udelay(@delay_us), then reset_deassert(). + * + * @reset_ctl: A reset control struct that was previously successfully + * requested by reset_get_by_*(). + * @delay_us: Delay in microseconds between assert and deassert on the + * fallback path; meaning is driver-specific when rst_reset is used. + * Use 0 for no delay on the fallback path. + * Return: 0 if OK, or a negative error code. + */ +int reset_reset(struct reset_ctl *reset_ctl, ulong delay_us); + +/** + * reset_reset_bulk - Reset all HW modules in a reset control bulk struct. + * + * This calls reset_reset() on each entry in order. Each line therefore + * completes its own assert/delay/deassert (or controller rst_reset) before + * the next entry starts. That matches Linux reset_control_bulk_reset(). + * + * When several lines must stay asserted together for @delay_us (typical + * multi-reset controllers), use reset_assert_bulk(), udelay(@delay_us), + * and reset_deassert_bulk() instead. + * + * @bulk: A reset control bulk struct that was previously successfully + * requested by reset_get_bulk(). + * @delay_us: Delay in microseconds passed to each reset_reset(); see + * reset_reset() and struct reset_ops.rst_reset. + * Return: 0 if OK, or a negative error code. + */ +int reset_reset_bulk(struct reset_ctl_bulk *bulk, ulong delay_us); + /** * rst_status - Check reset signal status. * @@ -443,6 +482,16 @@ static inline int reset_deassert_bulk(struct reset_ctl_bulk *bulk) return 0; } +static inline int reset_reset(struct reset_ctl *reset_ctl, ulong delay_us) +{ + return -ENOSYS; +} + +static inline int reset_reset_bulk(struct reset_ctl_bulk *bulk, ulong delay_us) +{ + return -ENOSYS; +} + static inline int reset_status(struct reset_ctl *reset_ctl) { return -ENOTSUPP; -- cgit v1.3.1 From 59e13ed8f6d8b030c6aaf7e2af77f073fecc3b30 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 19 Dec 2025 11:59:36 +1300 Subject: arm: mvebu: Add Allied Telesis x220 Add the Allied Telesis x220 board. There are a number of other variants with the same CPU block that are sold under some different brand names but the x220 was first. The x220 uses the AlleyCat3 switch chip with integrated ARMv7 CPU. Because of this it is reliant on a binary blob for the DDR training. In upstream u-boot this is replaced by an empty file. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- arch/arm/dts/Makefile | 1 + arch/arm/dts/armada-xp-atl-x220.dts | 162 +++++++++++++++++++++++++++++++ arch/arm/mach-mvebu/Kconfig | 7 ++ board/alliedtelesis/x220/.gitattributes | 1 + board/alliedtelesis/x220/.gitignore | 1 + board/alliedtelesis/x220/MAINTAINERS | 8 ++ board/alliedtelesis/x220/Makefile | 14 +++ board/alliedtelesis/x220/binary.0 | 11 +++ board/alliedtelesis/x220/kwbimage.cfg.in | 12 +++ board/alliedtelesis/x220/x220.c | 67 +++++++++++++ configs/x220_defconfig | 76 +++++++++++++++ doc/board/alliedtelesis/index.rst | 11 +++ doc/board/alliedtelesis/x220.rst | 39 ++++++++ doc/board/index.rst | 1 + include/configs/x220.h | 20 ++++ 15 files changed, 431 insertions(+) create mode 100644 arch/arm/dts/armada-xp-atl-x220.dts create mode 100644 board/alliedtelesis/x220/.gitattributes create mode 100644 board/alliedtelesis/x220/.gitignore create mode 100644 board/alliedtelesis/x220/MAINTAINERS create mode 100644 board/alliedtelesis/x220/Makefile create mode 100644 board/alliedtelesis/x220/binary.0 create mode 100644 board/alliedtelesis/x220/kwbimage.cfg.in create mode 100644 board/alliedtelesis/x220/x220.c create mode 100644 configs/x220_defconfig create mode 100644 doc/board/alliedtelesis/index.rst create mode 100644 doc/board/alliedtelesis/x220.rst create mode 100644 include/configs/x220.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b75f3ee4386..722a7a662b1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -137,6 +137,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-388-gp.dtb \ armada-388-helios4.dtb \ armada-38x-controlcenterdc.dtb \ + armada-xp-atl-x220.dtb \ armada-xp-crs305-1g-4s.dtb \ armada-xp-crs305-1g-4s-bit.dtb \ armada-xp-crs326-24g-2s.dtb \ diff --git a/arch/arm/dts/armada-xp-atl-x220.dts b/arch/arm/dts/armada-xp-atl-x220.dts new file mode 100644 index 00000000000..5b3307ed288 --- /dev/null +++ b/arch/arm/dts/armada-xp-atl-x220.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for x220 board + * + * Copyright (C) 2025 Allied Telesis Labs + */ + +/dts-v1/; +#include +#include "armada-xp-98dx3236.dtsi" +#include "mvebu-u-boot.dtsi" + +/ { + model = "x220"; + compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp-mv78260", + "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "console=ttyS0,115200"; + }; + + aliases { + i2c0 = &i2c0; + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + rtc@68 { + compatible = "dallas,ds1340"; + reg = <0x68>; + }; + + adt7476a@2e { + compatible = "adi,adt7476"; + reg = <0x2e>; + }; + + sfpgpio: gpio@27 { + #address-cells = <2>; + #size-cells = <0>; + compatible = "nxp,pca9555"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + }; + + systemgpio: gpio@25 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9555"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + + nand-protect { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "nand-protect"; + }; + + usb-enable { + gpio-hog; + gpios = <9 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-enable"; + }; + + phy-reset { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-high; + line-name = "phy-reset"; + }; + + led-enable { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "led-enable"; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + }; +}; + +&nand_controller { + compatible = "marvell,armada370-nand-controller"; + label = "pxa3xx_nand-0"; + status = "okay"; + nand-rb = <0>; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; +}; + +&{/} { + boot-board { + compatible = "atl,boot-board"; + present-gpio = <&systemgpio 12 GPIO_ACTIVE_HIGH>; + override-gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; +}; + diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 4afaee234ea..0b4df8e7be9 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -226,6 +226,10 @@ config TARGET_X240 select ALLEYCAT_5 imply BOOTSTD_DEFAULTS +config TARGET_X220 + bool "Support Allied Telesis x220" + select 98DX3336 + config TARGET_DB_XC3_24G4XG bool "Support DB-XC3-24G4XG" select 98DX3336 @@ -310,6 +314,7 @@ config SYS_BOARD default "x530" if TARGET_X530 default "x250" if TARGET_X250 default "x240" if TARGET_X240 + default "x220" if TARGET_X220 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5 @@ -335,6 +340,7 @@ config SYS_CONFIG_NAME default "x530" if TARGET_X530 default "x250" if TARGET_X250 default "x240" if TARGET_X240 + default "x220" if TARGET_X220 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5 @@ -360,6 +366,7 @@ config SYS_VENDOR default "alliedtelesis" if TARGET_X530 default "alliedtelesis" if TARGET_X250 default "alliedtelesis" if TARGET_X240 + default "alliedtelesis" if TARGET_X220 default "mikrotik" if TARGET_CRS3XX_98DX3236 default "Marvell" if TARGET_MVEBU_ALLEYCAT5 diff --git a/board/alliedtelesis/x220/.gitattributes b/board/alliedtelesis/x220/.gitattributes new file mode 100644 index 00000000000..2aeb4eee641 --- /dev/null +++ b/board/alliedtelesis/x220/.gitattributes @@ -0,0 +1 @@ +binary.0 binary diff --git a/board/alliedtelesis/x220/.gitignore b/board/alliedtelesis/x220/.gitignore new file mode 100644 index 00000000000..775b9346b85 --- /dev/null +++ b/board/alliedtelesis/x220/.gitignore @@ -0,0 +1 @@ +kwbimage.cfg diff --git a/board/alliedtelesis/x220/MAINTAINERS b/board/alliedtelesis/x220/MAINTAINERS new file mode 100644 index 00000000000..63da2725f71 --- /dev/null +++ b/board/alliedtelesis/x220/MAINTAINERS @@ -0,0 +1,8 @@ +x220 BOARD +M: Chris Packham +S: Maintained +F: board/alliedtelesis/x220 +F: include/configs/x220.h +F: configs/x220_defconfig +F: arch/arm/dts/armada-xp-atl-x220.dts +F: doc/board/alliedtelesis/x220.rst diff --git a/board/alliedtelesis/x220/Makefile b/board/alliedtelesis/x220/Makefile new file mode 100644 index 00000000000..a74f0a76948 --- /dev/null +++ b/board/alliedtelesis/x220/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 Allied Telesis Labs + +obj-y := x220.o +extra-y := kwbimage.cfg + +quiet_cmd_sed = SED $@ + cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F) + +SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|" +$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ + include/config/auto.conf + $(call if_changed,sed) diff --git a/board/alliedtelesis/x220/binary.0 b/board/alliedtelesis/x220/binary.0 new file mode 100644 index 00000000000..8dd687286a0 --- /dev/null +++ b/board/alliedtelesis/x220/binary.0 @@ -0,0 +1,11 @@ +-------- +WARNING: +-------- +This file should contain the bin_hdr generated by the original Marvell +U-Boot implementation. As this is currently not included in this +U-Boot version, we have added this placeholder, so that the U-Boot +image can be generated without errors. + +If you have a known to be working bin_hdr for your board, then you +just need to replace this text file here with the binary header +and recompile U-Boot. diff --git a/board/alliedtelesis/x220/kwbimage.cfg.in b/board/alliedtelesis/x220/kwbimage.cfg.in new file mode 100644 index 00000000000..8beda907ba4 --- /dev/null +++ b/board/alliedtelesis/x220/kwbimage.cfg.in @@ -0,0 +1,12 @@ +# +# Copyright (C) 2025 Allied Telesis Labs +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/alliedtelesis/x220/binary.0 0000005b 00000068 diff --git a/board/alliedtelesis/x220/x220.c b/board/alliedtelesis/x220/x220.c new file mode 100644 index 00000000000..7c9a73de9a2 --- /dev/null +++ b/board/alliedtelesis/x220/x220.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Allied Telesis Labs + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define X220_GPP_OUT_ENA_LOW (~(BIT(12) | BIT(17) | BIT(18) | BIT(31))) +#define X220_GPP_OUT_ENA_MID (~(0)) +#define X220_GPP_OUT_VAL_LOW (BIT(12) | BIT(18)) +#define X220_GPP_OUT_VAL_MID 0x0 +#define X220_GPP_POL_LOW 0x0 +#define X220_GPP_POL_MID 0x0 + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x44042222, MVEBU_MPP_BASE + 0x00); + writel(0x11000004, MVEBU_MPP_BASE + 0x04); + writel(0x44444004, MVEBU_MPP_BASE + 0x08); + writel(0x04444444, MVEBU_MPP_BASE + 0x0c); + writel(0x00000004, MVEBU_MPP_BASE + 0x10); + + /* Set GPP Out value */ + writel(X220_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(X220_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + + /* Set GPP Polarity */ + writel(X220_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + writel(X220_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); + + /* Set GPP Out Enable */ + writel(X220_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(X220_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + /* Disable MBUS Err Prop - in order to avoid data aborts */ + clrbits_le32(MVEBU_CPU_WIN_BASE + 0x200, (1 << 8)); + + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + puts("Board: Allied Telesis x220\n"); + + return 0; +} +#endif diff --git a/configs/x220_defconfig b/configs/x220_defconfig new file mode 100644 index 00000000000..4318f5e6ef1 --- /dev/null +++ b/configs/x220_defconfig @@ -0,0 +1,76 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_KWD_CONFIG="board/alliedtelesis/x220/kwbimage.cfg" +CONFIG_TEXT_BASE=0x00800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 +CONFIG_TARGET_X220=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x100000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DEFAULT_DEVICE_TREE="armada-xp-atl-x220" +CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_PCI=y +CONFIG_SYS_MEMTEST_START=0x00800000 +CONFIG_SYS_MEMTEST_END=0x00ffffff +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_BEST_MATCH=y +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SYS_MAXARGS=96 +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:112M(user),8M(errlog),8M(nand-bbt)" +CONFIG_CMD_UBI=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ARP_TIMEOUT=200 +CONFIG_NET_RETRY_COUNT=50 +CONFIG_GPIO_HOG=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +# CONFIG_MMC is not set +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_NAND_PXA3XX=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PCI_MVEBU=y +CONFIG_SYS_NS16550=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_WDT=y +CONFIG_WDT_ORION=y diff --git a/doc/board/alliedtelesis/index.rst b/doc/board/alliedtelesis/index.rst new file mode 100644 index 00000000000..a8de2986609 --- /dev/null +++ b/doc/board/alliedtelesis/index.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2026 Allied Telesis Labs + +Allied Telesis +============== + +.. toctree:: + :maxdepth: 2 + + x220 + diff --git a/doc/board/alliedtelesis/x220.rst b/doc/board/alliedtelesis/x220.rst new file mode 100644 index 00000000000..6ca5f61ec4e --- /dev/null +++ b/doc/board/alliedtelesis/x220.rst @@ -0,0 +1,39 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2026 Allied Telesis Labs + +x220 Platforms +============== + +Introduction +------------ + +The x220 has is a range of L2+ switches using the Marvell AlleyCat3 switch with +integrated ARMv7 CPU. It is also sold under some different brands for different +markets. + +- x220-52GP +- x220-52GT +- x220-28GS +- GS980M/52PS +- GS980M/52 +- x230-52 + +DDR Traning (binhdr) +-------------------- + +The AlleyCat3 uses a binary blob for it's DDR training. This is launched by +the built-in bootloader prior to U-Boot starting. + +To generate binary.0 from Marvell's bin_hdr.elf use the following command + +.. prompt:: bash $ + + arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \ + board/alliedtelesis/x220/binary.0 + +Alternatively, it is possible to extract the binary.0 from an existing U-Boot +image + +.. prompt:: bash $ + + ./tools/dumpimage -T kwbimage -p 1 -o board/alliedtelesis/x220/binary.0 u-boot.kwb diff --git a/doc/board/index.rst b/doc/board/index.rst index fcb4224bae3..4103fef8d8f 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -10,6 +10,7 @@ Board-specific doc actions/index advantech/index andestech/index + alliedtelesis/index allwinner/index amlogic/index anbernic/index diff --git a/include/configs/x220.h b/include/configs/x220.h new file mode 100644 index 00000000000..3022ad491b7 --- /dev/null +++ b/include/configs/x220.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Allied Telesis Labs + */ + +#ifndef _CONFIG_X220_H +#define _CONFIG_X220_H + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define CFG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#endif /* _CONFIG_X220_H */ -- cgit v1.3.1 From 3457acc01465644fff255ccbcd65470b64d57184 Mon Sep 17 00:00:00 2001 From: Vincent Jardin Date: Fri, 8 May 2026 15:54:05 +0200 Subject: board: freebox: add Nodebox 10G board support Add board support for the Freebox Nodebox 10G based on the Marvell Armada 8040 SoC. This board features: - Quad-core ARMv8 AP806 with dual CP110 companions - eMMC storage via Xenon SDHCI controller - 1G SGMII Ethernet on CP0 lane 5 - I2C buses for peripheral access - NS16550 UART console at 115200 baud The implementation includes: - Device tree for the Nodebox 10G hardware - Dedicated board directory (board/freebox/nbx10g/) - Board-specific Kconfig and defconfig The U-Boot comphy bindings (phy-type/phy-speed) differ from the mainline Linux PHY framework bindings used by phy-mvebu-cp110-comphy, so U-Boot and the kernel each have their own device tree. Signed-off-by: Vincent Jardin Reviewed-by: Stefan Roese --- arch/arm/dts/Makefile | 1 + arch/arm/dts/armada-8040-nbx.dts | 259 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-mvebu/Kconfig | 9 ++ board/freebox/nbx10g/Kconfig | 12 ++ board/freebox/nbx10g/MAINTAINERS | 6 + board/freebox/nbx10g/Makefile | 3 + board/freebox/nbx10g/board.c | 53 ++++++++ configs/mvebu_nbx_88f8040_defconfig | 75 +++++++++++ include/configs/nbx10g.h | 29 ++++ 9 files changed, 447 insertions(+) create mode 100644 arch/arm/dts/armada-8040-nbx.dts create mode 100644 board/freebox/nbx10g/Kconfig create mode 100644 board/freebox/nbx10g/MAINTAINERS create mode 100644 board/freebox/nbx10g/Makefile create mode 100644 board/freebox/nbx10g/board.c create mode 100644 configs/mvebu_nbx_88f8040_defconfig create mode 100644 include/configs/nbx10g.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 722a7a662b1..c647379c5ac 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -163,6 +163,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-8040-clearfog-gt-8k.dtb \ armada-8040-db.dtb \ armada-8040-mcbin.dtb \ + armada-8040-nbx.dtb \ armada-8040-puzzle-m801.dtb \ cn9130-db-A.dtb \ cn9130-db-B.dtb \ diff --git a/arch/arm/dts/armada-8040-nbx.dts b/arch/arm/dts/armada-8040-nbx.dts new file mode 100644 index 00000000000..b8b7298b4f5 --- /dev/null +++ b/arch/arm/dts/armada-8040-nbx.dts @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for NBX board (Freebox Nodebox10G) + * Based on Marvell Armada 8040 SoC + * + * Copyright (C) 2024 + */ + +#include "armada-8040.dtsi" + +/ { + model = "NBX Armada 8040"; + compatible = "nbx,armada8040", "marvell,armada8040"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + i2c0 = &cp0_i2c0; + i2c1 = &cp0_i2c1; + gpio0 = &ap_gpio0; + gpio1 = &cp0_gpio0; + gpio2 = &cp0_gpio1; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; /* 2GB */ + }; +}; + +/* AP806 UART - active */ +&uart0 { + status = "okay"; +}; + +/* AP806 pinctrl */ +&ap_pinctl { + /* + * MPP Bus: + * eMMC [0-10] + * UART0 [11,19] + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 1 1 1 1 1 1 1 1 1 1 + 1 3 0 0 0 0 0 0 0 3 >; +}; + +/* AP806 on-board eMMC */ +&ap_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&ap_emmc_pins>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* CP0 pinctrl */ +&cp0_pinctl { + /* + * MPP Bus: + * [0-31] = 0xff: Keep default CP0_shared_pins + * [32,34] GE_MDIO/MDC + * [35-36] I2C1 + * [37-38] I2C0 + * [57-58] MSS I2C + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 7 0 7 2 2 2 2 0 + 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 2 2 0 + 0 0 0 >; + + cp0_smi_pins: cp0-smi-pins { + marvell,pins = <32 34>; + marvell,function = <7>; + }; +}; + +/* CP0 I2C0 */ +&cp0_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +/* CP0 I2C1 */ +&cp0_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c1_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +/* CP0 MSS I2C0 - Management SubSystem I2C (pins 57-58, func 2) */ +&cp0_mss_i2c0 { + status = "okay"; +}; + +/* CP0 MDIO for PHY */ +&cp0_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_smi_pins>; + + nbx_phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +/* CP0 ComPhy - SerDes configuration */ +&cp0_comphy { + /* + * CP0 Serdes Configuration: + * Lane 0-3: Unconnected + * Lane 4: SFI (10G Ethernet) + * Lane 5: SGMII2 (1G Ethernet) + */ + phy0 { + phy-type = ; + }; + phy1 { + phy-type = ; + }; + phy2 { + phy-type = ; + }; + phy3 { + phy-type = ; + }; + phy4 { + phy-type = ; + phy-speed = ; + }; + phy5 { + phy-type = ; + phy-speed = ; + }; +}; + +/* CP0 Ethernet - only eth2 (MAC3) is active via SGMII */ +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth2 { + status = "okay"; + phy = <&nbx_phy0>; + phy-mode = "sgmii"; +}; + +/* CP0 UTMI PHY for USB */ +&cp0_utmi { + status = "okay"; +}; + +&cp0_utmi0 { + status = "okay"; +}; + +&cp0_utmi1 { + status = "okay"; +}; + +/* CP0 USB3 Host controllers */ +&cp0_usb3_0 { + status = "okay"; +}; + +&cp0_usb3_1 { + status = "okay"; +}; + +/* CP1 pinctrl */ +&cp1_pinctl { + /* + * MPP Bus: + * [0-26] = Unconfigured + * [27-28] GE_MDIO/MDC + * [29-30] MSS I2C + * [31] = Unconfigured + * [32-62] = 0xff: Keep default CP1_shared_pins + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x8 0x8 0x8 + 0x8 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff>; + + cp1_mss_i2c_pins: cp1-mss-i2c-pins { + marvell,pins = <29 30>; + marvell,function = <8>; + }; +}; + +/* CP1 MSS I2C0 - Management SubSystem I2C (pins 29-30, func 8) */ +&cp1_mss_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_mss_i2c_pins>; +}; + +/* CP1 ComPhy - SerDes configuration */ +&cp1_comphy { + /* + * CP1 Serdes Configuration: + * Lane 0: PCIe x1 + * Lane 1: USB3 Host + * Lane 2-3: Unconnected + * Lane 4: SFI (10G Ethernet) + * Lane 5: Unconnected + */ + phy0 { + phy-type = ; + }; + phy1 { + phy-type = ; + }; + phy2 { + phy-type = ; + }; + phy3 { + phy-type = ; + }; + phy4 { + phy-type = ; + phy-speed = ; + }; + phy5 { + phy-type = ; + }; +}; + +/* CP1 PCIe x1 on lane 0 */ +&cp1_pcie0 { + status = "okay"; +}; + +/* CP1 USB3 Host on lane 1 */ +&cp1_usb3_0 { + status = "okay"; +}; + +/* CP1 UTMI PHY for USB */ +&cp1_utmi { + status = "okay"; +}; + +&cp1_utmi0 { + status = "okay"; +}; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 0b4df8e7be9..3465ccfc151 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -166,6 +166,14 @@ config TARGET_MVEBU_ARMADA_8K select BOARD_LATE_INIT imply SCSI +config TARGET_NBX10G + bool "Support Freebox Nodebox 10G" + select ARMADA_8K + select BOARD_LATE_INIT + help + Enable support for the Freebox Nodebox 10G board based on the + Marvell Armada 8040 SoC with dual CP110 companion chips. + config TARGET_MVEBU_ALLEYCAT5 bool "Support AlleyCat 5 platforms" select ALLEYCAT_5 @@ -515,5 +523,6 @@ config ARMADA_32BIT_SYSCON_SYSRESET source "board/solidrun/clearfog/Kconfig" source "board/kobol/helios4/Kconfig" +source "board/freebox/nbx10g/Kconfig" endif diff --git a/board/freebox/nbx10g/Kconfig b/board/freebox/nbx10g/Kconfig new file mode 100644 index 00000000000..18a169761b7 --- /dev/null +++ b/board/freebox/nbx10g/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NBX10G + +config SYS_BOARD + default "nbx10g" + +config SYS_VENDOR + default "freebox" + +config SYS_CONFIG_NAME + default "nbx10g" + +endif diff --git a/board/freebox/nbx10g/MAINTAINERS b/board/freebox/nbx10g/MAINTAINERS new file mode 100644 index 00000000000..2e31eed45b9 --- /dev/null +++ b/board/freebox/nbx10g/MAINTAINERS @@ -0,0 +1,6 @@ +NBX10G BOARD +M: Vincent Jardin +S: Maintained +F: board/freebox/nbx10g/ +F: configs/mvebu_nbx_88f8040_defconfig +F: arch/arm/dts/armada-8040-nbx* diff --git a/board/freebox/nbx10g/Makefile b/board/freebox/nbx10g/Makefile new file mode 100644 index 00000000000..bf83bdf63ee --- /dev/null +++ b/board/freebox/nbx10g/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := board.o diff --git a/board/freebox/nbx10g/board.c b/board/freebox/nbx10g/board.c new file mode 100644 index 00000000000..7d16010ec7e --- /dev/null +++ b/board/freebox/nbx10g/board.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2018 Freebox SA + * Copyright (C) 2026 Free Mobile, Vincent Jardin + * + * Freebox Nodebox 10G board support + */ + +#include +#include +#include + +/* Management PHY reset GPIO */ +#define NBX_PHY_RESET_GPIO 83 + +/* Nodebox 10G ASCII art logo */ +static const char * const nbx_logo = + " _ _ _ _ __ ___ _____\n" + " | \\ | | | | | | /_ |/ _ \\ / ____|\n" + " | \\| | ___ __| | ___| |__ _____ __ | | | | | | __\n" + " | . ` |/ _ \\ / _` |/ _ \\ '_ \\ / _ \\ \\/ / | | | | | | |_ |\n" + " | |\\ | (_) | (_| | __/ |_) | (_) > < | | |_| | |__| |\n" + " |_| \\_|\\___/ \\__,_|\\___|_.__/ \\___/_/\\_\\ |_|\\___/ \\_____|\n"; + +int checkboard(void) +{ + printf("%s\n", nbx_logo); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + int ret; + + /* Reset the management PHY */ + ret = gpio_request(NBX_PHY_RESET_GPIO, "phy-reset"); + if (ret) { + printf("Failed to request PHY reset GPIO: %d\n", ret); + return 0; + } + + gpio_direction_output(NBX_PHY_RESET_GPIO, 0); + mdelay(100); + gpio_set_value(NBX_PHY_RESET_GPIO, 1); + mdelay(100); + + return 0; +} diff --git a/configs/mvebu_nbx_88f8040_defconfig b/configs/mvebu_nbx_88f8040_defconfig new file mode 100644 index 00000000000..85a3086d6a0 --- /dev/null +++ b/configs/mvebu_nbx_88f8040_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_MVEBU=y +CONFIG_TEXT_BASE=0x00000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 +CONFIG_TARGET_NBX10G=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x180000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="armada-8040-nbx" +CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0x1000000 +CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_PCI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_EFI_LOADER is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="echo (CRC warning is normal: no env saved yet)" +CONFIG_SYS_PBSIZE=1048 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="nodebox10G>> " +CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +# CONFIG_CMD_SF is not set +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_NBX_EMMCBOOT=y +CONFIG_CMD_NBX_FBXSERIAL=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_EFI_PARTITION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ARP_TIMEOUT=200 +CONFIG_NET_RETRY_COUNT=50 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_I2C_MUX=y +CONFIG_MISC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_XENON=y +# CONFIG_SPI_FLASH is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_GIGE=y +CONFIG_MVPP2=y +CONFIG_PCIE_DW_MVEBU=y +CONFIG_PHY=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_8K=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/nbx10g.h b/include/configs/nbx10g.h new file mode 100644 index 00000000000..bd083b7e7d8 --- /dev/null +++ b/include/configs/nbx10g.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017-2018 Freebox SA + * Copyright (C) 2026 Free Mobile, Vincent Jardin + * + * Configuration for Freebox Nodebox 10G + */ + +#ifndef _CONFIG_NBX10G_H +#define _CONFIG_NBX10G_H + +#include "mvebu_armada-8k.h" + +/* Override environment settings for NBX */ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ + "hostname=nodebox10G\0" \ + "ethrotate=no\0" \ + "image_addr=0x7000000\0" \ + "image_name=Image.nodebox10G\0" \ + "fdt_addr=0x6f00000\0" \ + "fdt_name=nodebox10G.dtb\0" \ + "console=ttyS0,115200\0" \ + "tftpboot=setenv bootargs console=${console} bank=tftp; " \ + "dhcp ${image_addr} ${image_name}; " \ + "tftp ${fdt_addr} ${fdt_name}; " \ + "booti ${image_addr} - ${fdt_addr}\0" + +#endif /* _CONFIG_NBX10G_H */ -- cgit v1.3.1 From 6c636eabbde7f7915fe37c84395b23c61c66ce64 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Tue, 26 May 2026 01:41:40 +0000 Subject: treewide: prefer __func__ over __FUNCTION__ and __PRETTY_FUNCTION__ __FUNCTION__ and __PRETTY_FUNCTION__ are gcc extensions that predate the C99 __func__ identifier. scripts/checkpatch.pl emits a warning for any new use of __FUNCTION__ and recommends __func__ instead. In C (unlike C++) __PRETTY_FUNCTION__ is identical to __func__ because C function names do not carry signature information, so the distinction has no behavioural effect here. The majority of the tree already uses __func__, but a handful of older files in arch/, board/, boot/, drivers/, examples/ and include/ still carry the gcc spellings (55 occurrences of __FUNCTION__ across 19 files plus one __PRETTY_FUNCTION__ in drivers/usb/musb-new/omap2430.c). Convert them all to the C99 form so the tree is consistent and new patches in these areas do not have to follow an outdated local style. Ten "Unnecessary ftrace-like logging - prefer using ftrace" warnings remain on the printf("%s\n", __func__) and dbg("%s\n", __func__) function-entry traces in drivers/net/rtl8169.c (behind DEBUG_RTL8169* preprocessor guards) and drivers/usb/host/ohci-hcd.c. checkpatch matches the literal "%s\n", __func__ shape regardless of the wrapper, so silencing those warnings would require changing the debug message text or removing the traces entirely. Signed-off-by: Aristo Chen Reviewed-by: Tom Rini --- arch/arm/mach-kirkwood/cpu.c | 10 +++++----- arch/mips/include/asm/system.h | 4 ++-- arch/powerpc/cpu/mpc85xx/liodn.c | 2 +- board/Marvell/guruplug/guruplug.c | 2 +- board/socrates/nand.c | 2 +- boot/fdt_support.c | 14 +++++++------- drivers/ddr/fsl/main.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen1.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen2.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 2 +- drivers/fpga/spartan2.c | 12 ++++++------ drivers/fpga/spartan3.c | 12 ++++++------ drivers/fpga/xilinx.c | 12 ++++++------ drivers/net/mcfmii.c | 2 +- drivers/net/rtl8169.c | 18 +++++++++--------- drivers/rtc/m41t62.c | 4 ++-- drivers/usb/host/ohci-hcd.c | 2 +- drivers/usb/musb-new/omap2430.c | 2 +- examples/standalone/sched.c | 2 +- include/usbdevice.h | 6 +++--- 20 files changed, 57 insertions(+), 57 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index a432abe615d..af59d63811c 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -99,16 +99,16 @@ static void kw_sysrst_action(void) if (!s) { debug("Error.. %s failed, check sysrstcmd\n", - __FUNCTION__); + __func__); return; } - debug("Starting %s process...\n", __FUNCTION__); + debug("Starting %s process...\n", __func__); ret = run_command(s, 0); if (ret != 0) - debug("Error.. %s failed\n", __FUNCTION__); + debug("Error.. %s failed\n", __func__); else - debug("%s process finished\n", __FUNCTION__); + debug("%s process finished\n", __func__); } static void kw_sysrst_check(void) @@ -152,7 +152,7 @@ int print_cpuinfo(void) u8 revid = readl(KW_REG_PCIE_REVID) & 0xff; if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) { - printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid); + printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __func__, devid); return -1; } diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h index 00699c4c11a..1156e299433 100644 --- a/arch/mips/include/asm/system.h +++ b/arch/mips/include/asm/system.h @@ -259,9 +259,9 @@ extern void __die_if_kernel(const char *, struct pt_regs *, const char *where, unsigned long line); #define die(msg, regs) \ - __die(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) + __die(msg, regs, __FILE__ ":" __func__, __LINE__) #define die_if_kernel(msg, regs) \ - __die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) + __die_if_kernel(msg, regs, __FILE__ ":" __func__, __LINE__) static inline void execution_hazard_barrier(void) { diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index af6731cbb3a..ddf0ac99cf6 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -110,7 +110,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev, break; #endif default: - printf("Error: Invalid device type to %s\n", __FUNCTION__); + printf("Error: Invalid device type to %s\n", __func__); return; } diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index 7c3cea22b93..78a6d1094b5 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -111,7 +111,7 @@ void mv_phy_88e1121_init(char *name) /* command to read PHY dev address */ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { printf("Err..%s could not read PHY dev address\n", - __FUNCTION__); + __func__); return; } diff --git a/board/socrates/nand.c b/board/socrates/nand.c index b8e6e2cd76e..fc0c04efdd1 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -135,7 +135,7 @@ static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ct break; default: - printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl); + printf("%s: unknown ctrl %#x\n", __func__, ctrl); } if (ctrl & NAND_NCE) diff --git a/boot/fdt_support.c b/boot/fdt_support.c index 1c215e548db..c4d3cc043c5 100644 --- a/boot/fdt_support.c +++ b/boot/fdt_support.c @@ -545,13 +545,13 @@ int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks) if (banks > MEMORY_BANKS_MAX) { printf("%s: num banks %d exceeds hardcoded limit %d." " Recompile with higher MEMORY_BANKS_MAX?\n", - __FUNCTION__, banks, MEMORY_BANKS_MAX); + __func__, banks, MEMORY_BANKS_MAX); return -1; } err = fdt_check_header(blob); if (err < 0) { - printf("%s: %s\n", __FUNCTION__, fdt_strerror(err)); + printf("%s: %s\n", __func__, fdt_strerror(err)); return err; } @@ -1497,7 +1497,7 @@ static u64 __of_translate_address(const void *blob, int node_offset, /* Cound address cells & copy address locally */ bus->count_cells(blob, parent, &na, &ns); if (!OF_CHECK_COUNTS(na, ns)) { - printf("%s: Bad cell count for %s\n", __FUNCTION__, + printf("%s: Bad cell count for %s\n", __func__, fdt_get_name(blob, node_offset, NULL)); goto bail; } @@ -1524,8 +1524,8 @@ static u64 __of_translate_address(const void *blob, int node_offset, pbus = of_match_bus(blob, parent); pbus->count_cells(blob, parent, &pna, &pns); if (!OF_CHECK_COUNTS(pna, pns)) { - printf("%s: Bad cell count for %s\n", __FUNCTION__, - fdt_get_name(blob, node_offset, NULL)); + printf("%s: Bad cell count for %s\n", __func__, + fdt_get_name(blob, node_offset, NULL)); break; } @@ -1612,7 +1612,7 @@ int fdt_get_dma_range(const void *blob, int node, phys_addr_t *cpu, bus_node = of_match_bus(blob, node); bus_node->count_cells(blob, node, &na, &ns); if (!OF_CHECK_COUNTS(na, ns)) { - printf("%s: Bad cell count for %s\n", __FUNCTION__, + printf("%s: Bad cell count for %s\n", __func__, fdt_get_name(blob, node, NULL)); return -EINVAL; goto out; @@ -1621,7 +1621,7 @@ int fdt_get_dma_range(const void *blob, int node, phys_addr_t *cpu, bus_node = of_match_bus(blob, parent); bus_node->count_cells(blob, parent, &pna, &pns); if (!OF_CHECK_COUNTS(pna, pns)) { - printf("%s: Bad cell count for %s\n", __FUNCTION__, + printf("%s: Bad cell count for %s\n", __func__, fdt_get_name(blob, parent, NULL)); return -EINVAL; goto out; diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index d59e94779ff..2b879c63b5f 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -221,7 +221,7 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, unsigned int i2c_address = 0; if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); return; } diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c index a8520754006..e43dc869fc5 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -21,7 +21,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, (struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR; if (ctrl_num != 0) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); return; } diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c index 00b4b376dd4..3a8ad6cc86b 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c @@ -26,7 +26,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #endif if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); return; } diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index b0a61fa2b41..ee9811481ab 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -71,7 +71,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, break; #endif default: - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); return; } diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 792e4033428..e3715bf2b24 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -52,7 +52,7 @@ static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize, default: printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + __func__, desc->iface); } return ret_val; @@ -75,7 +75,7 @@ static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) default: printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + __func__, desc->iface); } return ret_val; @@ -234,7 +234,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -279,7 +279,7 @@ static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) /* XXX - checksum the data? */ } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -423,7 +423,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -434,7 +434,7 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ printf ("%s: Slave Serial Dumping is unavailable\n", - __FUNCTION__); + __func__); return FPGA_FAIL; } diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 98405589134..6221041e092 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -57,7 +57,7 @@ static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize, default: printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + __func__, desc->iface); } return ret_val; @@ -80,7 +80,7 @@ static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) default: printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + __func__, desc->iface); } return ret_val; @@ -241,7 +241,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -286,7 +286,7 @@ static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) /* XXX - checksum the data? */ } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -442,7 +442,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -453,7 +453,7 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ printf ("%s: Slave Serial Dumping is unavailable\n", - __FUNCTION__); + __func__); return FPGA_FAIL; } diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 44d7ad6bd54..b6966c7d2cb 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -149,8 +149,8 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize, bitstream_type bstype, int flags) { - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); + if (!xilinx_validate(desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); return FPGA_FAIL; } @@ -200,8 +200,8 @@ int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize, int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) { - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); + if (!xilinx_validate(desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); return FPGA_FAIL; } @@ -217,7 +217,7 @@ int xilinx_info(xilinx_desc *desc) { int ret_val = FPGA_FAIL; - if (xilinx_validate (desc, (char *)__FUNCTION__)) { + if (xilinx_validate(desc, (char *)__func__)) { printf ("Family: \t"); switch (desc->family) { case xilinx_spartan2: @@ -293,7 +293,7 @@ int xilinx_info(xilinx_desc *desc) ret_val = FPGA_SUCCESS; } else { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); + printf("%s: Invalid device descriptor\n", __func__); } return ret_val; diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index 9bf887035d7..79ad6348de8 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -112,7 +112,7 @@ uint mii_send(uint mii_cmd) ep->eir = FEC_EIR_MII; /* clear MII complete */ #ifdef ET_DEBUG printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); + __FILE__, __LINE__, __func__, mii_cmd, mii_reply); #endif return (mii_reply & 0xffff); /* data read from phy */ diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 5b093623619..e203faed26b 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -404,7 +404,7 @@ static int rtl8169_init_board(unsigned long dev_iobase, const char *name) u32 tmp; #ifdef DEBUG_RTL8169 - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = dev_iobase; @@ -534,7 +534,7 @@ static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase, int length = 0; #ifdef DEBUG_RTL8169_RX - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = dev_iobase; @@ -608,7 +608,7 @@ static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase, #ifdef DEBUG_RTL8169_TX int stime = currticks(); - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); printf("sending %d bytes\n", len); #endif @@ -679,7 +679,7 @@ static void rtl8169_set_rx_mode(void) u32 tmp = 0; #ifdef DEBUG_RTL8169 - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif /* IFF_ALLMULTI */ @@ -701,7 +701,7 @@ static void rtl8169_hw_start(struct udevice *dev) #ifdef DEBUG_RTL8169 int stime = currticks(); - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif #if 0 @@ -771,7 +771,7 @@ static void rtl8169_init_ring(struct udevice *dev) #ifdef DEBUG_RTL8169 int stime = currticks(); - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif tpc->cur_rx = 0; @@ -810,7 +810,7 @@ static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr, #ifdef DEBUG_RTL8169 int stime = currticks(); - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = dev_iobase; @@ -851,7 +851,7 @@ static void rtl_halt_common(struct udevice *dev) int i; #ifdef DEBUG_RTL8169 - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = priv->iobase; @@ -906,7 +906,7 @@ static int rtl_init(unsigned long dev_ioaddr, const char *name, int option = -1, Cap10_100 = 0, Cap1000 = 0; #ifdef DEBUG_RTL8169 - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = dev_ioaddr; diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 7bfea9e0b31..b3734baf63e 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -66,7 +66,7 @@ static void m41t62_update_rtc_time(struct rtc_time *tm, u8 *buf) { debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", - __FUNCTION__, + __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); @@ -83,7 +83,7 @@ static void m41t62_update_rtc_time(struct rtc_time *tm, u8 *buf) debug("%s: tm is secs=%d, mins=%d, hours=%d, " "mday=%d, mon=%d, year=%d, wday=%d\n", - __FUNCTION__, + __func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); } diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 1d6711ccec4..3fcf9d53d59 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1750,7 +1750,7 @@ static int hc_reset(ohci_t *ohci) int timeout = 30; int smm_timeout = 50; /* 0,5 sec */ - dbg("%s\n", __FUNCTION__); + dbg("%s\n", __func__); #ifdef CONFIG_PCI_EHCI_DEVNO /* diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c index 7fd6639013a..c8c6bf0c84f 100644 --- a/drivers/usb/musb-new/omap2430.c +++ b/drivers/usb/musb-new/omap2430.c @@ -100,7 +100,7 @@ static int omap2430_musb_enable(struct musb *musb) #ifdef CONFIG_TWL4030_USB if (twl4030_usb_ulpi_init()) { serial_printf("ERROR: %s Could not initialize PHY\n", - __PRETTY_FUNCTION__); + __func__); } #endif return 0; diff --git a/examples/standalone/sched.c b/examples/standalone/sched.c index 64518c6890f..969628350d5 100644 --- a/examples/standalone/sched.c +++ b/examples/standalone/sched.c @@ -58,7 +58,7 @@ static uchar dbg = 0; #define PDEBUG(fmt, args...) { \ if(dbg != 0) { \ - printf("[%s %d %s]: ",__FILE__,__LINE__,__FUNCTION__);\ + printf("[%s %d %s]: ", __FILE__, __LINE__, __func__);\ printf(fmt, ##args); \ printf("\n"); \ } \ diff --git a/include/usbdevice.h b/include/usbdevice.h index d173c1c4e37..76fda5ff90b 100644 --- a/include/usbdevice.h +++ b/include/usbdevice.h @@ -22,19 +22,19 @@ #define MAX_URBS_QUEUED 5 #if 1 -#define usberr(fmt,args...) serial_printf("ERROR: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args) +#define usberr(fmt, args...) serial_printf("ERROR: %s(), %d: " fmt "\n", __func__, __LINE__, ##args) #else #define usberr(fmt,args...) do{}while(0) #endif #if 0 -#define usbdbg(fmt,args...) serial_printf("debug: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args) +#define usbdbg(fmt, args...) serial_printf("debug: %s(), %d: " fmt "\n", __func__, __LINE__, ##args) #else #define usbdbg(fmt,args...) do{}while(0) #endif #if 0 -#define usbinfo(fmt,args...) serial_printf("info: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args) +#define usbinfo(fmt, args...) serial_printf("info: %s(), %d: " fmt "\n", __func__, __LINE__, ##args) #else #define usbinfo(fmt,args...) do{}while(0) #endif -- cgit v1.3.1 From 3f1821162638acc34b47b6c68f3bc8bab365c08d Mon Sep 17 00:00:00 2001 From: Siu Ming Tong Date: Wed, 27 May 2026 19:38:37 -0700 Subject: grm: axiado: Add AX3005 based SCM3005 board support Introduce mach-axiado to support Axiado SoC-based boards. This adds the platform Kconfig and build infrastructure, along with initial SCM3005 board support using the AX3005 SoC. Introduces AXIADO_AX3005, which selects ARM64, driver model, GIC-v3, and Zynq UART. TARGET_SCM3005 selects ARCH_AXIADO, allowing future SoC variants to share the platform configuration. Secondary cores use spin-table boot. ft_board_setup() corrects the cpu-release-addr in the FDT, which arch_fixup_fdt() overwrites with the post-relocation address. Add U-Boot board support for the Axiado AX3005 based targets, a quad-core ARM Cortex-A53 (ARMv8) platform. Tested-by: Siu Ming Tong Signed-off-by: Karthikeyan Mitran Signed-off-by: Siu Ming Tong --- MAINTAINERS | 11 +++ arch/arm/Kconfig | 9 +++ arch/arm/mach-axiado/Kconfig | 22 ++++++ arch/arm/mach-axiado/Makefile | 6 ++ arch/arm/mach-axiado/scm3005/Kconfig | 11 +++ board/axiado/scm3005/Kconfig | 15 ++++ board/axiado/scm3005/Makefile | 5 ++ board/axiado/scm3005/scm3005.c | 128 +++++++++++++++++++++++++++++++++++ configs/ax3005_scm3005_defconfig | 74 ++++++++++++++++++++ include/configs/ax3005-scm3005.h | 29 ++++++++ 10 files changed, 310 insertions(+) create mode 100644 arch/arm/mach-axiado/Kconfig create mode 100644 arch/arm/mach-axiado/Makefile create mode 100644 arch/arm/mach-axiado/scm3005/Kconfig create mode 100644 board/axiado/scm3005/Kconfig create mode 100644 board/axiado/scm3005/Makefile create mode 100644 board/axiado/scm3005/scm3005.c create mode 100644 configs/ax3005_scm3005_defconfig create mode 100644 include/configs/ax3005-scm3005.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 056902f6ef2..0659d299fde 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -213,6 +213,17 @@ F: drivers/reset/reset-ast2500.c F: drivers/watchdog/ast_wdt.c N: aspeed +ARM AXIADO AX3005 SCM3005 +M: Siu Ming Tong +M: Karthikeyan Mitran +M: Prasad Bolisetty +S: Maintained +F: arch/arm/dts/ax3005* +F: arch/arm/mach-axiado/ +F: board/axiado/scm3005/ +F: configs/ax3005_scm3005_defconfig +F: include/configs/ax3005-scm3005.h + ARM BROADCOM BCM283X / BCM27XX M: Matthias Brugger M: Peter Robinson diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f624675eadf..3fcedee739f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2152,6 +2152,13 @@ config ARCH_ASPEED select OF_CONTROL imply CMD_DM +config ARCH_AXIADO + bool "Support Axiado SoCs" + select AXIADO_AX3005 + help + Support for Axiado AX-series SoCs such as the AX3005. + These ARM64 SoCs are used in BMC and security applications. + config TARGET_DURIAN bool "Support Phytium Durian Platform" select ARM64 @@ -2293,6 +2300,8 @@ source "arch/arm/mach-aspeed/Kconfig" source "arch/arm/mach-at91/Kconfig" +source "arch/arm/mach-axiado/Kconfig" + source "arch/arm/mach-bcm283x/Kconfig" source "arch/arm/mach-bcmbca/Kconfig" diff --git a/arch/arm/mach-axiado/Kconfig b/arch/arm/mach-axiado/Kconfig new file mode 100644 index 00000000000..12ad44070eb --- /dev/null +++ b/arch/arm/mach-axiado/Kconfig @@ -0,0 +1,22 @@ +if ARCH_AXIADO + +config SYS_ARCH + default "arm" + +config SYS_SOC + default "axiado" + +config AXIADO_AX3005 + bool + select ARM64 + select ARMV8_SWITCH_TO_EL1 + select DM + select DM_SERIAL + select GICV3 + select ZYNQ_SERIAL + select MMC_SDHCI_AXIADO + select PHY_AXIADO_EMMC + +source "arch/arm/mach-axiado/scm3005/Kconfig" + +endif diff --git a/arch/arm/mach-axiado/Makefile b/arch/arm/mach-axiado/Makefile new file mode 100644 index 00000000000..2acd5466dd9 --- /dev/null +++ b/arch/arm/mach-axiado/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2021-2026 Axiado Corporation (or its affiliates). +# + +obj-$(CONFIG_AXIADO_AX3005) += scm3005/ diff --git a/arch/arm/mach-axiado/scm3005/Kconfig b/arch/arm/mach-axiado/scm3005/Kconfig new file mode 100644 index 00000000000..fc74aa0871b --- /dev/null +++ b/arch/arm/mach-axiado/scm3005/Kconfig @@ -0,0 +1,11 @@ +if AXIADO_AX3005 + +config TARGET_SCM3005 + bool "Support Axiado AX3005 SCM3005" + help + Support for the Axiado AX3005 SCM3005 board. + Based on the Axiado AX3005 quad-core ARMv8 Cortex-A53 SoC. + +source "board/axiado/scm3005/Kconfig" + +endif diff --git a/board/axiado/scm3005/Kconfig b/board/axiado/scm3005/Kconfig new file mode 100644 index 00000000000..d6f4f311f55 --- /dev/null +++ b/board/axiado/scm3005/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SCM3005 + +config SYS_BOARD + string + default "scm3005" + +config SYS_VENDOR + string + default "axiado" + +config SYS_CONFIG_NAME + string + default "ax3005-scm3005" + +endif diff --git a/board/axiado/scm3005/Makefile b/board/axiado/scm3005/Makefile new file mode 100644 index 00000000000..3d35713bab9 --- /dev/null +++ b/board/axiado/scm3005/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2021-2026 Axiado Corporation (or its affiliates). + +obj-y := scm3005.o diff --git a/board/axiado/scm3005/scm3005.c b/board/axiado/scm3005/scm3005.c new file mode 100644 index 00000000000..4643ba4a55c --- /dev/null +++ b/board/axiado/scm3005/scm3005.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates). + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct mm_region axiado_ax3005_mem_map[] = { + { /* Peripherals including UART */ + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x4A000000UL, /* 0 to 0x4A000000: peripherals */ + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + { .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, + { + 0, + } +}; + +struct mm_region *mem_map = axiado_ax3005_mem_map; + +/* + * Accept any FIT configuration name - the board loads a single FIT image + * and the first matching config is used. + */ +int board_fit_config_name_match(const char *name) +{ + return 0; +} + +/* + * ft_board_setup - restore cpu-release-addr after relocation + * + * arch_fixup_fdt() / spin_table_update_dt() overwrites cpu-release-addr + * with U-Boot's relocated address. Restore the pre-relocation physical + * address so secondary cores spin on the correct location. + */ +int ft_board_setup(void *blob, struct bd_info *bd) +{ + int cpus_offset, offset; + const char *prop; + int ret; + u64 cpu_release_addr = (u64)&spin_table_cpu_release_addr - gd->reloc_off; + + cpus_offset = fdt_path_offset(blob, "/cpus"); + if (cpus_offset < 0) + return 0; + + for (offset = fdt_first_subnode(blob, cpus_offset); offset >= 0; + offset = fdt_next_subnode(blob, offset)) { + prop = fdt_getprop(blob, offset, "device_type", NULL); + if (!prop || strcmp(prop, "cpu")) + continue; + + prop = fdt_getprop(blob, offset, "enable-method", NULL); + if (!prop || strcmp(prop, "spin-table")) + continue; + + ret = fdt_setprop_u64(blob, offset, "cpu-release-addr", + cpu_release_addr); + if (ret) { + printf("WARNING: Failed to restore cpu-release-addr\n"); + return ret; + } + } + + return 0; +} + +/* + * dram_init - DDR is initialized by firmware, just setting size + */ +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); + return 0; +} + +/* + * the SOC uses single bank, non-interleaving + */ +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + return 0; +} + +/* + * timer_init - enable the AX3005 platform system timer + * + * CNTFRQ_EL0 is already set by arch/arm/cpu/armv8/start.S using + * CONFIG_COUNTER_FREQUENCY from the defconfig. + * + * SYS_TIMER_CTRL (0x48016000) is the AX3005 system timer control + * register — writing SYS_TIMER_ENABLE starts the counter that feeds + * the ARM generic timer. + */ +int timer_init(void) +{ + writel(SYS_TIMER_ENABLE, SYS_TIMER_CTRL); + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + /* For later ARM_PSCI_FW or watchdog reset */ +} diff --git a/configs/ax3005_scm3005_defconfig b/configs/ax3005_scm3005_defconfig new file mode 100644 index 00000000000..5dd72d87220 --- /dev/null +++ b/configs/ax3005_scm3005_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_AXIADO=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_TEXT_BASE=0x80000000 +CONFIG_SYS_MONITOR_BASE=0x80000000 +CONFIG_SYS_LOAD_ADDR=0x80100000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SYS_MALLOC_LEN=0x20000 +CONFIG_SYS_BOOTM_LEN=0x20000000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x5000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_COUNTER_FREQUENCY=1000000000 +CONFIG_ARMV8_MULTIENTRY=y +CONFIG_ARMV8_SET_SMPEN=y +CONFIG_ARMV8_SPIN_TABLE=y +CONFIG_SYS_CUSTOM_LDSCRIPT=y +CONFIG_SYS_LDSCRIPT="arch/arm/cpu/armv8/u-boot.lds" +CONFIG_BOOTDELAY=5 +CONFIG_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="ax3005-scm3005.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Axiado> " +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press \"\" to stop autobooting in %d seconds\n" +CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyPS3,115200 maxcpus=4 nr_cpus=4 earlycon hugepages=16 root=/dev/ram rw phram.phram=ramrofs,0x80B00000,0x6400000" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="bootm ${loadaddr}" +CONFIG_SYS_VENDOR="axiado" +CONFIG_SYS_BOARD="scm3005" +CONFIG_SYS_CONFIG_NAME="ax3005-scm3005" +# CONFIG_CMD_BOOTEFI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_GO is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="ax3005-scm3005" +CONFIG_MULTI_DTB_FIT=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_DM_MMC=y +# CONFIG_SUPPORT_EMMC_BOOT is not set +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_TARGET_SCM3005=y +CONFIG_CLK=y +CONFIG_LZMA=y +CONFIG_XZ=y +CONFIG_ZYNQ_SERIAL=y +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +# CONFIG_TOOLS_MKEFICAPSULE is not set diff --git a/include/configs/ax3005-scm3005.h b/include/configs/ax3005-scm3005.h new file mode 100644 index 00000000000..4eead2910c8 --- /dev/null +++ b/include/configs/ax3005-scm3005.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates). + */ + +#ifndef __AX3005_SCM3005_H +#define __AX3005_SCM3005_H + +#include + +#define GICD_BASE 0x40400000 +#define GICR_BASE 0x40500000 + +#define SYS_TIMER_CTRL 0x48016000 +#define SYS_TIMER_ENABLE 0x1 +#define SYS_TIMER_DISABLE 0x0 + +/* DRAM: 2 GB at 0x80000000 */ +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_SIZE SZ_2G +#define CFG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + SZ_1M) + +#define CFG_SYS_MAXARGS 64 +#define CFG_SYS_BARGSIZE CFG_SYS_CBSIZE + +#define CFG_SYS_BAUDRATE_TABLE \ + { 4800, 9600, 19200, 38400, 57600, 115200 } + +#endif /* __AX3005_SCM3005_H */ -- cgit v1.3.1 From b941dc47398b93aea37b9139d6816610ad78352f Mon Sep 17 00:00:00 2001 From: "Markus Schneider-Pargmann (TI)" Date: Mon, 1 Jun 2026 11:30:38 +0200 Subject: include: configs: am335x_evm: Enable vidconsole Enable vidconsole for the am335x-evm board. Reviewed-by: Kory Maincent Signed-off-by: Markus Schneider-Pargmann (TI) --- include/configs/am335x_evm.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index d2164b41d6d..babf065bc3e 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -83,6 +83,8 @@ "fdtfile=undefined\0" \ "finduuid=part uuid mmc 0:2 uuid\0" \ "console=ttyO0,115200n8\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ "partitions=" \ "uuid_disk=${uuid_gpt_disk};" \ "name=bootloader,start=384K,size=1792K," \ -- cgit v1.3.1 From 623f6c5b6ab7fa270a9e36db0c6136c5983a45a0 Mon Sep 17 00:00:00 2001 From: Randolph Sapp Date: Thu, 4 Jun 2026 10:50:35 -0500 Subject: boot: image-fdt: free old dtb reservations Add a free flag and an initial call to free allocations covered by the global FDT. This assumes that all calls to boot_fdt_add_mem_rsv_regions occur before the transition to the new device tree, thus we can access the currently active device tree through the global data pointer. This allows us to clearly indicate to the user when a device tree reservation fails. How we handle this can still use some improvement. Right now we'll keep the default behavior and try to boot anyway. Fixes: 5a6aa7d5913 ("boot: fdt: Handle already reserved memory in boot_fdt_reserve_region()") Signed-off-by: Randolph Sapp Acked-by: Ilias Apalodimas Reviewed-by: Simon Glass Fixes: tag with a 12-char hash: Fixes: 5a6aa7d59133 ("boot: fdt: Handle already reserved memory in --- boot/image-fdt.c | 77 +++++++++++++++++++++++++++++++++++++++++--------------- include/image.h | 2 +- 2 files changed, 58 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/boot/image-fdt.c b/boot/image-fdt.c index a3a4fb8b558..1150131a11e 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -69,35 +69,50 @@ static const struct legacy_img_hdr *image_get_fdt(ulong fdt_addr) } #endif -static void boot_fdt_reserve_region(u64 addr, u64 size, u32 flags) +/** + * boot_fdt_handle_region - Reserve or free a given FDT region in LMB + * @addr: Reservation base address + * @size: Reservation size + * @flags: Reservation flags + * @free: Indicate if region is being freed or allocated + * + * Add or free a given reservation from LMB. This reports to the user if any + * errors occurred during either operation. + */ +static void boot_fdt_handle_region(u64 addr, u64 size, u32 flags, bool free) { long ret; phys_addr_t rsv_addr; rsv_addr = (phys_addr_t)addr; - ret = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &rsv_addr, size, flags); + if (free) + ret = lmb_free(rsv_addr, size, flags); + else + ret = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &rsv_addr, size, + flags); + if (!ret) { - debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n", - (unsigned long long)addr, + debug(" %s fdt memory region: addr=%llx size=%llx flags=%x\n", + free ? "freed" : "reserved", (unsigned long long)addr, (unsigned long long)size, flags); - } else if (ret != -EEXIST && ret != -EINVAL) { - puts("ERROR: reserving fdt memory region failed "); - printf("(addr=%llx size=%llx flags=%x)\n", - (unsigned long long)addr, - (unsigned long long)size, flags); + } else { + printf("ERROR: %s fdt memory region failed (addr=%llx size=%llx flags=%x): %ld\n", + free ? "freeing" : "reserving", (unsigned long long)addr, + (unsigned long long)size, flags, ret); } } /** - * boot_fdt_add_mem_rsv_regions - Mark the memreserve and reserved-memory - * sections as unusable + * boot_fdt_handle_mem_rsv_regions - Handle FDT memreserve and reserved-memory + * sections * @fdt_blob: pointer to fdt blob base address + * @free: indicate if regions are being freed * - * Adds the and reserved-memorymemreserve regions in the dtb to the lmb block. - * Adding the memreserve regions prevents u-boot from using them to store the - * initrd or the fdt blob. + * Adds or removes reserved-memory and memreserve regions in the dtb to the lmb + * block. Adding the memreserve regions prevents u-boot from using them to store + * the initrd or the fdt blob. */ -void boot_fdt_add_mem_rsv_regions(void *fdt_blob) +static void boot_fdt_handle_mem_rsv_regions(const void *fdt_blob, bool free) { uint64_t addr, size; int i, total, ret; @@ -105,15 +120,12 @@ void boot_fdt_add_mem_rsv_regions(void *fdt_blob) struct fdt_resource res; u32 flags; - if (fdt_check_header(fdt_blob) != 0) - return; - /* process memreserve sections */ total = fdt_num_mem_rsv(fdt_blob); for (i = 0; i < total; i++) { if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0) continue; - boot_fdt_reserve_region(addr, size, LMB_NOOVERWRITE); + boot_fdt_handle_region(addr, size, LMB_NOOVERWRITE, free); } /* process reserved-memory */ @@ -131,7 +143,7 @@ void boot_fdt_add_mem_rsv_regions(void *fdt_blob) flags = LMB_NOMAP; addr = res.start; size = res.end - res.start + 1; - boot_fdt_reserve_region(addr, size, flags); + boot_fdt_handle_region(addr, size, flags, free); } subnode = fdt_next_subnode(fdt_blob, subnode); @@ -139,6 +151,31 @@ void boot_fdt_add_mem_rsv_regions(void *fdt_blob) } } +/** + * boot_fdt_add_mem_rsv_regions - Add FDT memreserve and reserved-memory + * sections + * @fdt_blob: pointer to fdt blob base address + * + * Adds reserved-memory and memreserve regions in the dtb to the lmb block. + * Adding the memreserve regions prevents u-boot from using them to store the + * initrd or the fdt blob. + * + * This function will attempt to clean the currently active reservations if a + * new device tree blob is given. This must be called before gd->fdt_blob is + * switched. + */ +void boot_fdt_add_mem_rsv_regions(const void *fdt_blob) +{ + if (fdt_check_header(fdt_blob) != 0) + return; + + /* Remove old regions */ + if (gd->fdt_blob != fdt_blob) + boot_fdt_handle_mem_rsv_regions(gd->fdt_blob, true); + + boot_fdt_handle_mem_rsv_regions(fdt_blob, false); +} + /** * boot_relocate_fdt - relocate flat device tree * @of_flat_tree: pointer to a char* variable, will hold fdt start address diff --git a/include/image.h b/include/image.h index 34efac6056d..151619f42bf 100644 --- a/include/image.h +++ b/include/image.h @@ -827,7 +827,7 @@ int boot_get_fdt(void *buf, const char *select, uint arch, struct bootm_headers *images, char **of_flat_tree, ulong *of_size); -void boot_fdt_add_mem_rsv_regions(void *fdt_blob); +void boot_fdt_add_mem_rsv_regions(const void *fdt_blob); int boot_relocate_fdt(char **of_flat_tree, ulong *of_size); int boot_ramdisk_high(ulong rd_data, ulong rd_len, ulong *initrd_start, -- cgit v1.3.1 From 48412f8f2962e27abe3b9a4a73221cebbfd73333 Mon Sep 17 00:00:00 2001 From: Randolph Sapp Date: Thu, 4 Jun 2026 10:50:38 -0500 Subject: memory: reserve from start_addr_sp to initial_relocaddr Add a new global data struct member called initial_relocaddr. This stores the original value of relocaddr, directly from setup_dest_addr. This is specifically to avoid any adjustments made by other init functions. Reserve the memory from gd->start_addr_sp - CONFIG_STACK_SIZE to gd->initial_relocaddr instead of gd->ram_top. This allows platform specific relocation addresses to work without unnecessarily painting over a large range. Signed-off-by: Randolph Sapp Reviewed-by: Simon Glass Reviewed-by: Ilias Apalodimas --- common/board_f.c | 9 ++++++++- include/asm-generic/global_data.h | 9 +++++++++ lib/efi_loader/efi_memory.c | 2 +- lib/lmb.c | 7 ++++--- 4 files changed, 22 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/common/board_f.c b/common/board_f.c index ce87c619e68..aeb53b4c274 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -330,6 +330,8 @@ __weak int arch_setup_dest_addr(void) static int setup_dest_addr(void) { + int ret; + debug("Monitor len: %08x\n", gd->mon_len); /* * Ram is setup, size stored in gd !! @@ -356,7 +358,12 @@ static int setup_dest_addr(void) gd->relocaddr = gd->ram_top; debug("Ram top: %08llX\n", (unsigned long long)gd->ram_top); - return arch_setup_dest_addr(); + ret = arch_setup_dest_addr(); + if (ret) + return ret; + + gd->initial_relocaddr = gd->relocaddr; + return 0; } #ifdef CFG_PRAM diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 745d2c3a966..8d1d49b1133 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -107,6 +107,15 @@ struct global_data { * GDB using the 'add-symbol-file u-boot ' command. */ unsigned long relocaddr; + /** + * @initial_relocaddr: top address of U-Boot in RAM + * + * This should be the value of relocaddr after setup_dest_addr() and + * before reserve_pram() or any other allocations or reservations shift + * it. This address will, depending on the platform, be equivalent to + * ram_top and should also be considered an exclusive address. + */ + unsigned long initial_relocaddr; /** * @irq_sp: IRQ stack pointer */ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 2feb29f0a2c..c3da7c20cb2 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -871,7 +871,7 @@ static void add_u_boot_and_runtime(void) /* Add U-Boot */ uboot_start = ((uintptr_t)map_sysmem(gd->start_addr_sp, 0) - uboot_stack_size) & ~EFI_PAGE_MASK; - uboot_pages = ((uintptr_t)map_sysmem(gd->ram_top - 1, 0) - + uboot_pages = ((uintptr_t)map_sysmem(gd->initial_relocaddr - 1, 0) - uboot_start + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; efi_update_memory_map(uboot_start, uboot_pages, EFI_BOOT_SERVICES_CODE, false, false); diff --git a/lib/lmb.c b/lib/lmb.c index 8f12c6ad8e5..27c8565e590 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -540,13 +540,14 @@ static void lmb_reserve_uboot_region(void) ulong pram = 0; rsv_start = gd->start_addr_sp - CONFIG_STACK_SIZE; - end = gd->ram_top; + end = gd->initial_relocaddr; /* * Reserve memory from aligned address below the bottom of U-Boot stack - * until end of RAM area to prevent LMB from overwriting that memory. + * until the original relocation address to prevent LMB from + * overwriting that memory. */ - debug("## Current stack ends at 0x%08lx ", (ulong)rsv_start); + debug("## Current stack ends at 0x%08lx\n", (ulong)rsv_start); #ifdef CFG_PRAM pram = env_get_ulong("pram", 10, CFG_PRAM); -- cgit v1.3.1 From 196b1fe9bf80959648cf54b2e36c08dfd24fc1ad Mon Sep 17 00:00:00 2001 From: Bastien Curutchet Date: Mon, 8 Jun 2026 15:12:00 +0200 Subject: configs: omap4: remove unused boot target devices This include file isn't used since the omap4 support has been dropped. Since this support is about to be reintroduced, this file is going to be used again. The upcoming support is minimal and doesn't include network, therefore leaving PXE and DHCP in the BOOT_TARGET_DEVICES list would lead to build errors. Remove PXE and DHCP from the list of BOOT_TARGET_DEVICES. Remove the LEGACY_MMC macros and the findfdt script that looks for no-longer supported boards. Remove the empty #ifdef XPL_BUILD Signed-off-by: Bastien Curutchet --- include/configs/ti_omap4_common.h | 40 --------------------------------------- 1 file changed, 40 deletions(-) (limited to 'include') diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 7a333090b18..e4b84719c86 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -35,25 +35,9 @@ /* * Environment setup */ -#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=" \ - "setenv mmcdev " #instance"; "\ - "setenv bootpart " #instance":2 ; "\ - "run mmcboot\0" - -#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ - #devtypel #instance " " - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(LEGACY_MMC, legacy_mmc, 0) \ func(MMC, mmc, 1) \ - func(LEGACY_MMC, legacy_mmc, 1) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) #include #include @@ -73,30 +57,6 @@ "uimageboot=echo Booting from mmc${mmcdev} ...; " \ "run args_mmc; " \ "bootm ${loadaddr}\0" \ - "findfdt="\ - "if test $board_name = sdp4430; then " \ - "setenv fdtfile omap4-sdp.dtb; fi; " \ - "if test $board_name = panda; then " \ - "setenv fdtfile omap4-panda.dtb; fi;" \ - "if test $board_name = panda-a4; then " \ - "setenv fdtfile omap4-panda-a4.dtb; fi;" \ - "if test $board_name = panda-es; then " \ - "setenv fdtfile omap4-panda-es.dtb; fi;" \ - "if test $board_name = duovero; then " \ - "setenv fdtfile omap4-duovero-parlor.dtb; fi;" \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" \ BOOTENV -/* - * Defines for SPL - * It is known that this will break HS devices. Since the current size of - * SPL is overlapped with public stack and breaking non HS devices to boot. - * So moving TEXT_BASE down to non-HS limit. - */ - -#ifdef CONFIG_XPL_BUILD -/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ -#endif - #endif /* __CONFIG_TI_OMAP4_COMMON_H */ -- cgit v1.3.1 From 157186fbfc24c54117b41e292a35809a0560b9c0 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 5 Jun 2026 15:44:46 +0200 Subject: global_data: fix type for gd_malloc_ptr() With commit 92aa3ec321b5 ("global_data: Reduce size of early-malloc vars") the type changes from (unsigned) long to int. But the type for default if SYS_MALLOC_F_LEN is unset was not changed. Remove the suffix. Fixes the warning: common/spl/spl.c:800:23: warning: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'long int' [-Wformat=] Fixes: 92aa3ec321b5 ("global_data: Reduce size of early-malloc vars") Signed-off-by: Alexander Stein Reviewed-by: Simon Glass --- include/asm-generic/global_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 8d1d49b1133..ba6a10cf2ad 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -547,7 +547,7 @@ static_assert(sizeof(struct global_data) == GD_SIZE); #if CONFIG_VAL(SYS_MALLOC_F_LEN) #define gd_malloc_ptr() gd->malloc_ptr #else -#define gd_malloc_ptr() 0L +#define gd_malloc_ptr() 0 #endif #if CONFIG_IS_ENABLED(UPL) -- cgit v1.3.1 From 1174c99ab421168221be372bd83a4143bf5f167d Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Wed, 17 Jun 2026 10:48:19 +0300 Subject: treewide: move bi_dram[] from bd to gd Currently, the bi_dram[] information is stored in the board info structure (bd). Because bd is only valid after reserve_board(), dram_init_banksize() must be called late in the initialization process. This limitation is problematic, as it forces us to rely on a variety of bespoke functions to determine board RAM, bank memory sizes, and other early setup requirements. By moving bi_dram[] into the global data (gd), we can run it earlier. This is particularly convenient since boards define their own dram_init_banksize() routines, which do not always rely on parsing Device Tree (DT) memory nodes. Additionally, U-Boot defaults to relocating to the top of the first memory bank. While boards currently use custom functions to override this behavior, having the DRAM bank information available earlier in gd makes relocating to a different bank trivial and standardizes the process. Reviewed-by: Anshul Dalal Tested-by: Michal Simek # Versal Gen 2 Vek385 Tested-by: Anshul Dalal Reviewed-by: Simon Glass Signed-off-by: Ilias Apalodimas Tested-by: Christophe Leroy (CS GROUP) --- api/api_platform.c | 4 +- arch/arm/cpu/armv8/cache_v8.c | 6 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 118 ++++++++++----------- arch/arm/lib/bootm-fdt.c | 5 +- arch/arm/lib/bootm.c | 4 +- arch/arm/lib/cache-cp15.c | 9 +- arch/arm/lib/image.c | 2 +- arch/arm/mach-airoha/an7581/init.c | 8 +- arch/arm/mach-apple/board.c | 4 +- arch/arm/mach-davinci/misc.c | 4 +- arch/arm/mach-imx/ele_ahab.c | 7 +- arch/arm/mach-imx/imx8/ahab.c | 7 +- arch/arm/mach-imx/imx8/cpu.c | 44 ++++---- arch/arm/mach-imx/imx8m/soc.c | 24 ++--- arch/arm/mach-imx/imx8ulp/soc.c | 20 ++-- arch/arm/mach-imx/imx9/scmi/soc.c | 24 ++--- arch/arm/mach-imx/imx9/soc.c | 24 ++--- arch/arm/mach-imx/mx5/mx53_dram.c | 8 +- arch/arm/mach-imx/spl.c | 4 +- arch/arm/mach-k3/k3-ddr.c | 4 +- arch/arm/mach-mvebu/alleycat5/cpu.c | 4 +- arch/arm/mach-mvebu/armada3700/cpu.c | 10 +- arch/arm/mach-mvebu/armada8k/dram.c | 10 +- arch/arm/mach-mvebu/dram.c | 6 +- arch/arm/mach-omap2/am33xx/board.c | 4 +- arch/arm/mach-omap2/omap-cache.c | 5 +- arch/arm/mach-omap2/omap3/emif4.c | 8 +- arch/arm/mach-omap2/omap3/sdrc.c | 8 +- arch/arm/mach-owl/soc.c | 4 +- arch/arm/mach-renesas/memmap-gen3.c | 8 +- arch/arm/mach-renesas/memmap-rzg2l.c | 4 +- arch/arm/mach-rockchip/rk3588/rk3588.c | 8 +- arch/arm/mach-rockchip/sdram.c | 42 ++++---- arch/arm/mach-snapdragon/board.c | 16 +-- arch/arm/mach-socfpga/board.c | 5 +- arch/arm/mach-socfpga/misc_arria10.c | 7 +- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 4 +- arch/arm/mach-stm32mp/stm32mp1/cpu.c | 7 +- arch/arm/mach-tegra/board2.c | 14 +-- arch/arm/mach-tegra/cboot.c | 4 +- arch/arm/mach-uniphier/dram_init.c | 6 +- arch/arm/mach-uniphier/fdt-fixup.c | 8 +- arch/arm/mach-versal-net/cpu.c | 8 +- arch/arm/mach-versal/cpu.c | 16 +-- arch/arm/mach-versal2/cpu.c | 7 +- arch/arm/mach-zynqmp/cpu.c | 8 +- arch/mips/mach-octeon/dram.c | 4 +- arch/riscv/cpu/k1/dram.c | 12 +-- arch/sandbox/cpu/spl.c | 4 +- arch/x86/cpu/coreboot/sdram.c | 4 +- arch/x86/cpu/efi/payload.c | 4 +- arch/x86/cpu/efi/sdram.c | 4 +- arch/x86/cpu/intel_common/mrc.c | 4 +- arch/x86/cpu/ivybridge/sdram_nop.c | 4 +- arch/x86/cpu/qemu/dram.c | 8 +- arch/x86/cpu/quark/dram.c | 4 +- arch/x86/cpu/slimbootloader/sdram.c | 4 +- arch/x86/cpu/tangier/sdram.c | 4 +- arch/x86/lib/bootm.c | 5 +- arch/x86/lib/fsp/fsp_dram.c | 18 ++-- board/CZ.NIC/turris_1x/turris_1x.c | 42 ++++---- board/armltd/corstone1000/corstone1000.c | 4 +- board/armltd/integrator/integrator.c | 4 +- board/armltd/total_compute/total_compute.c | 6 +- board/armltd/vexpress/vexpress_common.c | 8 +- board/atmel/common/video_display.c | 2 +- board/atmel/sam9x60_curiosity/sam9x60_curiosity.c | 2 +- board/atmel/sam9x75_curiosity/sam9x75_curiosity.c | 2 +- board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c | 2 +- .../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 2 +- .../atmel/sama5d29_curiosity/sama5d29_curiosity.c | 2 +- board/atmel/sama5d2_xplained/sama5d2_xplained.c | 2 +- .../atmel/sama7d65_curiosity/sama7d65_curiosity.c | 2 +- .../atmel/sama7g54_curiosity/sama7g54_curiosity.c | 2 +- board/axiado/scm3005/scm3005.c | 4 +- board/broadcom/bcmns3/ns3.c | 4 +- board/compulab/cm_fx6/cm_fx6.c | 28 ++--- board/elgin/elgin_rv1108/elgin_rv1108.c | 4 +- board/esd/meesc/meesc.c | 4 +- board/friendlyarm/nanopi2/board.c | 10 +- board/ge/mx53ppd/mx53ppd.c | 8 +- board/hisilicon/hikey/hikey.c | 24 ++--- board/hisilicon/hikey960/hikey960.c | 4 +- board/hisilicon/poplar/poplar.c | 4 +- board/k+p/kp_imx53/kp_imx53.c | 4 +- board/keymile/pg-wcom-ls102xa/ddr.c | 4 +- board/kontron/sl28/sl28.c | 4 +- board/kontron/sl28/spl_atf.c | 6 +- board/liebherr/btt/btt.c | 2 +- board/menlo/m53menlo/m53menlo.c | 8 +- board/nuvoton/arbel_evb/arbel_evb.c | 26 ++--- board/nxp/imxrt1020-evk/imxrt1020-evk.c | 2 +- board/nxp/imxrt1050-evk/imxrt1050-evk.c | 2 +- board/nxp/imxrt1170-evk/imxrt1170-evk.c | 2 +- board/nxp/ls1021aqds/ddr.c | 4 +- board/nxp/ls1028a/ls1028a.c | 10 +- board/nxp/ls1043aqds/ls1043aqds.c | 8 +- board/nxp/ls1043ardb/ls1043ardb.c | 8 +- board/nxp/ls1046afrwy/ls1046afrwy.c | 8 +- board/nxp/ls1046aqds/ls1046aqds.c | 8 +- board/nxp/ls1046ardb/ls1046ardb.c | 8 +- board/nxp/ls1088a/ls1088a.c | 6 +- board/nxp/ls2080aqds/ls2080aqds.c | 14 +-- board/nxp/ls2080ardb/ls2080ardb.c | 14 +-- board/nxp/lx2160a/lx2160a.c | 6 +- board/phytec/phycore_am62x/phycore-am62x.c | 26 ++--- board/phytec/phycore_am64x/phycore-am64x.c | 18 ++-- board/phytium/durian/durian.c | 4 +- board/phytium/pe2201/pe2201.c | 4 +- board/raspberrypi/rpi/rpi.c | 4 +- board/renesas/common/rcar64-common.c | 6 +- board/renesas/genmai/genmai.c | 4 +- board/renesas/sparrowhawk/sparrowhawk.c | 8 +- board/ronetix/pm9261/pm9261.c | 4 +- board/ronetix/pm9263/pm9263.c | 4 +- board/ronetix/pm9g45/pm9g45.c | 4 +- board/samsung/arndale/arndale.c | 4 +- board/samsung/common/board.c | 6 +- board/samsung/exynos-mobile/exynos-mobile.c | 4 +- board/samsung/goni/goni.c | 12 +-- board/samsung/smdkc100/smdkc100.c | 4 +- board/samsung/smdkv310/smdkv310.c | 16 +-- board/siemens/iot2050/board.c | 16 +-- board/socionext/developerbox/developerbox.c | 6 +- board/st/stih410-b2260/board.c | 4 +- board/ste/stemmy/stemmy.c | 4 +- board/ti/dra7xx/evm.c | 8 +- board/ti/ks2_evm/board.c | 4 +- board/toradex/colibri_imx7/colibri_imx7.c | 8 +- board/toradex/verdin-am62/verdin-am62.c | 2 +- board/toradex/verdin-am62p/verdin-am62p.c | 2 +- board/traverse/ten64/ten64.c | 6 +- board/xilinx/zynq/cmds.c | 6 +- board/xilinx/zynqmp/zynqmp.c | 4 +- boot/image-board.c | 2 +- boot/image-fdt.c | 4 +- cmd/bdinfo.c | 12 +-- cmd/ti/ddr4.c | 8 +- cmd/ufetch.c | 4 +- common/board_f.c | 10 +- common/init/handoff.c | 10 +- drivers/bootcount/bootcount_ram.c | 4 +- drivers/ddr/altera/sdram_agilex.c | 4 +- drivers/ddr/altera/sdram_agilex5.c | 18 ++-- drivers/ddr/altera/sdram_agilex7m.c | 4 +- drivers/ddr/altera/sdram_arria10.c | 12 +-- drivers/ddr/altera/sdram_n5x.c | 4 +- drivers/ddr/altera/sdram_s10.c | 4 +- drivers/ddr/altera/sdram_soc64.c | 28 ++--- drivers/mmc/mvebu_mmc.c | 4 +- drivers/net/mvgbe.c | 4 +- drivers/pci/pci-uclass.c | 8 +- drivers/usb/host/ehci-marvell.c | 4 +- drivers/video/meson/meson_vpu.c | 8 +- drivers/video/sunxi/sunxi_de2.c | 2 +- drivers/video/sunxi/sunxi_display.c | 2 +- include/asm-generic/global_data.h | 7 ++ include/asm-generic/u-boot.h | 4 - include/configs/m53menlo.h | 4 +- include/configs/mx53cx9020.h | 4 +- include/configs/mx53loco.h | 4 +- include/configs/mx53ppd.h | 4 +- include/fdtdec.h | 7 +- include/init.h | 2 +- lib/fdtdec.c | 23 ++-- lib/lmb.c | 19 ++-- test/cmd/bdinfo.c | 7 +- 167 files changed, 707 insertions(+), 714 deletions(-) (limited to 'include') diff --git a/api/api_platform.c b/api/api_platform.c index d5cbcd6e201..d4edf3a20fe 100644 --- a/api/api_platform.c +++ b/api/api_platform.c @@ -21,8 +21,8 @@ int platform_sys_info(struct sys_info *si) si->clk_cpu = gd->cpu_clk; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - platform_set_mr(si, gd->bd->bi_dram[i].start, - gd->bd->bi_dram[i].size, MR_ATTR_DRAM); + platform_set_mr(si, gd->dram[i].start, + gd->dram[i].size, MR_ATTR_DRAM); platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM); platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH); diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 6c85022556a..e59528e576e 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -69,9 +69,9 @@ int mem_map_from_dram_banks(unsigned int index, unsigned int len, u64 attrs) } for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - mem_map[index].virt = gd->bd->bi_dram[i].start; - mem_map[index].phys = gd->bd->bi_dram[i].start; - mem_map[index].size = gd->bd->bi_dram[i].size; + mem_map[index].virt = gd->dram[i].start; + mem_map[index].phys = gd->dram[i].start; + mem_map[index].size = gd->dram[i].size; mem_map[index].attrs = attrs; index++; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index cbeac6d4383..88adcf35432 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -538,16 +538,16 @@ static inline void final_mmu_setup(void) */ switch (final_map[index].virt) { case CFG_SYS_FSL_DRAM_BASE1: - final_map[index].virt = gd->bd->bi_dram[0].start; - final_map[index].phys = gd->bd->bi_dram[0].start; - final_map[index].size = gd->bd->bi_dram[0].size; + final_map[index].virt = gd->dram[0].start; + final_map[index].phys = gd->dram[0].start; + final_map[index].size = gd->dram[0].size; break; #ifdef CFG_SYS_FSL_DRAM_BASE2 case CFG_SYS_FSL_DRAM_BASE2: #if (CONFIG_NR_DRAM_BANKS >= 2) - final_map[index].virt = gd->bd->bi_dram[1].start; - final_map[index].phys = gd->bd->bi_dram[1].start; - final_map[index].size = gd->bd->bi_dram[1].size; + final_map[index].virt = gd->dram[1].start; + final_map[index].phys = gd->dram[1].start; + final_map[index].size = gd->dram[1].size; #else final_map[index].size = 0; #endif @@ -556,9 +556,9 @@ static inline void final_mmu_setup(void) #ifdef CFG_SYS_FSL_DRAM_BASE3 case CFG_SYS_FSL_DRAM_BASE3: #if (CONFIG_NR_DRAM_BANKS >= 3) - final_map[index].virt = gd->bd->bi_dram[2].start; - final_map[index].phys = gd->bd->bi_dram[2].start; - final_map[index].size = gd->bd->bi_dram[2].size; + final_map[index].virt = gd->dram[2].start; + final_map[index].phys = gd->dram[2].start; + final_map[index].size = gd->dram[2].size; #else final_map[index].size = 0; #endif @@ -1396,10 +1396,10 @@ static int tfa_dram_init_banksize(void) } debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2); - gd->bd->bi_dram[i].start = res.a1; - gd->bd->bi_dram[i].size = res.a2; + gd->dram[i].start = res.a1; + gd->dram[i].size = res.a2; - dram_size -= gd->bd->bi_dram[i].size; + dram_size -= gd->dram[i].size; i++; } while (dram_size); @@ -1410,24 +1410,24 @@ static int tfa_dram_init_banksize(void) #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bd->bi_dram[2].size >= - board_reserve_ram_top(gd->bd->bi_dram[2].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[2].start + - gd->bd->bi_dram[2].size - - board_reserve_ram_top(gd->bd->bi_dram[2].size); + if (gd->dram[2].size >= + board_reserve_ram_top(gd->dram[2].size)) { + gd->arch.resv_ram = gd->dram[2].start + + gd->dram[2].size - + board_reserve_ram_top(gd->dram[2].size); } else #endif { - if (gd->bd->bi_dram[1].size >= - board_reserve_ram_top(gd->bd->bi_dram[1].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[1].start + - gd->bd->bi_dram[1].size - - board_reserve_ram_top(gd->bd->bi_dram[1].size); - } else if (gd->bd->bi_dram[0].size > - board_reserve_ram_top(gd->bd->bi_dram[0].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - - board_reserve_ram_top(gd->bd->bi_dram[0].size); + if (gd->dram[1].size >= + board_reserve_ram_top(gd->dram[1].size)) { + gd->arch.resv_ram = gd->dram[1].start + + gd->dram[1].size - + board_reserve_ram_top(gd->dram[1].size); + } else if (gd->dram[0].size > + board_reserve_ram_top(gd->dram[0].size)) { + gd->arch.resv_ram = gd->dram[0].start + + gd->dram[0].size - + board_reserve_ram_top(gd->dram[0].size); } } #endif /* CONFIG_RESV_RAM */ @@ -1464,30 +1464,30 @@ int dram_init_banksize(void) } #endif - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - + gd->dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE; + gd->dram[1].start = CFG_SYS_DDR_BLOCK2_BASE; + gd->dram[1].size = gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; - gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - + if (gd->dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { + gd->dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; + gd->dram[2].size = gd->dram[1].size - CONFIG_SYS_DDR_BLOCK2_SIZE; - gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; + gd->dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; } #endif } else { - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; } #ifdef CFG_SYS_MEM_RESERVE_SECURE - if (gd->bd->bi_dram[0].size > + if (gd->dram[0].size > CFG_SYS_MEM_RESERVE_SECURE) { - gd->bd->bi_dram[0].size -= + gd->dram[0].size -= CFG_SYS_MEM_RESERVE_SECURE; - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size; + gd->arch.secure_ram = gd->dram[0].start + + gd->dram[0].size; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE; } @@ -1496,24 +1496,24 @@ int dram_init_banksize(void) #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bd->bi_dram[2].size >= - board_reserve_ram_top(gd->bd->bi_dram[2].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[2].start + - gd->bd->bi_dram[2].size - - board_reserve_ram_top(gd->bd->bi_dram[2].size); + if (gd->dram[2].size >= + board_reserve_ram_top(gd->dram[2].size)) { + gd->arch.resv_ram = gd->dram[2].start + + gd->dram[2].size - + board_reserve_ram_top(gd->dram[2].size); } else #endif { - if (gd->bd->bi_dram[1].size >= - board_reserve_ram_top(gd->bd->bi_dram[1].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[1].start + - gd->bd->bi_dram[1].size - - board_reserve_ram_top(gd->bd->bi_dram[1].size); - } else if (gd->bd->bi_dram[0].size > - board_reserve_ram_top(gd->bd->bi_dram[0].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - - board_reserve_ram_top(gd->bd->bi_dram[0].size); + if (gd->dram[1].size >= + board_reserve_ram_top(gd->dram[1].size)) { + gd->arch.resv_ram = gd->dram[1].start + + gd->dram[1].size - + board_reserve_ram_top(gd->dram[1].size); + } else if (gd->dram[0].size > + board_reserve_ram_top(gd->dram[0].size)) { + gd->arch.resv_ram = gd->dram[0].start + + gd->dram[0].size - + board_reserve_ram_top(gd->dram[0].size); } } #endif /* CONFIG_RESV_RAM */ @@ -1535,8 +1535,8 @@ int dram_init_banksize(void) CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, NULL, NULL, NULL); if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; + gd->dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->dram[2].size = dp_ddr_size; } else { puts("Not detected"); } @@ -1567,8 +1567,8 @@ void lmb_arch_add_memory(void) if (i == 2) continue; /* skip DP-DDR */ #endif - ram_start = gd->bd->bi_dram[i].start; - ram_size = gd->bd->bi_dram[i].size; + ram_start = gd->dram[i].start; + ram_size = gd->dram[i].size; #ifdef CONFIG_RESV_RAM if (gd->arch.resv_ram >= ram_start && gd->arch.resv_ram < ram_start + ram_size) diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 2671f9a0ebf..a82ceeaf22f 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -35,14 +35,13 @@ int arch_fixup_fdt(void *blob) { __maybe_unused int ret = 0; #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT) - struct bd_info *bd = gd->bd; int bank; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; #ifdef CONFIG_ARMV7_NONSEC ret = armv7_apply_memory_carveout(&start[bank], &size[bank]); if (ret) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 1cde655bc80..9a115cc6078 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -64,8 +64,8 @@ static void setup_memory_tags(struct bd_info *bd) params->hdr.tag = ATAG_MEM; params->hdr.size = tag_size (tag_mem32); - params->u.mem.start = bd->bi_dram[i].start; - params->u.mem.size = bd->bi_dram[i].size; + params->u.mem.start = gd->dram[i].start; + params->u.mem.size = gd->dram[i].size; params = tag_next (params); } diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 947012f2996..28bb6fd36c8 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -94,17 +94,16 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, __weak void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; - /* bd->bi_dram is available only after relocation */ + /* gd->dram is available only after relocation */ if ((gd->flags & GD_FLG_RELOC) == 0) return; debug("%s: bank: %d\n", __func__, bank); - for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + - (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); + for (i = gd->dram[bank].start >> MMU_SECTION_SHIFT; + i < (gd->dram[bank].start >> MMU_SECTION_SHIFT) + + (gd->dram[bank].size >> MMU_SECTION_SHIFT); i++) set_section_dcache(i, DCACHE_DEFAULT_OPTION); } diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c index 1f672eee2c8..2268661de93 100644 --- a/arch/arm/lib/image.c +++ b/arch/arm/lib/image.c @@ -69,7 +69,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, if (!force_reloc && (le64_to_cpu(ih->flags) & BIT(3))) dst = image - text_offset; else - dst = gd->bd->bi_dram[0].start; + dst = gd->dram[0].start; *relocated_addr = ALIGN(dst, SZ_2M) + text_offset; diff --git a/arch/arm/mach-airoha/an7581/init.c b/arch/arm/mach-airoha/an7581/init.c index ab32706a79d..f33527ca129 100644 --- a/arch/arm/mach-airoha/an7581/init.c +++ b/arch/arm/mach-airoha/an7581/init.c @@ -23,12 +23,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); if (gd->ram_size > SZ_2G) { - gd->bd->bi_dram[1].start = gd->ram_base + SZ_2G; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = gd->ram_base + SZ_2G; + gd->dram[1].size = gd->ram_size - SZ_2G; } return 0; diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 20054f54089..e74a5a76919 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -807,8 +807,8 @@ void build_mem_map(void) ; /* Align RAM mapping to page boundaries */ - base = gd->bd->bi_dram[0].start; - size = gd->bd->bi_dram[0].size; + base = gd->dram[0].start; + size = gd->dram[0].size; size += (base - ALIGN_DOWN(base, SZ_4K)); base = ALIGN_DOWN(base, SZ_4K); size = ALIGN(size, SZ_4K); diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 07125eac7cd..2281686d633 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -33,8 +33,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 86b11bdf2ac..e1284833ac5 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -311,12 +311,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) static inline bool check_in_dram(ulong addr) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - if (addr >= bd->bi_dram[i].start && - addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + if (gd->dram[i].size) { + if (addr >= gd->dram[i].start && + addr < (gd->dram[i].start + gd->dram[i].size)) return true; } } diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 71a3b341913..34712747fa3 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -111,12 +111,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) static inline bool check_in_dram(ulong addr) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - if (addr >= bd->bi_dram[i].start && - addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + if (gd->dram[i].size) { + if (addr >= gd->dram[i].start && + addr < (gd->dram[i].start + gd->dram[i].size)) return true; } } diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index f4738e3fda8..b52675d8aba 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -604,18 +604,18 @@ static void dram_bank_sort(int current_bank) phys_size_t size; while (current_bank > 0) { - if (gd->bd->bi_dram[current_bank - 1].start > - gd->bd->bi_dram[current_bank].start) { - start = gd->bd->bi_dram[current_bank - 1].start; - size = gd->bd->bi_dram[current_bank - 1].size; - - gd->bd->bi_dram[current_bank - 1].start = - gd->bd->bi_dram[current_bank].start; - gd->bd->bi_dram[current_bank - 1].size = - gd->bd->bi_dram[current_bank].size; - - gd->bd->bi_dram[current_bank].start = start; - gd->bd->bi_dram[current_bank].size = size; + if (gd->dram[current_bank - 1].start > + gd->dram[current_bank].start) { + start = gd->dram[current_bank - 1].start; + size = gd->dram[current_bank - 1].size; + + gd->dram[current_bank - 1].start = + gd->dram[current_bank].start; + gd->dram[current_bank - 1].size = + gd->dram[current_bank].size; + + gd->dram[current_bank].start = start; + gd->dram[current_bank].size = size; } current_bank--; } @@ -643,24 +643,24 @@ int dram_init_banksize(void) continue; if (start >= phys_sdram_1_start && start <= end1) { - gd->bd->bi_dram[i].start = start; + gd->dram[i].start = start; if ((end + 1) <= end1) - gd->bd->bi_dram[i].size = + gd->dram[i].size = end - start + 1; else - gd->bd->bi_dram[i].size = end1 - start; + gd->dram[i].size = end1 - start; dram_bank_sort(i); i++; } else if (start >= phys_sdram_2_start && start <= end2) { - gd->bd->bi_dram[i].start = start; + gd->dram[i].start = start; if ((end + 1) <= end2) - gd->bd->bi_dram[i].size = + gd->dram[i].size = end - start + 1; else - gd->bd->bi_dram[i].size = end2 - start; + gd->dram[i].size = end2 - start; dram_bank_sort(i); i++; @@ -670,10 +670,10 @@ int dram_init_banksize(void) /* If error, set to the default value */ if (!i) { - gd->bd->bi_dram[0].start = phys_sdram_1_start; - gd->bd->bi_dram[0].size = phys_sdram_1_size; - gd->bd->bi_dram[1].start = phys_sdram_2_start; - gd->bd->bi_dram[1].size = phys_sdram_2_size; + gd->dram[0].start = phys_sdram_1_start; + gd->dram[0].size = phys_sdram_1_size; + gd->dram[1].start = phys_sdram_2_start; + gd->dram[1].size = phys_sdram_2_size; } return 0; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 498bbe6704f..e600fd6b33e 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -224,11 +224,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx8m_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx8m_mem_map[entry].phys = gd->dram[i].start; + imx8m_mem_map[entry].virt = gd->dram[i].start; + imx8m_mem_map[entry].size = gd->dram[i].size; imx8m_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size); @@ -290,24 +290,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -315,8 +315,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index ccdb949a9da..6d6f3b81aca 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -512,11 +512,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx8ulp_arm64_mem_map[entry].phys = gd->dram[i].start; + imx8ulp_arm64_mem_map[entry].virt = gd->dram[i].start; + imx8ulp_arm64_mem_map[entry].size = gd->dram[i].size; imx8ulp_arm64_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size); @@ -568,24 +568,24 @@ int dram_init_banksize(void) if (ret) return ret; - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_size; + gd->dram[bank].size = sdram_size; } return 0; diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index 123c1d51a4d..82b3cdffeea 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -356,11 +356,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx9_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx9_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx9_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx9_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx9_mem_map[entry].phys = gd->dram[i].start; + imx9_mem_map[entry].virt = gd->dram[i].start; + imx9_mem_map[entry].size = gd->dram[i].size; imx9_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx9_mem_map[entry].phys, imx9_mem_map[entry].size); @@ -453,24 +453,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (rom_pointer[1] && PHYS_SDRAM < (phys_addr_t)rom_pointer[0]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -478,8 +478,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 6576ecefd5f..0c731e76329 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -367,11 +367,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx93_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx93_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx93_mem_map[entry].phys = gd->dram[i].start; + imx93_mem_map[entry].virt = gd->dram[i].start; + imx93_mem_map[entry].size = gd->dram[i].size; imx93_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx93_mem_map[entry].phys, imx93_mem_map[entry].size); @@ -445,24 +445,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -470,8 +470,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; diff --git a/arch/arm/mach-imx/mx5/mx53_dram.c b/arch/arm/mach-imx/mx5/mx53_dram.c index 180a745d435..5f7709e00b0 100644 --- a/arch/arm/mach-imx/mx5/mx53_dram.c +++ b/arch/arm/mach-imx/mx5/mx53_dram.c @@ -35,11 +35,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); return 0; } diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 57ae81c7834..1029c1e4e85 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -375,8 +375,8 @@ void *spl_load_simple_fit_fix_load(const void *fit) #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = imx_ddr_size(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = imx_ddr_size(); return 0; } diff --git a/arch/arm/mach-k3/k3-ddr.c b/arch/arm/mach-k3/k3-ddr.c index 6e3e60cdc86..35c30b1a16f 100644 --- a/arch/arm/mach-k3/k3-ddr.c +++ b/arch/arm/mach-k3/k3-ddr.c @@ -59,8 +59,8 @@ void fixup_memory_node(struct spl_image_info *spl_image) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index be2d9a25bf9..3ebb4294bdd 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -138,8 +138,8 @@ int alleycat5_dram_init_banksize(void) /* * Config single DRAM bank */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index 17525691e68..38d9b40f482 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -256,7 +256,7 @@ int a3700_dram_init_banksize(void) * build_mem_map. */ if (last_end == dram_wins[win].base) { - gd->bd->bi_dram[bank - 1].size += size; + gd->dram[bank - 1].size += size; last_end += size; } else { if (bank == CONFIG_NR_DRAM_BANKS) { @@ -264,8 +264,8 @@ int a3700_dram_init_banksize(void) return -ENOBUFS; } - gd->bd->bi_dram[bank].start = dram_wins[win].base; - gd->bd->bi_dram[bank].size = size; + gd->dram[bank].start = dram_wins[win].base; + gd->dram[bank].size = size; last_end = dram_wins[win].base + size; ++bank; } @@ -276,8 +276,8 @@ int a3700_dram_init_banksize(void) * the rest with zeros. */ for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) { - gd->bd->bi_dram[bank].start = 0; - gd->bd->bi_dram[bank].size = 0; + gd->dram[bank].start = 0; + gd->dram[bank].size = 0; } return 0; diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c index fd58551d0e3..af37dfa2252 100644 --- a/arch/arm/mach-mvebu/armada8k/dram.c +++ b/arch/arm/mach-mvebu/armada8k/dram.c @@ -38,16 +38,16 @@ int a8k_dram_init_banksize(void) */ phys_size_t max_bank0_size = SZ_4G - SZ_1G; - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size <= max_bank0_size) { - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return 0; } - gd->bd->bi_dram[0].size = max_bank0_size; + gd->dram[0].size = max_bank0_size; if (CONFIG_NR_DRAM_BANKS > 1) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = gd->ram_size - max_bank0_size; } return 0; diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index c00c6b9b3fc..41eaaa24bd0 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -294,11 +294,11 @@ int dram_init_banksize(void) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = mvebu_sdram_bar(i); - gd->bd->bi_dram[i].size = mvebu_sdram_bs(i); + gd->dram[i].start = mvebu_sdram_bar(i); + gd->dram[i].size = mvebu_sdram_bs(i); /* Clip the banksize to 1GiB if it exceeds the max size */ - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; if (size > MVEBU_SDRAM_SIZE_MAX) mvebu_sdram_bs_set(i, 0x40000000); } diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 8699cf46b67..729533d02d4 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -80,8 +80,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c index 200a08fa5c8..f08a9b263f6 100644 --- a/arch/arm/mach-omap2/omap-cache.c +++ b/arch/arm/mach-omap2/omap-cache.c @@ -53,11 +53,10 @@ void enable_caches(void) void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; - u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + u32 start = gd->dram[bank].start >> MMU_SECTION_SHIFT; + u32 size = gd->dram[bank].size >> MMU_SECTION_SHIFT; u32 end = start + size; debug("%s: bank: %d\n", __func__, bank); diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c index 049eedfeb65..67e14d70e92 100644 --- a/arch/arm/mach-omap2/omap3/emif4.c +++ b/arch/arm/mach-omap2/omap3/emif4.c @@ -150,10 +150,10 @@ int dram_init_banksize(void) size0 = get_sdr_cs_size(CS0); size1 = get_sdr_cs_size(CS1); - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); - gd->bd->bi_dram[1].size = size1; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = size0; + gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->dram[1].size = size1; return 0; } diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c index 24fae484369..c4187369c29 100644 --- a/arch/arm/mach-omap2/omap3/sdrc.c +++ b/arch/arm/mach-omap2/omap3/sdrc.c @@ -222,10 +222,10 @@ int dram_init_banksize(void) size0 = get_sdr_cs_size(CS0); size1 = get_sdr_cs_size(CS1); - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); - gd->bd->bi_dram[1].size = size1; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = size0; + gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->dram[1].size = size1; return 0; } diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index 0130cad7678..e316c2cc40e 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -50,8 +50,8 @@ int dram_init(void) /* This is called after dram_init() so use get_ram_size result */ int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-renesas/memmap-gen3.c b/arch/arm/mach-renesas/memmap-gen3.c index d24419f5daa..f7dc2be6cca 100644 --- a/arch/arm/mach-renesas/memmap-gen3.c +++ b/arch/arm/mach-renesas/memmap-gen3.c @@ -70,8 +70,8 @@ void enable_caches(void) /* Generate entires for DRAM in 32bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) @@ -114,8 +114,8 @@ void enable_caches(void) /* Generate entires for DRAM in 64bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) diff --git a/arch/arm/mach-renesas/memmap-rzg2l.c b/arch/arm/mach-renesas/memmap-rzg2l.c index 3b3c6f7cde9..5981b3c9c4d 100644 --- a/arch/arm/mach-renesas/memmap-rzg2l.c +++ b/arch/arm/mach-renesas/memmap-rzg2l.c @@ -67,8 +67,8 @@ void enable_caches(void) /* Generate entries for DRAM in 32bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index eedce7b9b08..c8de1a21024 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -243,14 +243,14 @@ int arch_cpu_init(void) int rockchip_dram_init_banksize_fixup(struct bd_info *bd) { - size_t ram_top = bd->bi_dram[1].start + bd->bi_dram[1].size; + size_t ram_top = gd->dram[1].start + gd->dram[1].size; if (ram_top > DRAM_GAP_START) { - bd->bi_dram[1].size = DRAM_GAP_START - bd->bi_dram[1].start; + gd->dram[1].size = DRAM_GAP_START - gd->dram[1].start; if (ram_top > DRAM_GAP_END && CONFIG_NR_DRAM_BANKS > 2) { - bd->bi_dram[2].start = DRAM_GAP_END; - bd->bi_dram[2].size = ram_top - bd->bi_dram[2].start; + gd->dram[2].start = DRAM_GAP_END; + gd->dram[2].size = ram_top - gd->dram[2].start; } } diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index ea0e3621af7..f0923186fa6 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -171,7 +171,7 @@ static int rockchip_dram_init_banksize(void) /* * Rockchip guaranteed DDR_MEM is ordered so no need to worry about - * bi_dram order. + * dram order. */ for (i = 0, j = 0; i < ddr_info->count; i++, j++) { phys_size_t size = ddr_info->bank[(i + ddr_info->count)]; @@ -261,8 +261,8 @@ static int rockchip_dram_init_banksize(void) * split the region in two, one for before the * reserved memory area and one for after. */ - gd->bd->bi_dram[j].start = start_addr; - gd->bd->bi_dram[j].size = rsrv_start - start_addr; + gd->dram[j].start = start_addr; + gd->dram[j].size = rsrv_start - start_addr; j++; @@ -281,8 +281,8 @@ static int rockchip_dram_init_banksize(void) return -ENOMEM; } - gd->bd->bi_dram[j].start = start_addr; - gd->bd->bi_dram[j].size = size; + gd->dram[j].start = start_addr; + gd->dram[j].size = size; } return 0; @@ -309,15 +309,15 @@ int dram_init_banksize(void) ret); /* Reserve 2M for ATF bl31 */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M; - gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; + gd->dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M; + gd->dram[0].size = top - gd->dram[0].start; /* Add usable memory beyond the blob of space for peripheral near 4GB */ if (ram_top > SZ_4G && top < SZ_4G) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = ram_top - gd->dram[1].start; } else if (ram_top > SZ_4G && top == SZ_4G) { - gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start; + gd->dram[0].size = ram_top - gd->dram[0].start; } #else #ifdef CONFIG_SPL_OPTEE_IMAGE @@ -327,23 +327,23 @@ int dram_init_banksize(void) TRUST_PARAMETER_OFFSET); if (tos_parameter->tee_mem.flags == 1) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = tos_parameter->tee_mem.phy_addr - CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + + gd->dram[1].start = tos_parameter->tee_mem.phy_addr + tos_parameter->tee_mem.size; - gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; + gd->dram[1].size = top - gd->dram[1].start; } else { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x8400000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x8400000; /* Reserve 32M for OPTEE with TA */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE - + gd->bd->bi_dram[0].size + 0x2000000; - gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; + gd->dram[1].start = CFG_SYS_SDRAM_BASE + + gd->dram[0].size + 0x2000000; + gd->dram[1].size = top - gd->dram[1].start; } #else - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = top - gd->dram[0].start; #endif #endif diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 829a0109ac7..35735f1551c 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -73,19 +73,19 @@ static int ddr_bank_cmp(const void *v1, const void *v2) } /* This has to be done post-relocation since gd->bd isn't preserved */ -static void qcom_configure_bi_dram(void) +static void qcom_configure_dram(void) { int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start; - gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size; + gd->dram[i].start = prevbl_ddr_banks[i].start; + gd->dram[i].size = prevbl_ddr_banks[i].size; } } int dram_init_banksize(void) { - qcom_configure_bi_dram(); + qcom_configure_dram(); return 0; } @@ -594,15 +594,15 @@ static void build_mem_map(void) */ mem_map[0].phys = 0x1000; mem_map[0].virt = mem_map[0].phys; - mem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys; + mem_map[0].size = gd->dram[0].start - mem_map[0].phys; mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; - for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->bd->bi_dram[j].size; i++, j++) { - mem_map[i].phys = gd->bd->bi_dram[j].start; + for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->dram[j].size; i++, j++) { + mem_map[i].phys = gd->dram[j].start; mem_map[i].virt = mem_map[i].phys; - mem_map[i].size = gd->bd->bi_dram[j].size; + mem_map[i].size = gd->dram[j].size; mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \ PTE_BLOCK_INNER_SHARE; } diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 4d7f0b9a79c..b202ca258bc 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -202,11 +202,10 @@ void board_prep_linux(struct bootm_headers *images) void lmb_arch_add_memory(void) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (bd->bi_dram[i].size) - lmb_add(bd->bi_dram[i].start, bd->bi_dram[i].size); + if (gd->dram[i].size) + lmb_add(gd->dram[i].start, gd->dram[i].size); } } #endif diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 7e0f3875b7c..338f73d6e73 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -246,7 +246,6 @@ int qspi_flash_software_reset(void) void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; u32 start, size; int i; @@ -261,11 +260,11 @@ void dram_bank_mmu_setup(int bank) * The default implementation of this function allows the DRAM dcache * to be enabled only after relocation. However, to speed up ECC * initialization, we want to be able to enable DRAM dcache before - * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram + * relocation, so we don't check GD_FLG_RELOC (this assumes gd->dram * is set first). */ - start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + start = gd->dram[bank].start >> MMU_SECTION_SHIFT; + size = gd->dram[bank].size >> MMU_SECTION_SHIFT; for (i = start; i < start + size; i++) set_section_dcache(i, DCACHE_DEFAULT_OPTION); } diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 835eaf48dfa..76c324b55ae 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -825,8 +825,8 @@ static int init_device(struct stm32prog_data *data, dev->mtd = mtd; break; case STM32PROG_RAM: - first_addr = gd->bd->bi_dram[0].start; - last_addr = first_addr + gd->bd->bi_dram[0].size; + first_addr = gd->dram[0].start; + last_addr = first_addr + gd->dram[0].size; dev->erase_size = 1; break; default: diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 252aef1852e..4d81c70b230 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -52,7 +52,6 @@ u32 get_bootauth(void) */ void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; phys_addr_t start; phys_addr_t addr; @@ -67,9 +66,9 @@ void dram_bank_mmu_setup(int bank) size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); #endif } else if (gd->flags & GD_FLG_RELOC) { - /* bd->bi_dram is available only after relocation */ - start = bd->bi_dram[bank].start; - size = bd->bi_dram[bank].size; + /* gd->dram is available only after relocation */ + start = gd->dram[bank].start; + size = gd->dram[bank].size; use_lmb = true; } else { /* mark cacheable and executable the beggining of the DDR */ diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 396851c5bd8..1763f95ace4 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -393,18 +393,18 @@ int dram_init_banksize(void) /* fall back to default DRAM bank size computation */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = usable_ram_size_below_4g(); #ifdef CONFIG_PHYS_64BIT if (gd->ram_size > SZ_2G) { - gd->bd->bi_dram[1].start = 0x100000000; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = 0x100000000; + gd->dram[1].size = gd->ram_size - SZ_2G; } else #endif { - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[1].start = 0; + gd->dram[1].size = 0; } return 0; @@ -418,7 +418,7 @@ int dram_init_banksize(void) * carve-out, as mentioned above. * * This function is called before dram_init_banksize(), so we can't simply - * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. + * return gd->dram[1].start + gd->dram[1].size. */ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c index e2342b2aece..ff15fa28eb5 100644 --- a/arch/arm/mach-tegra/cboot.c +++ b/arch/arm/mach-tegra/cboot.c @@ -185,8 +185,8 @@ int cboot_dram_init_banksize(void) } for (i = 0; i < ram_bank_count; i++) { - gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt; - gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; + gd->dram[i].start = tegra_mem_map[1 + i].virt; + gd->dram[i].size = tegra_mem_map[1 + i].size; } return 0; diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 0e1164a2680..ae495808dec 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -280,9 +280,9 @@ int dram_init_banksize(void) return ret; for (i = 0; i < ARRAY_SIZE(dram_map); i++) { - if (i < ARRAY_SIZE(gd->bd->bi_dram)) { - gd->bd->bi_dram[i].start = dram_map[i].base; - gd->bd->bi_dram[i].size = dram_map[i].size; + if (i < ARRAY_SIZE(gd->dram)) { + gd->dram[i].start = dram_map[i].base; + gd->dram[i].size = dram_map[i].size; } if (!dram_map[i].size) diff --git a/arch/arm/mach-uniphier/fdt-fixup.c b/arch/arm/mach-uniphier/fdt-fixup.c index dfa32fdd48b..4e1de15cd98 100644 --- a/arch/arm/mach-uniphier/fdt-fixup.c +++ b/arch/arm/mach-uniphier/fdt-fixup.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include #include @@ -20,6 +21,7 @@ */ static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd) { + DECLARE_GLOBAL_DATA_PTR; unsigned long rsv_addr; const unsigned long rsv_size = 64; int i, ret; @@ -28,11 +30,11 @@ static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd) uniphier_get_soc_id() != UNIPHIER_LD20_ID) return 0; - for (i = 0; i < ARRAY_SIZE(bd->bi_dram); i++) { - if (!bd->bi_dram[i].size) + for (i = 0; i < ARRAY_SIZE(gd->dram); i++) { + if (!gd->dram[i].size) continue; - rsv_addr = bd->bi_dram[i].start + bd->bi_dram[i].size; + rsv_addr = gd->dram[i].start + gd->dram[i].size; rsv_addr -= rsv_size; ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size); diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c index d088e440f63..78ead1f45f6 100644 --- a/arch/arm/mach-versal-net/cpu.c +++ b/arch/arm/mach-versal-net/cpu.c @@ -69,12 +69,12 @@ void mem_map_fill(void) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; - versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; - versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; - versal_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal_mem_map[banks].virt = gd->dram[i].start; + versal_mem_map[banks].phys = gd->dram[i].start; + versal_mem_map[banks].size = gd->dram[i].size; versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 363ce3007fd..0dd5cc153c4 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -82,21 +82,21 @@ void mem_map_fill(void) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; #if defined(CONFIG_VERSAL_NO_DDR) - if (gd->bd->bi_dram[i].start < 0x80000000UL || - gd->bd->bi_dram[i].start > 0x100000000UL) { + if (gd->dram[i].start < 0x80000000UL || + gd->dram[i].start > 0x100000000UL) { printf("Ignore caches over %llx/%llx\n", - gd->bd->bi_dram[i].start, - gd->bd->bi_dram[i].size); + gd->dram[i].start, + gd->dram[i].size); continue; } #endif - versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; - versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; - versal_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal_mem_map[banks].virt = gd->dram[i].start; + versal_mem_map[banks].phys = gd->dram[i].start; + versal_mem_map[banks].size = gd->dram[i].size; versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index a81609cdec7..f65c231bdab 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -109,7 +109,7 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks) * fill_bd_mem_info() - Copy DRAM banks from mem_map to bd_info * * Transfers DRAM bank information from the global versal2_mem_map[] - * array to bd->bi_dram[] for passing memory configuration to the + * array to gd->dram[] for passing memory configuration to the * Linux kernel via boot parameters (ATAGS/FDT). Each bank's physical * address and size are copied. * @@ -119,15 +119,14 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks) */ void fill_bd_mem_info(void) { - struct bd_info *bd = gd->bd; int banks = VERSAL2_MEM_MAP_USED; for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { if (!versal2_mem_map[banks].size) break; - bd->bi_dram[i].start = versal2_mem_map[banks].phys; - bd->bi_dram[i].size = versal2_mem_map[banks].size; + gd->dram[i].start = versal2_mem_map[banks].phys; + gd->dram[i].size = versal2_mem_map[banks].size; banks++; } } diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 5f194aaff9a..3dc47e5d48e 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -92,12 +92,12 @@ void mem_map_fill(void) #if !defined(CONFIG_ZYNQMP_NO_DDR) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; - zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start; - zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start; - zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size; + zynqmp_mem_map[banks].virt = gd->dram[i].start; + zynqmp_mem_map[banks].phys = gd->dram[i].start; + zynqmp_mem_map[banks].size = gd->dram[i].size; zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 5b1311d8b5b..817728aa569 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -41,8 +41,8 @@ int dram_init(void) * No DDR init yet -> run in L2 cache */ gd->ram_size = (4 << 20); - gd->bd->bi_dram[0].size = gd->ram_size; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = gd->ram_size; + gd->dram[1].size = 0; } return 0; diff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c index cc1e903c9dd..2893bc6b99a 100644 --- a/arch/riscv/cpu/k1/dram.c +++ b/arch/riscv/cpu/k1/dram.c @@ -56,12 +56,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); if (gd->ram_size > SZ_2G && CONFIG_NR_DRAM_BANKS > 1) { - gd->bd->bi_dram[1].start = 0x100000000; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = 0x100000000; + gd->dram[1].size = gd->ram_size - SZ_2G; } return 0; @@ -82,8 +82,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - start[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + start[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index 1668b58d3fb..460013f933b 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -131,8 +131,8 @@ SPL_LOAD_IMAGE_METHOD("sandbox_image", 7, BOOT_DEVICE_BOARD, load_from_image); int dram_init_banksize(void) { /* These are necessary so TFTP can use LMBs to check its load address */ - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); return 0; } diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index cc1edd7badd..81604ee12fb 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -91,8 +91,8 @@ int dram_init_banksize(void) struct memrange *memrange = &lib_sysinfo.memrange[i]; if (memrange->type == CB_MEM_RAM) { - gd->bd->bi_dram[j].start = memrange->base; - gd->bd->bi_dram[j].size = memrange->size; + gd->dram[j].start = memrange->base; + gd->dram[j].size = memrange->size; j++; if (j >= CONFIG_NR_DRAM_BANKS) break; diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index 6845ce72ff9..b86d50b2cab 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -123,8 +123,8 @@ int dram_init_banksize(void) if (desc->type != EFI_CONVENTIONAL_MEMORY || (desc->num_pages << EFI_PAGE_SHIFT) < 1 << 20) continue; - gd->bd->bi_dram[num_banks].start = desc->physical_start; - gd->bd->bi_dram[num_banks].size = desc->num_pages << + gd->dram[num_banks].start = desc->physical_start; + gd->dram[num_banks].size = desc->num_pages << EFI_PAGE_SHIFT; num_banks++; } diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c index 6fe40071140..e09fce8bb1b 100644 --- a/arch/x86/cpu/efi/sdram.c +++ b/arch/x86/cpu/efi/sdram.c @@ -24,8 +24,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = efi_get_ram_base(); - gd->bd->bi_dram[0].size = CONFIG_EFI_RAM_SIZE; + gd->dram[0].start = efi_get_ram_base(); + gd->dram[0].size = CONFIG_EFI_RAM_SIZE; return 0; } diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index baa1f0e32d6..11ce97b5143 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -67,8 +67,8 @@ void mrc_common_dram_init_banksize(void) if (area->start >= 1ULL << 32) continue; - gd->bd->bi_dram[num_banks].start = area->start; - gd->bd->bi_dram[num_banks].size = area->size; + gd->dram[num_banks].start = area->start; + gd->dram[num_banks].size = area->size; num_banks++; } } diff --git a/arch/x86/cpu/ivybridge/sdram_nop.c b/arch/x86/cpu/ivybridge/sdram_nop.c index d20c9a2a379..a5e81dfada5 100644 --- a/arch/x86/cpu/ivybridge/sdram_nop.c +++ b/arch/x86/cpu/ivybridge/sdram_nop.c @@ -11,8 +11,8 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { gd->ram_size = 1ULL << 31; - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index ba3638e6acc..3cba04f2c3e 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -69,13 +69,13 @@ int dram_init_banksize(void) { u64 high_mem_size; - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = qemu_get_low_memory_size(); + gd->dram[0].start = 0; + gd->dram[0].size = qemu_get_low_memory_size(); high_mem_size = qemu_get_high_memory_size(); if (high_mem_size) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = high_mem_size; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = high_mem_size; } return 0; diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 34e576940d4..34fdb7e026a 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -169,8 +169,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c index 75ca5273625..5aa4f6d3e07 100644 --- a/arch/x86/cpu/slimbootloader/sdram.c +++ b/arch/x86/cpu/slimbootloader/sdram.c @@ -129,8 +129,8 @@ int dram_init_banksize(void) return 0; /* simply use a single bank to have whole size for now */ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c index 6192f2296b8..6ce96b0569b 100644 --- a/arch/x86/cpu/tangier/sdram.c +++ b/arch/x86/cpu/tangier/sdram.c @@ -160,8 +160,8 @@ static int sfi_get_bank_size(void) if (mentry->type != SFI_MEM_CONV) continue; - gd->bd->bi_dram[bank].start = mentry->phys_start; - gd->bd->bi_dram[bank].size = mentry->pages << 12; + gd->dram[bank].start = mentry->phys_start; + gd->dram[bank].size = mentry->pages << 12; bank++; } diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index cde4fbf3557..e054f42fa86 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -43,14 +43,13 @@ void bootm_announce_and_cleanup(void) #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL) int arch_fixup_memory_node(void *blob) { - struct bd_info *bd = gd->bd; int bank; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 730721dc176..a45e4060ef2 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -64,8 +64,8 @@ int dram_init_banksize(void) update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2); if (!ll_boot_init()) { - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; if (update_mtrr) mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); @@ -89,21 +89,21 @@ int dram_init_banksize(void) mtrr_top = max(mtrr_top, res_desc->phys_start + res_desc->len); } else { - gd->bd->bi_dram[bank].start = res_desc->phys_start; - gd->bd->bi_dram[bank].size = res_desc->len; + gd->dram[bank].start = res_desc->phys_start; + gd->dram[bank].size = res_desc->len; if (update_mtrr) mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start, res_desc->len); log_debug("ram %llx %llx\n", - gd->bd->bi_dram[bank].start, - gd->bd->bi_dram[bank].size); + gd->dram[bank].start, + gd->dram[bank].size); } } /* Add the memory below 4GB */ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = low_end; + gd->dram[0].start = 0; + gd->dram[0].size = low_end; /* * Set up an MTRR to the top of low, reserved memory. This is necessary @@ -184,7 +184,7 @@ unsigned int install_e820_map(unsigned int max_entries, #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB) int handoff_arch_save(struct spl_handoff *ho) { - ho->arch.usable_ram_top = gd->bd->bi_dram[0].size; + ho->arch.usable_ram_top = gd->dram[0].size; ho->arch.hob_list = gd->arch.hob_list; return 0; diff --git a/board/CZ.NIC/turris_1x/turris_1x.c b/board/CZ.NIC/turris_1x/turris_1x.c index 2f9557a4170..32535ed6ee0 100644 --- a/board/CZ.NIC/turris_1x/turris_1x.c +++ b/board/CZ.NIC/turris_1x/turris_1x.c @@ -42,9 +42,9 @@ int dram_init_banksize(void) static_assert(CONFIG_NR_DRAM_BANKS >= 3); - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); - size -= gd->bd->bi_dram[0].size; + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); + size -= gd->dram[0].size; /* Note: This address space is not mapped via TLB entries in U-Boot */ @@ -68,16 +68,16 @@ int dram_init_banksize(void) if (size > 0) { /* Free space between PCIe bus 3 MEM and NOR */ - gd->bd->bi_dram[1].start = 0xc0200000; - gd->bd->bi_dram[1].size = min(size, 0xef000000 - gd->bd->bi_dram[1].start); - size -= gd->bd->bi_dram[1].size; + gd->dram[1].start = 0xc0200000; + gd->dram[1].size = min(size, 0xef000000 - gd->dram[1].start); + size -= gd->dram[1].size; } if (size > 0) { /* Free space between NOR and NAND */ - gd->bd->bi_dram[2].start = 0xf0000000; - gd->bd->bi_dram[2].size = min(size, 0xff800000 - gd->bd->bi_dram[2].start); - size -= gd->bd->bi_dram[2].size; + gd->dram[2].start = 0xf0000000; + gd->dram[2].size = min(size, 0xff800000 - gd->dram[2].start); + size -= gd->dram[2].size; } #else puts("\n\n!!! TODO: fix sdcard >2GB RAM\n\n\n"); @@ -231,8 +231,8 @@ void ft_memory_setup(void *blob, struct bd_info *bd) if (!env_get("bootm_low") && !env_get("bootm_size")) { for (count = 0; count < CONFIG_NR_DRAM_BANKS; count++) { - start[count] = gd->bd->bi_dram[count].start; - size[count] = gd->bd->bi_dram[count].size; + start[count] = gd->dram[count].start; + size[count] = gd->dram[count].size; if (!size[count]) break; } @@ -452,13 +452,13 @@ static void recalculate_used_pcie_mem(void) size = gd->ram_size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size -= gd->bd->bi_dram[i].size; + size -= gd->dram[i].size; if (size == 0) return; e = find_law_by_addr_id(CFG_SYS_PCIE3_MEM_PHYS, LAW_TRGT_IF_PCIE_3); - if (e.index < 0 && gd->bd->bi_dram[1].size > 0) { + if (e.index < 0 && gd->dram[1].size > 0) { /* * If there is no LAW for PCIe 3 MEM then 3rd PCIe controller * is inactive, which is the case for Turris 1.0 boards. So @@ -471,8 +471,8 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(bank_size, ""); printf(" of PCIe 3 MEM for DDR RAM\n"); - gd->bd->bi_dram[1].start -= bank_size; - gd->bd->bi_dram[1].size += bank_size; + gd->dram[1].start -= bank_size; + gd->dram[1].size += bank_size; size -= bank_size; if (size == 0) return; @@ -534,9 +534,9 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(free_size2, ""); printf(" of PCIe 2 MEM for DDR RAM\n"); - gd->bd->bi_dram[i].start = free_start2; - gd->bd->bi_dram[i].size = min(size, free_size2); - size -= gd->bd->bi_dram[i].start; + gd->dram[i].start = free_start2; + gd->dram[i].size = min(size, free_size2); + size -= gd->dram[i].start; i++; if (size == 0) return; @@ -548,9 +548,9 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(free_size1, ""); printf(" of PCIe 1 MEM for DDR RAM\n"); - gd->bd->bi_dram[i].start = free_start1; - gd->bd->bi_dram[i].size = min(size, free_size1); - size -= gd->bd->bi_dram[i].size; + gd->dram[i].start = free_start1; + gd->dram[i].size = min(size, free_size1); + size -= gd->dram[i].size; i++; if (size == 0) return; diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c index 16d0e679c3e..eb0f9c06849 100644 --- a/board/armltd/corstone1000/corstone1000.c +++ b/board/armltd/corstone1000/corstone1000.c @@ -86,8 +86,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index eaf87e3bfe3..6cd24bf25fb 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -137,7 +137,7 @@ int misc_init_r (void) int dram_init (void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; #ifdef CONFIG_CM_SPD_DETECT { extern void dram_query(void); @@ -170,7 +170,7 @@ extern void dram_query(void); PHYS_SDRAM_1_SIZE); #endif /* CM_SPD_DETECT */ /* We only have one bank of RAM, set it to whatever was detected */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index 12bb6defab2..057e916ab1b 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -89,9 +89,9 @@ void build_mem_map(void) * The first node is for I/O device, start from node 1 for * updating DRAM info. */ - mem_map[i + 1].virt = gd->bd->bi_dram[i].start; - mem_map[i + 1].phys = gd->bd->bi_dram[i].start; - mem_map[i + 1].size = gd->bd->bi_dram[i].size; + mem_map[i + 1].virt = gd->dram[i].start; + mem_map[i + 1].phys = gd->dram[i].start; + mem_map[i + 1].size = gd->dram[i].size; mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; } diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 3833af59b09..87e53f64e06 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -79,11 +79,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); return 0; diff --git a/board/atmel/common/video_display.c b/board/atmel/common/video_display.c index 77188820581..7cb492b2da6 100644 --- a/board/atmel/common/video_display.c +++ b/board/atmel/common/video_display.c @@ -40,7 +40,7 @@ int at91_video_show_board_info(void) dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - dram_size += gd->bd->bi_dram[i].size; + dram_size += gd->dram[i].size; nand_size = 0; #ifdef CONFIG_NAND_ATMEL diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c index 43797d625e9..b19ae3b4b03 100644 --- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c +++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c @@ -66,7 +66,7 @@ int misc_init_r(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; board_leds_init(); diff --git a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c index 364b6a3e24b..5c35239a90a 100644 --- a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c +++ b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c @@ -45,7 +45,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index 858061bf9f9..33ae6a76bf7 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -64,7 +64,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 19341d325bd..0e2d5592753 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -58,7 +58,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c index 8759ff6f01a..1a17db1bd5b 100644 --- a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c +++ b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c @@ -65,7 +65,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index c0862f58606..b48e8fe7697 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -63,7 +63,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c index 764c8f035c9..cdf2793b643 100644 --- a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c +++ b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c @@ -52,7 +52,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; board_leds_init(); diff --git a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c index b05c9754c96..02543d8e99f 100644 --- a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c +++ b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { // Address of boot parameters - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/axiado/scm3005/scm3005.c b/board/axiado/scm3005/scm3005.c index 4643ba4a55c..b2df6d89cd8 100644 --- a/board/axiado/scm3005/scm3005.c +++ b/board/axiado/scm3005/scm3005.c @@ -96,8 +96,8 @@ int dram_init(void) */ int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c index bb2f1e4f62a..2683f46f41c 100644 --- a/board/broadcom/bcmns3/ns3.c +++ b/board/broadcom/bcmns3/ns3.c @@ -176,8 +176,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M); - gd->bd->bi_dram[0].size = SZ_16M; + gd->dram[0].start = (BCM_NS3_MEM_END - SZ_16M); + gd->dram[0].size = SZ_16M; return 0; } diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index e20350dc5d5..5bc4d3248bd 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -666,34 +666,34 @@ int misc_init_r(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[1].start = PHYS_SDRAM_2; switch (gd->ram_size) { case 0x10000000: /* DDR_16BIT_256MB */ - gd->bd->bi_dram[0].size = 0x10000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x10000000; + gd->dram[1].size = 0; break; case 0x20000000: /* DDR_32BIT_512MB */ - gd->bd->bi_dram[0].size = 0x20000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x20000000; + gd->dram[1].size = 0; break; case 0x40000000: if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */ - gd->bd->bi_dram[0].size = 0x20000000; - gd->bd->bi_dram[1].size = 0x20000000; + gd->dram[0].size = 0x20000000; + gd->dram[1].size = 0x20000000; } else { /* DDR_64BIT_1GB */ - gd->bd->bi_dram[0].size = 0x40000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x40000000; + gd->dram[1].size = 0; } break; case 0x80000000: /* DDR_64BIT_2GB */ - gd->bd->bi_dram[0].size = 0x40000000; - gd->bd->bi_dram[1].size = 0x40000000; + gd->dram[0].size = 0x40000000; + gd->dram[1].size = 0x40000000; break; case 0xEFF00000: /* DDR_64BIT_4GB */ - gd->bd->bi_dram[0].size = 0x70000000; - gd->bd->bi_dram[1].size = 0x7FF00000; + gd->dram[0].size = 0x70000000; + gd->dram[1].size = 0x7FF00000; break; } diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c index 9fea4f86d5a..33f7ec6d048 100644 --- a/board/elgin/elgin_rv1108/elgin_rv1108.c +++ b/board/elgin/elgin_rv1108/elgin_rv1108.c @@ -66,8 +66,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = 0x60000000; - gd->bd->bi_dram[0].size = 0x8000000; + gd->dram[0].start = 0x60000000; + gd->dram[0].size = 0x8000000; return 0; } diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index dce69abdfd1..3d76c936073 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -141,8 +141,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c index eb10cd5143d..5e560a7f927 100644 --- a/board/friendlyarm/nanopi2/board.c +++ b/board/friendlyarm/nanopi2/board.c @@ -532,17 +532,17 @@ int dram_init_banksize(void) /* set global data memory */ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100; - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; /* Number of Row: 14 bits */ if ((reg_val >> 28) == 14) - gd->bd->bi_dram[0].size -= 0x20000000; + gd->dram[0].size -= 0x20000000; /* Number of Memory Chips */ if ((reg_val & 0x3) > 1) { - gd->bd->bi_dram[1].start = 0x80000000; - gd->bd->bi_dram[1].size = 0x40000000; + gd->dram[1].start = 0x80000000; + gd->dram[1].size = 0x40000000; } return 0; } diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index cb9b88a1a58..d3a385bf6b7 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -71,11 +71,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = mx53_dram_size[0]; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = mx53_dram_size[0]; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = mx53_dram_size[1]; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = mx53_dram_size[1]; return 0; } diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index 5e60ab9d7b7..ba0465cf96f 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -456,23 +456,23 @@ int dram_init_banksize(void) * 0x3e00,0000 - 0x3fff,ffff: OP-TEE */ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = 0x05e00000; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = 0x05e00000; - gd->bd->bi_dram[1].start = 0x05f00000; - gd->bd->bi_dram[1].size = 0x00001000; + gd->dram[1].start = 0x05f00000; + gd->dram[1].size = 0x00001000; - gd->bd->bi_dram[2].start = 0x05f02000; - gd->bd->bi_dram[2].size = 0x00efd000; + gd->dram[2].start = 0x05f02000; + gd->dram[2].size = 0x00efd000; - gd->bd->bi_dram[3].start = 0x06e00000; - gd->bd->bi_dram[3].size = 0x0060f000; + gd->dram[3].start = 0x06e00000; + gd->dram[3].size = 0x0060f000; - gd->bd->bi_dram[4].start = 0x07410000; - gd->bd->bi_dram[4].size = 0x1aaf0000; + gd->dram[4].start = 0x07410000; + gd->dram[4].size = 0x1aaf0000; - gd->bd->bi_dram[5].start = 0x22000000; - gd->bd->bi_dram[5].size = 0x1c000000; + gd->dram[5].start = 0x22000000; + gd->dram[5].size = 0x1c000000; return 0; } diff --git a/board/hisilicon/hikey960/hikey960.c b/board/hisilicon/hikey960/hikey960.c index fb56762fff6..e7908d4c048 100644 --- a/board/hisilicon/hikey960/hikey960.c +++ b/board/hisilicon/hikey960/hikey960.c @@ -74,8 +74,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c index c3ea080ff75..dbab67d6f65 100644 --- a/board/hisilicon/poplar/poplar.c +++ b/board/hisilicon/poplar/poplar.c @@ -87,8 +87,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET; - gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start; + gd->dram[0].start = KERNEL_TEXT_OFFSET; + gd->dram[0].size = gd->ram_size - gd->dram[0].start; return 0; } diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c index efb7b49cbe0..07668bae7a9 100644 --- a/board/k+p/kp_imx53/kp_imx53.c +++ b/board/k+p/kp_imx53/kp_imx53.c @@ -39,8 +39,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c index 51938a1b4d8..e37d4e767db 100644 --- a/board/keymile/pg-wcom-ls102xa/ddr.c +++ b/board/keymile/pg-wcom-ls102xa/ddr.c @@ -84,8 +84,8 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 8a9502037fb..ce778bc0849 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -175,8 +175,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < nbanks; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } fdt_fixup_memory_banks(blob, base, size, nbanks); diff --git a/board/kontron/sl28/spl_atf.c b/board/kontron/sl28/spl_atf.c index 0710316a48b..cc741dea504 100644 --- a/board/kontron/sl28/spl_atf.c +++ b/board/kontron/sl28/spl_atf.c @@ -36,9 +36,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, dram_regions_info.num_dram_regions = CONFIG_NR_DRAM_BANKS; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - dram_regions_info.region[i].addr = gd->bd->bi_dram[i].start; - dram_regions_info.region[i].size = gd->bd->bi_dram[i].size; - dram_regions_info.total_dram_size += gd->bd->bi_dram[i].size; + dram_regions_info.region[i].addr = gd->dram[i].start; + dram_regions_info.region[i].size = gd->dram[i].size; + dram_regions_info.total_dram_size += gd->dram[i].size; } bl_params = bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry, diff --git a/board/liebherr/btt/btt.c b/board/liebherr/btt/btt.c index e1ff041c54f..ba922b43064 100644 --- a/board/liebherr/btt/btt.c +++ b/board/liebherr/btt/btt.c @@ -239,7 +239,7 @@ int spl_start_uboot(void) static const char *get_board_name(void) { - if (gd->bd->bi_dram[0].size == SZ_128M) + if (gd->dram[0].size == SZ_128M) return STR_BTTC; return STR_BTT3; diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index fc76d5765fa..5e76942783f 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -69,11 +69,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = mx53_dram_size[0]; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = mx53_dram_size[0]; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = mx53_dram_size[1]; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = mx53_dram_size[1]; return 0; } diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index 05c4dd187fe..68d516c7db8 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -57,7 +57,7 @@ int dram_init_banksize(void) { phys_size_t ram_size = gd->ram_size; - gd->bd->bi_dram[0].start = 0; + gd->dram[0].start = 0; #if defined(CONFIG_SYS_MEM_TOP_HIDE) ram_size += CONFIG_SYS_MEM_TOP_HIDE; @@ -69,25 +69,25 @@ int dram_init_banksize(void) case DRAM_1GB_SIZE: case DRAM_2GB_ECC_SIZE: case DRAM_2GB_SIZE: - gd->bd->bi_dram[0].size = ram_size; - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = ram_size; + gd->dram[1].start = 0; + gd->dram[1].size = 0; break; case DRAM_4GB_ECC_SIZE: - gd->bd->bi_dram[0].size = DRAM_2GB_SIZE; - gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; - gd->bd->bi_dram[1].size = DRAM_2GB_SIZE - + gd->dram[0].size = DRAM_2GB_SIZE; + gd->dram[1].start = DRAM_4GB_SIZE; + gd->dram[1].size = DRAM_2GB_SIZE - (DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE); break; case DRAM_4GB_SIZE: - gd->bd->bi_dram[0].size = DRAM_2GB_SIZE; - gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; - gd->bd->bi_dram[1].size = DRAM_2GB_SIZE; + gd->dram[0].size = DRAM_2GB_SIZE; + gd->dram[1].start = DRAM_4GB_SIZE; + gd->dram[1].size = DRAM_2GB_SIZE; break; default: - gd->bd->bi_dram[0].size = DRAM_1GB_SIZE; - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = DRAM_1GB_SIZE; + gd->dram[1].start = 0; + gd->dram[1].size = 0; break; } diff --git a/board/nxp/imxrt1020-evk/imxrt1020-evk.c b/board/nxp/imxrt1020-evk/imxrt1020-evk.c index 11dbef84688..6843b33679d 100644 --- a/board/nxp/imxrt1020-evk/imxrt1020-evk.c +++ b/board/nxp/imxrt1020-evk/imxrt1020-evk.c @@ -73,7 +73,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/imxrt1050-evk/imxrt1050-evk.c b/board/nxp/imxrt1050-evk/imxrt1050-evk.c index 056489932ac..19d068fc626 100644 --- a/board/nxp/imxrt1050-evk/imxrt1050-evk.c +++ b/board/nxp/imxrt1050-evk/imxrt1050-evk.c @@ -78,7 +78,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/imxrt1170-evk/imxrt1170-evk.c b/board/nxp/imxrt1170-evk/imxrt1170-evk.c index 047aea8181a..3afd5ae2136 100644 --- a/board/nxp/imxrt1170-evk/imxrt1170-evk.c +++ b/board/nxp/imxrt1170-evk/imxrt1170-evk.c @@ -73,7 +73,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/ls1021aqds/ddr.c b/board/nxp/ls1021aqds/ddr.c index fd897e832c8..8d07f6110ce 100644 --- a/board/nxp/ls1021aqds/ddr.c +++ b/board/nxp/ls1021aqds/ddr.c @@ -192,8 +192,8 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/nxp/ls1028a/ls1028a.c b/board/nxp/ls1028a/ls1028a.c index 196e25931f3..e1e83137f4d 100644 --- a/board/nxp/ls1028a/ls1028a.c +++ b/board/nxp/ls1028a/ls1028a.c @@ -149,7 +149,7 @@ int board_early_init_f(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -202,10 +202,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/ls1043aqds/ls1043aqds.c b/board/nxp/ls1043aqds/ls1043aqds.c index 0f115c16232..dba93add698 100644 --- a/board/nxp/ls1043aqds/ls1043aqds.c +++ b/board/nxp/ls1043aqds/ls1043aqds.c @@ -542,10 +542,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u8 reg; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1043ardb/ls1043ardb.c b/board/nxp/ls1043ardb/ls1043ardb.c index bba041065b5..678c529cf55 100644 --- a/board/nxp/ls1043ardb/ls1043ardb.c +++ b/board/nxp/ls1043ardb/ls1043ardb.c @@ -305,10 +305,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046afrwy/ls1046afrwy.c b/board/nxp/ls1046afrwy/ls1046afrwy.c index 8889c24f1f0..6c35c0a4347 100644 --- a/board/nxp/ls1046afrwy/ls1046afrwy.c +++ b/board/nxp/ls1046afrwy/ls1046afrwy.c @@ -198,10 +198,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046aqds/ls1046aqds.c b/board/nxp/ls1046aqds/ls1046aqds.c index 679b0b2235f..ddd9993986f 100644 --- a/board/nxp/ls1046aqds/ls1046aqds.c +++ b/board/nxp/ls1046aqds/ls1046aqds.c @@ -426,10 +426,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u8 reg; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046ardb/ls1046ardb.c b/board/nxp/ls1046ardb/ls1046ardb.c index 83b280f7646..6677e271029 100644 --- a/board/nxp/ls1046ardb/ls1046ardb.c +++ b/board/nxp/ls1046ardb/ls1046ardb.c @@ -171,10 +171,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1088a/ls1088a.c b/board/nxp/ls1088a/ls1088a.c index 5783dd8a403..1b477e83676 100644 --- a/board/nxp/ls1088a/ls1088a.c +++ b/board/nxp/ls1088a/ls1088a.c @@ -830,7 +830,7 @@ int board_init(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -959,8 +959,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } #ifdef CONFIG_RESV_RAM diff --git a/board/nxp/ls2080aqds/ls2080aqds.c b/board/nxp/ls2080aqds/ls2080aqds.c index aba0560181a..325dc817aaf 100644 --- a/board/nxp/ls2080aqds/ls2080aqds.c +++ b/board/nxp/ls2080aqds/ls2080aqds.c @@ -253,12 +253,12 @@ int misc_init_r(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->dram[2].size) { puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); + print_size(gd->dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } #endif @@ -302,10 +302,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/ls2080ardb/ls2080ardb.c b/board/nxp/ls2080ardb/ls2080ardb.c index d08598d1c62..9dec818280b 100644 --- a/board/nxp/ls2080ardb/ls2080ardb.c +++ b/board/nxp/ls2080ardb/ls2080ardb.c @@ -359,12 +359,12 @@ int misc_init_r(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->dram[2].size) { puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); + print_size(gd->dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } #endif @@ -487,10 +487,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) size = calloc(total_memory_banks, sizeof(u64)); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/lx2160a/lx2160a.c b/board/nxp/lx2160a/lx2160a.c index b7a6ccf46aa..10729dfaf24 100644 --- a/board/nxp/lx2160a/lx2160a.c +++ b/board/nxp/lx2160a/lx2160a.c @@ -573,7 +573,7 @@ void detail_board_ddr_info(void) puts("\nDDR "); for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - ddr_size += gd->bd->bi_dram[i].size; + ddr_size += gd->dram[i].size; print_size(ddr_size, ""); print_ddr_info(0); } @@ -808,8 +808,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the three GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } #ifdef CONFIG_RESV_RAM diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index 3cdcbf2ecc9..6df521d789f 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -93,7 +93,7 @@ int dram_init_banksize(void) { u8 ram_size; - memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS); + memset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS); if (!IS_ENABLED(CONFIG_CPU_V7R)) return fdtdec_setup_memory_banksize(); @@ -101,34 +101,34 @@ int dram_init_banksize(void) ram_size = phytec_get_am62_ddr_size_default(); switch (ram_size) { case EEPROM_RAM_SIZE_1GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x40000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x40000000; gd->ram_size = 0x40000000; break; case EEPROM_RAM_SIZE_2GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; break; case EEPROM_RAM_SIZE_4GB: /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR upper region */ - gd->bd->bi_dram[1].start = 0x880000000; - gd->bd->bi_dram[1].size = 0x80000000; + gd->dram[1].start = 0x880000000; + gd->dram[1].size = 0x80000000; gd->ram_size = 0x100000000; #endif break; default: /* Continue with default 2GB setup */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; printf("DDR size %d is not supported\n", ram_size); } @@ -186,8 +186,8 @@ int do_board_detect(void) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } ret = fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c index 114aa217023..5e077872152 100644 --- a/board/phytec/phycore_am64x/phycore-am64x.c +++ b/board/phytec/phycore_am64x/phycore-am64x.c @@ -66,7 +66,7 @@ int dram_init_banksize(void) { u8 ram_size; - memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS); + memset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS); if (!IS_ENABLED(CONFIG_CPU_V7R)) return fdtdec_setup_memory_banksize(); @@ -74,21 +74,21 @@ int dram_init_banksize(void) ram_size = phytec_get_am64_ddr_size_default(); switch (ram_size) { case EEPROM_RAM_SIZE_1GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x40000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x40000000; gd->ram_size = 0x40000000; break; case EEPROM_RAM_SIZE_2GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; break; default: /* Continue with default 2GB setup */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; printf("DDR size %d is not supported\n", ram_size); } @@ -109,8 +109,8 @@ int do_board_detect(void) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } return fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c index 9fc63febdac..a738e3542e2 100644 --- a/board/phytium/durian/durian.c +++ b/board/phytium/durian/durian.c @@ -31,8 +31,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c index 6824454cdf4..421e193e730 100644 --- a/board/phytium/pe2201/pe2201.c +++ b/board/phytium/pe2201/pe2201.c @@ -44,8 +44,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index b0a1484c0fa..885c660a289 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -356,9 +356,9 @@ int dram_init_banksize(void) /* Update gd->ram_size to reflect total RAM across all banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (gd->bd->bi_dram[i].size == 0) + if (gd->dram[i].size == 0) break; - total_size += gd->bd->bi_dram[i].size; + total_size += gd->dram[i].size; } gd->ram_size = total_size; diff --git a/board/renesas/common/rcar64-common.c b/board/renesas/common/rcar64-common.c index 3d537be4d02..09667d46d99 100644 --- a/board/renesas/common/rcar64-common.c +++ b/board/renesas/common/rcar64-common.c @@ -49,15 +49,15 @@ int dram_init_banksize(void) return 0; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (gd->bd->bi_dram[bank].start != 0x48000000) + if (gd->dram[bank].start != 0x48000000) continue; /* * If this U-Boot runs in EL3, make the bottom 128 MiB * available for loading of follow up firmware blobs. */ - gd->bd->bi_dram[bank].start -= 0x8000000; - gd->bd->bi_dram[bank].size += 0x8000000; + gd->dram[bank].start -= 0x8000000; + gd->dram[bank].size += 0x8000000; break; } diff --git a/board/renesas/genmai/genmai.c b/board/renesas/genmai/genmai.c index 8153aed15e3..9245bf348f8 100644 --- a/board/renesas/genmai/genmai.c +++ b/board/renesas/genmai/genmai.c @@ -43,7 +43,7 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c index a229542ba7e..1503de675d5 100644 --- a/board/renesas/sparrowhawk/sparrowhawk.c +++ b/board/renesas/sparrowhawk/sparrowhawk.c @@ -261,10 +261,10 @@ void renesas_dram_init_banksize(void) /* 16 GiB device, adjust memory map. */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (gd->bd->bi_dram[bank].start == 0x480000000ULL) - gd->bd->bi_dram[bank].size = 0x180000000ULL; - else if (gd->bd->bi_dram[bank].start == 0x600000000ULL) - gd->bd->bi_dram[bank].size = 0x200000000ULL; + if (gd->dram[bank].start == 0x480000000ULL) + gd->dram[bank].size = 0x180000000ULL; + else if (gd->dram[bank].start == 0x600000000ULL) + gd->dram[bank].size = 0x200000000ULL; } } diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 1f78654b685..7a0a93c1afe 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -103,8 +103,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index cc58e0f3a38..0ff49dceb9e 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -97,8 +97,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 5d5edd9f253..b5664296a81 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -150,8 +150,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index e70b4a82687..130136e8596 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -67,8 +67,8 @@ int dram_init_banksize(void) addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; + gd->dram[i].start = addr; + gd->dram[i].size = size; } return 0; diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index eed1c2450fa..da3510023c4 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -115,7 +115,7 @@ int board_init(void) ulong size = CONFIG_SYS_MEM_TOP_HIDE; gd->ram_size -= size; - gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; + gd->dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; #endif exynos_init(); @@ -143,8 +143,8 @@ int dram_init_banksize(void) addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; + gd->dram[i].start = addr; + gd->dram[i].size = size; } return 0; diff --git a/board/samsung/exynos-mobile/exynos-mobile.c b/board/samsung/exynos-mobile/exynos-mobile.c index 6b2b1523663..d91e2e7d3f2 100644 --- a/board/samsung/exynos-mobile/exynos-mobile.c +++ b/board/samsung/exynos-mobile/exynos-mobile.c @@ -346,8 +346,8 @@ int dram_init_banksize(void) unsigned int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = mem_map[i + 1].phys; - gd->bd->bi_dram[i].size = mem_map[i + 1].size; + gd->dram[i].start = mem_map[i + 1].phys; + gd->dram[i].size = mem_map[i + 1].size; } return 0; diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index a1047f3fd2a..96a411233d1 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -43,12 +43,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = PHYS_SDRAM_2_SIZE; + gd->dram[2].start = PHYS_SDRAM_3; + gd->dram[2].size = PHYS_SDRAM_3_SIZE; return 0; } diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 7d0b0fcb0ae..7e992c23a1b 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -56,8 +56,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index 5a4874b29cd..f013893b465 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -57,17 +57,17 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, + gd->dram[2].start = PHYS_SDRAM_3; + gd->dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE); - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, + gd->dram[3].start = PHYS_SDRAM_4; + gd->dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); return 0; diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index 79cf34b40eb..69d3b9d61d3 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -397,20 +397,20 @@ int dram_init_banksize(void) if (gd->ram_size > SZ_2G) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = SZ_2G; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = SZ_2G; /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = CFG_SYS_SDRAM_BASE1; + gd->dram[1].size = gd->ram_size - SZ_2G; } else { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[1].start = 0; + gd->dram[1].size = 0; } return 0; diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index 556a9ed527e..a7bd08f69ad 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -170,11 +170,11 @@ int dram_init_banksize(void) struct draminfo_entry *ent = synquacer_draminfo->entry; int i; - for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { + for (i = 0; i < ARRAY_SIZE(gd->dram); i++) { if (i < synquacer_draminfo->nr_regions) { debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); - gd->bd->bi_dram[i].start = ent[i].base; - gd->bd->bi_dram[i].size = ent[i].size; + gd->dram[i].start = ent[i].base; + gd->dram[i].size = ent[i].size; } } diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index f5174720434..a1b0265d5ac 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -18,8 +18,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/ste/stemmy/stemmy.c b/board/ste/stemmy/stemmy.c index 826c002907d..66330184af8 100644 --- a/board/ste/stemmy/stemmy.c +++ b/board/ste/stemmy/stemmy.c @@ -70,8 +70,8 @@ int dram_init_banksize(void) if (t->hdr.tag != ATAG_MEM) continue; - gd->bd->bi_dram[bank].start = t->u.mem.start; - gd->bd->bi_dram[bank].size = t->u.mem.size; + gd->dram[bank].start = t->u.mem.start; + gd->dram[bank].size = t->u.mem.size; if (++bank == CONFIG_NR_DRAM_BANKS) break; } diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 0966db2bb62..6f1fed43e36 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -643,11 +643,11 @@ int dram_init_banksize(void) ram_size = board_ti_get_emif_size(); - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = get_effective_memsize(); if (ram_size > CFG_MAX_MEM_MAPPED) { - gd->bd->bi_dram[1].start = 0x200000000; - gd->bd->bi_dram[1].size = ram_size - CFG_MAX_MEM_MAPPED; + gd->dram[1].start = 0x200000000; + gd->dram[1].size = ram_size - CFG_MAX_MEM_MAPPED; } return 0; diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index a92aa5cfc67..43330993955 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -117,8 +117,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) } nbanks = 1; - start[0] = bd->bi_dram[0].start; - size[0] = bd->bi_dram[0].size; + start[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; /* adjust memory start address for LPAE */ if (lpae) { diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 69a8a18d3a7..c63812bd966 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -288,13 +288,13 @@ int ft_board_setup(void *blob, struct bd_info *bd) * Reserve 1MB of memory for M4 (1MiB is also the minimum * alignment for Linux due to MMU section size restrictions). */ - start[0] = gd->bd->bi_dram[0].start; + start[0] = gd->dram[0].start; size[0] = SZ_256M - SZ_1M; /* If needed, create a second entry for memory beyond 256M */ - if (gd->bd->bi_dram[0].size > SZ_256M) { - start[1] = gd->bd->bi_dram[0].start + SZ_256M; - size[1] = gd->bd->bi_dram[0].size - SZ_256M; + if (gd->dram[0].size > SZ_256M) { + start[1] = gd->dram[0].start + SZ_256M; + size[1] = gd->dram[0].size - SZ_256M; areas = 2; } diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index 19ac2ae9313..26af1af2069 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -44,7 +44,7 @@ int dram_init_banksize(void) printf("Error setting up memory banksize. %d\n", ret); /* Use the detected RAM size, we only support 1 bank right now. */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return ret; } diff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c index 1234b3887c6..ec7775e06a7 100644 --- a/board/toradex/verdin-am62p/verdin-am62p.c +++ b/board/toradex/verdin-am62p/verdin-am62p.c @@ -78,7 +78,7 @@ int dram_init_banksize(void) printf("Error setting up memory banksize. %d\n", ret); /* Use the detected RAM size, we only support 1 bank right now. */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return ret; } diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c index ac8c9a9a81a..5c45f9932c5 100644 --- a/board/traverse/ten64/ten64.c +++ b/board/traverse/ten64/ten64.c @@ -148,7 +148,7 @@ int fsl_initdram(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -277,8 +277,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; /* reduce size if reserved memory is within this bank */ if (IS_ENABLED(CONFIG_RESV_RAM) && RESV_MEM_IN_BANK(i)) size[i] = gd->arch.resv_ram - base[i]; diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c index 05ecb75406b..d8eff203a56 100644 --- a/board/xilinx/zynq/cmds.c +++ b/board/xilinx/zynq/cmds.c @@ -347,10 +347,10 @@ static int zynq_verify_image(u32 src_ptr) * This validation is just for PS DDR. * TODO: Update this for PL DDR check as well. */ - if (part_load_addr < gd->bd->bi_dram[0].start && + if (part_load_addr < gd->dram[0].start && ((part_load_addr + part_data_len) > - (gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size))) { + (gd->dram[0].start + + gd->dram[0].size))) { printf("INVALID_LOAD_ADDRESS_FAIL\n"); return -1; } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index eb41f84c198..a12c039d8c9 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -279,8 +279,8 @@ int dram_init(void) #else int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = get_effective_memsize(); mem_map_fill(); diff --git a/boot/image-board.c b/boot/image-board.c index 265f29d44ff..67938fdd200 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -118,7 +118,7 @@ phys_addr_t env_get_bootm_low(void) #if defined(CFG_SYS_SDRAM_BASE) return CFG_SYS_SDRAM_BASE; #elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV) - return gd->bd->bi_dram[0].start; + return gd->dram[0].start; #else return 0; #endif diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 1150131a11e..9e0e0f93edd 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -260,8 +260,8 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) of_start = NULL; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* DRAM bank addresses are too low, skip it. */ if (start + size < low) diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index ddf77303735..bf1eca75904 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -77,15 +77,15 @@ void bdinfo_print_mhz(const char *name, unsigned long hz) printf("%-12s= %6s MHz\n", name, strmhz(buf, hz)); } -static void print_bi_dram(const struct bd_info *bd) +static void print_dram(const struct bd_info *bd) { int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { + if (gd->dram[i].size) { bdinfo_print_num_l("DRAM bank", i); - bdinfo_print_num_ll("-> start", bd->bi_dram[i].start); - bdinfo_print_num_ll("-> size", bd->bi_dram[i].size); + bdinfo_print_num_ll("-> start", gd->dram[i].start); + bdinfo_print_num_ll("-> size", gd->dram[i].size); } } } @@ -144,7 +144,7 @@ static int bdinfo_print_all(struct bd_info *bd) bdinfo_print_num_l("bd address", (ulong)bd); #endif bdinfo_print_num_l("boot_params", (ulong)bd->bi_boot_params); - print_bi_dram(bd); + print_dram(bd); bdinfo_print_num_l("flashstart", (ulong)bd->bi_flashstart); bdinfo_print_num_l("flashsize", (ulong)bd->bi_flashsize); bdinfo_print_num_l("flashoffset", (ulong)bd->bi_flashoffset); @@ -199,7 +199,7 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) print_eth(); return CMD_RET_SUCCESS; case 'm': - print_bi_dram(bd); + print_dram(bd); return CMD_RET_SUCCESS; default: return CMD_RET_USAGE; diff --git a/cmd/ti/ddr4.c b/cmd/ti/ddr4.c index a8d71d11a91..36277cc154c 100644 --- a/cmd/ti/ddr4.c +++ b/cmd/ti/ddr4.c @@ -227,10 +227,10 @@ static int do_ddr4_ecc_inject(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - if (!((start_addr >= gd->bd->bi_dram[0].start && - (start_addr <= (gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - 1))) || - (start_addr >= gd->bd->bi_dram[1].start && - (start_addr <= (gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size - 1))))) { + if (!((start_addr >= gd->dram[0].start && + (start_addr <= (gd->dram[0].start + gd->dram[0].size - 1))) || + (start_addr >= gd->dram[1].start && + (start_addr <= (gd->dram[1].start + gd->dram[1].size - 1))))) { puts("Address is not in the DDR range\n"); return CMD_RET_FAILURE; } diff --git a/cmd/ufetch.c b/cmd/ufetch.c index e7b5d773f5e..763ab42c48a 100644 --- a/cmd/ufetch.c +++ b/cmd/ufetch.c @@ -202,8 +202,8 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc, printf("CPU: " RESET CONFIG_SYS_ARCH " (%d cores, 1 in use)\n", n_cpus); break; case MEMORY: - for (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->bd->bi_dram[j].size; j++) - size += gd->bd->bi_dram[j].size; + for (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->dram[j].size; j++) + size += gd->dram[j].size; printf("Memory:" RESET " "); print_size(size, "\n"); break; diff --git a/common/board_f.c b/common/board_f.c index fdb3577fec0..a3abec35271 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -222,11 +222,11 @@ static int show_dram_config(void) debug("\nRAM Configuration:\n"); for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; debug("Bank #%d: %llx ", i, - (unsigned long long)(gd->bd->bi_dram[i].start)); + (unsigned long long)(gd->dram[i].start)); #ifdef DEBUG - print_size(gd->bd->bi_dram[i].size, "\n"); + print_size(gd->dram[i].size, "\n"); #endif } debug("\nDRAM: "); @@ -244,8 +244,8 @@ static int show_dram_config(void) __weak int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); return 0; } diff --git a/common/init/handoff.c b/common/init/handoff.c index a7cd065fb38..a4d9d14393b 100644 --- a/common/init/handoff.c +++ b/common/init/handoff.c @@ -12,14 +12,13 @@ DECLARE_GLOBAL_DATA_PTR; void handoff_save_dram(struct spl_handoff *ho) { - struct bd_info *bd = gd->bd; int i; ho->ram_size = gd->ram_size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - ho->ram_bank[i].start = bd->bi_dram[i].start; - ho->ram_bank[i].size = bd->bi_dram[i].size; + ho->ram_bank[i].start = gd->dram[i].start; + ho->ram_bank[i].size = gd->dram[i].size; } } @@ -30,11 +29,10 @@ void handoff_load_dram_size(struct spl_handoff *ho) void handoff_load_dram_banks(struct spl_handoff *ho) { - struct bd_info *bd = gd->bd; int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - bd->bi_dram[i].start = ho->ram_bank[i].start; - bd->bi_dram[i].size = ho->ram_bank[i].size; + gd->dram[i].start = ho->ram_bank[i].start; + gd->dram[i].size = ho->ram_bank[i].size; } } diff --git a/drivers/bootcount/bootcount_ram.c b/drivers/bootcount/bootcount_ram.c index 33e157b865a..f726d9ab016 100644 --- a/drivers/bootcount/bootcount_ram.c +++ b/drivers/bootcount/bootcount_ram.c @@ -27,7 +27,7 @@ void bootcount_store(ulong a) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; save_addr = (ulong *)(size - BOOTCOUNT_ADDR); writel(a, save_addr); writel(CONFIG_SYS_BOOTCOUNT_MAGIC, &save_addr[1]); @@ -50,7 +50,7 @@ ulong bootcount_load(void) int i, tmp; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; save_addr = (ulong *)(size - BOOTCOUNT_ADDR); counter = readl(&save_addr[0]); diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index b36a765a5de..2d2b72cf766 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -104,7 +104,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); return -ENXIO; @@ -158,7 +158,7 @@ int sdram_mmr_init_full(struct udevice *dev) sdram_set_firewall(&bd); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; debug("DDR: HMC init success\n"); diff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c index ee66c72157a..d14e4bc5dcc 100644 --- a/drivers/ddr/altera/sdram_agilex5.c +++ b/drivers/ddr/altera/sdram_agilex5.c @@ -302,7 +302,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, gd->bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); ret = -ENXIO; @@ -345,19 +345,19 @@ int sdram_mmr_init_full(struct udevice *dev) for (i = 0; i < config_dram_banks; i++) { remaining_size = hw_size - size_counter; if (remaining_size <= dram_bank_info[i].max_size) { - gd->bd->bi_dram[i].start = dram_bank_info[i].start; - gd->bd->bi_dram[i].size = remaining_size; + gd->dram[i].start = dram_bank_info[i].start; + gd->dram[i].size = remaining_size; debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n", - i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); + i, gd->dram[i].start, gd->dram[i].size); break; } - gd->bd->bi_dram[i].start = dram_bank_info[i].start; - gd->bd->bi_dram[i].size = dram_bank_info[i].max_size; + gd->dram[i].start = dram_bank_info[i].start; + gd->dram[i].size = dram_bank_info[i].max_size; debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n", - i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); - size_counter += gd->bd->bi_dram[i].size; + i, gd->dram[i].start, gd->dram[i].size); + size_counter += gd->dram[i].size; } gd->ram_size = hw_size; @@ -408,7 +408,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("DDR: firewall init success\n"); - priv->info.base = gd->bd->bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; /* Ending DDR driver initialization success tracking */ diff --git a/drivers/ddr/altera/sdram_agilex7m.c b/drivers/ddr/altera/sdram_agilex7m.c index 9b3cc5c7b86..e4d522202d8 100644 --- a/drivers/ddr/altera/sdram_agilex7m.c +++ b/drivers/ddr/altera/sdram_agilex7m.c @@ -375,7 +375,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { printf("%s: Failed to decode memory node\n", memory_type_in_use(dev)); @@ -484,7 +484,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("%s: firewall init success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM")); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; /* Ending DDR driver initialization success tracking */ diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index c281f711fdf..9cc809b8001 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -674,9 +674,9 @@ static void sdram_size_check(void) debug("DDR: Running SDRAM size sanity check\n"); - ram_check = get_ram_size((long *)gd->bd->bi_dram[0].start, - gd->bd->bi_dram[0].size); - if (ram_check != gd->bd->bi_dram[0].size) { + ram_check = get_ram_size((long *)gd->dram[0].start, + gd->dram[0].size); + if (ram_check != gd->dram[0].size) { puts("DDR: SDRAM size check failed!\n"); hang(); } @@ -719,14 +719,14 @@ int ddr_calibration_sequence(void) /* setup the dram info within bd */ dram_init_banksize(); - if (gd->ram_size != gd->bd->bi_dram[0].size) { + if (gd->ram_size != gd->dram[0].size) { printf("DDR: Warning: DRAM size from device tree (%ld MiB)\n", - gd->bd->bi_dram[0].size >> 20); + gd->dram[0].size >> 20); printf(" mismatch with hardware (%ld MiB).\n", gd->ram_size >> 20); } - if (gd->bd->bi_dram[0].size > gd->ram_size) { + if (gd->dram[0].size > gd->ram_size) { printf("DDR: Error: DRAM size from device tree is greater\n"); printf(" than hardware size.\n"); hang(); diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 17ec6afa82b..900d4f59989 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -2279,7 +2279,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { debug("%s: Failed to decode memory node\n", __func__); return -1; @@ -2287,7 +2287,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("DDR: %lld MiB\n", gd->ram_size >> 20); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; sdram_size_check(&bd); diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 4ac4c79e0ac..6664090f86a 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -285,7 +285,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); return -1; @@ -328,7 +328,7 @@ int sdram_mmr_init_full(struct udevice *dev) sdram_size_check(&bd); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; debug("DDR: HMC init success\n"); diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 8ee7049b164..93df3d1812a 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -150,8 +150,8 @@ void sdram_init_ecc_bits(struct bd_info *bd) icache_enable(); - start_addr = bd->bi_dram[0].start; - size = bd->bi_dram[0].size; + start_addr = gd->dram[0].start; + size = gd->dram[0].size; /* Initialize small block for page table */ memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF); @@ -174,8 +174,8 @@ void sdram_init_ecc_bits(struct bd_info *bd) if (bank >= CONFIG_NR_DRAM_BANKS) break; - start_addr = bd->bi_dram[bank].start; - size = bd->bi_dram[bank].size; + start_addr = gd->dram[bank].start; + size = gd->dram[bank].size; } dcache_disable(); @@ -198,12 +198,12 @@ void sdram_size_check(struct bd_info *bd) phys_addr_t start = 0; phys_size_t remaining_size; - start = bd->bi_dram[bank].start; - remaining_size = bd->bi_dram[bank].size; + start = gd->dram[bank].start; + remaining_size = gd->dram[bank].size; debug("Checking bank %d: start=0x%llx, size=0x%llx\n", bank, start, remaining_size); - while (ram_check < bd->bi_dram[bank].size) { + while (ram_check < gd->dram[bank].size) { phys_size_t size, test_size, detected_size; size = min((phys_addr_t)SZ_1G, (phys_addr_t)remaining_size); @@ -232,7 +232,7 @@ void sdram_size_check(struct bd_info *bd) } ram_check += detected_size; - remaining_size = bd->bi_dram[bank].size - ram_check; + remaining_size = gd->dram[bank].size - ram_check; } total_ram_check += ram_check; @@ -292,10 +292,10 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) u32 lower, upper; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (!bd->bi_dram[i].size) + if (!gd->dram[i].size) continue; - value = bd->bi_dram[i].start; + value = gd->dram[i].start; /* Keep first 1MB of SDRAM memory region as secure region when * using ATF flow, where the ATF code is located. @@ -322,7 +322,7 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) (i * 4 * sizeof(u32))); /* Setting non-secure MPU limit and limit extended */ - value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; + value = gd->dram[i].start + gd->dram[i].size - 1; lower = lower_32_bits(value); upper = upper_32_bits(value); @@ -354,10 +354,10 @@ static void sdram_set_firewall_f2sdram(struct bd_info *bd) phys_size_t value; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (!bd->bi_dram[i].size) + if (!gd->dram[i].size) continue; - value = bd->bi_dram[i].start; + value = gd->dram[i].start; /* Keep first 1MB of SDRAM memory region as secure region when * using ATF flow, where the ATF code is located. @@ -376,7 +376,7 @@ static void sdram_set_firewall_f2sdram(struct bd_info *bd) (i * 4 * sizeof(u32))); /* Setting limit and limit extended */ - value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; + value = gd->dram[i].start + gd->dram[i].size - 1; lower = lower_32_bits(value); upper = upper_32_bits(value); diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c index 5af1953cd14..89d511c1a6f 100644 --- a/drivers/mmc/mvebu_mmc.c +++ b/drivers/mmc/mvebu_mmc.c @@ -375,8 +375,8 @@ static void mvebu_window_setup(const struct mmc *mmc) break; } - size = gd->bd->bi_dram[i].size; - base = gd->bd->bi_dram[i].start; + size = gd->dram[i].size; + base = gd->dram[i].start; if (size && attrib) { mvebu_mmc_write(mmc, WINDOW_CTRL(i), MVCPU_WIN_CTRL_DATA(size, diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 107a33aa9f5..4dc738980cb 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -256,8 +256,8 @@ static void set_dram_access(struct mvgbe_registers *regs) win_param.access_ctrl = EWIN_ACCESS_FULL; win_param.high_addr = 0; /* Get bank base and size */ - win_param.base_addr = gd->bd->bi_dram[i].start; - win_param.size = gd->bd->bi_dram[i].size; + win_param.base_addr = gd->dram[i].start; + win_param.size = gd->dram[i].size; if (win_param.size == 0) win_param.enable = 0; else diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index f58d542ef75..4bdd1f7477f 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1126,14 +1126,14 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, return 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - phys_addr_t start = bd->bi_dram[i].start; + if (gd->dram[i].size) { + phys_addr_t start = gd->dram[i].start; if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY)) - start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start); + start = virt_to_phys((void *)(uintptr_t)gd->dram[i].start); pci_set_region(hose->regions + hose->region_count++, - start, start, bd->bi_dram[i].size, + start, start, gd->dram[i].size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); } } diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 794a4168913..38ee17f063d 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -222,8 +222,8 @@ static void usb_brg_adrdec_setup(int index) break; } - size = gd->bd->bi_dram[i].size; - base = gd->bd->bi_dram[i].start; + size = gd->dram[i].size; + base = gd->dram[i].start; if ((size) && (attrib)) writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM, attrib, MVCPU_WIN_ENABLE), diff --git a/drivers/video/meson/meson_vpu.c b/drivers/video/meson/meson_vpu.c index ca627728743..a686faf9f58 100644 --- a/drivers/video/meson/meson_vpu.c +++ b/drivers/video/meson/meson_vpu.c @@ -81,8 +81,8 @@ cvbs: meson_fb.fb_size = ALIGN(meson_fb.xsize * meson_fb.ysize * ((1 << VPU_MAX_LOG2_BPP) / 8) + MESON_VPU_OVERSCAN, EFI_PAGE_SIZE); - meson_fb.base = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - meson_fb.fb_size; + meson_fb.base = gd->dram[0].start + + gd->dram[0].size - meson_fb.fb_size; /* Override the framebuffer address */ uc_plat->base = meson_fb.base; @@ -175,8 +175,8 @@ static void meson_vpu_setup_simplefb(void *fdt) * at the end of the RAM and we strip this portion from the kernel * allowed region */ - mem_start = gd->bd->bi_dram[0].start; - mem_size = gd->bd->bi_dram[0].size - meson_fb.fb_size; + mem_start = gd->dram[0].start; + mem_size = gd->dram[0].size - meson_fb.fb_size; ret = fdt_fixup_memory_banks(fdt, &mem_start, &mem_size, 1); if (ret) { eprintf("Cannot setup simplefb: Error reserving memory\n"); diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index 154641b9a69..ab36ee1595b 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -368,7 +368,7 @@ int sunxi_simplefb_setup(void *blob) return 0; /* Keep older kernels working */ } - start = gd->bd->bi_dram[0].start; + start = gd->dram[0].start; size = de2_plat->base - start; ret = fdt_fixup_memory_banks(blob, &start, &size, 1); if (ret) { diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 4a6a89ef9d2..fa492c661db 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -1336,7 +1336,7 @@ int sunxi_simplefb_setup(void *blob) * and e.g. Linux refuses to iomap RAM on ARM, see: * linux/arch/arm/mm/ioremap.c around line 301. */ - start = gd->bd->bi_dram[0].start; + start = gd->dram[0].start; size = sunxi_display->fb_addr - start; ret = fdt_fixup_memory_banks(blob, &start, &size, 1); if (ret) { diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index ba6a10cf2ad..ad7ebb1bbc9 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -457,6 +457,13 @@ struct global_data { */ struct upl *upl; #endif + /** + * @dram: array describing DRAM banks (start address and size for each bank) + */ + struct { /* RAM configuration */ + phys_addr_t start; + phys_size_t size; + } dram[CONFIG_NR_DRAM_BANKS]; }; #ifndef DO_DEPS_ONLY static_assert(sizeof(struct global_data) == GD_SIZE); diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 8c619c1b74a..931fe2f3274 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -59,10 +59,6 @@ struct bd_info { #endif ulong bi_arch_number; /* unique id for this board */ ulong bi_boot_params; /* where this board expects params */ - struct { /* RAM configuration */ - phys_addr_t start; - phys_size_t size; - } bi_dram[CONFIG_NR_DRAM_BANKS]; }; #endif /* __ASSEMBLY__ */ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index a6aafb51854..36e330887cd 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -15,9 +15,9 @@ * Memory configurations */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 2bd1426c7d9..e823611d2e4 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -51,9 +51,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 14095b99f03..acd6eb6f8ac 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -86,9 +86,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 3707de254e1..65babf50546 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -81,9 +81,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/fdtdec.h b/include/fdtdec.h index 46eaa0da63c..51d9f14a9f2 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -57,6 +57,7 @@ struct fdt_memory { }; struct bd_info; +struct global_data; /** * enum fdt_source_t - indicates where the devicetree came from @@ -974,7 +975,7 @@ int fdtdec_setup_mem_size_base(void); int fdtdec_setup_mem_size_base_lowest(void); /** - * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram + * fdtdec_setup_memory_banksize() - decode and populate gd->dram * * Decode the /memory 'reg' property to determine the address and size of the * memory banks. Use this data to populate the global data board info with the @@ -1256,12 +1257,12 @@ int board_fdt_blob_setup(void **fdtp); * @param basep Returns base address of first memory bank (NULL to * ignore) * @param sizep Returns total memory size (NULL to ignore) - * @param bd Updated with the memory bank information (NULL to skip) + * @param gd_ptr Updated with the memory bank information (NULL to skip) * Return: 0 if OK, -ve on error */ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, phys_addr_t *basep, phys_size_t *sizep, - struct bd_info *bd); + struct global_data *gd_ptr); /** * fdtdec_get_srcname() - Get the name of where the devicetree comes from diff --git a/include/init.h b/include/init.h index c31ebd83b85..23466d3f153 100644 --- a/include/init.h +++ b/include/init.h @@ -80,7 +80,7 @@ int dram_init(void); * dram_init_banksize() - Set up DRAM bank sizes * * This can be implemented by boards to set up the DRAM bank information in - * gd->bd->bi_dram(). It is called just before relocation, after dram_init() + * gd->dram[] It is called just before relocation, after dram_init() * is called. * * If this is not provided, a default implementation will try to set up a diff --git a/lib/fdtdec.c b/lib/fdtdec.c index d0a84b5034b..b91e067106d 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -35,6 +35,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -1142,14 +1143,14 @@ int fdtdec_setup_memory_banksize(void) if (ret != 0) return -EINVAL; - gd->bd->bi_dram[bank].start = (phys_addr_t)res.start; - gd->bd->bi_dram[bank].size = + gd->dram[bank].start = (phys_addr_t)res.start; + gd->dram[bank].size = (phys_size_t)(res.end - res.start + 1); debug("%s: DRAM Bank #%d: start = %pap, size = %pap\n", __func__, bank, - &gd->bd->bi_dram[bank].start, - &gd->bd->bi_dram[bank].size); + &gd->dram[bank].start, + &gd->dram[bank].size); } return 0; @@ -1930,7 +1931,7 @@ int fdtdec_resetup(int *rescan) int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, phys_addr_t *basep, phys_size_t *sizep, - struct bd_info *bd) + gd_t *gd_ptr) { int addr_cells, size_cells; const u32 *cell, *end; @@ -1982,8 +1983,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, } /* Note: if no matching subnode was found we use the parent node */ - if (bd) { - memset(bd->bi_dram, '\0', sizeof(bd->bi_dram[0]) * + if (gd_ptr) { + memset(gd_ptr->dram, '\0', sizeof(gd_ptr->dram[0]) * CONFIG_NR_DRAM_BANKS); } @@ -1999,8 +2000,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, if (addr_cells == 2) addr += (u64)fdt32_to_cpu(*cell++) << 32UL; addr += fdt32_to_cpu(*cell++); - if (bd) - bd->bi_dram[bank].start = addr; + if (gd_ptr) + gd_ptr->dram[bank].start = addr; if (basep && !bank) *basep = (phys_addr_t)addr; @@ -2022,8 +2023,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, } } - if (bd) - bd->bi_dram[bank].size = size; + if (gd_ptr) + gd_ptr->dram[bank].size = size; total_size += size; } diff --git a/lib/lmb.c b/lib/lmb.c index 779df35eb9c..77440a48486 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -555,12 +555,12 @@ static void lmb_reserve_uboot_region(void) #endif for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (!gd->bd->bi_dram[bank].size || - rsv_start < gd->bd->bi_dram[bank].start) + if (!gd->dram[bank].size || + rsv_start < gd->dram[bank].start) continue; /* Watch out for RAM at end of address space! */ - bank_end = gd->bd->bi_dram[bank].start + - gd->bd->bi_dram[bank].size - 1; + bank_end = gd->dram[bank].start + + gd->dram[bank].size - 1; if (rsv_start > bank_end) continue; if (bank_end > end) @@ -615,7 +615,6 @@ static void lmb_add_memory(void) phys_addr_t bank_end; phys_size_t size; u64 ram_top = gd->ram_top; - struct bd_info *bd = gd->bd; if (CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP)) return lmb_arch_add_memory(); @@ -625,22 +624,22 @@ static void lmb_add_memory(void) ram_top = 0x100000000ULL; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - size = bd->bi_dram[i].size; + size = gd->dram[i].size; if (size) { - lmb_add(bd->bi_dram[i].start, size); + lmb_add(gd->dram[i].start, size); if (!IS_ENABLED(CONFIG_LMB_LIMIT_DMA_BELOW_RAM_TOP)) continue; - bank_end = bd->bi_dram[i].start + size; + bank_end = gd->dram[i].start + size; /* * Reserve memory above ram_top as * no-overwrite so that it cannot be * allocated */ - if (bd->bi_dram[i].start >= ram_top) - lmb_reserve(bd->bi_dram[i].start, size, + if (gd->dram[i].start >= ram_top) + lmb_reserve(gd->dram[i].start, size, LMB_NOOVERWRITE); else if (bank_end > ram_top) lmb_reserve(ram_top, bank_end - ram_top, diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c index 7f4f1868c6a..7b7fb0894dd 100644 --- a/test/cmd/bdinfo.c +++ b/test/cmd/bdinfo.c @@ -138,16 +138,15 @@ static int lmb_test_dump_all(struct unit_test_state *uts) static int bdinfo_check_mem(struct unit_test_state *uts) { - struct bd_info *bd = gd->bd; int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { + if (gd->dram[i].size) { ut_assertok(test_num_l(uts, "DRAM bank", i)); ut_assertok(test_num_ll(uts, "-> start", - bd->bi_dram[i].start)); + gd->dram[i].start)); ut_assertok(test_num_ll(uts, "-> size", - bd->bi_dram[i].size)); + gd->dram[i].size)); } } -- cgit v1.3.1 From 599fd74e0c5ac8e0c420b7a48b619d36dcf211d9 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Wed, 10 Jun 2026 13:24:22 +0000 Subject: mx7ulp_evk: Move environment variables to .env file Move the board environment from CFG_EXTRA_ENV_SETTINGS in the config header to board/nxp/mx7ulp_evk/mx7ulp_evk.env for better maintainability. The file is named after CONFIG_SYS_BOARD so it is selected automatically without setting CONFIG_ENV_SOURCE_FILE. The generated default environment is unchanged. This was verified by comparing the output of scripts/get_default_envs.sh before and after the change, which produced identical results. Signed-off-by: Aristo Chen Reviewed-by: Peng Fan --- board/nxp/mx7ulp_evk/mx7ulp_evk.env | 59 ++++++++++++++++++++++++++++++++++ include/configs/mx7ulp_evk.h | 63 ------------------------------------- 2 files changed, 59 insertions(+), 63 deletions(-) create mode 100644 board/nxp/mx7ulp_evk/mx7ulp_evk.env (limited to 'include') diff --git a/board/nxp/mx7ulp_evk/mx7ulp_evk.env b/board/nxp/mx7ulp_evk/mx7ulp_evk.env new file mode 100644 index 00000000000..f5a384a61de --- /dev/null +++ b/board/nxp/mx7ulp_evk/mx7ulp_evk.env @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +console=ttyLP0 +initrd_high=0xffffffff +fdt_file=imx7ulp-evk.dtb +fdt_addr=0x63000000 +boot_fdt=try +earlycon=lpuart32,0x402D0010 +ip_dyn=yes +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk0p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + usb start; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 21dbec837f0..f36265f13e6 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -24,69 +24,6 @@ #define PHYS_SDRAM_SIZE SZ_1G #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttyLP0\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx7ulp-evk.dtb\0" \ - "fdt_addr=0x63000000\0" \ - "boot_fdt=try\0" \ - "earlycon=lpuart32,0x402D0010\0" \ - "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "usb start; "\ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE SZ_256K -- cgit v1.3.1 From 4377bd764ca861479a33683457f3ecac7317dd16 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Wed, 10 Jun 2026 13:24:23 +0000 Subject: mx6ullevk: Move environment variables to .env file Move the board environment from CFG_EXTRA_ENV_SETTINGS in the config header to board/nxp/mx6ullevk/mx6ullevk.env for better maintainability. The file is named after CONFIG_SYS_BOARD so it is selected automatically without setting CONFIG_ENV_SOURCE_FILE. Drop the now unused linux/stringify.h include. The generated default environment is unchanged. This was verified by comparing the output of scripts/get_default_envs.sh before and after the change, which produced identical results. Signed-off-by: Aristo Chen Reviewed-by: Peng Fan --- board/nxp/mx6ullevk/mx6ullevk.env | 69 ++++++++++++++++++++++++++++++++++++ include/configs/mx6ullevk.h | 73 --------------------------------------- 2 files changed, 69 insertions(+), 73 deletions(-) create mode 100644 board/nxp/mx6ullevk/mx6ullevk.env (limited to 'include') diff --git a/board/nxp/mx6ullevk/mx6ullevk.env b/board/nxp/mx6ullevk/mx6ullevk.env new file mode 100644 index 00000000000..0fce3aaaa4e --- /dev/null +++ b/board/nxp/mx6ullevk/mx6ullevk.env @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +console=ttymxc0 +initrd_high=0xffffffff +fdt_file=undefined +fdt_addr=0x83000000 +boot_fdt=try +ip_dyn=yes +videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +findfdt=if test $fdt_file = undefined; then + if test $board_name = ULZ-EVK && test $board_rev = 14X14; then + setenv fdt_file imx6ulz-14x14-evk.dtb; + fi; + if test $board_name = EVK && test $board_rev = 14X14; then + setenv fdt_file imx6ull-14x14-evk.dtb; + fi; + if test $fdt_file = undefined; then + echo WARNING: Could not determine dtb to use; + fi; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 88b535e1bd0..a535163fd19 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -9,7 +9,6 @@ #include #include -#include #include "mx6_common.h" #include @@ -23,78 +22,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=undefined\0" \ - "fdt_addr=0x83000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ - "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test $fdt_file = undefined; then " \ - "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \ - "setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \ - "if test $board_name = EVK && test $board_rev = 14X14; then " \ - "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \ - "if test $fdt_file = undefined; then " \ - "echo WARNING: Could not determine dtb to use; " \ - "fi; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - /* Miscellaneous configurable options */ /* Physical Memory Map */ -- cgit v1.3.1 From 8d21d74bdf1f43ba2e50234cbf37429b8b065b72 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Wed, 10 Jun 2026 13:24:24 +0000 Subject: mx6sabre: Move environment variables to .env files Move the shared environment from CFG_EXTRA_ENV_SETTINGS in mx6sabre_common.h to a common text environment fragment in include/env/nxp/mx6sabre_common.env. The mx6sabresd and mx6sabreauto board environments include this fragment and add their own console setting, which is the only board specific difference between them. The eMMC firmware update variables remain guarded by CONFIG_SUPPORT_EMMC_BOOT inside the fragment. The now unused CONSOLE_DEV defines and the linux/stringify.h include are dropped. The generated default environment is unchanged for both boards. This was verified by comparing the output of scripts/get_default_envs.sh before and after the change, which produced identical results. Signed-off-by: Aristo Chen Reviewed-by: Peng Fan --- board/nxp/mx6sabreauto/mx6sabreauto.env | 5 ++ board/nxp/mx6sabresd/mx6sabresd.env | 5 ++ include/configs/mx6sabre_common.h | 122 -------------------------------- include/configs/mx6sabreauto.h | 1 - include/configs/mx6sabresd.h | 1 - include/env/nxp/mx6sabre_common.env | 114 +++++++++++++++++++++++++++++ 6 files changed, 124 insertions(+), 124 deletions(-) create mode 100644 board/nxp/mx6sabreauto/mx6sabreauto.env create mode 100644 board/nxp/mx6sabresd/mx6sabresd.env create mode 100644 include/env/nxp/mx6sabre_common.env (limited to 'include') diff --git a/board/nxp/mx6sabreauto/mx6sabreauto.env b/board/nxp/mx6sabreauto/mx6sabreauto.env new file mode 100644 index 00000000000..31a16905ef5 --- /dev/null +++ b/board/nxp/mx6sabreauto/mx6sabreauto.env @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +console=ttymxc3 + +#include diff --git a/board/nxp/mx6sabresd/mx6sabresd.env b/board/nxp/mx6sabresd/mx6sabresd.env new file mode 100644 index 00000000000..3608e931665 --- /dev/null +++ b/board/nxp/mx6sabresd/mx6sabresd.env @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +console=ttymxc0 + +#include diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index ef2848b71f3..d3a57a10a16 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -8,133 +8,11 @@ #ifndef __MX6QSABRE_COMMON_CONFIG_H #define __MX6QSABRE_COMMON_CONFIG_H -#include - #include "mx6_common.h" /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#ifdef CONFIG_SUPPORT_EMMC_BOOT -#define EMMC_ENV \ - "emmcdev=2\0" \ - "update_emmc_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "if mmc dev ${emmcdev} 1; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" -#else -#define EMMC_ENV "" -#endif - -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdtfile=undefined\0" \ - "fdt_addr=0x18000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "console=" CONSOLE_DEV "\0" \ - "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ - "dfu_alt_info_spl=spl raw 0x400\0" \ - "dfu_alt_info_img=u-boot raw 0x10000\0" \ - "dfu_alt_info=spl raw 0x400\0" \ - "initrd_high=0xffffffff\0" \ - "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "mmcdev=" __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) "\0" \ - "mmcpart=1\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - EMMC_ENV \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ - "loadbootscript=" \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || " \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || " \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || " \ - "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test $fdtfile = undefined; then " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ - "setenv fdtfile imx6qp-sabreauto.dtb; fi; " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ - "setenv fdtfile imx6q-sabreauto.dtb; fi; " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ - "setenv fdtfile imx6dl-sabreauto.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \ - "setenv fdtfile imx6qp-sabresd.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ - "setenv fdtfile imx6q-sabresd.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ - "setenv fdtfile imx6dl-sabresd.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; " \ - "fi;\0" \ - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index e491af3e927..b5602def87d 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -9,7 +9,6 @@ #define __MX6SABREAUTO_CONFIG_H #define CFG_MXC_UART_BASE UART4_BASE -#define CONSOLE_DEV "ttymxc3" #define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index e34947c94d0..1ea08f835dd 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -9,7 +9,6 @@ #define __MX6SABRESD_CONFIG_H #define CFG_MXC_UART_BASE UART1_BASE -#define CONSOLE_DEV "ttymxc0" #include "mx6sabre_common.h" diff --git a/include/env/nxp/mx6sabre_common.env b/include/env/nxp/mx6sabre_common.env new file mode 100644 index 00000000000..5346cd4e953 --- /dev/null +++ b/include/env/nxp/mx6sabre_common.env @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +fdtfile=undefined +fdt_addr=0x18000000 +boot_fdt=try +ip_dyn=yes +dfuspi=dfu 0 sf 0:0:10000000:0 +dfu_alt_info_spl=spl raw 0x400 +dfu_alt_info_img=u-boot raw 0x10000 +dfu_alt_info=spl raw 0x400 +initrd_high=0xffffffff +splashimage=CONFIG_SYS_LOAD_ADDR +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +finduuid=part uuid mmc ${mmcdev}:2 uuid +update_sd_firmware=if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if mmc dev ${mmcdev}; then + if ${get_cmd} ${update_sd_firmware_filename}; then + setexpr fw_sz ${filesize} / 0x200; + setexpr fw_sz ${fw_sz} + 1; + mmc write ${loadaddr} 0x2 ${fw_sz}; + fi; + fi +#ifdef CONFIG_SUPPORT_EMMC_BOOT +emmcdev=2 +update_emmc_firmware=if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if ${get_cmd} ${update_sd_firmware_filename}; then + if mmc dev ${emmcdev} 1; then + setexpr fw_sz ${filesize} / 0x200; + setexpr fw_sz ${fw_sz} + 1; + mmc write ${loadaddr} 0x2 ${fw_sz}; + fi; + fi +#endif +mmcargs=setenv bootargs console=${console},${baudrate} root=PARTUUID=${uuid} rootwait rw +loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || + load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || + load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image} +loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || + load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile} +mmcboot=echo Booting from mmc ...; + run finduuid; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdtfile}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +findfdt=if test $fdtfile = undefined; then + if test $board_name = SABREAUTO && test $board_rev = MX6QP; then + setenv fdtfile imx6qp-sabreauto.dtb; + fi; + if test $board_name = SABREAUTO && test $board_rev = MX6Q; then + setenv fdtfile imx6q-sabreauto.dtb; + fi; + if test $board_name = SABREAUTO && test $board_rev = MX6DL; then + setenv fdtfile imx6dl-sabreauto.dtb; + fi; + if test $board_name = SABRESD && test $board_rev = MX6QP; then + setenv fdtfile imx6qp-sabresd.dtb; + fi; + if test $board_name = SABRESD && test $board_rev = MX6Q; then + setenv fdtfile imx6q-sabresd.dtb; + fi; + if test $board_name = SABRESD && test $board_rev = MX6DL; then + setenv fdtfile imx6dl-sabresd.dtb; + fi; + if test $fdtfile = undefined; then + echo WARNING: Could not determine dtb to use; + fi; + fi; -- cgit v1.3.1 From 3ac3708d168e1f85616817aae077326a6786ab59 Mon Sep 17 00:00:00 2001 From: Franz Schnyder Date: Thu, 11 Jun 2026 15:47:48 +0200 Subject: board: toradex: add initial support for aquila imx95 Add initial U-Boot support for Aquila iMX95 SoM. Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit Signed-off-by: Franz Schnyder Reviewed-by: Francesco Dolcini --- arch/arm/dts/imx95-aquila-dev-u-boot.dtsi | 40 + arch/arm/dts/imx95-aquila-dev.dts | 389 +++++++++ arch/arm/dts/imx95-aquila.dtsi | 1160 +++++++++++++++++++++++++++ arch/arm/mach-imx/imx9/Kconfig | 5 + board/toradex/aquila-imx95/Kconfig | 36 + board/toradex/aquila-imx95/MAINTAINERS | 11 + board/toradex/aquila-imx95/Makefile | 8 + board/toradex/aquila-imx95/aquila-imx95.c | 23 + board/toradex/aquila-imx95/aquila-imx95.env | 20 + board/toradex/aquila-imx95/spl.c | 75 ++ configs/aquila-imx95_defconfig | 186 +++++ doc/board/toradex/aquila-imx95.rst | 175 ++++ doc/board/toradex/index.rst | 1 + include/configs/aquila-imx95.h | 28 + 14 files changed, 2157 insertions(+) create mode 100644 arch/arm/dts/imx95-aquila-dev-u-boot.dtsi create mode 100644 arch/arm/dts/imx95-aquila-dev.dts create mode 100644 arch/arm/dts/imx95-aquila.dtsi create mode 100644 board/toradex/aquila-imx95/Kconfig create mode 100644 board/toradex/aquila-imx95/MAINTAINERS create mode 100644 board/toradex/aquila-imx95/Makefile create mode 100644 board/toradex/aquila-imx95/aquila-imx95.c create mode 100644 board/toradex/aquila-imx95/aquila-imx95.env create mode 100644 board/toradex/aquila-imx95/spl.c create mode 100644 configs/aquila-imx95_defconfig create mode 100644 doc/board/toradex/aquila-imx95.rst create mode 100644 include/configs/aquila-imx95.h (limited to 'include') diff --git a/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi b/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi new file mode 100644 index 00000000000..92ec0d3efa3 --- /dev/null +++ b/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) Toradex */ + +#include "imx95-u-boot.dtsi" + +/ { + sysinfo { + compatible = "toradex,sysinfo"; + }; +}; + +&lpuart1 { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&usb3 { + bootph-pre-ram; +}; + +&usb3_dwc3 { + bootph-pre-ram; + compatible = "fsl,imx95a-dwc3", "fsl,imx8mq-dwc3", "snps,dwc3"; +}; + +&usdhc1 { + bootph-pre-ram; +}; + diff --git a/arch/arm/dts/imx95-aquila-dev.dts b/arch/arm/dts/imx95-aquila-dev.dts new file mode 100644 index 00000000000..3df17700b63 --- /dev/null +++ b/arch/arm/dts/imx95-aquila-dev.dts @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/aquila-development-board-kit + */ + +/dts-v1/; + +#include +#include +#include "imx95-aquila.dtsi" + +/ { + model = "Aquila iMX95 on Aquila Development Board"; + compatible = "toradex,aquila-imx95-dev", + "toradex,aquila-imx95", + "fsl,imx95"; + + aliases { + eeprom1 = &carrier_eeprom; + }; + + dp_1_connector: dp0-connector { + compatible = "dp-connector"; + dp-pwr-supply = <®_dp_3p3v>; + type = "full-size"; + + port { + dp_1_connector_in: endpoint { + remote-endpoint = <&dsi2dp_out>; + }; + }; + }; + + reg_carrier_1p8v: regulator-carrier-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-carrier 1V8"; + }; + + reg_dp_3p3v: regulator-dp-3p3v { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_21_dp>; + /* Aquila GPIO_21_DP */ + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "DP_3V3"; + startup-delay-us = <10000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "aquila-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack", + "IN1R", "Digital Mic"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Microphone", "Digital Mic", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +/* Aquila ADC_[1-4] */ +&adc1 { + status = "okay"; +}; + +/* Aquila CTRL_WAKE1_MICO# */ +&aquila_key_wake { + status = "okay"; +}; + +&dsi2dp_out { + remote-endpoint = <&dp_1_connector_in>; +}; + +/* Aquila ETH_1 */ +&enetc_port0 { + status = "okay"; +}; + +/* Aquila CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Aquila CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +/* Aquila CAN_3 */ +&flexcan3 { + status = "okay"; +}; + +/* Aquila CAN_4 */ +&flexcan4 { + status = "okay"; +}; + +/* Aquila QSPI_1 */ +&flexspi1 { + pinctrl-0 = <&pinctrl_flexspi1_4bit>, + <&pinctrl_qspi_cs1>; + + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_8>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>; +}; + +/* Aquila I2C_1 */ +&lpi2c2 { + status = "okay"; + + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan { + cooling-levels = <255>; + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; + + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_mclk>; + clocks = <&scmi_clk IMX95_CLK_SAI2>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + AVDD-supply = <®_carrier_1p8v>; + CPVDD-supply = <®_carrier_1p8v>; + DBVDD-supply = <®_carrier_1p8v>; + DCVDD-supply = <®_carrier_1p8v>; + MICVDD-supply = <®_carrier_1p8v>; + wlf,drc-cfg-names = "default", "peaklimiter"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + wlf,in1r-as-dmicdat2; + }; + + /* Current measurement into module VCC */ + hwmon@41 { + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + /* USB-C OTG (TCPC USB PD PHY) */ + tcpc@52 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x52>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + op-sink-microwatt = <0>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb1_con_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb1_con_ss>; + }; + }; + }; + }; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_2 */ +&i3c2 { + status = "okay"; +}; + +/* Aquila I2C_4_CSI1 */ +&lpi2c4 { + status = "okay"; +}; + +/* Aquila I2C_6 */ +&lpi2c5 { + status = "okay"; +}; + +/* Aquila I2C_3_DSI1/I2C_5_CSI2 */ +&lpi2c8 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + /* I2C on DSI Connector Pin #4 and #6 */ + i2c_dsi_0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* I2C on DSI Connector Pin #52 and #54 */ + i2c_dsi_1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* Aquila SPI_1 */ +&lpspi6 { + status = "okay"; +}; + +/* Aquila UART_3, used as the Linux Console */ +&lpuart1 { + status = "okay"; +}; + +/* Aquila UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Aquila UART_1 */ +&lpuart3 { + status = "okay"; +}; + +/* Aquila UART_2 as RS485 */ +&lpuart7 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + + status = "okay"; +}; + +/* Aquila PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Aquila I2S_1 */ +&sai2 { + status = "okay"; +}; + +/* Aquila PWM_1 */ +&tpm3 { + status = "okay"; +}; + +/* Aquila PWM_2 */ +&tpm6 { + status = "okay"; +}; + +/* Aquila PWM_3_DSI and PWM_4_DP */ +&tpm5 { + status = "okay"; +}; + +/* Aquila USB_2, optional Bluetooth USB */ +&usb2 { + status = "okay"; +}; + +/* Aquila USB_1 */ +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + status = "okay"; + + port { + usb1_con_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + + status = "okay"; + + port { + usb1_con_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +/* Aquila SD_1 */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx95-aquila.dtsi b/arch/arm/dts/imx95-aquila.dtsi new file mode 100644 index 00000000000..69dc962a24a --- /dev/null +++ b/arch/arm/dts/imx95-aquila.dtsi @@ -0,0 +1,1160 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 + */ + +#include +#include "imx95.dtsi" + +/ { + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + can3 = &flexcan4; + eeprom0 = &som_eeprom; + ethernet0 = &enetc_port0; + i2c0 = &lpi2c3; + i2c1 = &lpi2c2; + i2c2 = &i3c2; + i2c3 = &lpi2c8; + i2c4 = &lpi2c4; + i2c6 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &rtc_i2c; + rtc1 = &scmi_bbm; + serial0 = &lpuart3; + serial1 = &lpuart7; + serial2 = &lpuart1; + serial3 = &lpuart2; + usb0 = &usb3; + usb1 = &usb2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + aquila_key_wake: gpio-key-wakeup { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + + status = "disabled"; + + key-wakeup { + /* Aquila CTRL_WAKE1_MICO# */ + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + label = "Wake Up"; + wakeup-source; + linux,code = ; + }; + }; + + clk_dsi2dp_refclk: clock-dsi2dp-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_dsi2dp_refclk_en: clock-dsi2dp-refclk-en { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_dp_clk_en>; + clocks = <&clk_dsi2dp_refclk>; + #clock-cells = <0>; + /* CTRL_DP_CLK_EN */ + enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + clk_serdes_eth_ref: clock-serdes-eth-ref { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + /* CTRL_ETH_REF_CLK_STBY */ + enable-gpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_LOW>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8"; + }; + + reg_dp_1p2v: regulator-dp-1p2v { + compatible = "regulator-fixed"; + /* CTRL_DP_BRIDGE_EN */ + gpios = <&som_gpio_expander_0 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "On-module +V1.2_DP"; + vin-supply = <®_1p8v>; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + /* Aquila USB_1_EN */ + gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_1_EN"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + /* Aquila USB_2_EN */ + gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_2_H_EN"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_pwr_en>; + /* Aquila SD_1_PWR_EN */ + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "SD_1_PWR_EN"; + startup-delay-us = <20000>; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + /* PMIC_SD_1_VSEL */ + gpios = <&som_gpio_expander_1 9 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "PMIC_SD_1_VSEL"; + states = <1800000 0x1>, + <3300000 0x0>; + }; + + remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mboxes = <&mu7 0 1 &mu7 1 1 &mu7 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + linux,cma-default; + }; + + m7_reserved: memory@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + }; +}; + +/* Aquila ADC_[1-4] */ +&adc1 { + vref-supply = <®_1p8v>; +}; + +/* Aquila ETH_1 */ +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; +}; + +/* Aquila CAN_1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* Aquila CAN_2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* Aquila CAN_3 */ +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; +}; + +/* Aquila CAN_4 */ +&flexcan4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan4>; +}; + +/* Aquila QSPI_1 */ +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1_8bit>, + <&pinctrl_qspi_cs1>; +}; + +&gpio1 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AQUILA_C24", /* 10 */ + "", + "AQUILA_B17", + "CTRL_GPIO_EXP_INT#", + "AQUILA_B18"; + + status = "okay"; +}; + +&gpio2 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "AQUILA_B42", + "", + "AQUILA_B43"; +}; + +&gpio3 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "AQUILA_A11", + "", /* 20 */ + "AQUILA_B57", + "AQUILA_B19"; +}; + +&gpio4 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "AQUILA_C22", + "AQUILA_C21", + "AQUILA_C20", + "", /* 20 */ + "", + "", + "AQUILA_C23", + "AQUILA_D23", + "AQUILA_D24", + "", + "AQUILA_D25"; +}; + +&gpio5 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "AQUILA_B44", + "AQUILA_B45"; +}; + +/* Aquila I2C_2 */ +&i3c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c2>; + i2c-scl-hz = <100000>; +}; + +/* Aquila I2C_1 */ +&lpi2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* On-module I2C - I2C_SOM */ +&lpi2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>, <&pinctrl_ctrl_gpio_exp_int>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>, <&pinctrl_ctrl_gpio_exp_int>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + status = "okay"; + + som_gpio_expander_0: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "AQUILA_C38", /* 0 */ + "PCIE_2_RESET#", + "AQUILA_B77", + "USB_2_H_EN", + "BT_DISABLE#", + "WIFI_DISABLE#", + "CTRL_ETH_REF_CLK_STBY", + "CTRL_DP_BRIDGE_EN"; + }; + + som_gpio_expander_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "AQUILA_C1", /* 0 */ + "AQUILA_C2", + "AQUILA_C3", + "AQUILA_C4", + "AQUILA_C36", + "AQUILA_B74", + "AQUILA_B75", + "USB_2_H_OC#", + "AQUILA_B81", + "PMIC_SD_1_VSEL", + "ETH_1_INT#", /* 10 */ + "CTRL_TPM_INT#", + "SPI_2_CS2_TPM", + "PCIE_WAKE_WIFI#", + "WIFI_WAKE_BT", + "WIFI_WAKEUP_HOST"; + }; + + som_dsi2dp_bridge: bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + clocks = <&clk_dsi2dp_refclk_en>; + clock-names = "refclk"; + vcc-supply = <®_dp_1p2v>; + vcca-supply = <®_dp_1p2v>; + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi2dp_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + + dsi2dp_out: endpoint { + data-lanes = <3 2 1 0>; + }; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_4_CSI1 */ +&lpi2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila I2C_6 */ +&lpi2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila I2C_3_DSI1/I2C_5_CSI2 */ +&lpi2c8 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c8>; + pinctrl-1 = <&pinctrl_lpi2c8_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila SPI_2 */ +&lpspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi4>; + cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>, + <&som_gpio_expander_1 12 GPIO_ACTIVE_LOW>; + + status = "okay"; + + som_tpm: tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0x1>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + /* + * Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz + * here as lpspi4's per-clock (2x the max speed) is 24 MHz. + */ + spi-max-frequency = <12000000>; + }; +}; + +/* Aquila SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +}; + +/* Aquila UART_3, used as the Linux Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* Aquila UART_4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +/* Aquila UART_1 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; +}; + +/* Aquila UART_2 */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + uart-has-rtscts; +}; + +&mu7 { + status = "okay"; +}; + +/* Aquila ETH_2_XGMII_MDIO, shared between all ethernet ports */ +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + + status = "okay"; + + ethphy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_timer { + status = "okay"; +}; + +/* Aquila PCIE_1 */ +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpios = <&som_gpio_expander_0 0 GPIO_ACTIVE_LOW>; +}; + +/* On-module Wi-Fi or Aquila PCIE_2 */ +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +/* Aquila I2S_1 */ +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI2>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; +}; + +&scmi_bbm { + linux,code = ; +}; + +&thermal_zones { + /* PF09 Main PMIC */ + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_ARM PMIC */ + pf53-arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_SOC PMIC */ + pf53-soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +/* Aquila PWM_1 */ +&tpm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +/* Aquila PWM_2 */ +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +/* Aquila PWM_3_DSI and PWM_4_DP */ +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_dsi>, <&pinctrl_pwm4_dp>; +}; + +/* Aquila USB_2, optional Bluetooth USB */ +&usb2 { + dr_mode = "host"; + vbus-supply = <®_usb2_vbus>; +}; + +/* Aquila USB_1 */ +&usb3 { + fsl,disable-port-power-control; +}; + +&usb3_dwc3 { + dr_mode = "otg"; + adp-disable; + hnp-disable; + srp-disable; + usb-role-switch; +}; + +&usb3_phy { + vbus-supply = <®_usb1_vbus>; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + + status = "okay"; +}; + +/* Aquila SD_1 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_sd1_cd_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_sd1_cd_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + +&wdog3 { + fsl,ext-reset-output; + + status = "okay"; +}; + +&scmi_iomuxc { + /* Aquila CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: ctrlwake1micogrp { + fsl,pins = ; /* Aquila D6 */ + }; + + pinctrl_ctrl_dp_clk_en: dpclkengrp { + fsl,pins = ; /* CTRL_DP_CLK_EN */ + }; + + /* Aquila ETH_2_XGMII_MDIO */ + pinctrl_emdio: emdiogrp { + fsl,pins = , /* Aquila B90 */ + ; /* Aquila B89 */ + }; + + /* Aquila ETH_1 */ + pinctrl_enetc0: enetc0grp { + fsl,pins = , /* ENET1_TX_CTL */ + , /* ENET1_TXC */ + , /* ENET1_TDO */ + , /* ENET1_TD1 */ + , /* ENET1_TD2 */ + , /* ENET1_TD3 */ + , /* ENET1_RX_CTL */ + , /* ENET1_RXC */ + , /* ENET1_RD0 */ + , /* ENET1_RD1 */ + , /* ENET1_RD2 */ + ; /* ENET1_RD3 */ + }; + + /* Aquila CAN_1 */ + pinctrl_flexcan1: flexcan1grp { + fsl,pins = , /* Aquila B48 */ + ; /* Aquila B49 */ + }; + + /* Aquila CAN_2 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = , /* Aquila B50 */ + ; /* Aquila B51 */ + }; + + /* Aquila CAN_3 */ + pinctrl_flexcan3: flexcan3grp { + fsl,pins = , /* Aquila B53 */ + ; /* Aquila B54 */ + }; + + /* Aquila CAN_4 */ + pinctrl_flexcan4: flexcan4grp { + fsl,pins = , /* Aquila B55 */ + ; /* Aquila B56 */ + }; + + /* Aquila QSPI_1 (4 bit) */ + pinctrl_flexspi1_4bit: flexspi14bitgrp { + fsl,pins = , /* Aquila B65 */ + , /* Aquila B68 */ + , /* Aquila B67 */ + , /* Aquila B61 */ + , /* Aquila B60 */ + ; /* Aquila B63 */ + }; + + /* Aquila QSPI_1 (8 bit) */ + pinctrl_flexspi1_8bit: flexspi18bitgrp { + fsl,pins = , /* Aquila B65 */ + , /* Aquila B68 */ + , /* Aquila B67 */ + , /* Aquila B61 */ + , /* Aquila B60 */ + , /* Aquila B70 */ + , /* Aquila B71 */ + , /* Aquila B72 */ + , /* Aquila B73 */ + ; /* Aquila B63 */ + }; + + /* Aquila GPIO_01 */ + pinctrl_gpio_1: gpio1grp { + fsl,pins = ; /* Aquila D23 */ + }; + + /* Aquila GPIO_02 */ + pinctrl_gpio_2: gpio2grp { + fsl,pins = ; /* Aquila D24 */ + }; + + /* Aquila GPIO_03 */ + pinctrl_gpio_3: gpio3grp { + fsl,pins = ; /* Aquila D25 */ + }; + + /* Aquila GPIO_04 */ + pinctrl_gpio_4: gpio4grp { + fsl,pins = ; /* Aquila C20 */ + }; + + /* Aquila GPIO_05 */ + pinctrl_gpio_5: gpio5grp { + fsl,pins = ; /* Aquila C21 */ + }; + + /* Aquila GPIO_06 */ + pinctrl_gpio_6: gpio6grp { + fsl,pins = ; /* Aquila C22 */ + }; + + /* Aquila GPIO_07 */ + pinctrl_gpio_7: gpio7grp { + fsl,pins = ; /* Aquila C23 */ + }; + + /* Aquila GPIO_08 */ + pinctrl_gpio_8: gpio8grp { + fsl,pins = ; /* Aquila C24 */ + }; + + /* Aquila GPIO_09_CSI_1 */ + pinctrl_gpio_9_csi_1: gpio9csi1grp { + fsl,pins = ; /* Aquila B17 */ + }; + + /* Aquila GPIO_10_CSI_1 */ + pinctrl_gpio_10_csi_1: gpio10csi1grp { + fsl,pins = ; /* Aquila B18 */ + }; + + /* Aquila GPIO_11_CSI_1 */ + pinctrl_gpio_11_csi_1: gpio11csi1grp { + fsl,pins = ; /* Aquila A11*/ + }; + + /* Aquila GPIO_12_CSI_1 */ + pinctrl_gpio_12_csi_1: gpio12csi1grp { + fsl,pins = ; /* Aquila B19 */ + }; + + /* Aquila GPIO_17_DSI_1 */ + pinctrl_gpio_17_dsi_1: gpio17dsi1grp { + fsl,pins = ; /* Aquila B42 */ + }; + + /* Aquila GPIO_18_DSI_1 */ + pinctrl_gpio_18_dsi_1: gpio18dsi1grp { + fsl,pins = ; /* Aquila B43 */ + }; + + /* Aquila GPIO_19_DSI_1 */ + pinctrl_gpio_19_dsi_1: gpio19dsi1grp { + fsl,pins = ; /* Aquila B44 */ + }; + + /* Aquila GPIO_20_DSI_1 */ + pinctrl_gpio_20_dsi_1: gpio20dsi1grp { + fsl,pins = ; /* Aquila B45 */ + }; + + /* Aquila GPIO_21_DP */ + pinctrl_gpio_21_dp: gpio21dpgrp { + fsl,pins = ; /* Aquila B57 */ + }; + + pinctrl_ctrl_gpio_exp_int: gpioexpintgrp { + fsl,pins = ; /* CTRL_GPIO_EXP_INT# */ + }; + + /* Aquila I2C_2 */ + pinctrl_i3c2: i3c2cgrp { + fsl,pins = , /* Aquila C17 */ + ; /* Aquila C16 */ + }; + + /* Aquila I2C_1 as GPIOs */ + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = , /* Aquila D8 */ + ; /* Aquila D7 */ + }; + + /* Aquila I2C_1 */ + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = , /* Aquila D8 */ + ; /* Aquila D7 */ + }; + + /* On-module I2C as GPIOs */ + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = , /* I2C_SOM_SDA */ + ; /* I2C_SOM_SCL */ + }; + + /* On-module I2C */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = , /* I2C_SOM_SDA */ + ; /* I2C_SOM_SCL */ + }; + + /* Aquila I2C_4_CSI1 as GPIO */ + pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { + fsl,pins = , /* Aquila A12 */ + ; /* Aquila A13 */ + }; + + /* Aquila I2C_4_CSI1 */ + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = , /* Aquila A12 */ + ; /* Aquila A13 */ + }; + + /* Aquila I2C_6 as GPIO */ + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins = , /* Aquila C18 */ + ; /* Aquila C19 */ + }; + + /* Aquila I2C_6 */ + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = , /* Aquila C18 */ + ; /* Aquila C19 */ + }; + + /* Aquila I2C_3_DSI1/I2C_5_CSI2 as GPIO */ + pinctrl_lpi2c8_gpio: lpi2c8gpiogrp { + fsl,pins = , /* Aquila C5/B40 */ + ; /* Aquila C6/B41 */ + }; + + /* Aquila I2C_3_DSI1/I2C_5_CSI2 */ + pinctrl_lpi2c8: lpi2c8grp { + fsl,pins = , /* Aquila C5/B40 */ + ; /* Aquila C6/B41 */ + }; + + /* Aquila SPI_2 */ + pinctrl_lpspi4: lpspi4grp { + fsl,pins = , /* Aquila D16 */ + , /* Aquila D15 */ + , /* Aquila D17 */ + ; /* Aquila D14 */ + }; + + /* Aquila SPI_1 */ + pinctrl_lpspi6: lpspi6grp { + fsl,pins = , /* Aquila D9 */ + , /* Aquila D10 */ + , /* Aquila D11 */ + ; /* Aquila D12 */ + }; + + /* Aquila PCIE_1 */ + pinctrl_pcie0: pcie0grp { + fsl,pins = ; /* Aquila C37 */ + }; + + /* Aquila PCIE_2 */ + pinctrl_pcie1: pcie1grp { + fsl,pins = ; /* Aquila C34 */ + }; + + /* Aquila QSPI_1_CS1# */ + pinctrl_qspi_cs1: qspics1grp { + fsl,pins = ; /* Aquila B66 */ + }; + + /* Aquila QSPI_1_CS2# as GPIO */ + pinctrl_qspi_cs2_gpio: qspics2gpiogrp { + fsl,pins = ; /* Aquila B62 */ + }; + + /* Aquila I2S_1 */ + pinctrl_sai2: sai2grp { + fsl,pins = , /* Aquila B21 */ + , /* Aquila B20 */ + , /* Aquila B23 */ + ; /* Aquila B22 */ + }; + + pinctrl_sai2_mclk: sai2mclkgrp { + fsl,pins = ; /* Aquila B24 */ + }; + + /* Aquila SD_1_CD# as GPIO */ + pinctrl_sd1_cd_gpio: sd1cdgpiogrp { + fsl,pins = ; /* Aquila A1 */ + }; + + /* Aquila SD_1_PWR_EN */ + pinctrl_sd1_pwr_en: sd1pwrengpiogrp { + fsl,pins = ; /* Aquila A6 */ + }; + + /* Aquila PWM_1 */ + pinctrl_pwm1: tpm3ch3grp { + fsl,pins = ; /* Aquila C25 */ + }; + + /* Aquila PWM_3_DSI as GPIO */ + pinctrl_pwm3_dsi_gpio: tpm5ch0gpiogrp { + fsl,pins = ; /* Aquila B46 */ + }; + + /* Aquila PWM_3_DSI */ + pinctrl_pwm3_dsi: tpm5ch0grp { + fsl,pins = ; /* Aquila B46 */ + }; + + /* Aquila PWM_4_DP */ + pinctrl_pwm4_dp: tpm5ch3grp { + fsl,pins = ; /* Aquila B58 */ + }; + + /* Aquila PWM_2 */ + pinctrl_pwm2: tpm6ch0grp { + fsl,pins = ; /* Aquila C26 */ + }; + + /* Aquila UART_3 */ + pinctrl_uart1: uart1grp { + fsl,pins = , /* Aquila D20 */ + ; /* Aquila D19 */ + }; + + /* Aquila UART_4 */ + pinctrl_uart2: uart2grp { + fsl,pins = , /* Aquila D22 */ + ; /* Aquila D21 */ + }; + + /* Aquila UART_1 */ + pinctrl_uart3: uart3grp { + fsl,pins = , /* Aquila B37 */ + , /* Aquila B35 */ + , /* Aquila B36 */ + ; /* Aquila B38 */ + }; + + /* Aquila UART_2 */ + pinctrl_uart7: uart7grp { + fsl,pins = , /* Aquila B33 */ + , /* Aquila B31 */ + , /* Aquila B32 */ + ; /* Aquila B34 */ + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , /* eMMC_CLK */ + , /* eMMC_CMD */ + , /* eMMC_DATA0 */ + , /* eMMC_DATA1 */ + , /* eMMC_DATA2 */ + , /* eMMC_DATA3 */ + , /* eMMC_DATA4 */ + , /* eMMC_DATA5 */ + , /* eMMC_DATA6 */ + , /* eMMC_DATA7 */ + ; /* eMMC_STROBE */ + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = , /* eMMC_CLK */ + , /* eMMC_CMD */ + , /* eMMC_DATA0 */ + , /* eMMC_DATA1 */ + , /* eMMC_DATA2 */ + , /* eMMC_DATA3 */ + , /* eMMC_DATA4 */ + , /* eMMC_DATA5 */ + , /* eMMC_DATA6 */ + , /* eMMC_DATA7 */ + ; /* eMMC_STROBE */ + }; + + /* Aquila SD_1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , /* Aquila A5 */ + , /* Aquila A7 */ + , /* Aquila A3 */ + , /* Aquila A2 */ + , /* Aquila A10 */ + ; /* Aquila A8 */ + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , /* Aquila A5 */ + , /* Aquila A7 */ + , /* Aquila A3 */ + , /* Aquila A2 */ + , /* Aquila A10 */ + ; /* Aquila A8 */ + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = , /* Aquila A5 */ + , /* Aquila A7 */ + , /* Aquila A3 */ + , /* Aquila A2 */ + , /* Aquila A10 */ + ; /* Aquila A8 */ + }; +}; diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index ee22e411cd6..cbd0078ba2a 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -173,6 +173,10 @@ config TARGET_IMX943_EVK imply BOOTSTD_FULL imply OF_UPSTREAM +config TARGET_AQUILA_IMX95 + bool "Support Toradex Aquila iMX95" + select IMX95 + config TARGET_TORADEX_SMARC_IMX95 bool "Support Toradex SMARC iMX95" select IMX95 @@ -206,6 +210,7 @@ source "board/phytec/phycore_imx91_93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" source "board/nxp/imx94_evk/Kconfig" source "board/nxp/imx95_evk/Kconfig" +source "board/toradex/aquila-imx95/Kconfig" source "board/toradex/smarc-imx95/Kconfig" source "board/toradex/verdin-imx95/Kconfig" source "board/nxp/imx952_evk/Kconfig" diff --git a/board/toradex/aquila-imx95/Kconfig b/board/toradex/aquila-imx95/Kconfig new file mode 100644 index 00000000000..5936946e1af --- /dev/null +++ b/board/toradex/aquila-imx95/Kconfig @@ -0,0 +1,36 @@ +if TARGET_AQUILA_IMX95 + +config SYS_BOARD + default "aquila-imx95" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "aquila-imx95" + +config TDX_CFG_BLOCK + default y + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CFG_BLOCK_PART + default "1" + +config TDX_HAVE_EEPROM_EXTRA + default y + +config TDX_HAVE_MMC + default y + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/aquila-imx95/MAINTAINERS b/board/toradex/aquila-imx95/MAINTAINERS new file mode 100644 index 00000000000..d2a74a53f5e --- /dev/null +++ b/board/toradex/aquila-imx95/MAINTAINERS @@ -0,0 +1,11 @@ +Aquila iMX95 +F: arch/arm/dts/imx95-aquila.dtsi +F: arch/arm/dts/imx95-aquila-dev.dts +F: arch/arm/dts/imx95-aquila-dev-u-boot.dtsi +F: board/toradex/aquila-imx95/ +F: configs/aquila-imx95_defconfig +F: doc/board/toradex/aquila-imx95.rst +F: include/configs/aquila-imx95.h +M: Francesco Dolcini +S: Maintained +W: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 diff --git a/board/toradex/aquila-imx95/Makefile b/board/toradex/aquila-imx95/Makefile new file mode 100644 index 00000000000..caaf09465c8 --- /dev/null +++ b/board/toradex/aquila-imx95/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (c) Toradex + +obj-y += aquila-imx95.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/toradex/aquila-imx95/aquila-imx95.c b/board/toradex/aquila-imx95/aquila-imx95.c new file mode 100644 index 00000000000..0c6473e4b3a --- /dev/null +++ b/board/toradex/aquila-imx95/aquila-imx95.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include +#include +#include +#include + +#include "../common/tdx-cfg-block.h" + +int board_phys_sdram_size(phys_size_t *size) +{ + *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; + + return 0; +} + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif diff --git a/board/toradex/aquila-imx95/aquila-imx95.env b/board/toradex/aquila-imx95/aquila-imx95.env new file mode 100644 index 00000000000..5ca6cb18aaa --- /dev/null +++ b/board/toradex/aquila-imx95/aquila-imx95.env @@ -0,0 +1,20 @@ +boot_scripts=boot.scr +boot_script_dhcp=boot.scr +boot_targets=mmc1 mmc0 dhcp +console=ttyLP2 +fdt_board=dev +fdt_addr=0x9c400000 +fdt_addr_r=0x9c400000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x94400000 +kernel_comp_size=0x8000000 +ramdisk_addr_r=0x9c800000 +scriptaddr=0x9c600000 + +update_uboot= + askenv confirm Did you load flash.bin (y/N)?; + if test "$confirm" = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt + ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 + ${blkcnt}; + fi diff --git a/board/toradex/aquila-imx95/spl.c b/board/toradex/aquila-imx95/spl.c new file mode 100644 index 00000000000..9f501c11c1d --- /dev/null +++ b/board/toradex/aquila-imx95/spl.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION)) + spl_save_restore_data(); + + timer_init(); + + /* Need dm_init() to run before any SCMI calls */ + spl_early_init(); + + /* Need to enable SCMI drivers and ELE driver before console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* MU not probed, nothing can be outputed, hang */ + + arch_cpu_init(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + board_init_r(NULL, 0); +} diff --git a/configs/aquila-imx95_defconfig b/configs/aquila-imx95_defconfig new file mode 100644 index 00000000000..bb3d475ef4d --- /dev/null +++ b/configs/aquila-imx95_defconfig @@ -0,0 +1,186 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x90200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx95-aquila-dev" +CONFIG_TARGET_AQUILA_IMX95=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x204d6000 +CONFIG_SPL_TEXT_BASE=0x20480000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x204d6000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x90400000 +CONFIG_WATCHDOG_TIMEOUT_MSECS=30000 +CONFIG_SPL=y +CONFIG_SPL_RECOVER_DATA_SECTION=y +CONFIG_PCI=y +CONFIG_SYS_MEMTEST_START=0x90000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTDELAY=1 +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan -b" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="test -n \"${fdtfile}\" || setenv fdtfile imx95-aquila-${fdt_board}.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_LOG=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set +CONFIG_PCI_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/scmi/container.cfg" +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="Aquila iMX95 # " +CONFIG_CMD_ASKENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_READ=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BOOTCOUNT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_UUID=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_SCMI=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +CONFIG_VERSION_VARIABLE=y +CONFIG_PROT_UDP=y +CONFIG_IP_DEFRAG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_CLK_CCF=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x90400000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_SPL_FIRMWARE=y +# CONFIG_SCMI_AGENT_SMCCC is not set +CONFIG_IMX_SM_CPU=y +CONFIG_IMX_SM_LMM=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_IMX_MU_MBOX=y +CONFIG_I2C_EEPROM=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_MDIO=y +CONFIG_MII=y +CONFIG_FSL_ENETC=y +CONFIG_PHYLIB=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX_SCMI=y +CONFIG_POWER_DOMAIN=y +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REMOTEPROC_IMX=y +CONFIG_DM_RNG=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_USB_GADGET_OS_DESCRIPTORS=y +CONFIG_SDP_LOADADDR=0x90400000 +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_SHA1 is not set +CONFIG_LZO=y diff --git a/doc/board/toradex/aquila-imx95.rst b/doc/board/toradex/aquila-imx95.rst new file mode 100644 index 00000000000..edd40252657 --- /dev/null +++ b/doc/board/toradex/aquila-imx95.rst @@ -0,0 +1,175 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Toradex Aquila iMX95 Module +=========================== + +- SoM: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 +- Carrier board: https://www.toradex.com/products/carrier-board/aquila-development-board-kit + +Quick Start +----------- + +- Setup environment +- Get ahab-container.img +- Get DDR PHY Firmware Images +- Get and Build OEI Images +- Get and Build System Manager Image +- Get and Build the ARM Trusted Firmware +- Build the Bootloader Image +- Boot + +Setup environment +----------------- + +Suggested current toolchains are ARM 14.3 (https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads): + +- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-arm-none-linux-gnueabihf.tar.xz +- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz + +.. code-block:: console + + $ export TOOLS= + $ export CROSS_COMPILE_32=arm-none-linux-gnueabihf- + $ export CROSS_COMPILE_64=aarch64-none-linux-gnu- + +Get ahab-container.img +---------------------- + +Note: `$srctree` is the U-Boot source directory + +.. code-block:: console + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin + $ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept + $ cp firmware-ele-imx-2.0.2-89161a8/mx95b0-ahab-container.img $(srctree) + +Get DDR PHY Firmware Images +--------------------------- + +Note: `$srctree` is the U-Boot source directory + +.. code-block:: console + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ sh firmware-imx-8.28-994fa14.bin --auto-accept + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr5*v202409.bin $(srctree) + +Get and Build OEI Images +------------------------ + +Note: `$srctree` is the U-Boot source directory +Get OEI from: https://git.toradex.com/cgit/imx-oei-toradex.git/ +branch: main + +.. code-block:: console + + $ git clone -b main https://git.toradex.com/cgit/imx-oei-toradex.git/ + $ cd imx-oei-toradex + + $ make board=toradex-aquila-imx95 oei=ddr DEBUG=1 r=B0 all + $ cp build/toradex-aquila-imx95/ddr/oei-m33-ddr.bin $(srctree) + + $ make board=toradex-aquila-imx95 oei=tcm DEBUG=1 r=B0 all + $ cp build/toradex-aquila-imx95/tcm/oei-m33-tcm.bin $(srctree) + +The Makefile will set `DDR_CONFIG` automatically based on the selected silicon +revision. + +Get and Build the System Manager Image +-------------------------------------- + +Note: `$srctree` is the U-Boot source directory +Get System Manager from: https://git.toradex.com/cgit/imx-sm-toradex.git/ +branch: main + +.. code-block:: console + + $ git clone -b main https://git.toradex.com/cgit/imx-sm-toradex.git/ + $ cd imx-sm-toradex + $ make config=aquila-imx95 all + $ cp build/aquila-imx95/m33_image.bin $(srctree) + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +Note: `$srctree` is the U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.12 + +.. code-block:: console + + $ export CROSS_COMPILE=$CROSS_COMPILE_64 + $ unset LDFLAGS + $ unset AS + $ git clone -b lf_v2.12 https://github.com/nxp-imx/imx-atf.git + $ cd imx-atf + $ make PLAT=imx95 bl31 + $ cp build/imx95/release/bl31.bin $(srctree) + +Build the Bootloader Image +-------------------------- + +.. code-block:: console + + $ export CROSS_COMPILE=$CROSS_COMPILE_64 + $ make aquila-imx95_defconfig + $ make + +Flash to eMMC +------------- + +.. code-block:: console + + > tftpboot ${loadaddr} flash.bin + > setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 + > mmc dev 0 1 && mmc write ${loadaddr} 0x0 ${blkcnt} + +As a convenience, instead of the last two commands, one may also use the update +U-Boot wrapper: + +.. code-block:: console + + > run update_uboot + +Boot +---- + +Boot sequence is: + +* SPL ---> ATF (TF-A) ---> U-Boot proper + +Output: + +.. code-block:: console + + U-Boot SPL 2026.07-rc3-00300-ge16706b72e14 (Jun 11 2026 - 13:07:49 +0200) + SYS Boot reason: por, origin: -1, errid: -1 + WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout) + Trying to boot from MMC1 + Load image from MMC/SD 0xd2800 + NOTICE: BL31: v2.10.0 (release):lf-6.6.52-2.2.1-dirty + NOTICE: BL31: Built : 06:40:36, Jul 7 2025 + + + U-Boot 2026.07-rc3-00300-ge16706b72e14 (Jun 11 2026 - 13:07:49 +0200) + + CPU: NXP i.MX95 Rev2.0 A55 at 1800 MHz - invalid sensor data + DRAM: 7.8 GiB + Core: 321 devices, 30 uclasses, devicetree: separate + WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout) + MMC: FSL_SDHC: 0, FSL_SDHC: 1 + Loading Environment from MMC... Reading from MMC(0)... OK + In: serial@44380000 + Out: serial@44380000 + Err: serial@44380000 + Model: Toradex 0098 Aquila iMX95 Hexa 8GB WB IT V1.0A + Serial#: 12594391 + + BuildInfo: + - ELE firmware version 2.0.2-c110ba4b + + Net: WARNING: no MAC address assigned for MAC0 + imx_get_mac_from_fuse: fuse read err: 0 + eth0: enetc-0 [PRIME] + Hit any key to stop autoboot: 0 + Aquila iMX95 # diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst index 2a45bde6991..c5955ea1ad8 100644 --- a/doc/board/toradex/index.rst +++ b/doc/board/toradex/index.rst @@ -8,6 +8,7 @@ Toradex apalis-imx8 aquila-am69 + aquila-imx95 colibri_imx7 colibri-imx8x smarc-imx8mp diff --git a/include/configs/aquila-imx95.h b/include/configs/aquila-imx95.h new file mode 100644 index 00000000000..07d09d138cb --- /dev/null +++ b/include/configs/aquila-imx95.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (c) Toradex */ + +#ifndef __AQUILA_IMX95_H +#define __AQUILA_IMX95_H + +#include +#include + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above */ +#define SZ_6G _AC(0x180000000, ULL) + +/* first 256MB reserved for firmware */ +#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M + +#define CFG_SYS_SDRAM_BASE 0x90000000 +#define PHYS_SDRAM 0x90000000 +#define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M) +#define PHYS_SDRAM_2_SIZE SZ_6G + +#define CFG_SYS_SECURE_SDRAM_BASE 0x8A000000 /* Secure DDR region for A55, SPL could use first 2MB */ +#define CFG_SYS_SECURE_SDRAM_SIZE 0x06000000 + +#endif -- cgit v1.3.1 From 3c9cb48b4757f631e30a6cba634d62be815ac066 Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:40 +0300 Subject: clk: clk-divider: add clk_register_divider_table() The existing clk_register_divider() only supports linear or power-of-two divider mappings. Some hardware (e.g. i.MX6 PLL5 post_div and video_div) uses non-linear register-value-to-divisor mappings that require a lookup table. Add clk_register_divider_table() which accepts a clk_div_table, and reimplement clk_register_divider() as a wrapper passing table=NULL. Signed-off-by: Brian Ruley --- drivers/clk/clk-divider.c | 16 +++++++++++++--- include/linux/clk-provider.h | 5 +++++ 2 files changed, 18 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index e692b9c2167..d30786a9e6c 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -228,20 +228,30 @@ static struct clk *_register_divider(struct udevice *dev, const char *name, return clk; } -struct clk *clk_register_divider(struct udevice *dev, const char *name, +struct clk *clk_register_divider_table(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, - u8 clk_divider_flags) + u8 clk_divider_flags, const struct clk_div_table *table) { struct clk *clk; clk = _register_divider(dev, name, parent_name, flags, reg, shift, - width, clk_divider_flags, NULL); + width, clk_divider_flags, table); if (IS_ERR(clk)) return ERR_CAST(clk); return clk; } +struct clk *clk_register_divider(struct udevice *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags) +{ + return clk_register_divider_table(dev, name, parent_name, flags, reg, + shift, width, clk_divider_flags, + NULL); +} + U_BOOT_DRIVER(ccf_clk_divider) = { .name = UBOOT_DM_CLK_CCF_DIVIDER, .id = UCLASS_CLK, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2d754fa4287..366f2d968a3 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -246,6 +246,11 @@ struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk *clk_register_divider_table(struct udevice *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table); + struct clk *clk_register_divider(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, -- cgit v1.3.1 From b62b55ba4b2d1cabd6bb0943685c3115f6ee8bd3 Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Fri, 12 Jun 2026 17:43:09 +0800 Subject: arm: aspeed: add ASPEED AST2700 SoC family support Add initial support for the ASPEED AST2700, an arm64 (Cortex-A35) Baseboard Management Controller (BMC) SoC. AST2700 is Aspeed's 8th generation BMC and uses a dual-die architecture: SoC0 (the "CPU" die) hosts the four Cortex-A35 cores and its own SCU at 0x12c02000, while SoC1 (the "IO" die) hosts the peripherals and its own SCU at 0x14c02000. This commit adds: - ASPEED_AST2700 Kconfig option and the ast2700 mach subdir (mach Makefile, ast2700/Kconfig, board/aspeed/evb_ast2700/*) - arm64 MMU map covering the SoC device window and the DRAM region at 0x4_0000_0000 (up to 8 GiB) - lowlevel_init.S for early CPU bring-up - cpu-info: print SoC ID (AST2700/2720/2750 A0/A1/A2 variants) and reset cause (cold reset, EXT reset, WDT reset) - board_common: dram_init via UCLASS_RAM, AHBC timeout init - platform: env_get_location() that selects SPI/eMMC based on the IO-die HW strap; arch_misc_init() that exposes ${boot_device} and ${verify} to the boot script - SCU0/SCU1 register layout header (scu_ast2700.h) - configs/evb-ast2700_defconfig and include/configs/evb_ast2700.h for the AST2700 EVB board The defconfig depends on ast2700-evb.dts, which is introduced in a subsequent patch; this commit must be applied with the remaining series for evb-ast2700_defconfig to build. Signed-off-by: Ryan Chen --- MAINTAINERS | 1 + arch/arm/include/asm/arch-aspeed/platform.h | 30 +- arch/arm/include/asm/arch-aspeed/scu_ast2700.h | 514 +++++++++++++++++++++++++ arch/arm/mach-aspeed/Kconfig | 11 + arch/arm/mach-aspeed/Makefile | 1 + arch/arm/mach-aspeed/ast2700/Kconfig | 36 ++ arch/arm/mach-aspeed/ast2700/Makefile | 2 + arch/arm/mach-aspeed/ast2700/arm64-mmu.c | 43 +++ arch/arm/mach-aspeed/ast2700/board_common.c | 90 +++++ arch/arm/mach-aspeed/ast2700/cpu-info.c | 114 ++++++ arch/arm/mach-aspeed/ast2700/lowlevel_init.S | 132 +++++++ arch/arm/mach-aspeed/ast2700/platform.c | 64 +++ board/aspeed/evb_ast2700/Kconfig | 13 + board/aspeed/evb_ast2700/Makefile | 1 + board/aspeed/evb_ast2700/evb_ast2700.c | 5 + configs/evb-ast2700_defconfig | 160 ++++++++ include/configs/evb_ast2700.h | 58 +++ 17 files changed, 1274 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-aspeed/scu_ast2700.h create mode 100644 arch/arm/mach-aspeed/ast2700/Kconfig create mode 100644 arch/arm/mach-aspeed/ast2700/Makefile create mode 100644 arch/arm/mach-aspeed/ast2700/arm64-mmu.c create mode 100644 arch/arm/mach-aspeed/ast2700/board_common.c create mode 100644 arch/arm/mach-aspeed/ast2700/cpu-info.c create mode 100644 arch/arm/mach-aspeed/ast2700/lowlevel_init.S create mode 100644 arch/arm/mach-aspeed/ast2700/platform.c create mode 100644 board/aspeed/evb_ast2700/Kconfig create mode 100644 board/aspeed/evb_ast2700/Makefile create mode 100644 board/aspeed/evb_ast2700/evb_ast2700.c create mode 100644 configs/evb-ast2700_defconfig create mode 100644 include/configs/evb_ast2700.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 571af196465..8da42bfdc60 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -224,6 +224,7 @@ F: drivers/ram/aspeed/ F: drivers/reset/reset-ast2500.c F: drivers/watchdog/ast_wdt.c N: aspeed +N: ast2700 ARM BROADCOM BCM283X / BCM27XX M: Matthias Brugger diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h index 589abd4a3f6..82699c03c00 100644 --- a/arch/arm/include/asm/arch-aspeed/platform.h +++ b/arch/arm/include/asm/arch-aspeed/platform.h @@ -18,8 +18,36 @@ #define ASPEED_DRAM_BASE 0x80000000 #define ASPEED_SRAM_BASE 0x10000000 #define ASPEED_SRAM_SIZE 0x16000 +#elif defined(CONFIG_ASPEED_AST2700) +#define ASPEED_CPU_AHBC_BASE 0x12000000 +#define ASPEED_CPU_REVISION_ID 0x12C02000 +#define ASPEED_CPU_SCU_BASE 0x12C02000 +#define ASPEED_CPU_HW_STRAP1 0x12C02010 +#define ASPEED_CPU_RESET_LOG1 0x12C02050 +#define ASPEED_CPU_RESET_LOG2 0x12C02060 +#define ASPEED_CPU_RESET_LOG3 0x12C02070 +#define ASPEED_MAC_COUNT 3 +#define ASPEED_DRAM_BASE 0x400000000 +#define ASPEED_SRAM_BASE 0x10000000 +#define ASPEED_SRAM_SIZE 0x20000 +#define ASPEED_FMC_REG_BASE 0x14000000 +#define ASPEED_FMC_CS0_BASE 0x100000000 +#define ASPEED_FMC_CS0_SIZE 0x80000000 +#define ASPEED_IO_MAC0_BASE 0x14050000 +#define ASPEED_IO_MAC1_BASE 0x14060000 +#define ASPEED_IO_AHBC_BASE 0x140b0000 +#define ASPEED_IO_REVISION_ID 0x14C02000 +#define CHIP_AST2700A1_ID_MASK BIT(16) +#define ASPEED_IO_SCU_BASE 0x14C02000 +#define ASPEED_IO_HW_STRAP1 0x14C02010 +#define ASPEED_IO_RESET_LOG1 0x14C02050 +#define ASPEED_IO_RESET_LOG2 0x14C02060 +#define ASPEED_IO_RESET_LOG3 0x14C02070 +#define ASPEED_IO_RESET_LOG4 0x14C02080 +#define ASPEED_IO_GPIO_BASE 0x14C0B000 +#define ASPEED_WDTA_BASE 0x14C37400 #else -#err "Unrecognized Aspeed platform." +#error "Unrecognized Aspeed platform." #endif #endif diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2700.h b/arch/arm/include/asm/arch-aspeed/scu_ast2700.h new file mode 100644 index 00000000000..b973fcc6610 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2700.h @@ -0,0 +1,514 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef _ASM_ARCH_SCU_AST2700_H +#define _ASM_ARCH_SCU_AST2700_H + +#include + +/* SoC0 SCU Register */ +#define SCU_CPU_REVISION_ID_HW GENMASK(23, 16) +#define SCU_CPU_REVISION_ID_EFUSE GENMASK(15, 8) + +#define SCU_CPU_HWSTRAP_DIS_RVAS BIT(30) +#define SCU_CPU_HWSTRAP_DP_SRC BIT(29) +#define SCU_CPU_HWSTRAP_DAC_SRC BIT(28) +#define SCU_CPU_HWSTRAP_VRAM_SIZE GENMASK(11, 10) +#define SCU_CPU_HWSTRAP_DIS_CPU BIT(0) + +#define SCU_CPU_MISC_DP_RESET_SRC BIT(11) +#define SCU_CPU_MISC_XDMA_CLIENT_EN BIT(4) +#define SCU_CPU_MISC_2D_CLIENT_EN BIT(3) + +#define SCU_CPU_RST_SSP BIT(30) +#define SCU_CPU_RST_DPMCU BIT(29) +#define SCU_CPU_RST_DP BIT(28) +#define SCU_CPU_RST_XDMA1 BIT(26) +#define SCU_CPU_RST_XDMA0 BIT(25) +#define SCU_CPU_RST_EMMC BIT(17) +#define SCU_CPU_RST_EN_DP_PCI BIT(15) +#define SCU_CPU_RST_CRT BIT(13) +#define SCU_CPU_RST_RVAS1 BIT(10) +#define SCU_CPU_RST_RVAS0 BIT(9) +#define SCU_CPU_RST_2D BIT(7) +#define SCU_CPU_RST_VIDEO BIT(6) +#define SCU_CPU_RST_SOC BIT(5) +#define SCU_CPU_RST_DDRPHY BIT(1) + +#define SCU_CPU_RST2_VGA BIT(12) +#define SCU_CPU_RST2_E2M1 BIT(11) +#define SCU_CPU_RST2_E2M0 BIT(10) +#define SCU_CPU_RST2_TSP BIT(9) + +#define SCU_CPU_VGA_FUNC_DAC_OUTPUT GENMASK(11, 10) +#define SCU_CPU_VGA_FUNC_DP_OUTPUT GENMASK(9, 8) +#define SCU_CPU_VGA_FUNC_DAC_DISABLE BIT(7) + +#define SCU_CPU_PCI_MISC0C_FB_SIZE GENMASK(4, 0) + +#define SCU_CPU_PCI_MISC70_EN_XHCI BIT(3) +#define SCU_CPU_PCI_MISC70_EN_EHCI BIT(2) +#define SCU_CPU_PCI_MISC70_EN_IPMI BIT(1) +#define SCU_CPU_PCI_MISC70_EN_VGA BIT(0) + +#define SCU_CPU_HPLL_P GENMASK(22, 19) +#define SCU_CPU_HPLL_N GENMASK(18, 13) +#define SCU_CPU_HPLL_M GENMASK(12, 0) + +#define SCU_CPU_HPLL2_LOCK BIT(31) +#define SCU_CPU_HPLL2_BWADJ GENMASK(11, 0) + +#define SCU_CPU_SSP_TSP_RESET_STS BIT(8) +#define SCU_CPU_SSP_TSP_SRAM_SD BIT(7) +#define SCU_CPU_SSP_TSP_SRAM_DSLP BIT(6) +#define SCU_CPU_SSP_TSP_SRAM_SLP BIT(5) +#define SCU_CPU_SSP_TSP_NIDEN BIT(4) +#define SCU_CPU_SSP_TSP_DBGEN BIT(3) +#define SCU_CPU_SSP_TSP_DBG_ENABLE BIT(2) +#define SCU_CPU_SSP_TSP_RESET BIT(1) +#define SCU_CPU_SSP_TSP_ENABLE BIT(0) + +/* SoC1 SCU Register */ +#define SCU_IO_HWSTRAP_UFS BIT(23) +#define SCU_IO_HWSTRAP_EMMC BIT(11) +#define SCU_IO_HWSTRAP_SECBOOT BIT(5) +#define SCU_IO_HWSTRAP_LTPI0_EN BIT(3) +#define SCU_IO_HWSTRAP_LTPI1_EN BIT(1) + +/* CLK information */ +#define CLKIN_25M 25000000UL + +#define SCU_CPU_CLKGATE1_RVAS1 BIT(28) +#define SCU_CPU_CLKGATE1_RVAS0 BIT(25) +#define SCU_CPU_CLKGATE1_E2M1 BIT(19) +#define SCU_CPU_CLKGATE1_DP BIT(18) +#define SCU_CPU_CLKGATE1_DAC BIT(17) +#define SCU_CPU_CLKGATE1_E2M0 BIT(12) +#define SCU_CPU_CLKGATE1_VGA1 BIT(10) +#define SCU_CPU_CLKGATE1_VGA0 BIT(5) + +/* + * Clock divider/multiplier configuration struct. + * For H-PLL and M-PLL the formula is + * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) + * M - Numerator + * N - Denumerator + * P - Post Divider + * They have the same layout in their control register. + * + */ +union ast2700_pll_reg { + u32 w; + struct { + uint16_t m : 13; /* bit[12:0] */ + uint8_t n : 6; /* bit[18:13] */ + uint8_t p : 4; /* bit[22:19] */ + uint8_t off : 1; /* bit[23] */ + uint8_t bypass : 1; /* bit[24] */ + uint8_t reset : 1; /* bit[25] */ + uint8_t reserved : 6; /* bit[31:26] */ + } b; +}; + +struct ast2700_pll_cfg { + union ast2700_pll_reg reg; + unsigned int ext_reg; +}; + +struct ast2700_pll_desc { + u32 in; + u32 out; + struct ast2700_pll_cfg cfg; +}; + +struct aspeed_clks { + ulong id; + const char *name; +}; + +#ifndef __ASSEMBLY__ +struct ast2700_scu0 { + u32 chip_id1; /* 0x000 */ + u32 rsv_0x04[3]; /* 0x004 ~ 0x00C */ + u32 hwstrap1; /* 0x010 */ + u32 hwstrap1_clr; /* 0x014 */ + u32 rsv_0x18[2]; /* 0x018 ~ 0x01C */ + u32 hwstrap1_lock; /* 0x020 */ + u32 hwstrap1_sec1; /* 0x024 */ + u32 hwstrap1_sec2; /* 0x028 */ + u32 hwstrap1_sec3; /* 0x02C */ + u32 rsv_0x30[8]; /* 0x030 ~ 0x4C */ + u32 sysrest_log1; /* 0x050 */ + u32 sysrest_log1_sec1; /* 0x054 */ + u32 sysrest_log1_sec2; /* 0x058 */ + u32 sysrest_log1_sec3; /* 0x05C */ + u32 sysrest_log2; /* 0x060 */ + u32 sysrest_log2_sec1; /* 0x064 */ + u32 sysrest_log2_sec2; /* 0x068 */ + u32 sysrest_log2_sec3; /* 0x06C */ + u32 sysrest_log3; /* 0x070 */ + u32 sysrest_log3_sec1; /* 0x074 */ + u32 sysrest_log3_sec2; /* 0x078 */ + u32 sysrest_log3_sec3; /* 0x07C */ + u32 rsv_0x80[8]; /* 0x080 ~ 0x9C */ + u32 probe_sig_select; /* 0x0A0 */ + u32 probe_sig_enable1; /* 0x0A4 */ + u32 probe_sig_enable2; /* 0x0A8 */ + u32 uart_dbg_rate; /* 0x0AC */ + u32 rsv_0xB0[4]; /* 0x0B0 ~ 0xBC*/ + u32 misc; /* 0x0C0 */ + u32 rsv_0xC4; /* 0x0C4 */ + u32 debug_ctrl; /* 0x0C8 */ + u32 rsv_0xCC[5]; /* 0x0CC ~ 0x0DC */ + u32 free_counter_read_low; /* 0x0E0 */ + u32 free_counter_read_high; /* 0x0E4 */ + u32 rsv_0xE8[2]; /* 0x0E8 ~ 0x0EC */ + u32 random_num_ctrl; /* 0x0F0 */ + u32 random_num_data; /* 0x0F4 */ + u32 rsv_0xF8[10]; /* 0x0F8 ~ 0x11C */ + u32 ssp_ctrl_1; /* 0x120 */ + u32 ssp_ctrl_2; /* 0x124 */ + u32 ssp_ctrl_3; /* 0x128 */ + u32 ssp_ctrl_4; /* 0x12C */ + u32 ssp_ctrl_5; /* 0x130 */ + u32 ssp_ctrl_6; /* 0x134 */ + u32 ssp_ctrl_7; /* 0x138 */ + u32 rsv_0x13c[1]; /* 0x13C */ + u32 ssp_remap0_base; /* 0x140 */ + u32 ssp_remap0_size; /* 0x144 */ + u32 ssp_remap1_base; /* 0x148 */ + u32 ssp_remap1_size; /* 0x14c */ + u32 ssp_remap2_base; /* 0x150 */ + u32 ssp_remap2_size; /* 0x154 */ + u32 rsv_0x158[2]; /* 0x158 ~ 0x15C */ + u32 tsp_ctrl_1; /* 0x160 */ + u32 rsv_0x164[1]; /* 0x164 */ + u32 tsp_ctrl_3; /* 0x168 */ + u32 tsp_ctrl_4; /* 0x16C */ + u32 tsp_ctrl_5; /* 0x170 */ + u32 tsp_ctrl_6; /* 0x174 */ + u32 tsp_ctrl_7; /* 0x178 */ + u32 rsv_0x17c[6]; /* 0x17C ~ 0x190 */ + u32 tsp_remap_size; /* 0x194 */ + u32 rsv_0x198[26]; /* 0x198 ~ 0x1FC */ + u32 modrst1_ctrl; /* 0x200 */ + u32 modrst1_clr; /* 0x204 */ + u32 rsv_0x208[2]; /* 0x208 ~ 0x20C */ + u32 modrst1_lock; /* 0x210 */ + u32 modrst1_prot1; /* 0x214 */ + u32 modrst1_prot2; /* 0x218 */ + u32 modrst1_prot3; /* 0x21C */ + u32 modrst2_ctrl; /* 0x220 */ + u32 modrst2_clr; /* 0x224 */ + u32 rsv_0x228[2]; /* 0x228 ~ 0x22C */ + u32 modrst2_lock; /* 0x230 */ + u32 modrst2_prot1; /* 0x234 */ + u32 modrst2_prot2; /* 0x238 */ + u32 modrst2_prot3; /* 0x23C */ + u32 clkgate_ctrl; /* 0x240 */ + u32 clkgate_clr; /* 0x244 */ + u32 rsv_0x248[2]; /* 0x248 */ + u32 clkgate_lock; /* 0x250 */ + u32 clkgate_secure1; /* 0x254 */ + u32 clkgate_secure2; /* 0x258 */ + u32 clkgate_secure3; /* 0x25c */ + u32 rsv_0x260[8]; /* 0x260 */ + u32 clk_sel1; /* 0x280 */ + u32 clk_sel2; /* 0x284 */ + u32 clk_sel3; /* 0x288 */ + u32 rsv_0x28c; /* 0x28c */ + u32 clk_sel1_lock; /* 0x290 */ + u32 clk_sel2_lock; /* 0x294 */ + u32 clk_sel3_lock; /* 0x298 */ + u32 rsv_0x29c; /* 0x29c */ + u32 clk_sel1_secure1; /* 0x2a0 */ + u32 clk_sel1_secure2; /* 0x2a4 */ + u32 clk_sel1_secure3; /* 0x2a8 */ + u32 rsv_0x2ac; /* 0x2ac */ + u32 clk_sel2_secure1; /* 0x2b0 */ + u32 clk_sel2_secure2; /* 0x2b4 */ + u32 clk_sel2_secure3; /* 0x2b8 */ + u32 rsv_0x2bc; /* 0x2bc */ + u32 clk_sel3_secure1; /* 0x2c0 */ + u32 clk_sel3_secure2; /* 0x2c4 */ + u32 clk_sel3_secure3; /* 0x2c8 */ + u32 rsv_0x2cc[9]; /* 0x2cc */ + u32 extrst_sel; /* 0x2f0 */ + u32 rsv_0x2f4[3]; /* 0x2f4 */ + u32 hpll; /* 0x300 */ + u32 hpll_ext; /* 0x304 */ + u32 dpll; /* 0x308 */ + u32 dpll_ext; /* 0x30C */ + u32 mpll; /* 0x310 */ + u32 mpll_ext; /* 0x314 */ + u32 rsv_0x318[2]; /* 0x318 ~ 0x31C */ + u32 d1clk_para; /* 0x320 */ + u32 rsv_0x324[3]; /* 0x324 ~ 0x32C */ + u32 d2clk_para; /* 0x330 */ + u32 rsv_0x334[3]; /* 0x334 ~ 0x33C */ + u32 crt1clk_para; /* 0x340 */ + u32 rsv_0x344[3]; /* 0x344 ~ 0x34C */ + u32 crt2clk_para; /* 0x350 */ + u32 rsv_0x354[3]; /* 0x354 ~ 0x35C */ + u32 mphyclk_para; /* 0x360 */ + u32 rsv_0x364[7]; /* 0x364 ~ 0x37C */ + u32 clkduty_meas_ctrl; /* 0x380 */ + u32 clkduty1; /* 0x384 */ + u32 clkduty2; /* 0x368 */ + u32 clkduty_meas_res; /* 0x38c */ + u32 rsv_0x390[4]; /* 0x390 ~ 0x39C */ + u32 freq_counter_ctrl; /* 0x3a0 */ + u32 freq_counter_cmp; /* 0x3a4 */ + u32 prog_delay_ring_ctrl0; /* 0x3a8 */ + u32 prog_delay_ring_ctrl1; /* 0x3ac */ + u32 freq_counter_readback; /* 0x3b0 */ + u32 rsv_0x3b4[19]; /* 0x3b4 */ + u32 pinmux1; /* 0x400 */ + u32 pinmux2; /* 0x404 */ + u32 pinmux3; /* 0x408 */ + u32 rsv_0x40c; /* 0x40C */ + u32 pinmux4; /* 0x410 */ + u32 vga_func_ctrl; /* 0x414 */ + u32 rsv_0x418[2]; /* 0x418 */ + u32 pinmux_lock0; /* 0x420 */ + u32 pinmux_lock1; /* 0x424 */ + u32 pinmux_lock2; /* 0x428 */ + u32 rsv_0x42c; + u32 pinmux_lock3; /* 0x430 */ + u32 pinmux_lock4; /* 0x434 */ + u32 rsv_0x438[18]; + u32 gpio18d0_ioctrl; /* 0x480 */ + u32 gpio18d1_ioctrl; /* 0x484 */ + u32 gpio18d2_ioctrl; /* 0x488 */ + u32 gpio18d3_ioctrl; /* 0x48c */ + u32 gpio18d4_ioctrl; /* 0x490 */ + u32 gpio18d5_ioctrl; /* 0x494 */ + u32 gpio18d6_ioctrl; /* 0x498 */ + u32 gpio18d7_ioctrl; /* 0x49c */ + u32 gpio18e0_ioctrl; /* 0x4a0 */ + u32 gpio18e1_ioctrl; /* 0x4a4 */ + u32 gpio18e2_ioctrl; /* 0x4a8 */ + u32 gpio18e3_ioctrl; /* 0x4ac */ + u32 jtag_ioctrl; /* 0x4b0 */ + u32 uart_ioctrl; /* 0x4b4 */ + u32 misc_ioctrl; /* 0x4b8 */ + u32 rsv_0x4bc[17]; /* 0x4bc ~ 0x4fc */ + u32 pinmux_seucre0_0; /* 0x500 */ + u32 pinmux_seucre0_1; /* 0x504 */ + u32 pinmux_seucre0_2; /* 0x508 */ + u32 rsv_0x50c; + u32 pinmux_seucre0_3; /* 0x510 */ + u32 pinmux_seucre0_4; /* 0x514 */ + u32 rsv_0x518[58]; + u32 pinmux_seucre1_0; /* 0x600 */ + u32 pinmux_seucre1_1; /* 0x604 */ + u32 pinmux_seucre1_2; /* 0x608 */ + u32 rsv_0x60c; + u32 pinmux_seucre1_3; /* 0x610 */ + u32 pinmux_seucre1_4; /* 0x614 */ + u32 rsv_0x618[58]; + u32 pinmux_seucre2_0; /* 0x700 */ + u32 pinmux_seucre2_1; /* 0x704 */ + u32 pinmux_seucre2_2; /* 0x708 */ + u32 rsv_0x70c; + u32 pinmux_seucre2_3; /* 0x710 */ + u32 pinmux_seucre2s_4; /* 0x714 */ + u32 rsv_0x718[26]; + u32 cpu_scratch[96]; /* 0x780 ~ 0x8FC */ + u32 vga0_scratch1[4]; /* 0x900 ~ 0x90C */ + u32 vga1_scratch1[4]; /* 0x910 ~ 0x91C */ + u32 vga0_scratch2[8]; /* 0x920 ~ 0x93C */ + u32 vga1_scratch2[8]; /* 0x940 ~ 0x95C */ + u32 pci_cfg1[3]; /* 0x960 ~ 0x968 */ + u32 rsv_0x96c; /* 0x96C */ + u32 pcie_cfg1; /* 0x970 */ + u32 mmio_decode1; /* 0x974 */ + u32 reloc_ctrl_decode1[2]; /* 0x978 ~ 0x97C */ + u32 rsv_0x980[4]; /* 0x980 ~ 0x98C */ + u32 mbox_decode1; /* 0x990 */ + u32 shared_sram_decode1[2];/* 0x994 ~ 0x998 */ + u32 rsv_0x99c; /* 0x99C */ + u32 pci_cfg2[3]; /* 0x9A0 ~ 0x9A8 */ + u32 rsv_0x9ac; /* 0x9AC */ + u32 pcie_cfg2; /* 0x9B0 */ + u32 mmio_decode2; /* 0x9B4 */ + u32 reloc_ctrl_decode2[2]; /* 0x9B8 ~ 0x9BC */ + u32 rsv_0x9c0[4]; /* 0x9C0 ~ 0x9CC */ + u32 mbox_decode2; /* 0x9D0 */ + u32 shared_sram_decode2[2];/* 0x9D4 ~ 0x9D8 */ + u32 rsv_0x9dc[9]; /* 0x9DC ~ 0x9FC */ + u32 pci0_misc[32]; /* 0xA00 ~ 0xA7C */ + u32 pci1_misc[32]; /* 0xA80 ~ 0xAFC */ +}; + +struct ast2700_scu1 { + u32 chip_id1; /* 0x000 */ + u32 rsv_0x04[3]; /* 0x004 ~ 0x00C */ + u32 hwstrap1; /* 0x010 */ + u32 hwstrap1_clr; /* 0x014 */ + u32 rsv_0x18[2]; /* 0x018 ~ 0x01C */ + u32 hwstrap1_lock; /* 0x020 */ + u32 hwstrap1_sec1; /* 0x024 */ + u32 hwstrap1_sec2; /* 0x028 */ + u32 hwstrap1_sec3; /* 0x02C */ + u32 hwstrap2; /* 0x030 */ + u32 hwstrap2_clr; /* 0x034 */ + u32 rsv_0x38[2]; /* 0x038 ~ 0x03C */ + u32 hwstrap2_lock; /* 0x040 */ + u32 hwstrap2_sec1; /* 0x044 */ + u32 hwstrap2_sec2; /* 0x048 */ + u32 hwstrap2_sec3; /* 0x04C */ + u32 sysrest_log1; /* 0x050 */ + u32 sysrest_log1_sec1; /* 0x054 */ + u32 sysrest_log1_sec2; /* 0x058 */ + u32 sysrest_log1_sec3; /* 0x05C */ + u32 sysrest_log2; /* 0x060 */ + u32 sysrest_log2_sec1; /* 0x064 */ + u32 sysrest_log2_sec2; /* 0x068 */ + u32 sysrest_log2_sec3; /* 0x06C */ + u32 sysrest_log3; /* 0x070 */ + u32 sysrest_log3_sec1; /* 0x074 */ + u32 sysrest_log3_sec2; /* 0x078 */ + u32 sysrest_log3_sec3; /* 0x07C */ + u32 sysrest_log4; /* 0x080 */ + u32 sysrest_log4_sec1; /* 0x084 */ + u32 sysrest_log4_sec2; /* 0x088 */ + u32 sysrest_log4_sec3; /* 0x08C */ + u32 rsv_0x90[7]; /* 0x090 ~ 0xA8 */ + u32 uart_dbg_rate; /* 0x0AC */ + u32 rsv_0xB0[4]; /* 0x0B0 ~ 0xBC*/ + u32 misc; /* 0x0C0 */ + u32 rsv_0xC4; /* 0x0C4 */ + u32 debug_ctrl; /* 0x0C8 */ + u32 rsv_0xCC; /* 0x0CC */ + u32 dac_ctrl; /* 0x0D0 */ + u32 dac_crc_ctrl; /* 0x0D4 */ + u32 rsv_0xD8[2]; /* 0x0D8 ~ 0x0DC */ + u32 video_input_ctrl; /* 0x0E0 */ + u32 rsv_0xE4[3]; /* 0x0E4 ~ 0x0EC */ + u32 random_num_ctrl; /* 0x0F0 */ + u32 random_num_data; /* 0x0F4 */ + u32 rsv_0xF0[2]; /* 0x0F8 ~ 0x0FC */ + u32 rsv_0x100[32]; /* 0x100 ~ 0x17C */ + u32 scratch[32]; /* 0x180 ~ 0x1FC */ + u32 modrst1_ctrl; /* 0x200 */ + u32 modrst1_clr; /* 0x204 */ + u32 rsv_0x208[2]; /* 0x208 ~ 0x20C */ + u32 modrst_lock1; /* 0x210 */ + u32 modrst1_sec1; /* 0x214 */ + u32 modrst1_sec2; /* 0x218 */ + u32 modrst1_sec3; /* 0x21C */ + u32 modrst2_ctrl; /* 0x220 */ + u32 modrst2_clr; /* 0x224 */ + u32 rsv_0x228[2]; /* 0x228 ~ 0x22C */ + u32 modrst2_lock; /* 0x230 */ + u32 modrst2_prot1; /* 0x234 */ + u32 modrst2_prot2; /* 0x238 */ + u32 modrst2_prot3; /* 0x23C */ + u32 clkgate_ctrl1; /* 0x240 */ + u32 clkgate_clr1; /* 0x244 */ + u32 rsv_0x248[2]; /* 0x248 */ + u32 clkgate_lock1; /* 0x250 */ + u32 clkgate_secure11; /* 0x254 */ + u32 clkgate_secure12; /* 0x258 */ + u32 clkgate_secure13; /* 0x25c */ + u32 clkgate_ctrl2; /* 0x260 */ + u32 clkgate_clr2; /* 0x264 */ + u32 rsv_0x268[2]; /* 0x268 */ + u32 clkgate_lock2; /* 0x270 */ + u32 clkgate_secure21; /* 0x274 */ + u32 clkgate_secure22; /* 0x278 */ + u32 clkgate_secure23; /* 0x27c */ + u32 clk_sel1; /* 0x280 */ + u32 clk_sel2; /* 0x284 */ + u32 rsv_0x288[2]; /* 0x288 */ + u32 clk_sel1_lock; /* 0x290 */ + u32 clk_sel2_lock; /* 0x294 */ + u32 rsv_0x298[2]; /* 0x298 */ + u32 clk_sel1_secure1; /* 0x2a0 */ + u32 clk_sel1_secure2; /* 0x2a4 */ + u32 rsv_0x2a8[2]; /* 0x2a8 */ + u32 clk_sel2_secure1; /* 0x2b0 */ + u32 clk_sel2_secure2; /* 0x2b4 */ + u32 rsv_0x2b8[2]; /* 0x2b8 */ + u32 clk_sel3_secure1; /* 0x2c0 */ + u32 clk_sel3_secure2; /* 0x2c4 */ + u32 rsv_0x2c8[10]; /* 0x2c8 */ + u32 extrst_sel1; /* 0x2f0 */ + u32 extrst_sel2; /* 0x2f4 */ + u32 rsv_0x2f8[2]; /* 0x2f8 */ + u32 hpll; /* 0x300 */ + u32 hpll_ext; /* 0x304 */ + u32 rsv_0x308[2]; /* 0x308 ~ 0x30C */ + u32 apll; /* 0x310 */ + u32 apll_ext; /* 0x314 */ + u32 rsv_0x318[2]; /* 0x318 ~ 0x31C */ + u32 dpll; /* 0x320 */ + u32 dpll_ext; /* 0x324 */ + u32 rsv_0x328[2]; /* 0x328 ~ 0x32C */ + u32 uxclk_ctrl; /* 0x330 */ + u32 huxclk_ctrl; /* 0x334 */ + u32 rsv_0x338[18]; /* 0x338 ~ 0x37C */ + u32 clkduty_meas_ctrl; /* 0x380 */ + u32 clkduty1; /* 0x384 */ + u32 clkduty2; /* 0x388 */ + u32 rsv_0x38c; /* 0x38c */ + u32 mac_delay; /* 0x390 */ + u32 mac_100m_delay; /* 0x394 */ + u32 mac_10m_delay; /* 0x398 */ + u32 rsv_0x39c; /* 0x39c */ + u32 freq_counter_ctrl; /* 0x3a0 */ + u32 freq_counter_cmp; /* 0x3a4 */ + u32 rsv_0x3a8[2]; /* 0x3a8 ~ 0x3aC */ + u32 usb_ctrl; /* 0x3b0 */ + u32 usb_lock; /* 0x3b4 */ + u32 usb_secure1; /* 0x3b8 */ + u32 usb_secure2; /* 0x3bc */ + u32 usb_secure3; /* 0x3c0 */ + u32 rsv_0x3c4[15]; /* 0x3c4 ~ 0x3fc */ + u32 pinumx1; /* 0x400 */ + u32 pinumx2; /* 0x404 */ + u32 pinumx3; /* 0x408 */ + u32 pinumx4; /* 0x40c */ + u32 pinumx5; /* 0x410 */ + u32 pinumx6; /* 0x414 */ + u32 pinumx7; /* 0x418 */ + u32 pinumx8; /* 0x41c */ + u32 pinumx9; /* 0x420 */ + u32 pinumx10; /* 0x424 */ + u32 pinumx11; /* 0x428 */ + u32 pinumx12; /* 0x42c */ + u32 pinumx13; /* 0x430 */ + u32 pinumx14; /* 0x434 */ + u32 pinumx15; /* 0x438 */ + u32 pinumx16; /* 0x43c */ + u32 pinumx17; /* 0x440 */ + u32 pinumx18; /* 0x444 */ + u32 pinumx19; /* 0x448 */ + u32 pinumx20; /* 0x44c */ + u32 pinumx21; /* 0x450 */ + u32 pinumx22; /* 0x454 */ + u32 pinumx23; /* 0x458 */ + u32 pinumx24; /* 0x45c */ + u32 pinumx25; /* 0x460 */ + u32 pinumx26; /* 0x464 */ + u32 pinumx27; /* 0x468 */ + u32 rsv_0x46c[4]; /* 0x46c ~ 0x478 */ + u32 pinumx31; /* 0x47c */ + u32 pull_down_dis[8]; /* 0x480 ~ 0x49c */ + u32 pin_conf; /* 0x4a0 */ + u32 rsv_0x4a4[7]; /* 0x4a4 ~ 0x4bc */ + u32 io_driving0; /* 0x4c0 */ + u32 io_driving1; /* 0x4c4 */ + u32 io_driving2; /* 0x4c8 */ + u32 io_driving3; /* 0x4cc */ + u32 io_driving4; /* 0x4d0 */ + u32 io_driving5; /* 0x4d4 */ + u32 io_driving6; /* 0x4d8 */ + u32 io_driving7; /* 0x4dc */ + u32 io_driving8; /* 0x4e0 */ +}; + +#endif +#endif diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index c88b1e59366..f4b038ebd9e 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -36,9 +36,20 @@ config ASPEED_AST2600 It is used as Board Management Controller on many server boards, which is enabled by support of LPC and eSPI peripherals. +config ASPEED_AST2700 + bool "Support Aspeed AST2700 SoC" + select ARM64 + select SYS_ARCH_TIMER + help + Support for the Aspeed AST2700, an arm64 (Cortex-A35) Baseboard + Management Controller (BMC) SoC. This is the 8th-generation BMC + SoC family from Aspeed and features a dual-die architecture + (CPU die + I/O die) connected via an internal coherent bus. + endchoice source "arch/arm/mach-aspeed/ast2500/Kconfig" source "arch/arm/mach-aspeed/ast2600/Kconfig" +source "arch/arm/mach-aspeed/ast2700/Kconfig" endif diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile index 42599c125b8..d0b4eb74c6c 100644 --- a/arch/arm/mach-aspeed/Makefile +++ b/arch/arm/mach-aspeed/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_ARCH_ASPEED) += ast_wdt.o obj-$(CONFIG_ASPEED_AST2500) += ast2500/ obj-$(CONFIG_ASPEED_AST2600) += ast2600/ +obj-$(CONFIG_ASPEED_AST2700) += ast2700/ diff --git a/arch/arm/mach-aspeed/ast2700/Kconfig b/arch/arm/mach-aspeed/ast2700/Kconfig new file mode 100644 index 00000000000..3dd68db76db --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/Kconfig @@ -0,0 +1,36 @@ +if ASPEED_AST2700 + +config SYS_CPU + default "armv8" + +config SPI_KERNEL_FIT_ADDR + hex "SPI address of kernel FIT image" + default 0x100420000 + help + Address in the SPI flash where the kernel FIT image is stored. + Used by the bootspi command to load and boot the kernel image + from the SPI flash on AST2700 platforms. + +choice + prompt "AST2700 board select" + depends on ASPEED_AST2700 + default TARGET_EVB_AST2700 + help + Select the AST2700 board model. Each board option configures + the board-specific Kconfig, defaults and devicetree. + +config TARGET_EVB_AST2700 + bool "EVB-AST2700" + depends on ASPEED_AST2700 + select ARCH_MISC_INIT + help + EVB-AST2700 is Aspeed evaluation board for AST2700A0 chip. + It has 512M of RAM, 32M of SPI flash, two Ethernet ports, + 4 Serial ports, 4 USB ports, VGA port, PCIe, SD card slot, + 20 pin JTAG, pinouts for 14 I2Cs, 3 SPIs and eSPI, 8 PWMs. + +endchoice + +source "board/aspeed/evb_ast2700/Kconfig" + +endif diff --git a/arch/arm/mach-aspeed/ast2700/Makefile b/arch/arm/mach-aspeed/ast2700/Makefile new file mode 100644 index 00000000000..38bd52f3d5d --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/Makefile @@ -0,0 +1,2 @@ +obj-y += lowlevel_init.o board_common.o arm64-mmu.o platform.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o diff --git a/arch/arm/mach-aspeed/ast2700/arm64-mmu.c b/arch/arm/mach-aspeed/ast2700/arm64-mmu.c new file mode 100644 index 00000000000..a068e6ede97 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/arm64-mmu.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include +#include + +static struct mm_region aspeed2700_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, + { + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x2C0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE, + }, + { + .virt = 0x400000000UL, + .phys = 0x400000000UL, + .size = 0x200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = aspeed2700_mem_map; + +u64 get_page_table_size(void) +{ + return 0x80000; +} diff --git a/arch/arm/mach-aspeed/ast2700/board_common.c b/arch/arm/mach-aspeed/ast2700/board_common.c new file mode 100644 index 00000000000..6d2160bbca4 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/board_common.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AHBC_GROUP(x) (0x40 * (x)) +#define AHBC_HREADY_WAIT_CNT_REG 0x34 +#define AHBC_HREADY_WAIT_CNT_MAX 0x3f + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + struct udevice *dev; + struct ram_info ram; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("cannot get DRAM driver\n"); + debug("cannot get DRAM driver\n"); + return ret; + } + + ret = ram_get_info(dev, &ram); + if (ret) { + debug("cannot get DRAM information\n"); + return ret; + } + + gd->ram_size = ram.size; + + return 0; +} + +static void ahbc_init(void) +{ + u32 reg_val; + int i; + + reg_val = readl(ASPEED_CPU_REVISION_ID); + if (FIELD_GET(SCU_CPU_REVISION_ID_HW, reg_val)) + return; + + /* CPU-die AHBC timeout counter */ + for (i = 0; i < 4; i++) + writel(AHBC_HREADY_WAIT_CNT_MAX, + (void *)ASPEED_CPU_AHBC_BASE + AHBC_GROUP(i) + AHBC_HREADY_WAIT_CNT_REG); + + /* IO-die AHBC timeout counter */ + for (i = 0; i < 8; i++) + writel(AHBC_HREADY_WAIT_CNT_MAX, + (void *)ASPEED_IO_AHBC_BASE + AHBC_GROUP(i) + AHBC_HREADY_WAIT_CNT_REG); +} + +int board_init(void) +{ + struct udevice *dev; + int i = 0; + int ret; + + ahbc_init(); + + /* + * Loop over all MISC uclass drivers to call the comphy code + * and init all CP110 devices enabled in the DT + */ + while (1) { + /* Call the comphy code via the MISC uclass driver */ + ret = uclass_get_device(UCLASS_MISC, i++, &dev); + + /* We're done, once no further CP110 device is found */ + if (ret) + break; + } + + return 0; +} diff --git a/arch/arm/mach-aspeed/ast2700/cpu-info.c b/arch/arm/mach-aspeed/ast2700/cpu-info.c new file mode 100644 index 00000000000..7f29c4d8c33 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/cpu-info.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + * Ryan Chen + */ + +#include +#include +#include +#include + +/* SoC mapping Table */ +#define SOC_ID(str, rev) { .name = str, .rev_id = rev, } + +struct soc_id { + const char *name; + u64 rev_id; +}; + +static struct soc_id soc_map_table[] = { + SOC_ID("AST2750-A0", 0x0600000306000003), + SOC_ID("AST2700-A0", 0x0600010306000103), + SOC_ID("AST2720-A0", 0x0600020306000203), + SOC_ID("AST2750-A1", 0x0601000306010003), + SOC_ID("AST2700-A1", 0x0601010306010103), + SOC_ID("AST2720-A1", 0x0601020306010203), + SOC_ID("AST2750-A2", 0x0602000306020003), + SOC_ID("AST2700-A2", 0x0602010306020103), + SOC_ID("AST2720-A2", 0x0602020306020203), +}; + +void ast2700_print_soc_id(void) +{ + int i; + u64 rev_id; + + rev_id = readl(ASPEED_CPU_REVISION_ID); + rev_id = ((u64)readl(ASPEED_IO_REVISION_ID) << 32) | rev_id; + + for (i = 0; i < ARRAY_SIZE(soc_map_table); i++) { + if (rev_id == soc_map_table[i].rev_id) + break; + } + if (i == ARRAY_SIZE(soc_map_table)) + printf("Unknown-SOC: %llx\n", rev_id); + else + printf("SOC: %4s\n", soc_map_table[i].name); +} + +#define SYS_DRAM_ECCRST BIT(3) +#define SYS_ABRRST BIT(2) +#define SYS_EXTRST BIT(1) +#define SYS_SRST BIT(0) + +#define WDT_RST_BIT_MASK(s) (GENMASK(3, 0) << (s)) +#define BIT_WDT_FULL(s) (BIT(0) << (s)) +#define BIT_WDT_ARM(s) (BIT(1) << (s)) +#define BIT_WDT_SOC(s) (BIT(2) << (s)) +#define BIT_WDT_SW(s) (BIT(3) << (s)) + +void ast2700_print_wdtrst_info(void) +{ + u32 wdt_rst = readl(ASPEED_IO_RESET_LOG4); + int i; + + for (i = 0; i < 8; i++) { + if (wdt_rst & WDT_RST_BIT_MASK(i * 4)) { + printf("RST: WDT%d ", i); + if (wdt_rst & BIT_WDT_SOC(i * 4)) { + printf("SOC "); + writel(BIT_WDT_SOC(i * 4), ASPEED_IO_RESET_LOG4); + } + if (wdt_rst & BIT_WDT_FULL(i * 4)) { + printf("FULL "); + writel(BIT_WDT_FULL(i * 4), ASPEED_IO_RESET_LOG4); + } + if (wdt_rst & BIT_WDT_ARM(i * 4)) { + printf("ARM "); + writel(BIT_WDT_ARM(i * 4), ASPEED_IO_RESET_LOG4); + } + if (wdt_rst & BIT_WDT_SW(i * 4)) { + printf("SW "); + writel(BIT_WDT_SW(i * 4), ASPEED_IO_RESET_LOG4); + } + printf("\n"); + } + } +} + +#define SYS_EXTRST BIT(1) +#define SYS_SRST BIT(0) + +void ast2700_print_sysrst_info(void) +{ + u32 sys_rst = readl(ASPEED_CPU_RESET_LOG1); + + if (sys_rst & SYS_SRST) { + printf("RST: Power On\n"); + writel(SYS_SRST, ASPEED_CPU_RESET_LOG1); + } else if (sys_rst & SYS_EXTRST) { + printf("RST: EXTRST\n"); + writel(SYS_EXTRST, ASPEED_CPU_RESET_LOG1); + } else { + ast2700_print_wdtrst_info(); + } +} + +int print_cpuinfo(void) +{ + ast2700_print_soc_id(); + ast2700_print_sysrst_info(); + + return 0; +} diff --git a/arch/arm/mach-aspeed/ast2700/lowlevel_init.S b/arch/arm/mach-aspeed/ast2700/lowlevel_init.S new file mode 100644 index 00000000000..9b78fed0b26 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/lowlevel_init.S @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) ASPEED Technology Inc. + */ +#include +#include + +/* + * SMP mailbox + * +-----------------------+ 0x40 + * | | + * | mailbox insn. for | + * | cpuN GO sign polling | + * | | + * +-----------------------+ 0x20 + * | cpu3 entrypoint | + * +-----------------------+ 0x18 + * | cpu2 entrypoint | + * +-----------------------+ 0x10 + * | cpu1 entrypoint | + * +-----------------------+ 0x8 + * | reserved | + * +-----------------------+ 0x4 + * | mailbox ready | + * +-----------------------+ SCU_CPU + 0x780 + */ + +#define SCU_CPU_BASE 0x12c02000 +#define SCU_CPU_SMP_READY (SCU_CPU_BASE + 0x780) +#define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788) +#define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790) +#define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798) +#define SCU_CPU_SMP_POLLINSN (SCU_CPU_BASE + 0x7a0) + +ENTRY(lowlevel_init) + /* backup LR */ + mov x29, lr + +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + /* reset SMP mailbox ASAP */ + ldr x0, =SCU_CPU_SMP_READY + str wzr, [x0] + + /* + * get cpu core id + * + * ast2700 has 1-cluster, 4-cores CPU topology. + * Affinity level 0 in MPIDR is sufficient. + */ + mrs x4, mpidr_el1 + ands x4, x4, #0xff + + /* cpu0 is the primary core to setup SMP mailbox */ + beq do_primary_core_setup + + /* hold cpuN until mailbox is ready */ + ldr x0, =SCU_CPU_SMP_READY + movz w1, #0xcafe + movk w1, #0xbabe, lsl #16 + +poll_mailbox_ready: + wfe + ldr w2, [x0] + cmp w1, w2 + bne poll_mailbox_ready + + /* + * parameters for relocated SMP go polling insn. + * x4 = cpu id + * x5 = SCU_CPU_SMP_EPx + */ + add x5, x0, x4, lsl #3 + + /* jump to the polling loop in SMP mailbox, no return */ + ldr x0, =SCU_CPU_SMP_POLLINSN + br x0 + +do_primary_core_setup: + /* relocate mailbox insn. for cpuN to poll for SMP go signal */ + adr x0, smp_mbox_insn + adr x1, smp_mbox_insn_end + ldr x2, =SCU_CPU_SMP_POLLINSN + +relocate_smp_mbox_insn: + ldr w3, [x0], #0x4 + str w3, [x2], #0x4 + cmp x0, x1 + bne relocate_smp_mbox_insn + + /* reset cpuN entrypoints */ + ldr x0, =SCU_CPU_SMP_EP1 + str xzr, [x0], #8 + str xzr, [x0], #8 + str xzr, [x0] + + /* notify cpuN that SMP mailbox is ready */ + movz w0, #0xcafe + movk w0, #0xbabe, lsl #16 + ldr x1, =SCU_CPU_SMP_READY + str w0, [x1] + + sev +#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ + + /* back to arch calling code */ + mov lr, x29 + ret +ENDPROC(lowlevel_init) + +/* + * insn. inside mailbox to poll SMP go signal. + * + * Note that this code will be relocated, any absolute + * addressing should NOT be used. + */ +smp_mbox_insn: + /* + * x4 = cpu id + * x5 = SCU_CPU_SMP_EPx + */ +poll_smp_mbox_go: + wfe + ldr x0, [x5] + cmp x0, xzr + beq poll_smp_mbox_go + + /* jump to secondary core entrypoint */ + br x0 + +smp_mbox_insn_end: + /* should never reach */ + b . diff --git a/arch/arm/mach-aspeed/ast2700/platform.c b/arch/arm/mach-aspeed/ast2700/platform.c new file mode 100644 index 00000000000..9cca85766f6 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/platform.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum env_location env_get_location(enum env_operation op, int prio) +{ + enum env_location env_loc = ENVL_UNKNOWN; + u32 strap = readl(ASPEED_IO_HW_STRAP1); + + if (prio) + return env_loc; + + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) { + env_loc = ENVL_NOWHERE; + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH) && + !(strap & SCU_IO_HWSTRAP_EMMC)) { + env_loc = ENVL_SPI_FLASH; + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) && + (strap & SCU_IO_HWSTRAP_EMMC) && + !(strap & SCU_IO_HWSTRAP_UFS)) { + env_loc = ENVL_MMC; + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) { + /* + * This tree does not carry an ENV_IS_IN_UFS backend yet. + * Fall back to SPI flash when that backend exists. + */ + env_loc = ENVL_SPI_FLASH; + } else { + env_loc = ENVL_NOWHERE; + } + + return env_loc; +} + +int arch_misc_init(void) +{ + if (IS_ENABLED(CONFIG_ARCH_MISC_INIT)) { + if ((readl(ASPEED_IO_HW_STRAP1) & SCU_IO_HWSTRAP_EMMC)) { + if ((readl(ASPEED_IO_HW_STRAP1) & SCU_IO_HWSTRAP_UFS)) + env_set("boot_device", "ufs"); + else + env_set("boot_device", "mmc"); + } else { + env_set("boot_device", "spi"); + } + + if ((readl(ASPEED_IO_HW_STRAP1) & SCU_IO_HWSTRAP_SECBOOT)) + env_set("verify", "yes"); + else + env_set("verify", "no"); + } + + return 0; +} diff --git a/board/aspeed/evb_ast2700/Kconfig b/board/aspeed/evb_ast2700/Kconfig new file mode 100644 index 00000000000..ede9eb7fb85 --- /dev/null +++ b/board/aspeed/evb_ast2700/Kconfig @@ -0,0 +1,13 @@ +if TARGET_EVB_AST2700 + +config SYS_BOARD + default "evb_ast2700" + +config SYS_VENDOR + default "aspeed" + +config SYS_CONFIG_NAME + string "board configuration name" + default "evb_ast2700" + +endif diff --git a/board/aspeed/evb_ast2700/Makefile b/board/aspeed/evb_ast2700/Makefile new file mode 100644 index 00000000000..0c29700f5a9 --- /dev/null +++ b/board/aspeed/evb_ast2700/Makefile @@ -0,0 +1 @@ +obj-y += evb_ast2700.o diff --git a/board/aspeed/evb_ast2700/evb_ast2700.c b/board/aspeed/evb_ast2700/evb_ast2700.c new file mode 100644 index 00000000000..b34aa6e1682 --- /dev/null +++ b/board/aspeed/evb_ast2700/evb_ast2700.c @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + diff --git a/configs/evb-ast2700_defconfig b/configs/evb-ast2700_defconfig new file mode 100644 index 00000000000..d0733e14c67 --- /dev/null +++ b/configs/evb-ast2700_defconfig @@ -0,0 +1,160 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_POSITION_INDEPENDENT=y +# CONFIG_INIT_SP_RELATIVE is not set +CONFIG_ARM_SMCCC=y +CONFIG_ARCH_ASPEED=y +CONFIG_TEXT_BASE=0x400000000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_ASPEED_AST2700=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x403000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="ast2700-evb" +CONFIG_DM_RESET=y +CONFIG_SYS_LOAD_ADDR=0x403000000 +CONFIG_DEBUG_UART_BASE=0x14c33b00 +CONFIG_DEBUG_UART_CLOCK=1846154 +# CONFIG_PSCI_RESET is not set +CONFIG_ARMV8_CRYPTO=y +CONFIG_ENV_ADDR=0x400000 +CONFIG_SYS_PCI_64BIT=y +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_SYS_MEMTEST_START=0x403000000 +CONFIG_SYS_MEMTEST_END=0x403001000 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +# CONFIG_BOOTMETH_EFILOADER is not set +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS12,115200n8 root=/dev/ram rw earlycon" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="echo Boot from ${boot_device}; if test ${boot_device} = mmc; then run bootmmc; fi; if test ${boot_device} = spi; then run bootspi; fi; if test ${boot_device} = ufs; then run bootufs; fi;" +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTFLOW is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_BOOTEFI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNLZ4 is not set +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_UFS=y +CONFIG_CMD_NCSI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_EFICONFIG is not set +CONFIG_CMD_TPM=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_CMD_CYCLIC is not set +CONFIG_DOS_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_MMC_USE_DT=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="ast2700-evb" +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_HASH=y +CONFIG_DFU_RAM=y +CONFIG_GPIO_HOG=y +CONFIG_ASPEED_G7_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AST2600=y +# CONFIG_INPUT is not set +CONFIG_DM_MAILBOX=y +CONFIG_I2C_EEPROM=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ASPEED=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_DM_MDIO=y +CONFIG_FTGMAC100=y +CONFIG_ASPEED_MDIO=y +CONFIG_PHY_BROADCOM=y +CONFIG_PHY_AIROHA=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_NCSI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_CONFIG_HOST_BRIDGE=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SPI_DIRMAP=y +CONFIG_SPI_ASPEED_SMC=y +CONFIG_SYSRESET=y +# CONFIG_TPM_V1 is not set +CONFIG_TPM2_TIS_SPI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="ASPEED" +CONFIG_USB_GADGET_VENDOR_NUM=0x2245 +CONFIG_USB_GADGET_PRODUCT_NUM=0x2700 +CONFIG_USB_GADGET_OS_DESCRIPTORS=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_UFS=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +# CONFIG_WDT_ASPEED is not set +CONFIG_ECDSA=y +CONFIG_ECDSA_VERIFY=y +CONFIG_TPM=y +CONFIG_LZ4=y +CONFIG_LZMA=y +# CONFIG_TOOLS_MKEFICAPSULE is not set diff --git a/include/configs/evb_ast2700.h b/include/configs/evb_ast2700.h new file mode 100644 index 00000000000..6b73eddc1af --- /dev/null +++ b/include/configs/evb_ast2700.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* Extra ENV for Boot Command */ +#define STR_HELPER(n) #n +#define STR(n) STR_HELPER(n) + +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE + +#define CFG_EXTRA_ENV_SETTINGS \ + "bootspi=fdt addr ${fdtspiaddr} && " \ + "fdt header get fitsize totalsize && " \ + "cp.b ${fdtspiaddr} ${loadaddr} ${fitsize} && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "loadaddr=" STR(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootside=a\0" \ + "rootfs=rofs-a\0" \ + "setmmcargs=setenv bootargs ${bootargs} " \ + "rootwait root=PARTLABEL=${rootfs}\0" \ + "boota=setenv bootpart 2; setenv rootfs rofs-a; " \ + "run setmmcargs; " \ + "ext4load mmc 0:${bootpart} ${loadaddr} fitImage && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "bootb=setenv bootpart 3; setenv rootfs rofs-b; " \ + "run setmmcargs; " \ + "ext4load mmc 0:${bootpart} ${loadaddr} fitImage && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "bootmmc=if test \"${bootside}\" = \"b\"; " \ + "then run bootb; run boota; " \ + "else run boota; run bootb; fi\0" \ + "setufsargs=setenv bootargs ${bootargs} " \ + "rootwait root=PARTLABEL=${rootfs}\0" \ + "ufsboota=setenv bootpart 2; setenv rootfs rofs-a; " \ + "run setufsargs; " \ + "ext4load scsi 0:${bootpart} ${loadaddr} fitImage && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "ufsbootb=setenv bootpart 3; setenv rootfs rofs-b; " \ + "run setufsargs; " \ + "ext4load scsi 0:${bootpart} ${loadaddr} fitImage && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "bootufs=if test \"${bootside}\" = \"b\"; " \ + "then run ufsbootb; run ufsboota; " \ + "else run ufsboota; run ufsbootb; fi\0" \ + "verify=no\0" \ + "" +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 4a0990218aa9185c2ccd7986dc1ad14b24aaaa9d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 12 Jun 2026 03:59:06 +0200 Subject: cros_ec: Convert dm_cros_ec_get_ops into an inline function and constify dm_cros_ec_ops Convert dm_cros_ec_get_ops into an inline function to improve compiler code coverage, and constify struct dm_cros_ec_ops in a few places. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/misc/cros_ec.c | 9 ++++----- include/cros_ec.h | 7 +++++-- 2 files changed, 9 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index c3e647edfac..e163224b8e3 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -258,7 +258,7 @@ static int send_command_proto3(struct cros_ec_dev *cdev, const void *dout, int dout_len, uint8_t **dinp, int din_len) { - struct dm_cros_ec_ops *ops; + const struct dm_cros_ec_ops *ops; int out_bytes, in_bytes; int rv; @@ -287,7 +287,7 @@ static int send_command(struct cros_ec_dev *dev, uint cmd, int cmd_version, const void *dout, int dout_len, uint8_t **dinp, int din_len) { - struct dm_cros_ec_ops *ops; + const struct dm_cros_ec_ops *ops; int ret = -1; /* Handle protocol version 3 support */ @@ -756,9 +756,8 @@ int cros_ec_flash_protect(struct udevice *dev, uint32_t set_mask, static int cros_ec_check_version(struct udevice *dev) { struct cros_ec_dev *cdev = dev_get_uclass_priv(dev); + const struct dm_cros_ec_ops *ops; struct ec_params_hello req; - - struct dm_cros_ec_ops *ops; int ret; ops = dm_cros_ec_get_ops(dev); @@ -1638,7 +1637,7 @@ int cros_ec_vstore_write(struct udevice *dev, int slot, const uint8_t *data, int cros_ec_get_switches(struct udevice *dev) { - struct dm_cros_ec_ops *ops; + const struct dm_cros_ec_ops *ops; int ret; ops = dm_cros_ec_get_ops(dev); diff --git a/include/cros_ec.h b/include/cros_ec.h index 4ef34815e35..6e5153ceb6a 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -12,6 +12,7 @@ #include #include #include +#include #include /* @@ -316,8 +317,10 @@ struct dm_cros_ec_ops { int (*get_switches)(struct udevice *dev); }; -#define dm_cros_ec_get_ops(dev) \ - ((struct dm_cros_ec_ops *)(dev)->driver->ops) +static inline const struct dm_cros_ec_ops *dm_cros_ec_get_ops(struct udevice *dev) +{ + return (const struct dm_cros_ec_ops *)(dev->driver->ops); +} int cros_ec_register(struct udevice *dev); -- cgit v1.3.1 From d5046398433e48e7b0b664c1ee3e4e2af6f861a8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 12 Jun 2026 04:05:38 +0200 Subject: treewide: Staticize and constify acpi ops Set the acpi_ops structure as static const where applicable. The The structure is not accessible from outside of drivers and is not going to be modified at runtime. The structure may be unused in a couple of drivers depending on their configuration, mark those sites with __maybe_unused . Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- arch/arm/lib/gic-v2.c | 2 +- arch/arm/lib/gic-v3-its.c | 2 +- arch/x86/cpu/apollolake/cpu.c | 4 +--- arch/x86/cpu/apollolake/hostbridge.c | 2 +- arch/x86/cpu/apollolake/lpc.c | 2 +- arch/x86/cpu/intel_common/generic_wifi.c | 2 +- arch/x86/lib/fsp/fsp_graphics.c | 2 +- board/google/chromebook_coral/coral.c | 2 +- drivers/core/acpi.c | 4 ++-- drivers/core/root.c | 2 +- drivers/cpu/armv8_cpu.c | 2 +- drivers/cpu/bcm283x_cpu.c | 2 +- drivers/gpio/sandbox.c | 4 ++-- drivers/i2c/designware_i2c_pci.c | 2 +- drivers/mmc/pci_mmc.c | 4 ++-- drivers/rtc/sandbox_rtc.c | 2 +- drivers/sound/da7219.c | 2 +- drivers/sound/max98357a.c | 2 +- drivers/tpm/cr50_i2c.c | 2 +- include/dm/device.h | 2 +- test/dm/acpi.c | 2 +- 21 files changed, 24 insertions(+), 26 deletions(-) (limited to 'include') diff --git a/arch/arm/lib/gic-v2.c b/arch/arm/lib/gic-v2.c index b70434a45d4..378bdb54c89 100644 --- a/arch/arm/lib/gic-v2.c +++ b/arch/arm/lib/gic-v2.c @@ -38,7 +38,7 @@ static int acpi_gicv2_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -static struct acpi_ops gic_v2_acpi_ops = { +static const struct acpi_ops gic_v2_acpi_ops = { .fill_madt = acpi_gicv2_fill_madt, }; #endif diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c index d11a1ea436e..064b93b2aa1 100644 --- a/arch/arm/lib/gic-v3-its.c +++ b/arch/arm/lib/gic-v3-its.c @@ -197,7 +197,7 @@ static int acpi_gicv3_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -struct acpi_ops gic_v3_acpi_ops = { +static const struct acpi_ops gic_v3_acpi_ops = { .fill_madt = acpi_gicv3_fill_madt, }; #endif diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c index f480bb1d8c3..d1f592ec57e 100644 --- a/arch/x86/cpu/apollolake/cpu.c +++ b/arch/x86/cpu/apollolake/cpu.c @@ -171,11 +171,9 @@ static int cpu_apl_probe(struct udevice *dev) return 0; } -#ifdef CONFIG_ACPIGEN -struct acpi_ops apl_cpu_acpi_ops = { +static const struct acpi_ops __maybe_unused apl_cpu_acpi_ops = { .fill_ssdt = acpi_cpu_fill_ssdt, }; -#endif static const struct cpu_ops cpu_x86_apl_ops = { .get_desc = cpu_x86_get_desc, diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c index 284f16cfd91..360d091121c 100644 --- a/arch/x86/cpu/apollolake/hostbridge.c +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -366,7 +366,7 @@ ulong sa_get_tseg_base(struct udevice *dev) return sa_read_reg(dev, TSEG); } -struct acpi_ops apl_hostbridge_acpi_ops = { +static const struct acpi_ops __maybe_unused apl_hostbridge_acpi_ops = { .get_name = apl_acpi_hb_get_name, #if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) .write_tables = apl_acpi_hb_write_tables, diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c index f34c199bf73..008c4dc0037 100644 --- a/arch/x86/cpu/apollolake/lpc.c +++ b/arch/x86/cpu/apollolake/lpc.c @@ -119,7 +119,7 @@ static int apl_acpi_lpc_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "LPCB"); } -struct acpi_ops apl_lpc_acpi_ops = { +static const struct acpi_ops __maybe_unused apl_lpc_acpi_ops = { .get_name = apl_acpi_lpc_get_name, #ifdef CONFIG_GENERATE_ACPI_TABLE .write_tables = intel_southbridge_write_acpi_tables, diff --git a/arch/x86/cpu/intel_common/generic_wifi.c b/arch/x86/cpu/intel_common/generic_wifi.c index 75fa4e01d8a..1a24c10ab0b 100644 --- a/arch/x86/cpu/intel_common/generic_wifi.c +++ b/arch/x86/cpu/intel_common/generic_wifi.c @@ -102,7 +102,7 @@ static int intel_wifi_acpi_fill_ssdt(const struct udevice *dev, return 0; } -struct acpi_ops wifi_acpi_ops = { +static const struct acpi_ops wifi_acpi_ops = { .fill_ssdt = intel_wifi_acpi_fill_ssdt, }; diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index ad25020086c..d425e80760b 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -150,7 +150,7 @@ static int fsp_video_acpi_write_tables(const struct udevice *dev, } #endif -struct acpi_ops fsp_video_acpi_ops = { +static const struct acpi_ops __maybe_unused fsp_video_acpi_ops = { #ifdef CONFIG_INTEL_GMA_ACPI .write_tables = fsp_video_acpi_write_tables, #endif diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index b4053fa097d..2bb54d59bb8 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -293,7 +293,7 @@ static int coral_write_acpi_tables(const struct udevice *dev, return 0; } -struct acpi_ops coral_acpi_ops = { +static const struct acpi_ops __maybe_unused coral_acpi_ops = { .write_tables = coral_write_acpi_tables, .inject_dsdt = chromeos_acpi_gpio_generate, }; diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c index 6a431171c8d..284fb70b036 100644 --- a/drivers/core/acpi.c +++ b/drivers/core/acpi.c @@ -87,7 +87,7 @@ int acpi_copy_name(char *out_name, const char *name) int acpi_get_name(const struct udevice *dev, char *out_name) { - struct acpi_ops *aops; + const struct acpi_ops *aops; const char *name; int ret; @@ -275,7 +275,7 @@ static int sort_acpi_item_type(struct acpi_ctx *ctx, void *start, acpi_method acpi_get_method(struct udevice *dev, enum method_t method) { - struct acpi_ops *aops; + const struct acpi_ops *aops; aops = device_get_acpi_ops(dev); if (aops) { diff --git a/drivers/core/root.c b/drivers/core/root.c index 1f32f33b295..2aa16d59b69 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -459,7 +459,7 @@ static int root_acpi_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "\\_SB"); } -struct acpi_ops root_acpi_ops = { +static const struct acpi_ops root_acpi_ops = { .get_name = root_acpi_get_name, }; #endif diff --git a/drivers/cpu/armv8_cpu.c b/drivers/cpu/armv8_cpu.c index ed87841b723..337661c23a8 100644 --- a/drivers/cpu/armv8_cpu.c +++ b/drivers/cpu/armv8_cpu.c @@ -124,7 +124,7 @@ int armv8_cpu_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -static struct acpi_ops armv8_cpu_acpi_ops = { +static const struct acpi_ops armv8_cpu_acpi_ops = { .fill_ssdt = armv8_cpu_fill_ssdt, .fill_madt = armv8_cpu_fill_madt, }; diff --git a/drivers/cpu/bcm283x_cpu.c b/drivers/cpu/bcm283x_cpu.c index ad638cd8fff..43e74d1811b 100644 --- a/drivers/cpu/bcm283x_cpu.c +++ b/drivers/cpu/bcm283x_cpu.c @@ -193,7 +193,7 @@ static int bcm_cpu_probe(struct udevice *dev) return ret; } -struct acpi_ops bcm283x_cpu_acpi_ops = { +static const struct acpi_ops __maybe_unused bcm283x_cpu_acpi_ops = { .fill_ssdt = armv8_cpu_fill_ssdt, .fill_madt = armv8_cpu_fill_madt, }; diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c index e8f50d815d7..76aff0ed5aa 100644 --- a/drivers/gpio/sandbox.c +++ b/drivers/gpio/sandbox.c @@ -306,7 +306,7 @@ static int sb_gpio_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "GPIO"); } -struct acpi_ops gpio_sandbox_acpi_ops = { +static const struct acpi_ops gpio_sandbox_acpi_ops = { .get_name = sb_gpio_get_name, }; #endif /* ACPIGEN */ @@ -568,7 +568,7 @@ static struct pinctrl_ops sandbox_pinctrl_gpio_ops = { }; #if CONFIG_IS_ENABLED(ACPIGEN) -struct acpi_ops pinctrl_sandbox_acpi_ops = { +static const struct acpi_ops pinctrl_sandbox_acpi_ops = { .get_name = sb_pinctrl_get_name, }; #endif diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index ad4122c2abd..db2706fdb6e 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -168,7 +168,7 @@ static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev, return 0; } -static struct acpi_ops dw_i2c_acpi_ops = { +static const struct acpi_ops dw_i2c_acpi_ops = { .fill_ssdt = dw_i2c_acpi_fill_ssdt, }; diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index d446c55f72b..82e393fd9d6 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -137,11 +137,11 @@ static int pci_mmc_acpi_fill_ssdt(const struct udevice *dev, return 0; } -struct acpi_ops pci_mmc_acpi_ops = { #ifdef CONFIG_ACPIGEN +static const struct acpi_ops pci_mmc_acpi_ops = { .fill_ssdt = pci_mmc_acpi_fill_ssdt, -#endif }; +#endif static const struct udevice_id pci_mmc_match[] = { { .compatible = "intel,apl-sd", .data = TYPE_SD }, diff --git a/drivers/rtc/sandbox_rtc.c b/drivers/rtc/sandbox_rtc.c index 4404501c2f6..1ade5d50b23 100644 --- a/drivers/rtc/sandbox_rtc.c +++ b/drivers/rtc/sandbox_rtc.c @@ -73,7 +73,7 @@ static int sandbox_rtc_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "RTCC"); } -struct acpi_ops sandbox_rtc_acpi_ops = { +static const struct acpi_ops sandbox_rtc_acpi_ops = { .get_name = sandbox_rtc_get_name, }; #endif diff --git a/drivers/sound/da7219.c b/drivers/sound/da7219.c index 5b9b3f65263..d1d03ae91d4 100644 --- a/drivers/sound/da7219.c +++ b/drivers/sound/da7219.c @@ -170,7 +170,7 @@ static int da7219_acpi_setup_nhlt(const struct udevice *dev, } #endif -struct acpi_ops da7219_acpi_ops = { +static const struct acpi_ops da7219_acpi_ops = { #ifdef CONFIG_ACPIGEN .fill_ssdt = da7219_acpi_fill_ssdt, #ifdef CONFIG_X86 diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c index da56ffdd6bb..47978d4fe27 100644 --- a/drivers/sound/max98357a.c +++ b/drivers/sound/max98357a.c @@ -136,7 +136,7 @@ static int max98357a_acpi_setup_nhlt(const struct udevice *dev, } #endif -struct acpi_ops max98357a_acpi_ops = { +static const struct acpi_ops max98357a_acpi_ops = { #ifdef CONFIG_ACPIGEN .fill_ssdt = max98357a_acpi_fill_ssdt, #ifdef CONFIG_X86 diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c index 14a94f8d4a8..46805eaa013 100644 --- a/drivers/tpm/cr50_i2c.c +++ b/drivers/tpm/cr50_i2c.c @@ -889,7 +889,7 @@ static int cr50_i2c_probe(struct udevice *dev) return 0; } -struct acpi_ops cr50_acpi_ops = { +static const struct acpi_ops cr50_acpi_ops = { .fill_ssdt = cr50_acpi_fill_ssdt, }; diff --git a/include/dm/device.h b/include/dm/device.h index 7bcf6df2892..5d700888503 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -388,7 +388,7 @@ struct driver { const void *ops; /* driver-specific operations */ uint32_t flags; #if CONFIG_IS_ENABLED(ACPIGEN) - struct acpi_ops *acpi_ops; + const struct acpi_ops *acpi_ops; #endif }; diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 2de7983f9ae..293ea0274b5 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -136,7 +136,7 @@ static int testacpi_inject_dsdt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -struct acpi_ops testacpi_ops = { +static const struct acpi_ops testacpi_ops = { .get_name = testacpi_get_name, .write_tables = testacpi_write_tables, .fill_madt = testacpi_fill_madt, -- cgit v1.3.1 From 93e9af685fefc454580dcf567b03c139a2fe8ebc Mon Sep 17 00:00:00 2001 From: Denis Mukhin Date: Tue, 23 Jun 2026 15:06:30 -0700 Subject: test: bootdev: scan with a broken high-priority device Add bootdev_hunt_fallthrough() test to verify that 'bootflow scan -l' falls back to a lower-priority bootdev when a higher-priority hunter fails. Introduce a simple 'sandbox-bootdev' device for the test. The new bootdev can be configured to produce an error at the hunting stage. Introduce new host_set_flags_by_label() API and a flags field to 'host_sb_plat' to simulate a bootdev hunter failure for the test. Adjust boot{dev,flow} tests which depend on bootdev hunters. Signed-off-by: Denis Mukhin Reviewed-by: Simon Glass --- drivers/block/Makefile | 2 +- drivers/block/host-uclass.c | 15 +++++++++ drivers/block/sandbox-bootdev.c | 73 +++++++++++++++++++++++++++++++++++++++++ include/sandbox_host.h | 18 ++++++++++ test/boot/bootdev.c | 23 ++++++------- test/boot/bootflow.c | 47 ++++++++++++++++++++++++++ test/boot/bootstd_common.h | 5 ++- 7 files changed, 170 insertions(+), 13 deletions(-) create mode 100644 drivers/block/sandbox-bootdev.c (limited to 'include') diff --git a/drivers/block/Makefile b/drivers/block/Makefile index f5a9d8637a3..c827fa81a2d 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -13,7 +13,7 @@ ifndef CONFIG_XPL_BUILD obj-$(CONFIG_IDE) += ide.o obj-$(CONFIG_RKMTD) += rkmtd.o endif -obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o +obj-$(CONFIG_SANDBOX) += sandbox.o sandbox-bootdev.o host-uclass.o host_dev.o obj-$(CONFIG_$(PHASE_)BLOCK_CACHE) += blkcache.o obj-$(CONFIG_$(PHASE_)BLKMAP) += blkmap.o obj-$(CONFIG_$(PHASE_)BLKMAP) += blkmap_helper.o diff --git a/drivers/block/host-uclass.c b/drivers/block/host-uclass.c index cf42bd1e07a..95b0b0b2ffe 100644 --- a/drivers/block/host-uclass.c +++ b/drivers/block/host-uclass.c @@ -150,6 +150,21 @@ struct udevice *host_find_by_label(const char *label) return NULL; } +int host_set_flags_by_label(const char *label, unsigned int flags) +{ + struct udevice *dev; + struct host_sb_plat *plat; + + dev = host_find_by_label(label); + if (!dev) + return -ENODEV; + + plat = dev_get_plat(dev); + plat->flags = flags; + + return 0; +} + struct udevice *host_get_cur_dev(void) { struct uclass *uc = uclass_find(UCLASS_HOST); diff --git a/drivers/block/sandbox-bootdev.c b/drivers/block/sandbox-bootdev.c new file mode 100644 index 00000000000..15af0c17d1f --- /dev/null +++ b/drivers/block/sandbox-bootdev.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#define LOG_CATEGORY UCLASS_HOST + +#include +#include +#include +#include + +static int sandbox_bootdev_bind(struct udevice *dev) +{ + struct bootdev_uc_plat *ucp = dev_get_uclass_plat(dev); + + ucp->prio = BOOTDEVP_4_SCAN_FAST; + + return 0; +} + +/** + * sandbox_bootdev_hunt() - Hunt host bootdev. + * + * Note, this hunter exists for bootdev testing to simulate a failure + * mode. Do not use as an example of a real hunter. + * + * @info: Hunter details. + * @show: Enable extra printouts. + * + * Returns: 0 if OK, -ve on error (expected by the test) + */ +static int sandbox_bootdev_hunt(struct bootdev_hunter *info, bool show) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + + uclass_id_foreach_dev(UCLASS_HOST, dev, uc) { + struct host_sb_plat *plat = dev_get_plat(dev); + + log_debug("hunting %s\n", plat->label); + + if (plat->flags & HOST_FLAG_BROKEN) { + ret = -ETIME; + log_debug("cannot hunt sandbox device '%s': %d\n", + plat->label, ret); + return ret; + } + } + + return 0; +} + +static const struct bootdev_ops sandbox_bootdev_ops = { +}; + +static const struct udevice_id sandbox_bootdev_ids[] = { + { .compatible = "u-boot,bootdev-sandbox" }, + { } +}; + +U_BOOT_DRIVER(sandbox_bootdev) = { + .name = "sandbox_bootdev", + .id = UCLASS_BOOTDEV, + .ops = &sandbox_bootdev_ops, + .bind = sandbox_bootdev_bind, + .of_match = sandbox_bootdev_ids, +}; + +BOOTDEV_HUNTER(sandbox_bootdev_hunter) = { + .prio = BOOTDEVP_4_SCAN_FAST, + .uclass = UCLASS_HOST, + .hunt = sandbox_bootdev_hunt, + .drv = DM_DRIVER_REF(sandbox_bootdev), +}; diff --git a/include/sandbox_host.h b/include/sandbox_host.h index f7a5fc67230..1330358ef7a 100644 --- a/include/sandbox_host.h +++ b/include/sandbox_host.h @@ -8,17 +8,26 @@ #ifndef __SANDBOX_HOST__ #define __SANDBOX_HOST__ +/** + * Device flags. + */ +enum host_platform_flags { + HOST_FLAG_BROKEN = BIT(0), /** Simulate broken device */ +}; + /** * struct host_sb_plat - platform data for a host device * * @label: Label for this device (allocated) * @filename: Name of file this is attached to, or NULL (allocated) * @fd: File descriptor of file, or 0 for none (file is not open) + * @flags: Device flags (e.g. for unit tests). */ struct host_sb_plat { char *label; char *filename; int fd; + unsigned int flags; }; /** @@ -122,4 +131,13 @@ struct udevice *host_get_cur_dev(void); */ void host_set_cur_dev(struct udevice *dev); +/** + * host_set_flags_by_label() - Set the host device test flags + * + * @label: Label of the attachment, e.g. "test1" + * @flags: Device flags + * Returns: 0 if OK, -ve on error + */ +int host_set_flags_by_label(const char *label, unsigned int flags); + #endif /* __SANDBOX_HOST__ */ diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c index 0820bf10ee0..c2eaf0b2c55 100644 --- a/test/boot/bootdev.c +++ b/test/boot/bootdev.c @@ -384,19 +384,19 @@ static int bootdev_test_hunter(struct unit_test_state *uts) ut_assert_nextline(" 2 mmc mmc_bootdev"); ut_assert_nextline(" 4 nvme nvme_bootdev"); ut_assert_nextline(" 4 qfw qfw_bootdev"); + ut_assert_nextline(" 4 host sandbox_bootdev"); ut_assert_nextline(" 4 scsi scsi_bootdev"); ut_assert_nextline(" 4 spi_flash sf_bootdev"); ut_assert_nextline(" 5 usb usb_bootdev"); ut_assert_nextline(" 4 virtio virtio_bootdev"); - ut_assert_nextline("(total hunters: 9)"); + ut_assert_nextline("(total hunters: 10)"); ut_assert_console_end(); ut_assertok(bootdev_hunt("usb1", false)); ut_assert_skip_to_line("Bus usb@1: 5 USB Device(s) found"); ut_assert_console_end(); - /* USB is 8th in the list, so bit 7 */ - ut_asserteq(BIT(7), std->hunters_used); + ut_asserteq(BIT(USB_HUNTER), std->hunters_used); return 0; } @@ -417,7 +417,7 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts) ut_assert_nextline("Prio Used Uclass Hunter"); ut_assert_nextlinen("----"); ut_assert_nextline(" 6 ethernet eth_bootdev"); - ut_assert_skip_to_line("(total hunters: 9)"); + ut_assert_skip_to_line("(total hunters: 10)"); ut_assert_console_end(); /* Use the MMC hunter and see that it updates */ @@ -425,7 +425,7 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts) ut_assertok(run_command("bootdev hunt -l", 0)); ut_assert_skip_to_line(" 5 ide ide_bootdev"); ut_assert_nextline(" 2 * mmc mmc_bootdev"); - ut_assert_skip_to_line("(total hunters: 9)"); + ut_assert_skip_to_line("(total hunters: 10)"); ut_assert_console_end(); /* Scan all hunters */ @@ -441,6 +441,7 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts) ut_assert_nextline("Hunting with: nvme"); ut_assert_nextline("Hunting with: qfw"); + ut_assert_nextline("Hunting with: host"); ut_assert_nextline("Hunting with: scsi"); ut_assert_nextline("scanning bus for devices..."); ut_assert_skip_to_line("Hunting with: spi_flash"); @@ -458,11 +459,12 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts) ut_assert_nextline(" 2 * mmc mmc_bootdev"); ut_assert_nextline(" 4 * nvme nvme_bootdev"); ut_assert_nextline(" 4 * qfw qfw_bootdev"); + ut_assert_nextline(" 4 * host sandbox_bootdev"); ut_assert_nextline(" 4 * scsi scsi_bootdev"); ut_assert_nextline(" 4 * spi_flash sf_bootdev"); ut_assert_nextline(" 5 * usb usb_bootdev"); ut_assert_nextline(" 4 * virtio virtio_bootdev"); - ut_assert_nextline("(total hunters: 9)"); + ut_assert_nextline("(total hunters: 10)"); ut_assert_console_end(); ut_asserteq(GENMASK(MAX_HUNTER, 0), std->hunters_used); @@ -646,8 +648,7 @@ static int bootdev_test_next_label(struct unit_test_state *uts) ut_asserteq_str("scsi.id0lun0.bootdev", dev->name); ut_asserteq(BOOTFLOW_METHF_SINGLE_UCLASS, mflags); - /* SCSI is 6th in the list, so bit 5 */ - ut_asserteq(BIT(MMC_HUNTER) | BIT(5), std->hunters_used); + ut_asserteq(BIT(MMC_HUNTER) | BIT(SCSI_HUNTER), std->hunters_used); ut_assertok(bootdev_next_label(&iter, &dev, &mflags)); ut_assert_console_end(); @@ -657,7 +658,7 @@ static int bootdev_test_next_label(struct unit_test_state *uts) mflags); /* dhcp: Ethernet is first so bit 0 */ - ut_asserteq(BIT(MMC_HUNTER) | BIT(5) | BIT(0), std->hunters_used); + ut_asserteq(BIT(MMC_HUNTER) | BIT(SCSI_HUNTER) | BIT(0), std->hunters_used); ut_assertok(bootdev_next_label(&iter, &dev, &mflags)); ut_assert_console_end(); @@ -667,7 +668,7 @@ static int bootdev_test_next_label(struct unit_test_state *uts) mflags); /* pxe: Ethernet is first so bit 0 */ - ut_asserteq(BIT(MMC_HUNTER) | BIT(5) | BIT(0), std->hunters_used); + ut_asserteq(BIT(MMC_HUNTER) | BIT(SCSI_HUNTER) | BIT(0), std->hunters_used); mflags = 123; ut_asserteq(-ENODEV, bootdev_next_label(&iter, &dev, &mflags)); @@ -675,7 +676,7 @@ static int bootdev_test_next_label(struct unit_test_state *uts) ut_assert_console_end(); /* no change */ - ut_asserteq(BIT(MMC_HUNTER) | BIT(5) | BIT(0), std->hunters_used); + ut_asserteq(BIT(MMC_HUNTER) | BIT(SCSI_HUNTER) | BIT(0), std->hunters_used); return 0; } diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index 56ee1952357..1cc137c9700 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -19,6 +19,8 @@ #include #ifdef CONFIG_SANDBOX #include +#include +#include #endif #include #include @@ -1532,3 +1534,48 @@ static int bootstd_images(struct unit_test_state *uts) return 0; } BOOTSTD_TEST(bootstd_images, UTF_CONSOLE); + +#if defined(CONFIG_SANDBOX) && defined(CONFIG_BOOTMETH_GLOBAL) +/* + * Check that bootdev scanning does not stop if higher-priority bootdevs + * are failed to be hunted. + */ +static int bootdev_hunt_fallthrough(struct unit_test_state *uts) +{ + struct bootstd_priv *std; + struct udevice *dev; + + ut_assertok(bootstd_get_priv(&std)); + bootstd_test_drop_bootdev_order(uts); + test_set_skip_delays(true); + bootstd_reset_usb(); + console_record_reset_enable(); + + /* + * Create a sandbox block device (BOOTDEVP_4_SCAN_FAST) and mark it as + * broken so that bootdev_hunt_prio() returns an error. + */ + ut_asserteq(0, uclass_id_count(UCLASS_HOST)); + ut_assertok(host_create_device("test", true, DEFAULT_BLKSZ, &dev)); + ut_assertok(host_set_flags_by_label("test", HOST_FLAG_BROKEN)); + ut_asserteq(1, uclass_id_count(UCLASS_HOST)); + + /* + * Scan with hunting. + * The sandbox hunter at priority 4 must fail, but the USB hunter at + * priority 5 must still be reached. + */ + ut_assertok(run_command("bootflow scan -l", 0)); + + ut_assert(!(std->hunters_used & BIT(HOST_HUNTER))); + ut_assert_skip_to_line("Hunting with: host"); + + /* USB was hunted despite the sandbox hunter failure */ + ut_assert(std->hunters_used & BIT(USB_HUNTER)); + ut_assert_skip_to_line("Bus usb@1: 5 USB Device(s) found"); + + return 0; +} +BOOTSTD_TEST(bootdev_hunt_fallthrough, + UTF_DM | UTF_SCAN_FDT | UTF_SF_BOOTDEV | UTF_CONSOLE); +#endif /* CONFIG_SANDBOX */ diff --git a/test/boot/bootstd_common.h b/test/boot/bootstd_common.h index dd769313a84..672917454a3 100644 --- a/test/boot/bootstd_common.h +++ b/test/boot/bootstd_common.h @@ -21,8 +21,11 @@ #define TEST_VERNUM 0x00010002 enum { - MAX_HUNTER = 8, MMC_HUNTER = 2, /* ID of MMC hunter */ + HOST_HUNTER = 5, + SCSI_HUNTER = 6, + USB_HUNTER = 8, + MAX_HUNTER = 9, }; struct unit_test_state; -- cgit v1.3.1 From 8d3963a0971caa4b0b16c1e531cee5eeea20c865 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Wed, 1 Jul 2026 06:21:25 +0000 Subject: ls1028ardb: Move environment variables to .env file Move the bulk of the board environment from CFG_EXTRA_ENV_SETTINGS in ls1028ardb.h to board/nxp/ls1028a/ls1028ardb.env. Because the board directory is shared with ls1028aqds, the file is selected through CONFIG_ENV_SOURCE_FILE rather than the SYS_BOARD default. The distro_bootcmd machinery cannot be expressed in a .env file. The BOOTENV macro expands to environment text with embedded NUL separators, and the board overrides three distro variables (boot_scripts, boot_a_script and scan_dev_for_boot_part) that must follow BOOTENV to take effect. BOOTENV and those three overrides therefore remain in CFG_EXTRA_ENV_SETTINGS, which is concatenated after the .env text, while every other variable moves to the .env file. The resulting default environment is functionally unchanged for both the ls1028ardb_tfa and ls1028ardb_tfa_SECURE_BOOT defconfigs. This was verified with an order aware comparison of the default environment before and after the change. The only difference is that three accidental double spaces in xspi_bootcmd, sd_bootcmd and emmc_bootcmd collapse to single spaces, because the preprocessor normalises whitespace in the now unquoted text, which does not affect command parsing. Signed-off-by: Aristo Chen Signed-off-by: Peng Fan --- board/nxp/ls1028a/ls1028ardb.env | 49 ++++++++++++++ configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028ardb_tfa_defconfig | 1 + include/configs/ls1028ardb.h | 99 ++++++---------------------- 4 files changed, 71 insertions(+), 79 deletions(-) create mode 100644 board/nxp/ls1028a/ls1028ardb.env (limited to 'include') diff --git a/board/nxp/ls1028a/ls1028ardb.env b/board/nxp/ls1028a/ls1028ardb.env new file mode 100644 index 00000000000..dc1cb01e50a --- /dev/null +++ b/board/nxp/ls1028a/ls1028ardb.env @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +board=ls1028ardb +hwconfig=fsl_ddr:bank_intlv=auto +fdtfile=fsl-ls1028a-rdb.dtb +image=Image +extra_bootargs=iommu.passthrough=1 arm-smmu.disable_bypass=0 +othbootargs=video=1920x1080-32@60 cma=640M +ramdisk_addr=0x800000 +ramdisk_size=0x2000000 +bootm_size=0x10000000 +kernel_addr=0x01000000 +scriptaddr=0x80000000 +scripthdraddr=0x80080000 +fdtheader_addr_r=0x80100000 +kernelheader_addr_r=0x80200000 +load_addr=0xa0000000 +kernel_addr_r=0x81000000 +fdt_addr_r=0x90000000 +ramdisk_addr_r=0xa0000000 +kernel_start=0x1000000 +kernelheader_start=0x600000 +kernel_load=0xa0000000 +kernel_size=0x2800000 +kernelheader_size=0x40000 +kernel_addr_sd=0x8000 +kernel_size_sd=0x14000 +kernelhdr_addr_sd=0x3000 +kernelhdr_size_sd=0x20 +console=ttyS0,115200 +console_dbg=earlycon=uart8250,mmio,0x21c0500 +boot_script_hdr=hdr_ls1028ardb_bs.out +xspi_bootcmd=echo Trying load from FlexSPI flash ...;sf probe 0:0 && sf read $load_addr + $kernel_start $kernel_size ; env exists secureboot &&sf read $kernelheader_addr_r + $kernelheader_start $kernelheader_size && esbc_validate ${kernelheader_addr_r}; bootm + $load_addr#$board +xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;sf probe 0:0 && sf read + $load_addr 0x940000 0x30000 && hdp load $load_addr 0x2000 +sd_bootcmd=echo Trying load from SD ...;mmc dev 0;mmcinfo; mmc read $load_addr $kernel_addr_sd + $kernel_size_sd && env exists secureboot && mmc read $kernelheader_addr_r $kernelhdr_addr_sd + $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm $load_addr#$board +sd_hdploadcmd=echo Trying load HDP firmware from SD..;mmc dev 0;mmcinfo;mmc read $load_addr + 0x4a00 0x200 && hdp load $load_addr 0x2000 +emmc_bootcmd=echo Trying load from EMMC ..;mmc dev 1;mmcinfo; mmc read $load_addr + $kernel_addr_sd $kernel_size_sd && env exists secureboot && mmc read $kernelheader_addr_r + $kernelhdr_addr_sd $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm + $load_addr#$board +emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;mmc dev 1;mmcinfo;mmc read $load_addr + 0x4a00 0x200 && hdp load $load_addr 0x2000 diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 6917fe7783b..a8c7c89c9d3 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_ENV_SOURCE_FILE="ls1028ardb" CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index f1c13afbb2e..ca19d6035ee 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -6,6 +6,7 @@ CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_ENV_SOURCE_FILE="ls1028ardb" CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 613abc50567..1811825baeb 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -50,85 +50,26 @@ /* Initial environment variables */ #ifndef SPL_NO_ENV #undef CFG_EXTRA_ENV_SETTINGS -#define CFG_EXTRA_ENV_SETTINGS \ - "board=ls1028ardb\0" \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "fdtfile=fsl-ls1028a-rdb.dtb\0" \ - "image=Image\0" \ - "extra_bootargs=iommu.passthrough=1 arm-smmu.disable_bypass=0\0" \ - "othbootargs=video=1920x1080-32@60 cma=640M\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "bootm_size=0x10000000\0" \ - "kernel_addr=0x01000000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_addr_r=0x81000000\0" \ - "fdt_addr_r=0x90000000\0" \ - "ramdisk_addr_r=0xa0000000\0" \ - "kernel_start=0x1000000\0" \ - "kernelheader_start=0x600000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernelheader_size=0x40000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x3000\0" \ - "kernelhdr_size_sd=0x20\0" \ - "console=ttyS0,115200\0" \ - "console_dbg=earlycon=uart8250,mmio,0x21c0500\0" \ - BOOTENV \ - "boot_scripts=ls1028ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ +#define CFG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "boot_scripts=ls1028ardb_boot.scr\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ "${scripthdraddr} ${prefix}${boot_script_hdr} " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \ - "sf probe 0:0 && sf read $load_addr " \ - "$kernel_start $kernel_size ; env exists secureboot &&" \ - "sf read $kernelheader_addr_r $kernelheader_start " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ - " bootm $load_addr#$board\0" \ - "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \ - "sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \ - "&& hdp load $load_addr 0x2000\0" \ - "sd_bootcmd=echo Trying load from SD ...;" \ - "mmc dev 0;mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" \ - "sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \ - "mmc dev 0;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \ - "&& hdp load $load_addr 0x2000\0" \ - "emmc_bootcmd=echo Trying load from EMMC ..;" \ - "mmc dev 1;mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" \ - "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \ - "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \ - "&& hdp load $load_addr 0x2000\0" + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" #endif #endif /* __LS1028A_RDB_H */ -- cgit v1.3.1