From bddec1b0e60a47e0898d649c0bc68e9aa2bcab8f Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Thu, 23 Jan 2020 17:55:10 +0530 Subject: board: fsl: lx2160a: Add support to reset to eMMC Add support of "qixis_reset emmc" command for lx2160a based platforms Signed-off-by: Meenakshi Aggarwal Reviewed-by: Priyanka Jain --- include/configs/lx2160aqds.h | 2 ++ include/configs/lx2160ardb.h | 2 ++ 2 files changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index f25cab18ae5..1eb63d826f9 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -22,7 +22,9 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SD +#define QIXIS_LBMAP_EMMC #define QIXIS_RCW_SRC_SD 0x08 +#define QIXIS_RCW_SRC_EMMC 0x09 #define NON_EXTENDED_DUTCFG #define QIXIS_SDID_MASK 0x07 #define QIXIS_ESDHC_NO_ADAPTER 0x7 diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index de385f82c89..82d49e53abd 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -22,7 +22,9 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SD +#define QIXIS_LBMAP_EMMC #define QIXIS_RCW_SRC_SD 0x08 +#define QIXIS_RCW_SRC_EMMC 0x09 #define NON_EXTENDED_DUTCFG /* VID */ -- cgit v1.3.1 From a0affb367ad638e1e6f51ed3678d3daad5724a40 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Tue, 31 Dec 2019 15:33:41 +0800 Subject: dm: arm64: ls1012a: add i2c DM support This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1012A Signed-off-by: Biwen Li Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 +- arch/arm/include/asm/gpio.h | 1 + board/freescale/ls1012aqds/ls1012aqds.c | 20 +++- board/freescale/ls1012ardb/eth.c | 35 ++++++ board/freescale/ls1012ardb/ls1012ardb.c | 148 +++++++++++++++++++++---- configs/ls1012a2g5rdb_qspi_defconfig | 3 + configs/ls1012a2g5rdb_tfa_defconfig | 3 + configs/ls1012afrdm_qspi_defconfig | 3 + configs/ls1012afrdm_tfa_defconfig | 3 + configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 3 + configs/ls1012afrwy_qspi_defconfig | 3 + configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 3 + configs/ls1012afrwy_tfa_defconfig | 3 + configs/ls1012aqds_qspi_defconfig | 3 + configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 3 + configs/ls1012aqds_tfa_defconfig | 3 + configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 3 + configs/ls1012ardb_qspi_defconfig | 3 + configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 3 + configs/ls1012ardb_tfa_defconfig | 3 + include/configs/ls1012a_common.h | 5 + 21 files changed, 230 insertions(+), 28 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index e2b92f0eabb..275c66d9929 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -16,8 +16,8 @@ config ARCH_LS1012A select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F select SYS_I2C_MXC - select SYS_I2C_MXC_I2C1 - select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C1 if !DM_I2C + select SYS_I2C_MXC_I2C2 if !DM_I2C imply PANIC_HANG config ARCH_LS1028A diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index acb7ea9a3eb..39ffc18e29e 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -4,6 +4,7 @@ !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \ !defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \ !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \ + !defined(CONFIG_ARCH_LS1012A) && \ !defined(CONFIG_ARCH_U8500) #include #endif diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 86c72ee357e..30bf1047d53 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -107,10 +107,26 @@ int board_early_init_f(void) int misc_init_r(void) { u8 mux_sdhc_cd = 0x80; - - i2c_set_bus_num(0); + int bus_num = 0; + +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1); +#else + i2c_set_bus_num(bus_num); i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); +#endif + return 0; } #endif diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c index 3cc0a65cb91..5edcfcf1cea 100644 --- a/board/freescale/ls1012ardb/eth.c +++ b/board/freescale/ls1012ardb/eth.c @@ -28,12 +28,47 @@ static inline void ls1012ardb_reset_phy(void) { #ifdef CONFIG_TARGET_LS1012ARDB /* Through reset IO expander reset both RGMII and SGMII PHYs */ +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + /* + * The I2C IO-expander PCAL9555A is mouted on I2C1 bus(bus number is 0). + */ + ret = i2c_get_chip_for_busnum(0, I2C_MUX_IO2_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + 0); + return; + } + /* Config port 0 + * - config pin IOXP_RST_ETH1_B and IOXP_RST_ETH2_B + * are enabled as an output. + */ + dm_i2c_reg_write(dev, 6, __PHY_MASK); + + /* + * Set port 0 output a value to reset ETH2 interface + * - pin IOXP_RST_ETH2_B output 0b0 + */ + dm_i2c_reg_write(dev, 2, __PHY_ETH2_MASK); + mdelay(10); + dm_i2c_reg_write(dev, 2, __PHY_ETH1_MASK); + /* + * Set port 0 output a value to reset ETH1 interface + * - pin IOXP_RST_ETH1_B output 0b0 + */ + mdelay(10); + dm_i2c_reg_write(dev, 2, 0xFF); +#else i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK); i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK); mdelay(10); i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK); mdelay(10); i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF); +#endif mdelay(50); #endif } diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 0f665c7bc68..ab83ef11a09 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -34,13 +34,27 @@ int checkboard(void) { #ifdef CONFIG_TARGET_LS1012ARDB u8 in1; + int ret, bus_num = 0; puts("Board: LS1012ARDB "); /* Initialize i2c early for Serial flash bank information */ - i2c_set_bus_num(0); +#if defined(CONFIG_DM_I2C) + struct udevice *dev; - if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1) < 0) { + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1); +#else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); + ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1); +#endif + if (ret < 0) { printf("Error reading i2c boot information!\n"); return 0; /* Don't want to hang() on this error */ } @@ -175,11 +189,25 @@ int esdhc_status_fixup(void *blob, const char *compat) bool sdhc2_en = false; u8 mux_sdhc2; u8 io = 0; + int ret, bus_num = 0; - i2c_set_bus_num(0); +#if defined(CONFIG_DM_I2C) + struct udevice *dev; + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1); +#else + i2c_set_bus_num(bus_num); /* IO1[7:3] is the field of board revision info. */ - if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1) < 0) { + ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1); +#endif + if (ret < 0) { printf("Error reading i2c boot information!\n"); return 0; } @@ -202,7 +230,12 @@ int esdhc_status_fixup(void *blob, const char *compat) * 10 - eMMC Memory * 11 - SPI */ - if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1) < 0) { +#if defined(CONFIG_DM_I2C) + ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1); +#else + ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1); +#endif + if (ret < 0) { printf("Error reading i2c boot information!\n"); return 0; } @@ -233,16 +266,63 @@ int ft_board_setup(void *blob, bd_t *bd) static int switch_to_bank1(void) { - u8 data; - int ret; + u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03; + int ret, bus_num = 0; - i2c_set_bus_num(0); +#if defined(CONFIG_DM_I2C) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, chip_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + /* + * -------------------------------------------------------------------- + * |bus |I2C address| Device | Notes | + * -------------------------------------------------------------------- + * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General | + * | |0x26 | RESET, and INT/ | Purpose parallel Input/Output| + * | | | KW41GPIO) - NXP | (GPIO) expansion for the | + * | | | PCAL9555AHF | I2C bus | + * ----- -------------------------------------------------------------- + * - mount three IO expander(PCAL9555AHF) on I2C1 + * + * PCAL9555A device address + * slave address + * -------------------------------------- + * | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W | + * -------------------------------------- + * | fixed | hardware selectable| + * + * Output port 1(Pinter register bits = 0x03) + * + * P1_[7~0] = 0xf4 + * P1_0 <---> CFG_MUX_QSPI_S0 + * P1_1 <---> CFG_MUX_QSPI_S1 + * CFG_MUX_QSPI_S[1:0] = 0b00 + * + * QSPI chip-select demultiplexer select + * --------------------------------------------------------------------- + * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0| Values + * --------------------------------------------------------------------- + * 0 | 0 |CS routed to SPI memory bank1(default) + * --------------------------------------------------------------------- + * 0 | 1 |CS routed to SPI memory bank2 + * --------------------------------------------------------------------- + * + */ + ret = dm_i2c_write(dev, offset_addr, &data, 1); +#else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); + ret = i2c_write(chip_addr, offset_addr, 1, &data, 1); +#endif - data = 0xf4; - ret = i2c_write(0x24, 0x3, 1, &data, 1); if (ret) { printf("i2c write error to chip : %u, addr : %u, data : %u\n", - 0x24, 0x3, data); + chip_addr, offset_addr, data); } return ret; @@ -250,25 +330,45 @@ static int switch_to_bank1(void) static int switch_to_bank2(void) { - u8 data; - int ret; + u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3}; + u8 chip_addr = 0x24; + int ret, i, bus_num = 0; - i2c_set_bus_num(0); +#if defined(CONFIG_DM_I2C) + struct udevice *dev; - data = 0xfc; - ret = i2c_write(0x24, 0x7, 1, &data, 1); + ret = i2c_get_chip_for_busnum(bus_num, chip_addr, + 1, &dev); if (ret) { - printf("i2c write error to chip : %u, addr : %u, data : %u\n", - 0x24, 0x7, data); - goto err; + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; } +#else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); +#endif - data = 0xf5; - ret = i2c_write(0x24, 0x3, 1, &data, 1); - if (ret) { - printf("i2c write error to chip : %u, addr : %u, data : %u\n", - 0x24, 0x3, data); + /* + * 1th step: config port 1 + * - the port 1 pin is enabled as an output + * 2th step: output port 1 + * - P1_[7:0] output 0xf5, + * then CFG_MUX_QSPI_S[1:0] equal to 0b01, + * CS routed to SPI memory bank2 + */ + for (i = 0; i < sizeof(data); i++) { +#if defined(CONFIG_DM_I2C) + ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1); +#else /* Non DM I2C support - will be removed */ + ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1); +#endif + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + chip_addr, offset_addr[i], data[i]); + goto err; + } } + err: return ret; } diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index be8b2e51eff..dabe2b52d55 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -52,3 +52,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index 0a035a83faa..2a5713b8521 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -52,3 +52,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 7258d47dfca..e5196defac2 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -52,3 +52,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index 85f87ba238f..4b55b0c485f 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -52,3 +52,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index a3c6fe7d8f6..14fdef4ad45 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -54,3 +54,6 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index eb732a1964b..6ca5599dfa5 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -54,3 +54,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 92d85994a35..79e4de9fc00 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -55,3 +55,6 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_CMD_SETEXPR=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index ca732c4b483..5f1469e6716 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -60,3 +60,6 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 1d6bcc51c44..3708f42e2fb 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -76,3 +76,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index f525544ccf2..ac9e92036c8 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -68,3 +68,6 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 656de21adbf..b1e3e51754d 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -76,3 +76,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index a7d1f959fb4..c59d74408db 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -58,3 +58,6 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index f3fede7b621..8ae63ef73dc 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -60,3 +60,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 2ecd5076256..19a2e5bfbee 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -58,3 +58,6 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index cb457abc648..b47a47d56b8 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -61,3 +61,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_DM_RTC=y diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 2579e2fb37e..e9baa2a8b66 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -66,7 +66,12 @@ CONFIG_SYS_SCSI_MAX_LUN) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -- cgit v1.3.1 From 9ebde8849a37beff5eccb462a991e05b07f8a360 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Tue, 31 Dec 2019 15:33:44 +0800 Subject: dm: arm: ls1021a: add i2c DM support This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1021A Signed-off-by: Biwen Li Signed-off-by: Priyanka Jain --- board/freescale/common/dcu_sii9022a.c | 96 ++++++++++++++++++++++ board/freescale/common/diu_ch7301.c | 81 ++++++++++++++++++ board/freescale/ls1021aqds/dcu.c | 46 ++++++++++- board/freescale/ls1021aqds/ls1021aqds.c | 21 ++++- board/freescale/ls1021atwr/ls1021atwr.c | 27 +++++- configs/ls1021aiot_qspi_defconfig | 2 + configs/ls1021aiot_sdcard_defconfig | 2 + configs/ls1021aqds_ddr4_nor_defconfig | 2 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 2 + configs/ls1021aqds_nand_defconfig | 2 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 + configs/ls1021aqds_nor_defconfig | 2 + configs/ls1021aqds_nor_lpuart_defconfig | 2 + configs/ls1021aqds_qspi_defconfig | 2 + configs/ls1021aqds_sdcard_ifc_defconfig | 2 + configs/ls1021aqds_sdcard_qspi_defconfig | 2 + configs/ls1021atsn_qspi_defconfig | 2 + configs/ls1021atsn_sdcard_defconfig | 2 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 + configs/ls1021atwr_nor_defconfig | 2 + configs/ls1021atwr_nor_lpuart_defconfig | 2 + configs/ls1021atwr_qspi_defconfig | 2 + .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 + configs/ls1021atwr_sdcard_ifc_defconfig | 2 + configs/ls1021atwr_sdcard_qspi_defconfig | 2 + include/configs/ls1021aiot.h | 7 ++ include/configs/ls1021aqds.h | 6 ++ include/configs/ls1021atsn.h | 7 +- include/configs/ls1021atwr.h | 7 ++ 29 files changed, 330 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/board/freescale/common/dcu_sii9022a.c b/board/freescale/common/dcu_sii9022a.c index 3bf71abf553..832ae258f14 100644 --- a/board/freescale/common/dcu_sii9022a.c +++ b/board/freescale/common/dcu_sii9022a.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include @@ -63,7 +64,101 @@ int dcu_set_dvi_encoder(struct fb_videomode *videomode) u8 temp; u16 temp1, temp2; u32 temp3; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM, + CONFIG_SYS_I2C_DVI_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + CONFIG_SYS_I2C_DVI_BUS_NUM); + return ret; + } + /* Enable TPI transmitter mode */ + temp = TPI_TRANS_MODE_ENABLE; + dm_i2c_write(dev, TPI_TRANS_MODE_REG, &temp, 1); + + /* Enter into D0 state, full operation */ + dm_i2c_read(dev, TPI_PWR_STAT_REG, &temp, 1); + temp &= ~TPI_PWR_STAT_MASK; + temp |= TPI_PWR_STAT_D0; + dm_i2c_write(dev, TPI_PWR_STAT_REG, &temp, 1); + + /* Enable source termination */ + temp = TPI_SET_PAGE_SII9022A; + dm_i2c_write(dev, TPI_SET_PAGE_REG, &temp, 1); + temp = TPI_SET_OFFSET_SII9022A; + dm_i2c_write(dev, TPI_SET_OFFSET_REG, &temp, 1); + + dm_i2c_read(dev, TPI_RW_ACCESS_REG, &temp, 1); + temp |= TPI_RW_EN_SRC_TERMIN; + dm_i2c_write(dev, TPI_RW_ACCESS_REG, &temp, 1); + + /* Set TPI system control */ + temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE; + dm_i2c_write(dev, TPI_SYS_CTRL_REG, &temp, 1); + + /* Set pixel clock */ + temp1 = PICOS2KHZ(videomode->pixclock) / 10; + temp = (u8)(temp1 & 0xFF); + dm_i2c_write(dev, PIXEL_CLK_LSB_REG, &temp, 1); + temp = (u8)(temp1 >> 8); + dm_i2c_write(dev, PIXEL_CLK_MSB_REG, &temp, 1); + + /* Set total pixels per line */ + temp1 = videomode->hsync_len + videomode->left_margin + + videomode->xres + videomode->right_margin; + temp = (u8)(temp1 & 0xFF); + dm_i2c_write(dev, TOTAL_PIXELS_LSB_REG, &temp, 1); + temp = (u8)(temp1 >> 8); + dm_i2c_write(dev, TOTAL_PIXELS_MSB_REG, &temp, 1); + + /* Set total lines */ + temp2 = videomode->vsync_len + videomode->upper_margin + + videomode->yres + videomode->lower_margin; + temp = (u8)(temp2 & 0xFF); + dm_i2c_write(dev, TOTAL_LINES_LSB_REG, &temp, 1); + temp = (u8)(temp2 >> 8); + dm_i2c_write(dev, TOTAL_LINES_MSB_REG, &temp, 1); + + /* Set vertical frequency in Hz */ + temp3 = temp1 * temp2; + temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3; + temp1 = (u16)temp3 * 100; + temp = (u8)(temp1 & 0xFF); + dm_i2c_write(dev, VERT_FREQ_LSB_REG, &temp, 1); + temp = (u8)(temp1 >> 8); + dm_i2c_write(dev, VERT_FREQ_MSB_REG, &temp, 1); + + /* Set TPI input bus and pixel repetition data */ + temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE | + TPI_INBUS_RISING_EDGE; + dm_i2c_write(dev, TPI_INBUS_FMT_REG, &temp, 1); + + /* Set TPI AVI Input format data */ + temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO | + TPI_INPUT_CLR_RGB; + dm_i2c_write(dev, TPI_INPUT_FMT_REG, &temp, 1); + + /* Set TPI AVI Output format data */ + temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO | + TPI_OUTPUT_CLR_HDMI_RGB; + dm_i2c_write(dev, TPI_OUTPUT_FMT_REG, &temp, 1); + + /* Set TPI audio configuration write data */ + temp = TPI_AUDIO_PASS_BASIC; + dm_i2c_write(dev, TPI_AUDIO_HANDING_REG, &temp, 1); + + temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL | + TPI_AUDIO_TYPE_PCM; + dm_i2c_write(dev, TPI_AUDIO_INTF_REG, &temp, 1); + + temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K; + dm_i2c_write(dev, TPI_AUDIO_FREQ_REG, &temp, 1); +#else i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM); /* Enable TPI transmitter mode */ @@ -147,6 +242,7 @@ int dcu_set_dvi_encoder(struct fb_videomode *videomode) temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K; i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_FREQ_REG, 1, &temp, 1); +#endif return 0; } diff --git a/board/freescale/common/diu_ch7301.c b/board/freescale/common/diu_ch7301.c index 435b4a3f1ac..7f11123e6f3 100644 --- a/board/freescale/common/diu_ch7301.c +++ b/board/freescale/common/diu_ch7301.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP * Authors: Priyanka Jain * Wang Dongsheng * @@ -51,6 +52,85 @@ int diu_set_dvi_encoder(unsigned int pixclock) u8 temp; temp = I2C_DVI_TEST_PATTERN_VAL; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM, + CONFIG_SYS_I2C_DVI_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + CONFIG_SYS_I2C_DVI_BUS_NUM); + return ret; + } + ret = dm_i2c_write(dev, I2C_DVI_TEST_PATTERN_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select proper dvi test pattern\n"); + return ret; + } + temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; + ret = dm_i2c_write(dev, I2C_DVI_INPUT_DATA_FORMAT_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi input data format\n"); + return ret; + } + + /* Set Sync polarity register */ + temp = I2C_DVI_SYNC_POLARITY_VAL; + ret = dm_i2c_write(dev, I2C_DVI_SYNC_POLARITY_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi syc polarity\n"); + return ret; + } + + /* Set PLL registers based on pixel clock rate*/ + if (pixclock > 65000000) { + temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; + ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; + ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; + ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } else { + temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; + ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; + ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; + ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } + + temp = I2C_DVI_POWER_MGMT_VAL; + ret = dm_i2c_write(dev, I2C_DVI_POWER_MGMT_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi power mgmt\n"); + return ret; + } +#else ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1, &temp, 1); if (ret) { @@ -128,6 +208,7 @@ int diu_set_dvi_encoder(unsigned int pixclock) puts("I2C: failed to select dvi power mgmt\n"); return ret; } +#endif udelay(500); diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c index c4eac5e3025..b648a7872bc 100644 --- a/board/freescale/ls1021aqds/dcu.c +++ b/board/freescale/ls1021aqds/dcu.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP * * FSL DCU Framebuffer driver */ @@ -15,11 +16,23 @@ DECLARE_GLOBAL_DATA_PTR; -static int select_i2c_ch_pca9547(u8 ch) +static int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -51,6 +64,28 @@ int platform_dcu_init(struct fb_info *fbinfo, u8 ch; /* Mux I2C3+I2C4 as HSYNC+VSYNC */ +#ifdef CONFIG_DM_I2C + struct udevice *dev; + + /* QIXIS device mount on I2C1 bus*/ + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_QIXIS_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + 0); + return ret; + } + ret = dm_i2c_read(dev, QIXIS_DCU_BRDCFG5, &ch, 1); + if (ret) { + printf("Error: failed to read I2C @%02x\n", + CONFIG_SYS_I2C_QIXIS_ADDR); + return ret; + } + ch &= 0x1F; + ch |= 0xA0; + ret = dm_i2c_write(dev, QIXIS_DCU_BRDCFG5, &ch, 1); + +#else ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5, 1, &ch, 1); if (ret) { @@ -62,6 +97,7 @@ int platform_dcu_init(struct fb_info *fbinfo, ch |= 0xA0; ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5, 1, &ch, 1); +#endif if (ret) { printf("Error: failed to write I2C @%02x\n", CONFIG_SYS_I2C_QIXIS_ADDR); @@ -76,10 +112,14 @@ int platform_dcu_init(struct fb_info *fbinfo, pixval = 1000000000 / dcu_fb_videomode->pixclock; pixval *= 1000; +#ifndef CONFIG_DM_I2C i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM); - select_i2c_ch_pca9547(I2C_MUX_CH_CH7301); +#endif + select_i2c_ch_pca9547(I2C_MUX_CH_CH7301, + CONFIG_SYS_I2C_DVI_BUS_NUM); diu_set_dvi_encoder(pixval); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, + CONFIG_SYS_I2C_DVI_BUS_NUM); } else { return 0; } diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index b7f8f1d5786..1ae822e5107 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include @@ -139,11 +140,23 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -158,8 +171,10 @@ int dram_init(void) * When resuming from deep sleep, the I2C channel may not be * in the default channel. So, switch to the default channel * before accessing DDR SPD. + * + * PCA9547(0x77) mount on I2C1 bus */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); return fsl_initdram(); } @@ -408,7 +423,7 @@ int board_init(void) erratum_a009942_check_cpo(); #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 497dce5f0f3..d1ff7b8ba6f 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include @@ -447,14 +448,37 @@ void board_init_f(ulong dummy) /* program the regulator (MC34VR500) to support deep sleep */ void ls1twr_program_regulator(void) { - unsigned int i2c_bus; u8 i2c_device_id; #define LS1TWR_I2C_BUS_MC34VR500 1 #define MC34VR500_ADDR 0x8 #define MC34VR500_DEVICEID 0x4 #define MC34VR500_DEVICEID_MASK 0x0f +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(LS1TWR_I2C_BUS_MC34VR500, MC34VR500_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + LS1TWR_I2C_BUS_MC34VR500); + return; + } + i2c_device_id = dm_i2c_reg_read(dev, 0x0) & + MC34VR500_DEVICEID_MASK; + if (i2c_device_id != MC34VR500_DEVICEID) { + printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n"); + return; + } + dm_i2c_reg_write(dev, 0x31, 0x4); + dm_i2c_reg_write(dev, 0x4d, 0x4); + dm_i2c_reg_write(dev, 0x6d, 0x38); + dm_i2c_reg_write(dev, 0x6f, 0x37); + dm_i2c_reg_write(dev, 0x71, 0x30); +#else + unsigned int i2c_bus; i2c_bus = i2c_get_bus_num(); i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500); i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) & @@ -471,6 +495,7 @@ void ls1twr_program_regulator(void) i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30); i2c_set_bus_num(i2c_bus); +#endif } #endif diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index c3376e106c6..8a3b79693b7 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -45,3 +45,5 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index a7a340076f1..684ae4e75f3 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -51,3 +51,5 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 70f7053ed08..fdfec314e9f 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -67,3 +67,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index eaa26ceee97..c0d9395f494 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -67,3 +67,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index c7c701de9eb..0a9438039b7 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -82,3 +82,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 3f990355535..6b12a4e277f 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -66,3 +66,5 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 6fe62a713de..9c35ba954f8 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -68,3 +68,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index ad222eb9ef7..39b82dd022e 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -68,3 +68,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index e643242b14c..ac5133896d7 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -69,3 +69,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 2c28b9efbac..17b6e6418c6 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -81,3 +81,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index d8065e72422..703eeff05dc 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -81,3 +81,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index c30e89d959a..543f96580bd 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -57,3 +57,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 3d3d743c87a..6c73a9f4eec 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -68,3 +68,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index dbd9d0e070a..2925f37a752 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -60,3 +60,5 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 7fcd4de2d09..cbcc491eb05 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -62,3 +62,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 0303d49045a..0b364dc85d1 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -63,3 +63,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 50b7eedcc2b..077ccef5f10 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -67,3 +67,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index c909f40bd13..01c541399ea 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -74,3 +74,5 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 97e6a4747f4..abc5d873fff 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -75,3 +75,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 3ad24eae2f7..7cc76aa3c61 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -78,3 +78,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 0b2d331b9b9..1d218aa703d 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #ifndef __CONFIG_H @@ -97,7 +98,13 @@ * I2C */ #define CONFIG_CMD_I2C + +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 8427be5adc1..8bac2d25612 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #ifndef __CONFIG_H @@ -331,7 +332,12 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index bdb4273cf5c..984df6249f9 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 - * Copyright 2016-2018 NXP Semiconductors + * Copyright 2016-2019 NXP Semiconductors * Copyright 2019 Vladimir Oltean */ @@ -107,7 +107,12 @@ #define CONFIG_BAUDRATE 115200 /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 1919d1e14f9..bec55a78af3 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #ifndef __CONFIG_H @@ -209,7 +210,12 @@ /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ @@ -446,6 +452,7 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#undef CONFIG_DM_I2C #else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif -- cgit v1.3.1 From feb8fa2ef0a5ff6627baac749a72dfaa15e37714 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 21 Jan 2020 07:33:01 +0000 Subject: configs: ls1021a: Reserve low memory for CMA The default reserved memory for CMA is high memory. If LPAE is enabled, highmem pages are non-remapped and can not be used with dma_alloc_coherent. This patch will reserve low memory for CMA and fix the issue on LS1021A. Signed-off-by: Peng Ma Signed-off-by: Shengzhou Liu Signed-off-by: Alison Wang Reviewed-by: Priyanka Jain --- include/configs/ls1021atwr.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index bec55a78af3..8e2784b14bf 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -313,6 +313,8 @@ "kernel_size=0x2800000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ + "$othbootargs\0" \ + "othbootargs=cma=64M@0x0-0xb0000000\0" \ BOOTENV \ "boot_scripts=ls1021atwr_boot.scr\0" \ "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ @@ -373,6 +375,8 @@ "kernel_size_sd=0x14000\0" \ "kernelhdr_addr_sd=0x4000\0" \ "kernelhdr_size_sd=0x10\0" \ + "$othbootargs\0" \ + "othbootargs=cma=64M@0x0-0xb0000000\0" \ BOOTENV \ "boot_scripts=ls1021atwr_boot.scr\0" \ "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ -- cgit v1.3.1 From e735ad3c43dcc6d2317c256ff101f9530d1e51da Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Wed, 22 Jan 2020 10:29:46 +0000 Subject: armv8: ls1046a: Updates secure boot headers offset Updates the secure boot headers offsets of Kernel and other firmware images for SD and QSPI boot sources used by esbc_validate command. Signed-off-by: Priyanka Singh Reviewed-by: Priyanka Jain --- include/configs/ls1046a_common.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 6543cfd868c..3944f877942 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ #ifndef __LS1046A_COMMON_H @@ -230,13 +230,13 @@ "fdt_addr_r=0x90000000\0" \ "ramdisk_addr_r=0xa0000000\0" \ "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ + "kernelheader_start=0x600000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernelheader_size=0x40000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ CONFIG_MTDPARTS_DEFAULT "\0" \ -- cgit v1.3.1 From 3e90cfee9d488c500838542f2fe6de96e7160e6b Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Wed, 22 Jan 2020 10:29:52 +0000 Subject: armv8: ls1012ardb: Updates secure boot headers offset Updates the secure boot headers offsets of Kernel and other firmware images used by esbc_validate command. Signed-off-by: Priyanka Singh Reviewed-by: Priyanka Jain --- include/configs/ls1012ardb.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index b419c46829e..0738b243c43 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2020 NXP * Copyright 2016 Freescale Semiconductor, Inc. */ @@ -64,7 +65,7 @@ "initrd_high=0xffffffffffffffff\0" \ "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ - "kernelheader_addr=0x800000\0" \ + "kernelheader_addr=0x600000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ -- cgit v1.3.1 From 20858a2be03b2a1d3f38cf50ad8c305f27528b67 Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Wed, 22 Jan 2020 10:31:22 +0000 Subject: armv8: lx2160a: Updates secure boot headers offset Updates the secure boot headers offsets of Kernel and other firmware images for SD and XSPI boot sources used by esbc_validate command. Signed-off-by: Priyanka Singh Reviewed-by: Priyanka Jain --- include/configs/lx2160a_common.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 02cccff0c82..373daebfbc4 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -189,18 +189,18 @@ unsigned long get_board_ddr_clk(void); /* Initial environment variables */ #define XSPI_MC_INIT_CMD \ "env exists secureboot && " \ - "esbc_validate 0x20700000 && " \ - "esbc_validate 0x20740000 ;" \ + "esbc_validate 0x20640000 && " \ + "esbc_validate 0x20680000 ;" \ "fsl_mc start mc 0x20a00000 0x20e00000\0" #define SD_MC_INIT_CMD \ "mmc read 0x80a00000 0x5000 0x1200;" \ "mmc read 0x80e00000 0x7000 0x800;" \ "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x20 && " \ - "mmc read 0x80740000 0x3A00 0x20 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80a00000 0x80e00000\0" #define EXTRA_ENV_SETTINGS \ @@ -211,7 +211,7 @@ unsigned long get_board_ddr_clk(void); "initrd_high=0xffffffffffffffff\0" \ "fdt_addr=0x64f00000\0" \ "kernel_start=0x1000000\0" \ - "kernelheader_start=0x7C0000\0" \ + "kernelheader_start=0x600000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ @@ -222,7 +222,7 @@ unsigned long get_board_ddr_clk(void); "load_addr=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernel_addr_sd=0x8000\0" \ - "kernelhdr_addr_sd=0x3E00\0" \ + "kernelhdr_addr_sd=0x3000\0" \ "kernel_size_sd=0x1d000\0" \ "kernelhdr_size_sd=0x20\0" \ "console=ttyAMA0,38400n8\0" \ @@ -250,7 +250,7 @@ unsigned long get_board_ddr_clk(void); #define XSPI_NOR_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x20780000; " \ + "&& esbc_validate 0x206C0000; " \ "env exists mcinitcmd && " \ "fsl_mc lazyapply dpl 0x20d00000; " \ "run distro_bootcmd;run xspi_bootcmd; " \ @@ -260,8 +260,8 @@ unsigned long get_board_ddr_clk(void); "env exists mcinitcmd && mmcinfo; " \ "mmc read 0x80d00000 0x6800 0x800; " \ "env exists mcinitcmd && env exists secureboot " \ - " && mmc read 0x80780000 0x3C00 0x20 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + " && mmc read 0x806C0000 0x3600 0x20 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80d00000;" \ "run distro_bootcmd;run sd_bootcmd;" \ "env exists secureboot && esbc_halt;" -- cgit v1.3.1 From 4238e37333da15239324bf119708f16ec5736773 Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Wed, 22 Jan 2020 10:32:34 +0000 Subject: armv8: ls1088a: Updates secure boot headers offset Updates the secure boot headers offsets of Kernel and other firmware images for SD and QSPI boot sources used by esbc_validate command. Signed-off-by: Priyanka Singh Signed-off-by: Priyanka Jain --- include/configs/ls1088aqds.h | 6 ++--- include/configs/ls1088ardb.h | 60 ++++++++++++++++++++++---------------------- 2 files changed, 33 insertions(+), 33 deletions(-) (limited to 'include') diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index a5125c8f37f..361c72fc8c9 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2020 NXP */ #ifndef __LS1088A_QDS_H @@ -407,9 +407,9 @@ unsigned long get_board_ddr_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ - "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \ + "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \ "sf read 0xa0e00000 0xe00000 0x100000;" \ - "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \ + "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \ "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ "mcmemsize=0x70000000 \0" #else /* if !(CONFIG_NXP_ESBC) */ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index d02ad083e86..b48efcc119f 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2020 NXP */ #ifndef __LS1088A_RDB_H @@ -296,19 +296,19 @@ "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ "sf read 0x80100000 0xE00000 0x100000;" \ "env exists secureboot && " \ - "sf read 0x80700000 0x700000 0x40000 && " \ - "sf read 0x80740000 0x740000 0x40000 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ + "sf read 0x80640000 0x640000 0x40000 && " \ + "sf read 0x80680000 0x680000 0x40000 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80000000 0x80100000\0" #define SD_MC_INIT_CMD \ "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ "mmc read 0x80100000 0x7000 0x800;" \ "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x20 && " \ - "mmc read 0x80740000 0x3A00 0x20 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80000000 0x80100000\0" #else #if defined(CONFIG_QSPI_BOOT) @@ -316,10 +316,10 @@ "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ "sf read 0x80100000 0xE00000 0x100000;" \ "env exists secureboot && " \ - "sf read 0x80700000 0x700000 0x40000 && " \ - "sf read 0x80740000 0x740000 0x40000 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ + "sf read 0x80640000 0x640000 0x40000 && " \ + "sf read 0x80680000 0x680000 0x40000 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80000000 0x80100000\0" \ "mcmemsize=0x70000000\0" #elif defined(CONFIG_SD_BOOT) @@ -327,10 +327,10 @@ "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ "mmc read 0x80100000 0x7000 0x800;" \ "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x20 && " \ - "mmc read 0x80740000 0x3A00 0x20 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80000000 0x80100000\0" \ "mcmemsize=0x70000000\0" #endif @@ -348,13 +348,13 @@ "fdt_addr=0x64f00000\0" \ "kernel_addr=0x1000000\0" \ "kernel_addr_sd=0x8000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ "kernel_start=0x580100000\0" \ - "kernelheader_start=0x580800000\0" \ + "kernelheader_start=0x580600000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr=0x800000\0" \ + "kernelheader_addr=0x600000\0" \ "kernelheader_addr_r=0x80200000\0" \ "kernel_addr_r=0x81000000\0" \ "kernelheader_size=0x40000\0" \ @@ -417,13 +417,13 @@ "fdt_addr=0x64f00000\0" \ "kernel_addr=0x1000000\0" \ "kernel_addr_sd=0x8000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ "kernel_start=0x580100000\0" \ "kernelheader_start=0x580800000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr=0x800000\0" \ + "kernelheader_addr=0x600000\0" \ "kernelheader_addr_r=0x80200000\0" \ "kernel_addr_r=0x81000000\0" \ "kernelheader_size=0x40000\0" \ @@ -480,8 +480,8 @@ #define QSPI_NOR_BOOTCOMMAND \ "sf read 0x80001000 0xd00000 0x100000;" \ "env exists mcinitcmd && env exists secureboot " \ - " && sf read 0x80780000 0x780000 0x100000 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + " && sf read 0x806C0000 0x6C0000 0x100000 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80001000;" \ "run distro_bootcmd;run qspi_bootcmd;" \ "env exists secureboot && esbc_halt;" @@ -489,8 +489,8 @@ "env exists mcinitcmd && mmcinfo; " \ "mmc read 0x80001000 0x6800 0x800; " \ "env exists mcinitcmd && env exists secureboot " \ - " && mmc read 0x80780000 0x3C00 0x20 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + " && mmc read 0x806C0000 0x3600 0x20 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80001000;" \ "run distro_bootcmd;run sd_bootcmd;" \ "env exists secureboot && esbc_halt;" @@ -500,8 +500,8 @@ #define CONFIG_BOOTCOMMAND \ "sf read 0x80001000 0xd00000 0x100000;" \ "env exists mcinitcmd && env exists secureboot " \ - " && sf read 0x80780000 0x780000 0x100000 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + " && sf read 0x806C0000 0x6C0000 0x100000 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80001000;" \ "run distro_bootcmd;run qspi_bootcmd;" \ "env exists secureboot && esbc_halt;" @@ -512,8 +512,8 @@ "env exists mcinitcmd && mmcinfo; " \ "mmc read 0x80001000 0x6800 0x800; " \ "env exists mcinitcmd && env exists secureboot " \ - " && mmc read 0x80780000 0x3C00 0x20 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + " && mmc read 0x806C0000 0x3600 0x20 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80001000;" \ "run distro_bootcmd;run sd_bootcmd;" \ "env exists secureboot && esbc_halt;" -- cgit v1.3.1 From 8526a58aa5c89ac36578d8e5f2e18ebdd11622c6 Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Wed, 22 Jan 2020 10:32:38 +0000 Subject: armv8: ls2088a: Updates secure boot headers offset Updates the secure boot headers offsets of Kernel and other firmware images for SD and NOR boot sources used by esbc_validate command. Signed-off-by: Priyanka Singh Reviewed-by: Priyanka Jain --- include/configs/ls2080aqds.h | 12 +++++----- include/configs/ls2080ardb.h | 52 ++++++++++++++++++++++---------------------- 2 files changed, 32 insertions(+), 32 deletions(-) (limited to 'include') diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 9539e2a8db2..88da69f36f0 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017, 2019 NXP + * Copyright 2017, 2019-2020 NXP * Copyright 2015 Freescale Semiconductor */ @@ -349,8 +349,8 @@ unsigned long get_board_ddr_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "mcmemsize=0x40000000\0" \ - "mcinitcmd=esbc_validate 0x580700000;" \ - "esbc_validate 0x580740000;" \ + "mcinitcmd=esbc_validate 0x580640000;" \ + "esbc_validate 0x580680000;" \ "fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" #else @@ -378,7 +378,7 @@ unsigned long get_board_ddr_clk(void); "kernel_size=0x2800000\0" \ "kernel_size_sd=0x14000\0" \ "load_addr=0xa0000000\0" \ - "kernelheader_addr=0x580800000\0" \ + "kernelheader_addr=0x580600000\0" \ "kernelheader_addr_r=0x80200000\0" \ "kernelheader_size=0x40000\0" \ "BOARD=ls2088aqds\0" \ @@ -431,7 +431,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_TFABOOT #define SD_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ + "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ "&& esbc_validate $load_addr; " \ "env exists mcinitcmd && run mcinitcmd " \ "&& mmc read 0x80d00000 0x6800 0x800 " \ @@ -441,7 +441,7 @@ unsigned long get_board_ddr_clk(void); #define IFC_NOR_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x580780000; env exists mcinitcmd "\ + "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ "&& fsl_mc lazyapply dpl 0x580d00000;" \ "run nor_bootcmd; " \ "env exists secureboot && esbc_halt;" diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index de14fb4ac82..c1819d22a84 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017, 2019 NXP + * Copyright 2017, 2019-2020 NXP * Copyright 2015 Freescale Semiconductor */ @@ -323,46 +323,46 @@ unsigned long get_board_sys_clk(void); #ifdef CONFIG_TFABOOT #define QSPI_MC_INIT_CMD \ "env exists secureboot && " \ - "esbc_validate 0x20700000 && " \ - "esbc_validate 0x20740000;" \ + "esbc_validate 0x20640000 && " \ + "esbc_validate 0x20680000;" \ "fsl_mc start mc 0x20a00000 0x20e00000 \0" #define SD_MC_INIT_CMD \ "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ "mmc read 0x80e00000 0x7000 0x800;" \ "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x20 && " \ - "mmc read 0x80740000 0x3A00 0x20 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80a00000 0x80e00000\0" #define IFC_MC_INIT_CMD \ "env exists secureboot && " \ - "esbc_validate 0x580700000 && " \ - "esbc_validate 0x580740000; " \ + "esbc_validate 0x580640000 && " \ + "esbc_validate 0x580680000; " \ "fsl_mc start mc 0x580a00000 0x580e00000 \0" #else #ifdef CONFIG_QSPI_BOOT #define MC_INIT_CMD \ "mcinitcmd=env exists secureboot && " \ - "esbc_validate 0x20700000 && " \ - "esbc_validate 0x20740000;" \ + "esbc_validate 0x20640000 && " \ + "esbc_validate 0x20680000;" \ "fsl_mc start mc 0x20a00000 0x20e00000 \0" #elif defined(CONFIG_SD_BOOT) #define MC_INIT_CMD \ "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ "mmc read 0x80100000 0x7000 0x800;" \ "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x20 && " \ - "mmc read 0x80740000 0x3A00 0x20 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80000000 0x80100000\0" \ "mcmemsize=0x70000000\0" #else #define MC_INIT_CMD \ "mcinitcmd=env exists secureboot && " \ - "esbc_validate 0x580700000 && " \ - "esbc_validate 0x580740000; " \ + "esbc_validate 0x580640000 && " \ + "esbc_validate 0x580680000; " \ "fsl_mc start mc 0x580a00000 0x580e00000 \0" #endif #endif @@ -384,7 +384,7 @@ unsigned long get_board_sys_clk(void); "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ "kernelheader_addr_r=0x80200000\0" \ - "kernelheader_addr=0x580800000\0" \ + "kernelheader_addr=0x580600000\0" \ "kernel_addr_r=0x81000000\0" \ "kernelheader_size=0x40000\0" \ "fdt_addr_r=0x90000000\0" \ @@ -442,12 +442,12 @@ unsigned long get_board_sys_clk(void); "fdt_addr=0x64f00000\0" \ "kernel_addr=0x581000000\0" \ "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ + "kernelheader_start=0x600000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ "kernelheader_addr_r=0x80200000\0" \ - "kernelheader_addr=0x580800000\0" \ + "kernelheader_addr=0x580600000\0" \ "kernel_addr_r=0x81000000\0" \ "kernelheader_size=0x40000\0" \ "fdt_addr_r=0x90000000\0" \ @@ -501,7 +501,7 @@ unsigned long get_board_sys_clk(void); #ifdef CONFIG_TFABOOT #define QSPI_NOR_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x20780000; " \ + "&& esbc_validate 0x206C0000; " \ "env exists mcinitcmd && " \ "fsl_mc lazyapply dpl 0x20d00000; " \ "run distro_bootcmd;run qspi_bootcmd; " \ @@ -510,7 +510,7 @@ unsigned long get_board_sys_clk(void); /* Try to boot an on-SD kernel first, then do normal distro boot */ #define SD_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ + "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ "&& esbc_validate $load_addr; " \ "env exists mcinitcmd && run mcinitcmd " \ "&& mmc read 0x80d00000 0x6800 0x800 " \ @@ -521,7 +521,7 @@ unsigned long get_board_sys_clk(void); /* Try to boot an on-NOR kernel first, then do normal distro boot */ #define IFC_NOR_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x580780000; env exists mcinitcmd "\ + "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ "&& fsl_mc lazyapply dpl 0x580d00000;" \ "run distro_bootcmd;run nor_bootcmd; " \ "env exists secureboot && esbc_halt;" @@ -531,7 +531,7 @@ unsigned long get_board_sys_clk(void); /* Try to boot an on-QSPI kernel first, then do normal distro boot */ #define CONFIG_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x20780000; " \ + "&& esbc_validate 0x206C0000; " \ "env exists mcinitcmd && " \ "fsl_mc lazyapply dpl 0x20d00000; " \ "run distro_bootcmd;run qspi_bootcmd; " \ @@ -540,7 +540,7 @@ unsigned long get_board_sys_clk(void); /* Try to boot an on-SD kernel first, then do normal distro boot */ #define CONFIG_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ + "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ "&& esbc_validate $load_addr; " \ "env exists mcinitcmd && run mcinitcmd " \ "&& mmc read 0x88000000 0x6800 0x800 " \ @@ -551,7 +551,7 @@ unsigned long get_board_sys_clk(void); /* Try to boot an on-NOR kernel first, then do normal distro boot */ #define CONFIG_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x580780000; env exists mcinitcmd "\ + "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ "&& fsl_mc lazyapply dpl 0x580d00000;" \ "run distro_bootcmd;run nor_bootcmd; " \ "env exists secureboot && esbc_halt;" -- cgit v1.3.1