From 5cca52a4cad8461457d938512829eeb9c68377ff Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 12 Sep 2016 12:01:47 -0300 Subject: wandboard: Remove videoargs script The videoargs script is kernel version dependent and since wandboard uses distro config, there is no need to handle videoargs locally. In case such video related settings are needed, then the proper location would be the distro extlinux.conf or boot.scr files. So remove 'videoargs' script. Signed-off-by: Fabio Estevam --- include/configs/wandboard.h | 26 -------------------------- 1 file changed, 26 deletions(-) (limited to 'include') diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 69d0fd5c88e..999ee6de97a 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -116,32 +116,6 @@ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ "fi; " \ "fi\0" \ - "videoargs=" \ - "setenv nextcon 0; " \ - "if hdmidet; then " \ - "setenv bootargs ${bootargs} " \ - "video=mxcfb${nextcon}:dev=hdmi,1280x720M@60," \ - "if=RGB24; " \ - "setenv fbmen fbmem=28M; " \ - "setexpr nextcon ${nextcon} + 1; " \ - "else " \ - "echo - no HDMI monitor;" \ - "fi; " \ - "i2c dev 1; " \ - "if i2c probe 0x10; then " \ - "setenv bootargs ${bootargs} " \ - "video=mxcfb${nextcon}:dev=lcd,800x480@60," \ - "if=RGB666,bpp=32; " \ - "if test 0 -eq ${nextcon}; then " \ - "setenv fbmem fbmem=10M; " \ - "else " \ - "setenv fbmem ${fbmem},10M; " \ - "fi; " \ - "setexpr nextcon ${nextcon} + 1; " \ - "else " \ - "echo '- no FWBADAPT-7WVGA-LCD-F07A-0102 display';" \ - "fi; " \ - "setenv bootargs ${bootargs} ${fbmem}\0" \ "findfdt="\ "if test $board_name = C1 && test $board_rev = MX6Q ; then " \ "setenv fdtfile imx6q-wandboard.dtb; fi; " \ -- cgit v1.3.1 From 29138c6ff80d6e736640050f5e9643637c44abad Mon Sep 17 00:00:00 2001 From: Soeren Moch Date: Wed, 21 Sep 2016 13:16:21 +0200 Subject: board: tbs2910: Fix BOOTMAPSZ The linux kernel imx_v6_v7_defconfig sets the user/kernel memory split to 3G/1G now (was 2G/2G before). We have to adapt the BOOTMAPSZ so that the decompressor finds zImage and dtb in lowmem. Signed-off-by: Soeren Moch --- include/configs/tbs2910.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 85501bca0ff..facd9cf0df9 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -39,7 +39,7 @@ #define CONFIG_SYS_MEMTEST_END \ (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ 0x6C000000 +#define CONFIG_SYS_BOOTMAPSZ 0x10000000 /* Serial console */ #define CONFIG_MXC_UART -- cgit v1.3.1 From 9eeab572113b2978d42cbb32886a1e90434bf07c Mon Sep 17 00:00:00 2001 From: Ross Parker Date: Tue, 2 Aug 2016 08:08:07 +0000 Subject: imx_watchdog: Do not assert WDOG_B on watchdog init Currently the driver asserts WDOG_B by clearing WCR_WDA bit when enabling the watchdog. Do not clear WCR_WDA. Signed-off-by: Ross Parker Cc: Stefano Babic --- drivers/watchdog/imx_watchdog.c | 2 +- include/fsl_wdog.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 2938d9f1fe9..3f826d10eb9 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -34,7 +34,7 @@ void hw_watchdog_init(void) #endif timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | - SET_WCR_WT(timeout), &wdog->wcr); + WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr); hw_watchdog_reset(); } #endif diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h index f698d4d64ed..683c3f3bac6 100644 --- a/include/fsl_wdog.h +++ b/include/fsl_wdog.h @@ -15,5 +15,6 @@ struct watchdog_regs { #define WCR_WDE 0x04 #define WCR_WDT 0x08 #define WCR_SRS 0x10 +#define WCR_WDA 0x20 #define SET_WCR_WT(x) (x << 8) #define WCR_WT_MSK SET_WCR_WT(0xFF) -- cgit v1.3.1 From 43a1be42ee34ac093460abc20d5959009aacdffe Mon Sep 17 00:00:00 2001 From: Soeren Moch Date: Thu, 22 Sep 2016 20:29:34 +0200 Subject: board: tbs2910: Add CMD_PART There is no stable mmcblk device numbering over different linux versions. Enable CMD_PART to be able to query the UUID of the root filesystem partition. So we can pass root=PARTUUID=XXX instead of root=/dev/mmcblkXpY in bootargs. Leave the default environment as is for now to stay compatible with original TBS settings. Signed-off-by: Soeren Moch --- include/configs/tbs2910.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index facd9cf0df9..d8773362a95 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -56,9 +56,11 @@ /* *** Command definition *** */ #define CONFIG_CMD_BMODE +#define CONFIG_CMD_PART /* Filesystems / image support */ #define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS /* MMC */ #define CONFIG_SYS_FSL_USDHC_NUM 3 -- cgit v1.3.1 From fa7209117b27115dd4d1f3df4ba57bc61f6c805c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 11 Aug 2016 14:02:54 +0800 Subject: dt-bindings: add i.mx6ul clock header Add i.mx6ul clock header, copied from kernel commit (29b4817d401). i.MX6ULL reuse the file in Linux Kernel, so let's keep the same. Signed-off-by: Peng Fan Cc: Simon Glass Cc: Stefano Babic --- include/dt-bindings/clock/imx6ul-clock.h | 253 +++++++++++++++++++++++++++++++ 1 file changed, 253 insertions(+) create mode 100644 include/dt-bindings/clock/imx6ul-clock.h (limited to 'include') diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h new file mode 100644 index 00000000000..18de0709322 --- /dev/null +++ b/include/dt-bindings/clock/imx6ul-clock.h @@ -0,0 +1,253 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H +#define __DT_BINDINGS_CLOCK_IMX6UL_H + +#define IMX6UL_CLK_DUMMY 0 +#define IMX6UL_CLK_CKIL 1 +#define IMX6UL_CLK_CKIH 2 +#define IMX6UL_CLK_OSC 3 +#define IMX6UL_PLL1_BYPASS_SRC 4 +#define IMX6UL_PLL2_BYPASS_SRC 5 +#define IMX6UL_PLL3_BYPASS_SRC 6 +#define IMX6UL_PLL4_BYPASS_SRC 7 +#define IMX6UL_PLL5_BYPASS_SRC 8 +#define IMX6UL_PLL6_BYPASS_SRC 9 +#define IMX6UL_PLL7_BYPASS_SRC 10 +#define IMX6UL_CLK_PLL1 11 +#define IMX6UL_CLK_PLL2 12 +#define IMX6UL_CLK_PLL3 13 +#define IMX6UL_CLK_PLL4 14 +#define IMX6UL_CLK_PLL5 15 +#define IMX6UL_CLK_PLL6 16 +#define IMX6UL_CLK_PLL7 17 +#define IMX6UL_PLL1_BYPASS 18 +#define IMX6UL_PLL2_BYPASS 19 +#define IMX6UL_PLL3_BYPASS 20 +#define IMX6UL_PLL4_BYPASS 21 +#define IMX6UL_PLL5_BYPASS 22 +#define IMX6UL_PLL6_BYPASS 23 +#define IMX6UL_PLL7_BYPASS 24 +#define IMX6UL_CLK_PLL1_SYS 25 +#define IMX6UL_CLK_PLL2_BUS 26 +#define IMX6UL_CLK_PLL3_USB_OTG 27 +#define IMX6UL_CLK_PLL4_AUDIO 28 +#define IMX6UL_CLK_PLL5_VIDEO 29 +#define IMX6UL_CLK_PLL6_ENET 30 +#define IMX6UL_CLK_PLL7_USB_HOST 31 +#define IMX6UL_CLK_USBPHY1 32 +#define IMX6UL_CLK_USBPHY2 33 +#define IMX6UL_CLK_USBPHY1_GATE 34 +#define IMX6UL_CLK_USBPHY2_GATE 35 +#define IMX6UL_CLK_PLL2_PFD0 36 +#define IMX6UL_CLK_PLL2_PFD1 37 +#define IMX6UL_CLK_PLL2_PFD2 38 +#define IMX6UL_CLK_PLL2_PFD3 39 +#define IMX6UL_CLK_PLL3_PFD0 40 +#define IMX6UL_CLK_PLL3_PFD1 41 +#define IMX6UL_CLK_PLL3_PFD2 42 +#define IMX6UL_CLK_PLL3_PFD3 43 +#define IMX6UL_CLK_ENET_REF 44 +#define IMX6UL_CLK_ENET2_REF 45 +#define IMX6UL_CLK_ENET2_REF_125M 46 +#define IMX6UL_CLK_ENET_PTP_REF 47 +#define IMX6UL_CLK_ENET_PTP 48 +#define IMX6UL_CLK_PLL4_POST_DIV 49 +#define IMX6UL_CLK_PLL4_AUDIO_DIV 50 +#define IMX6UL_CLK_PLL5_POST_DIV 51 +#define IMX6UL_CLK_PLL5_VIDEO_DIV 52 +#define IMX6UL_CLK_PLL2_198M 53 +#define IMX6UL_CLK_PLL3_80M 54 +#define IMX6UL_CLK_PLL3_60M 55 +#define IMX6UL_CLK_STEP 56 +#define IMX6UL_CLK_PLL1_SW 57 +#define IMX6UL_CLK_AXI_ALT_SEL 58 +#define IMX6UL_CLK_AXI_SEL 59 +#define IMX6UL_CLK_PERIPH_PRE 60 +#define IMX6UL_CLK_PERIPH2_PRE 61 +#define IMX6UL_CLK_PERIPH_CLK2_SEL 62 +#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63 +#define IMX6UL_CLK_USDHC1_SEL 64 +#define IMX6UL_CLK_USDHC2_SEL 65 +#define IMX6UL_CLK_BCH_SEL 66 +#define IMX6UL_CLK_GPMI_SEL 67 +#define IMX6UL_CLK_EIM_SLOW_SEL 68 +#define IMX6UL_CLK_SPDIF_SEL 69 +#define IMX6UL_CLK_SAI1_SEL 70 +#define IMX6UL_CLK_SAI2_SEL 71 +#define IMX6UL_CLK_SAI3_SEL 72 +#define IMX6UL_CLK_LCDIF_PRE_SEL 73 +#define IMX6UL_CLK_SIM_PRE_SEL 74 +#define IMX6UL_CLK_LDB_DI0_SEL 75 +#define IMX6UL_CLK_LDB_DI1_SEL 76 +#define IMX6UL_CLK_ENFC_SEL 77 +#define IMX6UL_CLK_CAN_SEL 78 +#define IMX6UL_CLK_ECSPI_SEL 79 +#define IMX6UL_CLK_UART_SEL 80 +#define IMX6UL_CLK_QSPI1_SEL 81 +#define IMX6UL_CLK_PERCLK_SEL 82 +#define IMX6UL_CLK_LCDIF_SEL 83 +#define IMX6UL_CLK_SIM_SEL 84 +#define IMX6UL_CLK_PERIPH 85 +#define IMX6UL_CLK_PERIPH2 86 +#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87 +#define IMX6UL_CLK_LDB_DI0_DIV_7 88 +#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89 +#define IMX6UL_CLK_LDB_DI1_DIV_7 90 +#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91 +#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 +#define IMX6UL_CLK_ARM 93 +#define IMX6UL_CLK_PERIPH_CLK2 94 +#define IMX6UL_CLK_PERIPH2_CLK2 95 +#define IMX6UL_CLK_AHB 96 +#define IMX6UL_CLK_MMDC_PODF 97 +#define IMX6UL_CLK_AXI_PODF 98 +#define IMX6UL_CLK_PERCLK 99 +#define IMX6UL_CLK_IPG 100 +#define IMX6UL_CLK_USDHC1_PODF 101 +#define IMX6UL_CLK_USDHC2_PODF 102 +#define IMX6UL_CLK_BCH_PODF 103 +#define IMX6UL_CLK_GPMI_PODF 104 +#define IMX6UL_CLK_EIM_SLOW_PODF 105 +#define IMX6UL_CLK_SPDIF_PRED 106 +#define IMX6UL_CLK_SPDIF_PODF 107 +#define IMX6UL_CLK_SAI1_PRED 108 +#define IMX6UL_CLK_SAI1_PODF 109 +#define IMX6UL_CLK_SAI2_PRED 110 +#define IMX6UL_CLK_SAI2_PODF 111 +#define IMX6UL_CLK_SAI3_PRED 112 +#define IMX6UL_CLK_SAI3_PODF 113 +#define IMX6UL_CLK_LCDIF_PRED 114 +#define IMX6UL_CLK_LCDIF_PODF 115 +#define IMX6UL_CLK_SIM_PODF 116 +#define IMX6UL_CLK_QSPI1_PDOF 117 +#define IMX6UL_CLK_ENFC_PRED 118 +#define IMX6UL_CLK_ENFC_PODF 119 +#define IMX6UL_CLK_CAN_PODF 120 +#define IMX6UL_CLK_ECSPI_PODF 121 +#define IMX6UL_CLK_UART_PODF 122 +#define IMX6UL_CLK_ADC1 123 +#define IMX6UL_CLK_ADC2 124 +#define IMX6UL_CLK_AIPSTZ1 125 +#define IMX6UL_CLK_AIPSTZ2 126 +#define IMX6UL_CLK_AIPSTZ3 127 +#define IMX6UL_CLK_APBHDMA 128 +#define IMX6UL_CLK_ASRC_IPG 129 +#define IMX6UL_CLK_ASRC_MEM 130 +#define IMX6UL_CLK_GPMI_BCH_APB 131 +#define IMX6UL_CLK_GPMI_BCH 132 +#define IMX6UL_CLK_GPMI_IO 133 +#define IMX6UL_CLK_GPMI_APB 134 +#define IMX6UL_CLK_CAAM_MEM 135 +#define IMX6UL_CLK_CAAM_ACLK 136 +#define IMX6UL_CLK_CAAM_IPG 137 +#define IMX6UL_CLK_CSI 138 +#define IMX6UL_CLK_ECSPI1 139 +#define IMX6UL_CLK_ECSPI2 140 +#define IMX6UL_CLK_ECSPI3 141 +#define IMX6UL_CLK_ECSPI4 142 +#define IMX6UL_CLK_EIM 143 +#define IMX6UL_CLK_ENET 144 +#define IMX6UL_CLK_ENET_AHB 145 +#define IMX6UL_CLK_EPIT1 146 +#define IMX6UL_CLK_EPIT2 147 +#define IMX6UL_CLK_CAN1_IPG 148 +#define IMX6UL_CLK_CAN1_SERIAL 149 +#define IMX6UL_CLK_CAN2_IPG 150 +#define IMX6UL_CLK_CAN2_SERIAL 151 +#define IMX6UL_CLK_GPT1_BUS 152 +#define IMX6UL_CLK_GPT1_SERIAL 153 +#define IMX6UL_CLK_GPT2_BUS 154 +#define IMX6UL_CLK_GPT2_SERIAL 155 +#define IMX6UL_CLK_I2C1 156 +#define IMX6UL_CLK_I2C2 157 +#define IMX6UL_CLK_I2C3 158 +#define IMX6UL_CLK_I2C4 159 +#define IMX6UL_CLK_IOMUXC 160 +#define IMX6UL_CLK_LCDIF_APB 161 +#define IMX6UL_CLK_LCDIF_PIX 162 +#define IMX6UL_CLK_MMDC_P0_FAST 163 +#define IMX6UL_CLK_MMDC_P0_IPG 164 +#define IMX6UL_CLK_OCOTP 165 +#define IMX6UL_CLK_OCRAM 166 +#define IMX6UL_CLK_PWM1 167 +#define IMX6UL_CLK_PWM2 168 +#define IMX6UL_CLK_PWM3 169 +#define IMX6UL_CLK_PWM4 170 +#define IMX6UL_CLK_PWM5 171 +#define IMX6UL_CLK_PWM6 172 +#define IMX6UL_CLK_PWM7 173 +#define IMX6UL_CLK_PWM8 174 +#define IMX6UL_CLK_PXP 175 +#define IMX6UL_CLK_QSPI 176 +#define IMX6UL_CLK_ROM 177 +#define IMX6UL_CLK_SAI1 178 +#define IMX6UL_CLK_SAI1_IPG 179 +#define IMX6UL_CLK_SAI2 180 +#define IMX6UL_CLK_SAI2_IPG 181 +#define IMX6UL_CLK_SAI3 182 +#define IMX6UL_CLK_SAI3_IPG 183 +#define IMX6UL_CLK_SDMA 184 +#define IMX6UL_CLK_SIM 185 +#define IMX6UL_CLK_SIM_S 186 +#define IMX6UL_CLK_SPBA 187 +#define IMX6UL_CLK_SPDIF 188 +#define IMX6UL_CLK_UART1_IPG 189 +#define IMX6UL_CLK_UART1_SERIAL 190 +#define IMX6UL_CLK_UART2_IPG 191 +#define IMX6UL_CLK_UART2_SERIAL 192 +#define IMX6UL_CLK_UART3_IPG 193 +#define IMX6UL_CLK_UART3_SERIAL 194 +#define IMX6UL_CLK_UART4_IPG 195 +#define IMX6UL_CLK_UART4_SERIAL 196 +#define IMX6UL_CLK_UART5_IPG 197 +#define IMX6UL_CLK_UART5_SERIAL 198 +#define IMX6UL_CLK_UART6_IPG 199 +#define IMX6UL_CLK_UART6_SERIAL 200 +#define IMX6UL_CLK_UART7_IPG 201 +#define IMX6UL_CLK_UART7_SERIAL 202 +#define IMX6UL_CLK_UART8_IPG 203 +#define IMX6UL_CLK_UART8_SERIAL 204 +#define IMX6UL_CLK_USBOH3 205 +#define IMX6UL_CLK_USDHC1 206 +#define IMX6UL_CLK_USDHC2 207 +#define IMX6UL_CLK_WDOG1 208 +#define IMX6UL_CLK_WDOG2 209 +#define IMX6UL_CLK_WDOG3 210 +#define IMX6UL_CLK_LDB_DI0 211 +#define IMX6UL_CLK_AXI 212 +#define IMX6UL_CLK_SPDIF_GCLK 213 +#define IMX6UL_CLK_GPT_3M 214 +#define IMX6UL_CLK_SIM2 215 +#define IMX6UL_CLK_SIM1 216 +#define IMX6UL_CLK_IPP_DI0 217 +#define IMX6UL_CLK_IPP_DI1 218 +#define IMX6UL_CA7_SECONDARY_SEL 219 +#define IMX6UL_CLK_PER_BCH 220 +#define IMX6UL_CLK_CSI_SEL 221 +#define IMX6UL_CLK_CSI_PODF 222 +#define IMX6UL_CLK_PLL3_120M 223 +/* For i.MX6ULL */ +#define IMX6UL_CLK_ESAI_SEL 224 +#define IMX6UL_CLK_ESAI_PRED 225 +#define IMX6UL_CLK_ESAI_PODF 226 +#define IMX6UL_CLK_ESAI_EXTAL 227 +#define IMX6UL_CLK_ESAI_MEM 228 +#define IMX6UL_CLK_ESAI_IPG 229 +#define IMX6UL_CLK_DCP_CLK 230 +#define IMX6UL_CLK_EPDC_PRE_SEL 231 +#define IMX6UL_CLK_EPDC_SEL 232 +#define IMX6UL_CLK_EPDC_PODF 233 +#define IMX6UL_CLK_EPDC_ACLK 234 +#define IMX6UL_CLK_EPDC_PIX 235 + +#define IMX6UL_CLK_END 236 + +#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ -- cgit v1.3.1 From 55a42b33f2e9b9f6330396fc6d89878a5deacc75 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 11 Aug 2016 14:02:57 +0800 Subject: arm: imx: add i.MX6ULL 14x14 EVK board support Add i.MX6ULL EVK board support: Add device tree file, which is copied from NXP Linux. Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR. The uart iomux settings are still keeped in board file. Boot Log: U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800) CPU: Freescale i.MX6ULL rev1.0 at 396MHz CPU: Commercial temperature grade (0C to 95C) at 15C Reset cause: POR Model: Freescale i.MX6 ULL 14x14 EVK Board Board: MX6ULL 14x14 EVK DRAM: 512 MiB MMC: initialized IMX pinctrl driver FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 => mmc dev 1 switch to partitions #0, OK mmc1 is current device Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/cpu/armv7/mx6/Kconfig | 7 + arch/arm/dts/Makefile | 2 + arch/arm/dts/imx6ull-14x14-evk.dts | 527 +++++++++++++++++++++++++++++++++ board/freescale/mx6ullevk/Kconfig | 12 + board/freescale/mx6ullevk/MAINTAINERS | 6 + board/freescale/mx6ullevk/Makefile | 6 + board/freescale/mx6ullevk/imximage.cfg | 116 ++++++++ board/freescale/mx6ullevk/mx6ullevk.c | 99 +++++++ configs/mx6ull_14x14_evk_defconfig | 30 ++ include/configs/mx6ullevk.h | 180 +++++++++++ 10 files changed, 985 insertions(+) create mode 100644 arch/arm/dts/imx6ull-14x14-evk.dts create mode 100644 board/freescale/mx6ullevk/Kconfig create mode 100644 board/freescale/mx6ullevk/MAINTAINERS create mode 100644 board/freescale/mx6ullevk/Makefile create mode 100644 board/freescale/mx6ullevk/imximage.cfg create mode 100644 board/freescale/mx6ullevk/mx6ullevk.c create mode 100644 configs/mx6ull_14x14_evk_defconfig create mode 100644 include/configs/mx6ullevk.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 32405c6fe43..d851b264ead 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -137,6 +137,12 @@ config TARGET_MX6UL_14X14_EVK select DM_THERMAL select SUPPORT_SPL +config TARGET_MX6ULL_14X14_EVK + bool "Support mx6ull_14x14_evk" + select MX6ULL + select DM + select DM_THERMAL + config TARGET_NITROGEN6X bool "nitrogen6x" @@ -226,6 +232,7 @@ source "board/freescale/mx6slevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" +source "board/freescale/mx6ullevk/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 032c5aebc1c..19140b48ca0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -280,6 +280,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ vf610-twr.dtb \ pcm052.dtb +dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb + dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2l-evm.dtb \ k2e-evm.dtb \ diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts new file mode 100644 index 00000000000..375bd4ea319 --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-evk.dts @@ -0,0 +1,527 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ull.dtsi" + +/ { + model = "Freescale i.MX6 ULL 14x14 EVK Board"; + compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + oe-gpios = <&gpio5 8 0>; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&cpu0 { + arm-supply = <®_arm>; + soc-supply = <®_soc>; + dc-supply = <®_gpio_dvfs>; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default_snvs"; + pinctrl-0 = <&pinctrl_hog_2>; + imx6ul-evk { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_lcdif_reset: lcdifresetgrp { + fsl,pins = < + /* used for lcd reset */ + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_sai2_hp_det_b: sai2_hp_det_grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + }; +}; + + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl + &pinctrl_lcdif_reset>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; diff --git a/board/freescale/mx6ullevk/Kconfig b/board/freescale/mx6ullevk/Kconfig new file mode 100644 index 00000000000..7eec497e3ea --- /dev/null +++ b/board/freescale/mx6ullevk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6ULL_14X14_EVK + +config SYS_BOARD + default "mx6ullevk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6ullevk" + +endif diff --git a/board/freescale/mx6ullevk/MAINTAINERS b/board/freescale/mx6ullevk/MAINTAINERS new file mode 100644 index 00000000000..4137674d36a --- /dev/null +++ b/board/freescale/mx6ullevk/MAINTAINERS @@ -0,0 +1,6 @@ +MX6ULLEVK BOARD +M: Peng Fan +S: Maintained +F: board/freescale/mx6ullevk/ +F: include/configs/mx6ullevk.h +F: configs/mx6ull_14x14_evk_defconfig diff --git a/board/freescale/mx6ullevk/Makefile b/board/freescale/mx6ullevk/Makefile new file mode 100644 index 00000000000..c64fba407e0 --- /dev/null +++ b/board/freescale/mx6ullevk/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ullevk.o diff --git a/board/freescale/mx6ullevk/imximage.cfg b/board/freescale/mx6ullevk/imximage.cfg new file mode 100644 index 00000000000..4604b624852 --- /dev/null +++ b/board/freescale/mx6ullevk/imximage.cfg @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ullevk/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x000C0030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000004 +DATA 4 0x021B083C 0x41640158 +DATA 4 0x021B0848 0x40403237 +DATA 4 0x021B0850 0x40403C33 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00944009 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 + +#endif diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c new file mode 100644 index 00000000000..489bf2114b8 --- /dev/null +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_map_to_kernel_blk(int devno) +{ + return devno; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + setenv("board_name", "EVK"); + setenv("board_rev", "14X14"); +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: MX6ULL 14x14 EVK\n"); + + return 0; +} diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig new file mode 100644 index 00000000000..a106b5d9a1e --- /dev/null +++ b/configs/mx6ull_14x14_evk_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_SPI=y diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h new file mode 100644 index 00000000000..ccce9546b71 --- /dev/null +++ b/include/configs/mx6ullevk.h @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 EVK board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6ULLEVK_CONFIG_H +#define __MX6ULLEVK_CONFIG_H + + +#include +#include +#include "mx6_common.h" +#include + +#ifdef CONFIG_SECURE_BOOT +#ifndef CONFIG_CSF_SIZE +#define CONFIG_CSF_SIZE 0x4000 +#endif +#endif + +#define PHYS_SDRAM_SIZE SZ_512M + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#ifdef CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* NAND pin conflicts with usdhc2 */ +#ifdef CONFIG_SYS_USE_NAND +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif +#endif + +/* I2C configs */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6ull-14x14-evk.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_OFFSET (12 * SZ_64K) + +#define CONFIG_CMD_BMODE + +#define CONFIG_IMX_THERMAL + +#define CONFIG_IOMUX_LPSR + +#define CONFIG_SOFT_SPI + +#endif -- cgit v1.3.1 From 27f7d4f5f754d0eb124a8aa8e92d0dd578e15286 Mon Sep 17 00:00:00 2001 From: "Albert ARIBAUD \\(3ADEV\\)" Date: Mon, 26 Sep 2016 09:08:03 +0200 Subject: pcm052: fix MTD partitioning Merge 'spare' into 'bootloader' partition Use same partition for ramdisk and rootfs boot scenarios. Remove 'ramdisk' partition, use 'rootfs' for ramdisk (ramdisk and nand boot scenarios are mutually exclusive). Expand last partition to end of actual NAND size. Adjust UBIFS rootfs boot kernel arguments. Signed-off-by: Albert ARIBAUD (3ADEV) --- include/configs/pcm052.h | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index a70c9887e75..0f749888896 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -53,14 +53,12 @@ #define CONFIG_MTD_PARTITIONS #define CONFIG_MTD_DEVICE #define MTDIDS_DEFAULT "nand0=NAND" -#define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\ - ",384k(bootloader)"\ +#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\ ",128k(env1)"\ ",128k(env2)"\ ",128k(dtb)"\ ",6144k(kernel)"\ - ",65536k(ramdisk)"\ - ",450944k(root)" + ",-(root)" #endif #define CONFIG_MMC @@ -144,7 +142,7 @@ "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \ "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \ "bootargs_nand=setenv bootargs ${bootargs} " \ - "ubi.mtd=6 rootfstype=ubifs root=ubi0:rootfs\0" \ + "ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \ "bootargs_ram=setenv bootargs ${bootargs} " \ "root=/dev/ram rw initrd=${ram_addr}\0" \ "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ @@ -163,7 +161,7 @@ "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ "nand read ${fdt_addr} dtb; " \ "nand read ${kernel_addr} kernel; " \ - "nand read ${ram_addr} ramdisk; " \ + "nand read ${ram_addr} root; " \ "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ "update_bootloader_from_tftp=mtdparts default; " \ "nand read ${blsec_addr} bootloader; " \ @@ -195,8 +193,8 @@ "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \ "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ "then mtdparts default; " \ - "nand erase.part ramdisk; " \ - "nand write ${ram_addr} ramdisk ${filesize}; fi\0" + "nand erase.part root; " \ + "nand write ${ram_addr} root ${filesize}; fi\0" /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -- cgit v1.3.1 From 083e4fd401f5a29343c28333a5b83693b44bea5a Mon Sep 17 00:00:00 2001 From: "Albert ARIBAUD \\(3ADEV\\)" Date: Mon, 26 Sep 2016 09:08:04 +0200 Subject: pcm052: remove target-specific dtb name from env Signed-off-by: Albert ARIBAUD (3ADEV) --- include/configs/pcm052.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 0f749888896..7ba8e0a65ab 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -124,7 +124,7 @@ "blimg_addr=0x81000400\0" \ "kernel_file=zImage\0" \ "kernel_addr=0x82000000\0" \ - "fdt_file=vf610-pcm052.dtb\0" \ + "fdt_file=zImage.dtb\0" \ "fdt_addr=0x81000000\0" \ "ram_file=uRamdisk\0" \ "ram_addr=0x83000000\0" \ -- cgit v1.3.1 From ed0c2c0a9ead7d1b5739fc83cf99ac85a16cb979 Mon Sep 17 00:00:00 2001 From: "Albert ARIBAUD \\(3ADEV\\)" Date: Mon, 26 Sep 2016 09:08:06 +0200 Subject: tools: mkimage: add support for Vybrid image format This format can be flashed directly at address 0 of the NAND FLASH, as it contains all necessary headers. Signed-off-by: Albert ARIBAUD (3ADEV) --- Makefile | 6 ++ arch/arm/config.mk | 3 + arch/arm/cpu/armv7/vf610/Makefile | 5 ++ common/image.c | 1 + include/configs/pcm052.h | 14 ++-- include/image.h | 1 + tools/Makefile | 1 + tools/vybridimage.c | 164 ++++++++++++++++++++++++++++++++++++++ 8 files changed, 187 insertions(+), 8 deletions(-) create mode 100644 tools/vybridimage.c (limited to 'include') diff --git a/Makefile b/Makefile index c67cc996332..e9cdf9a56d8 100644 --- a/Makefile +++ b/Makefile @@ -845,6 +845,12 @@ endif %.imx: %.bin $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ +%.vyb: %.imx + $(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@ + +quiet_cmd_copy = COPY $@ + cmd_copy = cp $< $@ + u-boot.dtb: dts/dt.dtb $(call cmd,copy) diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 8f8586295ef..542b897c31e 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -144,4 +144,7 @@ else ALL-y += u-boot.imx endif endif +ifneq ($(CONFIG_VF610),) +ALL-y += u-boot.vyb +endif endif diff --git a/arch/arm/cpu/armv7/vf610/Makefile b/arch/arm/cpu/armv7/vf610/Makefile index 68cb756d674..29453779f13 100644 --- a/arch/arm/cpu/armv7/vf610/Makefile +++ b/arch/arm/cpu/armv7/vf610/Makefile @@ -6,3 +6,8 @@ obj-y += generic.o obj-y += timer.o + +MKIMAGEFLAGS_u-boot.vyb = -T vybridimage + +u-boot.vyb: u-boot.imx + $(call if_changed,mkimage) diff --git a/common/image.c b/common/image.c index a5d19abfa93..c0ad36a60f8 100644 --- a/common/image.c +++ b/common/image.c @@ -161,6 +161,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_RKIMAGE, "rkimage", "Rockchip Boot Image" }, { IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" }, { IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" }, + { IH_TYPE_VYBRIDIMAGE, "vybridimage", "Vybrid Boot Image", }, { IH_TYPE_ZYNQIMAGE, "zynqimage", "Xilinx Zynq Boot Image" }, { IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" }, { IH_TYPE_FPGA, "fpga", "FPGA Image" }, diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 7ba8e0a65ab..564434ce4e7 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -119,9 +119,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "blimg_file=u-boot.imx\0" \ - "blsec_addr=0x81000000\0" \ - "blimg_addr=0x81000400\0" \ + "blimg_file=u-boot.vyb\0" \ + "blimg_addr=0x81000000\0" \ "kernel_file=zImage\0" \ "kernel_addr=0x82000000\0" \ "fdt_file=zImage.dtb\0" \ @@ -163,12 +162,11 @@ "nand read ${kernel_addr} kernel; " \ "nand read ${ram_addr} root; " \ "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ - "update_bootloader_from_tftp=mtdparts default; " \ - "nand read ${blsec_addr} bootloader; " \ - "mw.b ${blimg_addr} 0xff 0x5FC00; " \ - "if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \ + "update_bootloader_from_tftp=if tftp ${blimg_addr} "\ + "${tftpdir}${blimg_file}; then " \ + "mtdparts default; " \ "nand erase.part bootloader; " \ - "nand write ${blsec_addr} bootloader ${filesize}; fi\0" \ + "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \ "${kernel_file}; " \ "then mtdparts default; " \ diff --git a/include/image.h b/include/image.h index 64da7226490..2b1296c86c9 100644 --- a/include/image.h +++ b/include/image.h @@ -278,6 +278,7 @@ enum { IH_TYPE_ZYNQIMAGE, /* Xilinx Zynq Boot Image */ IH_TYPE_ZYNQMPIMAGE, /* Xilinx ZynqMP Boot Image */ IH_TYPE_FPGA, /* FPGA Image */ + IH_TYPE_VYBRIDIMAGE, /* VYBRID .vyb Image */ IH_TYPE_COUNT, /* Number of image types */ }; diff --git a/tools/Makefile b/tools/Makefile index 421414bc154..e6f7993f995 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -89,6 +89,7 @@ dumpimage-mkimage-objs := aisimage.o \ os_support.o \ pblimage.o \ pbl_crc32.o \ + vybridimage.o \ $(ROCKCHIP_OBS) \ socfpgaimage.o \ lib/sha1.o \ diff --git a/tools/vybridimage.c b/tools/vybridimage.c new file mode 100644 index 00000000000..a31fc1099cb --- /dev/null +++ b/tools/vybridimage.c @@ -0,0 +1,164 @@ +/* + * Image manipulator for Vybrid SoCs + * + * Derived from vybridimage.c + * + * (C) Copyright 2016 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "imagetool.h" +#include +#include + +/* + * NAND page 0 boot header + */ + +struct nand_page_0_boot_header { + union { + uint32_t fcb[128]; + uint8_t fcb_bytes[512]; + }; /* 0x00000000 - 0x000001ff */ + uint8_t sw_ecc[512]; /* 0x00000200 - 0x000003ff */ + uint32_t padding[65280]; /* 0x00000400 - 0x0003ffff */ + uint8_t ivt_prefix[1024]; /* 0x00040000 - 0x000403ff */ +}; + +/* signature byte for a readable block */ + +static struct nand_page_0_boot_header vybridimage_header; + +static int vybridimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_VYBRIDIMAGE) + return EXIT_SUCCESS; + return EXIT_FAILURE; +} + +static uint8_t vybridimage_sw_ecc(uint8_t byte) +{ + uint8_t bit0 = (byte & (1 << 0)) ? 1 : 0; + uint8_t bit1 = (byte & (1 << 1)) ? 1 : 0; + uint8_t bit2 = (byte & (1 << 2)) ? 1 : 0; + uint8_t bit3 = (byte & (1 << 3)) ? 1 : 0; + uint8_t bit4 = (byte & (1 << 4)) ? 1 : 0; + uint8_t bit5 = (byte & (1 << 5)) ? 1 : 0; + uint8_t bit6 = (byte & (1 << 6)) ? 1 : 0; + uint8_t bit7 = (byte & (1 << 7)) ? 1 : 0; + uint8_t res = 0; + + res |= ((bit6 ^ bit5 ^ bit3 ^ bit2) << 0); + res |= ((bit7 ^ bit5 ^ bit4 ^ bit2 ^ bit1) << 1); + res |= ((bit7 ^ bit6 ^ bit5 ^ bit1 ^ bit0) << 2); + res |= ((bit7 ^ bit4 ^ bit3 ^ bit0) << 3); + res |= ((bit6 ^ bit4 ^ bit3 ^ bit2 ^ bit1 ^ bit0) << 4); + + return res; +} + +static int vybridimage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + int idx; + + if (hdr->fcb[1] != 0x46434220) + return -1; + if (hdr->fcb[2] != 1) + return -1; + if (hdr->fcb[7] != 64) + return -1; + if (hdr->fcb[14] != 6) + return -1; + if (hdr->fcb[30] != 0x0001ff00) + return -1; + if (hdr->fcb[43] != 1) + return -1; + if (hdr->fcb[54] != 0) + return -1; + if (hdr->fcb[55] != 8) + return -1; + + /* check software ECC */ + for (idx = 0; idx < sizeof(hdr->fcb_bytes); idx++) { + uint8_t sw_ecc = vybridimage_sw_ecc(hdr->fcb_bytes[idx]); + if (sw_ecc != hdr->sw_ecc[idx]) + return -1; + } + + return 0; +} + +static void vybridimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + int idx; + + /* fill header with 0x00 for first 56 entries then 0xff */ + memset(&hdr->fcb[0], 0x0, 56*sizeof(uint32_t)); + memset(&hdr->fcb[56], 0xff, 72*sizeof(uint32_t)); + /* fill SW ecc and padding with 0xff */ + memset(&hdr->sw_ecc[0], 0xff, sizeof(hdr->sw_ecc)); + memset(&hdr->padding[0], 0xff, sizeof(hdr->padding)); + /* fill IVT prefix with 0x00 */ + memset(&hdr->ivt_prefix[0], 0x00, sizeof(hdr->ivt_prefix)); + + /* populate fcb */ + hdr->fcb[1] = 0x46434220; /* signature */ + hdr->fcb[2] = 0x00000001; /* version */ + hdr->fcb[5] = 2048; /* page size */ + hdr->fcb[6] = (2048+64); /* page + OOB size */ + hdr->fcb[7] = 64; /* pages per block */ + hdr->fcb[14] = 6; /* ECC mode 6 */ + hdr->fcb[26] = 128; /* fw address (0x40000) in 2K pages */ + hdr->fcb[27] = 128; /* fw address (0x40000) in 2K pages */ + hdr->fcb[30] = 0x0001ff00; /* DBBT search area start address */ + hdr->fcb[33] = 2048; /* BB marker physical offset */ + hdr->fcb[43] = 1; /* DISBBM */ + hdr->fcb[54] = 0; /* DISBB_Search */ + hdr->fcb[55] = 8; /* Bad block search limit */ + + /* compute software ECC */ + for (idx = 0; idx < sizeof(hdr->fcb_bytes); idx++) + hdr->sw_ecc[idx] = vybridimage_sw_ecc(hdr->fcb_bytes[idx]); +} + +static void vybridimage_print_hdr_field(struct nand_page_0_boot_header *hdr, + int idx) +{ + printf("header.fcb[%d] = %08x\n", idx, hdr->fcb[idx]); +} + +static void vybridimage_print_header(const void *ptr) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + int idx; + + for (idx = 0; idx < 56; idx++) + vybridimage_print_hdr_field(hdr, idx); +} + +/* + * vybridimage parameters + */ +U_BOOT_IMAGE_TYPE( + vybridimage, + "Vybrid Boot Image", + sizeof(vybridimage_header), + (void *)&vybridimage_header, + NULL, + vybridimage_verify_header, + vybridimage_print_header, + vybridimage_set_header, + NULL, + vybridimage_check_image_types, + NULL, + NULL +); -- cgit v1.3.1 From a7e5f7f3e5d2458090d8528a5a892a56911a11ce Mon Sep 17 00:00:00 2001 From: "Albert ARIBAUD \\(3ADEV\\)" Date: Mon, 26 Sep 2016 09:08:07 +0200 Subject: pcm052: allow specifying onboard DDR size in configs PCM052 SoMs may be equipped with various sizes of DDR. Keep default of 256MB; new PCM052-based targets will specify their actual DDR size. Linux command line is auto-adjusted to DDR size. Signed-off-by: Albert ARIBAUD (3ADEV) --- board/phytec/pcm052/Kconfig | 4 ++++ include/configs/pcm052.h | 5 +++-- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig index d67a69a747a..88524a34944 100644 --- a/board/phytec/pcm052/Kconfig +++ b/board/phytec/pcm052/Kconfig @@ -12,4 +12,8 @@ config SYS_SOC config SYS_CONFIG_NAME default "pcm052" +config PCM052_DDR_SIZE + int + default 256 + endif diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 564434ce4e7..32f958a6b25 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -134,7 +134,8 @@ "tftptimeout=1000\0" \ "tftptimeoutcountmax=1000000\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "bootargs_base=setenv bootargs rw mem=256M " \ + "bootargs_base=setenv bootargs rw " \ + " mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \ "console=ttyLP1,115200n8\0" \ "bootargs_sd=setenv bootargs ${bootargs} " \ "root=/dev/mmcblk0p2 rootwait\0" \ @@ -218,7 +219,7 @@ /* Physical memory map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM (0x80000000) -#define PHYS_SDRAM_SIZE (256 * 1024 * 1024) +#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -- cgit v1.3.1 From 27192d16eb3dacfedfb507f60a325b482bbf317f Mon Sep 17 00:00:00 2001 From: "Albert ARIBAUD \\(3ADEV\\)" Date: Mon, 26 Sep 2016 09:08:08 +0200 Subject: pcm052: add new BK4r1 target based on PCM052 SoM Signed-off-by: Albert ARIBAUD (3ADEV) --- arch/arm/Kconfig | 4 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/bk4r1.dts | 48 +++++++++++++ arch/arm/dts/vf.dtsi | 4 +- board/phytec/pcm052/Kconfig | 20 ++++++ board/phytec/pcm052/pcm052.c | 168 +++++++++++++++++++++++++++++-------------- configs/bk4r1_defconfig | 33 +++++++++ include/configs/bk4r1.h | 33 +++++++++ include/configs/pcm052.h | 45 ++++++++++-- 9 files changed, 298 insertions(+), 60 deletions(-) create mode 100644 arch/arm/dts/bk4r1.dts create mode 100644 configs/bk4r1_defconfig create mode 100644 include/configs/bk4r1.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f55d5b2cd74..2d3303bdaea 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -595,6 +595,10 @@ config TARGET_PCM052 bool "Support pcm-052" select CPU_V7 +config TARGET_BK4R1 + bool "Support BK4r1" + select CPU_V7 + config ARCH_ZYNQ bool "Xilinx Zynq Platform" select CPU_V7 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 19140b48ca0..efdd1ffaa55 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -278,7 +278,8 @@ dtb-$(CONFIG_MACH_SUN9I) += \ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ vf610-colibri.dtb \ vf610-twr.dtb \ - pcm052.dtb + pcm052.dtb \ + bk4r1.dtb dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb diff --git a/arch/arm/dts/bk4r1.dts b/arch/arm/dts/bk4r1.dts new file mode 100644 index 00000000000..197e5abd704 --- /dev/null +++ b/arch/arm/dts/bk4r1.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2016 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +/dts-v1/; +#include "vf.dtsi" + +/ { + model = "Phytec phyCORE-Vybrid"; + compatible = "phytec,pcm052", "fsl,vf610"; + + chosen { + stdout-path = &uart1; + }; + + aliases { + spi0 = &qspi0; + }; + +}; + +&uart1 { + status = "okay"; +}; + +&qspi0 { + bus-num = <0>; + num-cs = <2>; + status = "okay"; + + qflash0: spi_flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <108000000>; + reg = <0>; + }; + + qflash1: spi_flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <66000000>; + reg = <1>; + }; +}; diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi index d7d21a37ade..000aff260e1 100644 --- a/arch/arm/dts/vf.dtsi +++ b/arch/arm/dts/vf.dtsi @@ -83,7 +83,9 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,vf610-qspi"; - reg = <0x40044000 0x1000>; + reg = <0x40044000 0x1000>, + <0x20000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; status = "disabled"; }; diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig index 88524a34944..212f9942944 100644 --- a/board/phytec/pcm052/Kconfig +++ b/board/phytec/pcm052/Kconfig @@ -17,3 +17,23 @@ config PCM052_DDR_SIZE default 256 endif + +if TARGET_BK4R1 + +config SYS_BOARD + default "pcm052" + +config SYS_VENDOR + default "phytec" + +config SYS_SOC + default "vf610" + +config SYS_CONFIG_NAME + default "bk4r1" + +config PCM052_DDR_SIZE + int + default 512 + +endif diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 7341899015b..e75ff4fc3a3 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -152,57 +152,6 @@ static struct ddrmc_phy_setting pcm052_phy_settings[] = { int dram_init(void) { - static const struct ddr3_jedec_timings pcm052_ddr_timings = { - .tinit = 5, - .trst_pwron = 80000, - .cke_inactive = 200000, - .wrlat = 5, - .caslat_lin = 12, - .trc = 6, - .trrd = 4, - .tccd = 4, - .tbst_int_interval = 4, - .tfaw = 18, - .trp = 6, - .twtr = 4, - .tras_min = 15, - .tmrd = 4, - .trtp = 4, - .tras_max = 14040, - .tmod = 12, - .tckesr = 4, - .tcke = 3, - .trcd_int = 6, - .tras_lockout = 1, - .tdal = 10, - .bstlen = 3, - .tdll = 512, - .trp_ab = 6, - .tref = 1542, - .trfc = 64, - .tref_int = 5, - .tpdex = 3, - .txpdll = 10, - .txsnr = 68, - .txsr = 506, - .cksrx = 5, - .cksre = 5, - .freq_chg_en = 1, - .zqcl = 256, - .zqinit = 512, - .zqcs = 64, - .ref_per_zq = 64, - .zqcs_rotate = 1, - .aprebit = 10, - .cmd_age_cnt = 255, - .age_cnt = 255, - .q_fullness = 0, - .odt_rd_mapcs0 = 1, - .odt_wr_mapcs0 = 1, - .wlmrd = 40, - .wldqsen = 25, - }; - static const iomux_v3_cfg_t pcm052_pads[] = { PCM052_VF610_PAD_DDR_A15__DDR_A_15, PCM052_VF610_PAD_DDR_A14__DDR_A_14, @@ -256,11 +205,126 @@ int dram_init(void) PCM052_VF610_PAD_DDR_RESETB, }; - imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); +#if defined(CONFIG_TARGET_PCM052) + + static const struct ddr3_jedec_timings pcm052_ddr_timings = { + .tinit = 5, + .trst_pwron = 80000, + .cke_inactive = 200000, + .wrlat = 5, + .caslat_lin = 12, + .trc = 6, + .trrd = 4, + .tccd = 4, + .tbst_int_interval = 4, + .tfaw = 18, + .trp = 6, + .twtr = 4, + .tras_min = 15, + .tmrd = 4, + .trtp = 4, + .tras_max = 14040, + .tmod = 12, + .tckesr = 4, + .tcke = 3, + .trcd_int = 6, + .tras_lockout = 1, + .tdal = 10, + .bstlen = 3, + .tdll = 512, + .trp_ab = 6, + .tref = 1542, + .trfc = 64, + .tref_int = 5, + .tpdex = 3, + .txpdll = 10, + .txsnr = 68, + .txsr = 506, + .cksrx = 5, + .cksre = 5, + .freq_chg_en = 1, + .zqcl = 256, + .zqinit = 512, + .zqcs = 64, + .ref_per_zq = 64, + .zqcs_rotate = 1, + .aprebit = 10, + .cmd_age_cnt = 255, + .age_cnt = 255, + .q_fullness = 0, + .odt_rd_mapcs0 = 1, + .odt_wr_mapcs0 = 1, + .wlmrd = 40, + .wldqsen = 25, + }; ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, pcm052_phy_settings, 1, 2); +#elif defined(CONFIG_TARGET_BK4R1) + + static const struct ddr3_jedec_timings pcm052_ddr_timings = { + .tinit = 5, + .trst_pwron = 80000, + .cke_inactive = 200000, + .wrlat = 5, + .caslat_lin = 12, + .trc = 6, + .trrd = 4, + .tccd = 4, + .tbst_int_interval = 0, + .tfaw = 16, + .trp = 6, + .twtr = 4, + .tras_min = 15, + .tmrd = 4, + .trtp = 4, + .tras_max = 28080, + .tmod = 12, + .tckesr = 4, + .tcke = 3, + .trcd_int = 6, + .tras_lockout = 1, + .tdal = 12, + .bstlen = 3, + .tdll = 512, + .trp_ab = 6, + .tref = 3120, + .trfc = 104, + .tref_int = 0, + .tpdex = 3, + .txpdll = 10, + .txsnr = 108, + .txsr = 512, + .cksrx = 5, + .cksre = 5, + .freq_chg_en = 1, + .zqcl = 256, + .zqinit = 512, + .zqcs = 64, + .ref_per_zq = 64, + .zqcs_rotate = 1, + .aprebit = 10, + .cmd_age_cnt = 255, + .age_cnt = 255, + .q_fullness = 0, + .odt_rd_mapcs0 = 1, + .odt_wr_mapcs0 = 1, + .wlmrd = 40, + .wldqsen = 25, + }; + + ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, + pcm052_phy_settings, 1, 1); + +#else /* Unknown PCM052 variant */ + +#error DDR characteristics undefined for this target. Please define them. + +#endif + + imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig new file mode 100644 index 00000000000..26d9e813676 --- /dev/null +++ b/configs/bk4r1_defconfig @@ -0,0 +1,33 @@ +CONFIG_ARM=y +CONFIG_TARGET_BK4R1=y +CONFIG_DEFAULT_DEVICE_TREE="bk4r1" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND" +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_VYBRID_GPIO=y +CONFIG_NAND_VF610_NFC=y +CONFIG_SYS_NAND_BUSWIDTH_16BIT=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_CMD_DM=y +CONFIG_CMD_UBI=y diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h new file mode 100644 index 00000000000..5861eeb178a --- /dev/null +++ b/include/configs/bk4r1.h @@ -0,0 +1,33 @@ +/* + * Copyright 2016 3ADEV + * Written-by: Albert ARIBAUD + * + * Configuration settings for the phytec PCM-052 SoM-based BK4R1. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Define the BK4r1-specific env commands */ +#define PCM052_EXTRA_ENV_SETTINGS \ + "set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \ + "set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0" + +/* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/ +#define PCM052_BOOTCOMMAND "run set_gpio103; sf probe; " + +/* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */ +#define PCM052_NET_INIT "run set_gpio122; " + +/* add NOR to MTD env */ +#define MTDIDS_DEFAULT "nand0=NAND,nor0=NOR" +#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\ + ",128k(env1)"\ + ",128k(env2)"\ + ",128k(dtb)"\ + ",6144k(kernel)"\ + ",-(root);"\ + "NOR:-(nor)" + +/* now include standard PCM052 config */ + +#include "configs/pcm052.h" diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 32f958a6b25..0372e4376b0 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -52,7 +52,12 @@ #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_PARTITIONS #define CONFIG_MTD_DEVICE + +#ifndef MTDIDS_DEFAULT #define MTDIDS_DEFAULT "nand0=NAND" +#endif + +#ifndef MTDPARTS_DEFAULT #define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\ ",128k(env1)"\ ",128k(env2)"\ @@ -61,6 +66,8 @@ ",-(root)" #endif +#endif + #define CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -85,7 +92,6 @@ /* QSPI Configs*/ #ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_SYS_FSL_QSPI_LE @@ -115,8 +121,31 @@ #define CONFIG_SYS_TEXT_BASE 0x3f408000 #define CONFIG_BOARD_SIZE_LIMIT 524288 -#define CONFIG_BOOTCOMMAND "run bootcmd_sd" +/* if no target-specific extra environment settings were defined by the + target, define an empty one */ +#ifndef PCM052_EXTRA_ENV_SETTINGS +#define PCM052_EXTRA_ENV_SETTINGS +#endif + +/* if no target-specific boot command was defined by the target, + define an empty one */ +#ifndef PCM052_BOOTCOMMAND +#define PCM052_BOOTCOMMAND +#endif + +/* if no target-specific extra environment settings were defined by the + target, define an empty one */ +#ifndef PCM052_NET_INIT +#define PCM052_NET_INIT +#endif + +/* boot command, including the target-defined one if any */ +#define CONFIG_BOOTCOMMAND PCM052_BOOTCOMMAND "run bootcmd_nand" + +/* Extra env settings (including the target-defined ones if any) */ #define CONFIG_EXTRA_ENV_SETTINGS \ + PCM052_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "blimg_file=u-boot.vyb\0" \ @@ -163,7 +192,8 @@ "nand read ${kernel_addr} kernel; " \ "nand read ${ram_addr} root; " \ "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ - "update_bootloader_from_tftp=if tftp ${blimg_addr} "\ + "update_bootloader_from_tftp=" PCM052_NET_INIT \ + "if tftp ${blimg_addr} "\ "${tftpdir}${blimg_file}; then " \ "mtdparts default; " \ "nand erase.part bootloader; " \ @@ -176,7 +206,8 @@ "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \ "nand erase.part dtb; " \ "nand write ${fdt_addr} dtb ${filesize}; fi\0" \ - "update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \ + "update_kernel_from_tftp=" PCM052_NET_INIT \ + "if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \ "then setenv fdtsize ${filesize}; " \ "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \ "mtdparts default; " \ @@ -184,13 +215,15 @@ "nand write ${fdt_addr} dtb ${fdtsize}; " \ "nand erase.part kernel; " \ "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \ - "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \ + "update_rootfs_from_tftp=" PCM052_NET_INIT \ + "if tftp ${sys_addr} ${tftpdir}${filesys}; " \ "then mtdparts default; " \ "nand erase.part root; " \ "ubi part root; " \ "ubi create rootfs; " \ "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \ - "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ + "update_ramdisk_from_tftp=" PCM052_NET_INIT \ + "if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ "then mtdparts default; " \ "nand erase.part root; " \ "nand write ${ram_addr} root ${filesize}; fi\0" -- cgit v1.3.1 From 7443a1ddb19c047e5331962545ef5cbc34b5f60a Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 5 Oct 2016 15:27:07 -0700 Subject: colibri_imx7: remove legancy I2C support Remove legancy I2C config and code in favor of upcomming DM/DT enable I2C support. Signed-off-by: Stefan Agner --- board/toradex/colibri_imx7/colibri_imx7.c | 40 ------------------------------- include/configs/colibri_imx7.h | 2 -- 2 files changed, 42 deletions(-) (limited to 'include') diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 8eedd65bf07..ddb308548e2 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -12,13 +12,11 @@ #include #include #include -#include #include #include #include #include #include -#include #include #include #include @@ -38,9 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) -#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) - #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ PAD_CTL_DSE_3P3V_49OHM) @@ -48,36 +43,6 @@ DECLARE_GLOBAL_DATA_PTR; #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) -#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX7D_PAD_GPIO1_IO04__I2C1_SCL | PC, - .gpio_mode = MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | PC, - .gp = IMX_GPIO_NR(1, 4), - }, - .sda = { - .i2c_mode = MX7D_PAD_GPIO1_IO05__I2C1_SDA | PC, - .gpio_mode = MX7D_PAD_GPIO1_IO05__GPIO1_IO5 | PC, - .gp = IMX_GPIO_NR(1, 5), - }, -}; -/* I2C4 for Colibri I2C */ -static struct i2c_pads_info i2c_pad_info4 = { - .scl = { - .i2c_mode = MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL | PC, - .gpio_mode = MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 | PC, - .gp = IMX_GPIO_NR(7, 8), - }, - .sda = { - .i2c_mode = MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA | PC, - .gpio_mode = MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 | PC, - .gp = IMX_GPIO_NR(7, 9), - }, -}; -#endif - int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -331,11 +296,6 @@ int board_early_init_f(void) { setup_iomux_uart(); -#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); -#endif - return 0; } diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 16ae952f37c..55d8fcf4d42 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -59,9 +59,7 @@ #undef CONFIG_BOOTM_RTEMS /* I2C configs */ -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_IPADDR 192.168.10.2 -- cgit v1.3.1 From c571d6828d980e555ba40baf85aab45b39e118ee Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 5 Oct 2016 15:27:09 -0700 Subject: power: pmic: add Ricoh RN5T567 PMIC support Add device model enabled PMIC driver for Ricoh RN5T567 PMIC used on Colibri iMX7. Signed-off-by: Stefan Agner Reviewed-by: Simon Glass --- doc/device-tree-bindings/pmic/rn5t567.txt | 17 +++++ drivers/power/pmic/Kconfig | 8 +++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/rn5t567.c | 64 +++++++++++++++++ include/power/rn5t567_pmic.h | 113 ++++++++++++++++++++++++++++++ 5 files changed, 203 insertions(+) create mode 100644 doc/device-tree-bindings/pmic/rn5t567.txt create mode 100644 drivers/power/pmic/rn5t567.c create mode 100644 include/power/rn5t567_pmic.h (limited to 'include') diff --git a/doc/device-tree-bindings/pmic/rn5t567.txt b/doc/device-tree-bindings/pmic/rn5t567.txt new file mode 100644 index 00000000000..e9e688537c9 --- /dev/null +++ b/doc/device-tree-bindings/pmic/rn5t567.txt @@ -0,0 +1,17 @@ +Ricoh RN5T567 PMIC + +This file describes the binding info for the PMIC driver. + +Required properties: +- compatible: "ricoh,rn5t567" +- reg: depending on strapping, e.g. 0x33 + +With those two properties, the PMIC device can be used to read/write +registers. + +Example: + +rn5t567@33 { + compatible = "ricoh,rn5t567"; + reg = <0x33>; +}; diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 69f8d51885c..13d293a93d3 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -127,6 +127,14 @@ config PMIC_S5M8767 driver provides basic register access and sets up the attached regulators if regulator support is enabled. +config PMIC_RN5T567 + bool "Enable driver for Ricoh RN5T567 PMIC" + depends on DM_PMIC + ---help--- + The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO + regulators Real-Time Clock and 4 GPIOs. This driver provides + register access only. + config PMIC_TPS65090 bool "Enable driver for Texas Instruments TPS65090 PMIC" depends on DM_PMIC diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 52b4f711fbf..37d9eb55991 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o obj-$(CONFIG_PMIC_ACT8846) += act8846.o obj-$(CONFIG_PMIC_PM8916) += pm8916.o obj-$(CONFIG_PMIC_RK808) += rk808.o +obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o obj-$(CONFIG_PMIC_TPS65090) += tps65090.o obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o diff --git a/drivers/power/pmic/rn5t567.c b/drivers/power/pmic/rn5t567.c new file mode 100644 index 00000000000..001e69553e8 --- /dev/null +++ b/drivers/power/pmic/rn5t567.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2016 Toradex AG + * Stefan Agner + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +static int rn5t567_reg_count(struct udevice *dev) +{ + return RN5T567_NUM_OF_REGS; +} + +static int rn5t567_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + int ret; + + ret = dm_i2c_write(dev, reg, buff, len); + if (ret) { + debug("write error to device: %p register: %#x!", dev, reg); + return ret; + } + + return 0; +} + +static int rn5t567_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + int ret; + + ret = dm_i2c_read(dev, reg, buff, len); + if (ret) { + debug("read error from device: %p register: %#x!", dev, reg); + return ret; + } + + return 0; +} + +static struct dm_pmic_ops rn5t567_ops = { + .reg_count = rn5t567_reg_count, + .read = rn5t567_read, + .write = rn5t567_write, +}; + +static const struct udevice_id rn5t567_ids[] = { + { .compatible = "ricoh,rn5t567" }, + { } +}; + +U_BOOT_DRIVER(pmic_rn5t567) = { + .name = "rn5t567 pmic", + .id = UCLASS_PMIC, + .of_match = rn5t567_ids, + .ops = &rn5t567_ops, +}; diff --git a/include/power/rn5t567_pmic.h b/include/power/rn5t567_pmic.h new file mode 100644 index 00000000000..9ce601f2ad7 --- /dev/null +++ b/include/power/rn5t567_pmic.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2016 Toradex AG + * Stefan Agner + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __RN5T567_PMIC_H_ +#define __RN5T567_PMIC_H_ + +/* RN5T567 registers */ +enum { + RN5T567_LSIVER = 0x00, + RN5T567_OTPVER = 0x01, + RN5T567_IODAC = 0x02, + RN5T567_VINDAC = 0x03, + RN5T567_OUT32KEN = 0x05, + + RN5T567_CPUCNT = 0x06, + + RN5T567_PSWR = 0x07, + RN5T567_PONHIS = 0x09, + RN5T567_POFFHIS = 0x0A, + RN5T567_WATCHDOG = 0x0B, + RN5T567_WATCHDOGCNT = 0x0C, + RN5T567_PWRFUNC = 0x0D, + RN5T567_SLPCNT = 0x0E, + RN5T567_REPCNT = 0x0F, + RN5T567_PWRONTIMSET = 0x10, + RN5T567_NOETIMSETCNT = 0x11, + RN5T567_PWRIREN = 0x12, + RN5T567_PWRIRQ = 0x13, + RN5T567_PWRMON = 0x14, + RN5T567_PWRIRSEL = 0x15, + + RN5T567_DC1_SLOT = 0x16, + RN5T567_DC2_SLOT = 0x17, + RN5T567_DC3_SLOT = 0x18, + RN5T567_DC4_SLOT = 0x19, + + RN5T567_LDO1_SLOT = 0x1B, + RN5T567_LDO2_SLOT = 0x1C, + RN5T567_LDO3_SLOT = 0x1D, + RN5T567_LDO4_SLOT = 0x1E, + RN5T567_LDO5_SLOT = 0x1F, + + RN5T567_PSO0_SLOT = 0x25, + RN5T567_PSO1_SLOT = 0x26, + RN5T567_PSO2_SLOT = 0x27, + RN5T567_PSO3_SLOT = 0x28, + + RN5T567_LDORTC1_SLOT = 0x2A, + + RN5T567_DC1CTL = 0x2C, + RN5T567_DC1CTL2 = 0x2D, + RN5T567_DC2CTL = 0x2E, + RN5T567_DC2CTL2 = 0x2F, + RN5T567_DC3CTL = 0x30, + RN5T567_DC3CTL2 = 0x31, + RN5T567_DC4CTL = 0x32, + RN5T567_DC4CTL2 = 0x33, + + RN5T567_DC1DAC = 0x36, + RN5T567_DC2DAC = 0x37, + RN5T567_DC3DAC = 0x38, + RN5T567_DC4DAC = 0x39, + + RN5T567_DC1DAC_SLP = 0x3B, + RN5T567_DC2DAC_SLP = 0x3C, + RN5T567_DC3DAC_SLP = 0x3D, + RN5T567_DC4DAC_SLP = 0x3E, + + RN5T567_DCIREN = 0x40, + RN5T567_DCIRQ = 0x41, + RN5T567_DCIRMON = 0x42, + + RN5T567_LDOEN1 = 0x44, + RN5T567_LDOEN2 = 0x45, + RN5T567_LDODIS1 = 0x46, + + RN5T567_LDO1DAC = 0x4C, + RN5T567_LDO2DAC = 0x4D, + RN5T567_LDO3DAC = 0x4E, + RN5T567_LDO4DAC = 0x4F, + RN5T567_LDO5DAC = 0x50, + + RN5T567_LDORTC1DAC = 0x56, + RN5T567_LDORTC2DAC = 0x57, + + RN5T567_LDO1DAC_SLP = 0x58, + RN5T567_LDO2DAC_SLP = 0x59, + RN5T567_LDO3DAC_SLP = 0x5A, + RN5T567_LDO4DAC_SLP = 0x5B, + RN5T567_LDO5DAC_SLP = 0x5C, + + RN5T567_IOSEL = 0x90, + RN5T567_IOOUT = 0x91, + RN5T567_GPEDGE1 = 0x92, + RN5T567_EN_GPIR = 0x94, + RN5T567_IR_GPR = 0x95, + RN5T567_IR_GPF = 0x96, + RN5T567_MON_IOIN = 0x97, + RN5T567_GPLED_FUNC = 0x98, + RN5T567_INTPOL = 0x9C, + RN5T567_INTEN = 0x9D, + RN5T567_INTMON = 0x9E, + + RN5T567_PREVINDAC = 0xB0, + RN5T567_OVTEMP = 0xBC, + + RN5T567_NUM_OF_REGS = 0xBF, +}; + +#endif -- cgit v1.3.1 From 3dddc793e0114eb7dfc68b98a4316644d4031fcb Mon Sep 17 00:00:00 2001 From: Ken Lin Date: Fri, 7 Oct 2016 10:26:56 -0400 Subject: board: ge: bx50v3: Pass video bootargs for b850v3 Due to clock source restrictions on i.MX6, certain pixel clock rates can not be supported. Hence default the resolution/frame rate during boot to a supported value by passing video bootargs 1024x768@60 for HDMI (Display Port1) and LVDS (Display Port2) on B850v3. Signed-off-by: Ken Lin Signed-off-by: Akshay Bhat --- include/configs/ge_bx50v3.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 52f096eec1a..c77fef6f24e 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -15,6 +15,7 @@ #include #include +#define BX50V3_BOOTARGS_EXTRA #if defined(CONFIG_TARGET_GE_B450V3) #define CONFIG_BOARD_NAME "General Electric B450v3" #define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b450v3.dtb" @@ -24,6 +25,9 @@ #elif defined(CONFIG_TARGET_GE_B850V3) #define CONFIG_BOARD_NAME "General Electric B850v3" #define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b850v3.dtb" +#undef BX50V3_BOOTARGS_EXTRA +#define BX50V3_BOOTARGS_EXTRA "video=DP-1:1024x768@60 " \ + "video=HDMI-A-1:1024x768@60 " #else #define CONFIG_BOARD_NAME "General Electric BA16 Generic" #define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-ba16.dtb" @@ -166,7 +170,8 @@ "echo 'U-Boot upgraded. Please reset'; " \ "fi\0" \ "setargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/${rootdev} rw rootwait cma=128M\0" \ + "root=/dev/${rootdev} rw rootwait cma=128M " \ + BX50V3_BOOTARGS_EXTRA "\0" \ "loadbootscript=" \ "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \ -- cgit v1.3.1