From 340f418acd1159588b2f0fb50561053212c4247d Mon Sep 17 00:00:00 2001 From: Eddie Cai Date: Wed, 15 Mar 2017 08:43:28 -0600 Subject: spl: Add spl_early_init() At present malloc_base/_limit/_ptr are not initialised in spl_init() when we call spl_init() in board_init_f(). This is due to a recent change aimed at avoiding overwriting the malloc area set up on some boards by spl_relocate_stack_gd(). However if CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN is not defined, we now skip setting up the memory area in spl_init() which is obviously wrong. To fix this, add a new function spl_early_init() which can be called in board_init_f(). Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit) Signed-off-by: Eddie Cai Rewrote spl_{,early_}init() to avoid duplicate code: Rewrite/expand commit message: Signed-off-by: Simon Glass Reviewed-by: Eddie Cai --- include/asm-generic/global_data.h | 1 + include/spl.h | 24 +++++++++++++++++++++--- 2 files changed, 22 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index e02863dc031..5b356dd231e 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -127,5 +127,6 @@ typedef struct global_data { #define GD_FLG_SKIP_RELOC 0x00800 /* Don't relocate */ #define GD_FLG_RECORD 0x01000 /* Record console */ #define GD_FLG_ENV_DEFAULT 0x02000 /* Default variable flag */ +#define GD_FLG_SPL_EARLY_INIT 0x04000 /* Early SPL init is done */ #endif /* __ASM_GENERIC_GBL_DATA_H */ diff --git a/include/spl.h b/include/spl.h index bde44374eac..cdd196d187c 100644 --- a/include/spl.h +++ b/include/spl.h @@ -213,11 +213,29 @@ int spl_load_image_ext_os(struct spl_image_info *spl_image, struct blk_desc *block_dev, int partition); /** - * spl_init() - Set up device tree and driver model in SPL if enabled + * spl_early_init() - Set up device tree and driver model in SPL if enabled * * Call this function in board_init_f() if you want to use device tree and - * driver model early, before board_init_r() is called. This function will - * be called from board_init_r() if not called earlier. + * driver model early, before board_init_r() is called. + * + * If this is not called, then driver model will be inactive in SPL's + * board_init_f(), and no device tree will be available. + */ +int spl_early_init(void); + +/** + * spl_init() - Set up device tree and driver model in SPL if enabled + * + * You can optionally call spl_early_init(), then optionally call spl_init(). + * This function will be called from board_init_r() if not called earlier. + * + * Both spl_early_init() and spl_init() perform a similar function except that + * the latter will not set up the malloc() area if + * CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN is enabled, since it is assumed to + * already be done by a calll to spl_relocate_stack_gd() before board_init_r() + * is reached. + * + * This function will be called from board_init_r() if not called earlier. * * If this is not called, then driver model will be inactive in SPL's * board_init_f(), and no device tree will be available. -- cgit v1.2.3 From 5ae2fd97242d4eea97aeabe8801bb8592b37a8fe Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 13 Feb 2017 17:38:56 +0800 Subject: rockchip: clk: rk3399: update driver for spl Add ddr clock setting, add rockchip_get_pmucru API, and enable of-platdata support. Signed-off-by: Kever Yang Reviewed-by: Simon Glass Added rockchip tag and fix pmuclk_init() build warning: Signed-off-by: Simon Glass --- include/dt-bindings/clock/rk3399-cru.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 0a86aec50a2..d4bdcc663fe 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -122,6 +122,10 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 +#define SCLK_USBPHY0_480M_SRC 168 +#define SCLK_USBPHY1_480M_SRC 169 +#define SCLK_DDRCLK 170 +#define SCLK_TESTOUT2 171 #define DCLK_VOP0 180 #define DCLK_VOP1 181 @@ -589,13 +593,13 @@ #define SRST_P_SPI0 214 #define SRST_P_SPI1 215 #define SRST_P_SPI2 216 -#define SRST_P_SPI3 217 -#define SRST_P_SPI4 218 +#define SRST_P_SPI4 217 +#define SRST_P_SPI5 218 #define SRST_SPI0 219 #define SRST_SPI1 220 #define SRST_SPI2 221 -#define SRST_SPI3 222 -#define SRST_SPI4 223 +#define SRST_SPI4 222 +#define SRST_SPI5 223 /* cru_softrst_con14 */ #define SRST_I2S0_8CH 224 @@ -717,8 +721,8 @@ #define SRST_H_CM0S_NOC 3 #define SRST_DBG_CM0S 4 #define SRST_PO_CM0S 5 -#define SRST_P_SPI6 6 -#define SRST_SPI6 7 +#define SRST_P_SPI3 6 +#define SRST_SPI3 7 #define SRST_P_TIMER_0_1 8 #define SRST_P_TIMER_0 9 #define SRST_P_TIMER_1 10 -- cgit v1.2.3 From 27326c7ee269ff351bba8c2461e19f29d66b6a3a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Sat, 18 Feb 2017 19:46:21 +0100 Subject: dm: allow limiting pre-reloc markings to spl or tpl Right now the u-boot,dm-pre-reloc flag will make each marked node always appear in both spl and tpl. But systems needing an additional tpl might have special constraints for each, like the spl needing to be very tiny. So introduce two additional flags to mark nodes for only spl or tpl environments and introduce a function dm_fdt_pre_reloc to automate the necessary checks in code instances checking for pre-relocation flags. The behaviour of the original flag stays untouched and still marks a node for both spl and tpl. Signed-off-by: Heiko Stuebner Reviewed-by: Simon Glass Tested-by: Kever Yang --- include/dm/util.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'include') diff --git a/include/dm/util.h b/include/dm/util.h index 15daa3d19f1..32060ab30eb 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -48,4 +48,30 @@ static inline void dm_dump_devres(void) } #endif +/** + * Check if a dt node should be or was bound before relocation. + * + * Devicetree nodes can be marked as needed to be bound + * in the loader stages via special devicetree properties. + * + * Before relocation this function can be used to check if nodes + * are required in either SPL or TPL stages. + * + * After relocation and jumping into the real U-Boot binary + * it is possible to determine if a node was bound in one of + * SPL/TPL stages. + * + * There are 3 settings currently in use + * - + * - u-boot,dm-pre-reloc: legacy and indicates any of TPL or SPL + * Existing platforms only use it to indicate nodes needee in + * SPL. Should probably be replaced by u-boot,dm-spl for + * existing platforms. + * @blob: devicetree + * @offset: node offset + * + * Returns true if node is needed in SPL/TL, false otherwise. + */ +int dm_fdt_pre_reloc(const void *blob, int offset); + #endif -- cgit v1.2.3 From 7b2500babd6b9fce7ef9ae43132d42279442edc9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Sat, 18 Feb 2017 19:46:33 +0100 Subject: rockchip: rk3188: Add rk3066/rk3188 clock bindings Bring in required device clock binding files from Linux. The clock trees for rk3066 and rk3188 are largely similar, which makes them share the common parts in a shared header. While we focus on rk3188 for now, bring in both headers already for completeness sake. Signed-off-by: Heiko Stuebner Acked-by: Simon Glass Tested-by: Kever Yang --- include/dt-bindings/clock/rk3066a-cru.h | 32 ++++ include/dt-bindings/clock/rk3188-cru-common.h | 256 ++++++++++++++++++++++++++ include/dt-bindings/clock/rk3188-cru.h | 48 +++++ 3 files changed, 336 insertions(+) create mode 100644 include/dt-bindings/clock/rk3066a-cru.h create mode 100644 include/dt-bindings/clock/rk3188-cru-common.h create mode 100644 include/dt-bindings/clock/rk3188-cru.h (limited to 'include') diff --git a/include/dt-bindings/clock/rk3066a-cru.h b/include/dt-bindings/clock/rk3066a-cru.h new file mode 100644 index 00000000000..549ae6a3f3b --- /dev/null +++ b/include/dt-bindings/clock/rk3066a-cru.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H + +#include + +/* soft-reset indices */ +#define SRST_SRST1 0 +#define SRST_SRST2 1 + +#define SRST_L2MEM 18 +#define SRST_I2S0 23 +#define SRST_I2S1 24 +#define SRST_I2S2 25 +#define SRST_TIMER2 29 + +#define SRST_GPIO4 36 +#define SRST_GPIO6 38 + +#define SRST_TSADC 92 + +#define SRST_HDMI 96 +#define SRST_HDMI_APB 97 +#define SRST_CIF1 111 + +#endif diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h new file mode 100644 index 00000000000..8fc818b1d98 --- /dev/null +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H + +/* core clocks from */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define CORE_PERI 5 +#define CORE_L2C 6 +#define ARMCLK 7 + +/* sclk gates (special clocks) */ +#define SCLK_UART0 64 +#define SCLK_UART1 65 +#define SCLK_UART2 66 +#define SCLK_UART3 67 +#define SCLK_MAC 68 +#define SCLK_SPI0 69 +#define SCLK_SPI1 70 +#define SCLK_SARADC 71 +#define SCLK_SDMMC 72 +#define SCLK_SDIO 73 +#define SCLK_EMMC 74 +#define SCLK_I2S0 75 +#define SCLK_I2S1 76 +#define SCLK_I2S2 77 +#define SCLK_SPDIF 78 +#define SCLK_CIF0 79 +#define SCLK_CIF1 80 +#define SCLK_OTGPHY0 81 +#define SCLK_OTGPHY1 82 +#define SCLK_HSADC 83 +#define SCLK_TIMER0 84 +#define SCLK_TIMER1 85 +#define SCLK_TIMER2 86 +#define SCLK_TIMER3 87 +#define SCLK_TIMER4 88 +#define SCLK_TIMER5 89 +#define SCLK_TIMER6 90 +#define SCLK_JTAG 91 +#define SCLK_SMC 92 +#define SCLK_TSADC 93 + +#define DCLK_LCDC0 190 +#define DCLK_LCDC1 191 + +/* aclk gates */ +#define ACLK_DMA1 192 +#define ACLK_DMA2 193 +#define ACLK_GPS 194 +#define ACLK_LCDC0 195 +#define ACLK_LCDC1 196 +#define ACLK_GPU 197 +#define ACLK_SMC 198 +#define ACLK_CIF 199 +#define ACLK_IPP 200 +#define ACLK_RGA 201 +#define ACLK_CIF0 202 +#define ACLK_CPU 203 +#define ACLK_PERI 204 + +/* pclk gates */ +#define PCLK_GRF 320 +#define PCLK_PMU 321 +#define PCLK_TIMER0 322 +#define PCLK_TIMER1 323 +#define PCLK_TIMER2 324 +#define PCLK_TIMER3 325 +#define PCLK_PWM01 326 +#define PCLK_PWM23 327 +#define PCLK_SPI0 328 +#define PCLK_SPI1 329 +#define PCLK_SARADC 330 +#define PCLK_WDT 331 +#define PCLK_UART0 332 +#define PCLK_UART1 333 +#define PCLK_UART2 334 +#define PCLK_UART3 335 +#define PCLK_I2C0 336 +#define PCLK_I2C1 337 +#define PCLK_I2C2 338 +#define PCLK_I2C3 339 +#define PCLK_I2C4 340 +#define PCLK_GPIO0 341 +#define PCLK_GPIO1 342 +#define PCLK_GPIO2 343 +#define PCLK_GPIO3 344 +#define PCLK_GPIO4 345 +#define PCLK_GPIO6 346 +#define PCLK_EFUSE 347 +#define PCLK_TZPC 348 +#define PCLK_TSADC 349 +#define PCLK_CPU 350 +#define PCLK_PERI 351 +#define PCLK_DDRUPCTL 352 +#define PCLK_PUBL 353 + +/* hclk gates */ +#define HCLK_SDMMC 448 +#define HCLK_SDIO 449 +#define HCLK_EMMC 450 +#define HCLK_OTG0 451 +#define HCLK_EMAC 452 +#define HCLK_SPDIF 453 +#define HCLK_I2S0 454 +#define HCLK_I2S1 455 +#define HCLK_I2S2 456 +#define HCLK_OTG1 457 +#define HCLK_HSIC 458 +#define HCLK_HSADC 459 +#define HCLK_PIDF 460 +#define HCLK_LCDC0 461 +#define HCLK_LCDC1 462 +#define HCLK_ROM 463 +#define HCLK_CIF0 464 +#define HCLK_IPP 465 +#define HCLK_RGA 466 +#define HCLK_NANDC0 467 +#define HCLK_CPU 468 +#define HCLK_PERI 469 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_MCORE 2 +#define SRST_CORE0 3 +#define SRST_CORE1 4 +#define SRST_MCORE_DBG 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE0_WDT 12 +#define SRST_CORE1_WDT 13 +#define SRST_STRC_SYS 14 +#define SRST_L2C 15 + +#define SRST_CPU_AHB 17 +#define SRST_AHB2APB 19 +#define SRST_DMA1 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_SPDIF 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_EFUSE 30 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 + +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_UART3 42 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_I2C3 46 +#define SRST_I2C4 47 + +#define SRST_PWM0 48 +#define SRST_PWM1 49 +#define SRST_DAP_PO 50 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_TPIU_ATB 53 +#define SRST_PMU_APB 54 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERI_AXI 57 +#define SRST_PERI_AHB 58 +#define SRST_PERI_APB 59 +#define SRST_PERI_NIU 60 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_SMC 65 +#define SRST_MAC 66 +#define SRST_NANC0 68 +#define SRST_USBOTG0 69 +#define SRST_USBPHY0 70 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_USBPHY1 73 +#define SRST_OTGC1 74 +#define SRST_HSADC 76 +#define SRST_PIDFILTER 77 +#define SRST_DDR_MSCH 79 + +#define SRST_TZPC 80 +#define SRST_SDMMC 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_SPI1 85 +#define SRST_WDT 86 +#define SRST_SARADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_APB 89 +#define SRST_DDRCTL 90 +#define SRST_DDRCTL_APB 91 +#define SRST_DDRPUB 93 + +#define SRST_VIO0_AXI 98 +#define SRST_VIO0_AHB 99 +#define SRST_LCDC0_AXI 100 +#define SRST_LCDC0_AHB 101 +#define SRST_LCDC0_DCLK 102 +#define SRST_LCDC1_AXI 103 +#define SRST_LCDC1_AHB 104 +#define SRST_LCDC1_DCLK 105 +#define SRST_IPP_AXI 106 +#define SRST_IPP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_CIF0 110 + +#define SRST_VCODEC_AXI 112 +#define SRST_VCODEC_AHB 113 +#define SRST_VIO1_AXI 114 +#define SRST_VCODEC_CPU 115 +#define SRST_VCODEC_NIU 116 +#define SRST_GPU 120 +#define SRST_GPU_NIU 122 +#define SRST_TFUN_ATB 125 +#define SRST_TFUN_APB 126 +#define SRST_CTI4_APB 127 + +#define SRST_TPIU_APB 128 +#define SRST_TRACE 129 +#define SRST_CORE_DBG 130 +#define SRST_DBG_APB 131 +#define SRST_CTI0 132 +#define SRST_CTI0_APB 133 +#define SRST_CTI1 134 +#define SRST_CTI1_APB 135 +#define SRST_PTM_CORE0 136 +#define SRST_PTM_CORE1 137 +#define SRST_PTM0 138 +#define SRST_PTM0_ATB 139 +#define SRST_PTM1 140 +#define SRST_PTM1_ATB 141 +#define SRST_CTM 142 +#define SRST_TS 143 + +#endif diff --git a/include/dt-bindings/clock/rk3188-cru.h b/include/dt-bindings/clock/rk3188-cru.h new file mode 100644 index 00000000000..b6960b07bcf --- /dev/null +++ b/include/dt-bindings/clock/rk3188-cru.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H + +#include + +/* soft-reset indices */ +#define SRST_PTM_CORE2 0 +#define SRST_PTM_CORE3 1 +#define SRST_CORE2 5 +#define SRST_CORE3 6 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 + +#define SRST_TIMER2 16 +#define SRST_TIMER4 23 +#define SRST_I2S0 24 +#define SRST_TIMER5 25 +#define SRST_TIMER3 29 +#define SRST_TIMER6 31 + +#define SRST_PTM3 36 +#define SRST_PTM3_ATB 37 + +#define SRST_GPS 67 +#define SRST_HSICPHY 75 +#define SRST_TIMER 78 + +#define SRST_PTM2 92 +#define SRST_CORE2_WDT 94 +#define SRST_CORE3_WDT 95 + +#define SRST_PTM2_ATB 111 + +#define SRST_HSIC 117 +#define SRST_CTI2 118 +#define SRST_CTI2_APB 119 +#define SRST_GPU_BRIDGE 121 +#define SRST_CTI3 123 +#define SRST_CTI3_APB 124 + +#endif -- cgit v1.2.3 From 0a2be69fbf5e78e0174033f9bb27926a70cca9de Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Sat, 18 Feb 2017 19:46:36 +0100 Subject: rockchip: rk3188: Add core support Add the core architecture code for the rk3188. It doesn't support the SPL yet, as because of some unknown error it doesn't start yet. Signed-off-by: Heiko Stuebner Reviewed-by: Simon Glass Tested-by: Kever Yang Drop these defines from rk3188_common.h CONFIG_GENERIC_MMC, CONFIG_BOUNCE_BUFFER, CONFIG_DOS_PARTITION CONFIG_PARTITION_UUIDS, CONFIG_CMD_PART: Signed-off-by: Simon Glass --- include/configs/rk3188_common.h | 121 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 include/configs/rk3188_common.h (limited to 'include') diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h new file mode 100644 index 00000000000..445b2da496c --- /dev/null +++ b/include/configs/rk3188_common.h @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3188_COMMON_H +#define __CONFIG_RK3188_COMMON_H + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#include +#include "rockchip-common.h" + +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_THUMB_BUILD + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) +#define CONFIG_SYS_TIMER_COUNTS_DOWN + +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SPL_BOARD_INIT + +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x60100000 +#endif +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 + +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) +#define CONFIG_ROCKCHIP_CHIP_TAG "RK31" + +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_TEXT_BASE 0x10080804 +/* tpl size 1kb - 4byte RK31 header */ +#define CONFIG_SPL_MAX_SIZE (0x400 - 0x4) +#elif defined(CONFIG_SPL_BUILD) +/* spl size 32kb sram - 2kb bootrom - 1kb spl */ +#define CONFIG_SPL_MAX_SIZE (0x8000 - 0xC00) +#define CONFIG_SPL_TEXT_BASE 0x10080C00 +#define CONFIG_SPL_FRAMEWORK 1 +#define CONFIG_SPL_CLK 1 +#define CONFIG_SPL_PINCTRL 1 +#define CONFIG_SPL_REGMAP 1 +#define CONFIG_SPL_SYSCON 1 +#define CONFIG_SPL_RAM 1 +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1 +#define CONFIG_ROCKCHIP_SERIAL 1 +#endif + +#define CONFIG_SPL_STACK 0x10087fff + +/* MMC/SD IP block */ +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_FAT_WRITE + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#ifndef CONFIG_SPL_BUILD +/* usb otg */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_DWC2_OTG +#define CONFIG_ROCKCHIP_USB2_PHY +#define CONFIG_USB_GADGET_VBUS_DRAW 0 + +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_G_DNL_MANUFACTURER "Rockchip" +#define CONFIG_G_DNL_VENDOR_NUM 0x2207 +#define CONFIG_G_DNL_PRODUCT_NUM 0x310a + +/* usb host support */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX +#endif +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "pxefile_addr_r=0x60100000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include + +/* Linux fails to load the fdt if it's loaded above 256M on a Rock board, + * so limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x6fffffff\0" \ + "initrd_high=0x6fffffff\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV + +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_PREBOOT + +#endif -- cgit v1.2.3 From 26d5ee8f9b29e06272f8bab052b12df90fe7b6f8 Mon Sep 17 00:00:00 2001 From: Eddie Cai Date: Mon, 20 Feb 2017 11:08:16 +0800 Subject: rockchip: tinker: configs: use correct mmc instance as boot target device We are using wrong mmc instance as boot target device now. below Jaehoon Chung's patch use mmc alias which correct it. That make tinker board can not find mmc device. So give it correct mmc device instance. commit 02ad33aa3a84821c8d9a6c4f167f143f6248b084 Author: Jaehoon Chung Date: Thu Feb 2 13:41:14 2017 +0900 mmc: mmc-uclass: use the fixed devnum with alias node Signed-off-by: Eddie Cai Acked-by: Simon Glass --- include/configs/tinker_rk3288.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h index 860eb404fbf..c398e072d2c 100644 --- a/include/configs/tinker_rk3288.h +++ b/include/configs/tinker_rk3288.h @@ -13,7 +13,7 @@ #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) + func(MMC, mmc, 1) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 -- cgit v1.2.3 From 3012a840ed8fcec405dd401bb826c9e0bf442222 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 23 Feb 2017 16:09:05 +0800 Subject: rockchip: arm64: rk3399: add SPL support Add SPL support for rk3399, default with of-platdata enabled. Signed-off-by: Kever Yang Reviewed-by: Simon Glass Drop Kconfig changes to fix build error: Signed-off-by: Simon Glass --- include/configs/rk3399_common.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index ce64476c2ec..6921f68068e 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -22,6 +22,12 @@ #define CONFIG_SYS_TEXT_BASE 0x00200000 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0xff8effff +#define CONFIG_SPL_TEXT_BASE 0xff8c2008 +#define CONFIG_SPL_MAX_SIZE 0x30000 +/* BSS setup */ +#define CONFIG_SPL_BSS_START_ADDR 0xff8e0000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ -- cgit v1.2.3 From 66e87cc842e1a57cb2d666966fd9b250ca2f6e05 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 22 Feb 2017 16:56:38 +0800 Subject: rockchip: config: rk3399: enable SPL config for evb-rk3399 Enable all the CONFIGs which need by SPL. Signed-off-by: Kever Yang Reviewed-by: Simon Glass Added rockchip tag: Drop CONFIG_ROCKCHIP_DWMMC for now due to build error: Move changes to arch/arm/mach-rockchip/Kconfig to this patch: Signed-off-by: Simon Glass --- include/configs/rk3399_common.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 6921f68068e..eb383764fe3 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -16,6 +16,11 @@ #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SYS_NS16550_MEM32 -- cgit v1.2.3 From e94ffee335f23d86cad0f8816b049bb4100d5be3 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 23 Feb 2017 15:37:50 +0800 Subject: rockchip: rk3328: add device tree file Add dts binding header for rk3328, files origin from kernel. Signed-off-by: William Zhang Signed-off-by: Kever Yang Acked-by: Simon Glass --- include/dt-bindings/clock/rk3328-cru.h | 394 +++++++++++++++++++++++++++++++++ include/dt-bindings/pinctrl/rockchip.h | 2 + 2 files changed, 396 insertions(+) create mode 100644 include/dt-bindings/clock/rk3328-cru.h (limited to 'include') diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h new file mode 100644 index 00000000000..6d8bf1330ba --- /dev/null +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -0,0 +1,394 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_NPLL 5 +#define ARMCLK 6 + +/* sclk gates (special clocks) */ +#define SCLK_RTC32K 30 +#define SCLK_SDMMC_EXT 31 +#define SCLK_SPI 32 +#define SCLK_SDMMC 33 +#define SCLK_SDIO 34 +#define SCLK_EMMC 35 +#define SCLK_TSADC 36 +#define SCLK_SARADC 37 +#define SCLK_UART0 38 +#define SCLK_UART1 39 +#define SCLK_UART2 40 +#define SCLK_I2S0 41 +#define SCLK_I2S1 42 +#define SCLK_I2S2 43 +#define SCLK_I2S1_OUT 44 +#define SCLK_I2S2_OUT 45 +#define SCLK_SPDIF 46 +#define SCLK_TIMER0 47 +#define SCLK_TIMER1 48 +#define SCLK_TIMER2 49 +#define SCLK_TIMER3 50 +#define SCLK_TIMER4 51 +#define SCLK_TIMER5 52 +#define SCLK_WIFI 53 +#define SCLK_CIF_OUT 54 +#define SCLK_I2C0 55 +#define SCLK_I2C1 56 +#define SCLK_I2C2 57 +#define SCLK_I2C3 58 +#define SCLK_CRYPTO 59 +#define SCLK_PWM 60 +#define SCLK_PDM 61 +#define SCLK_EFUSE 62 +#define SCLK_OTP 63 +#define SCLK_DDRCLK 64 +#define SCLK_VDEC_CABAC 65 +#define SCLK_VDEC_CORE 66 +#define SCLK_VENC_DSP 67 +#define SCLK_VENC_CORE 68 +#define SCLK_RGA 69 +#define SCLK_HDMI_SFC 70 +#define SCLK_HDMI_CEC 71 +#define SCLK_USB3_REF 72 +#define SCLK_USB3_SUSPEND 73 +#define SCLK_SDMMC_DRV 74 +#define SCLK_SDIO_DRV 75 +#define SCLK_EMMC_DRV 76 +#define SCLK_SDMMC_EXT_DRV 77 +#define SCLK_SDMMC_SAMPLE 78 +#define SCLK_SDIO_SAMPLE 79 +#define SCLK_EMMC_SAMPLE 80 +#define SCLK_SDMMC_EXT_SAMPLE 81 +#define SCLK_VOP 82 +#define SCLK_MAC2PHY_RXTX 83 +#define SCLK_MAC2PHY_SRC 84 +#define SCLK_MAC2PHY_REF 85 +#define SCLK_MAC2PHY_OUT 86 +#define SCLK_MAC2IO_RX 87 +#define SCLK_MAC2IO_TX 88 +#define SCLK_MAC2IO_REFOUT 89 +#define SCLK_MAC2IO_REF 90 +#define SCLK_MAC2IO_OUT 91 +#define SCLK_TSP 92 +#define SCLK_HSADC_TSP 93 +#define SCLK_USB3PHY_REF 94 +#define SCLK_REF_USB3OTG 95 +#define SCLK_USB3OTG_REF 96 +#define SCLK_USB3OTG_SUSPEND 97 +#define SCLK_REF_USB3OTG_SRC 98 +#define SCLK_MAC2IO_SRC 99 + +/* dclk gates */ +#define DCLK_LCDC 180 +#define DCLK_HDMIPHY 181 +#define HDMIPHY 182 +#define USB480M 183 +#define DCLK_LCDC_SRC 184 + +/* aclk gates */ +#define ACLK_AXISRAM 190 +#define ACLK_VOP_PRE 191 +#define ACLK_USB3OTG 192 +#define ACLK_RGA_PRE 193 +#define ACLK_DMAC 194 +#define ACLK_GPU 195 +#define ACLK_BUS_PRE 196 +#define ACLK_PERI_PRE 197 +#define ACLK_RKVDEC_PRE 198 +#define ACLK_RKVDEC 199 +#define ACLK_RKVENC 200 +#define ACLK_VPU_PRE 201 +#define ACLK_VIO_PRE 202 +#define ACLK_VPU 203 +#define ACLK_VIO 204 +#define ACLK_VOP 205 +#define ACLK_GMAC 206 +#define ACLK_H265 207 +#define ACLK_H264 208 +#define ACLK_MAC2PHY 209 +#define ACLK_MAC2IO 210 +#define ACLK_DCF 211 +#define ACLK_TSP 212 +#define ACLK_PERI 213 +#define ACLK_RGA 214 +#define ACLK_IEP 215 +#define ACLK_CIF 216 +#define ACLK_HDCP 217 + +/* pclk gates */ +#define PCLK_GPIO0 300 +#define PCLK_GPIO1 301 +#define PCLK_GPIO2 302 +#define PCLK_GPIO3 303 +#define PCLK_GRF 304 +#define PCLK_I2C0 305 +#define PCLK_I2C1 306 +#define PCLK_I2C2 307 +#define PCLK_I2C3 308 +#define PCLK_SPI 309 +#define PCLK_UART0 310 +#define PCLK_UART1 311 +#define PCLK_UART2 312 +#define PCLK_TSADC 313 +#define PCLK_PWM 314 +#define PCLK_TIMER 315 +#define PCLK_BUS_PRE 316 +#define PCLK_PERI_PRE 317 +#define PCLK_HDMI_CTRL 318 +#define PCLK_HDMI_PHY 319 +#define PCLK_GMAC 320 +#define PCLK_H265 321 +#define PCLK_MAC2PHY 322 +#define PCLK_MAC2IO 323 +#define PCLK_USB3PHY_OTG 324 +#define PCLK_USB3PHY_PIPE 325 +#define PCLK_USB3_GRF 326 +#define PCLK_USB2_GRF 327 +#define PCLK_HDMIPHY 328 +#define PCLK_DDR 329 +#define PCLK_PERI 330 +#define PCLK_HDMI 331 +#define PCLK_HDCP 332 +#define PCLK_DCF 333 +#define PCLK_SARADC 334 + +/* hclk gates */ +#define HCLK_PERI 408 +#define HCLK_TSP 409 +#define HCLK_GMAC 410 +#define HCLK_I2S0_8CH 411 +#define HCLK_I2S1_8CH 413 +#define HCLK_I2S2_2CH 413 +#define HCLK_SPDIF_8CH 414 +#define HCLK_VOP 415 +#define HCLK_NANDC 416 +#define HCLK_SDMMC 417 +#define HCLK_SDIO 418 +#define HCLK_EMMC 419 +#define HCLK_SDMMC_EXT 420 +#define HCLK_RKVDEC_PRE 421 +#define HCLK_RKVDEC 422 +#define HCLK_RKVENC 423 +#define HCLK_VPU_PRE 424 +#define HCLK_VIO_PRE 425 +#define HCLK_VPU 426 +#define HCLK_VIO 427 +#define HCLK_BUS_PRE 428 +#define HCLK_PERI_PRE 429 +#define HCLK_H264 430 +#define HCLK_CIF 431 +#define HCLK_OTG_PMU 432 +#define HCLK_OTG 433 +#define HCLK_HOST0 434 +#define HCLK_HOST0_ARB 435 +#define HCLK_CRYPTO_MST 436 +#define HCLK_CRYPTO_SLV 437 +#define HCLK_PDM 438 +#define HCLK_IEP 439 +#define HCLK_RGA 440 +#define HCLK_HDCP 441 + +#define CLK_NR_CLKS (HCLK_HDCP + 1) + +#define SCLK_MAC2IO 0 +#define SCLK_MAC2PHY 1 + +#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NIU 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +#define SRST_A53_GIC 18 +#define SRST_DAP 19 +#define SRST_PMU_P 21 +#define SRST_EFUSE 22 +#define SRST_BUSSYS_H 23 +#define SRST_BUSSYS_P 24 +#define SRST_SPDIF 25 +#define SRST_INTMEM 26 +#define SRST_ROM 27 +#define SRST_GPIO0 28 +#define SRST_GPIO1 29 +#define SRST_GPIO2 30 +#define SRST_GPIO3 31 + +#define SRST_I2S0 32 +#define SRST_I2S1 33 +#define SRST_I2S2 34 +#define SRST_I2S0_H 35 +#define SRST_I2S1_H 36 +#define SRST_I2S2_H 37 +#define SRST_UART0 38 +#define SRST_UART1 39 +#define SRST_UART2 40 +#define SRST_UART0_P 41 +#define SRST_UART1_P 42 +#define SRST_UART2_P 43 +#define SRST_I2C0 44 +#define SRST_I2C1 45 +#define SRST_I2C2 46 +#define SRST_I2C3 47 + +#define SRST_I2C0_P 48 +#define SRST_I2C1_P 49 +#define SRST_I2C2_P 50 +#define SRST_I2C3_P 51 +#define SRST_EFUSE_SE_P 52 +#define SRST_EFUSE_NS_P 53 +#define SRST_PWM0 54 +#define SRST_PWM0_P 55 +#define SRST_DMA 56 +#define SRST_TSP_A 57 +#define SRST_TSP_H 58 +#define SRST_TSP 59 +#define SRST_TSP_HSADC 60 +#define SRST_DCF_A 61 +#define SRST_DCF_P 62 + +#define SRST_SCR 64 +#define SRST_SPI 65 +#define SRST_TSADC 66 +#define SRST_TSADC_P 67 +#define SRST_CRYPTO 68 +#define SRST_SGRF 69 +#define SRST_GRF 70 +#define SRST_USB_GRF 71 +#define SRST_TIMER_6CH_P 72 +#define SRST_TIMER0 73 +#define SRST_TIMER1 74 +#define SRST_TIMER2 75 +#define SRST_TIMER3 76 +#define SRST_TIMER4 77 +#define SRST_TIMER5 78 +#define SRST_USB3GRF 79 + +#define SRST_PHYNIU 80 +#define SRST_HDMIPHY 81 +#define SRST_VDAC 82 +#define SRST_ACODEC_p 83 +#define SRST_SARADC 85 +#define SRST_SARADC_P 86 +#define SRST_GRF_DDR 87 +#define SRST_DFIMON 88 +#define SRST_MSCH 89 +#define SRST_DDRMSCH 91 +#define SRST_DDRCTRL 92 +#define SRST_DDRCTRL_P 93 +#define SRST_DDRPHY 94 +#define SRST_DDRPHY_P 95 + +#define SRST_GMAC_NIU_A 96 +#define SRST_GMAC_NIU_P 97 +#define SRST_GMAC2PHY_A 98 +#define SRST_GMAC2IO_A 99 +#define SRST_MACPHY 100 +#define SRST_OTP_PHY 101 +#define SRST_GPU_A 102 +#define SRST_GPU_NIU_A 103 +#define SRST_SDMMCEXT 104 +#define SRST_PERIPH_NIU_A 105 +#define SRST_PERIHP_NIU_H 106 +#define SRST_PERIHP_P 107 +#define SRST_PERIPHSYS_H 108 +#define SRST_MMC0 109 +#define SRST_SDIO 110 +#define SRST_EMMC 111 + +#define SRST_USB2OTG_H 112 +#define SRST_USB2OTG 113 +#define SRST_USB2OTG_ADP 114 +#define SRST_USB2HOST_H 115 +#define SRST_USB2HOST_ARB 116 +#define SRST_USB2HOST_AUX 117 +#define SRST_USB2HOST_EHCIPHY 118 +#define SRST_USB2HOST_UTMI 119 +#define SRST_USB3OTG 120 +#define SRST_USBPOR 121 +#define SRST_USB2OTG_UTMI 122 +#define SRST_USB2HOST_PHY_UTMI 123 +#define SRST_USB3OTG_UTMI 124 +#define SRST_USB3PHY_U2 125 +#define SRST_USB3PHY_U3 126 +#define SRST_USB3PHY_PIPE 127 + +#define SRST_VIO_A 128 +#define SRST_VIO_BUS_H 129 +#define SRST_VIO_H2P_H 130 +#define SRST_VIO_ARBI_H 131 +#define SRST_VOP_NIU_A 132 +#define SRST_VOP_A 133 +#define SRST_VOP_H 134 +#define SRST_VOP_D 135 +#define SRST_RGA 136 +#define SRST_RGA_NIU_A 137 +#define SRST_RGA_A 138 +#define SRST_RGA_H 139 +#define SRST_IEP_A 140 +#define SRST_IEP_H 141 +#define SRST_HDMI 142 +#define SRST_HDMI_P 143 + +#define SRST_HDCP_A 144 +#define SRST_HDCP 145 +#define SRST_HDCP_H 146 +#define SRST_CIF_A 147 +#define SRST_CIF_H 148 +#define SRST_CIF_P 149 +#define SRST_OTP_P 150 +#define SRST_OTP_SBPI 151 +#define SRST_OTP_USER 152 +#define SRST_DDRCTRL_A 153 +#define SRST_DDRSTDY_P 154 +#define SRST_DDRSTDY 155 +#define SRST_PDM_H 156 +#define SRST_PDM 157 +#define SRST_USB3PHY_OTG_P 158 +#define SRST_USB3PHY_PIPE_P 159 + +#define SRST_VCODEC_A 160 +#define SRST_VCODEC_NIU_A 161 +#define SRST_VCODEC_H 162 +#define SRST_VCODEC_NIU_H 163 +#define SRST_VDEC_A 164 +#define SRST_VDEC_NIU_A 165 +#define SRST_VDEC_H 166 +#define SRST_VDEC_NIU_H 167 +#define SRST_VDEC_CORE 168 +#define SRST_VDEC_CABAC 169 +#define SRST_DDRPHYDIV 175 + +#define SRST_RKVENC_NIU_A 176 +#define SRST_RKVENC_NIU_H 177 +#define SRST_RKVENC_H265_A 178 +#define SRST_RKVENC_H265_P 179 +#define SRST_RKVENC_H265_CORE 180 +#define SRST_RKVENC_H265_DSP 181 +#define SRST_RKVENC_H264_A 182 +#define SRST_RKVENC_H264_H 183 +#define SRST_RKVENC_INTMEM 184 + +#endif diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h index 56887e14b5a..ecb76c7808a 100644 --- a/include/dt-bindings/pinctrl/rockchip.h +++ b/include/dt-bindings/pinctrl/rockchip.h @@ -22,5 +22,7 @@ #define RK_FUNC_2 2 #define RK_FUNC_3 3 #define RK_FUNC_4 4 +#define RK_FUNC_5 5 +#define RK_FUNC_6 6 #endif -- cgit v1.2.3 From 85a3cfb80aeda3500e32816f2d9c9ec66bf3b50e Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 23 Feb 2017 15:37:51 +0800 Subject: rockchip: rk3328: add soc basic support RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU. It supports two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-16MB range. Signed-off-by: William Zhang Signed-off-by: Kever Yang Acked-by: Simon Glass Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass --- include/configs/rk3328_common.h | 65 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 include/configs/rk3328_common.h (limited to 'include') diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h new file mode 100644 index 00000000000..eacf716d553 --- /dev/null +++ b/include/configs/rk3328_common.h @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3328_COMMON_H +#define __CONFIG_RK3328_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 1500000 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x00200000 +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +/* MMC/SD IP block */ +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_SUPPORT_VFAT +#define CONFIG_FS_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_FS_EXT4 + +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) + +/* FAT sd card locations. */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x04000000\0" + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "partitions=" PARTS_DEFAULT \ + BOOTENV + +#endif + +#endif -- cgit v1.2.3 From 625ec503cbec04b2e687490123a65f19a78632c6 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 23 Feb 2017 15:37:55 +0800 Subject: rockchip: rk3328: add evb-rk3328 support evb-rk3328 is an evb from Rockchip based on rk3328 SoC: - 2 USB2.0 Host port; - 1 USB3.0 Host port; - 1 HDMI port; - 2 10/100M eth port; - 2GB ddr; - 16GB eMMC; - UART to USB debug port; Signed-off-by: William Zhang Signed-off-by: Kever Yang Acked-by: Simon Glass --- include/configs/evb_rk3328.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 include/configs/evb_rk3328.h (limited to 'include') diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h new file mode 100644 index 00000000000..3a39a1bffe5 --- /dev/null +++ b/include/configs/evb_rk3328.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EVB_RK3328_H +#define __EVB_RK3328_H + +#include + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +/* + * SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) + +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif -- cgit v1.2.3 From d905cf7365ad25c55129ce6bc473b67a642d7817 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Thu, 23 Feb 2017 17:30:38 +0100 Subject: dm: Return actual bools in dm_fdt_pre_reloc Documentation says that we're returning true/false, not 1/0 so adapt the function to return actual booleans. Signed-off-by: Heiko Stuebner Acked-by: Simon Glass --- include/dm/util.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/dm/util.h b/include/dm/util.h index 32060ab30eb..45529ce0e6a 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -72,6 +72,6 @@ static inline void dm_dump_devres(void) * * Returns true if node is needed in SPL/TL, false otherwise. */ -int dm_fdt_pre_reloc(const void *blob, int offset); +bool dm_fdt_pre_reloc(const void *blob, int offset); #endif -- cgit v1.2.3 From 0e27248388a010b38858bdd592fa38f8b0c46e32 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Thu, 23 Feb 2017 17:30:40 +0100 Subject: rockchip: rk3188: drop CONFIG_SYS_NO_FLASH Commit e856bdcfb492 ("flash: complete CONFIG_SYS_NO_FLASH move with renaming") obsoleted the CONFIG_SYS_NO_FLASH option, which still is in our rk3188_common.h header, resulting in warnings like The following new ad-hoc CONFIG options were detected: CONFIG_SYS_NO_FLASH So also drop it from the rk3188 header. Signed-off-by: Heiko Stuebner Acked-by: Simon Glass --- include/configs/rk3188_common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 445b2da496c..2ff7cd7b70c 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -13,7 +13,6 @@ #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY -#define CONFIG_SYS_NO_FLASH #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MAXARGS 16 -- cgit v1.2.3