From e69a1fed16ad326457dc2b2f4ad8089b4ac96dd1 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 3 Aug 2024 10:40:35 +0200 Subject: clk: mediatek: mt7986: rename CB_CKSQ_40M to TOP_XTAL Upstream kernel linux clock include use TOP_XTAL instead of CB_CKSQ_40M. Rename this clock to the upstream kernel in preparation for support of OF_UPSTREAM. Signed-off-by: Christian Marangi --- include/dt-bindings/clock/mt7986-clk.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index 820f8631831..30720f9fb42 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -51,7 +51,7 @@ /* TOPCKGEN */ -#define CK_TOP_CB_CKSQ_40M 0 +#define CK_TOP_XTAL 0 #define CK_TOP_CB_M_416M 1 #define CK_TOP_CB_M_D2 2 #define CK_TOP_CB_M_D4 3 @@ -79,7 +79,7 @@ #define CK_TOP_CB_WEDMCU_760M 25 #define CK_TOP_WEDMCU_D5_D2 26 #define CK_TOP_CB_SGM_325M 27 -#define CK_TOP_CB_CKSQ_40M_D2 28 +#define CK_TOP_XTAL_D2 28 #define CK_TOP_CB_RTC_32K 29 #define CK_TOP_CB_RTC_32P7K 30 #define CK_TOP_NFI1X 31 -- cgit v1.2.3 From 5e4ee4b354717de295fc3d57077ce5ce9ed79059 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 3 Aug 2024 10:40:36 +0200 Subject: clk: mediatek: mt7986: rename 66M_MCK to SYSAXI_D2 Upstream kernel linux clock include use SYSAXI_D2 instead of 66M_MCK. Rename this clock to the upstream kernel in preparation for support of OF_UPSTREAM. Signed-off-by: Christian Marangi --- include/dt-bindings/clock/mt7986-clk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index 30720f9fb42..f45ef7afcc6 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -16,7 +16,7 @@ #define CK_INFRA_I2C 3 #define CK_INFRA_ISPI1 4 #define CK_INFRA_PWM 5 -#define CK_INFRA_66M_MCK 6 +#define CK_INFRA_SYSAXI_D2 6 #define CK_INFRA_CK_F32K 7 #define CK_INFRA_PCIE_CK 8 #define CK_INFRA_PWM_BCK 9 -- cgit v1.2.3 From 6df8029c9e744dcacfdde784c7aa556e3bfa331b Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 3 Aug 2024 10:40:38 +0200 Subject: clk: mediatek: mt7986: drop 1/1 infracfg spurious factor Now that we can have advanced parent handling for mux, we can drop spurious infracfg 1/1 factor. This is in preparation to make the clk ID match the ID in upstream include for mt7986. Drop the factor entry from mt7986-clk.h and reference to them in mt7981.dtsi. Muxes and gates are updated to reference the topckgen clk following how it's done in upstream kernel linux. Add relevant clk type flag in clk_tree for infracfg and topckgen. Signed-off-by: Christian Marangi --- include/dt-bindings/clock/mt7986-clk.h | 40 ++-------------------------------- 1 file changed, 2 insertions(+), 38 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index f45ef7afcc6..dbae389858a 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -10,44 +10,8 @@ /* INFRACFG */ -#define CK_INFRA_CK_F26M 0 -#define CK_INFRA_UART 1 -#define CK_INFRA_ISPI0 2 -#define CK_INFRA_I2C 3 -#define CK_INFRA_ISPI1 4 -#define CK_INFRA_PWM 5 -#define CK_INFRA_SYSAXI_D2 6 -#define CK_INFRA_CK_F32K 7 -#define CK_INFRA_PCIE_CK 8 -#define CK_INFRA_PWM_BCK 9 -#define CK_INFRA_PWM_CK1 10 -#define CK_INFRA_PWM_CK2 11 -#define CK_INFRA_133M_HCK 12 -#define CK_INFRA_EIP_CK 13 -#define CK_INFRA_66M_PHCK 14 -#define CK_INFRA_FAUD_L_CK 15 -#define CK_INFRA_FAUD_AUD_CK 17 -#define CK_INFRA_FAUD_EG2_CK 17 -#define CK_INFRA_I2CS_CK 18 -#define CK_INFRA_MUX_UART0 19 -#define CK_INFRA_MUX_UART1 20 -#define CK_INFRA_MUX_UART2 21 -#define CK_INFRA_NFI_CK 22 -#define CK_INFRA_SPINFI_CK 23 -#define CK_INFRA_MUX_SPI0 24 -#define CK_INFRA_MUX_SPI1 25 -#define CK_INFRA_RTC_32K 26 -#define CK_INFRA_FMSDC_CK 27 -#define CK_INFRA_FMSDC_HCK_CK 28 -#define CK_INFRA_PERI_133M 29 -#define CK_INFRA_133M_PHCK 30 -#define CK_INFRA_USB_SYS_CK 31 -#define CK_INFRA_USB_CK 32 -#define CK_INFRA_USB_XHCI_CK 33 -#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34 -#define CK_INFRA_F26M_CK0 35 -#define CK_INFRA_HD_133M 36 -#define CLK_INFRA_NR_CLK 37 +#define CK_INFRA_SYSAXI_D2 0 +#define CLK_INFRA_NR_CLK 1 /* TOPCKGEN */ -- cgit v1.2.3 From a6c0761f65096850536c95cb9eb54d560f2173f5 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 3 Aug 2024 10:40:39 +0200 Subject: clk: mediatek: mt7986: add missing entry for IPCIE_PIPE_CK infra gate Add missing entry for IPCIE_PIPE_CK infra gate clock. Renumber the clock order to match the expected offset in the gate array. Signed-off-by: Christian Marangi --- include/dt-bindings/clock/mt7986-clk.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index dbae389858a..16faca5fef8 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -167,9 +167,10 @@ #define CK_INFRA_IUSB_SYS_CK 40 #define CK_INFRA_IUSB_CK 41 #define CK_INFRA_IPCIE_CK 42 -#define CK_INFRA_IPCIER_CK 43 -#define CK_INFRA_IPCIEB_CK 44 -#define CLK_INFRA_AO_NR_CLK 45 +#define CK_INFRA_IPCIE_PIPE_CK 43 +#define CK_INFRA_IPCIER_CK 44 +#define CK_INFRA_IPCIEB_CK 45 +#define CLK_INFRA_AO_NR_CLK 46 /* APMIXEDSYS */ -- cgit v1.2.3 From b87f40fb7e165c6643853a86e7f71a48a83f8d80 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 3 Aug 2024 10:40:40 +0200 Subject: clk: mediatek: mt7986: fix typo for infra_i2c0_ck Fix a typo for infra_i2c0_ck where 0 was misspelled as O. Signed-off-by: Christian Marangi --- include/dt-bindings/clock/mt7986-clk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index 16faca5fef8..a48d57512d1 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -142,7 +142,7 @@ #define CK_INFRA_SEJ_CK 15 #define CK_INFRA_SEJ_13M_CK 16 #define CK_INFRA_THERM_CK 17 -#define CK_INFRA_I2CO_CK 18 +#define CK_INFRA_I2C0_CK 18 #define CK_INFRA_TRNG_CK 19 #define CK_INFRA_UART0_CK 20 #define CK_INFRA_UART1_CK 21 -- cgit v1.2.3 From 1062187a4b614bdda7a124afec9b4dcc879af5b2 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 3 Aug 2024 10:40:41 +0200 Subject: clk: mediatek: mt7986: rename TOPCKGEN factor clock to upstream naming Rename TOPCKGEN factor clock to upstream neaming. Upstream kernel linux reference the factor clock for apmixedpll with the "pll" suffix. Align the naming to the upstream naming format in preparation for OF_UPSTREAM support. Also rename rtc clock to drop the CB_ as upstream doesn't have that. Signed-off-by: Christian Marangi --- include/dt-bindings/clock/mt7986-clk.h | 54 +++++++++++++++++----------------- 1 file changed, 27 insertions(+), 27 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index a48d57512d1..f19948cca16 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -16,36 +16,36 @@ /* TOPCKGEN */ #define CK_TOP_XTAL 0 -#define CK_TOP_CB_M_416M 1 -#define CK_TOP_CB_M_D2 2 -#define CK_TOP_CB_M_D4 3 -#define CK_TOP_CB_M_D8 4 -#define CK_TOP_M_D8_D2 5 -#define CK_TOP_M_D3_D2 6 -#define CK_TOP_CB_MM_D2 7 -#define CK_TOP_CB_MM_D4 8 -#define CK_TOP_CB_MM_D8 9 -#define CK_TOP_MM_D8_D2 10 -#define CK_TOP_MM_D3_D8 11 -#define CK_TOP_CB_U2_PHYD_CK 12 +#define CK_TOP_CB_MPLL_416M 1 +#define CK_TOP_MPLL_D2 2 +#define CK_TOP_MPLL_D4 3 +#define CK_TOP_MPLL_D8 4 +#define CK_TOP_MPLL_D8_D2 5 +#define CK_TOP_MPLL_D3_D2 6 +#define CK_TOP_MMPLL_D2 7 +#define CK_TOP_MMPLL_D4 8 +#define CK_TOP_MMPLL_D8 9 +#define CK_TOP_MMPLL_D8_D2 10 +#define CK_TOP_MMPLL_D3_D8 11 +#define CK_TOP_MMPLL_U2PHYD 12 #define CK_TOP_CB_APLL2_196M 13 #define CK_TOP_APLL2_D4 14 -#define CK_TOP_CB_NET1_D4 15 -#define CK_TOP_CB_NET1_D5 16 -#define CK_TOP_NET1_D5_D2 17 -#define CK_TOP_NET1_D5_D4 18 -#define CK_TOP_NET1_D8_D2 19 -#define CK_TOP_NET1_D8_D4 20 -#define CK_TOP_CB_NET2_800M 21 -#define CK_TOP_CB_NET2_D4 22 -#define CK_TOP_NET2_D4_D2 23 -#define CK_TOP_NET2_D3_D2 24 -#define CK_TOP_CB_WEDMCU_760M 25 -#define CK_TOP_WEDMCU_D5_D2 26 -#define CK_TOP_CB_SGM_325M 27 +#define CK_TOP_NET1PLL_D4 15 +#define CK_TOP_NET1PLL_D5 16 +#define CK_TOP_NET1PLL_D5_D2 17 +#define CK_TOP_NET1PLL_D5_D4 18 +#define CK_TOP_NET1PLL_D8_D2 19 +#define CK_TOP_NET1PLL_D8_D4 20 +#define CK_TOP_CB_NET2PLL_800M 21 +#define CK_TOP_NET2PLL_D4 22 +#define CK_TOP_NET2PLL_D4_D2 23 +#define CK_TOP_NET2PLL_D3_D2 24 +#define CK_TOP_CB_WEDMCUPLL_760M 25 +#define CK_TOP_WEDMCUPLL_D5_D2 26 +#define CK_TOP_CB_SGMPLL_325M 27 #define CK_TOP_XTAL_D2 28 -#define CK_TOP_CB_RTC_32K 29 -#define CK_TOP_CB_RTC_32P7K 30 +#define CK_TOP_RTC_32K 29 +#define CK_TOP_RTC_32P7K 30 #define CK_TOP_NFI1X 31 #define CK_TOP_USB_EQ_RX250M 32 #define CK_TOP_USB_TX250M 33 -- cgit v1.2.3 From 8cf99baf99d3344de801c7a263e6a6e69e0dc63e Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 3 Aug 2024 10:40:42 +0200 Subject: clk: mediatek: mt7986: reorder TOPCKGEN factor ID Reorder TOPCKGEN factor ID to put TOP_FACTOR first and then PLL. This is to match how it's done in upstream kernel linux and in preparation for OF_UPSTREAM support. Signed-off-by: Christian Marangi --- include/dt-bindings/clock/mt7986-clk.h | 108 ++++++++++++++++----------------- 1 file changed, 54 insertions(+), 54 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index f19948cca16..0048d183389 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -16,60 +16,60 @@ /* TOPCKGEN */ #define CK_TOP_XTAL 0 -#define CK_TOP_CB_MPLL_416M 1 -#define CK_TOP_MPLL_D2 2 -#define CK_TOP_MPLL_D4 3 -#define CK_TOP_MPLL_D8 4 -#define CK_TOP_MPLL_D8_D2 5 -#define CK_TOP_MPLL_D3_D2 6 -#define CK_TOP_MMPLL_D2 7 -#define CK_TOP_MMPLL_D4 8 -#define CK_TOP_MMPLL_D8 9 -#define CK_TOP_MMPLL_D8_D2 10 -#define CK_TOP_MMPLL_D3_D8 11 -#define CK_TOP_MMPLL_U2PHYD 12 -#define CK_TOP_CB_APLL2_196M 13 -#define CK_TOP_APLL2_D4 14 -#define CK_TOP_NET1PLL_D4 15 -#define CK_TOP_NET1PLL_D5 16 -#define CK_TOP_NET1PLL_D5_D2 17 -#define CK_TOP_NET1PLL_D5_D4 18 -#define CK_TOP_NET1PLL_D8_D2 19 -#define CK_TOP_NET1PLL_D8_D4 20 -#define CK_TOP_CB_NET2PLL_800M 21 -#define CK_TOP_NET2PLL_D4 22 -#define CK_TOP_NET2PLL_D4_D2 23 -#define CK_TOP_NET2PLL_D3_D2 24 -#define CK_TOP_CB_WEDMCUPLL_760M 25 -#define CK_TOP_WEDMCUPLL_D5_D2 26 -#define CK_TOP_CB_SGMPLL_325M 27 -#define CK_TOP_XTAL_D2 28 -#define CK_TOP_RTC_32K 29 -#define CK_TOP_RTC_32P7K 30 -#define CK_TOP_NFI1X 31 -#define CK_TOP_USB_EQ_RX250M 32 -#define CK_TOP_USB_TX250M 33 -#define CK_TOP_USB_LN0_CK 34 -#define CK_TOP_USB_CDR_CK 35 -#define CK_TOP_SPINFI_BCK 36 -#define CK_TOP_I2C_BCK 37 -#define CK_TOP_PEXTP_TL 38 -#define CK_TOP_EMMC_250M 39 -#define CK_TOP_EMMC_416M 40 -#define CK_TOP_F_26M_ADC_CK 41 -#define CK_TOP_SYSAXI 42 -#define CK_TOP_NETSYS_WED_MCU 43 -#define CK_TOP_NETSYS_2X 44 -#define CK_TOP_SGM_325M 45 -#define CK_TOP_A1SYS 46 -#define CK_TOP_EIP_B 47 -#define CK_TOP_F26M 48 -#define CK_TOP_AUD_L 49 -#define CK_TOP_A_TUNER 50 -#define CK_TOP_U2U3_REF 51 -#define CK_TOP_U2U3_SYS 52 -#define CK_TOP_U2U3_XHCI 53 -#define CK_TOP_AP2CNN_HOST 54 +#define CK_TOP_XTAL_D2 1 +#define CK_TOP_RTC_32K 2 +#define CK_TOP_RTC_32P7K 3 +#define CK_TOP_NFI1X 4 +#define CK_TOP_USB_EQ_RX250M 5 +#define CK_TOP_USB_TX250M 6 +#define CK_TOP_USB_LN0_CK 7 +#define CK_TOP_USB_CDR_CK 8 +#define CK_TOP_SPINFI_BCK 9 +#define CK_TOP_I2C_BCK 10 +#define CK_TOP_PEXTP_TL 11 +#define CK_TOP_EMMC_250M 12 +#define CK_TOP_EMMC_416M 13 +#define CK_TOP_F_26M_ADC_CK 14 +#define CK_TOP_SYSAXI 15 +#define CK_TOP_NETSYS_WED_MCU 16 +#define CK_TOP_NETSYS_2X 17 +#define CK_TOP_SGM_325M 18 +#define CK_TOP_A1SYS 19 +#define CK_TOP_EIP_B 20 +#define CK_TOP_F26M 21 +#define CK_TOP_AUD_L 22 +#define CK_TOP_A_TUNER 23 +#define CK_TOP_U2U3_REF 24 +#define CK_TOP_U2U3_SYS 25 +#define CK_TOP_U2U3_XHCI 26 +#define CK_TOP_AP2CNN_HOST 27 +#define CK_TOP_CB_MPLL_416M 28 +#define CK_TOP_MPLL_D2 29 +#define CK_TOP_MPLL_D4 30 +#define CK_TOP_MPLL_D8 31 +#define CK_TOP_MPLL_D8_D2 32 +#define CK_TOP_MPLL_D3_D2 33 +#define CK_TOP_MMPLL_D2 34 +#define CK_TOP_MMPLL_D4 35 +#define CK_TOP_MMPLL_D8 36 +#define CK_TOP_MMPLL_D8_D2 37 +#define CK_TOP_MMPLL_D3_D8 38 +#define CK_TOP_MMPLL_U2PHYD 39 +#define CK_TOP_CB_APLL2_196M 40 +#define CK_TOP_APLL2_D4 41 +#define CK_TOP_NET1PLL_D4 42 +#define CK_TOP_NET1PLL_D5 43 +#define CK_TOP_NET1PLL_D5_D2 44 +#define CK_TOP_NET1PLL_D5_D4 45 +#define CK_TOP_NET1PLL_D8_D2 46 +#define CK_TOP_NET1PLL_D8_D4 47 +#define CK_TOP_CB_NET2PLL_800M 48 +#define CK_TOP_NET2PLL_D4 49 +#define CK_TOP_NET2PLL_D4_D2 50 +#define CK_TOP_NET2PLL_D3_D2 51 +#define CK_TOP_CB_WEDMCUPLL_760M 52 +#define CK_TOP_WEDMCUPLL_D5_D2 53 +#define CK_TOP_CB_SGMPLL_325M 54 #define CK_TOP_NFI1X_SEL 55 #define CK_TOP_SPINFI_SEL 56 #define CK_TOP_SPI_SEL 57 -- cgit v1.2.3 From 7124b9928a9360d7198a42298a4bd1359dc7b0ab Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 3 Aug 2024 10:40:43 +0200 Subject: clk: mediatek: mt7986: drop 1/1 spurious factor for topckgen Now that we can have advanced parent handling for mux, we can drop spurious topckgen 1/1 factor. This is in preparation to make the clk ID match the ID in upstream include for mt7986. Drop the factor entry from mt7986-clk.h and reference to them in mt7981.dtsi. Muxes and gates are updated to reference the apmixed clk following how it's done in upstream kernel linux. Add relevant clk type flag in clk_tree for apmixed. Signed-off-by: Christian Marangi --- include/dt-bindings/clock/mt7986-clk.h | 150 ++++++++++++++------------------- 1 file changed, 61 insertions(+), 89 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index 0048d183389..478538d7cce 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -19,95 +19,67 @@ #define CK_TOP_XTAL_D2 1 #define CK_TOP_RTC_32K 2 #define CK_TOP_RTC_32P7K 3 -#define CK_TOP_NFI1X 4 -#define CK_TOP_USB_EQ_RX250M 5 -#define CK_TOP_USB_TX250M 6 -#define CK_TOP_USB_LN0_CK 7 -#define CK_TOP_USB_CDR_CK 8 -#define CK_TOP_SPINFI_BCK 9 -#define CK_TOP_I2C_BCK 10 -#define CK_TOP_PEXTP_TL 11 -#define CK_TOP_EMMC_250M 12 -#define CK_TOP_EMMC_416M 13 -#define CK_TOP_F_26M_ADC_CK 14 -#define CK_TOP_SYSAXI 15 -#define CK_TOP_NETSYS_WED_MCU 16 -#define CK_TOP_NETSYS_2X 17 -#define CK_TOP_SGM_325M 18 -#define CK_TOP_A1SYS 19 -#define CK_TOP_EIP_B 20 -#define CK_TOP_F26M 21 -#define CK_TOP_AUD_L 22 -#define CK_TOP_A_TUNER 23 -#define CK_TOP_U2U3_REF 24 -#define CK_TOP_U2U3_SYS 25 -#define CK_TOP_U2U3_XHCI 26 -#define CK_TOP_AP2CNN_HOST 27 -#define CK_TOP_CB_MPLL_416M 28 -#define CK_TOP_MPLL_D2 29 -#define CK_TOP_MPLL_D4 30 -#define CK_TOP_MPLL_D8 31 -#define CK_TOP_MPLL_D8_D2 32 -#define CK_TOP_MPLL_D3_D2 33 -#define CK_TOP_MMPLL_D2 34 -#define CK_TOP_MMPLL_D4 35 -#define CK_TOP_MMPLL_D8 36 -#define CK_TOP_MMPLL_D8_D2 37 -#define CK_TOP_MMPLL_D3_D8 38 -#define CK_TOP_MMPLL_U2PHYD 39 -#define CK_TOP_CB_APLL2_196M 40 -#define CK_TOP_APLL2_D4 41 -#define CK_TOP_NET1PLL_D4 42 -#define CK_TOP_NET1PLL_D5 43 -#define CK_TOP_NET1PLL_D5_D2 44 -#define CK_TOP_NET1PLL_D5_D4 45 -#define CK_TOP_NET1PLL_D8_D2 46 -#define CK_TOP_NET1PLL_D8_D4 47 -#define CK_TOP_CB_NET2PLL_800M 48 -#define CK_TOP_NET2PLL_D4 49 -#define CK_TOP_NET2PLL_D4_D2 50 -#define CK_TOP_NET2PLL_D3_D2 51 -#define CK_TOP_CB_WEDMCUPLL_760M 52 -#define CK_TOP_WEDMCUPLL_D5_D2 53 -#define CK_TOP_CB_SGMPLL_325M 54 -#define CK_TOP_NFI1X_SEL 55 -#define CK_TOP_SPINFI_SEL 56 -#define CK_TOP_SPI_SEL 57 -#define CK_TOP_SPIM_MST_SEL 58 -#define CK_TOP_UART_SEL 59 -#define CK_TOP_PWM_SEL 60 -#define CK_TOP_I2C_SEL 61 -#define CK_TOP_PEXTP_TL_SEL 62 -#define CK_TOP_EMMC_250M_SEL 63 -#define CK_TOP_EMMC_416M_SEL 64 -#define CK_TOP_F_26M_ADC_SEL 65 -#define CK_TOP_DRAMC_SEL 66 -#define CK_TOP_DRAMC_MD32_SEL 67 -#define CK_TOP_SYSAXI_SEL 68 -#define CK_TOP_SYSAPB_SEL 69 -#define CK_TOP_ARM_DB_MAIN_SEL 70 -#define CK_TOP_ARM_DB_JTSEL 71 -#define CK_TOP_NETSYS_SEL 72 -#define CK_TOP_NETSYS_500M_SEL 73 -#define CK_TOP_NETSYS_MCU_SEL 74 -#define CK_TOP_NETSYS_2X_SEL 75 -#define CK_TOP_SGM_325M_SEL 76 -#define CK_TOP_SGM_REG_SEL 77 -#define CK_TOP_A1SYS_SEL 78 -#define CK_TOP_CONN_MCUSYS_SEL 79 -#define CK_TOP_EIP_B_SEL 80 -#define CK_TOP_PCIE_PHY_SEL 81 -#define CK_TOP_USB3_PHY_SEL 82 -#define CK_TOP_F26M_SEL 83 -#define CK_TOP_AUD_L_SEL 84 -#define CK_TOP_A_TUNER_SEL 85 -#define CK_TOP_U2U3_SEL 86 -#define CK_TOP_U2U3_SYS_SEL 87 -#define CK_TOP_U2U3_XHCI_SEL 88 -#define CK_TOP_DA_U2_REFSEL 89 -#define CK_TOP_DA_U2_CK_1P_SEL 90 -#define CK_TOP_AP2CNN_HOST_SEL 91 -#define CLK_TOP_NR_CLK 92 +#define CK_TOP_A_TUNER 4 +#define CK_TOP_MPLL_D2 5 +#define CK_TOP_MPLL_D4 6 +#define CK_TOP_MPLL_D8 7 +#define CK_TOP_MPLL_D8_D2 8 +#define CK_TOP_MPLL_D3_D2 9 +#define CK_TOP_MMPLL_D2 10 +#define CK_TOP_MMPLL_D4 11 +#define CK_TOP_MMPLL_D8 12 +#define CK_TOP_MMPLL_D8_D2 13 +#define CK_TOP_MMPLL_D3_D8 14 +#define CK_TOP_MMPLL_U2PHYD 15 +#define CK_TOP_APLL2_D4 16 +#define CK_TOP_NET1PLL_D4 17 +#define CK_TOP_NET1PLL_D5 18 +#define CK_TOP_NET1PLL_D5_D2 19 +#define CK_TOP_NET1PLL_D5_D4 20 +#define CK_TOP_NET1PLL_D8_D2 21 +#define CK_TOP_NET1PLL_D8_D4 22 +#define CK_TOP_NET2PLL_D4 23 +#define CK_TOP_NET2PLL_D4_D2 24 +#define CK_TOP_NET2PLL_D3_D2 25 +#define CK_TOP_WEDMCUPLL_D5_D2 26 +#define CK_TOP_NFI1X_SEL 27 +#define CK_TOP_SPINFI_SEL 28 +#define CK_TOP_SPI_SEL 29 +#define CK_TOP_SPIM_MST_SEL 30 +#define CK_TOP_UART_SEL 31 +#define CK_TOP_PWM_SEL 32 +#define CK_TOP_I2C_SEL 33 +#define CK_TOP_PEXTP_TL_SEL 34 +#define CK_TOP_EMMC_250M_SEL 35 +#define CK_TOP_EMMC_416M_SEL 36 +#define CK_TOP_F_26M_ADC_SEL 37 +#define CK_TOP_DRAMC_SEL 38 +#define CK_TOP_DRAMC_MD32_SEL 39 +#define CK_TOP_SYSAXI_SEL 40 +#define CK_TOP_SYSAPB_SEL 41 +#define CK_TOP_ARM_DB_MAIN_SEL 42 +#define CK_TOP_ARM_DB_JTSEL 43 +#define CK_TOP_NETSYS_SEL 44 +#define CK_TOP_NETSYS_500M_SEL 45 +#define CK_TOP_NETSYS_MCU_SEL 46 +#define CK_TOP_NETSYS_2X_SEL 47 +#define CK_TOP_SGM_325M_SEL 48 +#define CK_TOP_SGM_REG_SEL 49 +#define CK_TOP_A1SYS_SEL 50 +#define CK_TOP_CONN_MCUSYS_SEL 51 +#define CK_TOP_EIP_B_SEL 52 +#define CK_TOP_PCIE_PHY_SEL 53 +#define CK_TOP_USB3_PHY_SEL 54 +#define CK_TOP_F26M_SEL 55 +#define CK_TOP_AUD_L_SEL 56 +#define CK_TOP_A_TUNER_SEL 57 +#define CK_TOP_U2U3_SEL 58 +#define CK_TOP_U2U3_SYS_SEL 59 +#define CK_TOP_U2U3_XHCI_SEL 60 +#define CK_TOP_DA_U2_REFSEL 61 +#define CK_TOP_DA_U2_CK_1P_SEL 62 +#define CK_TOP_AP2CNN_HOST_SEL 63 +#define CLK_TOP_NR_CLK 64 /* * INFRACFG_AO -- cgit v1.2.3 From e4bdf9b004e191134b57120b9cdf739016ea4578 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 3 Aug 2024 10:40:44 +0200 Subject: clk: mediatek: mt7986: comment out CK_TOP_A_TUNER as not used Comment out CK_TOP_A_TUNER as not used and not defined in upstream kernel linux. This is to permit support of OF_UPSTREAM and have a 1:1 match with upstream linux clock ID. Signed-off-by: Christian Marangi --- include/dt-bindings/clock/mt7986-clk.h | 122 ++++++++++++++++----------------- 1 file changed, 61 insertions(+), 61 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index 478538d7cce..7df13665900 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -19,67 +19,67 @@ #define CK_TOP_XTAL_D2 1 #define CK_TOP_RTC_32K 2 #define CK_TOP_RTC_32P7K 3 -#define CK_TOP_A_TUNER 4 -#define CK_TOP_MPLL_D2 5 -#define CK_TOP_MPLL_D4 6 -#define CK_TOP_MPLL_D8 7 -#define CK_TOP_MPLL_D8_D2 8 -#define CK_TOP_MPLL_D3_D2 9 -#define CK_TOP_MMPLL_D2 10 -#define CK_TOP_MMPLL_D4 11 -#define CK_TOP_MMPLL_D8 12 -#define CK_TOP_MMPLL_D8_D2 13 -#define CK_TOP_MMPLL_D3_D8 14 -#define CK_TOP_MMPLL_U2PHYD 15 -#define CK_TOP_APLL2_D4 16 -#define CK_TOP_NET1PLL_D4 17 -#define CK_TOP_NET1PLL_D5 18 -#define CK_TOP_NET1PLL_D5_D2 19 -#define CK_TOP_NET1PLL_D5_D4 20 -#define CK_TOP_NET1PLL_D8_D2 21 -#define CK_TOP_NET1PLL_D8_D4 22 -#define CK_TOP_NET2PLL_D4 23 -#define CK_TOP_NET2PLL_D4_D2 24 -#define CK_TOP_NET2PLL_D3_D2 25 -#define CK_TOP_WEDMCUPLL_D5_D2 26 -#define CK_TOP_NFI1X_SEL 27 -#define CK_TOP_SPINFI_SEL 28 -#define CK_TOP_SPI_SEL 29 -#define CK_TOP_SPIM_MST_SEL 30 -#define CK_TOP_UART_SEL 31 -#define CK_TOP_PWM_SEL 32 -#define CK_TOP_I2C_SEL 33 -#define CK_TOP_PEXTP_TL_SEL 34 -#define CK_TOP_EMMC_250M_SEL 35 -#define CK_TOP_EMMC_416M_SEL 36 -#define CK_TOP_F_26M_ADC_SEL 37 -#define CK_TOP_DRAMC_SEL 38 -#define CK_TOP_DRAMC_MD32_SEL 39 -#define CK_TOP_SYSAXI_SEL 40 -#define CK_TOP_SYSAPB_SEL 41 -#define CK_TOP_ARM_DB_MAIN_SEL 42 -#define CK_TOP_ARM_DB_JTSEL 43 -#define CK_TOP_NETSYS_SEL 44 -#define CK_TOP_NETSYS_500M_SEL 45 -#define CK_TOP_NETSYS_MCU_SEL 46 -#define CK_TOP_NETSYS_2X_SEL 47 -#define CK_TOP_SGM_325M_SEL 48 -#define CK_TOP_SGM_REG_SEL 49 -#define CK_TOP_A1SYS_SEL 50 -#define CK_TOP_CONN_MCUSYS_SEL 51 -#define CK_TOP_EIP_B_SEL 52 -#define CK_TOP_PCIE_PHY_SEL 53 -#define CK_TOP_USB3_PHY_SEL 54 -#define CK_TOP_F26M_SEL 55 -#define CK_TOP_AUD_L_SEL 56 -#define CK_TOP_A_TUNER_SEL 57 -#define CK_TOP_U2U3_SEL 58 -#define CK_TOP_U2U3_SYS_SEL 59 -#define CK_TOP_U2U3_XHCI_SEL 60 -#define CK_TOP_DA_U2_REFSEL 61 -#define CK_TOP_DA_U2_CK_1P_SEL 62 -#define CK_TOP_AP2CNN_HOST_SEL 63 -#define CLK_TOP_NR_CLK 64 +/* #define CK_TOP_A_TUNER 4 */ +#define CK_TOP_MPLL_D2 4 +#define CK_TOP_MPLL_D4 5 +#define CK_TOP_MPLL_D8 6 +#define CK_TOP_MPLL_D8_D2 7 +#define CK_TOP_MPLL_D3_D2 8 +#define CK_TOP_MMPLL_D2 9 +#define CK_TOP_MMPLL_D4 10 +#define CK_TOP_MMPLL_D8 11 +#define CK_TOP_MMPLL_D8_D2 12 +#define CK_TOP_MMPLL_D3_D8 13 +#define CK_TOP_MMPLL_U2PHYD 14 +#define CK_TOP_APLL2_D4 15 +#define CK_TOP_NET1PLL_D4 16 +#define CK_TOP_NET1PLL_D5 17 +#define CK_TOP_NET1PLL_D5_D2 18 +#define CK_TOP_NET1PLL_D5_D4 19 +#define CK_TOP_NET1PLL_D8_D2 20 +#define CK_TOP_NET1PLL_D8_D4 21 +#define CK_TOP_NET2PLL_D4 22 +#define CK_TOP_NET2PLL_D4_D2 23 +#define CK_TOP_NET2PLL_D3_D2 24 +#define CK_TOP_WEDMCUPLL_D5_D2 25 +#define CK_TOP_NFI1X_SEL 26 +#define CK_TOP_SPINFI_SEL 27 +#define CK_TOP_SPI_SEL 28 +#define CK_TOP_SPIM_MST_SEL 29 +#define CK_TOP_UART_SEL 30 +#define CK_TOP_PWM_SEL 31 +#define CK_TOP_I2C_SEL 32 +#define CK_TOP_PEXTP_TL_SEL 33 +#define CK_TOP_EMMC_250M_SEL 34 +#define CK_TOP_EMMC_416M_SEL 35 +#define CK_TOP_F_26M_ADC_SEL 36 +#define CK_TOP_DRAMC_SEL 37 +#define CK_TOP_DRAMC_MD32_SEL 38 +#define CK_TOP_SYSAXI_SEL 39 +#define CK_TOP_SYSAPB_SEL 40 +#define CK_TOP_ARM_DB_MAIN_SEL 41 +#define CK_TOP_ARM_DB_JTSEL 42 +#define CK_TOP_NETSYS_SEL 43 +#define CK_TOP_NETSYS_500M_SEL 44 +#define CK_TOP_NETSYS_MCU_SEL 45 +#define CK_TOP_NETSYS_2X_SEL 46 +#define CK_TOP_SGM_325M_SEL 47 +#define CK_TOP_SGM_REG_SEL 48 +#define CK_TOP_A1SYS_SEL 49 +#define CK_TOP_CONN_MCUSYS_SEL 50 +#define CK_TOP_EIP_B_SEL 51 +#define CK_TOP_PCIE_PHY_SEL 52 +#define CK_TOP_USB3_PHY_SEL 53 +#define CK_TOP_F26M_SEL 54 +#define CK_TOP_AUD_L_SEL 55 +#define CK_TOP_A_TUNER_SEL 56 +#define CK_TOP_U2U3_SEL 57 +#define CK_TOP_U2U3_SYS_SEL 58 +#define CK_TOP_U2U3_XHCI_SEL 59 +#define CK_TOP_DA_U2_REFSEL 60 +#define CK_TOP_DA_U2_CK_1P_SEL 61 +#define CK_TOP_AP2CNN_HOST_SEL 62 +#define CLK_TOP_NR_CLK 63 /* * INFRACFG_AO -- cgit v1.2.3 From 6636017ad3257eeccbc14706db1edd07479ca39b Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 3 Aug 2024 10:40:45 +0200 Subject: clk: mediatek: mt7986: move INFRA_TRNG_CK to the bottom of the list Move INFRA_TRNG_CK to the bottom of the list to have a 1:1 match with upstream linux clock ID. Signed-off-by: Christian Marangi --- include/dt-bindings/clock/mt7986-clk.h | 54 +++++++++++++++++----------------- 1 file changed, 27 insertions(+), 27 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index 7df13665900..39939f8e028 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -115,33 +115,33 @@ #define CK_INFRA_SEJ_13M_CK 16 #define CK_INFRA_THERM_CK 17 #define CK_INFRA_I2C0_CK 18 -#define CK_INFRA_TRNG_CK 19 -#define CK_INFRA_UART0_CK 20 -#define CK_INFRA_UART1_CK 21 -#define CK_INFRA_UART2_CK 22 -#define CK_INFRA_NFI1_CK 23 -#define CK_INFRA_SPINFI1_CK 24 -#define CK_INFRA_NFI_HCK_CK 25 -#define CK_INFRA_SPI0_CK 26 -#define CK_INFRA_SPI1_CK 27 -#define CK_INFRA_SPI0_HCK_CK 28 -#define CK_INFRA_SPI1_HCK_CK 29 -#define CK_INFRA_FRTC_CK 30 -#define CK_INFRA_MSDC_CK 31 -#define CK_INFRA_MSDC_HCK_CK 32 -#define CK_INFRA_MSDC_133M_CK 33 -#define CK_INFRA_MSDC_66M_CK 34 -#define CK_INFRA_ADC_26M_CK 35 -#define CK_INFRA_ADC_FRC_CK 36 -#define CK_INFRA_FBIST2FPC_CK 37 -#define CK_INFRA_IUSB_133_CK 38 -#define CK_INFRA_IUSB_66M_CK 39 -#define CK_INFRA_IUSB_SYS_CK 40 -#define CK_INFRA_IUSB_CK 41 -#define CK_INFRA_IPCIE_CK 42 -#define CK_INFRA_IPCIE_PIPE_CK 43 -#define CK_INFRA_IPCIER_CK 44 -#define CK_INFRA_IPCIEB_CK 45 +#define CK_INFRA_UART0_CK 19 +#define CK_INFRA_UART1_CK 20 +#define CK_INFRA_UART2_CK 21 +#define CK_INFRA_NFI1_CK 22 +#define CK_INFRA_SPINFI1_CK 23 +#define CK_INFRA_NFI_HCK_CK 24 +#define CK_INFRA_SPI0_CK 25 +#define CK_INFRA_SPI1_CK 26 +#define CK_INFRA_SPI0_HCK_CK 27 +#define CK_INFRA_SPI1_HCK_CK 28 +#define CK_INFRA_FRTC_CK 29 +#define CK_INFRA_MSDC_CK 30 +#define CK_INFRA_MSDC_HCK_CK 31 +#define CK_INFRA_MSDC_133M_CK 32 +#define CK_INFRA_MSDC_66M_CK 33 +#define CK_INFRA_ADC_26M_CK 34 +#define CK_INFRA_ADC_FRC_CK 35 +#define CK_INFRA_FBIST2FPC_CK 36 +#define CK_INFRA_IUSB_133_CK 37 +#define CK_INFRA_IUSB_66M_CK 38 +#define CK_INFRA_IUSB_SYS_CK 39 +#define CK_INFRA_IUSB_CK 40 +#define CK_INFRA_IPCIE_CK 41 +#define CK_INFRA_IPCIE_PIPE_CK 42 +#define CK_INFRA_IPCIER_CK 43 +#define CK_INFRA_IPCIEB_CK 44 +#define CK_INFRA_TRNG_CK 45 #define CLK_INFRA_AO_NR_CLK 46 /* APMIXEDSYS */ -- cgit v1.2.3 From efc82b035f78b522f44bdc209dff5acc82ffc58f Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 3 Aug 2024 10:40:46 +0200 Subject: clk: mediatek: mt7986: replace infracfg ID with upstream linux Replace infracfg clk ID with upstream linux version. The same format is used here with the factor first, then mux and then gates. To correctly reference the gates in clk_gate function, define the gates_offs value in clk_tree now that they are at an offset from mux and factor. Signed-off-by: Christian Marangi --- include/dt-bindings/clock/mt7986-clk.h | 124 +++++++++++++++------------------ 1 file changed, 58 insertions(+), 66 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index 39939f8e028..1c28ab34dcf 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -8,11 +8,6 @@ #ifndef _DT_BINDINGS_CLK_MT7986_H #define _DT_BINDINGS_CLK_MT7986_H -/* INFRACFG */ - -#define CK_INFRA_SYSAXI_D2 0 -#define CLK_INFRA_NR_CLK 1 - /* TOPCKGEN */ #define CK_TOP_XTAL 0 @@ -81,68 +76,65 @@ #define CK_TOP_AP2CNN_HOST_SEL 62 #define CLK_TOP_NR_CLK 63 -/* - * INFRACFG_AO - * clock muxes need to be append to infracfg domain, and clock gates - * need to be keep in infracgh_ao domain - */ +/* INFRACFG */ -#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK) -#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK) -#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK) -#define CK_INFRA_GPT_STA 0 -#define CK_INFRA_PWM_HCK 1 -#define CK_INFRA_PWM_STA 2 -#define CK_INFRA_PWM1_CK 3 -#define CK_INFRA_PWM2_CK 4 -#define CK_INFRA_CQ_DMA_CK 5 -#define CK_INFRA_EIP97_CK 6 -#define CK_INFRA_AUD_BUS_CK 7 -#define CK_INFRA_AUD_26M_CK 8 -#define CK_INFRA_AUD_L_CK 9 -#define CK_INFRA_AUD_AUD_CK 10 -#define CK_INFRA_AUD_EG2_CK 11 -#define CK_INFRA_DRAMC_26M_CK 12 -#define CK_INFRA_DBG_CK 13 -#define CK_INFRA_AP_DMA_CK 14 -#define CK_INFRA_SEJ_CK 15 -#define CK_INFRA_SEJ_13M_CK 16 -#define CK_INFRA_THERM_CK 17 -#define CK_INFRA_I2C0_CK 18 -#define CK_INFRA_UART0_CK 19 -#define CK_INFRA_UART1_CK 20 -#define CK_INFRA_UART2_CK 21 -#define CK_INFRA_NFI1_CK 22 -#define CK_INFRA_SPINFI1_CK 23 -#define CK_INFRA_NFI_HCK_CK 24 -#define CK_INFRA_SPI0_CK 25 -#define CK_INFRA_SPI1_CK 26 -#define CK_INFRA_SPI0_HCK_CK 27 -#define CK_INFRA_SPI1_HCK_CK 28 -#define CK_INFRA_FRTC_CK 29 -#define CK_INFRA_MSDC_CK 30 -#define CK_INFRA_MSDC_HCK_CK 31 -#define CK_INFRA_MSDC_133M_CK 32 -#define CK_INFRA_MSDC_66M_CK 33 -#define CK_INFRA_ADC_26M_CK 34 -#define CK_INFRA_ADC_FRC_CK 35 -#define CK_INFRA_FBIST2FPC_CK 36 -#define CK_INFRA_IUSB_133_CK 37 -#define CK_INFRA_IUSB_66M_CK 38 -#define CK_INFRA_IUSB_SYS_CK 39 -#define CK_INFRA_IUSB_CK 40 -#define CK_INFRA_IPCIE_CK 41 -#define CK_INFRA_IPCIE_PIPE_CK 42 -#define CK_INFRA_IPCIER_CK 43 -#define CK_INFRA_IPCIEB_CK 44 -#define CK_INFRA_TRNG_CK 45 -#define CLK_INFRA_AO_NR_CLK 46 +#define CK_INFRA_SYSAXI_D2 0 +#define CK_INFRA_UART0_SEL 1 +#define CK_INFRA_UART1_SEL 2 +#define CK_INFRA_UART2_SEL 3 +#define CK_INFRA_SPI0_SEL 4 +#define CK_INFRA_SPI1_SEL 5 +#define CK_INFRA_PWM1_SEL 6 +#define CK_INFRA_PWM2_SEL 7 +#define CK_INFRA_PWM_BSEL 8 +#define CK_INFRA_PCIE_SEL 9 +#define CK_INFRA_GPT_STA 10 +#define CK_INFRA_PWM_HCK 11 +#define CK_INFRA_PWM_STA 12 +#define CK_INFRA_PWM1_CK 13 +#define CK_INFRA_PWM2_CK 14 +#define CK_INFRA_CQ_DMA_CK 15 +#define CK_INFRA_EIP97_CK 16 +#define CK_INFRA_AUD_BUS_CK 17 +#define CK_INFRA_AUD_26M_CK 18 +#define CK_INFRA_AUD_L_CK 19 +#define CK_INFRA_AUD_AUD_CK 20 +#define CK_INFRA_AUD_EG2_CK 21 +#define CK_INFRA_DRAMC_26M_CK 22 +#define CK_INFRA_DBG_CK 23 +#define CK_INFRA_AP_DMA_CK 24 +#define CK_INFRA_SEJ_CK 25 +#define CK_INFRA_SEJ_13M_CK 26 +#define CK_INFRA_THERM_CK 27 +#define CK_INFRA_I2C0_CK 28 +#define CK_INFRA_UART0_CK 29 +#define CK_INFRA_UART1_CK 30 +#define CK_INFRA_UART2_CK 31 +#define CK_INFRA_NFI1_CK 32 +#define CK_INFRA_SPINFI1_CK 33 +#define CK_INFRA_NFI_HCK_CK 34 +#define CK_INFRA_SPI0_CK 35 +#define CK_INFRA_SPI1_CK 36 +#define CK_INFRA_SPI0_HCK_CK 37 +#define CK_INFRA_SPI1_HCK_CK 38 +#define CK_INFRA_FRTC_CK 39 +#define CK_INFRA_MSDC_CK 40 +#define CK_INFRA_MSDC_HCK_CK 41 +#define CK_INFRA_MSDC_133M_CK 42 +#define CK_INFRA_MSDC_66M_CK 43 +#define CK_INFRA_ADC_26M_CK 44 +#define CK_INFRA_ADC_FRC_CK 45 +#define CK_INFRA_FBIST2FPC_CK 46 +#define CK_INFRA_IUSB_133_CK 47 +#define CK_INFRA_IUSB_66M_CK 48 +#define CK_INFRA_IUSB_SYS_CK 49 +#define CK_INFRA_IUSB_CK 50 +#define CK_INFRA_IPCIE_CK 51 +#define CK_INFRA_IPCIE_PIPE_CK 52 +#define CK_INFRA_IPCIER_CK 53 +#define CK_INFRA_IPCIEB_CK 54 +#define CK_INFRA_TRNG_CK 55 +#define CK_INFRA_AO_NR_CLK 46 /* APMIXEDSYS */ -- cgit v1.2.3 From 54f8ba658fb43c9e74879807cd61f84188fdf697 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 3 Aug 2024 10:40:48 +0200 Subject: clk: mediatek: mt7986: rename CK to CLK Rename each entry from CK to CLK to match the include in upstream kernel linux. Signed-off-by: Christian Marangi Tested-by: Frank Wunderlich --- include/dt-bindings/clock/mt7986-clk.h | 284 ++++++++++++++++----------------- 1 file changed, 142 insertions(+), 142 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index 1c28ab34dcf..5da260386fd 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -10,167 +10,167 @@ /* TOPCKGEN */ -#define CK_TOP_XTAL 0 -#define CK_TOP_XTAL_D2 1 -#define CK_TOP_RTC_32K 2 -#define CK_TOP_RTC_32P7K 3 -/* #define CK_TOP_A_TUNER 4 */ -#define CK_TOP_MPLL_D2 4 -#define CK_TOP_MPLL_D4 5 -#define CK_TOP_MPLL_D8 6 -#define CK_TOP_MPLL_D8_D2 7 -#define CK_TOP_MPLL_D3_D2 8 -#define CK_TOP_MMPLL_D2 9 -#define CK_TOP_MMPLL_D4 10 -#define CK_TOP_MMPLL_D8 11 -#define CK_TOP_MMPLL_D8_D2 12 -#define CK_TOP_MMPLL_D3_D8 13 -#define CK_TOP_MMPLL_U2PHYD 14 -#define CK_TOP_APLL2_D4 15 -#define CK_TOP_NET1PLL_D4 16 -#define CK_TOP_NET1PLL_D5 17 -#define CK_TOP_NET1PLL_D5_D2 18 -#define CK_TOP_NET1PLL_D5_D4 19 -#define CK_TOP_NET1PLL_D8_D2 20 -#define CK_TOP_NET1PLL_D8_D4 21 -#define CK_TOP_NET2PLL_D4 22 -#define CK_TOP_NET2PLL_D4_D2 23 -#define CK_TOP_NET2PLL_D3_D2 24 -#define CK_TOP_WEDMCUPLL_D5_D2 25 -#define CK_TOP_NFI1X_SEL 26 -#define CK_TOP_SPINFI_SEL 27 -#define CK_TOP_SPI_SEL 28 -#define CK_TOP_SPIM_MST_SEL 29 -#define CK_TOP_UART_SEL 30 -#define CK_TOP_PWM_SEL 31 -#define CK_TOP_I2C_SEL 32 -#define CK_TOP_PEXTP_TL_SEL 33 -#define CK_TOP_EMMC_250M_SEL 34 -#define CK_TOP_EMMC_416M_SEL 35 -#define CK_TOP_F_26M_ADC_SEL 36 -#define CK_TOP_DRAMC_SEL 37 -#define CK_TOP_DRAMC_MD32_SEL 38 -#define CK_TOP_SYSAXI_SEL 39 -#define CK_TOP_SYSAPB_SEL 40 -#define CK_TOP_ARM_DB_MAIN_SEL 41 -#define CK_TOP_ARM_DB_JTSEL 42 -#define CK_TOP_NETSYS_SEL 43 -#define CK_TOP_NETSYS_500M_SEL 44 -#define CK_TOP_NETSYS_MCU_SEL 45 -#define CK_TOP_NETSYS_2X_SEL 46 -#define CK_TOP_SGM_325M_SEL 47 -#define CK_TOP_SGM_REG_SEL 48 -#define CK_TOP_A1SYS_SEL 49 -#define CK_TOP_CONN_MCUSYS_SEL 50 -#define CK_TOP_EIP_B_SEL 51 -#define CK_TOP_PCIE_PHY_SEL 52 -#define CK_TOP_USB3_PHY_SEL 53 -#define CK_TOP_F26M_SEL 54 -#define CK_TOP_AUD_L_SEL 55 -#define CK_TOP_A_TUNER_SEL 56 -#define CK_TOP_U2U3_SEL 57 -#define CK_TOP_U2U3_SYS_SEL 58 -#define CK_TOP_U2U3_XHCI_SEL 59 -#define CK_TOP_DA_U2_REFSEL 60 -#define CK_TOP_DA_U2_CK_1P_SEL 61 -#define CK_TOP_AP2CNN_HOST_SEL 62 +#define CLK_TOP_XTAL 0 +#define CLK_TOP_XTAL_D2 1 +#define CLK_TOP_RTC_32K 2 +#define CLK_TOP_RTC_32P7K 3 +/* #define CLK_TOP_A_TUNER 4 */ +#define CLK_TOP_MPLL_D2 4 +#define CLK_TOP_MPLL_D4 5 +#define CLK_TOP_MPLL_D8 6 +#define CLK_TOP_MPLL_D8_D2 7 +#define CLK_TOP_MPLL_D3_D2 8 +#define CLK_TOP_MMPLL_D2 9 +#define CLK_TOP_MMPLL_D4 10 +#define CLK_TOP_MMPLL_D8 11 +#define CLK_TOP_MMPLL_D8_D2 12 +#define CLK_TOP_MMPLL_D3_D8 13 +#define CLK_TOP_MMPLL_U2PHYD 14 +#define CLK_TOP_APLL2_D4 15 +#define CLK_TOP_NET1PLL_D4 16 +#define CLK_TOP_NET1PLL_D5 17 +#define CLK_TOP_NET1PLL_D5_D2 18 +#define CLK_TOP_NET1PLL_D5_D4 19 +#define CLK_TOP_NET1PLL_D8_D2 20 +#define CLK_TOP_NET1PLL_D8_D4 21 +#define CLK_TOP_NET2PLL_D4 22 +#define CLK_TOP_NET2PLL_D4_D2 23 +#define CLK_TOP_NET2PLL_D3_D2 24 +#define CLK_TOP_WEDMCUPLL_D5_D2 25 +#define CLK_TOP_NFI1X_SEL 26 +#define CLK_TOP_SPINFI_SEL 27 +#define CLK_TOP_SPI_SEL 28 +#define CLK_TOP_SPIM_MST_SEL 29 +#define CLK_TOP_UART_SEL 30 +#define CLK_TOP_PWM_SEL 31 +#define CLK_TOP_I2C_SEL 32 +#define CLK_TOP_PEXTP_TL_SEL 33 +#define CLK_TOP_EMMC_250M_SEL 34 +#define CLK_TOP_EMMC_416M_SEL 35 +#define CLK_TOP_F_26M_ADC_SEL 36 +#define CLK_TOP_DRAMC_SEL 37 +#define CLK_TOP_DRAMC_MD32_SEL 38 +#define CLK_TOP_SYSAXI_SEL 39 +#define CLK_TOP_SYSAPB_SEL 40 +#define CLK_TOP_ARM_DB_MAIN_SEL 41 +#define CLK_TOP_ARM_DB_JTSEL 42 +#define CLK_TOP_NETSYS_SEL 43 +#define CLK_TOP_NETSYS_500M_SEL 44 +#define CLK_TOP_NETSYS_MCU_SEL 45 +#define CLK_TOP_NETSYS_2X_SEL 46 +#define CLK_TOP_SGM_325M_SEL 47 +#define CLK_TOP_SGM_REG_SEL 48 +#define CLK_TOP_A1SYS_SEL 49 +#define CLK_TOP_CONN_MCUSYS_SEL 50 +#define CLK_TOP_EIP_B_SEL 51 +#define CLK_TOP_PCIE_PHY_SEL 52 +#define CLK_TOP_USB3_PHY_SEL 53 +#define CLK_TOP_F26M_SEL 54 +#define CLK_TOP_AUD_L_SEL 55 +#define CLK_TOP_A_TUNER_SEL 56 +#define CLK_TOP_U2U3_SEL 57 +#define CLK_TOP_U2U3_SYS_SEL 58 +#define CLK_TOP_U2U3_XHCI_SEL 59 +#define CLK_TOP_DA_U2_REFSEL 60 +#define CLK_TOP_DA_U2_CK_1P_SEL 61 +#define CLK_TOP_AP2CNN_HOST_SEL 62 #define CLK_TOP_NR_CLK 63 /* INFRACFG */ -#define CK_INFRA_SYSAXI_D2 0 -#define CK_INFRA_UART0_SEL 1 -#define CK_INFRA_UART1_SEL 2 -#define CK_INFRA_UART2_SEL 3 -#define CK_INFRA_SPI0_SEL 4 -#define CK_INFRA_SPI1_SEL 5 -#define CK_INFRA_PWM1_SEL 6 -#define CK_INFRA_PWM2_SEL 7 -#define CK_INFRA_PWM_BSEL 8 -#define CK_INFRA_PCIE_SEL 9 -#define CK_INFRA_GPT_STA 10 -#define CK_INFRA_PWM_HCK 11 -#define CK_INFRA_PWM_STA 12 -#define CK_INFRA_PWM1_CK 13 -#define CK_INFRA_PWM2_CK 14 -#define CK_INFRA_CQ_DMA_CK 15 -#define CK_INFRA_EIP97_CK 16 -#define CK_INFRA_AUD_BUS_CK 17 -#define CK_INFRA_AUD_26M_CK 18 -#define CK_INFRA_AUD_L_CK 19 -#define CK_INFRA_AUD_AUD_CK 20 -#define CK_INFRA_AUD_EG2_CK 21 -#define CK_INFRA_DRAMC_26M_CK 22 -#define CK_INFRA_DBG_CK 23 -#define CK_INFRA_AP_DMA_CK 24 -#define CK_INFRA_SEJ_CK 25 -#define CK_INFRA_SEJ_13M_CK 26 -#define CK_INFRA_THERM_CK 27 -#define CK_INFRA_I2C0_CK 28 -#define CK_INFRA_UART0_CK 29 -#define CK_INFRA_UART1_CK 30 -#define CK_INFRA_UART2_CK 31 -#define CK_INFRA_NFI1_CK 32 -#define CK_INFRA_SPINFI1_CK 33 -#define CK_INFRA_NFI_HCK_CK 34 -#define CK_INFRA_SPI0_CK 35 -#define CK_INFRA_SPI1_CK 36 -#define CK_INFRA_SPI0_HCK_CK 37 -#define CK_INFRA_SPI1_HCK_CK 38 -#define CK_INFRA_FRTC_CK 39 -#define CK_INFRA_MSDC_CK 40 -#define CK_INFRA_MSDC_HCK_CK 41 -#define CK_INFRA_MSDC_133M_CK 42 -#define CK_INFRA_MSDC_66M_CK 43 -#define CK_INFRA_ADC_26M_CK 44 -#define CK_INFRA_ADC_FRC_CK 45 -#define CK_INFRA_FBIST2FPC_CK 46 -#define CK_INFRA_IUSB_133_CK 47 -#define CK_INFRA_IUSB_66M_CK 48 -#define CK_INFRA_IUSB_SYS_CK 49 -#define CK_INFRA_IUSB_CK 50 -#define CK_INFRA_IPCIE_CK 51 -#define CK_INFRA_IPCIE_PIPE_CK 52 -#define CK_INFRA_IPCIER_CK 53 -#define CK_INFRA_IPCIEB_CK 54 -#define CK_INFRA_TRNG_CK 55 -#define CK_INFRA_AO_NR_CLK 46 +#define CLK_INFRA_SYSAXI_D2 0 +#define CLK_INFRA_UART0_SEL 1 +#define CLK_INFRA_UART1_SEL 2 +#define CLK_INFRA_UART2_SEL 3 +#define CLK_INFRA_SPI0_SEL 4 +#define CLK_INFRA_SPI1_SEL 5 +#define CLK_INFRA_PWM1_SEL 6 +#define CLK_INFRA_PWM2_SEL 7 +#define CLK_INFRA_PWM_BSEL 8 +#define CLK_INFRA_PCIE_SEL 9 +#define CLK_INFRA_GPT_STA 10 +#define CLK_INFRA_PWM_HCK 11 +#define CLK_INFRA_PWM_STA 12 +#define CLK_INFRA_PWM1_CK 13 +#define CLK_INFRA_PWM2_CK 14 +#define CLK_INFRA_CQ_DMA_CK 15 +#define CLK_INFRA_EIP97_CK 16 +#define CLK_INFRA_AUD_BUS_CK 17 +#define CLK_INFRA_AUD_26M_CK 18 +#define CLK_INFRA_AUD_L_CK 19 +#define CLK_INFRA_AUD_AUD_CK 20 +#define CLK_INFRA_AUD_EG2_CK 21 +#define CLK_INFRA_DRAMC_26M_CK 22 +#define CLK_INFRA_DBG_CK 23 +#define CLK_INFRA_AP_DMA_CK 24 +#define CLK_INFRA_SEJ_CK 25 +#define CLK_INFRA_SEJ_13M_CK 26 +#define CLK_INFRA_THERM_CK 27 +#define CLK_INFRA_I2C0_CK 28 +#define CLK_INFRA_UART0_CK 29 +#define CLK_INFRA_UART1_CK 30 +#define CLK_INFRA_UART2_CK 31 +#define CLK_INFRA_NFI1_CK 32 +#define CLK_INFRA_SPINFI1_CK 33 +#define CLK_INFRA_NFI_HCK_CK 34 +#define CLK_INFRA_SPI0_CK 35 +#define CLK_INFRA_SPI1_CK 36 +#define CLK_INFRA_SPI0_HCK_CK 37 +#define CLK_INFRA_SPI1_HCK_CK 38 +#define CLK_INFRA_FRTC_CK 39 +#define CLK_INFRA_MSDC_CK 40 +#define CLK_INFRA_MSDC_HCK_CK 41 +#define CLK_INFRA_MSDC_133M_CK 42 +#define CLK_INFRA_MSDC_66M_CK 43 +#define CLK_INFRA_ADC_26M_CK 44 +#define CLK_INFRA_ADC_FRC_CK 45 +#define CLK_INFRA_FBIST2FPC_CK 46 +#define CLK_INFRA_IUSB_133_CK 47 +#define CLK_INFRA_IUSB_66M_CK 48 +#define CLK_INFRA_IUSB_SYS_CK 49 +#define CLK_INFRA_IUSB_CK 50 +#define CLK_INFRA_IPCIE_CK 51 +#define CLK_INFRA_IPCIE_PIPE_CK 52 +#define CLK_INFRA_IPCIER_CK 53 +#define CLK_INFRA_IPCIEB_CK 54 +#define CLK_INFRA_TRNG_CK 55 +#define CLK_INFRA_AO_NR_CLK 46 /* APMIXEDSYS */ -#define CK_APMIXED_ARMPLL 0 -#define CK_APMIXED_NET2PLL 1 -#define CK_APMIXED_MMPLL 2 -#define CK_APMIXED_SGMPLL 3 -#define CK_APMIXED_WEDMCUPLL 4 -#define CK_APMIXED_NET1PLL 5 -#define CK_APMIXED_MPLL 6 -#define CK_APMIXED_APLL2 7 +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_NET2PLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_SGMPLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_NET1PLL 5 +#define CLK_APMIXED_MPLL 6 +#define CLK_APMIXED_APLL2 7 #define CLK_APMIXED_NR_CLK 8 /* SGMIISYS_0 */ -#define CK_SGM0_TX_EN 0 -#define CK_SGM0_RX_EN 1 -#define CK_SGM0_CK0_EN 2 -#define CK_SGM0_CDR_CK0_EN 3 +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGM0_CK0_EN 2 +#define CLK_SGM0_CDR_CK0_EN 3 #define CLK_SGMII0_NR_CLK 4 /* SGMIISYS_1 */ -#define CK_SGM1_TX_EN 0 -#define CK_SGM1_RX_EN 1 -#define CK_SGM1_CK1_EN 2 -#define CK_SGM1_CDR_CK1_EN 3 +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGM1_CK1_EN 2 +#define CLK_SGM1_CDR_CK1_EN 3 #define CLK_SGMII1_NR_CLK 4 /* ETHSYS */ -#define CK_ETH_FE_EN 0 -#define CK_ETH_GP2_EN 1 -#define CK_ETH_GP1_EN 2 -#define CK_ETH_WOCPU1_EN 3 -#define CK_ETH_WOCPU0_EN 4 +#define CLK_ETH_FE_EN 0 +#define CLK_ETH_GP2_EN 1 +#define CLK_ETH_GP1_EN 2 +#define CLK_ETH_WOCPU1_EN 3 +#define CLK_ETH_WOCPU0_EN 4 #define CLK_ETH_NR_CLK 5 #endif -- cgit v1.2.3