From ddde6b7cf8341a15ad46551dc611488e9a3f36e6 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue, 22 Aug 2006 10:38:18 +0200
Subject: Add a fix for a buggy USB device on the FO300 board.

---
 include/configs/TQM5200.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index f157d42fce3..89ec1bf7a9b 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -63,7 +63,7 @@
 #define CFG_DEVICE_NULLDEV		1	/* enable null device */
 #define CONFIG_SILENT_CONSOLE		1	/* enable silent startup */
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* used to detect S1 switch position */
-
+#define CONFIG_USB_BIN_FIXUP		1	/* for a buggy USB device */
 #if 0
 #define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED	1	/* silent console on PSC1 when S1 */
 							/* switch is closed */
-- 
cgit v1.3.1


From ed1cf8456f2a5a4efdb4bb3d04b503d78f410e9c Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Thu, 24 Aug 2006 00:26:42 +0200
Subject: Updates for MCC200 / PRS200 boards: - support for configurations with
 SDRAM or DDR memory, - support for highboot and lowboot - adjusting
 environment definitions

---
 CHANGELOG                |  5 +++++
 Makefile                 | 31 +++++++++++++++++++++-----
 board/mcc200/config.mk   |  2 +-
 board/mcc200/mcc200.c    |  4 ++++
 include/configs/mcc200.h | 57 +++++++++++++++++++++++++++++++++---------------
 5 files changed, 75 insertions(+), 24 deletions(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index 82be4e3d779..7975cf38a0d 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,11 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Updates for MCC200 / PRS200 boards:
+  - support for configurations with SDRAM or DDR memory,
+  - support for highboot and lowboot
+  - adjusting environment definitions
+
 * Add support for WTK FO300 board (TQM5200 based).
 
 * Fix TQM834x hang.
diff --git a/Makefile b/Makefile
index a78f35b6219..7542ab4dcc9 100644
--- a/Makefile
+++ b/Makefile
@@ -323,10 +323,15 @@ lite5200b_LOWBOOT_config:	unconfig
 	@./mkconfig -a IceCube  ppc mpc5xxx icecube
 
 mcc200_config	\
-mcc200_SDRAM	\
-mcc200_highboot	\
-mcc200_COM12	\
-mcc200_highboot_SDRAM:	unconfig
+mcc200_SDRAM_config	\
+mcc200_highboot_config	\
+mcc200_COM12_config	\
+mcc200_COM12_SDRAM_config	\
+mcc200_highboot_SDRAM_config	\
+prs200_config	\
+prs200_DDR_config	\
+prs200_highboot_config	\
+prs200_highboot_DDR_config:	unconfig
 	@ >include/config.h
 	@[ -n "$(findstring highboot,$@)" ] || \
 		{ echo "... with lowboot configuration" ; \
@@ -336,7 +341,18 @@ mcc200_highboot_SDRAM:	unconfig
 		  echo "... with highboot configuration" ; \
 		}
 	@[ -n "$(findstring _SDRAM,$@)" ] || \
-		{ echo "... with DDR" ; \
+		{ if [ -n "$(findstring mcc200,$@)" ]; \
+		  then \
+		  	echo "... with DDR" ; \
+		  else \
+			if [ -n "$(findstring _DDR,$@)" ];\
+			then \
+				echo "... with DDR" ; \
+			else \
+				echo "#define CONFIG_MCC200_SDRAM" >>include/config.h ;\
+				echo "... with SDRAM" ; \
+			fi; \
+		  fi; \
 		}
 	@[ -z "$(findstring _SDRAM,$@)" ] || \
 		{ echo "#define CONFIG_MCC200_SDRAM"	>>include/config.h ; \
@@ -346,7 +362,10 @@ mcc200_highboot_SDRAM:	unconfig
 		{ echo "#define CONFIG_CONSOLE_COM12"	>>include/config.h ; \
 		  echo "... with console on COM12" ; \
 		}
-	@./mkconfig -a mcc200 ppc mpc5xxx mcc200
+	@[ -z "$(findstring prs200,$@)" ] || \
+		{ echo "#define CONFIG_PRS200"  >>include/config.h ;\
+		}
+	@./mkconfig -n $@ -a mcc200 ppc mpc5xxx mcc200
 
 o2dnt_config:
 	@./mkconfig o2dnt ppc mpc5xxx o2dnt
diff --git a/board/mcc200/config.mk b/board/mcc200/config.mk
index a8225598cc1..192272334a9 100644
--- a/board/mcc200/config.mk
+++ b/board/mcc200/config.mk
@@ -22,7 +22,7 @@
 #
 
 #
-# MCC200 board:
+# MCC200, PRS200 boards:
 #
 #	Valid values for TEXT_BASE are:
 #
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
index 775030c17cb..9c5780998ea 100644
--- a/board/mcc200/mcc200.c
+++ b/board/mcc200/mcc200.c
@@ -197,7 +197,11 @@ long int initdram (int board_type)
 
 int checkboard (void)
 {
+#if defined(CONFIG_PRS200)
+	puts ("Board: PRS200\n");
+#else
 	puts ("Board: MCC200\n");
+#endif
 	return 0;
 }
 
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index 563f7978d5f..aead49a926b 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -55,16 +55,28 @@
  *
  *  CONFIG_PSC_CONSOLE must be undefined in this case.
  */
+#if !defined(CONFIG_PRS200)
+/* MCC200 configuration: */
 #ifdef CONFIG_CONSOLE_COM12
 #define CONFIG_QUART_CONSOLE	6	/* console is on UARTF of QUART2	*/
 #else
 #define CONFIG_QUART_CONSOLE	8	/* console is on UARTH of QUART2	*/
 #endif
+#else
+/* PRS200 configuration: */
+#undef CONFIG_QUART_CONSOLE
+#endif /* CONFIG_PRS200 */
 /*
  *  To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
  * and undefine CONFIG_QUART_CONSOLE.
  */
-/*#define CONFIG_PSC_CONSOLE	1	*/ /* console is on PSC1		*/
+#if !defined(CONFIG_PRS200)
+/* MCC200 configuration: */
+#undef CONFIG_PSC_CONSOLE
+#else
+/* PRS200 configuration: */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1		*/
+#endif
 #if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE)
 #error "Select only one console device!"
 #endif
@@ -103,33 +115,44 @@
 
 #undef	CONFIG_BOOTARGS
 
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
+#define XMK_STR(x)	#x
+#define MK_STR(x)	XMK_STR(x)
+
+#ifdef CONFIG_PRS200
+# define CFG__BOARDNAME "prs200"
+#else
+# define CFG__BOARDNAME "mcc200"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
-	"hostname=mcc200\0"						\
+	"hostname=" CFG__BOARDNAME "\0"					\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
+	"addcons=etenv bootargs ${bootargs} "				\
+		"console=${console},${baudrate}\0"			\
+	"flash_nfs=run nfsargs addip addcons;"				\
 		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
+	"flash_self=run ramargs addip addcons;"				\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"net_nfs=tftp 200000 ${bootfile};"				\
+		"run nfsargs addip addcons;bootm\0"			\
+	"console=ttyS0\0"						\
 	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=/tftpboot/mcc200/uImage\0"				\
-	"baudrate=115200\0"						\
-	"load=tftp 200000 /tftpboot/mcc200/u-boot.bin\0"		\
-	"update=protect off FFF00000 +${filesize};"			\
-		"era FFF00000 +${filesize};"				\
-		"cp.b 200000 FFF00000 ${filesize}\0"		        \
-	"serverip=192.168.1.1\0"					\
-	"ipaddr=192.168.133.144\0"					\
-	"netmask=255.255.0.0\0"						\
+	"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0"		\
+	"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0"	\
+	"text_base=" MK_STR(TEXT_BASE) "\0"				\
+	"update=protect off ${text_base} +${filesize};"			\
+		"era ${text_base} +${filesize};"			\
+		"cp.b 200000 ${text_base} ${filesize}\0"		\
 	"unlock=yes\0"							\
-	"ethaddr=00:02:44:7D:73:3B\0"					\
 	""
+#undef MK_STR
+#undef XMK_STR
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
@@ -314,7 +337,7 @@
  * One of four SC16C554 UARTs is selected with
  * A3-A4 (DA5-DA6) lines.
  */
-#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5)
+#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
 #define CFG_NS16550_COM1	(CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
 #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
 #define CFG_NS16550_COM1	(CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
-- 
cgit v1.3.1


From 113f64e09ac4905ddc330181c8761a4b29e82394 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Fri, 25 Aug 2006 01:38:04 +0200
Subject: Update for MCC200 / PRS200 boards: - auto-adjust console device for
 Linux. - fix typos.

---
 CHANGELOG                | 4 ++++
 Makefile                 | 2 ++
 include/configs/mcc200.h | 6 ++++--
 3 files changed, 10 insertions(+), 2 deletions(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index b6dc06784c7..af180eed169 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,10 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Update for MCC200 / PRS200 boards:
+  - auto-adjust console device for Linux.
+  - fix typos.
+
 * Add a fix for a buggy USB device on the FO300 board.
 
 * Updates for MCC200 / PRS200 boards:
diff --git a/Makefile b/Makefile
index 7542ab4dcc9..9bf7c49fb9c 100644
--- a/Makefile
+++ b/Makefile
@@ -327,6 +327,8 @@ mcc200_SDRAM_config	\
 mcc200_highboot_config	\
 mcc200_COM12_config	\
 mcc200_COM12_SDRAM_config	\
+mcc200_COM12_highboot_config	\
+mcc200_COM12_highboot_SDRAM_config	\
 mcc200_highboot_SDRAM_config	\
 prs200_config	\
 prs200_DDR_config	\
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index aead49a926b..df3d68e9f77 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -120,8 +120,10 @@
 
 #ifdef CONFIG_PRS200
 # define CFG__BOARDNAME "prs200"
+# define LINUX_CONSOLE  "ttyS0"
 #else
 # define CFG__BOARDNAME "mcc200"
+# define LINUX_CONSOLE  "ttyEU7"
 #endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
@@ -133,7 +135,7 @@
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
-	"addcons=etenv bootargs ${bootargs} "				\
+	"addcons=setenv bootargs ${bootargs} "				\
 		"console=${console},${baudrate}\0"			\
 	"flash_nfs=run nfsargs addip addcons;"				\
 		"bootm ${kernel_addr}\0"				\
@@ -141,7 +143,7 @@
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};"				\
 		"run nfsargs addip addcons;bootm\0"			\
-	"console=ttyS0\0"						\
+	"console=" MK_STR(LINUX_CONSOLE) "\0"				\
 	"rootpath=/opt/eldk/ppc_6xx\0"					\
 	"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0"		\
 	"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0"	\
-- 
cgit v1.3.1


From 3b0ff842bf70baf1f370c8e76e8f33a0f9904c1b Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@nyx.denx.de>
Date: Fri, 25 Aug 2006 11:47:06 +0200
Subject: Fix typo in MCC200/PRS200 configuration

---
 include/configs/mcc200.h | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'include')

diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index df3d68e9f77..14a5bae36c7 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -115,15 +115,15 @@
 
 #undef	CONFIG_BOOTARGS
 
-#define XMK_STR(x)	#x
-#define MK_STR(x)	XMK_STR(x)
+#define XMK_STR(x)		#x
+#define MK_STR(x)		XMK_STR(x)
 
 #ifdef CONFIG_PRS200
-# define CFG__BOARDNAME "prs200"
-# define LINUX_CONSOLE  "ttyS0"
+# define CFG__BOARDNAME		"prs200"
+# define CFG__LINUX_CONSOLE	"ttyS0"
 #else
-# define CFG__BOARDNAME "mcc200"
-# define LINUX_CONSOLE  "ttyEU7"
+# define CFG__BOARDNAME		"mcc200"
+# define CFG__LINUX_CONSOLE	"ttyEU7"
 #endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
@@ -143,7 +143,7 @@
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};"				\
 		"run nfsargs addip addcons;bootm\0"			\
-	"console=" MK_STR(LINUX_CONSOLE) "\0"				\
+	"console=" LINUX_CONSOLE "\0"				\
 	"rootpath=/opt/eldk/ppc_6xx\0"					\
 	"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0"		\
 	"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0"	\
-- 
cgit v1.3.1


From 16850919ff8666f20d047cb83b4ee77581336515 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Sun, 27 Aug 2006 18:10:01 +0200
Subject: Code cleanup

---
 CHANGELOG                 |  2 ++
 board/amcc/common/flash.c | 60 +++++++++++++++++++++++------------------------
 board/cpu87/cpu87.c       |  8 +++----
 board/mcc200/mcc200.c     |  4 ++--
 board/tqm5200/tqm5200.c   |  6 ++---
 cpu/i386/sc520.c          |  2 +-
 cpu/i386/sc520_asm.S      | 12 +++++-----
 cpu/ppc4xx/440spe_pcie.c  |  2 +-
 include/configs/CPU87.h   |  2 +-
 9 files changed, 50 insertions(+), 48 deletions(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index af180eed169..e326782373e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Code cleanup
+
 * Update for MCC200 / PRS200 boards:
   - auto-adjust console device for Linux.
   - fix typos.
diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c
index a0acbba70c3..e6429ecd136 100644
--- a/board/amcc/common/flash.c
+++ b/board/amcc/common/flash.c
@@ -35,7 +35,7 @@
 #include <ppc4xx.h>
 #include <asm/processor.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -76,7 +76,7 @@ void flash_print_info(flash_info_t * info)
 	case FLASH_MAN_SST:
 		printf("SST ");
 		break;
-        case FLASH_MAN_MX:
+	case FLASH_MAN_MX:
 		printf ("MACRONIX ");
 		break;
 	default:
@@ -223,75 +223,75 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 		return (0);	/* no or unknown flash  */
 	}
 
-	value = addr2[1];	/* device ID            */
+	value = addr2[1];	/* device ID */
 	DEBUGF("\nFLASH DEVICEID: %x\n", value);
 
 	switch (value) {
 	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
-		info->size = 0x0080000;	/* => 512 ko */
+		info->size = 0x0080000;		/* => 512 KiB */
 		break;
 
 	case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
-		info->size = 0x0080000;	/* => 512 ko */
+		info->size = 0x0080000;		/* => 512 KiB */
 		break;
 
 	case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
-		info->size = 0x0080000;	/* => 512 ko */
+		info->size = 0x0080000;		/* => 512 KiB */
 		break;
 
 	case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
 		info->flash_id += FLASH_AMD016;
 		info->sector_count = 32;
-		info->size = 0x00200000;
-		break;		/* => 2 MB              */
+		info->size = 0x00200000;	/* => 2 MiB */
+		break;
 
 	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
 		info->flash_id += FLASH_AMDLV033C;
 		info->sector_count = 64;
-		info->size = 0x00400000;
-		break;		/* => 4 MB              */
+		info->size = 0x00400000;	/* => 4 MiB */
+		break;
 
 	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
 		info->flash_id += FLASH_AM400T;
 		info->sector_count = 11;
-		info->size = 0x00080000;
-		break;		/* => 0.5 MB            */
+		info->size = 0x00080000;	/* => 512 KiB */
+		break;
 
 	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
 		info->flash_id += FLASH_AM400B;
 		info->sector_count = 11;
-		info->size = 0x00080000;
-		break;		/* => 0.5 MB            */
+		info->size = 0x00080000;	/* => 512 KiB */
+		break;
 
 	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
 		info->flash_id += FLASH_AM800T;
 		info->sector_count = 19;
-		info->size = 0x00100000;
-		break;		/* => 1 MB              */
+		info->size = 0x00100000;	/* => 1 MiB */
+		break;
 
 	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
 		info->flash_id += FLASH_AM800B;
 		info->sector_count = 19;
-		info->size = 0x00100000;
-		break;		/* => 1 MB              */
+		info->size = 0x00100000;	/* => 1 MiB */
+		break;
 
 	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
 		info->flash_id += FLASH_AM160T;
 		info->sector_count = 35;
-		info->size = 0x00200000;
-		break;		/* => 2 MB              */
+		info->size = 0x00200000;	/* => 2 MiB */
+		break;
 
 	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
 		info->flash_id += FLASH_AM160B;
 		info->sector_count = 35;
-		info->size = 0x00200000;
-		break;		/* => 2 MB              */
+		info->size = 0x00200000;	/* => 2 MiB */
+		break;
 
 	default:
 		info->flash_id = FLASH_UNKNOWN;
@@ -306,7 +306,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 			info->start[i] = base + (i * 0x00010000);
 	} else {
 		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type        */
+			/* set sector offsets for bottom boot block type */
 			info->start[0] = base + 0x00000000;
 			info->start[1] = base + 0x00004000;
 			info->start[2] = base + 0x00006000;
@@ -316,7 +316,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 				    base + (i * 0x00010000) - 0x00030000;
 			}
 		} else {
-			/* set sector offsets for top boot block type           */
+			/* set sector offsets for top boot block type */
 			i = info->sector_count - 1;
 			info->start[i--] = base + info->size - 0x00004000;
 			info->start[i--] = base + info->size - 0x00006000;
@@ -666,7 +666,7 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
 		return (0);	/* no or unknown flash  */
 	}
 
-	value = addr2[1];	/* device ID            */
+	value = addr2[1];	/* device ID */
 
 	DEBUGF("\nFLASH DEVICEID: %x\n", value);
 
@@ -675,17 +675,17 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
 	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
+		info->size = 0x00400000;  break;	/* => 4 MiB	*/
 
 	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
 		info->flash_id += FLASH_AM320B;
 		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
+		info->size = 0x00400000;  break;	/* => 4 MiB	*/
 
 	case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
 		info->flash_id += FLASH_STMW320DT;
 		info->sector_count = 67;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
+		info->size = 0x00400000;  break;	/* => 4 MiB	*/
 
 	case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T:
 		info->flash_id += FLASH_MXLV320T;
@@ -743,7 +743,7 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
 			info->start[i] = base + i * 0x00010000;
 	} else {
 		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type        */
+			/* set sector offsets for bottom boot block type */
 			info->start[0] = base + 0x00000000;
 			info->start[1] = base + 0x00004000;
 			info->start[2] = base + 0x00006000;
@@ -753,7 +753,7 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
 				    base + (i * 0x00010000) - 0x00030000;
 			}
 		} else {
-			/* set sector offsets for top boot block type           */
+			/* set sector offsets for top boot block type */
 			i = info->sector_count - 1;
 			info->start[i--] = base + info->size - 0x00004000;
 			info->start[i--] = base + info->size - 0x00006000;
diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c
index e8c2614eb47..9fecdd0dfef 100644
--- a/board/cpu87/cpu87.c
+++ b/board/cpu87/cpu87.c
@@ -294,15 +294,15 @@ long int initdram (int board_type)
 	 */
 	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
 			  (uchar *) CFG_SDRAM_BASE);
-	
+
 	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
 			  (uchar *) CFG_SDRAM_BASE);
-	
+
 	size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL,
 			  (uchar *) CFG_SDRAM_BASE);
-	
+
 	psize = max(size8,max(size9,size10));
-	
+
 	if (psize == size8) {
 		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
 				  (uchar *) CFG_SDRAM_BASE);
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
index 9c5780998ea..71a691b5dbf 100644
--- a/board/mcc200/mcc200.c
+++ b/board/mcc200/mcc200.c
@@ -265,8 +265,8 @@ int misc_init_r (void)
 		*(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
 		printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
 		flash_info[0].size = 32 << 20;
-		for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20); 
-			flash_info[0].start[snum] < flash_sup_end; 
+		for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
+			flash_info[0].start[snum] < flash_sup_end;
 			snum++);
 		flash_info[0].sector_count = snum;
 	}
diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c
index c8350ab3b5d..2a0d542ef8b 100644
--- a/board/tqm5200/tqm5200.c
+++ b/board/tqm5200/tqm5200.c
@@ -743,7 +743,7 @@ int board_early_init_f (void)
 
 	/* Read in TIMER_3 pin status */
 	timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
-	
+
 #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
 	/* Force silent console mode if S1 switch
 	 * is in closed position (TIMER_3 pin status is LOW). */
@@ -757,5 +757,5 @@ int board_early_init_f (void)
 
 	return 0;
 }
-#endif
-#endif
+#endif	/* CONFIG_FO300 */
+#endif	/* CONFIG_BOARD_EARLY_INIT_F */
diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index 1c4370b0819..d0a73418827 100644
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -149,7 +149,7 @@ unsigned long init_sc520_dram(void)
 	/* these memory control registers are set up in the assember part,
 	 * in sc520_asm.S, during 'mem_init'.  If we muck with them here,
 	 * after we are running a stack in RAM, we have troubles.  Besides,
-	 * these refresh and delay values are better ? simply specified 
+	 * these refresh and delay values are better ? simply specified
 	 * outright in the include/configs/{cfg} file since the HW designer
 	 * simply dictates it.
 	 */
diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S
index e1fa37a4a61..8fc713d93bb 100644
--- a/cpu/i386/sc520_asm.S
+++ b/cpu/i386/sc520_asm.S
@@ -462,7 +462,7 @@ emptybank:
 
 #if defined CFG_SDRAM_DRCTMCTL
 	/* just have your hardware desinger _GIVE_ you what you need here! */
-	movl    $DRCTMCTL, %edi   
+	movl    $DRCTMCTL, %edi
 	movb    $CFG_SDRAM_DRCTMCTL,%al
 	movb    (%edi), %al
 #else
@@ -477,7 +477,7 @@ emptybank:
 #ifdef CFG_SDRAM_CAS_LATENCY_3T
 	orb     $0x10, %al
 #endif
-	movb    %al, (%edi) 
+	movb    %al, (%edi)
 #endif
 #endif
 	movl    $DRCCTL, %edi            /* DRAM Control register */
@@ -537,7 +537,7 @@ bank0: 	movl	(%edi), %eax
 	movl	%eax, %ebx
 
 
-done:	
+done:
 	movl	%ebx, %eax
 
 #if CFG_SDRAM_ECC_ENABLE
@@ -547,7 +547,7 @@ done:
 	movl	$0x1, %edi
 memtest0:
 	movb	$0xa5, (%edi)
-	cmpb    $0xa5, (%edi) 
+	cmpb    $0xa5, (%edi)
 	jne	out
 	shrl	$1, %ecx
 	andl	%ecx,%ecx
@@ -571,11 +571,11 @@ set_ecc:
 			/* enable NMI mapping for ECC */
 	movl    $ECCINT, %edi
 	mov	$0x10, %al
-	movb    %al, (%edi) 
+	movb    %al, (%edi)
 			/* Turn on ECC */
 	movl    $ECCCTL, %edi
 	mov	$0x05, %al
-	movb    %al, (%edi) 
+	movb    %al, (%edi)
 #endif
 out:
 	movl	%ebx, %eax
diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c
index 2e920aadf01..b2621c2ec5b 100644
--- a/cpu/ppc4xx/440spe_pcie.c
+++ b/cpu/ppc4xx/440spe_pcie.c
@@ -169,7 +169,7 @@ static void ppc440spe_setup_utl(u32 port) {
 		break;
 	}
 	utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
-	
+
 	/*
 	 * Set buffer allocations and then assert VRB and TXE.
 	 */
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index 7a1dada2db5..ce969ecdd18 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -527,7 +527,7 @@
 			 PSDMR_LDOTOPRE_1C		|\
 			 PSDMR_WRC_1C			|\
 			 PSDMR_CL_2)
-			 
+
 /*
  * Init Memory Controller:
  *
-- 
cgit v1.3.1


From 21a9cc028d00c50f542e25d58201e3debecd5166 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Tue, 29 Aug 2006 10:49:11 +0200
Subject: Fix typo.

---
 CHANGELOG                | 2 ++
 include/configs/mcc200.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index e326782373e..46e77e7c462 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Fix typo.
+
 * Code cleanup
 
 * Update for MCC200 / PRS200 boards:
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index 14a5bae36c7..fc5781e438f 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -143,7 +143,7 @@
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};"				\
 		"run nfsargs addip addcons;bootm\0"			\
-	"console=" LINUX_CONSOLE "\0"				\
+	"console=" CFG__LINUX_CONSOLE "\0"				\
 	"rootpath=/opt/eldk/ppc_6xx\0"					\
 	"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0"		\
 	"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0"	\
-- 
cgit v1.3.1


From 0fd30252c840ee54d2a80475d6504766d43b8add Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Wed, 30 Aug 2006 23:02:10 +0200
Subject: Make the serial driver framework work with CONFIG_SERIAL_MULTI
 enabled

---
 CHANGELOG                |   3 ++
 common/serial.c          |  28 +++++++++++-
 drivers/ns9750_serial.c  |   4 ++
 drivers/serial.c         | 111 +++++++++++++++++++++++++++++++++++++++++++++++
 include/configs/mcc200.h |   7 ++-
 include/serial.h         |   7 +++
 6 files changed, 157 insertions(+), 3 deletions(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index 02ccd30a3e7..87341755e27 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Make the serial driver framework work with CONFIG_SERIAL_MULTI
+  enabled
+
 * PCIe endpoint support for AMCC Yucca 440SPe board
   Patch by Tirumala R Marri, 26 Aug 2006
 
diff --git a/common/serial.c b/common/serial.c
index 38057d21f6c..605d4e34be0 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -42,7 +42,19 @@ struct serial_device *default_serial_console (void)
 	return &serial_scc_device;
 #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
    || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
-#if defined(CONFIG_UART1_CONSOLE)
+#if defined(CONFIG_CONS_INDEX) && defined(CFG_NS16550_SERIAL)
+#if (CONFIG_CONS_INDEX==1)
+	return &eserial1_device;
+#elif (CONFIG_CONS_INDEX==2)
+	return &eserial2_device;
+#elif (CONFIG_CONS_INDEX==3)
+	return &eserial3_device;
+#elif (CONFIG_CONS_INDEX==4)
+	return &eserial4_device;
+#else
+#error "Bad CONFIG_CONS_INDEX."
+#endif
+#elif defined(CONFIG_UART1_CONSOLE)
 		return &serial1_device;
 #else
 		return &serial0_device;
@@ -84,6 +96,20 @@ void serial_initialize (void)
 	serial_register(&serial1_device);
 #endif
 
+#if defined(CFG_NS16550_SERIAL)
+#if defined(CFG_NS16550_COM1)
+	serial_register(&eserial1_device);
+#endif
+#if defined(CFG_NS16550_COM2)
+	serial_register(&eserial2_device);
+#endif
+#if defined(CFG_NS16550_COM3)
+	serial_register(&eserial3_device);
+#endif
+#if defined(CFG_NS16550_COM4)
+	serial_register(&eserial4_device);
+#endif
+#endif /* CFG_NS16550_SERIAL */
 	serial_assign (default_serial_console ()->name);
 }
 
diff --git a/drivers/ns9750_serial.c b/drivers/ns9750_serial.c
index 8dff3677450..02c0d395209 100644
--- a/drivers/ns9750_serial.c
+++ b/drivers/ns9750_serial.c
@@ -35,6 +35,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if !defined(CONFIG_CONS_INDEX)
+#error "No console index specified."
+#endif
+
 #define CONSOLE CONFIG_CONS_INDEX
 
 static unsigned int calcBitrateRegister( void );
diff --git a/drivers/serial.c b/drivers/serial.c
index 228781b46a6..8d1ae96bf85 100644
--- a/drivers/serial.c
+++ b/drivers/serial.c
@@ -30,10 +30,20 @@
 #include <ns87308.h>
 #endif
 
+#if defined (CONFIG_SERIAL_MULTI)
+#include <serial.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #if !defined(CONFIG_CONS_INDEX)
+#if defined (CONFIG_SERIAL_MULTI)
+/*   with CONFIG_SERIAL_MULTI we might have no console
+ *  on these devices 
+ */
+#else
 #error	"No console index specified."
+#endif /* CONFIG_SERIAL_MULTI */
 #elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4)
 #error	"Invalid console index value."
 #endif
@@ -75,7 +85,42 @@ static NS16550_t serial_ports[4] = {
 };
 
 #define PORT	serial_ports[port-1]
+#if defined(CONFIG_CONS_INDEX)
 #define CONSOLE	(serial_ports[CONFIG_CONS_INDEX-1])
+#endif
+
+#if defined(CONFIG_SERIAL_MULTI)
+
+/* Multi serial device functions */
+#define DECLARE_ESERIAL_FUNCTIONS(port) \
+    int  eserial##port##_init (void) {\
+	int clock_divisor; \
+	clock_divisor = calc_divisor(serial_ports[port-1]); \
+	NS16550_init(serial_ports[port-1], clock_divisor); \
+	return(0);}\
+    void eserial##port##_setbrg (void) {\
+	serial_setbrg_dev(port);}\
+    int  eserial##port##_getc (void) {\
+	return serial_getc_dev(port);}\
+    int  eserial##port##_tstc (void) {\
+	return serial_tstc_dev(port);}\
+    void eserial##port##_putc (const char c) {\
+	serial_putc_dev(port, c);}\
+    void eserial##port##_puts (const char *s) {\
+	serial_puts_dev(port, s);}
+
+/* Serial device descriptor */
+#define INIT_ESERIAL_STRUCTURE(port,name,bus) {\
+	name,\
+	bus,\
+	eserial##port##_init,\
+	eserial##port##_setbrg,\
+	eserial##port##_getc,\
+	eserial##port##_tstc,\
+	eserial##port##_putc,\
+	eserial##port##_puts, }
+
+#endif /* CONFIG_SERIAL_MULTI */
 
 static int calc_divisor (NS16550_t port)
 {
@@ -103,6 +148,7 @@ static int calc_divisor (NS16550_t port)
 
 }
 
+#if !defined(CONFIG_SERIAL_MULTI)
 int serial_init (void)
 {
 	int clock_divisor;
@@ -130,6 +176,7 @@ int serial_init (void)
 
 	return (0);
 }
+#endif
 
 void
 _serial_putc(const char c,const int port)
@@ -176,40 +223,104 @@ _serial_setbrg (const int port)
 	NS16550_reinit(PORT, clock_divisor);
 }
 
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void
+serial_putc_dev(unsigned int dev_index,const char c)
+{
+	_serial_putc(c,dev_index);
+}
+#else
 void
 serial_putc(const char c)
 {
 	_serial_putc(c,CONFIG_CONS_INDEX);
 }
+#endif
 
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void 
+serial_putc_raw_dev(unsigned int dev_index,const char c)
+{
+	_serial_putc_raw(c,dev_index);
+}
+#else
 void
 serial_putc_raw(const char c)
 {
 	_serial_putc_raw(c,CONFIG_CONS_INDEX);
 }
+#endif
 
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void
+serial_puts_dev(unsigned int dev_index,const char *s)
+{
+	_serial_puts(s,dev_index);
+}
+#else
 void
 serial_puts(const char *s)
 {
 	_serial_puts(s,CONFIG_CONS_INDEX);
 }
+#endif
 
+#if defined(CONFIG_SERIAL_MULTI)
+static inline int
+serial_getc_dev(unsigned int dev_index)
+{
+	return _serial_getc(dev_index);
+}
+#else
 int
 serial_getc(void)
 {
 	return _serial_getc(CONFIG_CONS_INDEX);
 }
+#endif
 
+#if defined(CONFIG_SERIAL_MULTI)
+static inline int
+serial_tstc_dev(unsigned int dev_index)
+{
+	return _serial_tstc(dev_index);
+}
+#else
 int
 serial_tstc(void)
 {
 	return _serial_tstc(CONFIG_CONS_INDEX);
 }
+#endif
 
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void
+serial_setbrg_dev(unsigned int dev_index)
+{
+	_serial_setbrg(dev_index);
+}
+#else
 void
 serial_setbrg(void)
 {
 	_serial_setbrg(CONFIG_CONS_INDEX);
 }
+#endif
+
+#if defined(CONFIG_SERIAL_MULTI)
+
+DECLARE_ESERIAL_FUNCTIONS(1);
+struct serial_device eserial1_device = 
+	INIT_ESERIAL_STRUCTURE(1,"eserial0","EUART1");
+DECLARE_ESERIAL_FUNCTIONS(2);
+struct serial_device eserial2_device =
+	INIT_ESERIAL_STRUCTURE(2,"eserial1","EUART2");
+DECLARE_ESERIAL_FUNCTIONS(3);
+struct serial_device eserial3_device =
+	INIT_ESERIAL_STRUCTURE(3,"eserial2","EUART3");
+DECLARE_ESERIAL_FUNCTIONS(4);
+struct serial_device eserial4_device =
+	INIT_ESERIAL_STRUCTURE(4,"eserial3","EUART4");
+#endif /* CONFIG_SERIAL_MULTI */
 
 #endif
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index fc5781e438f..61014ecd1f2 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -72,12 +72,15 @@
  */
 #if !defined(CONFIG_PRS200)
 /* MCC200 configuration: */
-#undef CONFIG_PSC_CONSOLE
+#define CONFIG_SERIAL_MULTI	1
+#define CONFIG_PSC_CONSOLE	1	/* PSC1 may be COM */
+#define CONFIG_PSC_CONSOLE2	2	/* PSC2 is PSoC */
 #else
 /* PRS200 configuration: */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1		*/
 #endif
-#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE)
+#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \
+	!defined(CONFIG_SERIAL_MULTI)
 #error "Select only one console device!"
 #endif
 #define CONFIG_BAUDRATE		115200
diff --git a/include/serial.h b/include/serial.h
index 8c7b1c26c13..48800595d78 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -26,6 +26,13 @@ extern struct serial_device * default_serial_console (void);
    || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
 extern struct serial_device serial0_device;
 extern struct serial_device serial1_device;
+#if defined(CFG_NS16550_SERIAL)
+extern struct serial_device eserial1_device;
+extern struct serial_device eserial2_device;
+extern struct serial_device eserial3_device;
+extern struct serial_device eserial4_device;
+#endif /* CFG_NS16550_SERIAL */
+
 #endif
 
 
-- 
cgit v1.3.1


From e8143e72e1cbe2f771258533e26ee2105a8768a7 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Wed, 30 Aug 2006 23:09:00 +0200
Subject: Add splashscreen support for MCC200 board.

---
 CHANGELOG                |   2 +
 board/mcc200/Makefile    |   2 +-
 board/mcc200/lcd.c       | 190 +++++++++++++++++++++++++++++++++++++++++++++++
 common/lcd.c             |  28 ++++++-
 cpu/mpc5xxx/serial.c     |  56 ++++++++++++++
 include/configs/mcc200.h |  15 ++++
 include/lcd.h            |   9 ++-
 7 files changed, 297 insertions(+), 5 deletions(-)
 create mode 100644 board/mcc200/lcd.c

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index 87341755e27..7df923c047d 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Add splashscreen support for MCC200 board.
+
 * Make the serial driver framework work with CONFIG_SERIAL_MULTI
   enabled
 
diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile
index 7fdc088e9c1..bd75859f615 100644
--- a/board/mcc200/Makefile
+++ b/board/mcc200/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= $(BOARD).o
+OBJS	:= $(BOARD).o lcd.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)
diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c
new file mode 100644
index 00000000000..b2625160a5e
--- /dev/null
+++ b/board/mcc200/lcd.c
@@ -0,0 +1,190 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <mpc5xxx.h>
+
+#ifdef CONFIG_LCD
+
+#define SWAPPED_LCD
+/*
+ *  The name of the device used for communication
+ * with the PSoC.
+ */
+#define PSOC_PSC	MPC5XXX_PSC2
+#define PSOC_BAUD	500000UL
+
+#define RTS_ASSERT	1
+#define RTS_NEGATE	0
+#define CTS_ASSERT	1
+#define CTS_NEGATE	0
+
+/*
+ * Dimensions in pixels
+ */
+#define LCD_WIDTH	160
+#define LCD_HEIGHT	100
+
+/*
+ * Dimensions in bytes
+ */
+#define LCD_BUF_SIZE	((LCD_WIDTH*LCD_HEIGHT)>>3)
+
+#if LCD_BPP != LCD_MONOCHROME
+#error "MCC200 support only monochrome displays (1 bpp)!"
+#endif
+
+#define PSOC_RETRIES	10	/* each of PSOC_WAIT_TIME */
+#define PSOC_WAIT_TIME	10	/* usec */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * LCD information
+ */
+vidinfo_t panel_info = {
+	LCD_WIDTH, LCD_HEIGHT, LCD_BPP
+};
+
+int lcd_line_length;
+
+int lcd_color_fg;
+int lcd_color_bg;
+
+/*
+ * Frame buffer memory information
+ */
+void *lcd_base;			/* Start of framebuffer memory  */
+void *lcd_console_address;	/* Start of console buffer      */
+
+short console_col = 0;
+short console_row = 0;
+
+/*
+ *  The device we use to communicate with PSoC
+ */
+int serial_inited = 0;
+
+/*
+ * Exported functions
+ */
+void lcd_initcolregs (void);
+void lcd_ctrl_init (void *lcdbase);
+void lcd_enable (void);
+
+/*
+ *  Imported functions to support the PSoC protocol
+ */
+extern int serial_init_dev (unsigned long dev_base);
+extern void serial_setrts_dev (unsigned long dev_base, int s);
+extern int serial_getcts_dev (unsigned long dev_base);
+extern void serial_putc_raw_dev(unsigned long dev_base, const char c);
+
+/*
+ *  Just stubs for our driver, needed for compiling compabilty with
+ * the common LCD driver code.
+ */
+void lcd_initcolregs (void)
+{
+}
+
+void lcd_ctrl_init (void *lcdbase)
+{
+}
+
+/*
+ * Function sends the contents of the frame-buffer to the LCD
+ */
+void lcd_enable (void)
+{
+	int i, retries, fb_size;
+
+	if (!serial_inited) {
+		unsigned long baud;
+
+		baud = gd->baudrate;
+		gd->baudrate = PSOC_BAUD;
+		serial_init_dev(PSOC_PSC);
+		gd->baudrate = baud;
+		serial_setrts_dev (PSOC_PSC, RTS_ASSERT);
+		serial_inited = 1;
+	}
+
+	/*
+	 *  Implement PSoC communication protocol:
+	 * 1. Assert RTS, wait CTS assertion
+	 * 2. Transmit data
+	 * 3. Negate RTS, wait CTS negation
+	 */
+
+	/* 1 */
+	serial_setrts_dev (PSOC_PSC, RTS_ASSERT);
+	for (retries = PSOC_RETRIES; retries; retries--) {
+		if (serial_getcts_dev(PSOC_PSC) == CTS_ASSERT)
+			break;
+		udelay (PSOC_WAIT_TIME);
+	}
+	if (!retries) {
+		printf ("%s Error: PSoC doesn't respond on "
+			"RTS ASSERT\n",	__FUNCTION__);
+	}
+
+	/* 2 */
+	fb_size = panel_info.vl_row * (panel_info.vl_col >> 3);
+
+#if !defined(SWAPPED_LCD)
+	for (i=0; i<fb_size; i++) {
+		serial_putc_raw_dev (PSOC_PSC, ((char *)lcd_base)[i]);
+	}
+#else
+    {
+	int x, y, pwidth;
+	char *p = (char *)lcd_base;
+
+	pwidth = ((panel_info.vl_col+7) >> 3);
+	for (y=0; y<panel_info.vl_row; y++) {
+		i = y * pwidth;
+		for (x=0; x<pwidth; x+=5) {
+			serial_putc_raw_dev (PSOC_PSC, (p[i+x+2]<<4 & 0xF0) | (p[i+x+3]>>4 & 0x0F));
+			serial_putc_raw_dev (PSOC_PSC, (p[i+x+3]<<4 & 0xF0) | (p[i+x+4]>>4 & 0x0F));
+			serial_putc_raw_dev (PSOC_PSC, (p[i+x+4]<<4 & 0xF0) | (p[i+x]>>4 & 0x0F));
+			serial_putc_raw_dev (PSOC_PSC, (p[i+x]<<4 & 0xF0) | (p[i+x+1]>>4 & 0x0F));
+			serial_putc_raw_dev (PSOC_PSC, (p[i+x+1]<<4 & 0xF0) | (p[i+x+2]>>4 & 0x0F));
+		}
+	}
+    }
+#endif
+
+	/* 3 */
+	serial_setrts_dev (PSOC_PSC, RTS_NEGATE);
+	for (retries = PSOC_RETRIES; retries; retries--) {
+		if (serial_getcts_dev(PSOC_PSC) == CTS_NEGATE)
+			break;
+		udelay (PSOC_WAIT_TIME);
+	}
+	if (!retries) {
+		printf ("%s Error: PSoC doesn't respond on "
+			"RTS NEGATE\n",	__FUNCTION__);
+	}
+
+	return;
+}
+#endif /* CONFIG_LCD */
diff --git a/common/lcd.c b/common/lcd.c
index 0be1912a359..d79350f2347 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -585,6 +585,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	uchar *bmap;
 	ushort padded_line;
 	unsigned long width, height;
+	unsigned long pwidth = panel_info.vl_col;
 	unsigned colors,bpix;
 	unsigned long compression;
 #if defined(CONFIG_PXA250)
@@ -628,6 +629,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		cmap = (ushort *)fbi->palette;
 #elif defined(CONFIG_MPC823)
 		cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
+#elif defined(CONFIG_MCC200)
+		/* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
 #else
 # error "Don't know location of color map"
 #endif
@@ -652,9 +655,28 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		}
 	}
 
+	/*
+	 *  BMP format for Monochrome assumes that the state of a
+	 * pixel is described on a per Bit basis, not per Byte.
+	 *  So, in case of Monochrome BMP we should align widths
+	 * on a byte boundary and convert them from Bit to Byte
+	 * units.
+	 *  Probably, PXA250 and MPC823 process 1bpp BMP images in 
+	 * their own ways, so make the converting to be MCC200 
+	 * specific.
+	 */
+#if defined(CONFIG_MCC200)
+	if (bpix==1)
+	{
+		width = ((width + 7) & ~7) >> 3;
+		x     = ((x + 7) & ~7) >> 3;
+		pwidth= ((pwidth + 7) & ~7) >> 3;
+	}
+#endif
+
 	padded_line = (width&0x3) ? ((width&~0x3)+4) : (width);
-	if ((x + width)>panel_info.vl_col)
-		width = panel_info.vl_col - x;
+	if ((x + width)>pwidth)
+		width = pwidth - x;
 	if ((y + height)>panel_info.vl_row)
 		height = panel_info.vl_row - y;
 
@@ -666,7 +688,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		for (j = 0; j < width ; j++)
 #if defined(CONFIG_PXA250)
 			*(fb++)=*(bmap++);
-#elif defined(CONFIG_MPC823)
+#elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
 			*(fb++)=255-*(bmap++);
 #endif
 		bmap += (width - padded_line);
diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c
index 6cb523d3c7b..430d63f7464 100644
--- a/cpu/mpc5xxx/serial.c
+++ b/cpu/mpc5xxx/serial.c
@@ -165,6 +165,25 @@ void serial_putc(const char c)
 	psc->psc_buffer_8 = c;
 }
 
+#if defined(CONFIG_SERIAL_MULTI)
+void serial_putc_raw_dev(unsigned long dev_base, const char c)
+#else
+void serial_putc_raw(const char c)
+#endif
+{
+#if defined(CONFIG_SERIAL_MULTI)
+	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+#else
+	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#endif
+	/* Wait for last character to go. */
+	while (!(psc->psc_status & PSC_SR_TXEMP))
+		;
+
+	psc->psc_buffer_8 = c;
+}
+
+
 #if defined(CONFIG_SERIAL_MULTI)
 void serial_puts_dev (unsigned long dev_base, const char *s)
 #else
@@ -239,6 +258,43 @@ void serial_setbrg(void)
 	psc->ctlr =  div & 0xff;
 }
 
+#if defined(CONFIG_SERIAL_MULTI)
+void serial_setrts_dev (unsigned long dev_base, int s)
+#else
+void serial_setrts(int s)
+#endif
+{
+#if defined(CONFIG_SERIAL_MULTI)
+	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+#else
+	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#endif
+
+	if (s) {
+		/* Assert RTS (become LOW) */
+		psc->op1 = 0x1;
+	}
+	else {
+		/* Negate RTS (become HIGH) */
+		psc->op0 = 0x1;
+	}
+}
+
+#if defined(CONFIG_SERIAL_MULTI)
+int serial_getcts_dev (unsigned long dev_base)
+#else
+int serial_getcts(void)
+#endif
+{
+#if defined(CONFIG_SERIAL_MULTI)
+	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+#else
+	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#endif
+
+	return (psc->ip & 0x1) ? 0 : 1;
+}
+
 #if defined(CONFIG_SERIAL_MULTI)
 int serial0_init(void)
 {
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index 61014ecd1f2..e95d68bfb88 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -258,12 +258,27 @@
 /* #define CONFIG_FEC_10MBIT 1 */
 #define CONFIG_PHY_ADDR		1
 
+/*
+ * LCD Splash Screen
+ */
+#define CONFIG_LCD		1
+#if defined(CONFIG_LCD)
+#define CONFIG_SPLASH_SCREEN	1
+#define CFG_CONSOLE_IS_IN_ENV	1
+#define LCD_BPP		LCD_MONOCHROME
+#endif
+
 /*
  * GPIO configuration
  */
 /* 0x10000004 = 32MB SDRAM */
 /* 0x90000004 = 64MB SDRAM */
+#if defined(CONFIG_LCD)
+/* set PSC2 in UART mode */
+#define CFG_GPS_PORT_CONFIG	0x00000044
+#else
 #define CFG_GPS_PORT_CONFIG	0x00000004
+#endif
 
 /*
  * Miscellaneous configurable options
diff --git a/include/lcd.h b/include/lcd.h
index 7e23736bca9..b688583828b 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -148,7 +148,14 @@ typedef struct vidinfo {
 
 extern vidinfo_t panel_info;
 
-#endif /* CONFIG_MPC823 or CONFIG_PXA250 */
+#elif defined(CONFIG_MCC200)
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 160) */
+	ushort	vl_row;		/* Number of rows (i.e. 100) */
+
+	u_char	vl_bpix;	/* Bits per pixel, 0 = 1 */
+} vidinfo_t;
+#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 */
 
 /* Video functions */
 
-- 
cgit v1.3.1


From 43835aac4803d459dd73fabce09b27a826a381d7 Mon Sep 17 00:00:00 2001
From: Detlev Zundel <dzu@pollux.denx.de>
Date: Fri, 1 Sep 2006 11:59:23 +0200
Subject: Added interrupt handling capabilities for mpc5xxx processors. Also
 added Linux like BUG() macros.

---
 cpu/mpc5xxx/interrupts.c | 292 ++++++++++++++++++++++++++++++++++++++++++++---
 include/common.h         |   6 +
 include/mpc5xxx.h        |  59 ++++++++++
 3 files changed, 342 insertions(+), 15 deletions(-)

(limited to 'include')

diff --git a/cpu/mpc5xxx/interrupts.c b/cpu/mpc5xxx/interrupts.c
index 7bacecd595b..7b5cb8be4e2 100644
--- a/cpu/mpc5xxx/interrupts.c
+++ b/cpu/mpc5xxx/interrupts.c
@@ -1,4 +1,7 @@
 /*
+ * (C) Copyright 2006
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de
+ *
  * (C) Copyright -2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
@@ -24,18 +27,212 @@
  * MA 02111-1307 USA
  */
 
-/*
- * interrupts.c - just enough support for the decrementer/timer
+/* this section was ripped out of arch/ppc/syslib/mpc52xx_pic.c in the
+ * Linux 2.6 source with the following copyright.
+ *
+ * Based on (well, mostly copied from) the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ * 
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
  */
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <command.h>
 
-int interrupt_init_cpu (ulong *decrementer_count)
+struct irq_action {
+	interrupt_handler_t *handler;
+	void *arg;
+	ulong count;
+};
+
+static struct irq_action irq_handlers[NR_IRQS];
+
+static struct mpc5xxx_intr *intr;
+static struct mpc5xxx_sdma *sdma;
+
+static void mpc5xxx_ic_disable(unsigned int irq)
+{
+	u32 val;
+
+	if (irq == MPC5XXX_IRQ0) {
+		val = in_be32(&intr->ctrl);
+		val &= ~(1 << 11);
+		out_be32(&intr->ctrl, val);
+	} else if (irq < MPC5XXX_IRQ1) {
+		BUG();
+	} else if (irq <= MPC5XXX_IRQ3) {
+		val = in_be32(&intr->ctrl);
+		val &= ~(1 << (10 - (irq - MPC5XXX_IRQ1)));
+		out_be32(&intr->ctrl, val);
+	} else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
+		val = in_be32(&intr->main_mask);
+		val |= 1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE));
+		out_be32(&intr->main_mask, val);
+	} else if (irq < MPC5XXX_PERP_IRQ_BASE) {
+		val = in_be32(&sdma->IntMask);
+		val |= 1 << (irq - MPC5XXX_SDMA_IRQ_BASE);
+		out_be32(&sdma->IntMask, val);
+	} else {
+		val = in_be32(&intr->per_mask);
+		val |= 1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE));
+		out_be32(&intr->per_mask, val);
+	}
+}
+
+static void mpc5xxx_ic_enable(unsigned int irq)
+{
+	u32 val;
+
+	if (irq == MPC5XXX_IRQ0) {
+		val = in_be32(&intr->ctrl);
+		val |= 1 << 11;
+		out_be32(&intr->ctrl, val);
+	} else if (irq < MPC5XXX_IRQ1) {
+		BUG();
+	} else if (irq <= MPC5XXX_IRQ3) {
+		val = in_be32(&intr->ctrl);
+		val |= 1 << (10 - (irq - MPC5XXX_IRQ1));
+		out_be32(&intr->ctrl, val);
+	} else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
+		val = in_be32(&intr->main_mask);
+		val &= ~(1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE)));
+		out_be32(&intr->main_mask, val);
+	} else if (irq < MPC5XXX_PERP_IRQ_BASE) {
+		val = in_be32(&sdma->IntMask);
+		val &= ~(1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
+		out_be32(&sdma->IntMask, val);
+	} else {
+		val = in_be32(&intr->per_mask);
+		val &= ~(1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE)));
+		out_be32(&intr->per_mask, val);
+	}
+}
+
+static void mpc5xxx_ic_ack(unsigned int irq)
+{
+	u32 val;
+
+	/*
+	 * Only some irqs are reset here, others in interrupting hardware.
+	 */
+
+	switch (irq) {
+	case MPC5XXX_IRQ0:
+		val = in_be32(&intr->ctrl);
+		val |= 0x08000000;
+		out_be32(&intr->ctrl, val);
+		break;
+	case MPC5XXX_CCS_IRQ:
+		val = in_be32(&intr->enc_status);
+		val |= 0x00000400;
+		out_be32(&intr->enc_status, val);
+		break;
+	case MPC5XXX_IRQ1:
+		val = in_be32(&intr->ctrl);
+		val |= 0x04000000;
+		out_be32(&intr->ctrl, val);
+		break;
+	case MPC5XXX_IRQ2:
+		val = in_be32(&intr->ctrl);
+		val |= 0x02000000;
+		out_be32(&intr->ctrl, val);
+		break;
+	case MPC5XXX_IRQ3:
+		val = in_be32(&intr->ctrl);
+		val |= 0x01000000;
+		out_be32(&intr->ctrl, val);
+		break;
+	default:
+		if (irq >= MPC5XXX_SDMA_IRQ_BASE
+		    && irq < (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)) {
+			out_be32(&sdma->IntPend,
+				 1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
+		}
+		break;
+	}
+}
+
+static void mpc5xxx_ic_disable_and_ack(unsigned int irq)
+{
+	mpc5xxx_ic_disable(irq);
+	mpc5xxx_ic_ack(irq);
+}
+
+static void mpc5xxx_ic_end(unsigned int irq)
+{
+	mpc5xxx_ic_enable(irq);
+}
+
+void mpc5xxx_init_irq(void)
+{
+	u32 intr_ctrl;
+
+	/* Remap the necessary zones */
+	intr = (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
+	sdma = (struct mpc5xxx_sdma *)(MPC5XXX_SDMA);
+
+	/* Disable all interrupt sources. */
+	out_be32(&sdma->IntPend, 0xffffffff);	/* 1 means clear pending */
+	out_be32(&sdma->IntMask, 0xffffffff);	/* 1 means disabled */
+	out_be32(&intr->per_mask, 0x7ffffc00);	/* 1 means disabled */
+	out_be32(&intr->main_mask, 0x00010fff);	/* 1 means disabled */
+	intr_ctrl = in_be32(&intr->ctrl);
+	intr_ctrl |= 0x0f000000 |	/* clear IRQ 0-3 */
+	    0x00ff0000 |	/* IRQ 0-3 level sensitive low active */
+	    0x00001000 |	/* MEE master external enable */
+	    0x00000000 |	/* 0 means disable IRQ 0-3 */
+	    0x00000001;		/* CEb route critical normally */
+	out_be32(&intr->ctrl, intr_ctrl);
+
+	/* Zero a bunch of the priority settings.  */
+	out_be32(&intr->per_pri1, 0);
+	out_be32(&intr->per_pri2, 0);
+	out_be32(&intr->per_pri3, 0);
+	out_be32(&intr->main_pri1, 0);
+	out_be32(&intr->main_pri2, 0);
+}
+
+int mpc5xxx_get_irq(struct pt_regs *regs)
+{
+	u32 status;
+	int irq = -1;
+
+	status = in_be32(&intr->enc_status);
+
+	if (status & 0x00000400) {	/* critical */
+		irq = (status >> 8) & 0x3;
+		if (irq == 2)	/* high priority peripheral */
+			goto peripheral;
+		irq += MPC5XXX_CRIT_IRQ_BASE;
+	} else if (status & 0x00200000) {	/* main */
+		irq = (status >> 16) & 0x1f;
+		if (irq == 4)	/* low priority peripheral */
+			goto peripheral;
+		irq += MPC5XXX_MAIN_IRQ_BASE;
+	} else if (status & 0x20000000) {	/* peripheral */
+	      peripheral:
+		irq = (status >> 24) & 0x1f;
+		if (irq == 0) {	/* bestcomm */
+			status = in_be32(&sdma->IntPend);
+			irq = ffs(status) + MPC5XXX_SDMA_IRQ_BASE - 1;
+		} else
+			irq += MPC5XXX_PERP_IRQ_BASE;
+	}
+
+	return irq;
+}
+
+/****************************************************************************/
+
+int interrupt_init_cpu(ulong * decrementer_count)
 {
 	*decrementer_count = get_tbclk() / CFG_HZ;
 
+	mpc5xxx_init_irq();
+
 	return (0);
 }
 
@@ -44,14 +241,32 @@ int interrupt_init_cpu (ulong *decrementer_count)
 /*
  * Handle external interrupts
  */
-void
-external_interrupt(struct pt_regs *regs)
+void external_interrupt(struct pt_regs *regs)
 {
-	puts("external_interrupt (oops!)\n");
+	int irq, unmask = 1;
+
+	irq = mpc5xxx_get_irq(regs);
+
+	mpc5xxx_ic_disable_and_ack(irq);
+
+	enable_interrupts();
+
+	if (irq_handlers[irq].handler != NULL)
+		(*irq_handlers[irq].handler) (irq_handlers[irq].arg);
+	else {
+		printf("\nBogus External Interrupt IRQ %d\n", irq);
+		/*
+		 * turn off the bogus interrupt, otherwise it
+		 * might repeat forever
+		 */
+		unmask = 0;
+	}
+
+	if (unmask)
+		mpc5xxx_ic_end(irq);
 }
 
-void
-timer_interrupt_cpu (struct pt_regs *regs)
+void timer_interrupt_cpu(struct pt_regs *regs)
 {
 	/* nothing to do here */
 	return;
@@ -63,22 +278,69 @@ timer_interrupt_cpu (struct pt_regs *regs)
  * Install and free a interrupt handler.
  */
 
-void
-irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
+void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
 {
+	if (irq < 0 || irq >= NR_IRQS) {
+		printf("irq_install_handler: bad irq number %d\n", irq);
+		return;
+	}
 
+	if (irq_handlers[irq].handler != NULL)
+		printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
+		       (ulong) handler, (ulong) irq_handlers[irq].handler);
+
+	irq_handlers[irq].handler = handler;
+	irq_handlers[irq].arg = arg;
+
+	mpc5xxx_ic_enable(irq);
 }
 
-void
-irq_free_handler(int vec)
+void irq_free_handler(int irq)
 {
+	if (irq < 0 || irq >= NR_IRQS) {
+		printf("irq_free_handler: bad irq number %d\n", irq);
+		return;
+	}
+
+	mpc5xxx_ic_disable(irq);
 
+	irq_handlers[irq].handler = NULL;
+	irq_handlers[irq].arg = NULL;
 }
 
 /****************************************************************************/
 
-void
-do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
+void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
 {
-	puts("IRQ related functions are unimplemented currently.\n");
+	int irq, re_enable;
+	u32 intr_ctrl;
+	char *irq_config[] = { "level sensitive, active high",
+		"edge sensitive, rising active edge",
+		"edge sensitive, falling active edge",
+		"level sensitive, active low"
+	};
+
+	re_enable = disable_interrupts();
+
+	intr_ctrl = in_be32(&intr->ctrl);
+	printf("Interrupt configuration:\n");
+
+	for (irq = 0; irq <= 3; irq++) {
+		printf("IRQ%d: %s\n", irq,
+		       irq_config[(intr_ctrl >> (22 - 2 * irq)) & 0x3]);
+	}
+
+	puts("\nInterrupt-Information:\n" "Nr  Routine   Arg       Count\n");
+
+	for (irq = 0; irq < NR_IRQS; irq++)
+		if (irq_handlers[irq].handler != NULL)
+			printf("%02d  %08lx  %08lx  %ld\n", irq,
+			       (ulong) irq_handlers[irq].handler,
+			       (ulong) irq_handlers[irq].arg,
+			       irq_handlers[irq].count);
+
+	if (re_enable)
+		enable_interrupts();
 }
+#endif
diff --git a/include/common.h b/include/common.h
index 9a19001c18d..bee2fb70224 100644
--- a/include/common.h
+++ b/include/common.h
@@ -109,6 +109,12 @@ typedef volatile unsigned char	vu_char;
 #define debugX(level,fmt,args...)
 #endif	/* DEBUG */
 
+#define BUG() do { \
+        printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
+	panic("BUG!"); \
+} while (0)
+#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
+
 typedef void (interrupt_handler_t)(void *);
 
 #include <asm/u-boot.h> /* boot information for Linux kernel */
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index daa4d5f6d4c..1d20d1dcf55 100644
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -232,6 +232,65 @@
 #define MPC5XXX_ICTL_PER_STS	(MPC5XXX_ICTL + 0x0030)
 #define MPC5XXX_ICTL_BUS_STS	(MPC5XXX_ICTL + 0x0038)
 
+#define NR_IRQS			64
+
+/* IRQ mapping - these are our logical IRQ numbers */
+#define MPC5XXX_CRIT_IRQ_NUM	4
+#define MPC5XXX_MAIN_IRQ_NUM	17
+#define MPC5XXX_SDMA_IRQ_NUM	17
+#define MPC5XXX_PERP_IRQ_NUM	23
+
+#define MPC5XXX_CRIT_IRQ_BASE	1
+#define MPC5XXX_MAIN_IRQ_BASE	(MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
+#define MPC5XXX_SDMA_IRQ_BASE	(MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
+#define MPC5XXX_PERP_IRQ_BASE	(MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
+
+#define MPC5XXX_IRQ0			(MPC5XXX_CRIT_IRQ_BASE + 0)
+#define MPC5XXX_SLICE_TIMER_0_IRQ	(MPC5XXX_CRIT_IRQ_BASE + 1)
+#define MPC5XXX_HI_INT_IRQ		(MPC5XXX_CRIT_IRQ_BASE + 2)
+#define MPC5XXX_CCS_IRQ			(MPC5XXX_CRIT_IRQ_BASE + 3)
+
+#define MPC5XXX_IRQ1			(MPC5XXX_MAIN_IRQ_BASE + 1)
+#define MPC5XXX_IRQ2			(MPC5XXX_MAIN_IRQ_BASE + 2)
+#define MPC5XXX_IRQ3			(MPC5XXX_MAIN_IRQ_BASE + 3)
+#define MPC5XXX_RTC_PINT_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 5)
+#define MPC5XXX_RTC_SINT_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 6)
+#define MPC5XXX_RTC_GPIO_STD_IRQ	(MPC5XXX_MAIN_IRQ_BASE + 7)
+#define MPC5XXX_RTC_GPIO_WKUP_IRQ	(MPC5XXX_MAIN_IRQ_BASE + 8)
+#define MPC5XXX_TMR0_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 9)
+#define MPC5XXX_TMR1_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 10)
+#define MPC5XXX_TMR2_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 11)
+#define MPC5XXX_TMR3_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 12)
+#define MPC5XXX_TMR4_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 13)
+#define MPC5XXX_TMR5_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 14)
+#define MPC5XXX_TMR6_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 15)
+#define MPC5XXX_TMR7_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 16)
+
+#define MPC5XXX_SDMA_IRQ		(MPC5XXX_PERP_IRQ_BASE + 0)
+#define MPC5XXX_PSC1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 1)
+#define MPC5XXX_PSC2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 2)
+#define MPC5XXX_PSC3_IRQ		(MPC5XXX_PERP_IRQ_BASE + 3)
+#define MPC5XXX_PSC6_IRQ		(MPC5XXX_PERP_IRQ_BASE + 4)
+#define MPC5XXX_IRDA_IRQ		(MPC5XXX_PERP_IRQ_BASE + 4)
+#define MPC5XXX_FEC_IRQ			(MPC5XXX_PERP_IRQ_BASE + 5)
+#define MPC5XXX_USB_IRQ			(MPC5XXX_PERP_IRQ_BASE + 6)
+#define MPC5XXX_ATA_IRQ			(MPC5XXX_PERP_IRQ_BASE + 7)
+#define MPC5XXX_PCI_CNTRL_IRQ		(MPC5XXX_PERP_IRQ_BASE + 8)
+#define MPC5XXX_PCI_SCIRX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 9)
+#define MPC5XXX_PCI_SCITX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 10)
+#define MPC5XXX_PSC4_IRQ		(MPC5XXX_PERP_IRQ_BASE + 11)
+#define MPC5XXX_PSC5_IRQ		(MPC5XXX_PERP_IRQ_BASE + 12)
+#define MPC5XXX_SPI_MODF_IRQ		(MPC5XXX_PERP_IRQ_BASE + 13)
+#define MPC5XXX_SPI_SPIF_IRQ		(MPC5XXX_PERP_IRQ_BASE + 14)
+#define MPC5XXX_I2C1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 15)
+#define MPC5XXX_I2C2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 16)
+#define MPC5XXX_MSCAN1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 17)
+#define MPC5XXX_MSCAN2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 18)
+#define MPC5XXX_IR_RX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 19)
+#define MPC5XXX_IR_TX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 20)
+#define MPC5XXX_XLB_ARB_IRQ		(MPC5XXX_PERP_IRQ_BASE + 21)
+#define MPC5XXX_BDLC_IRQ		(MPC5XXX_PERP_IRQ_BASE + 22)
+
 /* General Purpose Timers registers */
 #define MPC5XXX_GPT0_ENABLE		(MPC5XXX_GPT + 0x0)
 #define MPC5XXX_GPT0_COUNTER		(MPC5XXX_GPT + 0x4)
-- 
cgit v1.3.1


From d7c2a02dea550e8701d1151010a823df48ad5c98 Mon Sep 17 00:00:00 2001
From: Detlev Zundel <dzu@pollux.denx.de>
Date: Fri, 1 Sep 2006 15:00:02 +0200
Subject: Added simple_strtoul(), getenv() and setenv() to the exported
 functions. Also bumped up ABI version to reflect this change.

---
 common/exports.c   | 7 +++++--
 include/_exports.h | 3 +++
 include/exports.h  | 5 ++++-
 3 files changed, 12 insertions(+), 3 deletions(-)

(limited to 'include')

diff --git a/common/exports.c b/common/exports.c
index ef253381697..0cb4396ea4a 100644
--- a/common/exports.c
+++ b/common/exports.c
@@ -23,8 +23,11 @@ void jumptable_init (void)
 	gd->jt[XF_get_version] = (void *) get_version;
 	gd->jt[XF_malloc] = (void *) malloc;
 	gd->jt[XF_free] = (void *) free;
-	gd->jt[XF_get_timer] = (void *)get_timer;
-	gd->jt[XF_udelay] = (void *)udelay;
+	gd->jt[XF_getenv] = (void *) getenv;
+	gd->jt[XF_setenv] = (void *) setenv;
+	gd->jt[XF_get_timer] = (void *) get_timer;
+	gd->jt[XF_simple_strtoul] = (void *) simple_strtoul;
+	gd->jt[XF_udelay] = (void *) udelay;
 #if defined(CONFIG_I386) || defined(CONFIG_PPC)
 	gd->jt[XF_install_hdlr] = (void *) irq_install_handler;
 	gd->jt[XF_free_hdlr] = (void *) irq_free_handler;
diff --git a/include/_exports.h b/include/_exports.h
index 61dcaaf331c..2b8ec3d3f91 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -12,6 +12,9 @@ EXPORT_FUNC(udelay)
 EXPORT_FUNC(get_timer)
 EXPORT_FUNC(vprintf)
 EXPORT_FUNC(do_reset)
+EXPORT_FUNC(getenv)
+EXPORT_FUNC(setenv)
+EXPORT_FUNC(simple_strtoul)
 #if (CONFIG_COMMANDS & CFG_CMD_I2C)
 EXPORT_FUNC(i2c_write)
 EXPORT_FUNC(i2c_read)
diff --git a/include/exports.h b/include/exports.h
index 0eaf66e1838..8f7f61703c6 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -20,6 +20,9 @@ void udelay(unsigned long);
 unsigned long get_timer(unsigned long);
 void vprintf(const char *, va_list);
 void do_reset (void);
+unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
+char *getenv (char *name);
+void setenv (char *varname, char *varvalue);
 #if (CONFIG_COMMANDS & CFG_CMD_I2C)
 int i2c_write (uchar, uint, int , uchar* , int);
 int i2c_read (uchar, uint, int , uchar* , int);
@@ -37,7 +40,7 @@ enum {
 	XF_MAX
 };
 
-#define XF_VERSION	2
+#define XF_VERSION	3
 
 #if defined(CONFIG_I386)
 extern gd_t *global_data;
-- 
cgit v1.3.1


From 360b4103677b27ad4018174a1d186218969d83a1 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Sun, 3 Sep 2006 18:17:46 +0200
Subject: Fixed problems on PRS200 board caused by adding splash screen on
 MCC200

---
 CHANGELOG                |  2 ++
 include/configs/mcc200.h | 41 ++++++++++++++++++++++-------------------
 2 files changed, 24 insertions(+), 19 deletions(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index 5e6e1f36847..5743bbc3927 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Fixed problems on PRS200 board caused by adding splash screen on MCC200
+
 * Extended README entry on coding style
 
 * Added another example showing simple interrupt interception.
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index e95d68bfb88..0c935bfcea9 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -37,12 +37,12 @@
 
 #define CONFIG_MISC_INIT_R
 
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH 	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot	     		*/
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs 			*/
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value 	*/
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
@@ -92,7 +92,7 @@
 
 /* USB */
 #define CONFIG_USB_OHCI
-#define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
+#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
 #define CONFIG_USB_STORAGE
 
 /*
@@ -167,7 +167,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#define CFG_IPBSPEED_133		/* define for 133MHz speed */
 
 /*
  * I2C configuration
@@ -183,9 +183,9 @@
  * TEXT base always at 0xFFF00000
  * ENV_ADDR always at  0xFFF40000
  * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
- *               0xFE000000 for 32 MB
- *               0xFF000000 for 16 MB
- *               0xFF800000 for  8 MB
+ *		 0xFE000000 for 32 MB
+ *		 0xFF000000 for 16 MB
+ *		 0xFF800000 for  8 MB
  */
 #define CFG_FLASH_BASE		0xfc000000
 #define CFG_FLASH_SIZE		0x04000000
@@ -207,9 +207,9 @@
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 #define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
 
-#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/
 
-#define CFG_ENV_SECT_SIZE	0x40000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x40000	/* size of one complete sector	*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 #define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
@@ -239,7 +239,7 @@
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
+#define CFG_MONITOR_BASE	TEXT_BASE
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #   define CFG_RAMBOOT		1
 #endif
@@ -261,11 +261,14 @@
 /*
  * LCD Splash Screen
  */
+#if !defined(CONFIG_PRS200)
 #define CONFIG_LCD		1
+#endif
+
 #if defined(CONFIG_LCD)
 #define CONFIG_SPLASH_SCREEN	1
 #define CFG_CONSOLE_IS_IN_ENV	1
-#define LCD_BPP		LCD_MONOCHROME
+#define LCD_BPP			LCD_MONOCHROME
 #endif
 
 /*
@@ -283,18 +286,18 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
 #define CFG_MAXARGS		16		/* max number of command args	*/
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
 #define CFG_LOAD_ADDR		0x100000	/* default load address */
-- 
cgit v1.3.1


From f60ba0d35e13e9dcf839d4563f9436d07468b1ef Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Mon, 4 Sep 2006 02:01:27 +0200
Subject: Fix build problems on sorcery board.

---
 CHANGELOG                 | 2 ++
 board/sorcery/sorcery.c   | 2 +-
 cpu/mpc8220/pci.c         | 2 +-
 include/configs/sorcery.h | 1 +
 4 files changed, 5 insertions(+), 2 deletions(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index be18ac206c1..a288465b3b9 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Fix build problems on sorcery board.
+
 * Fix coldfire build problems.
   Patch by Marian Balakowicz, 01 Sep 2006
 
diff --git a/board/sorcery/sorcery.c b/board/sorcery/sorcery.c
index 35d6a06084b..165e9e2999f 100644
--- a/board/sorcery/sorcery.c
+++ b/board/sorcery/sorcery.c
@@ -33,7 +33,7 @@ long int initdram (int board_type)
 
 	size = dramSetup ();
 
-	return get_ram_size((ulong *)CFG_SDRAM_BASE, size);
+	return get_ram_size(CFG_SDRAM_BASE, size);
 }
 
 int checkboard (void)
diff --git a/cpu/mpc8220/pci.c b/cpu/mpc8220/pci.c
index ca4a04d21e1..4ef214e5402 100644
--- a/cpu/mpc8220/pci.c
+++ b/cpu/mpc8220/pci.c
@@ -170,7 +170,7 @@ pci_mpc8220_init(struct pci_controller *hose)
 	hose->region_count = 3;
 
 	hose->cfg_addr = &(xcpci->cfg_adr);
-	hose->cfg_data = CONFIG_PCI_CFG_BUS;
+	hose->cfg_data = (volatile unsigned char *)CONFIG_PCI_CFG_BUS;
 
 	pci_set_ops(hose,
 		mpc8220_pci_read_config_byte,
diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
index 3d907f888c2..4937638820b 100644
--- a/include/configs/sorcery.h
+++ b/include/configs/sorcery.h
@@ -261,6 +261,7 @@
 #define CONFIG_MPC8220_FEC	1
 #define CONFIG_FEC_10MBIT	1 /* Workaround for FEC 100Mbit problem */
 #define CONFIG_PHY_ADDR		0x1F
+#define CONFIG_MII		1
 
 /*
  * Miscellaneous configurable options
-- 
cgit v1.3.1


From 887e2ec9ecf49366a60a49b32b73825804909865 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 7 Sep 2006 11:51:23 +0200
Subject: Add support for AMCC Sequoia PPC440EPx eval board - Add support for
 PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller  
 in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board,  
 please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image
 doesn't support environment   in NAND for now. This will be added in a short
 while. Patch by Stefan Roese, 07 Sep 2006

---
 CHANGELOG                              |  10 +
 MAINTAINERS                            |   1 +
 MAKEALL                                |   9 +-
 Makefile                               |  39 ++-
 board/amcc/sequoia/Makefile            |  52 +++
 board/amcc/sequoia/config.mk           |  41 +++
 board/amcc/sequoia/init.S              | 157 +++++++++
 board/amcc/sequoia/sdram.c             |  83 +++++
 board/amcc/sequoia/sequoia.c           | 552 ++++++++++++++++++++++++++++++
 board/amcc/sequoia/sequoia.h           |  67 ++++
 board/amcc/sequoia/u-boot-nand.lds     | 131 +++++++
 board/amcc/sequoia/u-boot.lds          | 145 ++++++++
 common/cmd_bdinfo.c                    |   6 +-
 config.mk                              |   4 +
 cpu/ppc4xx/405gp_pci.c                 |   3 +-
 cpu/ppc4xx/4xx_enet.c                  | 184 ++++++++--
 cpu/ppc4xx/Makefile                    |   2 +-
 cpu/ppc4xx/cpu.c                       | 109 +++++-
 cpu/ppc4xx/interrupts.c                |  57 ++-
 cpu/ppc4xx/miiphy.c                    |  14 +-
 cpu/ppc4xx/ndfc.c                      | 173 ++++++++++
 cpu/ppc4xx/serial.c                    | 263 +++++---------
 cpu/ppc4xx/speed.c                     |   3 +-
 cpu/ppc4xx/start.S                     | 128 ++++++-
 cpu/ppc4xx/usb_ohci.c                  |   8 +-
 cpu/ppc4xx/usbdev.c                    |  20 +-
 cpu/ppc4xx/vecnum.h                    |  89 ++++-
 doc/README.nand-boot-ppc440            |  36 ++
 dtt/lm75.c                             |   5 +
 include/405_mal.h                      |   2 +-
 include/440_i2c.h                      |   3 +-
 include/asm-ppc/processor.h            |   4 +
 include/asm-ppc/u-boot.h               |   3 +-
 include/configs/bamboo.h               |   1 +
 include/configs/pcs440ep.h             |   1 +
 include/configs/sequoia.h              | 431 +++++++++++++++++++++++
 include/configs/yellowstone.h          |   1 +
 include/configs/yosemite.h             |   1 +
 include/linux/mtd/compat.h             |   2 +
 include/linux/mtd/ndfc.h               |  67 ++++
 include/ppc440.h                       | 609 +++++++++++++++++++++++++++++++--
 include/ppc4xx_enet.h                  |  22 +-
 include/ppc_asm.tmpl                   |   2 +-
 lib_ppc/board.c                        |  12 +-
 nand_spl/board/amcc/sequoia/Makefile   |  83 +++++
 nand_spl/board/amcc/sequoia/config.mk  |  49 +++
 nand_spl/board/amcc/sequoia/u-boot.lds |  65 ++++
 nand_spl/nand_boot.c                   | 178 ++++++++++
 48 files changed, 3606 insertions(+), 321 deletions(-)
 create mode 100644 board/amcc/sequoia/Makefile
 create mode 100644 board/amcc/sequoia/config.mk
 create mode 100644 board/amcc/sequoia/init.S
 create mode 100644 board/amcc/sequoia/sdram.c
 create mode 100644 board/amcc/sequoia/sequoia.c
 create mode 100644 board/amcc/sequoia/sequoia.h
 create mode 100644 board/amcc/sequoia/u-boot-nand.lds
 create mode 100644 board/amcc/sequoia/u-boot.lds
 create mode 100644 cpu/ppc4xx/ndfc.c
 create mode 100644 doc/README.nand-boot-ppc440
 create mode 100644 include/configs/sequoia.h
 create mode 100644 include/linux/mtd/ndfc.h
 create mode 100644 nand_spl/board/amcc/sequoia/Makefile
 create mode 100644 nand_spl/board/amcc/sequoia/config.mk
 create mode 100644 nand_spl/board/amcc/sequoia/u-boot.lds
 create mode 100644 nand_spl/nand_boot.c

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index 3c42d93fe84..576cd7fb861 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,16 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Add support for AMCC Sequoia PPC440EPx eval board
+  - Add support for PPC440EPx & PPC440GRx
+  - Add support for PPC440EP(x)/GR(x) NAND controller
+    in cpu/ppc4xx directory
+  - Add NAND boot functionality for Sequoia board,
+    please see doc/README.nand-boot-ppc440 for details
+  - This Sequoia NAND image doesn't support environment
+    in NAND for now. This will be added in a short while.
+  Patch by Stefan Roese, 07 Sep 2006
+
 * Fix mkimage -l bug with multifile images on 64bit platforms
   Patch by David Updegraff, 06 Sep 2006
 
diff --git a/MAINTAINERS b/MAINTAINERS
index 0c4cfb43cf4..42627196f86 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -285,6 +285,7 @@ Stefan Roese <sr@denx.de>
 	ocotea			PPC440GX
 	p3p440			PPC440GP
 	pcs440ep		PPC440EP
+	sequoia			PPC440EPx
 	sycamore		PPC405GPr
 	walnut			PPC405GP
 	yellowstone		PPC440GR
diff --git a/MAKEALL b/MAKEALL
index d2f86d3ac8a..8039f3d7082 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -13,7 +13,7 @@ if [ "${MAKEALL_LOGDIR}" ] ; then
 else
 	LOG_DIR="LOG"
 fi
-	
+
 if [ ! "${BUILD_DIR}" ] ; then
 	BUILD_DIR="."
 fi
@@ -85,9 +85,10 @@ LIST_4xx="	\
 	ML2		ml300		ocotea		OCRTC		\
 	ORSG		p3p440		PCI405		pcs440ep	\
 	PIP405		PLU405		PMC405		PPChameleonEVB	\
-	sbc405		VOH405		VOM405		W7OLMC		\
-	W7OLMG		walnut		WUH405		XPEDITE1K	\
-	yellowstone	yosemite	yucca		bamboo		\
+	sbc405		sequoia		sequoia_nand	VOH405		\
+	VOM405		W7OLMC		W7OLMG		walnut		\
+	WUH405		XPEDITE1K	yellowstone	yosemite	\
+	yucca		bamboo		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index fc7b117e3fe..a63aaef15bc 100644
--- a/Makefile
+++ b/Makefile
@@ -48,7 +48,7 @@ VENDOR=
 #
 # U-boot build supports producing a object files to the separate external
 # directory. Two use cases are supported:
-# 
+#
 # 1) Add O= to the make command line
 # 'make O=/tmp/build all'
 #
@@ -59,12 +59,12 @@ VENDOR=
 # The second approach can also be used with a MAKEALL script
 # 'export BUILD_DIR=/tmp/build'
 # './MAKEALL'
-# 
+#
 # Command line 'O=' setting overrides BUILD_DIR environent variable.
-# 
+#
 # When none of the above methods is used the local build is performed and
 # the object files are placed in the source directory.
-# 
+#
 
 ifdef O
 ifeq ("$(origin O)", "command line")
@@ -101,7 +101,7 @@ src := $(SRCTREE)/
 else
 obj :=
 src :=
-endif   
+endif
 export obj src
 
 #########################################################################
@@ -214,13 +214,18 @@ SUBDIRS	= tools \
 	  post/cpu
 .PHONY : $(SUBDIRS)
 
+ifeq ($(CONFIG_NAND_U_BOOT),y)
+NAND_SPL = nand_spl
+U_BOOT_NAND = $(obj)u-boot-nand.bin
+endif
+
 __OBJS := $(subst $(obj),,$(OBJS))
 __LIBS := $(subst $(obj),,$(LIBS))
 
 #########################################################################
 #########################################################################
 
-ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
+ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
 
 all:		$(ALL)
 
@@ -258,6 +263,12 @@ $(LIBS):
 $(SUBDIRS):
 		$(MAKE) -C $@ all
 
+$(NAND_SPL):	version
+		$(MAKE) -C nand_spl all
+
+$(U_BOOT_NAND):	$(NAND_SPL) $(obj)u-boot.bin
+		cat nand_spl/u-boot-spl-4k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
+
 version:
 		@echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \
 		echo -n "$(U_BOOT_VERSION)" >> $(VERSION_FILE); \
@@ -309,7 +320,8 @@ endif
 #########################################################################
 
 unconfig:
-	@rm -f $(obj)include/config.h $(obj)include/config.mk $(obj)board/*/config.tmp
+	@rm -f $(obj)include/config.h $(obj)include/config.mk \
+		$(obj)board/*/config.tmp $(obj)board/*/*/config.tmp
 
 #========================================================================
 # PowerPC
@@ -1128,6 +1140,17 @@ PPChameleonEVB_HI_33_config:	unconfig
 sbc405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
 
+sequoia_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx sequoia amcc
+
+sequoia_nand_config:	unconfig
+	@ln -s board/amcc/sequoia/Makefile nand_spl/Makefile
+	@echo "#define CONFIG_NAND_U_BOOT" >include/config.h
+	@echo "Compile NAND boot image for sequoia"
+	@$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
+	@echo "TEXT_BASE = 0x01000000" >board/amcc/sequoia/config.tmp
+	@echo "CONFIG_NAND_U_BOOT = y" >> include/config.mk
+
 sycamore_config:	unconfig
 	@echo "Configuring for sycamore board as subset of walnut..."
 	@$(MKCONFIG) -a walnut ppc ppc4xx walnut amcc
@@ -2195,6 +2218,8 @@ clean:
 	rm -f $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom
 	rm -f $(obj)board/integratorap/u-boot.lds $(obj)board/integratorcp/u-boot.lds
 	rm -f $(obj)include/bmp_logo.h
+	find nand_spl -lname "*" -print | xargs rm -f
+	rm -f nand_spl/u-boot-spl nand_spl/u-boot-spl.map
 
 clobber:	clean
 	find $(OBJTREE) -type f \( -name .depend \
diff --git a/board/amcc/sequoia/Makefile b/board/amcc/sequoia/Makefile
new file mode 100644
index 00000000000..b29c04a0d9e
--- /dev/null
+++ b/board/amcc/sequoia/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+include $(TOPDIR)/include/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o sdram.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk
new file mode 100644
index 00000000000..7713a72be85
--- /dev/null
+++ b/board/amcc/sequoia/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 440EPx Reference Platform (Sequoia) board
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFA0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
new file mode 100644
index 00000000000..3d4ac8543d5
--- /dev/null
+++ b/board/amcc/sequoia/init.S
@@ -0,0 +1,157 @@
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+#define _256M       0x10000000
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_8M       0x00000060
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	*/
+#ifndef CONFIG_NAND_SPL
+	tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+#else
+	tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
+#endif
+
+	/* TLB-entry for DDR SDRAM (Up to 2GB) */
+	tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+#ifdef CFG_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+#endif
+
+	/* TLB-entry for PCI Memory */
+	tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+
+	/* TLB-entry for EBC */
+	tlbentry( CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+	/* TLB-entry for NAND */
+	tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+	/* TLB-entry for Internal Registers & OCM */
+	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I )
+
+	/*TLB-entry PCI registers*/
+	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_R|AC_W|AC_X|SA_G|SA_I )
+
+	/* TLB-entry for peripherals */
+	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	tlbtab_end
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+	/*
+	 * For NAND booting the first TLB has to be reconfigured to full size
+	 * and with caching disabled after running from RAM!
+	 */
+#define TLB00	TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01	TLB1(CFG_BOOT_BASE_ADDR, 1)
+#define TLB02	TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	.globl	reconfig_tlb0
+reconfig_tlb0:
+	sync
+	isync
+	addi	r4,r0,0x0000		/* TLB entry #0 */
+	lis	r5,TLB00@h
+	ori	r5,r5,TLB00@l
+	tlbwe	r5,r4,0x0000		/* Save it out */
+	lis	r5,TLB01@h
+	ori	r5,r5,TLB01@l
+	tlbwe	r5,r4,0x0001		/* Save it out */
+	lis	r5,TLB02@h
+	ori	r5,r5,TLB02@l
+	tlbwe	r5,r4,0x0002		/* Save it out */
+	sync
+	isync
+	blr
+#endif
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
new file mode 100644
index 00000000000..a62648bb5f4
--- /dev/null
+++ b/board/amcc/sequoia/sdram.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+
+/*************************************************************************
+ *
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ *
+ ************************************************************************/
+long int initdram (int board_type)
+{
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+	volatile ulong val;
+
+	mtsdram(DDR0_02, 0x00000000);
+
+	/*
+	 * Soft-reset SDRAM controller
+	 */
+	mtsdr(sdr_srst, SDR0_SRST0_DMC);
+	mtsdr(sdr_srst, 0x00000000);
+
+	mtsdram(DDR0_00, 0x0000190A);
+	mtsdram(DDR0_01, 0x01000000);
+	mtsdram(DDR0_03, 0x02030602);
+	mtsdram(DDR0_04, 0x13030300);
+	mtsdram(DDR0_05, 0x0202050E);
+	mtsdram(DDR0_06, 0x0104C823);
+	mtsdram(DDR0_07, 0x000D0100);
+	mtsdram(DDR0_08, 0x02360001);
+	mtsdram(DDR0_09, 0x00011D5F);
+	mtsdram(DDR0_10, 0x00000300);
+	mtsdram(DDR0_11, 0x0027C800);
+	mtsdram(DDR0_12, 0x00000003);
+	mtsdram(DDR0_14, 0x00000000);
+	mtsdram(DDR0_17, 0x19000000);
+	mtsdram(DDR0_18, 0x19191919);
+	mtsdram(DDR0_19, 0x19191919);
+	mtsdram(DDR0_20, 0x0B0B0B0B);
+	mtsdram(DDR0_21, 0x0B0B0B0B);
+	mtsdram(DDR0_22, 0x00267F0B);
+	mtsdram(DDR0_23, 0x00000000);
+	mtsdram(DDR0_24, 0x01010002);
+	mtsdram(DDR0_26, 0x5B260181);
+	mtsdram(DDR0_27, 0x0000682B);
+	mtsdram(DDR0_28, 0x00000000);
+	mtsdram(DDR0_31, 0x00000000);
+	mtsdram(DDR0_42, 0x01000006);
+	mtsdram(DDR0_43, 0x050A0200);
+	mtsdram(DDR0_44, 0x00000005);
+	mtsdram(DDR0_02, 0x00000001);
+
+	/*
+	 * Wait for DCC master delay line to finish calibration
+	 */
+	mfsdram(DDR0_17, val);
+	while (((val >> 8) & 0x000007f) == 0) {
+		mfsdram(DDR0_17, val);
+	}
+#endif /* #ifndef CONFIG_NAND_U_BOOT */
+
+	return (CFG_MBYTES_SDRAM << 20);
+}
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
new file mode 100644
index 00000000000..95734b9c57c
--- /dev/null
+++ b/board/amcc/sequoia/sequoia.c
@@ -0,0 +1,552 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+#include "sequoia.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+int board_early_init_f(void)
+{
+	unsigned long sdr0_cust0;
+	unsigned long sdr0_pfc1, sdr0_pfc2;
+	register uint reg;
+
+	mtdcr(ebccfga, xbcfg);
+	mtdcr(ebccfgd, 0xb8400000);
+
+	/*--------------------------------------------------------------------
+	 * Setup the GPIO pins
+	 *-------------------------------------------------------------------*/
+	/* test-only: take GPIO init from pcs440ep ???? in config file */
+	out32(GPIO0_OR, 0x00000000);
+	out32(GPIO0_TCR, 0x0000000f);
+	out32(GPIO0_OSRL, 0x50015400);
+	out32(GPIO0_OSRH, 0x550050aa);
+	out32(GPIO0_TSRL, 0x50015400);
+	out32(GPIO0_TSRH, 0x55005000);
+	out32(GPIO0_ISR1L, 0x50000000);
+	out32(GPIO0_ISR1H, 0x00000000);
+	out32(GPIO0_ISR2L, 0x00000000);
+	out32(GPIO0_ISR2H, 0x00000100);
+	out32(GPIO0_ISR3L, 0x00000000);
+	out32(GPIO0_ISR3H, 0x00000000);
+
+	out32(GPIO1_OR, 0x00000000);
+	out32(GPIO1_TCR, 0xc2000000);
+	out32(GPIO1_OSRL, 0x5c280000);
+	out32(GPIO1_OSRH, 0x00000000);
+	out32(GPIO1_TSRL, 0x0c000000);
+	out32(GPIO1_TSRH, 0x00000000);
+	out32(GPIO1_ISR1L, 0x00005550);
+	out32(GPIO1_ISR1H, 0x00000000);
+	out32(GPIO1_ISR2L, 0x00050000);
+	out32(GPIO1_ISR2H, 0x00000000);
+	out32(GPIO1_ISR3L, 0x01400000);
+	out32(GPIO1_ISR3H, 0x00000000);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(uic0er, 0x00000000);	/* disable all */
+	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(uic0pr, 0xfffff7ff);	/* per ref-board manual */
+	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(uic1er, 0x00000000);	/* disable all */
+	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic1pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr(uic1tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+	mtdcr(uic2er, 0x00000000);	/* disable all */
+	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+
+	/* 50MHz tmrclk */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
+
+	/* clear write protects */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
+
+	/* enable Ethernet */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00;
+
+	/* enable USB device */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20;
+
+	/* select Ethernet pins */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
+	mfsdr(SDR0_PFC2, sdr0_pfc2);
+	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
+	mtsdr(SDR0_PFC2, sdr0_pfc2);
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+	/* PCI arbiter enabled */
+	mfsdr(sdr_pci0, reg);
+	mtsdr(sdr_pci0, 0x80000000 | reg);
+
+	/* setup NAND FLASH */
+	mfsdr(SDR0_CUST0, sdr0_cust0);
+        sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
+		SDR0_CUST0_NDFC_ENABLE		|
+		SDR0_CUST0_NDFC_BW_8_BIT	|
+		SDR0_CUST0_NDFC_ARE_MASK	|
+		(0x80000000 >> (28 + CFG_NAND_CS));
+        mtsdr(SDR0_CUST0, sdr0_cust0);
+
+	return 0;
+}
+
+/*---------------------------------------------------------------------------+
+  | misc_init_r.
+  +---------------------------------------------------------------------------*/
+int misc_init_r(void)
+{
+	uint pbcr;
+	int size_val = 0;
+	unsigned long usb2d0cr = 0;
+	unsigned long usb2phy0cr, usb2h0cr = 0;
+	unsigned long sdr0_pfc1;
+	char *act = getenv("usbact");
+
+	/*
+	 * FLASH stuff...
+	 */
+
+	/* Re-do sizing to get full correct info */
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+	mtdcr(ebccfga, pb3cr);
+#else
+	mtdcr(ebccfga, pb0cr);
+#endif
+	pbcr = mfdcr(ebccfgd);
+	switch (gd->bd->bi_flashsize) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	case 32 << 20:
+		size_val = 5;
+		break;
+	case 64 << 20:
+		size_val = 6;
+		break;
+	case 128 << 20:
+		size_val = 7;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+	mtdcr(ebccfga, pb3cr);
+#else
+	mtdcr(ebccfga, pb0cr);
+#endif
+	mtdcr(ebccfgd, pbcr);
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+#ifdef CFG_ENV_IS_IN_FLASH
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	/* Env protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CFG_ENV_ADDR_REDUND,
+			    CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+			    &flash_info[0]);
+#endif
+
+	/*
+	 * USB suff...
+	 */
+	if (act == NULL || strcmp(act, "hostdev") == 0)	{
+		/* SDR Setting */
+        	mfsdr(SDR0_PFC1, sdr0_pfc1);
+        	mfsdr(SDR0_USB0, usb2d0cr);
+        	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+        	mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
+        	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
+
+		/* An 8-bit/60MHz interface is the only possible alternative
+		   when connecting the Device to the PHY */
+        	usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+        	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
+
+        	/* To enable the USB 2.0 Device function through the UTMI interface */
+        	usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+        	usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;		/*1*/
+
+        	sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+        	sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;		/*0*/
+
+        	mtsdr(SDR0_PFC1, sdr0_pfc1);
+        	mtsdr(SDR0_USB0, usb2d0cr);
+        	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+        	mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+		/*clear resets*/
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x00000000);
+		udelay (1000);
+		mtsdr(SDR0_SRST0, 0x00000000);
+
+		printf("USB:   Host(int phy) Device(ext phy)\n");
+
+	} else if (strcmp(act, "dev") == 0) {
+		/*-------------------PATCH-------------------------------*/
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x672c6000);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST0, 0x00000080);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x60206000);
+
+		*(unsigned int *)(0xe0000350) = 0x00000001;
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x60306000);
+		/*-------------------PATCH-------------------------------*/
+
+		/* SDR Setting */
+        	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mfsdr(SDR0_USB2H0CR, usb2h0cr);
+		mfsdr(SDR0_USB0, usb2d0cr);
+		mfsdr(SDR0_PFC1, sdr0_pfc1);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
+        	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;	/*0*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;		/*1*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;		/*0*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;		/*0*/
+
+		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+        	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;		/*0*/
+
+		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+        	usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;		/*0*/
+
+		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+        	sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;		/*1*/
+
+        	mtsdr(SDR0_USB2H0CR, usb2h0cr);
+        	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mtsdr(SDR0_USB0, usb2d0cr);
+		mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+		/*clear resets*/
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x00000000);
+		udelay (1000);
+		mtsdr(SDR0_SRST0, 0x00000000);
+
+		printf("USB:   Device(int phy)\n");
+	}
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+	unsigned long *mem = (unsigned long *)0;
+	const unsigned long kend = (1024 / sizeof(unsigned long));
+	unsigned long k, n;
+
+	mtmsr(0);
+
+	for (k = 0; k < CFG_MBYTES_SDRAM;
+	     ++k, mem += (1024 / sizeof(unsigned long))) {
+		if ((k & 1023) == 0) {
+			printf("%3d MB\r", k / 1024);
+		}
+
+		memset(mem, 0xaaaaaaaa, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0xaaaaaaaa) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+
+		memset(mem, 0x55555555, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0x55555555) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+	}
+	printf("SDRAM test passes\n");
+	return 0;
+}
+#endif
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+	unsigned long addr;
+#if 0
+	/*--------------------------------------------------------------------------+
+	 *	Cactus is always configured as the host & requires the
+	 *	PCI arbiter to be enabled ???
+	 *--------------------------------------------------------------------------*/
+	unsigned long strap;
+	mfsdr(sdr_sdstp1, strap);
+	if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
+		printf("PCI: SDR0_STRP1[PAE] not set.\n");
+		printf("PCI: Configuration aborted.\n");
+		return 0;
+	}
+#endif
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB3 devices to 0.
+	  | Set PLB3 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp1, addr);
+	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb3_acr);
+	mtdcr(plb3_acr, addr | 0x80000000);
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB4 devices to 0.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp0, addr);
+	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
+	mtdcr(plb4_acr, addr);
+
+	/*-------------------------------------------------------------------------+
+	  | Set Nebula PLB4 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	/* Segment0 */
+	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+	mtdcr(plb0_acr, addr);
+
+	/* Segment1 */
+	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+	mtdcr(plb1_acr, addr);
+
+	return 1;
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	/*--------------------------------------------------------------------------+
+	 * Set up Direct MMIO registers
+	 *--------------------------------------------------------------------------*/
+	/*--------------------------------------------------------------------------+
+	  | PowerPC440EPX PCI Master configuration.
+	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+	  |   Use byte reversed out routines to handle endianess.
+	  | Make this region non-prefetchable.
+	  +--------------------------------------------------------------------------*/
+	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
+	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
+
+	/*--------------------------------------------------------------------------+
+	 * Set up Configuration registers
+	 *--------------------------------------------------------------------------*/
+
+	/* Program the board's subsystem id/vendor id */
+	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+			      CFG_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+	/* Configure command register as bus master */
+	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+	/* 240nS PCI clock */
+	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+	/* No error reporting */
+	pci_write_config_word(0, PCI_ERREN, 0);
+
+	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+	unsigned short temp_short;
+
+	/*--------------------------------------------------------------------------+
+	  | Write the PowerPC440 EP PCI Configuration regs.
+	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
+	  +--------------------------------------------------------------------------*/
+	pci_read_config_word(0, PCI_COMMAND, &temp_short);
+	pci_write_config_word(0, PCI_COMMAND,
+			      temp_short | PCI_COMMAND_MASTER |
+			      PCI_COMMAND_MEMORY);
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* Cactus is always configured as host. */
+	return (1);
+}
+#endif				/* defined(CONFIG_PCI) */
diff --git a/board/amcc/sequoia/sequoia.h b/board/amcc/sequoia/sequoia.h
new file mode 100644
index 00000000000..1d44b164649
--- /dev/null
+++ b/board/amcc/sequoia/sequoia.h
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+/*----------------------------------------------------------------------------+
+  | EBC Configuration Register - EBC0_CFG
+  +----------------------------------------------------------------------------*/
+/* External Bus Three-State Control */
+#define EBC0_CFG_EBTC_DRIVEN	    0x80000000
+/* Device-Paced Time-out Disable */
+#define EBC0_CFG_PTD_ENABLED	    0x00000000
+/* Ready Timeout Count */
+#define EBC0_CFG_RTC_MASK	    0x38000000
+#define EBC0_CFG_RTC_16PERCLK	    0x00000000
+#define EBC0_CFG_RTC_32PERCLK	    0x08000000
+#define EBC0_CFG_RTC_64PERCLK	    0x10000000
+#define EBC0_CFG_RTC_128PERCLK	    0x18000000
+#define EBC0_CFG_RTC_256PERCLK	    0x20000000
+#define EBC0_CFG_RTC_512PERCLK	    0x28000000
+#define EBC0_CFG_RTC_1024PERCLK	    0x30000000
+#define EBC0_CFG_RTC_2048PERCLK	    0x38000000
+/* External Master Priority Low */
+#define EBC0_CFG_EMPL_LOW	    0x00000000
+#define EBC0_CFG_EMPL_MEDIUM_LOW    0x02000000
+#define EBC0_CFG_EMPL_MEDIUM_HIGH   0x04000000
+#define EBC0_CFG_EMPL_HIGH	    0x06000000
+/* External Master Priority High */
+#define EBC0_CFG_EMPH_LOW	    0x00000000
+#define EBC0_CFG_EMPH_MEDIUM_LOW    0x00800000
+#define EBC0_CFG_EMPH_MEDIUM_HIGH   0x01000000
+#define EBC0_CFG_EMPH_HIGH	    0x01800000
+/* Chip Select Three-State Control */
+#define EBC0_CFG_CSTC_DRIVEN	    0x00400000
+/* Burst Prefetch */
+#define EBC0_CFG_BPF_ONEDW	    0x00000000
+#define EBC0_CFG_BPF_TWODW	    0x00100000
+#define EBC0_CFG_BPF_FOURDW	    0x00200000
+/* External Master Size */
+#define EBC0_CFG_EMS_8BIT	    0x00000000
+/* Power Management Enable */
+#define EBC0_CFG_PME_DISABLED	    0x00000000
+#define EBC0_CFG_PME_ENABLED	    0x00020000
+/* Power Management Timer */
+#define EBC0_CFG_PMT_ENCODE(n)		((((unsigned long)(n))&0x1F)<<12)
+
+#define SDR0_USB0                    0x0320     /* USB Control Register */
diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds
new file mode 100644
index 00000000000..c3d3d968fed
--- /dev/null
+++ b/board/amcc/sequoia/u-boot-nand.lds
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/sequoia/u-boot.lds b/board/amcc/sequoia/u-boot.lds
new file mode 100644
index 00000000000..a423f982858
--- /dev/null
+++ b/board/amcc/sequoia/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 256e4bc7968..70de795deed 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -62,11 +62,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
     defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-	defined(CONFIG_440SP)
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ||	\
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	print_str ("procfreq",	    strmhz(buf, bd->bi_procfreq));
 	print_str ("plb_busfreq",   strmhz(buf, bd->bi_plb_busfreq));
 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	print_str ("pci_busfreq",   strmhz(buf, bd->bi_pci_busfreq));
 #endif
 #else	/* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */
diff --git a/config.mk b/config.mk
index 3ed7107fb80..0f5d0f43d94 100644
--- a/config.mk
+++ b/config.mk
@@ -132,8 +132,12 @@ DBGFLAGS= -g # -DDEBUG
 OPTFLAGS= -Os #-fomit-frame-pointer
 ifndef LDSCRIPT
 #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
+ifeq ($(CONFIG_NAND_U_BOOT),y)
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+else
 LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
 endif
+endif
 OBJCFLAGS += --gap-fill=0xff
 
 gccincdir := $(shell $(CC) -print-file-name=include)
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 0b0686bcf71..03128d3f6d1 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -555,7 +555,8 @@ void pci_440_init (struct pci_controller *hose)
 #ifdef CONFIG_PCI_SCAN_SHOW
 		printf("PCI:   Bus Dev VenId DevId Class Int\n");
 #endif
-#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
+#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
+    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
 		out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
 #endif
 		hose->last_busno = pci_hose_scan(hose);
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index fab65aff78a..5b1c17c351a 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -130,7 +130,17 @@
 #define BI_PHYMODE_NONE	 0
 #define BI_PHYMODE_ZMII	 1
 #define BI_PHYMODE_RGMII 2
+#define BI_PHYMODE_GMII  3
+#define BI_PHYMODE_RTBI  4
+#define BI_PHYMODE_TBI   5
+#if defined (CONFIG_440EPX)
+#define BI_PHYMODE_SMII  6
+#define BI_PHYMODE_MII   7
+#endif
 
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_MFR_ETH_CLK_SEL_V(n)	((0x01<<27) / (n+1))
+#endif
 
 /*-----------------------------------------------------------------------------+
  * Global variables. TX and RX descriptors and buffers.
@@ -181,7 +191,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
 {
 	EMAC_4XX_HW_PST hw_p = dev->priv;
 	uint32_t failsafe = 10000;
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	unsigned long mfr;
 #endif
 
@@ -205,19 +215,19 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
 	}
 
 	/* EMAC RESET */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	/* provide clocks for EMAC internal loopback  */
 	mfsdr (sdr_mfr, mfr);
-	mfr |= 0x08000000;
+	mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
 	mtsdr(sdr_mfr, mfr);
 #endif
 
 	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	/* remove clocks for EMAC internal loopback  */
 	mfsdr (sdr_mfr, mfr);
-	mfr &= ~0x08000000;
+	mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
 	mtsdr(sdr_mfr, mfr);
 #endif
 
@@ -317,10 +327,50 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 	out32 (RGMII_FER, rmiifer);
 
 	return ((int)pfc1);
-
 }
 #endif	/* CONFIG_440_GX */
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
+{
+	unsigned long zmiifer=0x0;
+
+	/*
+	 * Right now only 2*RGMII is supported. Please extend when needed.
+	 * sr - 2006-08-29
+	 */
+	switch (1) {
+	case 0:
+		/* 1 x GMII port */
+		out32 (ZMII_FER, 0x00);
+		out32 (RGMII_FER, 0x00000037);
+		bis->bi_phymode[0] = BI_PHYMODE_GMII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
+		break;
+	case 1:
+		/* 2 x RGMII ports */
+		out32 (ZMII_FER, 0x00);
+		out32 (RGMII_FER, 0x00000055);
+		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
+		break;
+	case 2:
+		/* 2 x SMII ports */
+
+		break;
+	default:
+		break;
+	}
+
+	/* Ensure we setup mdio for this devnum and ONLY this devnum */
+	zmiifer = in32 (ZMII_FER);
+	zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
+	out32 (ZMII_FER, zmiifer);
+
+	return ((int)0x0);
+}
+#endif	/* CONFIG_440EPX */
+
 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 {
 	int i, j;
@@ -332,13 +382,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	unsigned mode_reg;
 	unsigned short devnum;
 	unsigned short reg_short;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	sys_info_t sysinfo;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	int ethgroup = -1;
 #endif
 #endif
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
 	unsigned long mfr;
 #endif
 
@@ -352,7 +405,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 		return -1;
 	}
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	/* Need to get the OPB frequency so we can access the PHY */
 	get_sys_info (&sysinfo);
 #endif
@@ -407,7 +462,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
-#elif defined(CONFIG_440GX)
+#elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
 #elif defined(CONFIG_440GP)
 	/* set RMII mode */
@@ -429,10 +484,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	__asm__ volatile ("eieio");
 
 	/* reset emac so we have access to the phy */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	/* provide clocks for EMAC internal loopback  */
 	mfsdr (sdr_mfr, mfr);
-	mfr |= 0x08000000;
+	mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
 	mtsdr(sdr_mfr, mfr);
 #endif
 
@@ -444,15 +499,19 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 		udelay (1000);
 		failsafe--;
 	}
+	if (failsafe <= 0)
+		printf("\nProblem resetting EMAC!\n");
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	/* remove clocks for EMAC internal loopback  */
 	mfsdr (sdr_mfr, mfr);
-	mfr &= ~0x08000000;
+	mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
 	mtsdr(sdr_mfr, mfr);
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	/* Whack the M1 register */
 	mode_reg = 0x0;
 	mode_reg &= ~0x00000038;
@@ -502,15 +561,39 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	 * otherwise, just check the speeds & feeds
 	 */
 	if (hw_p->first_init == 0) {
+#if defined(CONFIG_88E1111_CLK_DELAY)
+		/*
+		 * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs
+		 * the "RGMII transmit timing control" and "RGMII receive
+		 * timing control" bits set, so that Gbit communication works
+		 * without problems.
+		 * Also set the "Transmitter disable" to 1 to enable the
+		 * transmitter.
+		 * After setting these bits a soft-reset must occur for this
+		 * change to become active.
+		 */
+		miiphy_read (dev->name, reg, 0x14, &reg_short);
+		reg_short |= (1 << 7) | (1 << 1) | (1 << 0);
+		miiphy_write (dev->name, reg, 0x14, reg_short);
+#endif
+#if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */
+		miiphy_write (dev->name, reg, 0x14, 0x0ce3);
+		miiphy_write (dev->name, reg, 0x18, 0x4101);
+		miiphy_write (dev->name, reg, 0x09, 0x0e00);
+		miiphy_write (dev->name, reg, 0x04, 0x01e1);
+#endif
 		miiphy_reset (dev->name, reg);
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+
 #if defined(CONFIG_CIS8201_PHY)
 		/*
 		 * Cicada 8201 PHY needs to have an extended register whacked
 		 * for RGMII mode.
 		 */
-		if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
+		if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
 #if defined(CONFIG_CIS8201_SHORT_ETCH)
 			miiphy_write (dev->name, reg, 23, 0x1300);
 #else
@@ -580,7 +663,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 			(int) speed, (duplex == HALF) ? "HALF" : "FULL");
 	}
 
-#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
+#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
+    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	mfsdr(sdr_mfr, reg);
 	if (speed == 100) {
@@ -603,15 +687,34 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 			reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
 		else if (speed == 100)
 			reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
-		else
+		else if (speed == 10)
 			reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
-
+		else {
+			printf("Error in RGMII Speed\n");
+			return -1;
+		}
 		out32 (RGMII_SSR, reg);
 	}
 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	if (speed == 1000)
+		reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
+	else if (speed == 100)
+		reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
+	else if (speed == 10)
+		reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
+	else {
+		printf("Error in RGMII Speed\n");
+		return -1;
+	}
+	out32 (RGMII_SSR, reg);
+#endif
+
 	/* set the Mal configuration reg */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
 	       MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
 #else
@@ -795,8 +898,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 
 	/* set speed */
 	if (speed == _1000BASET) {
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 		unsigned long pfc1;
+
 		mfsdr (sdr_pfc1, pfc1);
 		pfc1 |= SDR0_PFC1_EM_1000;
 		mtsdr (sdr_pfc1, pfc1);
@@ -942,6 +1047,14 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
 #define UIC0SR		uic0sr
 #endif
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define UICMSR_ETHX	uic0msr
+#define UICSR_ETHX	uic0sr
+#else
+#define UICMSR_ETHX	uic1msr
+#define UICSR_ETHX	uic1sr
+#endif
+
 int enetInt (struct eth_device *dev)
 {
 	int serviced;
@@ -950,6 +1063,7 @@ int enetInt (struct eth_device *dev)
 	unsigned long emac_isr = 0;
 	unsigned long mal_rx_eob;
 	unsigned long my_uic0msr, my_uic1msr;
+	unsigned long my_uicmsr_ethx;
 
 #if defined(CONFIG_440GX)
 	unsigned long my_uic2msr;
@@ -977,8 +1091,11 @@ int enetInt (struct eth_device *dev)
 #if defined(CONFIG_440GX)
 		my_uic2msr = mfdcr (uic2msr);
 #endif
+		my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
+
 		if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
-		    && !(my_uic1msr & (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
+		    && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))
+		    && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) {
 			/* not for us */
 			return (rc);
 		}
@@ -997,8 +1114,7 @@ int enetInt (struct eth_device *dev)
 			mal_isr = mfdcr (malesr);
 			/* look for mal error */
 			if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
-				mal_err (dev, mal_isr, my_uic0msr,
-					 MAL_UIC_DEF, MAL_UIC_ERR);
+				mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR);
 				serviced = 1;
 				rc = 0;
 			}
@@ -1006,7 +1122,7 @@ int enetInt (struct eth_device *dev)
 
 		/* port by port dispatch of emac interrupts */
 		if (hw_p->devnum == 0) {
-			if (UIC_ETH0 & my_uic1msr) {	/* look for EMAC errors */
+			if (UIC_ETH0 & my_uicmsr_ethx) {	/* look for EMAC errors */
 				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
 				if ((hw_p->emac_ier & emac_isr) != 0) {
 					emac_err (dev, emac_isr);
@@ -1017,14 +1133,15 @@ int enetInt (struct eth_device *dev)
 			if ((hw_p->emac_ier & emac_isr)
 			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
 				mtdcr (UIC0SR, UIC_MRE | UIC_MTE);	/* Clear */
-				mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+				mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+				mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
 				return (rc);	/* we had errors so get out */
 			}
 		}
 
 #if !defined(CONFIG_440SP)
 		if (hw_p->devnum == 1) {
-			if (UIC_ETH1 & my_uic1msr) {	/* look for EMAC errors */
+			if (UIC_ETH1 & my_uicmsr_ethx) {	/* look for EMAC errors */
 				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
 				if ((hw_p->emac_ier & emac_isr) != 0) {
 					emac_err (dev, emac_isr);
@@ -1035,7 +1152,8 @@ int enetInt (struct eth_device *dev)
 			if ((hw_p->emac_ier & emac_isr)
 			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
 				mtdcr (UIC0SR, UIC_MRE | UIC_MTE);	/* Clear */
-				mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+				mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
+				mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
 				return (rc);	/* we had errors so get out */
 			}
 		}
@@ -1102,10 +1220,10 @@ int enetInt (struct eth_device *dev)
 		mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
 		switch (hw_p->devnum) {
 		case 0:
-			mtdcr (uic1sr, UIC_ETH0);
+			mtdcr (UICSR_ETHX, UIC_ETH0);
 			break;
 		case 1:
-			mtdcr (uic1sr, UIC_ETH1);
+			mtdcr (UICSR_ETHX, UIC_ETH1);
 			break;
 #if defined (CONFIG_440GX)
 		case 2:
@@ -1512,7 +1630,7 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 
 		if (0 == virgin) {
 			/* set the MAL IER ??? names may change with new spec ??? */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 			mal_ier =
 				MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
 				MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile
index 93416b57bf7..16dc8d62c05 100644
--- a/cpu/ppc4xx/Makefile
+++ b/cpu/ppc4xx/Makefile
@@ -30,7 +30,7 @@ SOBJS	= dcr.o
 COBJS	= 405gp_pci.o 4xx_enet.o \
 	  bedbug_405.o commproc.o \
 	  cpu.o cpu_init.o i2c.o interrupts.o \
-	  miiphy.o sdram.o serial.o \
+	  miiphy.o ndfc.o sdram.o serial.o \
 	  spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o \
 	  440spe_pcie.o
 
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index bc51fbfdbed..94478dbb109 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -41,14 +41,15 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-
 #if defined(CONFIG_440)
 #define FREQ_EBC		(sys_info.freqEPB)
 #else
 #define FREQ_EBC		(sys_info.freqPLB / sys_info.pllExtBusDiv)
 #endif
 
-#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_405GP) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 #define PCI_ASYNC
 
@@ -58,7 +59,8 @@ int pci_async_enabled(void)
 	return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
 #endif
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	unsigned long val;
 
 	mfsdr(sdr_sdstp1, val);
@@ -82,9 +84,10 @@ int pci_arbiter_enabled(void)
 	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
-     defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
-     defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	unsigned long val;
 
 	mfsdr(sdr_sdstp1, val);
@@ -93,8 +96,10 @@ int pci_arbiter_enabled(void)
 }
 #endif
 
-#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) ||  \
-     defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 
 #define I2C_BOOTROM
 
@@ -102,17 +107,75 @@ int i2c_bootrom_enabled(void)
 {
 #if defined(CONFIG_405EP)
 	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
-#endif
-
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
-     defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
-	defined(CONFIG_440SPE)
+#else
 	unsigned long val;
 
 	mfsdr(sdr_sdcs, val);
 	return (val & SDR0_SDCS_SDD);
 #endif
 }
+
+#if defined(CONFIG_440GX)
+#define SDR0_PINSTP_SHIFT	29
+static char *bootstrap_str[] = {
+	"EBC (16 bits)",
+	"EBC (8 bits)",
+	"EBC (32 bits)",
+	"EBC (8 bits)",
+	"PCI",
+	"I2C (Addr 0x54)",
+	"Reserved",
+	"I2C (Addr 0x50)",
+};
+#endif
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#define SDR0_PINSTP_SHIFT	30
+static char *bootstrap_str[] = {
+	"EBC (8 bits)",
+	"PCI",
+	"I2C (Addr 0x54)",
+	"I2C (Addr 0x50)",
+};
+#endif
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define SDR0_PINSTP_SHIFT	29
+static char *bootstrap_str[] = {
+	"EBC (8 bits)",
+	"PCI",
+	"NAND (8 bits)",
+	"EBC (16 bits)",
+	"EBC (16 bits)",
+	"I2C (Addr 0x54)",
+	"PCI",
+	"I2C (Addr 0x52)",
+};
+#endif
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_PINSTP_SHIFT	29
+static char *bootstrap_str[] = {
+	"EBC (8 bits)",
+	"EBC (16 bits)",
+	"EBC (16 bits)",
+	"NAND (8 bits)",
+	"PCI",
+	"I2C (Addr 0x54)",
+	"PCI",
+	"I2C (Addr 0x52)",
+};
+#endif
+
+#if defined(SDR0_PINSTP_SHIFT)
+static int bootstrap_option(void)
+{
+	unsigned long val;
+
+	mfsdr(sdr_pinstp, val);
+	return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT);
+}
+#endif /* SDR0_PINSTP_SHIFT */
 #endif
 
 
@@ -244,6 +307,22 @@ int checkcpu (void)
 #endif /* CONFIG_440GR */
 #endif /* CONFIG_440 */
 
+	case PVR_440EPX1_RA:
+		puts("EPx Rev. A - Security/Kasumi support");
+		break;
+
+	case PVR_440EPX2_RA:
+		puts("EPx Rev. A - No Security/Kasumi support");
+		break;
+
+	case PVR_440GRX1_RA:
+		puts("GRx Rev. A - Security/Kasumi support");
+		break;
+
+	case PVR_440GRX2_RA:
+		puts("GRx Rev. A - No Security/Kasumi support");
+		break;
+
 	case PVR_440SP_RA:
 		puts("SP Rev. A");
 		break;
@@ -272,6 +351,10 @@ int checkcpu (void)
 
 #if defined(I2C_BOOTROM)
 	printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
+#if defined(SDR0_PINSTP_SHIFT)
+	printf ("       Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
+	printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
+#endif
 #endif
 
 #if defined(CONFIG_PCI)
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 886f4051562..c5a9f02566a 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -57,12 +57,13 @@ static struct irq_action irq_vecs1[32]; /* For UIC1 */
 
 void uic1_interrupt( void * parms); /* UIC1 handler */
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 static struct irq_action irq_vecs2[32]; /* For UIC2 */
 void uic2_interrupt( void * parms); /* UIC2 handler */
 #endif /* CONFIG_440GX CONFIG_440SPE */
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 static struct irq_action irq_vecs3[32]; /* For UIC3 */
 void uic3_interrupt( void * parms); /* UIC3 handler */
 #endif /* CONFIG_440SPE */
@@ -119,12 +120,13 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 		irq_vecs1[vec].handler = NULL;
 		irq_vecs1[vec].arg = NULL;
 		irq_vecs1[vec].count = 0;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 		irq_vecs2[vec].handler = NULL;
 		irq_vecs2[vec].arg = NULL;
 		irq_vecs2[vec].count = 0;
 #endif /* CONFIG_440GX */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 		irq_vecs3[vec].handler = NULL;
 		irq_vecs3[vec].arg = NULL;
 		irq_vecs3[vec].count = 0;
@@ -230,6 +232,32 @@ void external_interrupt(struct pt_regs *regs)
 
 } /* external_interrupt CONFIG_440GX */
 
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+void external_interrupt(struct pt_regs *regs)
+{
+	ulong uic_msr;
+
+	/*
+	 * Read masked interrupt status register to determine interrupt source
+	 */
+	/* 440 SPe uses base uic register */
+	uic_msr = mfdcr(uic0msr);
+
+	if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
+		uic1_interrupt(0);
+
+	if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
+		uic2_interrupt(0);
+
+	if (uic_msr & ~(UICB0_ALL))
+		uic0_interrupt(0);
+
+	mtdcr(uic0sr, uic_msr);
+
+	return;
+
+} /* external_interrupt CONFIG_440EPX & CONFIG_440GRX */
+
 #elif defined(CONFIG_440SPE)
 void external_interrupt(struct pt_regs *regs)
 {
@@ -303,7 +331,8 @@ void external_interrupt(struct pt_regs *regs)
 }
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 /* Handler for UIC0 interrupt */
 void uic0_interrupt( void * parms)
 {
@@ -394,7 +423,8 @@ void uic1_interrupt( void * parms)
 }
 #endif /* defined(CONFIG_440) */
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 /* Handler for UIC2 interrupt */
 void uic2_interrupt( void * parms)
 {
@@ -496,7 +526,8 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
 	int i = vec;
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	if ((vec > 31) && (vec < 64)) {
 		i = vec - 32;
 		irqa = irq_vecs1;
@@ -523,7 +554,8 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
 	irqa[i].arg = arg;
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	if ((vec > 31) && (vec < 64))
 		mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
 	else if (vec > 63)
@@ -546,7 +578,8 @@ void irq_free_handler (int vec)
 	int i = vec;
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	if ((vec > 31) && (vec < 64)) {
 		irqa = irq_vecs1;
 		i = vec - 32;
@@ -567,7 +600,8 @@ void irq_free_handler (int vec)
 #endif
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	if ((vec > 31) && (vec < 64))
 		mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
 	else if (vec > 63)
@@ -635,7 +669,8 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	printf("\n");
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	printf ("\nUIC 2\n");
 	printf ("Nr  Routine   Arg       Count\n");
 
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index aa580ed48f9..6b98025308f 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -173,7 +173,8 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
 	}
 	sta_reg = reg;		/* reg address */
 	/* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #if defined(CONFIG_IBM_EMAC4_V4)      /* EMAC4 V4 changed bit setting */
 		sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
 #else
@@ -183,7 +184,9 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
 	sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
 #endif
 
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE)
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
+    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
+    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
 	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
 #endif
 	sta_reg = sta_reg | (addr << 5);	/* Phy address */
@@ -244,7 +247,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
 	sta_reg = 0;
 	sta_reg = reg;		/* reg address */
 	/* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #if defined(CONFIG_IBM_EMAC4_V4)      /* EMAC4 V4 changed bit setting */
 		sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
 #else
@@ -254,7 +258,9 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
 	sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
 #endif
 
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE)
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
+    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
+    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
 	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;	/* Set clock frequency (PLB freq. dependend) */
 #endif
 	sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */
diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
new file mode 100644
index 00000000000..e4ab326bbfc
--- /dev/null
+++ b/cpu/ppc4xx/ndfc.c
@@ -0,0 +1,173 @@
+/*
+ * Overview:
+ *   Platform independend driver for NDFC (NanD Flash Controller)
+ *   integrated into EP440 cores
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Based on original work by
+ *	Thomas Gleixner
+ *	Copyright 2006 IBM
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
+
+#include <nand.h>
+#include <linux/mtd/ndfc.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+
+static u8 hwctl = 0;
+
+static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+	switch (cmd) {
+	case NAND_CTL_SETCLE:
+		hwctl |= 0x1;
+		break;
+
+	case NAND_CTL_CLRCLE:
+		hwctl &= ~0x1;
+		break;
+
+	case NAND_CTL_SETALE:
+		hwctl |= 0x2;
+		break;
+
+	case NAND_CTL_CLRALE:
+		hwctl &= ~0x2;
+		break;
+	}
+}
+
+static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
+{
+        struct nand_chip *this = mtdinfo->priv;
+        ulong base = (ulong) this->IO_ADDR_W;
+
+	if (hwctl & 0x1)
+		out8(base + NDFC_CMD, byte);
+	else if (hwctl & 0x2)
+		out8(base + NDFC_ALE, byte);
+	else
+		out8(base + NDFC_DATA, byte);
+}
+
+static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
+{
+        struct nand_chip *this = mtdinfo->priv;
+        ulong base = (ulong) this->IO_ADDR_W;
+
+	return (in8(base + NDFC_DATA));
+}
+
+static int ndfc_dev_ready(struct mtd_info *mtdinfo)
+{
+        struct nand_chip *this = mtdinfo->priv;
+        ulong base = (ulong) this->IO_ADDR_W;
+
+	while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY))
+		;
+
+	return 1;
+}
+
+#ifndef CONFIG_NAND_SPL
+/*
+ * Don't use these speedup functions in NAND boot image, since the image
+ * has to fit into 4kByte.
+ */
+
+/*
+ * Speedups for buffer read/write/verify
+ *
+ * NDFC allows 32bit read/write of data. So we can speed up the buffer
+ * functions. No further checking, as nand_base will always read/write
+ * page aligned.
+ */
+static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
+{
+        struct nand_chip *this = mtdinfo->priv;
+        ulong base = (ulong) this->IO_ADDR_W;
+	uint32_t *p = (uint32_t *) buf;
+
+	for(;len > 0; len -= 4)
+		*p++ = in32(base + NDFC_DATA);
+}
+
+static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+        struct nand_chip *this = mtdinfo->priv;
+        ulong base = (ulong) this->IO_ADDR_W;
+	uint32_t *p = (uint32_t *) buf;
+
+	for(; len > 0; len -= 4)
+		out32(base + NDFC_DATA, *p++);
+}
+
+static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+        struct nand_chip *this = mtdinfo->priv;
+        ulong base = (ulong) this->IO_ADDR_W;
+	uint32_t *p = (uint32_t *) buf;
+
+	for(; len > 0; len -= 4)
+		if (*p++ != in32(base + NDFC_DATA))
+			return -1;
+
+	return 0;
+}
+#endif /* #ifndef CONFIG_NAND_SPL */
+
+void board_nand_init(struct nand_chip *nand)
+{
+	nand->eccmode = NAND_ECC_SOFT;
+
+	nand->hwcontrol  = ndfc_hwcontrol;
+	nand->read_byte  = ndfc_read_byte;
+	nand->write_byte = ndfc_write_byte;
+	nand->dev_ready  = ndfc_dev_ready;
+
+#ifndef CONFIG_NAND_SPL
+	nand->write_buf  = ndfc_write_buf;
+	nand->read_buf   = ndfc_read_buf;
+	nand->verify_buf = ndfc_verify_buf;
+#else
+	/*
+	 * Setup EBC (CS0 only right now)
+	 */
+	mtdcr(ebccfga, xbcfg);
+	mtdcr(ebccfgd, 0xb8400000);
+
+	mtebc(pb0cr, CFG_EBC_PB0CR);
+	mtebc(pb0ap, CFG_EBC_PB0AP);
+#endif
+
+	/* Set NandFlash Core Configuration Register */
+	/* Chip select 3, 1col x 2 rows */
+	out32(CFG_NAND_BASE + NDFC_CCR, 0x00000000 | (CFG_NAND_CS << 24));
+	out32(CFG_NAND_BASE + NDFC_BCFG0 + (CFG_NAND_CS << 2), 0x80002222);
+}
+
+#endif
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c
index ad3ca6e819e..fab0d950063 100644
--- a/cpu/ppc4xx/serial.c
+++ b/cpu/ppc4xx/serial.c
@@ -264,10 +264,12 @@ int serial_tstc ()
 #endif	/* CONFIG_IOP480 */
 
 /*****************************************************************************/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
+    defined(CONFIG_440)
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000300
 #define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000400
 #else
@@ -279,15 +281,34 @@ int serial_tstc ()
 #define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000600
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define CR0_MASK        0xdfffffff
-#define CR0_EXTCLK_ENA  0x00800000
-#define CR0_UDIV_POS    0
-#else
+#if defined(CONFIG_440GP)
 #define CR0_MASK        0x3fff0000
 #define CR0_EXTCLK_ENA  0x00600000
 #define CR0_UDIV_POS    16
-#endif /* CONFIG_440GX */
+#define UDIV_SUBTRACT	1
+#define UART0_SDR	cntrl0
+#define MFREG(a, d)	d = mfdcr(a)
+#define MTREG(a, d)	mtdcr(a, d)
+#else /* #if defined(CONFIG_440GP) */
+/* all other 440 PPC's access clock divider via sdr register */
+#define CR0_MASK        0xdfffffff
+#define CR0_EXTCLK_ENA  0x00800000
+#define CR0_UDIV_POS    0
+#define UDIV_SUBTRACT	0
+#define UART0_SDR	sdr_uart0
+#define UART1_SDR	sdr_uart1
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
+    defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPe)
+#define UART2_SDR	sdr_uart2
+#endif
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
+    defined(CONFIG_440GR) || defined(CONFIG_440GRx)
+#define UART3_SDR	sdr_uart3
+#endif
+#define MFREG(a, d)	mfsdr(a, d)
+#define MTREG(a, d)	mtsdr(a, d)
+#endif /* #if defined(CONFIG_440GP) */
 #elif defined(CONFIG_405EP)
 #define UART0_BASE      0xef600300
 #define UART1_BASE      0xef600400
@@ -309,21 +330,15 @@ int serial_tstc ()
 #if defined(CONFIG_UART1_CONSOLE)
 #define ACTING_UART0_BASE	UART1_BASE
 #define ACTING_UART1_BASE	UART0_BASE
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
-	defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
-	defined(CONFIG_440SPE)
-#define UART0_SDR           sdr_uart1
-#define UART1_SDR           sdr_uart0
-#endif /* CONFIG_440GX */
 #else
 #define ACTING_UART0_BASE	UART0_BASE
 #define ACTING_UART1_BASE	UART1_BASE
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
-	defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
-	defined(CONFIG_440SPE)
-#define UART0_SDR           sdr_uart0
-#define UART1_SDR           sdr_uart1
-#endif /* CONFIG_440GX */
+#endif
+
+#if defined(CONFIG_SERIAL_MULTI)
+#define UART_BASE	dev_base
+#else
+#define UART_BASE	ACTING_UART0_BASE
 #endif
 
 #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
@@ -419,7 +434,7 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
 	*pbdiv = div/udiv;
 
 }
-#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
+#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
 
 /*
  * Minimal serial functions needed to use one of the SMC ports
@@ -441,23 +456,9 @@ int serial_init(void)
 	unsigned long tmp;
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
-	defined(CONFIG_440SPE)
-#if defined(CONFIG_SERIAL_MULTI)
-	if (UART0_BASE == dev_base) {
-		mfsdr(UART0_SDR,reg);
-		reg &= ~CR0_MASK;
-	} else {
-		mfsdr(UART1_SDR,reg);
-		reg &= ~CR0_MASK;
-	}
-#else
-	mfsdr(UART0_SDR,reg);
+	MFREG(UART0_SDR, reg);
 	reg &= ~CR0_MASK;
-#endif
-#else
-	reg = mfdcr(cntrl0) & ~CR0_MASK;
-#endif /* CONFIG_440GX */
+
 #ifdef CFG_EXT_SERIAL_CLOCK
 	reg |= CR0_EXTCLK_ENA;
 	udiv = 1;
@@ -471,47 +472,34 @@ int serial_init(void)
 	serial_divs (gd->baudrate, &udiv, &bdiv);
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
-	defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
-	defined(CONFIG_440SPE)
-	reg |= udiv << CR0_UDIV_POS;	/* set the UART divisor */
-#if defined(CONFIG_SERIAL_MULTI)
-	if (UART0_BASE == dev_base) {
-		mtsdr (UART0_SDR,reg);
-	} else {
-		mtsdr (UART1_SDR,reg);
-	}
-#else
-	mtsdr (UART0_SDR,reg);
+	reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS;	/* set the UART divisor */
+
+	/*
+	 * Configure input clock to baudrate generator for all
+	 * available serial ports here
+	 */
+	MTREG(UART0_SDR, reg);
+#if defined(UART1_SDR)
+	MTREG(UART1_SDR, reg);
 #endif
-#else
-	reg |= (udiv - 1) << CR0_UDIV_POS;	/* set the UART divisor */
-	mtdcr (cntrl0, reg);
+#if defined(UART2_SDR)
+	MTREG(UART2_SDR, reg);
 #endif
-
-#if defined(CONFIG_SERIAL_MULTI)
-	out8 (dev_base + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (dev_base + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (dev_base + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
-	out8 (dev_base + UART_FCR, 0x00);	/* disable FIFO */
-	out8 (dev_base + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in8 (dev_base + UART_LSR);	/* clear line status */
-	val = in8 (dev_base + UART_RBR);	/* read receive buffer */
-	out8 (dev_base + UART_SCR, 0x00);	/* set scratchpad */
-	out8 (dev_base + UART_IER, 0x00);	/* set interrupt enable reg */
-#else
-	out8 (ACTING_UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (ACTING_UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (ACTING_UART0_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
-	out8 (ACTING_UART0_BASE + UART_FCR, 0x00);	/* disable FIFO */
-	out8 (ACTING_UART0_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in8 (ACTING_UART0_BASE + UART_LSR);	/* clear line status */
-	val = in8 (ACTING_UART0_BASE + UART_RBR);	/* read receive buffer */
-	out8 (ACTING_UART0_BASE + UART_SCR, 0x00);	/* set scratchpad */
-	out8 (ACTING_UART0_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
+#if defined(UART3_SDR)
+	MTREG(UART3_SDR, reg);
 #endif
+
+	out8(UART_BASE + UART_LCR, 0x80);	/* set DLAB bit */
+	out8(UART_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
+	out8(UART_BASE + UART_DLM, bdiv >> 8);	/* set baudrate divisor */
+	out8(UART_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	out8(UART_BASE + UART_FCR, 0x00);	/* disable FIFO */
+	out8(UART_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
+	val = in8(UART_BASE + UART_LSR);	/* clear line status */
+	val = in8(UART_BASE + UART_RBR);	/* read receive buffer */
+	out8(UART_BASE + UART_SCR, 0x00);	/* set scratchpad */
+	out8(UART_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
+
 	return (0);
 }
 
@@ -564,29 +552,17 @@ int serial_init (void)
 	tmp = gd->baudrate * udiv * 16;
 	bdiv = (clk + tmp / 2) / tmp;
 
-#if defined(CONFIG_SERIAL_MULTI)
-	out8 (dev_base + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (dev_base + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (dev_base + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
-	out8 (dev_base + UART_FCR, 0x00);	/* disable FIFO */
-	out8 (dev_base + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in8 (dev_base + UART_LSR);	/* clear line status */
-	val = in8 (dev_base + UART_RBR);	/* read receive buffer */
-	out8 (dev_base + UART_SCR, 0x00);	/* set scratchpad */
-	out8 (dev_base + UART_IER, 0x00);	/* set interrupt enable reg */
-#else
-	out8 (ACTING_UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (ACTING_UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (ACTING_UART0_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
-	out8 (ACTING_UART0_BASE + UART_FCR, 0x00);	/* disable FIFO */
-	out8 (ACTING_UART0_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in8 (ACTING_UART0_BASE + UART_LSR);	/* clear line status */
-	val = in8 (ACTING_UART0_BASE + UART_RBR);	/* read receive buffer */
-	out8 (ACTING_UART0_BASE + UART_SCR, 0x00);	/* set scratchpad */
-	out8 (ACTING_UART0_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
-#endif
+	out8(UART_BASE + UART_LCR, 0x80);	/* set DLAB bit */
+	out8(UART_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
+	out8(UART_BASE + UART_DLM, bdiv >> 8);	/* set baudrate divisor */
+	out8(UART_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	out8(UART_BASE + UART_FCR, 0x00);	/* disable FIFO */
+	out8(UART_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
+	val = in8(UART_BASE + UART_LSR);	/* clear line status */
+	val = in8(UART_BASE + UART_RBR);	/* read receive buffer */
+	out8(UART_BASE + UART_SCR, 0x00);	/* set scratchpad */
+	out8(UART_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
+
 	return (0);
 }
 
@@ -598,55 +574,10 @@ void serial_setbrg_dev (unsigned long dev_base)
 void serial_setbrg (void)
 #endif
 {
-	unsigned long tmp;
-	unsigned long clk;
-	unsigned long udiv;
-	unsigned short bdiv;
-
-#ifdef CFG_EXT_SERIAL_CLOCK
-	clk = CFG_EXT_SERIAL_CLOCK;
-#else
-	clk = gd->cpu_clk;
-#endif
-
-#ifdef CONFIG_405EP
-	udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
-#else
-	udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
-#endif /* CONFIG_405EP */
-
-#if !defined(CFG_EXT_SERIAL_CLOCK) && \
-	( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
-	  defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
-	  defined(CONFIG_440SPE) )
-	serial_divs (gd->baudrate, &udiv, &bdiv);
-	tmp = udiv << CR0_UDIV_POS;		/* set the UART divisor */
-#if defined(CONFIG_SERIAL_MULTI)
-	if (UART0_BASE == dev_base) {
-		mtsdr (UART0_SDR, tmp);
-	} else {
-		mtsdr (UART1_SDR, tmp);
-	}
-#else
-	mtsdr (UART0_SDR, tmp);
-#endif
-
-#else
-
-	tmp = gd->baudrate * udiv * 16;
-	bdiv = (clk + tmp / 2) / tmp;
-#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */
-
 #if defined(CONFIG_SERIAL_MULTI)
-	out8 (dev_base + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (dev_base + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (dev_base + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	serial_init_dev(dev_base);
 #else
-	out8 (ACTING_UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (ACTING_UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (ACTING_UART0_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	serial_init();
 #endif
 }
 
@@ -667,19 +598,11 @@ void serial_putc (const char c)
 
 	/* check THRE bit, wait for transmiter available */
 	for (i = 1; i < 3500; i++) {
-#if defined(CONFIG_SERIAL_MULTI)
-		if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20)
-#else
-		if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
-#endif
+		if ((in8 (UART_BASE + UART_LSR) & 0x20) == 0x20)
 			break;
 		udelay (100);
 	}
-#if defined(CONFIG_SERIAL_MULTI)
-	out8 (dev_base + UART_THR, c);	/* put character out */
-#else
-	out8 (ACTING_UART0_BASE + UART_THR, c);	/* put character out */
-#endif
+	out8 (UART_BASE + UART_THR, c);	/* put character out */
 }
 
 #if defined(CONFIG_SERIAL_MULTI)
@@ -709,11 +632,7 @@ int serial_getc (void)
 #if defined(CONFIG_HW_WATCHDOG)
 		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
 #endif	/* CONFIG_HW_WATCHDOG */
-#if defined(CONFIG_SERIAL_MULTI)
-		status = in8 (dev_base + UART_LSR);
-#else
-		status = in8 (ACTING_UART0_BASE + UART_LSR);
-#endif
+		status = in8 (UART_BASE + UART_LSR);
 		if ((status & asyncLSRDataReady1) != 0x0) {
 			break;
 		}
@@ -721,22 +640,14 @@ int serial_getc (void)
 				asyncLSROverrunError1 |
 				asyncLSRParityError1  |
 				asyncLSRBreakInterrupt1 )) != 0) {
-#if defined(CONFIG_SERIAL_MULTI)
-			out8 (dev_base + UART_LSR,
-#else
-			out8 (ACTING_UART0_BASE + UART_LSR,
-#endif
+			out8 (UART_BASE + UART_LSR,
 			      asyncLSRFramingError1 |
 			      asyncLSROverrunError1 |
 			      asyncLSRParityError1  |
 			      asyncLSRBreakInterrupt1);
 		}
 	}
-#if defined(CONFIG_SERIAL_MULTI)
-	return (0x000000ff & (int) in8 (dev_base));
-#else
-	return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
-#endif
+	return (0x000000ff & (int) in8 (UART_BASE));
 }
 
 #if defined(CONFIG_SERIAL_MULTI)
@@ -747,11 +658,7 @@ int serial_tstc (void)
 {
 	unsigned char status;
 
-#if defined(CONFIG_SERIAL_MULTI)
-	status = in8 (dev_base + UART_LSR);
-#else
-	status = in8 (ACTING_UART0_BASE + UART_LSR);
-#endif
+	status = in8 (UART_BASE + UART_LSR);
 	if ((status & asyncLSRDataReady1) != 0x0) {
 		return (1);
 	}
@@ -759,11 +666,7 @@ int serial_tstc (void)
 			asyncLSROverrunError1 |
 			asyncLSRParityError1  |
 			asyncLSRBreakInterrupt1 )) != 0) {
-#if defined(CONFIG_SERIAL_MULTI)
-		out8 (dev_base + UART_LSR,
-#else
-		out8 (ACTING_UART0_BASE + UART_LSR,
-#endif
+		out8 (UART_BASE + UART_LSR,
 		      asyncLSRFramingError1 |
 		      asyncLSROverrunError1 |
 		      asyncLSRParityError1  |
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index e552c034733..2d16a83420a 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -199,7 +199,8 @@ ulong get_PCI_freq (void)
 
 #elif defined(CONFIG_440)
 
-#if  defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 void get_sys_info (sys_info_t *sysInfo)
 {
 	unsigned long temp;
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 60ed2d54536..5a1ab386b18 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -117,12 +117,16 @@
 
 	.extern ext_bus_cntlr_init
 	.extern sdram_init
+#ifdef CONFIG_NAND_U_BOOT
+	.extern reconfig_tlb0
+#endif
 
 /*
  * Set up GOT: Global Offset Table
  *
  * Use r14 to access the GOT
  */
+#if !defined(CONFIG_NAND_SPL)
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
 	GOT_ENTRY(_FIXUP_TABLE_)
@@ -136,6 +140,18 @@
 	GOT_ENTRY(_end)
 	GOT_ENTRY(__bss_start)
 	END_GOT
+#endif /* CONFIG_NAND_SPL */
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+	/*
+	 * NAND U-Boot image is started from offset 0
+	 */
+	.text
+	bl	reconfig_tlb0
+	GET_GOT
+	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */
+	bl	board_init_f
+#endif
 
 /*
  * 440 Startup -- on reset only the top 4k of the effective
@@ -150,11 +166,21 @@
  */
 
 #if defined(CONFIG_440)
+#if !defined(CONFIG_NAND_SPL)
     .section .bootpg,"ax"
+#endif
     .globl _start_440
 
 /**************************************************************************/
 _start_440:
+        /*--------------------------------------------------------------------+
+        | 440EPX BUP Change - Hardware team request
+        +--------------------------------------------------------------------*/
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	sync
+	nop
+	nop
+#endif
 	/*----------------------------------------------------------------+
 	| Core bug fix.  Clear the esr
 	+-----------------------------------------------------------------*/
@@ -171,15 +197,19 @@ _start_440:
 	mtspr	srr1,r0
 	mtspr	csrr0,r0
 	mtspr	csrr1,r0
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)  /* NOTE: 440GX adds machine check status regs */
+	/* NOTE: 440GX adds machine check status regs */
+#if defined(CONFIG_440) && !defined(CONFIG_440GP)
 	mtspr	mcsrr0,r0
 	mtspr	mcsrr1,r0
-	mfspr	r1, mcsr
+	mfspr	r1,mcsr
 	mtspr	mcsr,r1
 #endif
 	/*----------------------------------------------------------------*/
 	/* Initialize debug */
 	/*----------------------------------------------------------------*/
+	mfspr	r1,dbcr0
+	andis.	r1, r1, 0x8000	/* test DBCR0[EDM] bit			*/
+	bne	skip_debug_init	/* if set, don't clear debug register	*/
 	mtspr	dbcr0,r0
 	mtspr	dbcr1,r0
 	mtspr	dbcr2,r0
@@ -193,6 +223,7 @@ _start_440:
 
 	mfspr	r1,dbsr
 	mtspr	dbsr,r1		/* Clear all valid bits */
+skip_debug_init:
 
 	/*----------------------------------------------------------------*/
 	/* CCR0 init */
@@ -352,7 +383,53 @@ rsttlb:	tlbwe	r0,r1,0x0000	/* Invalidate all entries (V=0)*/
 	/*----------------------------------------------------------------*/
 	/* Continue from 'normal' start */
 	/*----------------------------------------------------------------*/
-2:	bl	3f
+2:
+
+#if defined(CONFIG_NAND_SPL)
+	/*
+	 * Enable internal SRAM
+	 */
+	lis	r2,0x7fff
+	ori	r2,r2,0xffff
+	mfdcr	r1,isram0_dpc
+	and	r1,r1,r2		/* Disable parity check */
+	mtdcr	isram0_dpc,r1
+	mfdcr	r1,isram0_pmeg
+	and	r1,r1,r2		/* Disable pwr mgmt */
+	mtdcr	isram0_pmeg,r1
+
+	/*
+	 * Copy SPL from cache into internal SRAM
+	 */
+	li	r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
+	mtctr	r4
+	lis	r2,CFG_NAND_BOOT_SPL_SRC@h
+	ori	r2,r2,CFG_NAND_BOOT_SPL_SRC@l
+	lis	r3,CFG_NAND_BOOT_SPL_DST@h
+	ori	r3,r3,CFG_NAND_BOOT_SPL_DST@l
+spl_loop:
+	lwzu	r4,4(r2)
+	stwu	r4,4(r3)
+	bdnz	spl_loop
+
+	/*
+	 * Jump to code in RAM
+	 */
+	bl	00f
+00:	mflr	r10
+	lis	r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
+	ori	r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
+	sub	r10,r10,r3
+	addi	r10,r10,28
+	mtlr	r10
+	blr
+
+start_ram:
+	sync
+	isync
+#endif
+
+	bl	3f
 	b	_start
 
 3:	li	r0,0
@@ -366,6 +443,7 @@ rsttlb:	tlbwe	r0,r1,0x0000	/* Invalidate all entries (V=0)*/
  * r3 - 1st arg to board_init(): IMMP pointer
  * r4 - 2nd arg to board_init(): boot flag
  */
+#ifndef CONFIG_NAND_SPL
 	.text
 	.long	0x27051956		/* U-Boot Magic Number			*/
 	.globl	version_string
@@ -379,6 +457,7 @@ version_string:
  * location (0x100) is where the CriticalInput Execption should be.
  */
 	. = EXC_OFF_SYS_RESET
+#endif
 	.globl	_start
 _start:
 
@@ -417,7 +496,8 @@ _start:
 	/* Setup the internal SRAM */
 	/*----------------------------------------------------------------*/
 	li	r0,0
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+
+#ifdef CFG_INIT_RAM_DCACHE
 	/* Clear Dcache to use as RAM */
 	addis	r3,r0,CFG_INIT_RAM_ADDR@h
 	ori	r3,r3,CFG_INIT_RAM_ADDR@l
@@ -433,19 +513,22 @@ _start:
 	dcbz	r0,r3
 	addi	r3,r3,32
 	bdnz	..d_ag
-#else
-#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#endif /* CFG_INIT_RAM_DCACHE */
+
+	/* 440EP & 440GR are only 440er PPC's without internal SRAM */
+#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
+	/* not all PPC's have internal SRAM usable as L2-cache */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	mtdcr	l2_cache_cfg,r0		/* Ensure L2 Cache is off */
 #endif
-	mtdcr	isram0_sb1cr,r0		/* Disable bank 1 */
 
-	li	r2,0x7fff
+	lis	r2,0x7fff
 	ori	r2,r2,0xffff
 	mfdcr	r1,isram0_dpc
 	and	r1,r1,r2		/* Disable parity check */
 	mtdcr	isram0_dpc,r1
 	mfdcr	r1,isram0_pmeg
-	andis.	r1,r1,r2		/* Disable pwr mgmt */
+	and	r1,r1,r2		/* Disable pwr mgmt */
 	mtdcr	isram0_pmeg,r1
 
 	lis	r1,0x8000		/* BAS = 8000_0000 */
@@ -474,11 +557,12 @@ _start:
 	lis	r1, 0x0003
 	ori	r1,r1, 0x0984		/* fourth 64k */
 	mtdcr	isram0_sb3cr,r1
-#else
+#elif defined(CONFIG_440GP)
 	ori	r1,r1,0x0380		/* 8k rw */
 	mtdcr	isram0_sb0cr,r1
+	mtdcr	isram0_sb1cr,r0		/* Disable bank 1 */
 #endif
-#endif
+#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
 
 	/*----------------------------------------------------------------*/
 	/* Setup the stack in internal SRAM */
@@ -495,10 +579,14 @@ _start:
 	stwu	r1,-8(r1)		/* Save back chain and move SP */
 	stw	r0,+12(r1)		/* Save return addr (underflow vect) */
 
+#ifdef CONFIG_NAND_SPL
+	bl	nand_boot		/* will not return */
+#else
 	GET_GOT
 
 	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */
 	bl	board_init_f
+#endif
 
 #endif /* CONFIG_440 */
 
@@ -808,6 +896,7 @@ _start:
 	/*----------------------------------------------------------------------- */
 
 
+#ifndef CONFIG_NAND_SPL
 /*****************************************************************************/
 	.globl	_start_of_vectors
 _start_of_vectors:
@@ -1013,6 +1102,7 @@ crit_return:
 	lwz	r1,GPR1(r1)
 	SYNC
 	rfci
+#endif /* CONFIG_NAND_SPL */
 
 /* Cache functions.
 */
@@ -1254,6 +1344,7 @@ ppcSync:
 
 /*------------------------------------------------------------------------------*/
 
+#ifndef CONFIG_NAND_SPL
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
@@ -1267,7 +1358,9 @@ ppcSync:
  */
 	.globl	relocate_code
 relocate_code:
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SPE)
 	/*
 	 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
 	 * to speed up the boot process. Now this cache needs to be disabled.
@@ -1482,22 +1575,22 @@ trap_init:
 	cmplw	0, r7, r8
 	blt	4b
 
-#if !defined(CONFIG_440GX) && !defined(CONFIG_440SPE)
+#if !defined(CONFIG_440)
 	addi	r7,r0,0x1000		/* set ME bit (Machine Exceptions) */
 	oris	r7,r7,0x0002		/* set CE bit (Critical Exceptions) */
 	mtmsr	r7			/* change MSR */
 #else
-	bl	__440gx_msr_set
-	b	__440gx_msr_continue
+	bl	__440_msr_set
+	b	__440_msr_continue
 
-__440gx_msr_set:
+__440_msr_set:
 	addi	r7,r0,0x1000		/* set ME bit (Machine Exceptions) */
 	oris	r7,r7,0x0002		/* set CE bit (Critical Exceptions) */
 	mtspr	srr1,r7
 	mflr	r7
 	mtspr	srr0,r7
 	rfi
-__440gx_msr_continue:
+__440_msr_continue:
 #endif
 
 	mtlr	r4			/* restore link register	*/
@@ -1516,6 +1609,7 @@ trap_reloc:
 	stw	r0, 4(r7)
 
 	blr
+#endif /* CONFIG_NAND_SPL */
 
 
 /**************************************************************************/
diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c
index bb5765891f8..ab852c525cf 100644
--- a/cpu/ppc4xx/usb_ohci.c
+++ b/cpu/ppc4xx/usb_ohci.c
@@ -76,7 +76,7 @@
 #define m16_swap(x) swap_16(x)
 #define m32_swap(x) swap_32(x)
 
-#ifdef CONFIG_440EP
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
 #define ohci_cpu_to_le16(x) (x)
 #define ohci_cpu_to_le32(x) (x)
 #else
@@ -1599,7 +1599,11 @@ int usb_lowlevel_init(void)
 	gohci.disabled = 1;
 	gohci.sleeping = 0;
 	gohci.irq = -1;
-	gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
+#if defined(CONFIG_440EP)
+ 	gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
+#elif defined(CONFIG_440EPX)
+	gohci.regs = (struct ohci_regs *)(CFG_USB_HOST);
+#endif
 
 	gohci.flags = 0;
 	gohci.slot_name = "ppc440";
diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c
index 8262c54bef1..6140d2a9089 100644
--- a/cpu/ppc4xx/usbdev.c
+++ b/cpu/ppc4xx/usbdev.c
@@ -3,7 +3,7 @@
 #include <common.h>
 #include <asm/processor.h>
 
-#ifdef CONFIG_440EP
+#if (defined(CONFIG_440EP) || defined(CONFIG_440EPX)) && (CONFIG_COMMANDS & CFG_CMD_USB)
 
 #include <usb.h>
 #include "usbdev.h"
@@ -186,6 +186,21 @@ int usbInt(void)
 	return 0;
 }
 
+#if defined(CONFIG_440EPX)
+void usb_dev_init()
+{
+	printf("USB 2.0 Device init\n");
+
+	/*usb dev init */
+	*(unsigned char *)USB2D0_POWER_8 = 0xa1;	/* 2.0 */
+
+	/*enable interrupts */
+	*(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f;
+
+	irq_install_handler(VECNUM_HSB2D, (interrupt_handler_t *) usbInt,
+			    NULL);
+}
+#else
 void usb_dev_init()
 {
 #ifdef USB_2_0_DEVICE
@@ -210,5 +225,6 @@ void usb_dev_init()
 	irq_install_handler(VECNUM_USBDEV, (interrupt_handler_t *) usbInt,
 			    NULL);
 }
+#endif
 
-#endif				/*CONFIG_440EP */
+#endif /* CONFIG_440EP || CONFIG_440EPX */
diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h
index 93cef026a3f..70e436aab23 100644
--- a/cpu/ppc4xx/vecnum.h
+++ b/cpu/ppc4xx/vecnum.h
@@ -31,7 +31,94 @@
 #ifndef _VECNUMS_H_
 #define _VECNUMS_H_
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440_GRX)
+
+/* UIC 0 */
+#define VECNUM_U0                   0  /* UART 0                        */
+#define VECNUM_U1                   1  /* UART 1                        */
+#define VECNUM_IIC0                 2  /* IIC                           */
+#define VECNUM_KRD                  3  /* Kasumi Ready for data         */
+#define VECNUM_KDA                  4  /* Kasumi Data Available         */
+#define VECNUM_PCRW                 5  /* PCI command register write    */
+#define VECNUM_PPM                  6  /* PCI power management          */
+#define VECNUM_IIC1                 7  /* IIC                           */
+#define VECNUM_SPI                  8  /* SPI                           */
+#define VECNUM_EPCISER              9  /* External PCI SERR             */
+#define VECNUM_MTE                 10  /* MAL TXEOB                     */
+#define VECNUM_MRE                 11  /* MAL RXEOB                     */
+#define VECNUM_D0                  12  /* DMA channel 0                 */
+#define VECNUM_D1                  13  /* DMA channel 1                 */
+#define VECNUM_D2                  14  /* DMA channel 2                 */
+#define VECNUM_D3                  15  /* DMA channel 3                 */
+#define VECNUM_UD0                 16  /* UDMA irq 0                    */
+#define VECNUM_UD1                 17  /* UDMA irq 1                    */
+#define VECNUM_UD2                 18  /* UDMA irq 2                    */
+#define VECNUM_UD3                 19  /* UDMA irq 3                    */
+#define VECNUM_HSB2D               20  /* USB2.0 Device                 */
+#define VECNUM_USBDEV		   20  /* USB 1.1/USB 2.0 Device        */
+#define VECNUM_OHCI1               21  /* USB2.0 Host OHCI irq 1        */
+#define VECNUM_OHCI2               22  /* USB2.0 Host OHCI irq 2        */
+#define VECNUM_EIP94               23  /* Security EIP94                */
+#define VECNUM_ETH0                24  /* Emac 0                        */
+#define VECNUM_ETH1                25  /* Emac 1                        */
+#define VECNUM_EHCI                26  /* USB2.0 Host EHCI              */
+#define VECNUM_EIR4                27  /* External interrupt 4          */
+#define VECNUM_UIC2NC              28  /* UIC2 non-critical interrupt   */
+#define VECNUM_UIC2C               29  /* UIC2 critical interrupt       */
+#define VECNUM_UIC1NC              30  /* UIC1 non-critical interrupt   */
+#define VECNUM_UIC1C               31  /* UIC1 critical interrupt       */
+
+/* UIC 1 */
+#define VECNUM_MS           (32 +  0)  /* MAL SERR                      */
+#define VECNUM_MTDE         (32 +  1)  /* MAL TXDE                      */
+#define VECNUM_MRDE         (32 +  2)  /* MAL RXDE                      */
+#define VECNUM_U2           (32 +  3)  /* UART 2                        */
+#define VECNUM_U3           (32 +  4)  /* UART 3                        */
+#define VECNUM_EBCO         (32 +  5)  /* EBCO interrupt status         */
+#define VECNUM_NDFC         (32 +  6)  /* NDFC                          */
+#define VECNUM_KSLE         (32 +  7)  /* KASUMI slave error            */
+#define VECNUM_CT5          (32 +  8)  /* GPT compare timer 5           */
+#define VECNUM_CT6          (32 +  9)  /* GPT compare timer 6           */
+#define VECNUM_PLB34I0      (32 + 10)  /* PLB3X4X MIRQ0                 */
+#define VECNUM_PLB34I1      (32 + 11)  /* PLB3X4X MIRQ1                 */
+#define VECNUM_PLB34I2      (32 + 12)  /* PLB3X4X MIRQ2                 */
+#define VECNUM_PLB34I3      (32 + 13)  /* PLB3X4X MIRQ3                 */
+#define VECNUM_PLB34I4      (32 + 14)  /* PLB3X4X MIRQ4                 */
+#define VECNUM_PLB34I5      (32 + 15)  /* PLB3X4X MIRQ5                 */
+#define VECNUM_CT0          (32 + 16)  /* GPT compare timer 0           */
+#define VECNUM_CT1          (32 + 17)  /* GPT compare timer 1           */
+#define VECNUM_EIR7         (32 + 18)  /* External interrupt 7          */
+#define VECNUM_EIR8         (32 + 19)  /* External interrupt 8          */
+#define VECNUM_EIR9         (32 + 20)  /* External interrupt 9          */
+#define VECNUM_CT2          (32 + 21)  /* GPT compare timer 2           */
+#define VECNUM_CT3          (32 + 22)  /* GPT compare timer 3           */
+#define VECNUM_CT4          (32 + 23)  /* GPT compare timer 4           */
+#define VECNUM_SRE          (32 + 24)  /* Serial ROM error              */
+#define VECNUM_GPTDC        (32 + 25)  /* GPT decrementer pulse         */
+#define VECNUM_RSVD0        (32 + 26)  /* Reserved                      */
+#define VECNUM_EPCIPER      (32 + 27)  /* External PCI PERR             */
+#define VECNUM_EIR0         (32 + 28)  /* External interrupt 0          */
+#define VECNUM_EWU0         (32 + 29)  /* Ethernet 0 wakeup             */
+#define VECNUM_EIR1         (32 + 30)  /* External interrupt 1          */
+#define VECNUM_EWU1         (32 + 31)  /* Ethernet 1 wakeup             */
+
+#define VECNUM_TXDE         VECNUM_MTDE
+#define VECNUM_RXDE         VECNUM_MRDE
+
+/* UIC 2 */
+#define VECNUM_EIR5         (62 +  0)  /* External interrupt 5          */
+#define VECNUM_EIR6         (62 +  1)  /* External interrupt 6          */
+#define VECNUM_OPB          (62 +  2)  /* OPB to PLB bridge int stat    */
+#define VECNUM_EIR2         (62 +  3)  /* External interrupt 2          */
+#define VECNUM_EIR3         (62 +  4)  /* External interrupt 3          */
+#define VECNUM_DDR2         (62 +  5)  /* DDR2 sdram                    */
+#define VECNUM_MCTX0        (62 +  6)  /* MAl intp coalescence TX0      */
+#define VECNUM_MCTX1        (62 +  7)  /* MAl intp coalescence TX1      */
+#define VECNUM_MCTR0        (62 +  8)  /* MAl intp coalescence TR0      */
+#define VECNUM_MCTR1        (62 +  9)  /* MAl intp coalescence TR1      */
+
+#elif defined(CONFIG_440SPE)
+
 /* UIC 0 */
 #define VECNUM_U0           0           /* UART0                        */
 #define VECNUM_U1           1           /* UART1                        */
diff --git a/doc/README.nand-boot-ppc440 b/doc/README.nand-boot-ppc440
new file mode 100644
index 00000000000..a82a10ee6a5
--- /dev/null
+++ b/doc/README.nand-boot-ppc440
@@ -0,0 +1,36 @@
+-----------------------------
+NAND boot on PPC440 platforms
+-----------------------------
+
+This document describes the U-Boot NAND boot feature as it
+is implemented for the AMCC Sequoia (PPC440EPx) board.
+
+The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH,
+completely without NOR FLASH. This can be done by using the NAND
+boot feature of the 440 NAND flash controller (NDFC).
+
+Here a short desciption of the different boot stages:
+
+a) IPL (Initial Program Loader, integrated inside CPU)
+------------------------------------------------------
+Will load first 4k from NAND (SPL) into cache and execute it from there.
+
+b) SPL (Secondary Program Loader)
+---------------------------------
+Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+controller and the NAND controller so that the special U-Boot image can be
+loaded from NAND to SDRAM.
+This special image is build in the directory "nand_spl".
+
+c) NUB (NAND U-Boot)
+--------------------
+This NAND U-Boot (NUB) is a special U-Boot version which can be started
+from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+
+On 440EPx the SPL is copied to internal SRAM before the NAND controller
+is set up. While still running from cache, I experienced problems accessing
+the NAND controller.
+
+
+September 07 2006, Stefan Roese <sr@denx.de>
diff --git a/dtt/lm75.c b/dtt/lm75.c
index 59daa453976..63f3b7551e9 100644
--- a/dtt/lm75.c
+++ b/dtt/lm75.c
@@ -146,8 +146,13 @@ static int _dtt_init(int sensor)
     /*
      * Setup configuraton register
      */
+#ifdef CONFIG_DTT_AD7414
+    /* config = alert active low and disabled */
+    val = 0x60;
+#else
     /* config = 6 sample integration, int mode, active low, and enable */
     val = 0x18;
+#endif
     if (dtt_write(sensor, DTT_CONFIG, val) != 0)
 	return 1;
 
diff --git a/include/405_mal.h b/include/405_mal.h
index 05985869534..2a421848b4b 100644
--- a/include/405_mal.h
+++ b/include/405_mal.h
@@ -92,7 +92,7 @@
 #define MAL_ESR_PBEI	  0x00000001
       /* ^^			 ^^   */
       /* Mal IER		      */
-#ifdef CONFIG_440SPE
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define MAL_IER_PT	  0x00000080
 #define MAL_IER_PRE	  0x00000040
 #define MAL_IER_PWE	  0x00000020
diff --git a/include/440_i2c.h b/include/440_i2c.h
index 9c90a9e3c48..0c2bf362730 100644
--- a/include/440_i2c.h
+++ b/include/440_i2c.h
@@ -1,7 +1,8 @@
 #ifndef _440_i2c_h_
 #define _440_i2c_h_
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define    I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
 #else
 #define    I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 44b23f1eb4c..bbd3497c50e 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -728,6 +728,10 @@
 #define PVR_440EP_RC	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
 #define PVR_440GR_RA	0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
 #define PVR_440GR_RB	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
+#define PVR_440EPX1_RA  0x216218D0 /* 440EPX rev A with Security / Kasumi */
+#define PVR_440EPX2_RA  0x216218D4 /* 440EPX rev A without Security / Kasumi */
+#define PVR_440GRX1_RA  0x216218D8 /* 440GRX rev A with Security / Kasumi */
+#define PVR_440GRX2_RA  0x216218DC /* 440GRX rev A without Security / Kasumi */
 #define PVR_440GX_RA	0x51B21850
 #define PVR_440GX_RB	0x51B21851
 #define PVR_440GX_RC	0x51B21892
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index f7aa55f3343..794a6d49747 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -108,7 +108,8 @@ typedef struct bd_info {
 #endif
 
 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR)
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	unsigned int	bi_opbfreq;		/* OPB clock in Hz */
 	int		bi_iic_fast[2];		/* Use fast i2c mode */
 #endif
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index cd4339b5822..4961011b5cd 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -73,6 +73,7 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
 #define CFG_INIT_RAM_END	(4 << 10)
 #define CFG_GBL_DATA_SIZE	256		    	/* num bytes initial data	*/
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index 50c1c4fd4cb..23bdfc8dfb9 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -63,6 +63,7 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
 #define CFG_INIT_RAM_END	(8 << 10)
 #define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
new file mode 100644
index 00000000000..d3fcc032aa5
--- /dev/null
+++ b/include/configs/sequoia.h
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * sequoia.h - configuration for Sequoia board (PowerPC440EPx)
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_SEQUOIA		1		/* Board is Sequoia	*/
+#define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
+#define CONFIG_4xx		1		/* ... PPC4xx family	*/
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+#define CFG_BOOT_BASE_ADDR	0xf0000000
+#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CFG_FLASH_BASE		0xfe000000	/* start of FLASH	*/
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_NAND_ADDR		0xd0000000      /* NAND Flash		*/
+#define CFG_OCM_BASE		0xe0010000      /* ocm			*/
+#define CFG_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
+#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
+#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
+
+#define CFG_USB2D0_BASE		0xe0000100
+#define CFG_USB_DEVICE		0xe0000000
+#define CFG_USB_HOST		0xe0000400
+#define CFG_BCSR_BASE		0xc0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+#if 0
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
+#define CFG_INIT_RAM_ADDR	0x70000000	/* DCache		*/
+#else
+#define CFG_INIT_RAM_OCM	1		/* OCM as init ram	*/
+#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
+#endif
+
+#define CFG_INIT_RAM_END	(4 << 10)
+#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI     1
+/* define this if you want console on UART1 */
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE						\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1 /* test-only */
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CFG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
+#endif
+#if 0
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CFG_NAND_BASE		CFG_NAND_ADDR
+
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 4k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ * On 440EPx the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from cache, I experienced problems accessing
+ * the NAND controller.	sr - 2006-08-25
+ */
+#define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
+#define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
+#define CFG_NAND_BOOT_SPL_DST	(CFG_OCM_BASE + (12 << 10)) /* Copy SPL here	*/
+#define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
+#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST /* Start NUB from this addr	*/
+#define CFG_NAND_BOOT_SPL_DELTA	(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CFG_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
+#define CFG_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
+
+/*
+ * Now the NAND chip has to be defined (no autodetection used!)
+ */
+#define CFG_NAND_PAGE_SIZE	(512)		/* NAND chip page size		*/
+#define CFG_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
+#define CFG_NAND_PAGE_COUNT	(32)		/* NAND chip page count		*/
+#define CFG_NAND_BAD_BLOCK_POS	(5)		/* Location of bad block marker	*/
+#undef CFG_NAND_4_ADDR_CYCLE			/* No fourth addr used (<=32MB)	*/
+
+#ifdef CFG_ENV_IS_IN_NAND
+#define CFG_ENV_SIZE		0x4000
+#define CFG_ENV_OFFSET		(CFG_NAND_U_BOOT_OFFS + CFG_NAND_U_BOOT_SIZE)
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET + CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM        (256)    /* 256MB			*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE		0x200		/* Size of Environment vars	*/
+#define CFG_ENV_OFFSET		0x0
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_AD7414	1		/* use AD7414		*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define CFG_DTT_HYSTERESIS	3
+
+#define CONFIG_PREBOOT	"echo;"						\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=sequoia\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/sequoia/uImage\0"				\
+	"kernel_addr=FE000000\0"					\
+	"ramdisk_addr=FE180000\0"					\
+	"load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0"		\
+	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
+		"cp.b 100000 FFFA0000 60000\0"			        \
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_M88E1111_PHY	1
+#define	CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
+
+#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY1_ADDR	1
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define CONFIG_COMMANDS       (CONFIG_CMD_DFL	|	\
+			       CFG_CMD_ASKENV	|	\
+			       CFG_CMD_DHCP	|	\
+			       CFG_CMD_DTT	|	\
+			       CFG_CMD_DIAG	|	\
+			       CFG_CMD_EEPROM	|	\
+			       CFG_CMD_ELF	|	\
+			       CFG_CMD_FAT	|	\
+			       CFG_CMD_I2C	|	\
+			       CFG_CMD_IRQ	|	\
+			       CFG_CMD_MII	|	\
+			       CFG_CMD_NAND	|	\
+			       CFG_CMD_NET	|	\
+			       CFG_CMD_NFS	|	\
+			       CFG_CMD_PCI	|	\
+			       CFG_CMD_PING	|	\
+			       CFG_CMD_REGINFO	|	\
+			       CFG_CMD_SDRAM	|	\
+			       CFG_CMD_USB    )
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
+#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
+#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH		CFG_FLASH_BASE
+#define CFG_NAND		0xD0000000
+#define CFG_CPLD		0xC0000000
+
+/*
+ * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
+ */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_NAND_CS		3		/* NAND chip connected to CSx	*/
+/* Memory Bank 0 (NOR-FLASH) initialization					*/
+#define CFG_EBC_PB0AP		0x03017300
+#define CFG_EBC_PB0CR		(CFG_FLASH | 0xba000)
+
+/* Memory Bank 3 (NAND-FLASH) initialization					*/
+#define CFG_EBC_PB3AP		0x018003c0
+#define CFG_EBC_PB3CR		(CFG_NAND | 0x1c000)
+#else
+#define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
+/* Memory Bank 3 (NOR-FLASH) initialization					*/
+#define CFG_EBC_PB3AP		0x03017300
+#define CFG_EBC_PB3CR		(CFG_FLASH | 0xba000)
+
+/* Memory Bank 0 (NAND-FLASH) initialization					*/
+#define CFG_EBC_PB0AP		0x018003c0
+#define CFG_EBC_PB0CR		(CFG_NAND | 0x1c000)
+#endif
+
+/* Memory Bank 2 (CPLD) initialization						*/
+#define CFG_EBC_PB2AP		0x24814580
+#define CFG_EBC_PB2CR		(CFG_CPLD | 0x38000)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE		(32<<10)  /* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	      /* ...			            */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	      /* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h
index cf42b666b00..bcafd8ba8b3 100644
--- a/include/configs/yellowstone.h
+++ b/include/configs/yellowstone.h
@@ -65,6 +65,7 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
 #define CFG_INIT_RAM_END	(8 << 10)
 #define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 86a85b8a6d3..3d7b4a2f4bc 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -65,6 +65,7 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
 #define CFG_INIT_RAM_END	(8 << 10)
 #define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
diff --git a/include/linux/mtd/compat.h b/include/linux/mtd/compat.h
index 460cd45c808..fe55087ea93 100644
--- a/include/linux/mtd/compat.h
+++ b/include/linux/mtd/compat.h
@@ -31,11 +31,13 @@
 #define max_t(type,x,y) \
 	({ type __x = (x); type __y = (y); __x > __y ? __x: __y; })
 
+#ifndef BUG
 #define BUG() do { \
 	printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \
 } while (0)
 
 #define BUG_ON(condition) do { if (condition) BUG(); } while(0)
+#endif /* BUG */
 
 #define likely(x)	__builtin_expect(!!(x), 1)
 #define unlikely(x)	__builtin_expect(!!(x), 0)
diff --git a/include/linux/mtd/ndfc.h b/include/linux/mtd/ndfc.h
new file mode 100644
index 00000000000..d0558a98262
--- /dev/null
+++ b/include/linux/mtd/ndfc.h
@@ -0,0 +1,67 @@
+/*
+ *  linux/include/linux/mtd/ndfc.h
+ *
+ *  Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Info:
+ *   Contains defines, datastructures for ndfc nand controller
+ *
+ */
+#ifndef __LINUX_MTD_NDFC_H
+#define __LINUX_MTD_NDFC_H
+
+/* NDFC Register definitions */
+#define NDFC_CMD		0x00
+#define NDFC_ALE		0x04
+#define NDFC_DATA		0x08
+#define NDFC_ECC		0x10
+#define NDFC_BCFG0		0x30
+#define NDFC_BCFG1		0x34
+#define NDFC_BCFG2		0x38
+#define NDFC_BCFG3		0x3c
+#define NDFC_CCR		0x40
+#define NDFC_STAT		0x44
+#define NDFC_HWCTL		0x48
+#define NDFC_REVID		0x50
+
+#define NDFC_STAT_IS_READY	0x01000000
+
+#define NDFC_CCR_RESET_CE	0x80000000 /* CE Reset */
+#define NDFC_CCR_RESET_ECC	0x40000000 /* ECC Reset */
+#define NDFC_CCR_RIE		0x20000000 /* Interrupt Enable on Device Rdy */
+#define NDFC_CCR_REN		0x10000000 /* Enable wait for Rdy in LinearR */
+#define NDFC_CCR_ROMEN		0x08000000 /* Enable ROM In LinearR */
+#define NDFC_CCR_ARE		0x04000000 /* Auto-Read Enable */
+#define NDFC_CCR_BS(x)		(((x) & 0x3) << 24) /* Select Bank on CE[x] */
+#define NDFC_CCR_BS_MASK	0x03000000 /* Select Bank */
+#define NDFC_CCR_ARAC0		0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
+#define NDFC_CCR_ARAC1		0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
+#define NDFC_CCR_ARAC2		0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
+#define NDFC_CCR_ARAC3		0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
+#define NDFC_CCR_ARAC_MASK	0x00003000 /* Auto-Read mode Addr Cycles */
+#define NDFC_CCR_RPG		0x0000C000 /* Auto-Read Page */
+#define NDFC_CCR_EBCC		0x00000004 /* EBC Configuration Completed */
+#define NDFC_CCR_DHC		0x00000002 /* Direct Hardware Control Enable */
+
+#define NDFC_BxCFG_EN		0x80000000 /* Bank Enable */
+#define NDFC_BxCFG_CED		0x40000000 /* nCE Style */
+#define NDFC_BxCFG_SZ_MASK	0x08000000 /* Bank Size */
+#define NDFC_BxCFG_SZ_8BIT	0x00000000 /* 8bit */
+#define NDFC_BxCFG_SZ_16BIT	0x08000000 /* 16bit */
+
+#define NDFC_MAX_BANKS		4
+
+struct ndfc_controller_settings {
+	uint32_t	ccr_settings;
+	uint64_t	ndfc_erpn;
+};
+
+struct ndfc_chip_settings {
+	uint32_t	bank_settings;
+};
+
+#endif
diff --git a/include/ppc440.h b/include/ppc440.h
index d5a9f66a419..c4a3ed54835 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -82,7 +82,10 @@
 #define	 ivor13 0x19d	/* interrupt vector offset register 13 */
 #define	 ivor14 0x19e	/* interrupt vector offset register 14 */
 #define	 ivor15 0x19f	/* interrupt vector offset register 15 */
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #define	 mcsrr0 0x23a	/* machine check save/restore register 0 */
 #define	 mcsrr1 0x23b	/* mahcine check save/restore register 1 */
 #define	 mcsr	0x23c	/* machine check status register */
@@ -151,7 +154,18 @@
 #define sdr_ecid1	0x0081
 #define sdr_ecid2	0x0082
 #define sdr_jtag	0x00c0
+#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
 #define sdr_ddrdl	0x00e0
+#else
+#define sdr_cfg		0x00e0
+#define SDR_CFG_LT2_MASK          0x01000000 /* Leakage test 2*/
+#define SDR_CFG_64_32BITS_MASK    0x01000000 /* Switch DDR 64 bits or 32 bits */
+#define SDR_CFG_32BITS            0x00000000  /* 32 bits */
+#define SDR_CFG_64BITS            0x01000000  /* 64 bits */
+#define SDR_CFG_MC_V2518_MASK     0x02000000 /* Low VDD2518 (2.5 or 1.8V) */
+#define SDR_CFG_MC_V25            0x00000000  /* 2.5 V */
+#define SDR_CFG_MC_V18            0x02000000  /* 1.8 V */
+#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
 #define sdr_ebc		0x0100
 #define sdr_uart0	0x0120	/* UART0 Config */
 #define sdr_uart1	0x0121	/* UART1 Config */
@@ -180,6 +194,54 @@
 #define sdr_plbtr	0x4200
 #define sdr_mfr		0x4300	/* SDR0_MFR reg */
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* test-only!!!! */
+#define DDR0_00	0x00
+#define DDR0_01	0x01
+#define DDR0_02	0x02
+#define DDR0_03	0x03
+#define DDR0_04	0x04
+#define DDR0_05	0x05
+#define DDR0_06	0x06
+#define DDR0_07	0x07
+#define DDR0_08	0x08
+#define DDR0_09	0x09
+#define DDR0_10	0x0A
+#define DDR0_11	0x0B
+#define DDR0_12	0x0C
+#define DDR0_13	0x0D
+#define DDR0_14	0x0E
+#define DDR0_15	0x0F
+#define DDR0_16	0x10
+#define DDR0_17	0x11
+#define DDR0_18	0x12
+#define DDR0_19	0x13
+#define DDR0_20	0x14
+#define DDR0_21	0x15
+#define DDR0_22	0x16
+#define DDR0_23	0x17
+#define DDR0_24	0x18
+#define DDR0_25	0x19
+#define DDR0_26	0x1A
+#define DDR0_27	0x1B
+#define DDR0_28	0x1C
+#define DDR0_29	0x1D
+#define DDR0_30	0x1E
+#define DDR0_31	0x1F
+#define DDR0_32	0x20
+#define DDR0_33	0x21
+#define DDR0_34	0x22
+#define DDR0_35	0x23
+#define DDR0_36	0x24
+#define DDR0_37	0x25
+#define DDR0_38	0x26
+#define DDR0_39	0x27
+#define DDR0_40	0x28
+#define DDR0_41	0x29
+#define DDR0_42	0x2A
+#define DDR0_43	0x2B
+#define DDR0_44	0x2C
+#endif /*CONFIG_440EPX*/
+
 /*-----------------------------------------------------------------------------
  | SDRAM Controller
  +----------------------------------------------------------------------------*/
@@ -787,7 +849,8 @@
 #define xbcfg		0x23	/* external bus configuration reg	*/
 #define xbcid		0x24	/* external bus core id reg		*/
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 /* PLB4 to PLB3 Bridge OUT */
 #define P4P3_DCR_BASE           0x020
@@ -877,6 +940,7 @@
 #define plb1_bearl                (PLB_ARBITER_BASE+ 0x0C)
 #define plb1_bearh                (PLB_ARBITER_BASE+ 0x0D)
 
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 /* Pin Function Control Register 1 */
 #define SDR0_PFC1                    0x4101
 #define   SDR0_PFC1_U1ME_MASK         0x02000000    /* UART1 Mode Enable */
@@ -918,6 +982,178 @@
 #define   SDR0_USB0_LEEN_DISABLE      0x00000000      /* Little Endian Disable */
 #define   SDR0_USB0_LEEN_ENABLE       0x00000001      /* Little Endian Enable */
 
+/* Miscealleneaous Function Reg. */
+#define SDR0_MFR                     0x4300
+#define   SDR0_MFR_ETH0_CLK_SEL_MASK   0x08000000   /* Ethernet0 Clock Select */
+#define   SDR0_MFR_ETH0_CLK_SEL_EXT    0x00000000
+#define   SDR0_MFR_ETH1_CLK_SEL_MASK   0x04000000   /* Ethernet1 Clock Select */
+#define   SDR0_MFR_ETH1_CLK_SEL_EXT    0x00000000
+#define   SDR0_MFR_ZMII_MODE_MASK      0x03000000   /* ZMII Mode Mask */
+#define   SDR0_MFR_ZMII_MODE_MII       0x00000000     /* ZMII Mode MII */
+#define   SDR0_MFR_ZMII_MODE_SMII      0x01000000     /* ZMII Mode SMII */
+#define   SDR0_MFR_ZMII_MODE_RMII_10M  0x02000000     /* ZMII Mode RMII - 10 Mbs */
+#define   SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000     /* ZMII Mode RMII - 100 Mbs */
+#define   SDR0_MFR_ZMII_MODE_BIT0      0x02000000     /* ZMII Mode Bit0 */
+#define   SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
+#define   SDR0_MFR_ZM_ENCODE(n)        ((((unsigned long)(n))&0x3)<<24)
+#define   SDR0_MFR_ZM_DECODE(n)        ((((unsigned long)(n))<<24)&0x3)
+
+#define   SDR0_MFR_ERRATA3_EN0         0x00800000
+#define   SDR0_MFR_ERRATA3_EN1         0x00400000
+#define   SDR0_MFR_PKT_REJ_MASK        0x00180000   /* Pkt Rej. Enable Mask */
+#define   SDR0_MFR_PKT_REJ_EN          0x00180000   /* Pkt Rej. Enable on both EMAC3 0-1 */
+#define   SDR0_MFR_PKT_REJ_EN0         0x00100000   /* Pkt Rej. Enable on EMAC3(0) */
+#define   SDR0_MFR_PKT_REJ_EN1         0x00080000   /* Pkt Rej. Enable on EMAC3(1) */
+#define   SDR0_MFR_PKT_REJ_POL         0x00200000   /* Packet Reject Polarity */
+
+#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR_USB2D0CR                 0x0320
+#define   SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK   0x00000004    /* USB 2.0 Device/EBC Master Selection */
+#define   SDR0_USB2D0CR_USB2DEV_SELECTION      0x00000004    /* USB 2.0 Device Selection */
+#define   SDR0_USB2D0CR_EBC_SELECTION          0x00000000    /* EBC Selection */
+
+#define   SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK   0x00000002    /* USB Device Interface Selection */
+#define   SDR0_USB2D0CR_USB20D_DEVSEL          0x00000000      /* USB2.0 Device Selected */
+#define   SDR0_USB2D0CR_USB11D_DEVSEL          0x00000002      /* USB1.1 Device Selected */
+
+#define   SDR0_USB2D0CR_LEEN_MASK              0x00000001    /* Little Endian selection */
+#define   SDR0_USB2D0CR_LEEN_DISABLE           0x00000000      /* Little Endian Disable */
+#define   SDR0_USB2D0CR_LEEN_ENABLE            0x00000001      /* Little Endian Enable */
+
+/* USB2 Host Control Register */
+#define SDR0_USB2H0CR                0x0340
+#define   SDR0_USB2H0CR_WDINT_MASK             0x00000001 /* Host UTMI Word Interface */
+#define   SDR0_USB2H0CR_WDINT_8BIT_60MHZ       0x00000000  /* 8-bit/60MHz */
+#define   SDR0_USB2H0CR_WDINT_16BIT_30MHZ      0x00000001  /* 16-bit/30MHz */
+#define   SDR0_USB2H0CR_EFLADJ_MASK            0x0000007e /* EHCI Frame Length Adjustment */
+
+/* Pin Function Control Register 1 */
+#define SDR0_PFC1                    0x4101
+#define   SDR0_PFC1_U1ME_MASK                  0x02000000    /* UART1 Mode Enable */
+#define   SDR0_PFC1_U1ME_DSR_DTR               0x00000000      /* UART1 in DSR/DTR Mode */
+#define   SDR0_PFC1_U1ME_CTS_RTS               0x02000000      /* UART1 in CTS/RTS Mode */
+
+#define   SDR0_PFC1_SELECT_MASK                0x01C00000 /* Ethernet Pin Select EMAC 0 */
+#define   SDR0_PFC1_SELECT_CONFIG_1_1          0x00C00000   /* 1xMII   using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_1_2          0x00000000   /* 1xMII   using  ZMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_2            0x00C00000   /* 1xGMII  using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_3            0x01000000   /* 1xTBI   using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_4            0x01400000   /* 2xRGMII using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_5            0x01800000   /* 2xRTBI  using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_6            0x00800000   /* 2xSMII  using  ZMII bridge */
+
+#define   SDR0_PFC1_U0ME_MASK                  0x00080000    /* UART0 Mode Enable */
+#define   SDR0_PFC1_U0ME_DSR_DTR               0x00000000      /* UART0 in DSR/DTR Mode */
+#define   SDR0_PFC1_U0ME_CTS_RTS               0x00080000      /* UART0 in CTS/RTS Mode */
+#define   SDR0_PFC1_U0IM_MASK                  0x00040000    /* UART0 Interface Mode */
+#define   SDR0_PFC1_U0IM_8PINS                 0x00000000      /* UART0 Interface Mode 8 pins */
+#define   SDR0_PFC1_U0IM_4PINS                 0x00040000      /* UART0 Interface Mode 4 pins */
+#define   SDR0_PFC1_SIS_MASK                   0x00020000    /* SCP or IIC1 Selection */
+#define   SDR0_PFC1_SIS_SCP_SEL                0x00000000      /* SCP Selected */
+#define   SDR0_PFC1_SIS_IIC1_SEL               0x00020000      /* IIC1 Selected */
+#define   SDR0_PFC1_UES_MASK                   0x00010000    /* USB2D_RX_Active / EBC_Hold Req Selection */
+#define   SDR0_PFC1_UES_USB2D_SEL              0x00000000      /* USB2D_RX_Active Selected */
+#define   SDR0_PFC1_UES_EBCHR_SEL              0x00010000      /* EBC_Hold Req Selected */
+#define   SDR0_PFC1_DIS_MASK                   0x00008000    /* DMA_Req(1) / UIC_IRQ(5) Selection */
+#define   SDR0_PFC1_DIS_DMAR_SEL               0x00000000      /* DMA_Req(1) Selected */
+#define   SDR0_PFC1_DIS_UICIRQ5_SEL            0x00008000      /* UIC_IRQ(5) Selected */
+#define   SDR0_PFC1_ERE_MASK                   0x00004000    /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
+#define   SDR0_PFC1_ERE_EXTR_SEL               0x00000000      /* EBC Mast.Ext.Req.En. Selected */
+#define   SDR0_PFC1_ERE_GPIO0_27_SEL           0x00004000      /* GPIO0(27) Selected */
+#define   SDR0_PFC1_UPR_MASK                   0x00002000    /* USB2 Device Packet Reject Selection */
+#define   SDR0_PFC1_UPR_DISABLE                0x00000000      /* USB2 Device Packet Reject Disable */
+#define   SDR0_PFC1_UPR_ENABLE                 0x00002000      /* USB2 Device Packet Reject Enable */
+
+#define   SDR0_PFC1_PLB_PME_MASK               0x00001000    /* PLB3/PLB4 Perf. Monitor En. Selection */
+#define   SDR0_PFC1_PLB_PME_PLB3_SEL           0x00000000      /* PLB3 Performance Monitor Enable */
+#define   SDR0_PFC1_PLB_PME_PLB4_SEL           0x00001000      /* PLB3 Performance Monitor Enable */
+#define   SDR0_PFC1_GFGGI_MASK                 0x0000000F    /* GPT Frequency Generation Gated In */
+
+/* Ethernet PLL Configuration Register */
+#define SDR0_PFC2                    0x4102
+#define   SDR0_PFC2_TUNE_MASK                  0x01FF8000  /* Loop stability tuning bits */
+#define   SDR0_PFC2_MULTI_MASK                 0x00007C00  /* Frequency multiplication selector */
+#define   SDR0_PFC2_RANGEB_MASK                0x00000380  /* PLLOUTB/C frequency selector */
+#define   SDR0_PFC2_RANGEA_MASK                0x00000071  /* PLLOUTA frequency selector */
+
+#define   SDR0_PFC2_SELECT_MASK                0xE0000000  /* Ethernet Pin select EMAC1 */
+#define   SDR0_PFC2_SELECT_CONFIG_1_1          0x60000000   /* 1xMII   using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_1_2          0x00000000   /* 1xMII   using  ZMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_2            0x60000000   /* 1xGMII  using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_3            0x80000000   /* 1xTBI   using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_4            0xA0000000   /* 2xRGMII using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_5            0xC0000000   /* 2xRTBI  using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_6            0x40000000   /* 2xSMII  using  ZMII bridge */
+
+/* USB2PHY0 Control Register */
+#define SDR0_USB2PHY0CR               0x4103
+#define   SDR0_USB2PHY0CR_UTMICN_MASK          0x00100000 /*  PHY UTMI interface connection */
+#define   SDR0_USB2PHY0CR_UTMICN_DEV           0x00000000  /* Device support */
+#define   SDR0_USB2PHY0CR_UTMICN_HOST          0x00100000  /* Host support */
+
+#define   SDR0_USB2PHY0CR_DWNSTR_MASK          0x00400000 /* Select downstream port mode */
+#define   SDR0_USB2PHY0CR_DWNSTR_DEV           0x00000000  /* Device */
+#define   SDR0_USB2PHY0CR_DWNSTR_HOST          0x00400000  /* Host   */
+
+#define   SDR0_USB2PHY0CR_DVBUS_MASK           0x00800000 /* VBus detect (Device mode only)  */
+#define   SDR0_USB2PHY0CR_DVBUS_PURDIS         0x00000000  /* Pull-up resistance on D+ is disabled */
+#define   SDR0_USB2PHY0CR_DVBUS_PUREN          0x00800000  /* Pull-up resistance on D+ is enabled */
+
+#define   SDR0_USB2PHY0CR_WDINT_MASK           0x01000000 /* PHY UTMI data width and clock select  */
+#define   SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ     0x00000000  /* 8-bit data/60MHz */
+#define   SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ    0x01000000  /* 16-bit data/30MHz */
+
+#define   SDR0_USB2PHY0CR_LOOPEN_MASK          0x02000000 /* Loop back test enable  */
+#define   SDR0_USB2PHY0CR_LOOP_ENABLE          0x00000000  /* Loop back disabled */
+#define   SDR0_USB2PHY0CR_LOOP_DISABLE         0x02000000  /* Loop back enabled (only test purposes) */
+
+#define   SDR0_USB2PHY0CR_XOON_MASK            0x04000000 /* Force XO block on during a suspend  */
+#define   SDR0_USB2PHY0CR_XO_ON                0x00000000  /* PHY XO block is powered-on */
+#define   SDR0_USB2PHY0CR_XO_OFF               0x04000000  /* PHY XO block is powered-off when all ports are suspended */
+
+#define   SDR0_USB2PHY0CR_PWRSAV_MASK          0x08000000 /* Select PHY power-save mode  */
+#define   SDR0_USB2PHY0CR_PWRSAV_OFF           0x00000000  /* Non-power-save mode */
+#define   SDR0_USB2PHY0CR_PWRSAV_ON            0x08000000  /* Power-save mode. Valid only for full-speed operation */
+
+#define   SDR0_USB2PHY0CR_XOREF_MASK           0x10000000 /* Select reference clock source  */
+#define   SDR0_USB2PHY0CR_XOREF_INTERNAL       0x00000000  /* PHY PLL uses chip internal 48M clock as a reference */
+#define   SDR0_USB2PHY0CR_XOREF_XO             0x10000000  /* PHY PLL uses internal XO block output as a reference */
+
+#define   SDR0_USB2PHY0CR_XOCLK_MASK           0x20000000 /* Select clock for XO block  */
+#define   SDR0_USB2PHY0CR_XOCLK_EXTERNAL       0x00000000  /* PHY macro used an external clock */
+#define   SDR0_USB2PHY0CR_XOCLK_CRYSTAL        0x20000000  /* PHY macro uses the clock from a crystal */
+
+#define   SDR0_USB2PHY0CR_CLKSEL_MASK          0xc0000000 /* Select ref clk freq */
+#define   SDR0_USB2PHY0CR_CLKSEL_12MHZ         0x00000000 /* Select ref clk freq = 12 MHz*/
+#define   SDR0_USB2PHY0CR_CLKSEL_48MHZ         0x40000000 /* Select ref clk freq = 48 MHz*/
+#define   SDR0_USB2PHY0CR_CLKSEL_24MHZ         0x80000000 /* Select ref clk freq = 24 MHz*/
+
+/* Miscealleneaous Function Reg. */
+#define SDR0_MFR                     0x4300
+#define   SDR0_MFR_ETH0_CLK_SEL_MASK   0x08000000   /* Ethernet0 Clock Select */
+#define   SDR0_MFR_ETH0_CLK_SEL_EXT    0x00000000
+#define   SDR0_MFR_ETH1_CLK_SEL_MASK   0x04000000   /* Ethernet1 Clock Select */
+#define   SDR0_MFR_ETH1_CLK_SEL_EXT    0x00000000
+#define   SDR0_MFR_ZMII_MODE_MASK      0x03000000   /* ZMII Mode Mask */
+#define   SDR0_MFR_ZMII_MODE_MII       0x00000000     /* ZMII Mode MII */
+#define   SDR0_MFR_ZMII_MODE_SMII      0x01000000     /* ZMII Mode SMII */
+#define   SDR0_MFR_ZMII_MODE_BIT0      0x02000000     /* ZMII Mode Bit0 */
+#define   SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
+#define   SDR0_MFR_ZM_ENCODE(n)        ((((unsigned long)(n))&0x3)<<24)
+#define   SDR0_MFR_ZM_DECODE(n)        ((((unsigned long)(n))<<24)&0x3)
+
+#define   SDR0_MFR_ERRATA3_EN0         0x00800000
+#define   SDR0_MFR_ERRATA3_EN1         0x00400000
+#define   SDR0_MFR_PKT_REJ_MASK        0x00180000   /* Pkt Rej. Enable Mask */
+#define   SDR0_MFR_PKT_REJ_EN          0x00180000   /* Pkt Rej. Enable on both EMAC3 0-1 */
+#define   SDR0_MFR_PKT_REJ_EN0         0x00100000   /* Pkt Rej. Enable on EMAC3(0) */
+#define   SDR0_MFR_PKT_REJ_EN1         0x00080000   /* Pkt Rej. Enable on EMAC3(1) */
+#define   SDR0_MFR_PKT_REJ_POL         0x00200000   /* Packet Reject Polarity */
+
+#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
+
 /* CUST0 Customer Configuration Register0 */
 #define SDR0_CUST0                   0x4000
 #define   SDR0_CUST0_MUX_E_N_G_MASK   0xC0000000     /* Mux_Emac_NDFC_GPIO */
@@ -1007,27 +1243,18 @@
 #define   SDR0_PFC1_PLB_PME_PLB4_SEL  0x00001000      /* PLB3 Performance Monitor Enable */
 #define   SDR0_PFC1_GFGGI_MASK        0x0000000F    /* GPT Frequency Generation Gated In */
 
-/* Miscealleneaous Function Reg. */
-#define SDR0_MFR                     0x4300
-#define   SDR0_MFR_ETH0_CLK_SEL        0x08000000   /* Ethernet0 Clock Select */
-#define   SDR0_MFR_ETH1_CLK_SEL        0x04000000   /* Ethernet1 Clock Select */
-#define   SDR0_MFR_ZMII_MODE_MASK      0x03000000   /* ZMII Mode Mask */
-#define   SDR0_MFR_ZMII_MODE_MII       0x00000000     /* ZMII Mode MII */
-#define   SDR0_MFR_ZMII_MODE_SMII      0x01000000     /* ZMII Mode SMII */
-#define   SDR0_MFR_ZMII_MODE_RMII_10M  0x02000000     /* ZMII Mode RMII - 10 Mbs */
-#define   SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000     /* ZMII Mode RMII - 100 Mbs */
-#define   SDR0_MFR_ZMII_MODE_BIT0      0x02000000     /* ZMII Mode Bit0 */
-#define   SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
-#define   SDR0_MFR_ZM_ENCODE(n)        ((((unsigned long)(n))&0x3)<<24)
-#define   SDR0_MFR_ZM_DECODE(n)        ((((unsigned long)(n))<<24)&0x3)
-
-#define   SDR0_MFR_ERRATA3_EN0         0x00800000
-#define   SDR0_MFR_ERRATA3_EN1         0x00400000
-#define   SDR0_MFR_PKT_REJ_MASK        0x00300000   /* Pkt Rej. Enable Mask */
-#define   SDR0_MFR_PKT_REJ_EN          0x00300000   /* Pkt Rej. Enable on both EMAC3 0-1 */
-#define   SDR0_MFR_PKT_REJ_EN0         0x00200000   /* Pkt Rej. Enable on EMAC3(0) */
-#define   SDR0_MFR_PKT_REJ_EN1         0x00100000   /* Pkt Rej. Enable on EMAC3(1) */
-#define   SDR0_MFR_PKT_REJ_POL         0x00080000   /* Packet Reject Polarity */
+/*-----------------------------------------------------------------------------
+ | Internal SRAM
+ +----------------------------------------------------------------------------*/
+#define ISRAM0_DCR_BASE 0x380
+#define isram0_sb0cr	(ISRAM0_DCR_BASE+0x00)	/* SRAM bank config 0*/
+#define isram0_bear	(ISRAM0_DCR_BASE+0x04)	/* SRAM bus error addr reg */
+#define isram0_besr0	(ISRAM0_DCR_BASE+0x05)	/* SRAM bus error status reg 0 */
+#define isram0_besr1	(ISRAM0_DCR_BASE+0x06)	/* SRAM bus error status reg 1 */
+#define isram0_pmeg	(ISRAM0_DCR_BASE+0x07)	/* SRAM power management */
+#define isram0_cid	(ISRAM0_DCR_BASE+0x08)	/* SRAM bus core id reg */
+#define isram0_revid	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
+#define isram0_dpc	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
 
 #else
 
@@ -1121,7 +1348,7 @@
 #define uic1vr	(UIC1_DCR_BASE+0x7)   /* UIC1 vector			   */
 #define uic1vcr (UIC1_DCR_BASE+0x8)   /* UIC1 vector configuration	   */
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define UIC2_DCR_BASE 0xe0
 #define uic2sr	(UIC0_DCR_BASE+0x0)   /* UIC2 status-Read Clear		*/
 #define uic2srs	(UIC0_DCR_BASE+0x1)   /* UIC2 status-Read Set */
@@ -1423,6 +1650,46 @@
 #define UIC_EIR6	0x00000004	/* External interrupt 6		    */
 #define UIC_UIC1NC	0x00000002	/* UIC1 non-critical interrupt	    */
 #define UIC_UIC1C	0x00000001	/* UIC1 critical interrupt	    */
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+#define UIC_U0        0x80000000  /* UART 0                             */
+#define UIC_U1        0x40000000  /* UART 1                             */
+#define UIC_IIC0      0x20000000  /* IIC                                */
+#define UIC_KRD       0x10000000  /* Kasumi Ready for data              */
+#define UIC_KDA       0x08000000  /* Kasumi Data Available              */
+#define UIC_PCRW      0x04000000  /* PCI command register write         */
+#define UIC_PPM       0x02000000  /* PCI power management               */
+#define UIC_IIC1      0x01000000  /* IIC                                */
+#define UIC_SPI       0x00800000  /* SPI                                */
+#define UIC_EPCISER   0x00400000  /* External PCI SERR                  */
+#define UIC_MTE       0x00200000  /* MAL TXEOB                          */
+#define UIC_MRE       0x00100000  /* MAL RXEOB                          */
+#define UIC_D0        0x00080000  /* DMA channel 0                      */
+#define UIC_D1        0x00040000  /* DMA channel 1                      */
+#define UIC_D2        0x00020000  /* DMA channel 2                      */
+#define UIC_D3        0x00010000  /* DMA channel 3                      */
+#define UIC_UD0       0x00008000  /* UDMA irq 0                         */
+#define UIC_UD1       0x00004000  /* UDMA irq 1                         */
+#define UIC_UD2       0x00002000  /* UDMA irq 2                         */
+#define UIC_UD3       0x00001000  /* UDMA irq 3                         */
+#define UIC_HSB2D     0x00000800  /* USB2.0 Device                      */
+#define UIC_OHCI1     0x00000400  /* USB2.0 Host OHCI irq 1             */
+#define UIC_OHCI2     0x00000200  /* USB2.0 Host OHCI irq 2             */
+#define UIC_EIP94     0x00000100  /* Security EIP94                     */
+#define UIC_ETH0      0x00000080  /* Emac 0                             */
+#define UIC_ETH1      0x00000040  /* Emac 1                             */
+#define UIC_EHCI      0x00000020  /* USB2.0 Host EHCI                   */
+#define UIC_EIR4      0x00000010  /* External interrupt 4               */
+#define UIC_UIC2NC    0x00000008  /* UIC2 non-critical interrupt        */
+#define UIC_UIC2C     0x00000004  /* UIC2 critical interrupt            */
+#define UIC_UIC1NC    0x00000002  /* UIC1 non-critical interrupt        */
+#define UIC_UIC1C     0x00000001  /* UIC1 critical interrupt            */
+
+/* For compatibility with 405 code */
+#define UIC_MAL_TXEOB	UIC_MTE
+#define UIC_MAL_RXEOB	UIC_MRE
+
 #elif !defined(CONFIG_440SPE)
 #define UIC_U0		0x80000000	/* UART 0			    */
 #define UIC_U1		0x40000000	/* UART 1			    */
@@ -1531,6 +1798,48 @@
 #define UIC_EWU0	0x00000004	/* Ethernet 0 wakeup		    */
 #define UIC_ETH1	0x00000002	/* Ethernet 1			    */
 #define UIC_EWU1	0x00000001	/* Ethernet 1 wakeup		    */
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+#define UIC_MS        0x80000000  /* MAL SERR                           */
+#define UIC_MTDE      0x40000000  /* MAL TXDE                           */
+#define UIC_MRDE      0x20000000  /* MAL RXDE                           */
+#define UIC_U2        0x10000000  /* UART 2                             */
+#define UIC_U3        0x08000000  /* UART 3                             */
+#define UIC_EBCO      0x04000000  /* EBCO interrupt status              */
+#define UIC_NDFC      0x02000000  /* NDFC                               */
+#define UIC_KSLE      0x01000000  /* KASUMI slave error                 */
+#define UIC_CT5       0x00800000  /* GPT compare timer 5                */
+#define UIC_CT6       0x00400000  /* GPT compare timer 6                */
+#define UIC_PLB34I0   0x00200000  /* PLB3X4X MIRQ0                      */
+#define UIC_PLB34I1   0x00100000  /* PLB3X4X MIRQ1                      */
+#define UIC_PLB34I2   0x00080000  /* PLB3X4X MIRQ2                      */
+#define UIC_PLB34I3   0x00040000  /* PLB3X4X MIRQ3                      */
+#define UIC_PLB34I4   0x00020000  /* PLB3X4X MIRQ4                      */
+#define UIC_PLB34I5   0x00010000  /* PLB3X4X MIRQ5                      */
+#define UIC_CT0       0x00008000  /* GPT compare timer 0                */
+#define UIC_CT1       0x00004000  /* GPT compare timer 1                */
+#define UIC_EIR7      0x00002000  /* External interrupt 7               */
+#define UIC_EIR8      0x00001000  /* External interrupt 8               */
+#define UIC_EIR9      0x00000800  /* External interrupt 9               */
+#define UIC_CT2       0x00000400  /* GPT compare timer 2                */
+#define UIC_CT3       0x00000200  /* GPT compare timer 3                */
+#define UIC_CT4       0x00000100  /* GPT compare timer 4                */
+#define UIC_SRE       0x00000080  /* Serial ROM error                   */
+#define UIC_GPTDC     0x00000040  /* GPT decrementer pulse              */
+#define UIC_RSVD0     0x00000020  /* Reserved                           */
+#define UIC_EPCIPER   0x00000010  /* External PCI PERR                  */
+#define UIC_EIR0      0x00000008  /* External interrupt 0               */
+#define UIC_EWU0      0x00000004  /* Ethernet 0 wakeup                  */
+#define UIC_EIR1      0x00000002  /* External interrupt 1               */
+#define UIC_EWU1      0x00000001  /* Ethernet 1 wakeup                  */
+
+/* For compatibility with 405 code */
+#define UIC_MAL_SERR	UIC_MS
+#define UIC_MAL_TXDE	UIC_MTDE
+#define UIC_MAL_RXDE	UIC_MRDE
+#define UIC_ENET	UIC_ETH0
+
 #elif !defined(CONFIG_440SPE)
 #define UIC_MS		0x80000000	/* MAL SERR			    */
 #define UIC_MTDE	0x40000000	/* MAL TXDE			    */
@@ -1608,6 +1917,20 @@
 #define UIC_RSVD29	0x00000004	/* Reserved			    */
 #define UIC_RSVD30	0x00000002	/* Reserved			    */
 #define UIC_RSVD31	0x00000001	/* Reserved			    */
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */
+
+#define UIC_EIR5    0x80000000  /* External interrupt 5                 */
+#define UIC_EIR6    0x40000000  /* External interrupt 6                 */
+#define UIC_OPB     0x20000000  /* OPB to PLB bridge interrupt stat     */
+#define UIC_EIR2    0x10000000  /* External interrupt 2                 */
+#define UIC_EIR3    0x08000000  /* External interrupt 3                 */
+#define UIC_DDR2    0x04000000  /* DDR2 sdram                           */
+#define UIC_MCTX0   0x02000000  /* MAl intp coalescence TX0             */
+#define UIC_MCTX1   0x01000000  /* MAl intp coalescence TX1             */
+#define UIC_MCTR0   0x00800000  /* MAl intp coalescence TR0             */
+#define UIC_MCTR1   0x00400000  /* MAl intp coalescence TR1             */
+
 #endif	/* CONFIG_440GX */
 
 /*---------------------------------------------------------------------------+
@@ -1623,6 +1946,17 @@
 
 #define UICB0_ALL		(UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
 						 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+#define UICB0_UIC1CI	0x00000000	/* UIC1 Critical Interrupt	    */
+#define UICB0_UIC1NCI	0x00000000	/* UIC1 Noncritical Interrupt	    */
+#define UICB0_UIC2CI	0x00000000	/* UIC2 Critical Interrupt	    */
+#define UICB0_UIC2NCI	0x00000000	/* UIC2 Noncritical Interrupt	    */
+
+#define UICB0_ALL		(UICB0_UIC1CI | UICB0_UIC1NCI | \
+						 UICB0_UIC1CI | UICB0_UIC2NCI)
+
 #endif /* CONFIG_440GX */
 /*---------------------------------------------------------------------------+
 |  Universal interrupt controller interrupts
@@ -2262,7 +2596,8 @@
 #define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 13)
 #define SDR0_SDSTP1_PISE_MASK		(0x80000000 >> 15)
 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 21)
 #define SDR0_SDSTP1_PAME_MASK		(0x80000000 >> 27)
 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
@@ -2390,11 +2725,81 @@
 #define SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
 #define SDR0_MFR_ERRATA3_EN0         0x00800000
 #define SDR0_MFR_ERRATA3_EN1         0x00400000
+#if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
 #define SDR0_MFR_PKT_REJ_MASK        0x00300000   /* Pkt Rej. Enable Mask */
 #define SDR0_MFR_PKT_REJ_EN          0x00300000   /* Pkt Rej. Enable on both EMAC3 0-1 */
 #define SDR0_MFR_PKT_REJ_EN0         0x00200000   /* Pkt Rej. Enable on EMAC3(0) */
 #define SDR0_MFR_PKT_REJ_EN1         0x00100000   /* Pkt Rej. Enable on EMAC3(1) */
 #define SDR0_MFR_PKT_REJ_POL         0x00080000   /* Packet Reject Polarity      */
+#endif
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_PFC1_EPS_ENCODE(n)		((((unsigned long)(n))&0x07)<<22)
+#define SDR0_PFC1_EPS_DECODE(n)		((((unsigned long)(n))>>22)&0x07)
+#define SDR0_PFC2_EPS_ENCODE(n)		((((unsigned long)(n))&0x07)<<29)
+#define SDR0_PFC2_EPS_DECODE(n)		((((unsigned long)(n))>>29)&0x07)
+#endif
+
+#define SDR0_MFR_ECS_MASK		0x10000000
+#define SDR0_MFR_ECS_INTERNAL		0x10000000
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_SRST0        0x200
+#define SDR0_SRST0_BGO          0x80000000 /* PLB to OPB bridge */
+#define SDR0_SRST0_PLB4         0x40000000 /* PLB4 arbiter */
+#define SDR0_SRST0_EBC          0x20000000 /* External bus controller */
+#define SDR0_SRST0_OPB          0x10000000 /* OPB arbiter */
+#define SDR0_SRST0_UART0        0x08000000 /* Universal asynchronous receiver/transmitter 0 */
+#define SDR0_SRST0_UART1        0x04000000 /* Universal asynchronous receiver/transmitter 1 */
+#define SDR0_SRST0_IIC0         0x02000000 /* Inter integrated circuit 0 */
+#define SDR0_SRST0_USB2H        0x01000000 /* USB2.0 Host */
+#define SDR0_SRST0_GPIO         0x00800000 /* General purpose I/O */
+#define SDR0_SRST0_GPT          0x00400000 /* General purpose timer */
+#define SDR0_SRST0_DMC          0x00200000 /* DDR SDRAM memory controller */
+#define SDR0_SRST0_PCI          0x00100000 /* PCI */
+#define SDR0_SRST0_EMAC0        0x00080000 /* Ethernet media access controller 0 */
+#define SDR0_SRST0_EMAC1        0x00040000 /* Ethernet media access controller 1 */
+#define SDR0_SRST0_CPM0         0x00020000 /* Clock and power management */
+#define SDR0_SRST0_ZMII         0x00010000 /* ZMII bridge */
+#define SDR0_SRST0_UIC0         0x00008000 /* Universal interrupt controller 0 */
+#define SDR0_SRST0_UIC1         0x00004000 /* Universal interrupt controller 1 */
+#define SDR0_SRST0_IIC1         0x00002000 /* Inter integrated circuit 1 */
+#define SDR0_SRST0_SCP          0x00001000 /* Serial communications port */
+#define SDR0_SRST0_BGI          0x00000800 /* OPB to PLB bridge */
+#define SDR0_SRST0_DMA          0x00000400 /* Direct memory access controller */
+#define SDR0_SRST0_DMAC         0x00000200 /* DMA channel */
+#define SDR0_SRST0_MAL          0x00000100 /* Media access layer */
+#define SDR0_SRST0_USB2D        0x00000080 /* USB2.0 device */
+#define SDR0_SRST0_GPTR         0x00000040 /* General purpose timer */
+#define SDR0_SRST0_P4P3         0x00000010 /* PLB4 to PLB3 bridge */
+#define SDR0_SRST0_P3P4         0x00000008 /* PLB3 to PLB4 bridge */
+#define SDR0_SRST0_PLB3         0x00000004 /* PLB3 arbiter */
+#define SDR0_SRST0_UART2        0x00000002 /* Universal asynchronous receiver/transmitter 2 */
+#define SDR0_SRST0_UART3        0x00000001 /* Universal asynchronous receiver/transmitter 3 */
+
+#define SDR0_SRST1        0x201
+#define SDR0_SRST1_NDFC         0x80000000 /* Nand flash controller */
+#define SDR0_SRST1_OPBA1        0x40000000 /* OPB Arbiter attached to PLB4 */
+#define SDR0_SRST1_P4OPB0       0x20000000 /* PLB4 to OPB Bridge0 */
+#define SDR0_SRST1_PLB42OPB0    SDR0_SRST1_P4OPB0
+#define SDR0_SRST1_DMA4         0x10000000 /* DMA to PLB4 */
+#define SDR0_SRST1_DMA4CH       0x08000000 /* DMA Channel to PLB4 */
+#define SDR0_SRST1_OPBA2        0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
+#define SDR0_SRST1_OPB2PLB40    0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
+#define SDR0_SRST1_PLB42OPB1    0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
+#define SDR0_SRST1_CPM1         0x00800000 /* Clock and Power management 1 */
+#define SDR0_SRST1_UIC2         0x00400000 /* Universal Interrupt Controller 2 */
+#define SDR0_SRST1_CRYP0        0x00200000 /* Security Engine */
+#define SDR0_SRST1_USB20PHY     0x00100000 /* USB 2.0 Phy */
+#define SDR0_SRST1_USB2HUTMI    0x00080000 /* USB 2.0 Host UTMI Interface */
+#define SDR0_SRST1_USB2HPHY     0x00040000 /* USB 2.0 Host Phy Interface */
+#define SDR0_SRST1_SRAM0        0x00020000 /* Internal SRAM Controller */
+#define SDR0_SRST1_RGMII0       0x00010000 /* RGMII Bridge */
+#define SDR0_SRST1_ETHPLL       0x00008000 /* Ethernet PLL */
+#define SDR0_SRST1_FPU          0x00004000 /* Floating Point Unit */
+#define SDR0_SRST1_KASU0        0x00002000 /* Kasumi Engine */
+
+#else
 
 #define SDR0_SRST_BGO			0x80000000
 #define SDR0_SRST_PLB			0x40000000
@@ -2427,10 +2832,15 @@
 #define SDR0_SRST_EMAC3			0x00000008
 #define SDR0_SRST_RGMII			0x00000001
 
+#endif
+
 /*-----------------------------------------------------------------------------+
 |  Clocking
 +-----------------------------------------------------------------------------*/
-#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
+#if !defined (CONFIG_440GX) && \
+    !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
+    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
+    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
 #define PLLSYS0_TUNE_MASK	0xffc00000	/* PLL TUNE bits	    */
 #define PLLSYS0_FB_DIV_MASK	0x003c0000	/* Feedback divisor	    */
 #define PLLSYS0_FWD_DIV_A_MASK	0x00038000	/* Forward divisor A	    */
@@ -2498,6 +2908,120 @@
 #define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
 #endif /* CONFIG_440GX */
 
+#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
+/*--------------------------------------*/
+#define CPR0_PLLC                   0x40
+#define   CPR0_PLLC_RST_MASK           0x80000000
+#define   CPR0_PLLC_RST_PLLLOCKED      0x00000000
+#define   CPR0_PLLC_RST_PLLRESET       0x80000000
+#define   CPR0_PLLC_ENG_MASK           0x40000000
+#define   CPR0_PLLC_ENG_DISABLE        0x00000000
+#define   CPR0_PLLC_ENG_ENABLE         0x40000000
+#define   CPR0_PLLC_ENG_ENCODE(n)      ((((unsigned long)(n))&0x01)<<30)
+#define   CPR0_PLLC_ENG_DECODE(n)      ((((unsigned long)(n))>>30)&0x01)
+#define   CPR0_PLLC_SRC_MASK           0x20000000
+#define   CPR0_PLLC_SRC_PLLOUTA        0x00000000
+#define   CPR0_PLLC_SRC_PLLOUTB        0x20000000
+#define   CPR0_PLLC_SRC_ENCODE(n)      ((((unsigned long)(n))&0x01)<<29)
+#define   CPR0_PLLC_SRC_DECODE(n)      ((((unsigned long)(n))>>29)&0x01)
+#define   CPR0_PLLC_SEL_MASK           0x07000000
+#define   CPR0_PLLC_SEL_PLL            0x00000000
+#define   CPR0_PLLC_SEL_CPU            0x01000000
+#define   CPR0_PLLC_SEL_PER            0x05000000
+#define   CPR0_PLLC_SEL_ENCODE(n)      ((((unsigned long)(n))&0x07)<<24)
+#define   CPR0_PLLC_SEL_DECODE(n)      ((((unsigned long)(n))>>24)&0x07)
+#define   CPR0_PLLC_TUNE_MASK          0x000003FF
+#define   CPR0_PLLC_TUNE_ENCODE(n)     ((((unsigned long)(n))&0x3FF)<<0)
+#define   CPR0_PLLC_TUNE_DECODE(n)     ((((unsigned long)(n))>>0)&0x3FF)
+/*--------------------------------------*/
+#define CPR0_PLLD                   0x60
+#define   CPR0_PLLD_FBDV_MASK          0x1F000000
+#define   CPR0_PLLD_FBDV_ENCODE(n)     ((((unsigned long)(n))&0x1F)<<24)
+#define   CPR0_PLLD_FBDV_DECODE(n)     ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
+#define   CPR0_PLLD_FWDVA_MASK         0x000F0000
+#define   CPR0_PLLD_FWDVA_ENCODE(n)    ((((unsigned long)(n))&0x0F)<<16)
+#define   CPR0_PLLD_FWDVA_DECODE(n)    ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
+#define   CPR0_PLLD_FWDVB_MASK         0x00000700
+#define   CPR0_PLLD_FWDVB_ENCODE(n)    ((((unsigned long)(n))&0x07)<<8)
+#define   CPR0_PLLD_FWDVB_DECODE(n)    ((((((unsigned long)(n))>>8)-1)&0x07)+1)
+#define   CPR0_PLLD_LFBDV_MASK         0x0000003F
+#define   CPR0_PLLD_LFBDV_ENCODE(n)    ((((unsigned long)(n))&0x3F)<<0)
+#define   CPR0_PLLD_LFBDV_DECODE(n)    ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
+/*--------------------------------------*/
+#define CPR0_PRIMAD                 0x80
+#define   CPR0_PRIMAD_PRADV0_MASK      0x07000000
+#define   CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+#define   CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+/*--------------------------------------*/
+#define CPR0_PRIMBD                 0xA0
+#define   CPR0_PRIMBD_PRBDV0_MASK      0x07000000
+#define   CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+#define   CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+/*--------------------------------------*/
+#if 0
+#define CPR0_CPM0_ER                0xB0    /* CPM Enable Register */
+#define CPR0_CPM0_FR                0xB1    /* CPM Force Register */
+#define CPR0_CPM0_SR                0xB2    /* CPM Status Register */
+#define CPR0_CPM0_IIC0               0x80000000    /* Inter-Intergrated Circuit0 */
+#define CPR0_CPM0_IIC1               0x40000000    /* Inter-Intergrated Circuit1 */
+#define CPR0_CPM0_PCI                0x20000000    /* Peripheral Component Interconnect */
+#define CPR0_CPM0_USB1H              0x08000000    /* USB1.1 Host */
+#define CPR0_CPM0_FPU                0x04000000    /* PPC440 FPU */
+#define CPR0_CPM0_CPU                0x02000000    /* PPC440x5 Processor Core */
+#define CPR0_CPM0_DMA                0x01000000    /* Direct Memory Access Controller */
+#define CPR0_CPM0_BGO                0x00800000    /* PLB to OPB Bridge */
+#define CPR0_CPM0_BGI                0x00400000    /* OPB to PLB Bridge */
+#define CPR0_CPM0_EBC                0x00200000    /* External Bus Controller */
+#define CPR0_CPM0_NDFC               0x00100000    /* Nand Flash Controller */
+#define CPR0_CPM0_MADMAL             0x00080000    /* DDR SDRAM Controller or MADMAL ??? */
+#define CPR0_CPM0_DMC                0x00080000    /* DDR SDRAM Controller or MADMAL ??? */
+#define CPR0_CPM0_PLB4               0x00040000    /* PLB4 Arbiter */
+#define CPR0_CPM0_PLB4x3x            0x00020000    /* PLB4 to PLB3 */
+#define CPR0_CPM0_PLB3x4x            0x00010000    /* PLB3 to PLB4 */
+#define CPR0_CPM0_PLB3               0x00008000    /* PLB3 Arbiter */
+#define CPR0_CPM0_PPM                0x00002000    /* PLB Performance Monitor */
+#define CPR0_CPM0_UIC1               0x00001000    /* Universal Interrupt Controller 1 */
+#define CPR0_CPM0_GPIO               0x00000800    /* General Purpose IO */
+#define CPR0_CPM0_GPT                0x00000400    /* General Purpose Timer */
+#define CPR0_CPM0_UART0              0x00000200    /* Universal Asynchronous Rcver/Xmitter 0 */
+#define CPR0_CPM0_UART1              0x00000100    /* Universal Asynchronous Rcver/Xmitter 1 */
+#define CPR0_CPM0_UIC0               0x00000080    /* Universal Interrupt Controller 0 */
+#define CPR0_CPM0_TMRCLK             0x00000040    /* CPU Timer */
+#define CPR0_CPM0_EMC0               0x00000020    /* Ethernet 0 */
+#define CPR0_CPM0_EMC1               0x00000010    /* Ethernet 1 */
+#define CPR0_CPM0_UART2              0x00000008    /* Universal Asynchronous Rcver/Xmitter 2 */
+#define CPR0_CPM0_UART3              0x00000004    /* Universal Asynchronous Rcver/Xmitter 3 */
+#define CPR0_CPM0_USB2D              0x00000002    /* USB2.0 Device */
+#define CPR0_CPM0_USB2H              0x00000001    /* USB2.0 Host */
+#endif
+/*--------------------------------------*/
+#define CPR0_OPBD                   0xC0
+#define   CPR0_OPBD_OPBDV0_MASK        0x03000000
+#define   CPR0_OPBD_OPBDV0_ENCODE(n)   ((((unsigned long)(n))&0x03)<<24)
+#define   CPR0_OPBD_OPBDV0_DECODE(n)   ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+/*--------------------------------------*/
+#define CPR0_PERD                   0xE0
+#define   CPR0_PERD_PERDV0_MASK        0x07000000
+#define   CPR0_PERD_PERDV0_ENCODE(n)   ((((unsigned long)(n))&0x07)<<24)
+#define   CPR0_PERD_PERDV0_DECODE(n)   ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+/*--------------------------------------*/
+#define CPR0_MALD                  0x100
+#define   CPR0_MALD_MALDV0_MASK        0x03000000
+#define   CPR0_MALD_MALDV0_ENCODE(n)   ((((unsigned long)(n))&0x03)<<24)
+#define   CPR0_MALD_MALDV0_DECODE(n)   ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+/*--------------------------------------*/
+#define CPR0_SPCID                 0x120
+#define   CPR0_SPCID_SPCIDV0_MASK      0x03000000
+#define   CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+#define   CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+/*--------------------------------------*/
+#define CPR0_ICFG                  0x140
+#define   CPR0_ICFG_RLI_MASK           0x80000000
+#define   CPR0_ICFG_RLI_RESETCPR       0x00000000
+#define   CPR0_ICFG_RLI_PRESERVECPR    0x80000000
+#define   CPR0_ICFG_ICS_MASK           0x00000007
+#endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */
+
 /*-----------------------------------------------------------------------------
 | IIC Register Offsets
 '----------------------------------------------------------------------------*/
@@ -2539,7 +3063,8 @@
 #define PCIX0_CFGBASE		(CFG_PCI_BASE + 0x0ec80000)
 #define PCIX0_IOBASE		(CFG_PCI_BASE + 0x08000000)
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 /* PCI Local Configuration Registers
    --------------------------------- */
@@ -2625,6 +3150,33 @@
 
 #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+/* USB2.0 Device */
+#define USB2D0_BASE         CFG_USB2D0_BASE
+
+#define USB2D0_INTRIN       (USB2D0_BASE + 0x00000000)
+
+#define USB2D0_INTRIN       (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
+#define USB2D0_POWER        (USB2D0_BASE + 0x00000000) /* Power management register */
+#define USB2D0_FADDR        (USB2D0_BASE + 0x00000000) /* Function address register */
+#define USB2D0_INTRINE      (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
+#define USB2D0_INTROUT      (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
+#define USB2D0_INTRUSBE     (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
+#define USB2D0_INTRUSB      (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
+#define USB2D0_INTROUTE     (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
+#define USB2D0_TSTMODE      (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
+#define USB2D0_INDEX        (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
+#define USB2D0_FRAME        (USB2D0_BASE + 0x00000000) /* Frame number */
+#define USB2D0_INCSR0       (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
+#define USB2D0_INCSR        (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_INMAXP       (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTCSR       (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTMAXP      (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTCOUNT0    (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
+#define USB2D0_OUTCOUNT     (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
+#endif
+
 /******************************************************************************
  * GPIO macro register defines
  ******************************************************************************/
@@ -2640,7 +3192,8 @@
 #define GPIO0_IR               (GPIO0_BASE+0x1C)
 #endif /* CONFIG_440GP */
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000B00)
 #define GPIO1_BASE             (CFG_PERIPHERAL_BASE+0x00000C00)
 
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index ec2e3629bb8..43c5ca451e0 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -145,12 +145,14 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_STACR_OC_MASK	(0x00000000)
 #endif
 
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define SDR0_PFC1_EM_1000	(0x00200000)
 #endif
 
 /*ZMII Bridge Register addresses */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0D00)
 #else
 #define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0780)
@@ -163,6 +165,7 @@ typedef struct emac_4xx_hw_st {
 #define ZMII_MDI0			0x80000000
 
 /* ZMII FER Register Bit Definitions */
+#define ZMII_FER_DIS		(0x0)
 #define ZMII_FER_MDI		(0x8)
 #define ZMII_FER_SMII		(0x4)
 #define ZMII_FER_RMII		(0x2)
@@ -197,7 +200,11 @@ typedef struct emac_4xx_hw_st {
 #define ZMII_SMIISR_V(__x)	((3 - __x) * 8)
 
 /* RGMII Register Addresses */
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x1000)
+#else
 #define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x0790)
+#endif
 #define RGMII_FER		(RGMII_BASE + 0x00)
 #define RGMII_SSR		(RGMII_BASE + 0x04)
 
@@ -216,7 +223,11 @@ typedef struct emac_4xx_hw_st {
 #define RGMII_SSR_SP_100MBPS	(0x02)
 #define RGMII_SSR_SP_1000MBPS	(0x04)
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define RGMII_SSR_V(__x)	((__x) * 8)
+#else
 #define RGMII_SSR_V(__x)	((__x -2) * 8)
+#endif
 
 
 /*---------------------------------------------------------------------------+
@@ -286,7 +297,8 @@ typedef struct emac_4xx_hw_st {
 
 /* Ethernet MAC Regsiter Addresses */
 #if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0E00)
 #else
 #define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0800)
@@ -332,7 +344,9 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_M0_WKE			    (0x04000000)
 
 /* on 440GX EMAC_MR1 has a different layout! */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 /* MODE Reg 1 */
 #define EMAC_M1_FDE		(0x80000000)
 #define EMAC_M1_ILE		(0x40000000)
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 72d690ef0f8..3e47e82abad 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -312,7 +312,7 @@ label:                                                  \
 	lwz     r3,GOT(transfer_to_handler);            \
 	mtlr    r3;                                     \
 	addi    r3,r1,STACK_FRAME_OVERHEAD;             \
-	li      r20,MSR_KERNEL;                         \
+	li      r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
 	rlwimi  r20,r23,0,25,25;                        \
 	blrl    ;                                       \
 .L_ ## label :                                          \
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index db80f775603..cf0e3fdf4b6 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -763,6 +763,12 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	spi_init_r ();
 #endif
 
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	WATCHDOG_RESET ();
+	puts ("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
 	/* relocate environment function pointers etc. */
 	env_relocate ();
 
@@ -959,12 +965,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	doc_init ();
 #endif
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-	WATCHDOG_RESET ();
-	puts ("NAND:  ");
-	nand_init();		/* go init the NAND */
-#endif
-
 #if (CONFIG_COMMANDS & CFG_CMD_NET)
 #if defined(CONFIG_NET_MULTI)
 	WATCHDOG_RESET ();
diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile
new file mode 100644
index 00000000000..6c07e3dd8df
--- /dev/null
+++ b/nand_spl/board/amcc/sequoia/Makefile
@@ -0,0 +1,83 @@
+#
+# (C) Copyright 2006
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+include board/$(BOARDDIR)/config.mk
+
+LDSCRIPT= board/$(BOARDDIR)/u-boot.lds
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS	+= -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_NAND_SPL
+
+SOBJS	= start.o init.o resetvec.o
+COBJS	= nand_boot.o ndfc.o sdram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+ALL	= u-boot-spl u-boot-spl.bin u-boot-spl-4k.bin
+
+all:	$(obj).depend $(ALL)
+
+u-boot-spl-4k.bin: u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+u-boot-spl.bin:	u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+u-boot-spl:	$(OBJS)
+	$(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
+		-Map u-boot-spl.map -o u-boot-spl
+
+# create symbolic links for common files
+
+# from cpu directory
+ndfc.c:
+	@rm -f ndfc.c
+	ln -s ../cpu/ppc4xx/ndfc.c ndfc.c
+
+resetvec.S:
+	@rm -f resetvec.S
+	ln -s ../cpu/ppc4xx/resetvec.S resetvec.S
+
+start.S:
+	@rm -f start.S
+	ln -s ../cpu/ppc4xx/start.S start.S
+
+# from board directory
+init.S:
+	@rm -f init.S
+	ln -s ../board/amcc/sequoia/init.S init.S
+
+sdram.c:
+	@rm -f sdram.c
+	ln -s ../board/amcc/sequoia/sdram.c sdram.c
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/amcc/sequoia/config.mk b/nand_spl/board/amcc/sequoia/config.mk
new file mode 100644
index 00000000000..a29ba5fd0dc
--- /dev/null
+++ b/nand_spl/board/amcc/sequoia/config.mk
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2006
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 440EPx Reference Platform (Sequoia) board
+#
+
+#
+# TEXT_BASE for SPL:
+#
+# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
+# in the last 4kBytes of memory space in cache.
+# We will copy this SPL into internal SRAM in start.S. So we set
+# TEXT_BASE to starting address in internal SRAM here.
+#
+TEXT_BASE = 0xE0013000
+
+# PAD_TO used to generate a 16kByte binary needed for the combined image
+# -> PAD_TO = TEXT_BASE + 0x4000
+PAD_TO	= 0xE0017000
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/nand_spl/board/amcc/sequoia/u-boot.lds b/nand_spl/board/amcc/sequoia/u-boot.lds
new file mode 100644
index 00000000000..156368911a2
--- /dev/null
+++ b/nand_spl/board/amcc/sequoia/u-boot.lds
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc:common)
+SECTIONS
+{
+  .resetvec 0xE0013FFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .text      :
+  {
+    start.o	(.text)
+    init.o	(.text)
+    nand_boot.o	(.text)
+    sdram.o	(.text)
+    ndfc.o	(.text)
+
+    *(.text)
+    *(.fixup)
+  }
+  _etext = .;
+
+  .data    :
+  {
+    *(.rodata*)
+    *(.data*)
+    *(.sdata*)
+    __got2_start = .;
+    *(.got2)
+    __got2_end = .;
+  }
+
+  _edata  =  .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss)
+   *(.bss)
+  }
+
+  _end = . ;
+}
diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c
new file mode 100644
index 00000000000..6e3af13939f
--- /dev/null
+++ b/nand_spl/nand_boot.c
@@ -0,0 +1,178 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+
+#define CFG_NAND_READ_DELAY \
+	{ volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }
+
+extern void board_nand_init(struct nand_chip *nand);
+extern void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd);
+extern void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte);
+extern u_char ndfc_read_byte(struct mtd_info *mtdinfo);
+extern int ndfc_dev_ready(struct mtd_info *mtdinfo);
+extern int jump_to_ram(ulong delta);
+extern int jump_to_uboot(ulong addr);
+
+static int nand_is_bad_block(struct mtd_info *mtd, int block)
+{
+        struct nand_chip *this = mtd->priv;
+	int page_addr = block * CFG_NAND_PAGE_COUNT;
+
+	/* Begin command latch cycle */
+	this->hwcontrol(mtd, NAND_CTL_SETCLE);
+	this->write_byte(mtd, NAND_CMD_READOOB);
+	/* Set ALE and clear CLE to start address cycle */
+	this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+	this->hwcontrol(mtd, NAND_CTL_SETALE);
+	/* Column address */
+	this->write_byte(mtd, CFG_NAND_BAD_BLOCK_POS);			/* A[7:0] */
+	this->write_byte(mtd, (uchar)(page_addr & 0xff));		/* A[16:9] */
+	this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff));	/* A[24:17] */
+#ifdef CFG_NAND_4_ADDR_CYCLE
+	/* One more address cycle for devices > 32MiB */
+	this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f));	/* A[xx:25] */
+#endif
+	/* Latch in address */
+	this->hwcontrol(mtd, NAND_CTL_CLRALE);
+
+	/*
+	 * Wait a while for the data to be ready
+	 */
+	if (this->dev_ready)
+		this->dev_ready(mtd);
+	else
+		CFG_NAND_READ_DELAY;
+
+	/*
+	 * Read on byte
+	 */
+	if (this->read_byte(mtd) != 0xff)
+		return 1;
+
+	return 0;
+}
+
+static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
+{
+        struct nand_chip *this = mtd->priv;
+	int page_addr = page + block * CFG_NAND_PAGE_COUNT;
+	int i;
+
+	/* Begin command latch cycle */
+	this->hwcontrol(mtd, NAND_CTL_SETCLE);
+	this->write_byte(mtd, NAND_CMD_READ0);
+	/* Set ALE and clear CLE to start address cycle */
+	this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+	this->hwcontrol(mtd, NAND_CTL_SETALE);
+	/* Column address */
+	this->write_byte(mtd, 0);					/* A[7:0] */
+	this->write_byte(mtd, (uchar)(page_addr & 0xff));		/* A[16:9] */
+	this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff));	/* A[24:17] */
+#ifdef CFG_NAND_4_ADDR_CYCLE
+	/* One more address cycle for devices > 32MiB */
+	this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f));	/* A[xx:25] */
+#endif
+	/* Latch in address */
+	this->hwcontrol(mtd, NAND_CTL_CLRALE);
+
+	/*
+	 * Wait a while for the data to be ready
+	 */
+	if (this->dev_ready)
+		this->dev_ready(mtd);
+	else
+		CFG_NAND_READ_DELAY;
+
+	/*
+	 * Read page into buffer
+	 */
+	for (i=0; i<CFG_NAND_PAGE_SIZE; i++)
+		*dst++ = this->read_byte(mtd);
+
+	return 0;
+}
+
+static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst)
+{
+	int block;
+	int blockcopy_count;
+	int page;
+
+	/*
+	 * offs has to be aligned to a block address!
+	 */
+	block = offs / CFG_NAND_BLOCK_SIZE;
+	blockcopy_count = 0;
+
+	while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) {
+		if (!nand_is_bad_block(mtd, block)) {
+			/*
+			 * Skip bad blocks
+			 */
+			for (page = 0; page < CFG_NAND_PAGE_COUNT; page++) {
+				nand_read_page(mtd, block, page, dst);
+				dst += CFG_NAND_PAGE_SIZE;
+			}
+
+			blockcopy_count++;
+		}
+
+		block++;
+	}
+
+	return 0;
+}
+
+void nand_boot(void)
+{
+	ulong mem_size;
+	struct nand_chip nand_chip;
+	nand_info_t nand_info;
+	int ret;
+	void (*uboot)(void);
+
+	/*
+	 * Init sdram, so we have access to memory
+	 */
+	mem_size = initdram(0);
+
+	/*
+	 * Init board specific nand support
+	 */
+	nand_info.priv = &nand_chip;
+	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void  __iomem *)CFG_NAND_BASE;
+	nand_chip.dev_ready = NULL;	/* preset to NULL */
+	board_nand_init(&nand_chip);
+
+	/*
+	 * Load U-Boot image from NAND into RAM
+	 */
+	ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS,
+			CFG_NAND_U_BOOT_SIZE,
+			(uchar *)CFG_NAND_U_BOOT_DST);
+
+	/*
+	 * Jump to U-Boot image
+	 */
+	uboot = (void (*)(void))CFG_NAND_U_BOOT_START;
+	(*uboot)();
+}
-- 
cgit v1.3.1


From 8cacfb85a89f9136d685697eb2c97dae5bddfe8d Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 7 Sep 2006 12:23:02 +0200
Subject: Change Yellowstone to use CFI write buffer Patch by Stefan Roese, 07
 Aug 2006

---
 CHANGELOG                     | 3 +++
 include/configs/yellowstone.h | 2 ++
 2 files changed, 5 insertions(+)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index 576cd7fb861..f71c864228a 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Change Yellowstone to use CFI write buffer
+  Patch by Stefan Roese, 07 Aug 2006
+
 * Add support for AMCC Sequoia PPC440EPx eval board
   - Add support for PPC440EPx & PPC440GRx
   - Add support for PPC440EP(x)/GR(x) NAND controller
diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h
index bcafd8ba8b3..ba27f37f6eb 100644
--- a/include/configs/yellowstone.h
+++ b/include/configs/yellowstone.h
@@ -110,6 +110,8 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #ifdef CFG_ENV_IS_IN_FLASH
-- 
cgit v1.3.1


From efa20585b3ccfdde431c19c6a9d9d8dae46fe5bb Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 7 Sep 2006 12:48:49 +0200
Subject: Fix build problem with CPCI440 Patch by Stefan Roese, 07 Sep 2006

---
 CHANGELOG                 | 5 ++++-
 include/configs/CPCI440.h | 3 ++-
 2 files changed, 6 insertions(+), 2 deletions(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index f71c864228a..27d9226fde9 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,8 +2,11 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Fix build problem with CPCI440
+  Patch by Stefan Roese, 07 Sep 2006
+
 * Change Yellowstone to use CFI write buffer
-  Patch by Stefan Roese, 07 Aug 2006
+  Patch by Stefan Roese, 07 Sep 2006
 
 * Add support for AMCC Sequoia PPC440EPx eval board
   - Add support for PPC440EPx & PPC440GRx
diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h
index a5bc773e177..90d3a8d8fa3 100644
--- a/include/configs/CPCI440.h
+++ b/include/configs/CPCI440.h
@@ -31,7 +31,8 @@
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
-#define CONFIG_EBONY		1	    /* Board is ebony		*/
+#define CONFIG_CPCI440		1	    /* Board is ebony		*/
+#define CONFIG_440GP		1	    /* Specifc GP support	*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 #undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
-- 
cgit v1.3.1


From d12ae80889568365ecb9e6698322f9771ae76dde Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Tue, 12 Sep 2006 20:19:10 +0200
Subject: Add NAND environment support for PPC440EPx Sequoia NAND boot config
 Patch by Stefan Roese, 12 Sep 2006

---
 CHANGELOG                          |  3 +++
 board/amcc/sequoia/u-boot-nand.lds |  8 +++++-
 common/env_nand.c                  | 50 +++++++++++++++++++++++++++++++++++++-
 common/environment.c               |  3 ++-
 include/configs/sequoia.h          | 27 ++++++--------------
 include/environment.h              |  4 +++
 nand_spl/nand_boot.c               |  3 +--
 7 files changed, 73 insertions(+), 25 deletions(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index a6dc7623483..9840863bf7e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Add NAND environment support for PPC440EPx Sequoia NAND boot config
+  Patch by Stefan Roese, 12 Sep 2006
+
 * Update NAND boot documentation
   Patch by Stefan Roese, 12 Sep 2006
 
diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds
index c3d3d968fed..cf2e2b55812 100644
--- a/board/amcc/sequoia/u-boot-nand.lds
+++ b/board/amcc/sequoia/u-boot-nand.lds
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2002
+ * (C) Copyright 2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -56,6 +56,12 @@ SECTIONS
 
     cpu/ppc4xx/start.o	(.text)
 
+    /* Align to next NAND block */
+    . = ALIGN(0x4000);
+    common/environment.o  (.ppcenv)
+    /* Keep some space here for redundant env and potential bad env blocks */
+    . = ALIGN(0x10000);
+
     *(.text)
     *(.fixup)
     *(.got1)
diff --git a/common/env_nand.c b/common/env_nand.c
index 0a05b09a7a8..67c4a4e0117 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2004
  * Jian Zhang, Texas Instruments, jzhang@ti.com.
 
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
@@ -76,7 +76,9 @@ env_t *env_ptr = 0;
 
 
 /* local functions */
+#if !defined(ENV_IS_EMBEDDED)
 static void use_default(void);
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -91,11 +93,55 @@ uchar env_get_char_spec (int index)
  * Mark it OK for now. env_relocate() in env_common.c
  * will call our relocate function which will does
  * the real validation.
+ *
+ * When using a NAND boot image (like sequoia_nand), the environment
+ * can be embedded or attached to the U-Boot image in NAND flash. This way
+ * the SPL loads not only the U-Boot image from NAND but also the
+ * environment.
  */
 int env_init(void)
 {
+#if defined(ENV_IS_EMBEDDED)
+	ulong total;
+	int crc1_ok = 0, crc2_ok = 0;
+	env_t *tmp_env1, *tmp_env2;
+
+	total = CFG_ENV_SIZE;
+
+	tmp_env1 = env_ptr;
+	tmp_env2 = (env_t *)((ulong)env_ptr + CFG_ENV_SIZE);
+
+	crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc);
+	crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc);
+
+	if (!crc1_ok && !crc2_ok)
+		gd->env_valid = 0;
+	else if(crc1_ok && !crc2_ok)
+		gd->env_valid = 1;
+	else if(!crc1_ok && crc2_ok)
+		gd->env_valid = 2;
+	else {
+		/* both ok - check serial */
+		if(tmp_env1->flags == 255 && tmp_env2->flags == 0)
+			gd->env_valid = 2;
+		else if(tmp_env2->flags == 255 && tmp_env1->flags == 0)
+			gd->env_valid = 1;
+		else if(tmp_env1->flags > tmp_env2->flags)
+			gd->env_valid = 1;
+		else if(tmp_env2->flags > tmp_env1->flags)
+			gd->env_valid = 2;
+		else /* flags are equal - almost impossible */
+			gd->env_valid = 1;
+	}
+
+	if (gd->env_valid == 1)
+		env_ptr = tmp_env1;
+	else if (gd->env_valid == 2)
+		env_ptr = tmp_env2;
+#else /* ENV_IS_EMBEDDED */
 	gd->env_addr  = (ulong)&default_environment[0];
 	gd->env_valid = 1;
+#endif /* ENV_IS_EMBEDDED */
 
 	return (0);
 }
@@ -236,6 +282,7 @@ void env_relocate_spec (void)
 }
 #endif /* CFG_ENV_OFFSET_REDUND */
 
+#if !defined(ENV_IS_EMBEDDED)
 static void use_default()
 {
 	puts ("*** Warning - bad CRC or NAND, using default environment\n\n");
@@ -253,5 +300,6 @@ static void use_default()
 	gd->env_valid = 1;
 
 }
+#endif
 
 #endif /* CFG_ENV_IS_IN_NAND */
diff --git a/common/environment.c b/common/environment.c
index 81471ce71cd..19bdeb0f62a 100644
--- a/common/environment.c
+++ b/common/environment.c
@@ -60,7 +60,8 @@
      defined(CONFIG_RRVISION)	|| \
      defined(CONFIG_TRAB)   	|| \
      defined(CONFIG_PPCHAMELEONEVB) || \
-     defined(CONFIG_M5271EVB))	&& \
+     defined(CONFIG_M5271EVB)	|| \
+     defined(CONFIG_NAND_U_BOOT))	&& \
      defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */
 /* XXX - This only works with GNU C */
 #  define __PPCENV__ __attribute__ ((section(".ppcenv")))
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index d3fcc032aa5..639765d5990 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -69,14 +69,9 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer
  *----------------------------------------------------------------------*/
-#if 0
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
-#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
-#define CFG_INIT_RAM_ADDR	0x70000000	/* DCache		*/
-#else
 #define CFG_INIT_RAM_OCM	1		/* OCM as init ram	*/
 #define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
-#endif
 
 #define CFG_INIT_RAM_END	(4 << 10)
 #define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
@@ -98,18 +93,11 @@
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#if 1 /* test-only */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
 #else
 #define CFG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
 #endif
-#if 0
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
-#endif
 
 /*-----------------------------------------------------------------------
  * FLASH related
@@ -189,8 +177,12 @@
 #undef CFG_NAND_4_ADDR_CYCLE			/* No fourth addr used (<=32MB)	*/
 
 #ifdef CFG_ENV_IS_IN_NAND
-#define CFG_ENV_SIZE		0x4000
-#define CFG_ENV_OFFSET		(CFG_NAND_U_BOOT_OFFS + CFG_NAND_U_BOOT_SIZE)
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
+ */
+#define CFG_ENV_SIZE		CFG_NAND_BLOCK_SIZE
+#define CFG_ENV_OFFSET		(CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
 #define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET + CFG_ENV_SIZE)
 #endif
 
@@ -214,11 +206,6 @@
 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 
-#ifdef CFG_ENV_IS_IN_EEPROM
-#define CFG_ENV_SIZE		0x200		/* Size of Environment vars	*/
-#define CFG_ENV_OFFSET		0x0
-#endif /* CFG_ENV_IS_IN_EEPROM */
-
 /* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
 #define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
 #define CONFIG_DTT_AD7414	1		/* use AD7414		*/
diff --git a/include/environment.h b/include/environment.h
index 422f800897f..26b07120da1 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -79,6 +79,10 @@
 # ifdef CFG_ENV_OFFSET_REDUND
 #  define CFG_REDUNDAND_ENVIRONMENT
 # endif
+# if defined(CONFIG_NAND_U_BOOT)
+/* Use embedded environment in NAND boot versions */
+#  define ENV_IS_EMBEDDED	1
+# endif
 #endif /* CFG_ENV_IS_IN_NAND */
 
 
diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c
index 6e3af13939f..21abb09e39b 100644
--- a/nand_spl/nand_boot.c
+++ b/nand_spl/nand_boot.c
@@ -166,8 +166,7 @@ void nand_boot(void)
 	/*
 	 * Load U-Boot image from NAND into RAM
 	 */
-	ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS,
-			CFG_NAND_U_BOOT_SIZE,
+	ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE,
 			(uchar *)CFG_NAND_U_BOOT_DST);
 
 	/*
-- 
cgit v1.3.1


From 854bc8da75709f13dab4cfa6e9094c0cb49b5c5a Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 13 Sep 2006 13:51:58 +0200
Subject: Add support for AMCC Rainier PPX440GRx eval board Patch by Stefan
 Roese, 13 Sep 2006

---
 CHANGELOG                    |  3 +++
 Makefile                     | 15 +++++++++++++++
 board/amcc/sequoia/sequoia.c |  8 ++++++++
 cpu/ppc4xx/4xx_enet.c        |  2 +-
 cpu/ppc4xx/vecnum.h          |  2 +-
 include/configs/sequoia.h    | 13 ++++++++++++-
 6 files changed, 40 insertions(+), 3 deletions(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index a896e253a96..0f4b4d561e9 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -7,6 +7,9 @@ Changes since U-Boot 1.1.4:
 
 * Cleanup examples binaries
 
+* Add support for AMCC Rainier PPX440GRx eval board
+  Patch by Stefan Roese, 13 Sep 2006
+
 * Add NAND environment support for PPC440EPx Sequoia NAND boot config
   Patch by Stefan Roese, 12 Sep 2006
 
diff --git a/Makefile b/Makefile
index ccf7f9f88fc..f48ca6cebb5 100644
--- a/Makefile
+++ b/Makefile
@@ -1142,6 +1142,21 @@ PPChameleonEVB_HI_33_config:	unconfig
 		}
 	@$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
 
+rainier_config:	unconfig
+	@echo "#define CONFIG_RAINIER" > include/config.h
+	@echo "Configuring for rainier board as subset of sequoia..."
+	@$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
+
+rainier_nand_config:	unconfig
+	@echo "#define CONFIG_RAINIER" > include/config.h
+	@echo "Configuring for rainier board as subset of sequoia..."
+	@ln -s board/amcc/sequoia/Makefile nand_spl/Makefile
+	@echo "#define CONFIG_NAND_U_BOOT" >> include/config.h
+	@echo "Compile NAND boot image for sequoia"
+	@$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
+	@echo "TEXT_BASE = 0x01000000" >board/amcc/sequoia/config.tmp
+	@echo "CONFIG_NAND_U_BOOT = y" >> include/config.mk
+
 sbc405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
 
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 95734b9c57c..a8ba2c08319 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -140,10 +140,12 @@ int misc_init_r(void)
 {
 	uint pbcr;
 	int size_val = 0;
+#ifdef CONFIG_440EPX
 	unsigned long usb2d0cr = 0;
 	unsigned long usb2phy0cr, usb2h0cr = 0;
 	unsigned long sdr0_pfc1;
 	char *act = getenv("usbact");
+#endif
 
 	/*
 	 * FLASH stuff...
@@ -211,6 +213,7 @@ int misc_init_r(void)
 	/*
 	 * USB suff...
 	 */
+#ifdef CONFIG_440EPX
 	if (act == NULL || strcmp(act, "hostdev") == 0)	{
 		/* SDR Setting */
         	mfsdr(SDR0_PFC1, sdr0_pfc1);
@@ -322,6 +325,7 @@ int misc_init_r(void)
 
 		printf("USB:   Device(int phy)\n");
 	}
+#endif /* CONFIG_440EPX */
 
 	return 0;
 }
@@ -330,7 +334,11 @@ int checkboard(void)
 {
 	char *s = getenv("serial#");
 
+#ifdef CONFIG_440EPX
 	printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
+#else
+	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
+#endif
 	if (s != NULL) {
 		puts(", serial# ");
 		puts(s);
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 5b1c17c351a..81d49ffdfeb 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -133,7 +133,7 @@
 #define BI_PHYMODE_GMII  3
 #define BI_PHYMODE_RTBI  4
 #define BI_PHYMODE_TBI   5
-#if defined (CONFIG_440EPX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define BI_PHYMODE_SMII  6
 #define BI_PHYMODE_MII   7
 #endif
diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h
index 70e436aab23..685d48bcf64 100644
--- a/cpu/ppc4xx/vecnum.h
+++ b/cpu/ppc4xx/vecnum.h
@@ -31,7 +31,7 @@
 #ifndef _VECNUMS_H_
 #define _VECNUMS_H_
 
-#if defined(CONFIG_440EPX) || defined(CONFIG_440_GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 /* UIC 0 */
 #define VECNUM_U0                   0  /* UART 0                        */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 639765d5990..f67fd9163d0 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -31,8 +31,13 @@
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
+/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
+#ifndef CONFIG_RAINIER
 #define CONFIG_SEQUOIA		1		/* Board is Sequoia	*/
 #define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
+#else
+#define CONFIG_440GRX		1		/* Specific PPC440GRx	*/
+#endif
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
 
@@ -272,12 +277,18 @@
 #define CONFIG_PHY1_ADDR	1
 
 /* USB */
+#ifdef CONFIG_440EPX
 #define CONFIG_USB_OHCI
 #define CONFIG_USB_STORAGE
 
 /* Comment this out to enable USB 1.1 device */
 #define USB_2_0_DEVICE
 
+#define CMD_USB			CFG_CMD_USB
+#else
+#define CMD_USB			0	/* no USB on 440GRx		*/
+#endif /* CONFIG_440EPX */
+
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -301,7 +312,7 @@
 			       CFG_CMD_PING	|	\
 			       CFG_CMD_REGINFO	|	\
 			       CFG_CMD_SDRAM	|	\
-			       CFG_CMD_USB    )
+			       CMD_USB)
 
 #define CONFIG_SUPPORT_VFAT
 
-- 
cgit v1.3.1


From ac611700e5bcdd5a762dcc4d28db256fcc5a4bf2 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@fifi.denx.de>
Date: Wed, 20 Sep 2006 23:47:49 +0200
Subject: Fix comments in include/ppc440.h Patch by Martin Hicks, 16 Jun 2006

---
 CHANGELOG        | 3 +++
 include/ppc440.h | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index a896e253a96..2059b66038b 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Fix comments in include/ppc440.h
+  Patch by Martin Hicks, 16 Jun 2006
+
 * Disable autoboot abort for FO300 when silent mode is enabled
   (according to S1 switch setting).
 
diff --git a/include/ppc440.h b/include/ppc440.h
index c4a3ed54835..e407320a9ef 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1570,8 +1570,8 @@
 #define malrxctp0r  (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg   */
 #define malrxctp1r  (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg   */
 #if defined(CONFIG_440GX)
-#define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg   */
-#define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg   */
+#define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg   */
+#define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg   */
 #endif /* CONFIG_440GX */
 #define malrcbs0    (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg	    */
 #define malrcbs1    (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg	    */
-- 
cgit v1.3.1


From 7299712c869ce1f409a854ca0d2b268783038ab2 Mon Sep 17 00:00:00 2001
From: Marian Balakowicz <m8@semihalf.com>
Date: Tue, 3 Oct 2006 20:28:38 +0200
Subject: Update for CAM5200 board:   - Map in a additional chip selects CS4
 and CS5.   - Modify the port configration, configure six UARTs and no PCI,   
  ATA and USB.   - Add custom flash driver to handle specific byte swapping

---
 CHANGELOG                     |   6 +
 board/tqm5200/Makefile        |   5 +-
 board/tqm5200/cam5200_flash.c | 786 ++++++++++++++++++++++++++++++++++++++++++
 include/configs/TQM5200.h     | 101 ++++--
 include/flash.h               |   4 +
 5 files changed, 868 insertions(+), 34 deletions(-)
 create mode 100644 board/tqm5200/cam5200_flash.c

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index a896e253a96..42768a365fc 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,12 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Update for CAM5200 board:
+  - Map in a additional chip selects CS4 and CS5.
+  - Modify the port configration, configure six UARTs and no PCI,
+    ATA and USB.
+  - Add custom flash driver to handle specific byte swapping
+
 * Disable autoboot abort for FO300 when silent mode is enabled
   (according to S1 switch setting).
 
diff --git a/board/tqm5200/Makefile b/board/tqm5200/Makefile
index d0dde2657c7..383b0386082 100644
--- a/board/tqm5200/Makefile
+++ b/board/tqm5200/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o cmd_stk52xx.o cmd_tb5200.o
+COBJS	:= $(BOARD).o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
@@ -40,6 +40,9 @@ clean:
 distclean:	clean
 	rm -f $(LIB) core *.bak .depend
 
+cam5200_flash.o:	cam5200_flash.c
+	$(CC) $(CFLAGS) -fno-strict-aliasing -c -o $@ $<
+
 #########################################################################
 
 # defines $(obj).depend target
diff --git a/board/tqm5200/cam5200_flash.c b/board/tqm5200/cam5200_flash.c
new file mode 100644
index 00000000000..85d310b77df
--- /dev/null
+++ b/board/tqm5200/cam5200_flash.c
@@ -0,0 +1,786 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <asm/processor.h>
+
+#ifdef CONFIG_CAM5200
+
+#if 0
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif
+
+#define swap16(x) __swab16(x)
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*
+ * CAM5200 is a TQM5200B based board. Additionally it also features
+ * a NIOS cpu. The NIOS CPU peripherals are accessible through MPC5xxx
+ * Local Bus on CS5. This includes 32 bit wide RAM and SRAM as well as
+ * 16 bit wide flash device. Big Endian order on a 32 bit CS5 makes
+ * access to flash chip slightly more complicated as additional byte
+ * swapping is necessary within each 16 bit wide flash 'word'.
+ *
+ * This driver's task is to handle both flash devices: 32 bit TQM5200B
+ * flash chip and 16 bit NIOS cpu flash chip. In the below 
+ * flash_addr_table table we use least significant address bit to mark
+ * 16 bit flash bank and two sets of routines *_32 and *_16 to handle
+ * specifics of both flashes.
+ */
+static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
+	{CFG_BOOTCS_START, CFG_CS5_START | 1}
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word_32(flash_info_t * info, ulong dest, ulong data);
+static int write_word_16(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_32(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_16(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_32(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_16(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+	int i, k;
+	int size, erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			printf("AMD ");
+			break;
+		case FLASH_MAN_FUJ:
+			printf("FUJITSU ");
+			break;
+		default:
+			printf("Unknown Vendor ");
+			break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_S29GL128N:
+			printf ("S29GL128N (256 Mbit, uniform sector size)\n");
+			break;
+		case FLASH_AM320B:
+			printf ("29LV320B (32 Mbit, bottom boot sect)\n");
+			break;
+		case FLASH_AM320T:
+			printf ("29LV320T (32 Mbit, top boot sect)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			break;
+	}
+
+	printf("  Size: %ld KB in %d Sectors\n",
+			info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf("\n   ");
+
+		printf(" %08lX%s%s", info->start[i],
+				erased ? " E" : "  ",
+				info->protect[i] ? "RO " : "   ");
+	}
+	printf("\n");
+	return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+
+	DEBUGF("get_size: FLASH ADDR %08lx\n", addr);
+
+	/* bit 0 used for big flash marking */
+	if ((ulong)addr & 0x1)
+		return flash_get_size_16((vu_long *)((ulong)addr & 0xfffffffe), info);
+	else
+		return flash_get_size_32(addr, info);
+}
+
+static ulong flash_get_size_32(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+	short i;
+	CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+		case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+		case AMD_ID_MIRROR:
+			DEBUGF("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
+					addr[14], addr[15]);
+			switch(addr[14]) {
+				case AMD_ID_GL128N_2:
+					if (addr[15] != AMD_ID_GL128N_3) {
+						DEBUGF("Chip: S29GL128N -> unknown\n");
+						info->flash_id = FLASH_UNKNOWN;
+					} else {
+						DEBUGF("Chip: S29GL128N\n");
+						info->flash_id += FLASH_S29GL128N;
+						info->sector_count = 128;
+						info->size = 0x02000000;
+					}
+					break;
+				default:
+					info->flash_id = FLASH_UNKNOWN;
+					return(0);
+			}
+			break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00040000);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+		info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_32(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CFG_FLASH_WORD_SIZE *addr =
+		(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+			(CFG_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
+		return flash_erase_16(info, s_first, s_last);
+	} else {
+		return flash_erase_32(info, s_first, s_last);
+	}
+}
+
+static int flash_erase_32(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!", prot);
+
+	printf("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+			addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_32(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp)
+			data = (data << 8) | (*(uchar *) cp);
+
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+
+		for (; cnt == 0 && i < 4; ++i, ++cp)
+			data = (data << 8) | (*(uchar *) cp);
+
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i)
+			data = (data << 8) | *src++;
+
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0)
+		return (0);
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp)
+		data = (data << 8) | (*(uchar *) cp);
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
+		return write_word_16(info, dest, data);
+	} else {
+		return write_word_32(info, dest, data);
+	}
+}
+
+static int write_word_32(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i, flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data)
+		return (2);
+
+	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+				(data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+				return (1);
+		}
+	}
+
+	return (0);
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+
+#undef  CFG_FLASH_WORD_SIZE
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_16(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90009000;
+	udelay(1000);
+
+	value = swap16(addr2[0]);
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+		case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+		case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+			info->flash_id = FLASH_MAN_FUJ;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* no or unknown flash  */
+	}
+
+	value = swap16(addr2[1]);	/* device ID            */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+		case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+			info->flash_id += FLASH_AM320B;
+			info->sector_count = 71;
+			info->size = 0x00400000;
+			break;	/* => 4 MB	*/
+		case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+			info->flash_id += FLASH_AM320T;
+			info->sector_count = 71;
+			info->size = 0x00400000;
+			break;	/* => 4 MB	*/
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);	/* => no or unknown flash */
+	}
+
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type        */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00002000;
+		info->start[2] = base + 0x00004000;
+		info->start[3] = base + 0x00006000;
+		info->start[4] = base + 0x00008000;
+		info->start[5] = base + 0x0000a000;
+		info->start[6] = base + 0x0000c000;
+		info->start[7] = base + 0x0000e000;
+
+		for (i = 8; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000) - 0x00070000;
+	} else {
+		/* set sector offsets for top boot block type           */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00002000;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000a000;
+		info->start[i--] = base + info->size - 0x0000c000;
+		info->start[i--] = base + info->size - 0x0000e000;
+
+		for (; i >= 0; i--)
+			info->start[i] = base + i * 0x00010000;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+		info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_16(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CFG_FLASH_WORD_SIZE *addr =
+		(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x80008000) !=
+			(CFG_FLASH_WORD_SIZE) 0x80008000) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+static int flash_erase_16(flash_info_t * info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!",	prot);
+
+	printf("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00;
+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500;
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80008000;
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00;
+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500;
+			addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30003000;	/* sector erase */
+
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_16(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+static int write_word_16(flash_info_t * info, ulong dest, ulong data)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+		if ((dest2[i] & swap16(data2[i])) != swap16(data2[i]))
+			return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00;
+		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500;
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA000A000;
+
+		dest2[i] = swap16(data2[i]);
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80008000) !=
+				(swap16(data2[i]) & (CFG_FLASH_WORD_SIZE) 0x80008000)) {
+
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+#endif /* CFG_FLASH_2ND_16BIT_DEV */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0)
+			continue;
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+				&flash_info[i]);
+
+		flash_info[i].size = size_b[i];
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+					i, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+				    &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH)
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+				    CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#if defined(CFG_ENV_ADDR_REDUND)
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+				    CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#endif
+#endif
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
+#endif /* ifdef CONFIG_CAM5200 */
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index e0de5c1b367..897d1b262b2 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -285,7 +285,7 @@
  */
 #define CFG_IPBSPEED_133		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200)
 /*
  * PCI Bus clocking configuration
  *
@@ -349,13 +349,29 @@
  */
 #define CFG_FLASH_BASE		0xFC000000
 
+#ifndef CONFIG_CAM5200
 /* use CFI flash driver */
 #define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
 #define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#else /* CONFIG_CAM5200 */
+#define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_FLASH_WORD_SIZE	unsigned int /* main flash device with */
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ADDR0		0x555
+#define CFG_FLASH_ADDR1		0x2AA
+#define CFG_FLASH_2ND_16BIT_DEV	1	/* NIOS flash is a 16bit device */
+#define CFG_MAX_FLASH_SECT	128
+#endif /* ifndef CONFIG_CAM5200 */
+
 #define CFG_FLASH_EMPTY_INFO
 #define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
 #define CFG_FLASH_USE_BUFFER_WRITE	1
 
 #if defined (CONFIG_CAM5200)
@@ -366,9 +382,6 @@
 # define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
 #endif
 
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
-					   (= chip selects) */
-
 /* Dynamic MTD partition support */
 #define CONFIG_JFFS2_CMDLINE
 #define MTDIDS_DEFAULT		"nor0=TQM5200-0"
@@ -401,10 +414,8 @@
 #elif defined (CONFIG_CAM5200)
 #   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:768k(firmware),"	\
 						"1792k(kernel),"	\
-						"3584k(small-fs),"	\
-						"2m(initrd),"		\
-						"8m(misc),"		\
-						"16m(big-fs)"
+						"5632k(rootfs),"	\
+						"24m(home)"
 #elif defined (CONFIG_FO300)
 #   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
 						"1408k(kernel),"	\
@@ -479,31 +490,43 @@
 /*
  * GPIO configuration
  *
- * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
- *	Bit 0 (mask: 0x80000000): 1
+ * use CS1: Bit 0 (mask: 0x80000000):
+ *	   1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- *	00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
- *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
- *	      Use for REV200 STK52XX boards and FO300 boards. Do not use
- *	      with REV100 modules (because, there I2C1 is used as I2C bus)
- * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
- * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
- *	000 -> All PSC2 pins are GIOPs
- *	001 -> CAN1/2 on PSC2 pins
- *	       Use for REV100 STK52xx boards
- *	01x -> Use AC97
- * use PSC3: Bits 20-23 (mask: 0x00000f00)
- *	1100 -> UART/SPI (on FO300 board)
- * use PSC6:
- *   on STK52xx and FO300:
- *	use as UART. Pins PSC6_0 to PSC6_3 are used.
- *	Bits 9:11 (mask: 0x00700000):
- *	   101 -> PSC6 : Extended POST test is not available
- *   on MINI-FAP and TQM5200_IB:
- *	use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
- *	   000 -> PSC6 could not be used as UART, CODEC or IrDA
- *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
- *   tests.
+ *	  00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ *		SPI on PSC3 according to PSC3 setting. Use for CAM5200.
+ *	  01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ *		Use for REV200 STK52XX boards and FO300 boards. Do not use
+ *		with REV100 modules (because, there I2C1 is used as I2C bus).
+ * use ATA: Bits 6-7 (mask 0x03000000):
+ *	  00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
+ *		Use for CAM5200 board.
+ *	  01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
+ * use PSC6: Bits 9-11 (mask 0x00700000):
+ *	 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
+ *		UART, CODEC or IrDA.
+ *		GPIO on PSC6_3 is used in post_hotkeys_pressed() to
+ *		enable extended POST tests.
+ *		Use for MINI-FAP and TQM5200_IB boards.
+ *	 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
+ *		Extended POST test is not available.
+ *		Use for STK52xx, FO300 and CAM5200 boards.
+ * use PCI_DIS: Bit 16 (mask 0x00008000):
+ *	   1 -> disable PCI controller (on CAM5200 board).
+ * use USB: Bits 18-19 (mask 0x00003000):
+ *	  10 -> two UARTs (on FO300 and CAM5200).
+ * use PSC3: Bits 20-23 (mask: 0x00000f00):
+ *	0000 -> All PSC3 pins are GPIOs.
+ *	1100 -> UART/SPI (on FO300 board).
+ *	0100 -> UART (on CAM5200 board).
+ * use PSC2: Bits 25:27 (mask: 0x00000030):
+ *	 000 -> All PSC2 pins are GPIOs.
+ *	 100 -> UART (on CAM5200 board).
+ *	 001 -> CAN1/2 on PSC2 pins.
+ *	        Use for REV100 STK52xx boards
+ *	 01x -> Use AC97 (on FO300 board).
+ * use PSC1: Bits 29-31 (mask: 0x00000007):
+ *	 100 -> UART (on all boards).
  */
 #if defined (CONFIG_MINIFAP)
 # define CFG_GPS_PORT_CONFIG	0x91000004
@@ -519,6 +542,8 @@
 # endif
 #elif defined (CONFIG_FO300)
 # define CFG_GPS_PORT_CONFIG	0x91502c24
+#elif defined (CONFIG_CAM5200)
+# define CFG_GPS_PORT_CONFIG	0x8050A444
 #else  /* TMQ5200 Inbetriebnahme-Board */
 # define CFG_GPS_PORT_CONFIG	0x81000004
 #endif
@@ -613,6 +638,16 @@
 #define CFG_CS_BURST		0x00000000
 #define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
 
+#if defined(CONFIG_CAM5200)
+#define CFG_CS4_START		0xB0000000
+#define CFG_CS4_SIZE		0x00010000
+#define CFG_CS4_CFG		0x01019C10
+
+#define CFG_CS5_START		0xD0000000
+#define CFG_CS5_SIZE		0x01208000
+#define CFG_CS5_CFG		0x1414BF10
+#endif
+
 #define CFG_RESET_ADDRESS	0xff000000
 
 /*-----------------------------------------------------------------------
diff --git a/include/flash.h b/include/flash.h
index 84b48a9f2e7..d91589a6c02 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -209,6 +209,9 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define AMD_ID_GL064M_3 0x22012201	/* 3rd ID word for S29GL064M-R6 */
 #define AMD_ID_GL064MT_2 0x22102210	/* 2nd ID word for S29GL064M-R3 (top boot sector) */
 #define AMD_ID_GL064MT_3 0x22012201	/* 3rd ID word for S29GL064M-R3 (top boot sector) */
+#define AMD_ID_GL128N_2	0x22212221	/* 2nd ID word for S29GL128N */
+#define AMD_ID_GL128N_3	0x22012201	/* 3rd ID word for S29GL128N */
+
 
 #define AMD_ID_LV320B_2 0x221A221A	/* 2d ID word for AM29LV320MB at 0x38 */
 #define AMD_ID_LV320B_3 0x22002200	/* 3d ID word for AM29LV320MB at 0x3c */
@@ -417,6 +420,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define FLASH_FUJLV650	0x00D0		/* Fujitsu MBM 29LV650UE/651UE		*/
 #define FLASH_MT28S4M16LC 0x00E1	/* Micron MT28S4M16LC			*/
 #define FLASH_S29GL064M 0x00F0		/* Spansion S29GL064M-R6		*/
+#define FLASH_S29GL128N 0x00F1		/* Spansion S29GL128N			*/
 
 #define FLASH_UNKNOWN	0xFFFF		/* unknown flash type			*/
 
-- 
cgit v1.3.1


From 511d0c72b82aab9b807efde50fc9e390365f5ca1 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@atlas.denx.de>
Date: Mon, 9 Oct 2006 00:42:01 +0200
Subject: Coding style cleanup

---
 CHANGELOG                      |  2 ++
 board/Marvell/db64360/Makefile |  2 +-
 board/Marvell/db64460/Makefile |  2 +-
 board/amcc/sequoia/sequoia.c   | 72 +++++++++++++++++++++---------------------
 board/amcc/yucca/yucca.c       |  3 --
 board/dave/B2/Makefile         |  2 +-
 board/esd/cpci750/Makefile     |  2 +-
 board/evb64260/Makefile        |  2 +-
 board/ispan/Makefile           |  2 +-
 board/jse/Makefile             |  2 +-
 board/netstar/Makefile         |  2 +-
 board/sc520_spunk/Makefile     |  2 +-
 board/tqm5200/cam5200_flash.c  |  2 +-
 board/tqm834x/Makefile         |  2 +-
 common/lcd.c                   |  4 +--
 config.mk                      |  2 +-
 cpu/i386/Makefile              |  2 +-
 cpu/mpc5xxx/interrupts.c       |  2 +-
 cpu/mpc83xx/Makefile           |  2 +-
 cpu/ppc4xx/ndfc.c              | 24 +++++++-------
 cpu/ppc4xx/start.S             |  6 ++--
 drivers/serial.c               |  6 ++--
 drivers/sk98lin/Makefile       |  1 -
 include/common.h               |  2 +-
 lib_generic/Makefile           |  2 +-
 nand_spl/nand_boot.c           |  4 +--
 tools/Makefile                 |  2 +-
 tools/gdb/Makefile             |  2 +-
 28 files changed, 79 insertions(+), 81 deletions(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index e12d767276e..6e797d6c9aa 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Coding style cleanup
+
 * Add support for EP82xxM boards
   Patch by Aaron Sells, 20 Jun 2006
 
diff --git a/board/Marvell/db64360/Makefile b/board/Marvell/db64360/Makefile
index a084c894ae3..f983cd96b4b 100644
--- a/board/Marvell/db64360/Makefile
+++ b/board/Marvell/db64360/Makefile
@@ -1,7 +1,7 @@
 #
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# 
+#
 # (C) Copyright 2001
 # Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
 #
diff --git a/board/Marvell/db64460/Makefile b/board/Marvell/db64460/Makefile
index a084c894ae3..f983cd96b4b 100644
--- a/board/Marvell/db64460/Makefile
+++ b/board/Marvell/db64460/Makefile
@@ -1,7 +1,7 @@
 #
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# 
+#
 # (C) Copyright 2001
 # Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
 #
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index a8ba2c08319..ccf6f0c8039 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2006
  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -123,12 +123,12 @@ int board_early_init_f(void)
 
 	/* setup NAND FLASH */
 	mfsdr(SDR0_CUST0, sdr0_cust0);
-        sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
+	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
 		SDR0_CUST0_NDFC_ENABLE		|
 		SDR0_CUST0_NDFC_BW_8_BIT	|
 		SDR0_CUST0_NDFC_ARE_MASK	|
 		(0x80000000 >> (28 + CFG_NAND_CS));
-        mtsdr(SDR0_CUST0, sdr0_cust0);
+	mtsdr(SDR0_CUST0, sdr0_cust0);
 
 	return 0;
 }
@@ -216,38 +216,38 @@ int misc_init_r(void)
 #ifdef CONFIG_440EPX
 	if (act == NULL || strcmp(act, "hostdev") == 0)	{
 		/* SDR Setting */
-        	mfsdr(SDR0_PFC1, sdr0_pfc1);
-        	mfsdr(SDR0_USB0, usb2d0cr);
-        	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-        	mfsdr(SDR0_USB2H0CR, usb2h0cr);
+		mfsdr(SDR0_PFC1, sdr0_pfc1);
+		mfsdr(SDR0_USB0, usb2d0cr);
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mfsdr(SDR0_USB2H0CR, usb2h0cr);
 
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
-        	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
 
 		/* An 8-bit/60MHz interface is the only possible alternative
 		   when connecting the Device to the PHY */
-        	usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
-        	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
+		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
 
-        	/* To enable the USB 2.0 Device function through the UTMI interface */
-        	usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-        	usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;		/*1*/
+		/* To enable the USB 2.0 Device function through the UTMI interface */
+		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;		/*1*/
 
-        	sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-        	sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;		/*0*/
+		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;		/*0*/
 
-        	mtsdr(SDR0_PFC1, sdr0_pfc1);
-        	mtsdr(SDR0_USB0, usb2d0cr);
-        	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-        	mtsdr(SDR0_USB2H0CR, usb2h0cr);
+		mtsdr(SDR0_PFC1, sdr0_pfc1);
+		mtsdr(SDR0_USB0, usb2d0cr);
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mtsdr(SDR0_USB2H0CR, usb2h0cr);
 
 		/*clear resets*/
 		udelay (1000);
@@ -264,11 +264,11 @@ int misc_init_r(void)
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
 		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 
 		udelay (1000);
@@ -287,33 +287,33 @@ int misc_init_r(void)
 		/*-------------------PATCH-------------------------------*/
 
 		/* SDR Setting */
-        	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 		mfsdr(SDR0_USB2H0CR, usb2h0cr);
 		mfsdr(SDR0_USB0, usb2d0cr);
 		mfsdr(SDR0_PFC1, sdr0_pfc1);
 
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
-        	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;	/*0*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;		/*1*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;		/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;		/*0*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;		/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;		/*0*/
 
 		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
-        	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;		/*0*/
+		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;		/*0*/
 
 		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-        	usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;		/*0*/
+		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;		/*0*/
 
 		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-        	sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;		/*1*/
+		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;		/*1*/
 
-        	mtsdr(SDR0_USB2H0CR, usb2h0cr);
-        	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mtsdr(SDR0_USB2H0CR, usb2h0cr);
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 		mtsdr(SDR0_USB0, usb2d0cr);
 		mtsdr(SDR0_PFC1, sdr0_pfc1);
 
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index cd175265f0d..e9b34dd249a 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -958,7 +958,6 @@ int is_pci_host(struct pci_controller *hose)
 	return 1;
 }
 
-
 int yucca_pcie_card_present(int port)
 {
 	u16 reg;
@@ -1084,8 +1083,6 @@ void yucca_setup_pcie_fpga_endpoint(int port)
 		 (endpoint | in_be16((u16 *)FPGA_REG1C)));
 }
 
-
-
 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
 
 void pcie_setup_hoses(void)
diff --git a/board/dave/B2/Makefile b/board/dave/B2/Makefile
index 106025da1eb..1762f6f084c 100644
--- a/board/dave/B2/Makefile
+++ b/board/dave/B2/Makefile
@@ -1,7 +1,7 @@
 #
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# 
+#
 # (C) Copyright 2002
 # Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 # Marius Groeger <mgroeger@sysgo.de>
diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile
index 0dfec601ea8..2f61d94e88d 100644
--- a/board/esd/cpci750/Makefile
+++ b/board/esd/cpci750/Makefile
@@ -1,7 +1,7 @@
 #
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# 
+#
 # (C) Copyright 2001
 # Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
 #
diff --git a/board/evb64260/Makefile b/board/evb64260/Makefile
index b28372d818c..925844ccc4e 100644
--- a/board/evb64260/Makefile
+++ b/board/evb64260/Makefile
@@ -1,7 +1,7 @@
 #
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# 
+#
 # (C) Copyright 2001
 # Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
 #
diff --git a/board/ispan/Makefile b/board/ispan/Makefile
index 0c1cb0253ab..d0223b51ffc 100644
--- a/board/ispan/Makefile
+++ b/board/ispan/Makefile
@@ -1,7 +1,7 @@
 #
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# 
+#
 # Copyright (C) 2004 Arabella Software Ltd.
 # Yuli Barcohen <yuli@arabellasw.com>
 #
diff --git a/board/jse/Makefile b/board/jse/Makefile
index be6bd315cdf..edbfc3f776d 100644
--- a/board/jse/Makefile
+++ b/board/jse/Makefile
@@ -1,7 +1,7 @@
 #
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# 
+#
 # Copyright 2004 Picture Elements, Inc.
 # Stephen Williams <steve@icarus.com>
 #
diff --git a/board/netstar/Makefile b/board/netstar/Makefile
index b7c092d24f0..27d96d2baab 100644
--- a/board/netstar/Makefile
+++ b/board/netstar/Makefile
@@ -1,4 +1,4 @@
-# 
+#
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
diff --git a/board/sc520_spunk/Makefile b/board/sc520_spunk/Makefile
index 9958e802686..5e8c15d1eb7 100644
--- a/board/sc520_spunk/Makefile
+++ b/board/sc520_spunk/Makefile
@@ -1,7 +1,7 @@
 #
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# 
+#
 # (C) Copyright 2002
 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
 #
diff --git a/board/tqm5200/cam5200_flash.c b/board/tqm5200/cam5200_flash.c
index 85d310b77df..1a40633e569 100644
--- a/board/tqm5200/cam5200_flash.c
+++ b/board/tqm5200/cam5200_flash.c
@@ -46,7 +46,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
  * swapping is necessary within each 16 bit wide flash 'word'.
  *
  * This driver's task is to handle both flash devices: 32 bit TQM5200B
- * flash chip and 16 bit NIOS cpu flash chip. In the below 
+ * flash chip and 16 bit NIOS cpu flash chip. In the below
  * flash_addr_table table we use least significant address bit to mark
  * 16 bit flash bank and two sets of routines *_32 and *_16 to handle
  * specifics of both flashes.
diff --git a/board/tqm834x/Makefile b/board/tqm834x/Makefile
index 6991cfbf28a..24bd93f92b9 100644
--- a/board/tqm834x/Makefile
+++ b/board/tqm834x/Makefile
@@ -1,7 +1,7 @@
 #
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# 
+#
 # Copyright 2004 Freescale Semiconductor, Inc.
 #
 # See file CREDITS for list of people who contributed to this
diff --git a/common/lcd.c b/common/lcd.c
index d79350f2347..df31ca9b8c2 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -661,8 +661,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	 *  So, in case of Monochrome BMP we should align widths
 	 * on a byte boundary and convert them from Bit to Byte
 	 * units.
-	 *  Probably, PXA250 and MPC823 process 1bpp BMP images in 
-	 * their own ways, so make the converting to be MCC200 
+	 *  Probably, PXA250 and MPC823 process 1bpp BMP images in
+	 * their own ways, so make the converting to be MCC200
 	 * specific.
 	 */
 #if defined(CONFIG_MCC200)
diff --git a/config.mk b/config.mk
index 0f5d0f43d94..500fbcfe117 100644
--- a/config.mk
+++ b/config.mk
@@ -25,7 +25,7 @@
 
 ifneq ($(OBJTREE),$(SRCTREE))
 ifeq ($(CURDIR),$(SRCTREE))
-dir := 
+dir :=
 else
 dir := $(subst $(SRCTREE)/,,$(CURDIR))
 endif
diff --git a/cpu/i386/Makefile b/cpu/i386/Makefile
index cd46dea2c74..1245cf01081 100644
--- a/cpu/i386/Makefile
+++ b/cpu/i386/Makefile
@@ -1,7 +1,7 @@
 #
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# 
+#
 # (C) Copyright 2002
 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
 #
diff --git a/cpu/mpc5xxx/interrupts.c b/cpu/mpc5xxx/interrupts.c
index 7b5cb8be4e2..beeb222636e 100644
--- a/cpu/mpc5xxx/interrupts.c
+++ b/cpu/mpc5xxx/interrupts.c
@@ -32,7 +32,7 @@
  *
  * Based on (well, mostly copied from) the code from the 2.4 kernel by
  * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
- * 
+ *
  * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
  * Copyright (C) 2003 Montavista Software, Inc
  */
diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
index f3fa6fd93ab..85e32e16302 100644
--- a/cpu/mpc83xx/Makefile
+++ b/cpu/mpc83xx/Makefile
@@ -1,7 +1,7 @@
 #
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# 
+#
 # Copyright 2004 Freescale Semiconductor, Inc.
 #
 # See file CREDITS for list of people who contributed to this
diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
index c255f93e6bb..183ab5ef168 100644
--- a/cpu/ppc4xx/ndfc.c
+++ b/cpu/ppc4xx/ndfc.c
@@ -65,8 +65,8 @@ static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
 
 static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
 {
-        struct nand_chip *this = mtdinfo->priv;
-        ulong base = (ulong) this->IO_ADDR_W;
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) this->IO_ADDR_W;
 
 	if (hwctl & 0x1)
 		out8(base + NDFC_CMD, byte);
@@ -78,16 +78,16 @@ static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
 
 static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
 {
-        struct nand_chip *this = mtdinfo->priv;
-        ulong base = (ulong) this->IO_ADDR_W;
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) this->IO_ADDR_W;
 
 	return (in8(base + NDFC_DATA));
 }
 
 static int ndfc_dev_ready(struct mtd_info *mtdinfo)
 {
-        struct nand_chip *this = mtdinfo->priv;
-        ulong base = (ulong) this->IO_ADDR_W;
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) this->IO_ADDR_W;
 
 	while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY))
 		;
@@ -110,8 +110,8 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo)
  */
 static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
 {
-        struct nand_chip *this = mtdinfo->priv;
-        ulong base = (ulong) this->IO_ADDR_W;
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) this->IO_ADDR_W;
 	uint32_t *p = (uint32_t *) buf;
 
 	for(;len > 0; len -= 4)
@@ -120,8 +120,8 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
 
 static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 {
-        struct nand_chip *this = mtdinfo->priv;
-        ulong base = (ulong) this->IO_ADDR_W;
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) this->IO_ADDR_W;
 	uint32_t *p = (uint32_t *) buf;
 
 	for(; len > 0; len -= 4)
@@ -130,8 +130,8 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
 
 static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 {
-        struct nand_chip *this = mtdinfo->priv;
-        ulong base = (ulong) this->IO_ADDR_W;
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) this->IO_ADDR_W;
 	uint32_t *p = (uint32_t *) buf;
 
 	for(; len > 0; len -= 4)
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 5a1ab386b18..3f2931411f3 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -173,9 +173,9 @@
 
 /**************************************************************************/
 _start_440:
-        /*--------------------------------------------------------------------+
-        | 440EPX BUP Change - Hardware team request
-        +--------------------------------------------------------------------*/
+	/*--------------------------------------------------------------------+
+	| 440EPX BUP Change - Hardware team request
+	+--------------------------------------------------------------------*/
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	sync
 	nop
diff --git a/drivers/serial.c b/drivers/serial.c
index 8d1ae96bf85..76425d87901 100644
--- a/drivers/serial.c
+++ b/drivers/serial.c
@@ -39,7 +39,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #if !defined(CONFIG_CONS_INDEX)
 #if defined (CONFIG_SERIAL_MULTI)
 /*   with CONFIG_SERIAL_MULTI we might have no console
- *  on these devices 
+ *  on these devices
  */
 #else
 #error	"No console index specified."
@@ -238,7 +238,7 @@ serial_putc(const char c)
 #endif
 
 #if defined(CONFIG_SERIAL_MULTI)
-static inline void 
+static inline void
 serial_putc_raw_dev(unsigned int dev_index,const char c)
 {
 	_serial_putc_raw(c,dev_index);
@@ -310,7 +310,7 @@ serial_setbrg(void)
 #if defined(CONFIG_SERIAL_MULTI)
 
 DECLARE_ESERIAL_FUNCTIONS(1);
-struct serial_device eserial1_device = 
+struct serial_device eserial1_device =
 	INIT_ESERIAL_STRUCTURE(1,"eserial0","EUART1");
 DECLARE_ESERIAL_FUNCTIONS(2);
 struct serial_device eserial2_device =
diff --git a/drivers/sk98lin/Makefile b/drivers/sk98lin/Makefile
index ac21e02133f..76c750cdb86 100644
--- a/drivers/sk98lin/Makefile
+++ b/drivers/sk98lin/Makefile
@@ -104,4 +104,3 @@ include $(SRCTREE)/rules.mk
 sinclude $(obj).depend
 
 #########################################################################
-
diff --git a/include/common.h b/include/common.h
index bee2fb70224..a873fa99b7a 100644
--- a/include/common.h
+++ b/include/common.h
@@ -110,7 +110,7 @@ typedef volatile unsigned char	vu_char;
 #endif	/* DEBUG */
 
 #define BUG() do { \
-        printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
+	printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
 	panic("BUG!"); \
 } while (0)
 #define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
diff --git a/lib_generic/Makefile b/lib_generic/Makefile
index fcd43c676f7..a05b3552de3 100644
--- a/lib_generic/Makefile
+++ b/lib_generic/Makefile
@@ -29,7 +29,7 @@ COBJS	= bzlib.o bzlib_crctable.o bzlib_decompress.o \
 	  bzlib_randtable.o bzlib_huffman.o \
 	  crc32.o ctype.o display_options.o ldiv.o \
 	  string.o vsprintf.o zlib.o
-	  
+
 SRCS 	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 
diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c
index 21abb09e39b..a136fb70745 100644
--- a/nand_spl/nand_boot.c
+++ b/nand_spl/nand_boot.c
@@ -34,7 +34,7 @@ extern int jump_to_uboot(ulong addr);
 
 static int nand_is_bad_block(struct mtd_info *mtd, int block)
 {
-        struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd->priv;
 	int page_addr = block * CFG_NAND_PAGE_COUNT;
 
 	/* Begin command latch cycle */
@@ -73,7 +73,7 @@ static int nand_is_bad_block(struct mtd_info *mtd, int block)
 
 static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
 {
-        struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd->priv;
 	int page_addr = page + block * CFG_NAND_PAGE_COUNT;
 	int i;
 
diff --git a/tools/Makefile b/tools/Makefile
index 606f0240376..6177f902716 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -108,7 +108,7 @@ endif
 include $(TOPDIR)/config.mk
 
 # now $(obj) is defined
-SRCS	:= $(addprefix $(obj),$(OBJ_LINKS:.o=.c)) $(OBJ_FILES:.o=.c) 
+SRCS	:= $(addprefix $(obj),$(OBJ_LINKS:.o=.c)) $(OBJ_FILES:.o=.c)
 BINS	:= $(addprefix $(obj),$(BIN_FILES))
 
 #
diff --git a/tools/gdb/Makefile b/tools/gdb/Makefile
index dbcb91f5ed7..632103d4538 100644
--- a/tools/gdb/Makefile
+++ b/tools/gdb/Makefile
@@ -31,7 +31,7 @@ BINS	= gdbsend gdbcont
 COBJS	= gdbsend.o gdbcont.o error.o remote.o serial.o
 
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SRCS	:= $(COBJS:.o=.c) 
+SRCS	:= $(COBJS:.o=.c)
 BINS	:= $(addprefix $(obj),$(BINS))
 
 #
-- 
cgit v1.3.1


From 7ce343e49993341f2cdd559e0c44ad7507f71eb7 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@atlas.denx.de>
Date: Mon, 9 Oct 2006 00:48:57 +0200
Subject: Add missing files for EP82xxM boards Patch by Aaron Sells, 20 Jun
 2006

---
 board/ep82xxm/Makefile    |  49 ++++++
 board/ep82xxm/config.mk   |  26 +++
 board/ep82xxm/ep82xxm.c   | 291 ++++++++++++++++++++++++++++++++++
 board/ep82xxm/u-boot.lds  | 125 +++++++++++++++
 include/configs/ep82xxm.h | 395 ++++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 886 insertions(+)
 create mode 100644 board/ep82xxm/Makefile
 create mode 100644 board/ep82xxm/config.mk
 create mode 100644 board/ep82xxm/ep82xxm.c
 create mode 100644 board/ep82xxm/u-boot.lds
 create mode 100644 include/configs/ep82xxm.h

(limited to 'include')

diff --git a/board/ep82xxm/Makefile b/board/ep82xxm/Makefile
new file mode 100644
index 00000000000..3d5490aa58b
--- /dev/null
+++ b/board/ep82xxm/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ep82xxm/config.mk b/board/ep82xxm/config.mk
new file mode 100644
index 00000000000..da039e21b3e
--- /dev/null
+++ b/board/ep82xxm/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# EP82xxM series boards by Embedded Planet
+
+TEXT_BASE = 0xFFF00000
diff --git a/board/ep82xxm/ep82xxm.c b/board/ep82xxm/ep82xxm.c
new file mode 100644
index 00000000000..35e644df8c3
--- /dev/null
+++ b/board/ep82xxm/ep82xxm.c
@@ -0,0 +1,291 @@
+/*
+ * Copyright (C) 2006 Embedded Planet, LLC.
+ *
+ * Support for Embedded Planet EP82xxM boards.
+ * Tested on EP82xxM (MPC8270).
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+#include <asm/m8260_pci.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#endif
+#include <miiphy.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CFG_FCC2 1
+#define CFG_FCC3 1
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A */
+    {	/*	     conf      ppar psor pdir podr pdat */
+	/* PA31 */ { 0,          0,   0,   0,   0,   1 }, /* PA31	     */
+	/* PA30 */ { 0,          0,   0,   0,   0,   1 }, /* PA30	     */
+	/* PA29 */ { 0,          0,   0,   0,   0,   1 }, /* PA29	     */
+	/* PA28 */ { 0,          0,   0,   0,   0,   1 }, /* PA28	     */
+	/* PA27 */ { 0,          0,   0,   0,   0,   1 }, /* PA27	     */
+	/* PA26 */ { 0,          0,   0,   0,   0,   1 }, /* PA26	     */
+	/* PA25 */ { 0,          0,   0,   0,   0,   1 }, /* PA25            */
+	/* PA24 */ { 0,          0,   0,   0,   0,   1 }, /* PA24            */
+	/* PA23 */ { 0,          0,   0,   0,   0,   1 }, /* PA23            */
+	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22            */
+	/* PA21 */ { 0,          0,   0,   0,   0,   1 }, /* PA21	     */
+	/* PA20 */ { 0,          0,   0,   0,   0,   1 }, /* PA20 	     */
+	/* PA19 */ { 0,          0,   0,   0,   0,   1 }, /* PA19	     */
+	/* PA18 */ { 0,          0,   0,   0,   0,   1 }, /* PA18	     */
+	/* PA17 */ { 0,          0,   0,   0,   0,   1 }, /* PA17  	     */
+	/* PA16 */ { 0,          0,   0,   0,   0,   1 }, /* PA16	     */
+	/* PA15 */ { 0,          0,   0,   0,   0,   1 }, /* PA15	     */
+	/* PA14 */ { 0,          0,   0,   0,   0,   1 }, /* PA14	     */
+	/* PA13 */ { 0,          0,   0,   0,   0,   1 }, /* PA13            */
+	/* PA12 */ { 0,          0,   0,   0,   0,   1 }, /* PA12            */
+	/* PA11 */ { 0,          0,   0,   0,   0,   1 }, /* PA11            */
+	/* PA10 */ { 0,          0,   0,   0,   0,   1 }, /* PA10            */
+	/* PA9  */ { 1,          1,   0,   1,   0,   1 }, /* SMC2 TxD        */
+	/* PA8  */ { 1,          1,   0,   0,   0,   1 }, /* SMC2 RxD        */
+	/* PA7  */ { 0,          0,   0,   0,   0,   1 }, /* PA7             */
+	/* PA6  */ { 0,          0,   0,   0,   0,   1 }, /* PA6             */
+	/* PA5  */ { 0,          0,   0,   0,   0,   1 }, /* PA5             */
+	/* PA4  */ { 0,          0,   0,   0,   0,   1 }, /* PA4             */
+	/* PA3  */ { 0,          0,   0,   0,   0,   1 }, /* PA3             */
+	/* PA2  */ { 0,          0,   0,   0,   0,   1 }, /* PA2             */
+	/* PA1  */ { 0,          0,   0,   0,   0,   1 }, /* PA1             */
+	/* PA0  */ { 0,          0,   0,   0,   0,   1 }  /* PA0             */
+    },
+
+    /* Port B */
+    {   /*	     conf       ppar psor pdir podr pdat */
+	/* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_DIV     */
+	/* PB16 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_ERR     */
+	/* PB15 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_ERR     */
+	/* PB14 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_EN      */
+	/* PB13 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:COL	     */
+	/* PB12 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:CRS        */
+	/* PB11 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD        */
+	/* PB10 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD        */
+	/* PB9  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD        */
+	/* PB8  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD        */
+	/* PB7  */ { 0,		 0,   0,   0,   0,   0 }, /* PB7             */
+	/* PB6  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD        */
+	/* PB5  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD        */
+	/* PB4  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD        */
+	/* PB3  */ { 0,        	 0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    },
+
+    /* Port C */
+    {   /*	     conf	ppar psor pdir podr pdat */
+	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
+	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
+	/* PC29 */ { 1,          1,   1,   0,   0,   0 }, /* SCC1 CTS#       */
+	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
+	/* PC27 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3: TXD[0]    */
+	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
+	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
+	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
+	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
+	/* PC22 */ { 0,  	 0,   0,   0,   0,   0 }, /* PC22	     */
+	/* PC21 */ { 0,   	 0,   0,   0,   0,   0 }, /* PC21	     */
+	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
+	/* PC19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* RxClk (CLK13)   */
+	/* PC18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* TxClk (CLK14)   */
+	/* PC17 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* RxClk (CLK15)   */
+	/* PC16 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* TxClk (CLK16)   */
+	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
+	/* PC14 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 CD#        */
+	/* PC13 */ { 1,          1,   0,   0,   0,   0 }, /* SCC2 CTS#       */
+	/* PC12 */ { 1,          1,   0,   0,   0,   0 }, /* SCC2 CD#        */
+	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
+	/* PC10 */ { 1,          1,   0,   0,   0,   0 }, /* SCC3 CD#        */
+	/* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9             */
+	/* PC8  */ { 1,          1,   1,   0,   0,   0 }, /* SCC3 CTS#       */
+	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
+	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
+	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5             */
+	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4             */
+	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
+	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
+	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
+	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
+    },
+
+    /* Port D */
+    {   /*	     conf      ppar psor pdir podr pdat */
+	/* PD31 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 RXD        */
+	/* PD30 */ { 1,          1,   1,   1,   0,   1 }, /* SCC1 TXD        */
+	/* PD29 */ { 1,          1,   0,   1,   0,   0 }, /* SCC1 RTS#       */
+	/* PD28 */ { 1,          1,   0,   0,   0,   0 }, /* SCC2 RXD        */
+	/* PD27 */ { 1,          1,   0,   1,   0,   0 }, /* SCC2 TXD        */
+	/* PD26 */ { 1,          1,   0,   1,   0,   0 }, /* SCC2 RTS#       */
+	/* PD25 */ { 1,          1,   0,   0,   0,   0 }, /* SCC3 RXD        */
+	/* PD24 */ { 1,          1,   0,   1,   0,   0 }, /* SCC3 TXD        */
+	/* PD23 */ { 1,          1,   0,   1,   0,   0 }, /* SCC3 RTS#       */
+	/* PD22 */ { 0,          0,   0,   0,   0,   1 }, /* PD22            */
+	/* PD21 */ { 0,          0,   0,   0,   0,   1 }, /* PD21            */
+	/* PD20 */ { 0,          0,   0,   0,   0,   1 }, /* PD20            */
+	/* PD19 */ { 0,          0,   0,   0,   0,   1 }, /* PD19            */
+	/* PD18 */ { 0,          0,   0,   0,   0,   1 }, /* PD18            */
+	/* PD17 */ { 0,          0,   0,   0,   0,   1 }, /* PD17            */
+	/* PD16 */ { 0,          0,   0,   0,   0,   1 }, /* PD16            */
+	/* PD15 */ { 1,          1,   1,   0,   1,   1 }, /* I2C SDA         */
+	/* PD14 */ { 1,          1,   1,   0,   1,   1 }, /* I2C SCL         */
+	/* PD13 */ { 0,          0,   0,   0,   0,   1 }, /* PD13            */
+	/* PD12 */ { 0,          0,   0,   0,   0,   1 }, /* PD12            */
+	/* PD11 */ { 0,          0,   0,   0,   0,   1 }, /* PD11            */
+	/* PD10 */ { 0,          0,   0,   0,   0,   1 }, /* PD10            */
+	/* PD9  */ { 1,          1,   0,   1,   0,   1 }, /* SMC1 TxD        */
+	/* PD8  */ { 1,          1,   0,   0,   0,   1 }, /* SMC1 RxD        */
+	/* PD7  */ { 1,          1,   0,   0,   0,   1 }, /* SMC1 SMSYN      */
+	/* PD6  */ { 0,          0,   0,   0,   0,   1 }, /* PD6             */
+	/* PD5  */ { 0,          0,   0,   0,   0,   1 }, /* PD5             */
+	/* PD4  */ { 0,          0,   0,   0,   0,   1 }, /* PD4             */
+	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    }
+};
+
+#ifdef CONFIG_PCI
+typedef struct pci_ic_s {
+	unsigned long pci_int_stat;
+	unsigned long pci_int_mask;
+}pci_ic_t;
+#endif
+
+int board_early_init_f (void)
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+	bcsr[4] |= 0x30; /* Turn the LEDs off */
+
+#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
+	bcsr[6] |= 0x10;
+#endif
+#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
+	bcsr[7] |= 0x10;
+#endif
+
+#if CFG_FCC3
+	bcsr[8] |= 0xC0;
+#endif /* CFG_FCC3 */
+#if CFG_FCC2
+	bcsr[8] |= 0x30;
+#endif /* CFG_FCC2 */
+
+	return 0;
+}
+
+long int initdram(int board_type)
+{
+	/* Size in MB of SDRAM populated on board*/
+	long int msize = 256;
+
+#ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE;
+	uchar c = 0xFF;
+	uint psdmr = CFG_PSDMR;
+	int i;
+
+	unsigned char           ramtmp;
+    	unsigned char           *ramptr1 = (unsigned char *)0x00000110;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+
+udelay(400);
+
+	/* Initialise 60x bus SDRAM */
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_or1  = CFG_SDRAM_OR;
+	memctl->memc_br1  = CFG_SDRAM_BR;
+	memctl->memc_psdmr = psdmr;
+
+udelay(400);
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+	ramtmp = *ramptr1;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+	for (i = 0; i < 8; i++) {
+		memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+	}
+	ramtmp = *ramptr1;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
+	*ramptr1  = 0xFF;
+	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
+#endif /* !CFG_RAMBOOT */
+
+	/* Return total 60x bus SDRAM size */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+	puts("Board: ");
+	switch (bcsr[0]) {
+	case 0x0A:
+		printf("EP82xxM 1.0 CPLD revision %d\n", bcsr[1]);
+		break;
+	default:
+		printf("unknown: ID=%02X\n", bcsr[0]);
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
diff --git a/board/ep82xxm/u-boot.lds b/board/ep82xxm/u-boot.lds
new file mode 100644
index 00000000000..18c4b46f47b
--- /dev/null
+++ b/board/ep82xxm/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
new file mode 100644
index 00000000000..5d7bed611a0
--- /dev/null
+++ b/include/configs/ep82xxm.h
@@ -0,0 +1,395 @@
+/*
+ * Copyright (C) 2006 Embedded Planet, LLC.
+ *
+ * U-Boot configuration for Embedded Planet EP82xxM boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC8260
+#define CPU_ID_STR		"MPC8270"
+
+#define CONFIG_EP82XXM	/* Embedded Planet EP82xxM H 1.0 board /*
+			/* 256MB SDRAM / 64MB FLASH */
+
+#undef DEBUG
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f */
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
+#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
+#undef	CONFIG_CONS_NONE		/* It's not on external UART */
+#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
+
+#define CFG_BCSR		0xFA000000
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CFG_CMD_NET must
+ * be removed from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
+#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
+#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
+
+#define CONFIG_NET_MULTI
+
+#define CONFIG_ETHER_ON_FCC2
+#define CONFIG_ETHER_ON_FCC3
+
+#define CFG_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
+#define CFG_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#define CONFIG_MII			/* MII PHY management        */
+#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
+
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT		0	/* Not used - implemented in BCSR */
+#define MDIO_ACTIVE		(*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
+#define MDIO_TRISTATE		(*(vu_char *)(CFG_BCSR + 8) |= 0x04)
+#define MDIO_READ		(*(vu_char *)(CFG_BCSR + 8) & 1)
+
+#define MDIO(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
+				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFE
+
+#define MDC(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
+				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFD
+
+#define MIIDELAY		udelay(1)
+
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN	66000000 /* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL   \
+				| CFG_CMD_DHCP    \
+				| CFG_CMD_ECHO    \
+				| CFG_CMD_I2C     \
+				| CFG_CMD_IMMAP   \
+				| CFG_CMD_MII     \
+				| CFG_CMD_PING    \
+				| CFG_CMD_DATE    \
+				| CFG_CMD_DTT	  \
+				| CFG_CMD_EEPROM  \
+				| CFG_CMD_PCI	  \
+				| CFG_CMD_DIAG	  \
+				)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_ETHADDR		00:10:EC:00:88:65
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:10:EC:80:88:65
+#define CONFIG_IPADDR		10.0.0.245
+#define CONFIG_HOSTNAME		EP82xxM
+#define CONFIG_SERVERIP		10.0.0.26
+#define CONFIG_GATEWAYIP	10.0.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CFG_ENV_IN_OWN_SECT	1
+#define CFG_AUTO_COMPLETE
+#define	CONFIG_EXTRA_ENV_SETTINGS	"ethprime=FCC3 ETHERNET"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	1	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"ep82xxm=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0xFC000000
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector in flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+/* EEPROM Configuration */
+#define CFG_EEPROM_SIZE	0x1000
+#define CFG_I2C_EEPROM_ADDR	0x54
+#define CFG_I2C_EEPROM_ADDR_LEN	1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE		0x200	    /* Size of Environment vars */
+#define CFG_ENV_OFFSET		0x0
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+/* RTC Configuration */
+#define CONFIG_RTC_M41T11	1 	/* uses a M41T81 */
+#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_M41T11_BASE_YEAR	1900
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75		1
+#define CONFIG_DTT_SENSORS	{0}
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define	CFG_DTT_HYSTERESIS	3
+
+/*-----------------------------------------------------------------------
+ * NVRAM Configuration
+ *-----------------------------------------------------------------------
+ */
+#define CFG_NVRAM_BASE_ADDR	0xFA080000
+#define CFG_NVRAM_SIZE		(128*1024)-16
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CONFIG_PCI_BOOTDELAY	0
+
+/* PCI Memory map (if different from default map */
+#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
+#define CFG_PCI_SLV_MEM_BUS		0x00000000	/* PCI base */
+#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+				 PICMR_PREFETCH_EN)
+
+/*
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
+ * these windows.
+ */
+
+/*
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
+#define CFG_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
+#define	CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CFG_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
+#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/*
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
+#define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
+#define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
+#define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
+#define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
+
+/*
+ * Master window that allows the CPU to access PCI IO space.
+ * This window will be setup with the first set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
+#define CFG_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
+#define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
+#define CFG_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
+#define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
+
+
+/* PCIBR0 - for PCI IO*/
+#define CFG_PCI_MSTR0_LOCAL		CFG_PCI_MSTR_IO_LOCAL		/* Local base */
+#define CFG_PCIMSK0_MASK		~(CFG_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
+/* PCIBR1 - prefetch and non-prefetch regions joined together */
+#define CFG_PCI_MSTR1_LOCAL		CFG_PCI_MSTR_MEM_LOCAL
+#define CFG_PCIMSK1_MASK		~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
+
+
+#define	CFG_DIRECT_FLASH_TFTP
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
+#define CFG_JFFS2_FIRST_SECTOR  0
+#define CFG_JFFS2_LAST_SECTOR   62
+#define CFG_JFFS2_SORT_FRAGMENTS
+#define CFG_JFFS_CUSTOM_PART
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
+#define CFG_I2C_SPEED		100000	/* I2C speed			*/
+#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+#endif /* CFG_CMD_I2C */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(512 << 10)	/* Reserve 256KB for Monitor */
+
+#define CFG_DEFAULT_IMMR	0x00010000
+#define CFG_IMMR		0xF0000000
+
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/* Hard reset configuration word */
+#define CFG_HRCW_MASTER		0 /*0x1C800641*/  /* Not used - provided by CPLD */
+/* No slaves */
+#define CFG_HRCW_SLAVE1 	0
+#define CFG_HRCW_SLAVE2 	0
+#define CFG_HRCW_SLAVE3 	0
+#define CFG_HRCW_SLAVE4 	0
+#define CFG_HRCW_SLAVE5 	0
+#define CFG_HRCW_SLAVE6 	0
+#define CFG_HRCW_SLAVE7 	0
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot                  */
+
+#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+
+#define CFG_HID2		0
+
+#define CFG_SIUMCR		0x02610000
+#define CFG_SYPCR		0xFFFF0689
+#define CFG_BCR			0x8080E000
+#define CFG_SCCR		0x00000001
+
+#define CFG_RMR			0
+#define CFG_TMCNTSC		0x000000C3
+#define CFG_PISCR		0x00000083
+#define CFG_RCCR		0
+
+#define CFG_MPTPR		0x0A00
+#define CFG_PSDMR		0xC432246E
+#define CFG_PSRT		0x32
+
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_BR		(CFG_SDRAM_BASE | 0x00000041)
+#define CFG_SDRAM_OR		0xF0002900
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00001801)
+#define CFG_OR0_PRELIM		0xFC000882
+#define CFG_BR4_PRELIM		(CFG_BCSR | 0x00001001)
+#define CFG_OR4_PRELIM		0xFFF00050
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#endif /* __CONFIG_H */
-- 
cgit v1.3.1


From 1a1b7374b89a04737c76948b00207b56a1bb37b6 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 9 Oct 2006 12:55:38 +0200
Subject: Define IH_CPU_AVR32 Make it possible to generate AVR32 uImage files
 with mkimage and make cmd_bootm recognize them. Patch by Haavard Skinnemoen,
 22 Sep 2006

---
 CHANGELOG          | 5 +++++
 common/cmd_bootm.c | 3 +++
 include/image.h    | 1 +
 tools/mkimage.c    | 1 +
 4 files changed, 10 insertions(+)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index b6ba66d09ce..e3ab62138dd 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,11 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Define IH_CPU_AVR32
+  Make it possible to generate AVR32 uImage files with mkimage and
+  make cmd_bootm recognize them.
+  Patch by Haavard Skinnemoen, 22 Sep 2006
+
 * Make bootp implementation RFC3046 compliant
   Patch by Joakim Larsson, 27 Jun 2006
 
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index fdf7180a19a..2168e6737a0 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -260,6 +260,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (hdr->ih_arch != IH_CPU_NIOS2)
 #elif defined(__blackfin__)
 	if (hdr->ih_arch != IH_CPU_BLACKFIN)
+#elif defined(__avr32__)
+	if (hdr->ih_arch != IH_CPU_AVR32)
 #else
 # error Unknown CPU type
 #endif
@@ -1236,6 +1238,7 @@ print_type (image_header_t *hdr)
 	case IH_CPU_INVALID:	arch = "Invalid CPU";		break;
 	case IH_CPU_ALPHA:	arch = "Alpha";			break;
 	case IH_CPU_ARM:	arch = "ARM";			break;
+	case IH_CPU_AVR32:	arch = "AVR32";			break;
 	case IH_CPU_I386:	arch = "Intel x86";		break;
 	case IH_CPU_IA64:	arch = "IA64";			break;
 	case IH_CPU_MIPS:	arch = "MIPS";			break;
diff --git a/include/image.h b/include/image.h
index 139df0b2d1e..d9f2d461a5f 100644
--- a/include/image.h
+++ b/include/image.h
@@ -76,6 +76,7 @@
 #define IH_CPU_MICROBLAZE	14	/* MicroBlaze   */
 #define IH_CPU_NIOS2		15	/* Nios-II	*/
 #define IH_CPU_BLACKFIN		16	/* Blackfin	*/
+#define IH_CPU_AVR32		17	/* AVR32	*/
 
 /*
  * Image Types
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 60aac79f234..5f3634de426 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -94,6 +94,7 @@ table_entry_t arch_name[] = {
     {	IH_CPU_SPARC,		"sparc",	"SPARC",	},
     {	IH_CPU_SPARC64,		"sparc64",	"SPARC 64 Bit",	},
     {	IH_CPU_BLACKFIN,	"blackfin",	"Blackfin",	},
+    {	IH_CPU_AVR32,		"avr32",	"AVR32",	},
     {	-1,			"",		"",		},
 };
 
-- 
cgit v1.3.1


From 2255b2d2044d434463eb2661e18018e50f1643d9 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Tue, 10 Oct 2006 12:36:02 +0200
Subject: * Several improvements to the new NAND subsystem:   - JFFS2 related
 commands implemented in mtd-utils style   - Support for bad blocks   - Bad
 block testing commands   - NAND lock commands   Please take a look at
 doc/README.nand for more details   Patch by Guido Classen, 10 Oct 2006

---
 CHANGELOG                |   8 +
 common/cmd_nand.c        | 226 ++++++++++--
 doc/README.nand          |  44 +++
 drivers/nand/Makefile    |   2 +-
 drivers/nand/nand_util.c | 869 +++++++++++++++++++++++++++++++++++++++++++++++
 include/nand.h           |  57 ++++
 lib_generic/crc32.c      |   4 +-
 7 files changed, 1183 insertions(+), 27 deletions(-)
 create mode 100644 drivers/nand/nand_util.c

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index a2ea35d68e3..9ed65bdbfe4 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,14 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Several improvements to the new NAND subsystem:
+  - JFFS2 related commands implemented in mtd-utils style
+  - Support for bad blocks
+  - Bad block testing commands
+  - NAND lock commands
+  Please take a look at doc/README.nand for more details
+  Patch by Guido Classen, 10 Oct 2006
+
 * Define IH_CPU_AVR32
   Make it possible to generate AVR32 uImage files with mkimage and
   make cmd_bootm recognize them.
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 21adb1b4786..274ef0b9938 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -135,11 +135,16 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	ulong addr, off, size;
 	char *cmd, *s;
 	nand_info_t *nand;
+	int quiet = 0;
+	const char *quiet_str = getenv("quiet");
 
 	/* at least two arguments please */
 	if (argc < 2)
 		goto usage;
 
+	if (quiet_str)
+		quiet = simple_strtoul(quiet_str, NULL, 0) != 0;
+
 	cmd = argv[1];
 
 	if (strcmp(cmd, "info") == 0) {
@@ -178,7 +183,10 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 	if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 &&
 	    strncmp(cmd, "dump", 4) != 0 &&
-	    strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0)
+	    strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 &&
+	    strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 &&
+	    strcmp(cmd, "biterr") != 0 &&
+	    strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 )
 		goto usage;
 
 	/* the following commands operate on the current device */
@@ -197,14 +205,64 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 		return 0;
 	}
 
-	if (strcmp(cmd, "erase") == 0) {
-		arg_off_size(argc - 2, argv + 2, &off, &size, nand->size);
-		if (off == 0 && size == 0)
-			return 1;
+	if (strcmp(cmd, "erase") == 0 || strcmp(cmd, "scrub") == 0) {
+		nand_erase_options_t opts;
+		int clean = argc >= 3 && !strcmp("clean", argv[2]);
+		int rest_argc = argc - 2;
+		char **rest_argv = argv + 2;
+		int scrub = !strcmp(cmd, "scrub");
+
+		if (clean) {
+			rest_argc--;
+			rest_argv++;
+		}
+
+		if (rest_argc == 0) {
 
-		printf("\nNAND erase: device %d offset 0x%x, size 0x%x ",
-		       nand_curr_device, off, size);
-		ret = nand_erase(nand, off, size);
+			printf("\nNAND %s: device %d whole chip\n",
+			       cmd,
+			       nand_curr_device);
+
+			off = size = 0;
+		} else {
+			arg_off_size(rest_argc, rest_argv, &off, &size,
+				     nand->size);
+
+			if (off == 0 && size == 0)
+				return 1;
+
+			printf("\nNAND %s: device %d offset 0x%x, size 0x%x\n",
+			       cmd, nand_curr_device, off, size);
+		}
+
+		memset(&opts, 0, sizeof(opts));
+		opts.offset = off;
+		opts.length = size;
+		opts.jffs2  = clean;
+		opts.quiet  = quiet;
+
+		if (scrub) {
+			printf("Warning: "
+			       "scrub option will erase all factory set "
+			       "bad blocks!\n"
+			       "	 "
+			       "There is no reliable way to recover them.\n"
+			       "	 "
+			       "Use this command only for testing purposes "
+			       "if you\n"
+			       "	 "
+			       "are shure of what you are doing!\n"
+			       "\nReally scrub this NAND flash? <y/N>\n"
+				);
+
+			if (getc() == 'y' && getc() == '\r') {
+				opts.scrub = 1;
+			} else {
+				printf("scrub aborted\n");
+				return -1;
+			}
+		}
+		ret = nand_erase_opts(nand, &opts);
 		printf("%s\n", ret ? "ERROR" : "OK");
 
 		return ret == 0 ? 0 : 1;
@@ -228,37 +286,153 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 	/* read write */
 	if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) {
+		int read;
+
 		if (argc < 4)
 			goto usage;
-/*
-		s = strchr(cmd, '.');
-		clean = CLEAN_NONE;
-		if (s != NULL) {
-			if (strcmp(s, ".jffs2") == 0 || strcmp(s, ".e") == 0
-			    || strcmp(s, ".i"))
-				clean = CLEAN_JFFS2;
-		}
-*/
+
 		addr = (ulong)simple_strtoul(argv[2], NULL, 16);
 
 		arg_off_size(argc - 3, argv + 3, &off, &size, nand->size);
 		if (off == 0 && size == 0)
 			return 1;
 
-		i = strncmp(cmd, "read", 4) == 0;	/* 1 = read, 0 = write */
+		read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
 		printf("\nNAND %s: device %d offset %u, size %u ... ",
-		       i ? "read" : "write", nand_curr_device, off, size);
+		       read ? "read" : "write", nand_curr_device, off, size);
 
-		if (i)
+		s = strchr(cmd, '.');
+		if (s != NULL &&
+		    (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i"))) {
+			if (read) {
+				/* read */
+				nand_read_options_t opts;
+				memset(&opts, 0, sizeof(opts));
+				opts.buffer	= (u_char*) addr;
+				opts.length	= size;
+				opts.offset	= off;
+				opts.quiet      = quiet;
+				ret = nand_read_opts(nand, &opts);
+			} else {
+				/* write */
+				nand_write_options_t opts;
+				memset(&opts, 0, sizeof(opts));
+				opts.buffer	= (u_char*) addr;
+				opts.length	= size;
+				opts.offset	= off;
+				/* opts.forcejffs2 = 1; */
+				opts.pad	= 1;
+				opts.blockalign = 1;
+				opts.quiet      = quiet;
+				ret = nand_write_opts(nand, &opts);
+			}
+			printf("%s\n", ret ? "ERROR" : "OK");
+			return ret == 0 ? 0 : 1;
+		}
+
+		if (read)
 			ret = nand_read(nand, off, &size, (u_char *)addr);
 		else
 			ret = nand_write(nand, off, &size, (u_char *)addr);
 
 		printf(" %d bytes %s: %s\n", size,
-		       i ? "read" : "written", ret ? "ERROR" : "OK");
+		       read ? "read" : "written", ret ? "ERROR" : "OK");
 
 		return ret == 0 ? 0 : 1;
 	}
+
+	/* 2006-09-28 gc: implement missing commands */
+	if (strcmp(cmd, "markbad") == 0) {
+		addr = (ulong)simple_strtoul(argv[2], NULL, 16);
+
+		int ret = nand->block_markbad(nand, addr);
+		if (ret == 0) {
+			printf("block 0x%08lx successfully marked as bad\n",
+			       (ulong) addr);
+			return 0;
+		} else {
+			printf("block 0x%08lx NOT marked as bad! ERROR %d\n",
+			       (ulong) addr, ret);
+		}
+		return 1;
+	}
+	if (strcmp(cmd, "biterr") == 0) {
+		/* todo */
+		return 1;
+	}
+
+	if (strcmp(cmd, "lock") == 0) {
+		int tight  = 0;
+		int status = 0;
+		if (argc == 3) {
+			if (!strcmp("tight", argv[2]))
+				tight = 1;
+			if (!strcmp("status", argv[2]))
+				status = 1;
+		}
+
+		if (status) {
+			ulong block_start = 0;
+			ulong off;
+			int last_status = -1;
+
+			struct nand_chip *nand_chip = nand->priv;
+			/* check the WP bit */
+			nand_chip->cmdfunc (nand, NAND_CMD_STATUS, -1, -1);
+			printf("device is %swrite protected\n",
+			       (nand_chip->read_byte(nand) & 0x80 ?
+				"NOT " : "" ) );
+
+			for (off = 0; off < nand->size; off += nand->oobblock) {
+				int s = nand_get_lock_status(nand, off);
+
+				/* print message only if status has changed
+				 * or at end of chip
+				 */
+				if (off == nand->size - nand->oobblock
+				    || (s != last_status && off != 0))	{
+
+					printf("%08x - %08x: %8d pages %s%s%s\n",
+					       block_start,
+					       off-1,
+					       (off-block_start)/nand->oobblock,
+					       ((last_status & NAND_LOCK_STATUS_TIGHT) ? "TIGHT " : ""),
+					       ((last_status & NAND_LOCK_STATUS_LOCK) ? "LOCK " : ""),
+					       ((last_status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : ""));
+				}
+
+				last_status = s;
+		       }
+		} else {
+			if (!nand_lock(nand, tight)) {
+				printf ("NAND flash successfully locked\n");
+			} else {
+				printf ("Error locking NAND flash. \n");
+				return 1;
+			}
+		}
+		return 0;
+	}
+
+	if (strcmp(cmd, "unlock") == 0) {
+		if (argc == 2) {
+			off = 0;
+			size = nand->size;
+		} else {
+			arg_off_size(argc - 2, argv + 2, &off, &size,
+				     nand->size);
+		}
+
+		if (!nand_unlock(nand, off, size)) {
+			printf("NAND flash successfully unlocked\n");
+		} else {
+			printf("Error unlocking NAND flash. "
+			       "Write and erase will probably fail\n");
+			return 1;
+		}
+		return 0;
+	}
+
 usage:
 	printf("Usage:\n%s\n", cmdtp->usage);
 	return 1;
@@ -277,7 +451,9 @@ U_BOOT_CMD(nand, 5, 1, do_nand,
 	"nand dump[.oob] off - dump page\n"
 	"nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n"
 	"nand markbad off - mark bad block at offset (UNSAFE)\n"
-	"nand biterr off - make a bit error at offset (UNSAFE)\n");
+	"nand biterr off - make a bit error at offset (UNSAFE)\n"
+	"nand lock [tight] [status] - bring nand to lock state or display locked pages\n"
+	"nand unlock [offset] [size] - unlock section\n");
 
 int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
@@ -596,7 +772,7 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			return 1;
 		}
 
-		printf ("\nNAND %s: device %d offset %ld, size %ld ... ",
+		printf ("\nNAND %s: device %d offset %ld, size %ld ...\n",
 			(cmd & NANDRW_READ) ? "read" : "write",
 			curr_device, off, size);
 
@@ -615,7 +791,7 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		ulong size = simple_strtoul(argv[3 + clean], NULL, 16);
 		int ret;
 
-		printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
+		printf ("\nNAND erase: device %d offset %ld, size %ld ...\n",
 			curr_device, off, size);
 
 		ret = nand_legacy_erase (nand_dev_desc + curr_device,
@@ -635,7 +811,7 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 U_BOOT_CMD(
 	nand,	5,	1,	do_nand,
-	"nand    - NAND sub-system\n",
+	"nand    - legacy NAND sub-system\n",
 	"info  - show available NAND devices\n"
 	"nand device [dev] - show or set current device\n"
 	"nand read[.jffs2[s]]  addr off size\n"
diff --git a/doc/README.nand b/doc/README.nand
index f2d6a5b1e65..2b9a52966c5 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -207,3 +207,47 @@ As mentioned above, the legacy code is still used by the DoC subsystem.
 The consequence of this is that the legacy NAND can't be removed  from
 the tree until the DoC is ported to use the new NAND support (or boards
 with DoC will break).
+
+
+
+Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
+
+JFFS2 related commands:
+
+  implement "nand erase clean" and old "nand erase"
+  using both the new code which is able to skip bad blocks
+  "nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.
+
+  "nand write.jffs2"
+  like "nand write" but skip found bad eraseblocks
+
+  "nand read.jffs2"
+  like "nand read" but skip found bad eraseblocks
+
+Miscellaneous and testing commands:
+  "markbad [offset]"
+  create an artificial bad block (for testing bad block handling)
+
+  "scrub [offset length]"
+  like "erase" but don't skip bad block. Instead erase them.
+  DANGEROUS!!! Factory set bad blocks will be lost. Use only
+  to remove artificial bad blocks created with the "markbad" command.
+
+
+NAND locking command (for chips with active LOCKPRE pin)
+
+  "nand lock"
+  set NAND chip to lock state (all pages locked)
+
+  "nand lock tight"
+  set NAND chip to lock tight state (software can't change locking anymore)
+
+  "nand lock status"
+  displays current locking status of all pages
+
+  "nand unlock [offset] [size]"
+  unlock consecutive area (can be called multiple times for different areas)
+
+
+I have tested the code with board containing 128MiB NAND large page chips
+and 32MiB small page chips.
diff --git a/drivers/nand/Makefile b/drivers/nand/Makefile
index b03604dc4e9..fb0185b991b 100644
--- a/drivers/nand/Makefile
+++ b/drivers/nand/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB 	:= $(obj)libnand.a
 
-COBJS 	:= nand.o nand_base.o nand_ids.o nand_ecc.o nand_bbt.o
+COBJS 	:= nand.o nand_base.o nand_ids.o nand_ecc.o nand_bbt.o nand_util.o
 
 SRCS 	:= $(COBJS:.o=.c)
 OBJS 	:= $(addprefix $(obj),$(COBJS))
diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c
new file mode 100644
index 00000000000..5a8e58a741c
--- /dev/null
+++ b/drivers/nand/nand_util.c
@@ -0,0 +1,869 @@
+/*
+ * drivers/nand/nand_util.c
+ *
+ * Copyright (C) 2006 by Weiss-Electronic GmbH.
+ * All rights reserved.
+ *
+ * @author:	Guido Classen <clagix@gmail.com>
+ * @descr:	NAND Flash support
+ * @references: borrowed heavily from Linux mtd-utils code:
+ *		flash_eraseall.c by Arcom Control System Ltd
+ *		nandwrite.c by Steven J. Hill (sjhill@realitydiluted.com)
+ *			       and Thomas Gleixner (tglx@linutronix.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
+
+#include <command.h>
+#include <watchdog.h>
+#include <malloc.h>
+
+#include <nand.h>
+#include <jffs2/jffs2.h>
+
+typedef struct erase_info erase_info_t;
+typedef struct mtd_info	  mtd_info_t;
+
+/* support only for native endian JFFS2 */
+#define cpu_to_je16(x) (x)
+#define cpu_to_je32(x) (x)
+
+/*****************************************************************************/
+static int nand_block_bad_scrub(struct mtd_info *mtd, loff_t ofs, int getchip)
+{
+	return 0;
+}
+
+/**
+ * nand_erase_opts: - erase NAND flash with support for various options
+ *		      (jffs2 formating)
+ *
+ * @param meminfo	NAND device to erase
+ * @param opts		options,  @see struct nand_erase_options
+ * @return		0 in case of success
+ *
+ * This code is ported from flash_eraseall.c from Linux mtd utils by
+ * Arcom Control System Ltd.
+ */
+int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
+{
+	struct jffs2_unknown_node cleanmarker;
+	int clmpos = 0;
+	int clmlen = 8;
+	erase_info_t erase;
+	ulong erase_length;
+	int isNAND;
+	int bbtest = 1;
+	int result;
+	int percent_complete = -1;
+	int (*nand_block_bad_old)(struct mtd_info *, loff_t, int) = NULL;
+	const char *mtd_device = meminfo->name;
+
+	memset(&erase, 0, sizeof(erase));
+
+	erase.mtd = meminfo;
+	erase.len  = meminfo->erasesize;
+	if (opts->offset == 0 && opts->length == 0) {
+		/* erase complete chip */
+		erase.addr = 0;
+		erase_length = meminfo->size;
+	} else {
+		/* erase specified region */
+		erase.addr = opts->offset;
+		erase_length = opts->length;
+	}
+
+	isNAND = meminfo->type == MTD_NANDFLASH ? 1 : 0;
+
+	if (opts->jffs2) {
+		cleanmarker.magic = cpu_to_je16 (JFFS2_MAGIC_BITMASK);
+		cleanmarker.nodetype = cpu_to_je16 (JFFS2_NODETYPE_CLEANMARKER);
+		if (isNAND) {
+			struct nand_oobinfo *oobinfo = &meminfo->oobinfo;
+
+			/* check for autoplacement */
+			if (oobinfo->useecc == MTD_NANDECC_AUTOPLACE) {
+				/* get the position of the free bytes */
+				if (!oobinfo->oobfree[0][1]) {
+					printf(" Eeep. Autoplacement selected "
+					       "and no empty space in oob\n");
+					return -1;
+				}
+				clmpos = oobinfo->oobfree[0][0];
+				clmlen = oobinfo->oobfree[0][1];
+				if (clmlen > 8)
+					clmlen = 8;
+			} else {
+				/* legacy mode */
+				switch (meminfo->oobsize) {
+				case 8:
+					clmpos = 6;
+					clmlen = 2;
+					break;
+				case 16:
+					clmpos = 8;
+					clmlen = 8;
+					break;
+				case 64:
+					clmpos = 16;
+					clmlen = 8;
+					break;
+				}
+			}
+
+			cleanmarker.totlen = cpu_to_je32(8);
+		} else {
+			cleanmarker.totlen =
+				cpu_to_je32(sizeof(struct jffs2_unknown_node));
+		}
+		cleanmarker.hdr_crc =  cpu_to_je32(
+			crc32_no_comp(0, (unsigned char *) &cleanmarker,
+				      sizeof(struct jffs2_unknown_node) - 4));
+	}
+
+	/* scrub option allows to erase badblock. To prevent internal
+	 * check from erase() method, set block check method to dummy
+	 * and disable bad block table while erasing.
+	 */
+	if (opts->scrub) {
+		struct nand_chip *priv_nand = meminfo->priv;
+
+		nand_block_bad_old = priv_nand->block_bad;
+		priv_nand->block_bad = nand_block_bad_scrub;
+		/* we don't need the bad block table anymore...
+		 * after scrub, there are no bad blocks left!
+		 */
+		if (priv_nand->bbt) {
+			kfree(priv_nand->bbt);
+		}
+		priv_nand->bbt = NULL;
+	}
+
+	for (;
+	     erase.addr < opts->offset + erase_length;
+	     erase.addr += meminfo->erasesize) {
+
+		WATCHDOG_RESET ();
+
+		if (!opts->scrub && bbtest) {
+			int ret = meminfo->block_isbad(meminfo, erase.addr);
+			if (ret > 0) {
+				if (!opts->quiet)
+					printf("\rSkipping bad block at  "
+                                               "0x%08x                   "
+                                               "                         \n",
+                                               erase.addr);
+				continue;
+
+			} else if (ret < 0) {
+				printf("\n%s: MTD get bad block failed: %d\n",
+				       mtd_device,
+				       ret);
+				return -1;
+			}
+		}
+
+		result = meminfo->erase(meminfo, &erase);
+		if (result != 0) {
+			printf("\n%s: MTD Erase failure: %d\n",
+			       mtd_device, result);
+			continue;
+		}
+
+		/* format for JFFS2 ? */
+		if (opts->jffs2) {
+
+			/* write cleanmarker */
+			if (isNAND) {
+				size_t written;
+				result = meminfo->write_oob(meminfo,
+							    erase.addr + clmpos,
+							    clmlen,
+							    &written,
+							    (unsigned char *)
+							    &cleanmarker);
+				if (result != 0) {
+					printf("\n%s: MTD writeoob failure: %d\n",
+					       mtd_device, result);
+					continue;
+				}
+			} else {
+				printf("\n%s: this erase routine only supports"
+				       " NAND devices!\n",
+				       mtd_device);
+			}
+		}
+
+		if (!opts->quiet) {
+			int percent = (int)
+				((unsigned long long)
+				 (erase.addr+meminfo->erasesize-opts->offset)
+				 * 100 / erase_length);
+
+			/* output progress message only at whole percent
+			 * steps to reduce the number of messages printed
+			 * on (slow) serial consoles
+			 */
+			if (percent != percent_complete) {
+				percent_complete = percent;
+
+				printf("\rErasing at 0x%x -- %3d%% complete.",
+				       erase.addr, percent);
+
+				if (opts->jffs2 && result == 0)
+					printf(" Cleanmarker written at 0x%x.",
+					       erase.addr);
+			}
+		}
+	}
+	if (!opts->quiet)
+		printf("\n");
+
+	if (nand_block_bad_old) {
+		struct nand_chip *priv_nand = meminfo->priv;
+
+		priv_nand->block_bad = nand_block_bad_old;
+		priv_nand->scan_bbt(meminfo);
+	}
+
+	return 0;
+}
+
+#define MAX_PAGE_SIZE	2048
+#define MAX_OOB_SIZE	64
+
+/*
+ * buffer array used for writing data
+ */
+static unsigned char data_buf[MAX_PAGE_SIZE];
+static unsigned char oob_buf[MAX_OOB_SIZE];
+
+/* OOB layouts to pass into the kernel as default */
+static struct nand_oobinfo none_oobinfo = {
+	.useecc = MTD_NANDECC_OFF,
+};
+
+static struct nand_oobinfo jffs2_oobinfo = {
+	.useecc = MTD_NANDECC_PLACE,
+	.eccbytes = 6,
+	.eccpos = { 0, 1, 2, 3, 6, 7 }
+};
+
+static struct nand_oobinfo yaffs_oobinfo = {
+	.useecc = MTD_NANDECC_PLACE,
+	.eccbytes = 6,
+	.eccpos = { 8, 9, 10, 13, 14, 15}
+};
+
+static struct nand_oobinfo autoplace_oobinfo = {
+	.useecc = MTD_NANDECC_AUTOPLACE
+};
+
+/**
+ * nand_write_opts: - write image to NAND flash with support for various options
+ *
+ * @param meminfo	NAND device to erase
+ * @param opts		write options (@see nand_write_options)
+ * @return		0 in case of success
+ *
+ * This code is ported from nandwrite.c from Linux mtd utils by
+ * Steven J. Hill and Thomas Gleixner.
+ */
+int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts)
+{
+	int imglen = 0;
+	int pagelen;
+	int baderaseblock;
+	int blockstart = -1;
+	loff_t offs;
+	int readlen;
+	int oobinfochanged = 0;
+	int percent_complete = -1;
+	struct nand_oobinfo old_oobinfo;
+	ulong mtdoffset = opts->offset;
+	ulong erasesize_blockalign;
+	u_char *buffer = opts->buffer;
+	size_t written;
+	int result;
+
+	if (opts->pad && opts->writeoob) {
+		printf("Can't pad when oob data is present.\n");
+		return -1;
+	}
+
+	/* set erasesize to specified number of blocks - to match
+	 * jffs2 (virtual) block size */
+	if (opts->blockalign == 0) {
+		erasesize_blockalign = meminfo->erasesize;
+	} else {
+		erasesize_blockalign = meminfo->erasesize * opts->blockalign;
+	}
+
+	/* make sure device page sizes are valid */
+	if (!(meminfo->oobsize == 16 && meminfo->oobblock == 512)
+	    && !(meminfo->oobsize == 8 && meminfo->oobblock == 256)
+	    && !(meminfo->oobsize == 64 && meminfo->oobblock == 2048)) {
+		printf("Unknown flash (not normal NAND)\n");
+		return -1;
+	}
+
+	/* read the current oob info */
+	memcpy(&old_oobinfo, &meminfo->oobinfo, sizeof(old_oobinfo));
+
+	/* write without ecc? */
+	if (opts->noecc) {
+		memcpy(&meminfo->oobinfo, &none_oobinfo,
+		       sizeof(meminfo->oobinfo));
+		oobinfochanged = 1;
+	}
+
+	/* autoplace ECC? */
+	if (opts->autoplace && (old_oobinfo.useecc != MTD_NANDECC_AUTOPLACE)) {
+
+		memcpy(&meminfo->oobinfo, &autoplace_oobinfo,
+		       sizeof(meminfo->oobinfo));
+		oobinfochanged = 1;
+	}
+
+	/* force OOB layout for jffs2 or yaffs? */
+	if (opts->forcejffs2 || opts->forceyaffs) {
+		struct nand_oobinfo *oobsel =
+			opts->forcejffs2 ? &jffs2_oobinfo : &yaffs_oobinfo;
+
+		if (meminfo->oobsize == 8) {
+			if (opts->forceyaffs) {
+				printf("YAFSS cannot operate on "
+				       "256 Byte page size\n");
+				goto restoreoob;
+			}
+			/* Adjust number of ecc bytes */
+			jffs2_oobinfo.eccbytes = 3;
+		}
+
+		memcpy(&meminfo->oobinfo, oobsel, sizeof(meminfo->oobinfo));
+	}
+
+	/* get image length */
+	imglen = opts->length;
+	pagelen = meminfo->oobblock
+		+ ((opts->writeoob != 0) ? meminfo->oobsize : 0);
+
+	/* check, if file is pagealigned */
+	if ((!opts->pad) && ((imglen % pagelen) != 0)) {
+		printf("Input block length is not page aligned\n");
+		goto restoreoob;
+	}
+
+	/* check, if length fits into device */
+	if (((imglen / pagelen) * meminfo->oobblock)
+	     > (meminfo->size - opts->offset)) {
+		printf("Image %d bytes, NAND page %d bytes, "
+		       "OOB area %u bytes, device size %u bytes\n",
+		       imglen, pagelen, meminfo->oobblock, meminfo->size);
+		printf("Input block does not fit into device\n");
+		goto restoreoob;
+	}
+
+	if (!opts->quiet)
+		printf("\n");
+
+	/* get data from input and write to the device */
+	while (imglen && (mtdoffset < meminfo->size)) {
+
+		WATCHDOG_RESET ();
+
+		/*
+		 * new eraseblock, check for bad block(s). Stay in the
+		 * loop to be sure if the offset changes because of
+		 * a bad block, that the next block that will be
+		 * written to is also checked. Thus avoiding errors if
+		 * the block(s) after the skipped block(s) is also bad
+		 * (number of blocks depending on the blockalign
+		 */
+		while (blockstart != (mtdoffset & (~erasesize_blockalign+1))) {
+			blockstart = mtdoffset & (~erasesize_blockalign+1);
+			offs = blockstart;
+			baderaseblock = 0;
+
+			/* check all the blocks in an erase block for
+			 * bad blocks */
+			do {
+				int ret = meminfo->block_isbad(meminfo, offs);
+
+				if (ret < 0) {
+					printf("Bad block check failed\n");
+					goto restoreoob;
+				}
+				if (ret == 1) {
+					baderaseblock = 1;
+					if (!opts->quiet)
+						printf("\rBad block at 0x%lx "
+						       "in erase block from "
+						       "0x%x will be skipped\n",
+						       (long) offs,
+						       blockstart);
+				}
+
+				if (baderaseblock) {
+					mtdoffset = blockstart
+						+ erasesize_blockalign;
+				}
+				offs +=	 erasesize_blockalign
+					/ opts->blockalign;
+			} while (offs < blockstart + erasesize_blockalign);
+		}
+
+		readlen = meminfo->oobblock;
+		if (opts->pad && (imglen < readlen)) {
+			readlen = imglen;
+			memset(data_buf + readlen, 0xff,
+			       meminfo->oobblock - readlen);
+		}
+
+		/* read page data from input memory buffer */
+		memcpy(data_buf, buffer, readlen);
+		buffer += readlen;
+
+		if (opts->writeoob) {
+			/* read OOB data from input memory block, exit
+			 * on failure */
+			memcpy(oob_buf, buffer, meminfo->oobsize);
+			buffer += meminfo->oobsize;
+
+			/* write OOB data first, as ecc will be placed
+			 * in there*/
+			result = meminfo->write_oob(meminfo,
+						    mtdoffset,
+						    meminfo->oobsize,
+						    &written,
+						    (unsigned char *)
+						    &oob_buf);
+
+			if (result != 0) {
+				printf("\nMTD writeoob failure: %d\n",
+				       result);
+				goto restoreoob;
+			}
+			imglen -= meminfo->oobsize;
+		}
+
+		/* write out the page data */
+		result = meminfo->write(meminfo,
+					mtdoffset,
+					meminfo->oobblock,
+					&written,
+					(unsigned char *) &data_buf);
+
+		if (result != 0) {
+			printf("writing NAND page at offset 0x%lx failed\n",
+			       mtdoffset);
+			goto restoreoob;
+		}
+		imglen -= readlen;
+
+		if (!opts->quiet) {
+			int percent = (int)
+				((unsigned long long)
+				 (opts->length-imglen) * 100
+				 / opts->length);
+			/* output progress message only at whole percent
+			 * steps to reduce the number of messages printed
+			 * on (slow) serial consoles
+			 */
+			if (percent != percent_complete) {
+				printf("\rWriting data at 0x%x "
+				       "-- %3d%% complete.",
+				       mtdoffset, percent);
+				percent_complete = percent;
+			}
+		}
+
+		mtdoffset += meminfo->oobblock;
+	}
+
+	if (!opts->quiet)
+		printf("\n");
+
+restoreoob:
+	if (oobinfochanged) {
+		memcpy(&meminfo->oobinfo, &old_oobinfo,
+		       sizeof(meminfo->oobinfo));
+	}
+
+	if (imglen > 0) {
+		printf("Data did not fit into device, due to bad blocks\n");
+		return -1;
+	}
+
+	/* return happy */
+	return 0;
+}
+
+/**
+ * nand_read_opts: - read image from NAND flash with support for various options
+ *
+ * @param meminfo	NAND device to erase
+ * @param opts		read options (@see struct nand_read_options)
+ * @return		0 in case of success
+ *
+ */
+int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts)
+{
+	int imglen = opts->length;
+	int pagelen;
+	int baderaseblock;
+	int blockstart = -1;
+	int percent_complete = -1;
+	loff_t offs;
+	size_t readlen;
+	ulong mtdoffset = opts->offset;
+	u_char *buffer = opts->buffer;
+	int result;
+
+	/* make sure device page sizes are valid */
+	if (!(meminfo->oobsize == 16 && meminfo->oobblock == 512)
+	    && !(meminfo->oobsize == 8 && meminfo->oobblock == 256)
+	    && !(meminfo->oobsize == 64 && meminfo->oobblock == 2048)) {
+		printf("Unknown flash (not normal NAND)\n");
+		return -1;
+	}
+
+	pagelen = meminfo->oobblock
+		+ ((opts->readoob != 0) ? meminfo->oobsize : 0);
+
+	/* check, if length is not larger than device */
+	if (((imglen / pagelen) * meminfo->oobblock)
+	     > (meminfo->size - opts->offset)) {
+		printf("Image %d bytes, NAND page %d bytes, "
+		       "OOB area %u bytes, device size %u bytes\n",
+		       imglen, pagelen, meminfo->oobblock, meminfo->size);
+		printf("Input block is larger than device\n");
+		return -1;
+	}
+
+	if (!opts->quiet)
+		printf("\n");
+
+	/* get data from input and write to the device */
+	while (imglen && (mtdoffset < meminfo->size)) {
+
+		WATCHDOG_RESET ();
+
+		/*
+		 * new eraseblock, check for bad block(s). Stay in the
+		 * loop to be sure if the offset changes because of
+		 * a bad block, that the next block that will be
+		 * written to is also checked. Thus avoiding errors if
+		 * the block(s) after the skipped block(s) is also bad
+		 * (number of blocks depending on the blockalign
+		 */
+		while (blockstart != (mtdoffset & (~meminfo->erasesize+1))) {
+			blockstart = mtdoffset & (~meminfo->erasesize+1);
+			offs = blockstart;
+			baderaseblock = 0;
+
+			/* check all the blocks in an erase block for
+			 * bad blocks */
+			do {
+				int ret = meminfo->block_isbad(meminfo, offs);
+
+				if (ret < 0) {
+					printf("Bad block check failed\n");
+					return -1;
+				}
+				if (ret == 1) {
+					baderaseblock = 1;
+					if (!opts->quiet)
+						printf("\rBad block at 0x%lx "
+						       "in erase block from "
+						       "0x%x will be skipped\n",
+						       (long) offs,
+						       blockstart);
+				}
+
+				if (baderaseblock) {
+					mtdoffset = blockstart
+						+ meminfo->erasesize;
+				}
+				offs +=	 meminfo->erasesize;
+
+			} while (offs < blockstart + meminfo->erasesize);
+		}
+
+
+		/* read page data to memory buffer */
+		result = meminfo->read(meminfo,
+				       mtdoffset,
+				       meminfo->oobblock,
+				       &readlen,
+				       (unsigned char *) &data_buf);
+
+		if (result != 0) {
+			printf("reading NAND page at offset 0x%lx failed\n",
+			       mtdoffset);
+			return -1;
+		}
+
+		if (imglen < readlen) {
+			readlen = imglen;
+		}
+
+		memcpy(buffer, data_buf, readlen);
+		buffer += readlen;
+		imglen -= readlen;
+
+		if (opts->readoob) {
+			result = meminfo->read_oob(meminfo,
+						   mtdoffset,
+						   meminfo->oobsize,
+						   &readlen,
+						   (unsigned char *)
+						   &oob_buf);
+
+			if (result != 0) {
+				printf("\nMTD readoob failure: %d\n",
+				       result);
+				return -1;
+			}
+
+
+			if (imglen < readlen) {
+				readlen = imglen;
+			}
+
+			memcpy(buffer, oob_buf, readlen);
+
+			buffer += readlen;
+			imglen -= readlen;
+		}
+
+		if (!opts->quiet) {
+			int percent = (int)
+				((unsigned long long)
+				 (opts->length-imglen) * 100
+				 / opts->length);
+			/* output progress message only at whole percent
+			 * steps to reduce the number of messages printed
+			 * on (slow) serial consoles
+			 */
+			if (percent != percent_complete) {
+			if (!opts->quiet)
+				printf("\rReading data from 0x%x "
+				       "-- %3d%% complete.",
+				       mtdoffset, percent);
+				percent_complete = percent;
+			}
+		}
+
+		mtdoffset += meminfo->oobblock;
+	}
+
+	if (!opts->quiet)
+		printf("\n");
+
+	if (imglen > 0) {
+		printf("Could not read entire image due to bad blocks\n");
+		return -1;
+	}
+
+	/* return happy */
+	return 0;
+}
+
+/******************************************************************************
+ * Support for locking / unlocking operations of some NAND devices
+ *****************************************************************************/
+
+#define NAND_CMD_LOCK		0x2a
+#define NAND_CMD_LOCK_TIGHT	0x2c
+#define NAND_CMD_UNLOCK1	0x23
+#define NAND_CMD_UNLOCK2	0x24
+#define NAND_CMD_LOCK_STATUS	0x7a
+
+/**
+ * nand_lock: Set all pages of NAND flash chip to the LOCK or LOCK-TIGHT
+ *	      state
+ *
+ * @param meminfo	nand mtd instance
+ * @param tight		bring device in lock tight mode
+ *
+ * @return		0 on success, -1 in case of error
+ *
+ * The lock / lock-tight command only applies to the whole chip. To get some
+ * parts of the chip lock and others unlocked use the following sequence:
+ *
+ * - Lock all pages of the chip using nand_lock(mtd, 0) (or the lockpre pin)
+ * - Call nand_unlock() once for each consecutive area to be unlocked
+ * - If desired: Bring the chip to the lock-tight state using nand_lock(mtd, 1)
+ *
+ *   If the device is in lock-tight state software can't change the
+ *   current active lock/unlock state of all pages. nand_lock() / nand_unlock()
+ *   calls will fail. It is only posible to leave lock-tight state by
+ *   an hardware signal (low pulse on _WP pin) or by power down.
+ */
+int nand_lock(nand_info_t *meminfo, int tight)
+{
+	int ret = 0;
+	int status;
+	struct nand_chip *this = meminfo->priv;
+
+	/* select the NAND device */
+	this->select_chip(meminfo, 0);
+
+	this->cmdfunc(meminfo,
+		      (tight ? NAND_CMD_LOCK_TIGHT : NAND_CMD_LOCK),
+		      -1, -1);
+
+	/* call wait ready function */
+	status = this->waitfunc(meminfo, this, FL_WRITING);
+
+	/* see if device thinks it succeeded */
+	if (status & 0x01) {
+		ret = -1;
+	}
+
+	/* de-select the NAND device */
+	this->select_chip(meminfo, -1);
+	return ret;
+}
+
+/**
+ * nand_get_lock_status: - query current lock state from one page of NAND
+ *			   flash
+ *
+ * @param meminfo	nand mtd instance
+ * @param offset	page address to query (muss be page aligned!)
+ *
+ * @return		-1 in case of error
+ *			>0 lock status:
+ *			  bitfield with the following combinations:
+ *			  NAND_LOCK_STATUS_TIGHT: page in tight state
+ *			  NAND_LOCK_STATUS_LOCK:  page locked
+ *			  NAND_LOCK_STATUS_UNLOCK: page unlocked
+ *
+ */
+int nand_get_lock_status(nand_info_t *meminfo, ulong offset)
+{
+	int ret = 0;
+	int chipnr;
+	int page;
+	struct nand_chip *this = meminfo->priv;
+
+	/* select the NAND device */
+	chipnr = (int)(offset >> this->chip_shift);
+	this->select_chip(meminfo, chipnr);
+
+
+	if ((offset & (meminfo->oobblock - 1)) != 0) {
+		printf ("nand_get_lock_status: "
+			"Start address must be beginning of "
+			"nand page!\n");
+		ret = -1;
+		goto out;
+	}
+
+	/* check the Lock Status */
+	page = (int)(offset >> this->page_shift);
+	this->cmdfunc(meminfo, NAND_CMD_LOCK_STATUS, -1, page & this->pagemask);
+
+	ret = this->read_byte(meminfo) & (NAND_LOCK_STATUS_TIGHT
+					  | NAND_LOCK_STATUS_LOCK
+					  | NAND_LOCK_STATUS_UNLOCK);
+
+ out:
+	/* de-select the NAND device */
+	this->select_chip(meminfo, -1);
+	return ret;
+}
+
+/**
+ * nand_unlock: - Unlock area of NAND pages
+ *		  only one consecutive area can be unlocked at one time!
+ *
+ * @param meminfo	nand mtd instance
+ * @param start		start byte address
+ * @param length	number of bytes to unlock (must be a multiple of
+ *			page size nand->oobblock)
+ *
+ * @return		0 on success, -1 in case of error
+ */
+int nand_unlock(nand_info_t *meminfo, ulong start, ulong length)
+{
+	int ret = 0;
+	int chipnr;
+	int status;
+	int page;
+	struct nand_chip *this = meminfo->priv;
+	printf ("nand_unlock: start: %08x, length: %d!\n",
+		(int)start, (int)length);
+
+	/* select the NAND device */
+	chipnr = (int)(start >> this->chip_shift);
+	this->select_chip(meminfo, chipnr);
+
+	/* check the WP bit */
+	this->cmdfunc(meminfo, NAND_CMD_STATUS, -1, -1);
+	if ((this->read_byte(meminfo) & 0x80) == 0) {
+		printf ("nand_unlock: Device is write protected!\n");
+		ret = -1;
+		goto out;
+	}
+
+	if ((start & (meminfo->oobblock - 1)) != 0) {
+		printf ("nand_unlock: Start address must be beginning of "
+			"nand page!\n");
+		ret = -1;
+		goto out;
+	}
+
+	if (length == 0 || (length & (meminfo->oobblock - 1)) != 0) {
+		printf ("nand_unlock: Length must be a multiple of nand page "
+			"size!\n");
+		ret = -1;
+		goto out;
+	}
+
+	/* submit address of first page to unlock */
+	page = (int)(start >> this->page_shift);
+	this->cmdfunc(meminfo, NAND_CMD_UNLOCK1, -1, page & this->pagemask);
+
+	/* submit ADDRESS of LAST page to unlock */
+	page += (int)(length >> this->page_shift) - 1;
+	this->cmdfunc(meminfo, NAND_CMD_UNLOCK2, -1, page & this->pagemask);
+
+	/* call wait ready function */
+	status = this->waitfunc(meminfo, this, FL_WRITING);
+	/* see if device thinks it succeeded */
+	if (status & 0x01) {
+		/* there was an error */
+		ret = -1;
+		goto out;
+	}
+
+ out:
+	/* de-select the NAND device */
+	this->select_chip(meminfo, -1);
+	return ret;
+}
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) */
diff --git a/include/nand.h b/include/nand.h
index 905115b3dac..5c7311fd505 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -60,4 +60,61 @@ static inline int nand_erase(nand_info_t *info, ulong off, ulong size)
 	return info->erase(info, &instr);
 }
 
+
+/*****************************************************************************
+ * declarations from nand_util.c
+ ****************************************************************************/
+
+struct nand_write_options {
+	u_char *buffer;		/* memory block containing image to write */
+	ulong length;		/* number of bytes to write */
+	ulong offset;		/* start address in NAND */
+	int quiet;		/* don't display progress messages */
+	int autoplace;		/* if true use auto oob layout */
+	int forcejffs2;		/* force jffs2 oob layout */
+	int forceyaffs;		/* force yaffs oob layout */
+	int noecc;		/* write without ecc */
+	int writeoob;		/* image contains oob data */
+	int pad;		/* pad to page size */
+	int blockalign;		/* 1|2|4 set multiple of eraseblocks
+				 * to align to */
+};
+
+typedef struct nand_write_options nand_write_options_t;
+
+struct nand_read_options {
+	u_char *buffer;		/* memory block in which read image is written*/
+	ulong length;		/* number of bytes to read */
+	ulong offset;		/* start address in NAND */
+	int quiet;		/* don't display progress messages */
+	int readoob;		/* put oob data in image */
+};
+
+typedef struct nand_read_options nand_read_options_t;
+
+struct nand_erase_options {
+	ulong length;		/* number of bytes to erase */
+	ulong offset;		/* first address in NAND to erase */
+	int quiet;		/* don't display progress messages */
+	int jffs2;		/* if true: format for jffs2 usage
+				 * (write appropriate cleanmarker blocks) */
+	int scrub;		/* if true, really clean NAND by erasing
+				 * bad blocks (UNSAFE) */
+};
+
+typedef struct nand_erase_options nand_erase_options_t;
+
+int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts);
+
+int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts);
+int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts);
+
+#define NAND_LOCK_STATUS_TIGHT	0x01
+#define NAND_LOCK_STATUS_LOCK	0x02
+#define NAND_LOCK_STATUS_UNLOCK 0x04
+
+int nand_lock( nand_info_t *meminfo, int tight );
+int nand_unlock( nand_info_t *meminfo, ulong start, ulong length );
+int nand_get_lock_status(nand_info_t *meminfo, ulong offset);
+
 #endif
diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c
index 50ca4ffd380..82834135022 100644
--- a/lib_generic/crc32.c
+++ b/lib_generic/crc32.c
@@ -171,7 +171,9 @@ uLong ZEXPORT crc32(crc, buf, len)
     return crc ^ 0xffffffffL;
 }
 
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)					\
+	|| (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
+
 
 /* No ones complement version. JFFS2 (and other things ?)
  * don't use ones compliment in their CRC calculations.
-- 
cgit v1.3.1