From 074596c0b5f4e9a3642a3159a9fc7f8b8064c18a Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 7 Apr 2016 16:22:21 +0800 Subject: armv8/ls1043: Add workaround for DDR erratum A-008850 Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- include/fsl_ddr_sdram.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index cf316a4665f..44ae7fbb9ce 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -146,6 +146,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define WR_DATA_DELAY_SHIFT 10 #endif +/* DDR_EOR register */ +#define DDR_EOR_RD_REOD_DIS 0x07000000 +#define DDR_EOR_WD_REOD_DIS 0x00100000 + /* DDR_MD_CNTL */ #define MD_CNTL_MD_EN 0x80000000 #define MD_CNTL_CS_SEL_CS0 0x00000000 -- cgit v1.3.1 From 4a68489e12313a7fa8740463dee0eea2985eb563 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 16 Mar 2016 13:50:22 +0800 Subject: drivers/ddr/fsl: update workaround for erratum A-008511 Per the latest erratum document, update step 4 and step 8, only DEBUG_29[21] is changed, all other bits should not be changed. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- drivers/ddr/fsl/fsl_ddr_gen4.c | 10 +++++++--- include/fsl_ddr_sdram.h | 3 +++ 2 files changed, 10 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 608810d4e29..7cdb7008b46 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -240,8 +240,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, /* Disable DRAM VRef training */ ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); - /* Disable deskew */ - ddr_out32(&ddr->debug[28], 0x400); + /* disable transmit bit deskew */ + temp32 = ddr_in32(&ddr->debug[28]); + temp32 |= DDR_TX_BD_DIS; + ddr_out32(&ddr->debug[28], temp32); /* Disable D_INIT */ ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); @@ -358,7 +360,9 @@ step2: debug("MR6 = 0x%08x\n", temp32); } ddr_out32(&ddr->sdram_md_cntl, 0); - ddr_out32(&ddr->debug[28], 0); /* Enable deskew */ + temp32 = ddr_in32(&ddr->debug[28]); + temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */ + ddr_out32(&ddr->debug[28], temp32); ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */ /* wait for idle */ timeout = 40; diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 44ae7fbb9ce..acddf14a3f5 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -189,6 +189,9 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ +/* DEBUG_29 register */ +#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */ + #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) -- cgit v1.3.1 From 5fc62fe57097e195a8047859cd3c278a5d6790b6 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 16 Mar 2016 13:50:23 +0800 Subject: driver/ddr/fsl: Add workaround for erratum A-009801 The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + drivers/ddr/fsl/fsl_ddr_gen4.c | 7 +++++++ include/fsl_ddr_sdram.h | 4 ++++ 3 files changed, 12 insertions(+) (limited to 'include') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index a24dc2805d4..6529281c94d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -134,6 +134,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A008751 #define CONFIG_SYS_FSL_ERRATUM_A009635 #define CONFIG_SYS_FSL_ERRATUM_A009663 +#define CONFIG_SYS_FSL_ERRATUM_A009801 #define CONFIG_SYS_FSL_ERRATUM_A009803 #define CONFIG_SYS_FSL_ERRATUM_A009942 diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 7cdb7008b46..1dc06314409 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -251,6 +251,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009801 + temp32 = ddr_in32(&ddr->debug[25]); + temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK; + temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT; + ddr_out32(&ddr->debug[25], temp32); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; tmp = ddr_in32(&ddr->debug[28]); diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index acddf14a3f5..486e47e508d 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -189,6 +189,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ +/* DEBUG_26 register */ +#define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */ +#define DDR_CAS_TO_PRE_SUB_SHIFT 12 + /* DEBUG_29 register */ #define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */ -- cgit v1.3.1 From bcb55f67f22b297d6c10e039bfcef9847a20fbfb Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Wed, 6 Apr 2016 22:25:51 +0530 Subject: armv8: ls2080: enable sec_init in U-Boot Define CONFIG_FSL_CAAM for LS2080 which would enable call to sec_init() during U-Boot. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- include/configs/ls2080a_common.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index a3aad1b99d9..c78aeb57ed4 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -26,6 +26,8 @@ /* We need architecture specific misc initializations */ #define CONFIG_ARCH_MISC_INIT +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + /* Link Definitions */ #ifdef CONFIG_SPL #define CONFIG_SYS_TEXT_BASE 0x80400000 @@ -292,4 +294,10 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #endif /* __LS2_COMMON_H */ -- cgit v1.3.1 From 7ad9cc969b00cd5e238f4a194f0e974d74706b8e Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 19 Apr 2016 08:53:42 +0530 Subject: armv8: ls2080a: update eth prime As per new PHY framework, DPNI naming convetion is no more used. Use new naming convention. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- include/configs/ls2080aqds.h | 2 +- include/configs/ls2080ardb.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 2d7567f394f..16a536aa625 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -374,7 +374,7 @@ unsigned long get_board_ddr_clk(void); #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf #define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "DPNI1" +#define CONFIG_ETHPRIME "DPMAC1@xgmii" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 5bec5099af7..45827f6a038 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -366,7 +366,7 @@ unsigned long get_board_sys_clk(void); #define AQR405_IRQ_MASK 0x36 #define CONFIG_MII -#define CONFIG_ETHPRIME "DPNI1" +#define CONFIG_ETHPRIME "DPMAC1@xgmii" #define CONFIG_PHY_GIGE #define CONFIG_PHY_AQUANTIA #endif -- cgit v1.3.1 From 1297cdb452fcdc6e7149c6761e43629f9c732010 Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Mon, 25 Apr 2016 16:53:53 +0800 Subject: armv8: ls1043a: copy kernel from QSPI when booting with QSPI enabled IFC won't be initialized in U-Boot if QSPI is enabled on LS1043AQDS. So this patch could fix 'sync abort' caused by autoboot that tries to access IFC address. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- include/configs/ls1043a_common.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 54968b52312..a7d49ed6e84 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -257,8 +257,13 @@ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500" +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ + "e0000 f00000 && bootm $kernel_load" +#else #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" +#endif #define CONFIG_BOOTDELAY 10 /* Monitor Command Prompt */ -- cgit v1.3.1 From 76394c9c9139b82e21a6e52da0e7341a3374f4be Mon Sep 17 00:00:00 2001 From: Alex Porosanu Date: Fri, 29 Apr 2016 15:18:00 +0300 Subject: crypto/fsl: add support for multiple SEC engines initialization For SoCs that contain multiple SEC engines, each of them needs to be initialized (by means of initializing among others the random number generator). Signed-off-by: Alex Porosanu Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 ++ drivers/crypto/fsl/jr.c | 271 +++++++++++++++++++++--------------- drivers/crypto/fsl/jr.h | 3 + include/fsl_sec.h | 6 +- 4 files changed, 172 insertions(+), 117 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index f168375b45d..61f5639e0de 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -958,6 +958,15 @@ int cpu_init_r(void) #ifdef CONFIG_FSL_CAAM sec_init(); + +#if defined(CONFIG_PPC_C29X) + if ((SVR_SOC_VER(svr) == SVR_C292) || + (SVR_SOC_VER(svr) == SVR_C293)) + sec_init_idx(1); + + if (SVR_SOC_VER(svr) == SVR_C293) + sec_init_idx(2); +#endif #endif #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 8bc517dadcf..510fa4e3760 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -19,11 +19,26 @@ #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size)) -struct jobring jr; +uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = { + 0, +#if defined(CONFIG_PPC_C29X) + CONFIG_SYS_FSL_SEC_IDX_OFFSET, + 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET +#endif +}; + +#define SEC_ADDR(idx) \ + ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx])) + +#define SEC_JR0_ADDR(idx) \ + (SEC_ADDR(idx) + \ + (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET)) + +struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC]; -static inline void start_jr0(void) +static inline void start_jr0(uint8_t sec_idx) { - ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); u32 ctpr_ms = sec_in32(&sec->ctpr_ms); u32 scfgr = sec_in32(&sec->scfgr); @@ -42,15 +57,15 @@ static inline void start_jr0(void) } } -static inline void jr_reset_liodn(void) +static inline void jr_reset_liodn(uint8_t sec_idx) { - ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); sec_out32(&sec->jrliodnr[0].ls, 0); } -static inline void jr_disable_irq(void) +static inline void jr_disable_irq(uint8_t sec_idx) { - struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; + struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); uint32_t jrcfg = sec_in32(®s->jrcfg1); jrcfg = jrcfg | JR_INTMASK; @@ -58,11 +73,12 @@ static inline void jr_disable_irq(void) sec_out32(®s->jrcfg1, jrcfg); } -static void jr_initregs(void) +static void jr_initregs(uint8_t sec_idx) { - struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; - phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring); - phys_addr_t op_base = virt_to_phys((void *)jr.output_ring); + struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); + struct jobring *jr = &jr0[sec_idx]; + phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring); + phys_addr_t op_base = virt_to_phys((void *)jr->output_ring); #ifdef CONFIG_PHYS_64BIT sec_out32(®s->irba_h, ip_base >> 32); @@ -79,59 +95,63 @@ static void jr_initregs(void) sec_out32(®s->ors, JR_SIZE); sec_out32(®s->irs, JR_SIZE); - if (!jr.irq) - jr_disable_irq(); + if (!jr->irq) + jr_disable_irq(sec_idx); } -static int jr_init(void) +static int jr_init(uint8_t sec_idx) { - memset(&jr, 0, sizeof(struct jobring)); + struct jobring *jr = &jr0[sec_idx]; - jr.jq_id = DEFAULT_JR_ID; - jr.irq = DEFAULT_IRQ; + memset(jr, 0, sizeof(struct jobring)); + + jr->jq_id = DEFAULT_JR_ID; + jr->irq = DEFAULT_IRQ; #ifdef CONFIG_FSL_CORENET - jr.liodn = DEFAULT_JR_LIODN; + jr->liodn = DEFAULT_JR_LIODN; #endif - jr.size = JR_SIZE; - jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, + jr->size = JR_SIZE; + jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, JR_SIZE * sizeof(dma_addr_t)); - if (!jr.input_ring) + if (!jr->input_ring) return -1; - jr.op_size = roundup(JR_SIZE * sizeof(struct op_ring), - ARCH_DMA_MINALIGN); - jr.output_ring = - (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr.op_size); - if (!jr.output_ring) + jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring), + ARCH_DMA_MINALIGN); + jr->output_ring = + (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size); + if (!jr->output_ring) return -1; - memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t)); - memset(jr.output_ring, 0, jr.op_size); + memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t)); + memset(jr->output_ring, 0, jr->op_size); - start_jr0(); + start_jr0(sec_idx); - jr_initregs(); + jr_initregs(sec_idx); return 0; } -static int jr_sw_cleanup(void) +static int jr_sw_cleanup(uint8_t sec_idx) { - jr.head = 0; - jr.tail = 0; - jr.read_idx = 0; - jr.write_idx = 0; - memset(jr.info, 0, sizeof(jr.info)); - memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t)); - memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring)); + struct jobring *jr = &jr0[sec_idx]; + + jr->head = 0; + jr->tail = 0; + jr->read_idx = 0; + jr->write_idx = 0; + memset(jr->info, 0, sizeof(jr->info)); + memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t)); + memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring)); return 0; } -static int jr_hw_reset(void) +static int jr_hw_reset(uint8_t sec_idx) { - struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; + struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); uint32_t timeout = 100000; uint32_t jrint, jrcr; @@ -161,10 +181,11 @@ static int jr_hw_reset(void) /* -1 --- error, can't enqueue -- no space available */ static int jr_enqueue(uint32_t *desc_addr, void (*callback)(uint32_t status, void *arg), - void *arg) + void *arg, uint8_t sec_idx) { - struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; - int head = jr.head; + struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); + struct jobring *jr = &jr0[sec_idx]; + int head = jr->head; uint32_t desc_word; int length = desc_len(desc_addr); int i; @@ -184,18 +205,14 @@ static int jr_enqueue(uint32_t *desc_addr, phys_addr_t desc_phys_addr = virt_to_phys(desc_addr); - if (sec_in32(®s->irsa) == 0 || - CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0) - return -1; - - jr.info[head].desc_phys_addr = desc_phys_addr; - jr.info[head].callback = (void *)callback; - jr.info[head].arg = arg; - jr.info[head].op_done = 0; + jr->info[head].desc_phys_addr = desc_phys_addr; + jr->info[head].callback = (void *)callback; + jr->info[head].arg = arg; + jr->info[head].op_done = 0; - unsigned long start = (unsigned long)&jr.info[head] & + unsigned long start = (unsigned long)&jr->info[head] & ~(ARCH_DMA_MINALIGN - 1); - unsigned long end = ALIGN((unsigned long)&jr.info[head] + + unsigned long end = ALIGN((unsigned long)&jr->info[head] + sizeof(struct jr_info), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); @@ -205,11 +222,11 @@ static int jr_enqueue(uint32_t *desc_addr, * depend on endianness of SEC block. */ #ifdef CONFIG_SYS_FSL_SEC_LE - addr_lo = (uint32_t *)(&jr.input_ring[head]); - addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1; + addr_lo = (uint32_t *)(&jr->input_ring[head]); + addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1; #elif defined(CONFIG_SYS_FSL_SEC_BE) - addr_hi = (uint32_t *)(&jr.input_ring[head]); - addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1; + addr_hi = (uint32_t *)(&jr->input_ring[head]); + addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1; #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */ sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32)); @@ -217,21 +234,21 @@ static int jr_enqueue(uint32_t *desc_addr, #else /* Write the 32 bit Descriptor address on Input Ring. */ - sec_out32(&jr.input_ring[head], desc_phys_addr); + sec_out32(&jr->input_ring[head], desc_phys_addr); #endif /* ifdef CONFIG_PHYS_64BIT */ - start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); - end = ALIGN((unsigned long)&jr.input_ring[head] + + start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)&jr->input_ring[head] + sizeof(dma_addr_t), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); - jr.head = (head + 1) & (jr.size - 1); + jr->head = (head + 1) & (jr->size - 1); /* Invalidate output ring */ - start = (unsigned long)jr.output_ring & + start = (unsigned long)jr->output_ring & ~(ARCH_DMA_MINALIGN - 1); - end = ALIGN((unsigned long)jr.output_ring + jr.op_size, - ARCH_DMA_MINALIGN); + end = ALIGN((unsigned long)jr->output_ring + jr->op_size, + ARCH_DMA_MINALIGN); invalidate_dcache_range(start, end); sec_out32(®s->irja, 1); @@ -239,11 +256,12 @@ static int jr_enqueue(uint32_t *desc_addr, return 0; } -static int jr_dequeue(void) +static int jr_dequeue(int sec_idx) { - struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; - int head = jr.head; - int tail = jr.tail; + struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); + struct jobring *jr = &jr0[sec_idx]; + int head = jr->head; + int tail = jr->tail; int idx, i, found; void (*callback)(uint32_t status, void *arg); void *arg = NULL; @@ -253,7 +271,8 @@ static int jr_dequeue(void) uint32_t *addr; #endif - while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) { + while (sec_in32(®s->orsf) && CIRC_CNT(jr->head, jr->tail, + jr->size)) { found = 0; @@ -264,11 +283,11 @@ static int jr_dequeue(void) * depend on endianness of SEC block. */ #ifdef CONFIG_SYS_FSL_SEC_LE - addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc); - addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1; + addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc); + addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1; #elif defined(CONFIG_SYS_FSL_SEC_BE) - addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc); - addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1; + addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc); + addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1; #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */ op_desc = ((u64)sec_in32(addr_hi) << 32) | @@ -276,15 +295,15 @@ static int jr_dequeue(void) #else /* Read the 32 bit Descriptor address from Output Ring. */ - addr = (uint32_t *)&jr.output_ring[jr.tail].desc; + addr = (uint32_t *)&jr->output_ring[jr->tail].desc; op_desc = sec_in32(addr); #endif /* ifdef CONFIG_PHYS_64BIT */ - uint32_t status = sec_in32(&jr.output_ring[jr.tail].status); + uint32_t status = sec_in32(&jr->output_ring[jr->tail].status); - for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) { - idx = (tail + i) & (jr.size - 1); - if (op_desc == jr.info[idx].desc_phys_addr) { + for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) { + idx = (tail + i) & (jr->size - 1); + if (op_desc == jr->info[idx].desc_phys_addr) { found = 1; break; } @@ -294,9 +313,9 @@ static int jr_dequeue(void) if (!found) return -1; - jr.info[idx].op_done = 1; - callback = (void *)jr.info[idx].callback; - arg = jr.info[idx].arg; + jr->info[idx].op_done = 1; + callback = (void *)jr->info[idx].callback; + arg = jr->info[idx].arg; /* When the job on tail idx gets done, increment * tail till the point where job completed out of oredr has @@ -304,14 +323,14 @@ static int jr_dequeue(void) */ if (idx == tail) do { - tail = (tail + 1) & (jr.size - 1); - } while (jr.info[tail].op_done); + tail = (tail + 1) & (jr->size - 1); + } while (jr->info[tail].op_done); - jr.tail = tail; - jr.read_idx = (jr.read_idx + 1) & (jr.size - 1); + jr->tail = tail; + jr->read_idx = (jr->read_idx + 1) & (jr->size - 1); sec_out32(®s->orjr, 1); - jr.info[idx].op_done = 0; + jr->info[idx].op_done = 0; callback(status, arg); } @@ -327,7 +346,7 @@ static void desc_done(uint32_t status, void *arg) x->done = 1; } -int run_descriptor_jr(uint32_t *desc) +static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) { unsigned long long timeval = get_ticks(); unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); @@ -336,7 +355,7 @@ int run_descriptor_jr(uint32_t *desc) memset(&op, 0, sizeof(op)); - ret = jr_enqueue(desc, desc_done, &op); + ret = jr_enqueue(desc, desc_done, &op, sec_idx); if (ret) { debug("Error in SEC enq\n"); ret = JQ_ENQ_ERR; @@ -346,7 +365,7 @@ int run_descriptor_jr(uint32_t *desc) timeval = get_ticks(); timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); while (op.done != 1) { - ret = jr_dequeue(); + ret = jr_dequeue(sec_idx); if (ret) { debug("Error in SEC deq\n"); ret = JQ_DEQ_ERR; @@ -368,20 +387,30 @@ out: return ret; } -int jr_reset(void) +int run_descriptor_jr(uint32_t *desc) +{ + return run_descriptor_jr_idx(desc, 0); +} + +static inline int jr_reset_sec(uint8_t sec_idx) { - if (jr_hw_reset() < 0) + if (jr_hw_reset(sec_idx) < 0) return -1; /* Clean up the jobring structure maintained by software */ - jr_sw_cleanup(); + jr_sw_cleanup(sec_idx); return 0; } -int sec_reset(void) +int jr_reset(void) { - ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + return jr_reset_sec(0); +} + +static inline int sec_reset_idx(uint8_t sec_idx) +{ + ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); uint32_t mcfgr = sec_in32(&sec->mcfgr); uint32_t timeout = 100000; @@ -408,14 +437,13 @@ int sec_reset(void) return 0; } -static int instantiate_rng(void) +static int instantiate_rng(uint8_t sec_idx) { struct result op; u32 *desc; u32 rdsta_val; int ret = 0; - ccsr_sec_t __iomem *sec = - (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; @@ -432,7 +460,7 @@ static int instantiate_rng(void) flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); - ret = run_descriptor_jr(desc); + ret = run_descriptor_jr_idx(desc, sec_idx); if (ret) printf("RNG: Instantiation failed with error %x\n", ret); @@ -444,9 +472,14 @@ static int instantiate_rng(void) return ret; } -static u8 get_rng_vid(void) +int sec_reset(void) +{ + return sec_reset_idx(0); +} + +static u8 get_rng_vid(uint8_t sec_idx) { - ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); u32 cha_vid = sec_in32(&sec->chavid_ls); return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT; @@ -456,10 +489,9 @@ static u8 get_rng_vid(void) * By default, the TRNG runs for 200 clocks per sample; * 1200 clocks per sample generates better entropy. */ -static void kick_trng(int ent_delay) +static void kick_trng(int ent_delay, uint8_t sec_idx) { - ccsr_sec_t __iomem *sec = - (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; u32 val; @@ -486,11 +518,10 @@ static void kick_trng(int ent_delay) sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM); } -static int rng_init(void) +static int rng_init(uint8_t sec_idx) { int ret, ent_delay = RTSDCTL_ENT_DLY_MIN; - ccsr_sec_t __iomem *sec = - (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; @@ -509,7 +540,7 @@ static int rng_init(void) * Also, if a handle was instantiated, do not change * the TRNG parameters. */ - kick_trng(ent_delay); + kick_trng(ent_delay, sec_idx); ent_delay += 400; /* * if instantiate_rng(...) fails, the loop will rerun @@ -518,7 +549,7 @@ static int rng_init(void) * interval, leading to a sucessful initialization of * the RNG. */ - ret = instantiate_rng(); + ret = instantiate_rng(sec_idx); } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); if (ret) { printf("RNG: Failed to instantiate RNG\n"); @@ -531,9 +562,9 @@ static int rng_init(void) return ret; } -int sec_init(void) +int sec_init_idx(uint8_t sec_idx) { - ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); uint32_t mcr = sec_in32(&sec->mcfgr); int ret = 0; @@ -543,6 +574,11 @@ int sec_init(void) uint32_t liodn_s; #endif + if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) { + printf("SEC initialization failed\n"); + return -1; + } + /* * Modifying CAAM Read/Write Attributes * For LS2080A @@ -568,7 +604,7 @@ int sec_init(void) liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT; #endif - ret = jr_init(); + ret = jr_init(sec_idx); if (ret < 0) { printf("SEC initialization failed\n"); return -1; @@ -582,13 +618,18 @@ int sec_init(void) pamu_enable(); #endif - if (get_rng_vid() >= 4) { - if (rng_init() < 0) { - printf("RNG instantiation failed\n"); + if (get_rng_vid(sec_idx) >= 4) { + if (rng_init(sec_idx) < 0) { + printf("SEC%u: RNG instantiation failed\n", sec_idx); return -1; } - printf("SEC: RNG instantiated\n"); + printf("SEC%u: RNG instantiated\n", sec_idx); } return ret; } + +int sec_init(void) +{ + return sec_init_idx(0); +} diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 1642dbbf4c2..d897e572d6e 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -90,6 +90,9 @@ struct jobring { /* This ring can be on the stack */ struct jr_info info[JR_SIZE]; struct op_ring *output_ring; + /* Offset in CCSR to the SEC engine to which this JR belongs */ + uint32_t sec_offset; + }; struct result { diff --git a/include/fsl_sec.h b/include/fsl_sec.h index a52110a625c..bffabc89b99 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -294,8 +294,6 @@ struct sg_entry { #endif -int sec_init(void); - /* blob_dek: * Encapsulates the src in a secure blob and stores it dst * @src: reference to the plaintext @@ -305,6 +303,10 @@ int sec_init(void); */ int blob_dek(const u8 *src, u8 *dst, u8 len); +#if defined(CONFIG_PPC_C29X) +int sec_init_idx(uint8_t); +#endif +int sec_init(void); #endif #endif /* __FSL_SEC_H */ -- cgit v1.3.1 From 7942550a146f3eaf00add0e13442946365cc9775 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Fri, 29 Apr 2016 22:07:21 +0800 Subject: armv8: ls1043ardb: invert irq pin polarity for AQR105 PHY To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by setting relative bit in SCFG_INTPCR register, because AQR105 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie Reviewed-by: York Sun --- board/freescale/ls1043ardb/ls1043ardb.c | 4 ++++ include/configs/ls1043ardb.h | 1 + 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index b1691393e6e..14365207da1 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -82,6 +82,8 @@ int board_early_init_f(void) int board_init(void) { + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + #ifdef CONFIG_FSL_IFC init_final_memctl_regs(); #endif @@ -93,6 +95,8 @@ int board_init(void) #ifdef CONFIG_U_QE u_qe_init(); #endif + /* invert AQR105 IRQ pins polarity */ + out_be32(&scfg->intpcr, AQR105_IRQ_MASK); return 0; } diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 6d35be2e473..39687cfef4d 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -253,6 +253,7 @@ #define CONFIG_PHY_VITESSE #define CONFIG_PHY_REALTEK #define CONFIG_PHY_AQUANTIA +#define AQR105_IRQ_MASK 0x40000000 #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 -- cgit v1.3.1 From bc323b3fa7cbf1008f02d342c0505231961b5fa6 Mon Sep 17 00:00:00 2001 From: Po Liu Date: Wed, 18 May 2016 10:09:38 +0800 Subject: armv8: ls1043ardb: enable scsi command and pcie to sata converter Enable scsi command and pcie to sata chip 88SE9170. Signed-off-by: Po Liu Reviewed-by: York Sun --- include/configs/ls1043ardb.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'include') diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 39687cfef4d..aca8d95c153 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -286,6 +286,27 @@ #define CONFIG_USB_STORAGE #endif +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_CMD_SCSI +#ifndef CONFIG_CMD_FAT +#define CONFIG_CMD_FAT +#endif +#ifndef CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT2 +#endif +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 2 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define SCSI_VEND_ID 0x1b4b +#define SCSI_DEV_ID 0x9170 +#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#define CONFIG_PCI + #include #endif /* __LS1043ARDB_H__ */ -- cgit v1.3.1