From 331bee87868993f0ddd968b7b97716580fa3183b Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Wed, 28 Aug 2019 19:12:20 +0200 Subject: bmips: enable vr-3032u nand support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas --- include/configs/comtrend_vr3032u.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/comtrend_vr3032u.h b/include/configs/comtrend_vr3032u.h index e183288c5d1..d625101ecba 100644 --- a/include/configs/comtrend_vr3032u.h +++ b/include/configs/comtrend_vr3032u.h @@ -10,3 +10,8 @@ #define CONFIG_ENV_SIZE (8 * 1024) +#ifdef CONFIG_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif /* CONFIG_NAND */ -- cgit v1.3.1 From 9e484636f1ff5847293c04ceab90358315a42c2a Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Fri, 30 Aug 2019 11:52:59 +0200 Subject: mips: bmips: remove unneeded definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are no longer needed. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Daniel Schwierzeck --- include/configs/bmips_common.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'include') diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index 788f4af70da..ca079fa2e2c 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -14,10 +14,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } -/* RAM */ -#define CONFIG_SYS_MEMTEST_START 0xa0000000 -#define CONFIG_SYS_MEMTEST_END 0xa2000000 - /* Memory usage */ #define CONFIG_SYS_MAXARGS 24 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) -- cgit v1.3.1 From 55daf1c45c6fee60840842f86796368a766c01e9 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Fri, 30 Aug 2019 11:54:27 +0200 Subject: bmips: configs: switch to size definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Daniel Schwierzeck --- include/configs/bmips_bcm3380.h | 6 ++++-- include/configs/bmips_bcm6318.h | 6 ++++-- include/configs/bmips_bcm63268.h | 6 ++++-- include/configs/bmips_bcm6328.h | 6 ++++-- include/configs/bmips_bcm6338.h | 6 ++++-- include/configs/bmips_bcm6348.h | 6 ++++-- include/configs/bmips_bcm6358.h | 6 ++++-- include/configs/bmips_bcm6362.h | 8 +++++--- include/configs/bmips_bcm6368.h | 6 ++++-- include/configs/bmips_bcm6838.h | 6 ++++-- include/configs/bmips_common.h | 8 +++++--- include/configs/broadcom_bcm968380gerg.h | 2 +- include/configs/comtrend_ar5315u.h | 3 +-- include/configs/comtrend_ar5387un.h | 3 +-- include/configs/comtrend_ct5361.h | 3 +-- include/configs/comtrend_vr3032u.h | 2 +- include/configs/comtrend_wap5813n.h | 3 +-- include/configs/huawei_hg556a.h | 3 +-- include/configs/netgear_cg3100d.h | 3 +-- include/configs/netgear_dgnd3700v2.h | 5 ++--- include/configs/sagem_f@st1704.h | 3 +-- include/configs/sfr_nb4_ser.h | 3 +-- 22 files changed, 58 insertions(+), 45 deletions(-) (limited to 'include') diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h index e2f9e76a978..573ff3e4018 100644 --- a/include/configs/bmips_bcm3380.h +++ b/include/configs/bmips_bcm3380.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM3380_H #define __CONFIG_BMIPS_BCM3380_H +#include + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 166500000 @@ -13,11 +15,11 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM3380_H */ diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index 476aa51af30..c7e7119aafd 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM6318_H #define __CONFIG_BMIPS_BCM6318_H +#include + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 166500000 @@ -20,11 +22,11 @@ #define CONFIG_USB_OHCI_NEW /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6318_H */ diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index 1456b0ec479..45f26bb3097 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM63268_H #define __CONFIG_BMIPS_BCM63268_H +#include + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 @@ -20,11 +22,11 @@ #define CONFIG_USB_OHCI_NEW /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM63268_H */ diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index faf9abcc3e4..8d594387853 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM6328_H #define __CONFIG_BMIPS_BCM6328_H +#include + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 160000000 @@ -20,11 +22,11 @@ #define CONFIG_USB_OHCI_NEW /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6328_H */ diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h index 83050c94a6b..38dd9e3af3a 100644 --- a/include/configs/bmips_bcm6338.h +++ b/include/configs/bmips_bcm6338.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM6338_H #define __CONFIG_BMIPS_BCM6338_H +#include + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 120000000 @@ -13,11 +15,11 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #define CONFIG_SYS_FLASH_BASE 0xbfc00000 diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index 5eb8b0f9d09..061d6b25b71 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM6348_H #define __CONFIG_BMIPS_BCM6348_H +#include + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 128000000 @@ -18,11 +20,11 @@ #define CONFIG_USB_OHCI_NEW /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #define CONFIG_SYS_FLASH_BASE 0xbfc00000 diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index 7becf3fcb92..583217d2621 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM6358_H #define __CONFIG_BMIPS_BCM6358_H +#include + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 150000000 @@ -20,11 +22,11 @@ #define CONFIG_USB_OHCI_NEW /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #define CONFIG_SYS_FLASH_BASE 0xbe000000 diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index 60777207e1b..570bc3b33d3 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2018 Álvaro Fernández Rojas */ #ifndef __CONFIG_BMIPS_BCM6362_H #define __CONFIG_BMIPS_BCM6362_H +#include + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 @@ -20,11 +22,11 @@ #define CONFIG_USB_OHCI_NEW /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6362_H */ diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index 1a57476e055..ab5bdac7268 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM6368_H #define __CONFIG_BMIPS_BCM6368_H +#include + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 @@ -20,11 +22,11 @@ #define CONFIG_USB_OHCI_NEW /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #define CONFIG_SYS_FLASH_BASE 0xb8000000 diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h index d735c51efc8..f1ff05414d5 100644 --- a/include/configs/bmips_bcm6838.h +++ b/include/configs/bmips_bcm6838.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_BCM6838_H #define __CONFIG_BMIPS_BCM6838_H +#include + /* CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 160000000 @@ -13,11 +15,11 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6838_H */ diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index ca079fa2e2c..3cb2d4050d0 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_BMIPS_COMMON_H #define __CONFIG_BMIPS_COMMON_H +#include + /* ETH */ #define CONFIG_PHY_RESET_DELAY 20 #define CONFIG_SYS_RX_ETH_BUFFER 6 @@ -16,9 +18,9 @@ /* Memory usage */ #define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MALLOC_LEN SZ_2M +#define CONFIG_SYS_BOOTPARAMS_LEN SZ_128K +#define CONFIG_SYS_CBSIZE SZ_512 /* U-Boot */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/broadcom_bcm968380gerg.h b/include/configs/broadcom_bcm968380gerg.h index aa6ce67d533..b0e93376fe3 100644 --- a/include/configs/broadcom_bcm968380gerg.h +++ b/include/configs/broadcom_bcm968380gerg.h @@ -6,7 +6,7 @@ #include #include -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SIZE SZ_8K #ifdef CONFIG_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/comtrend_ar5315u.h b/include/configs/comtrend_ar5315u.h index a5eb3aea195..1da96c163a1 100644 --- a/include/configs/comtrend_ar5315u.h +++ b/include/configs/comtrend_ar5315u.h @@ -8,5 +8,4 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/comtrend_ar5387un.h b/include/configs/comtrend_ar5387un.h index 71c5ba45be5..73e6a5dac79 100644 --- a/include/configs/comtrend_ar5387un.h +++ b/include/configs/comtrend_ar5387un.h @@ -8,5 +8,4 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/comtrend_ct5361.h b/include/configs/comtrend_ct5361.h index da705923066..72f9ecbb06f 100644 --- a/include/configs/comtrend_ct5361.h +++ b/include/configs/comtrend_ct5361.h @@ -8,5 +8,4 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/comtrend_vr3032u.h b/include/configs/comtrend_vr3032u.h index d625101ecba..cb888056bcf 100644 --- a/include/configs/comtrend_vr3032u.h +++ b/include/configs/comtrend_vr3032u.h @@ -8,7 +8,7 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SIZE SZ_8K #ifdef CONFIG_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/comtrend_wap5813n.h b/include/configs/comtrend_wap5813n.h index 7070a1c757f..b67f6548e68 100644 --- a/include/configs/comtrend_wap5813n.h +++ b/include/configs/comtrend_wap5813n.h @@ -8,5 +8,4 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/huawei_hg556a.h b/include/configs/huawei_hg556a.h index 1c9bee6d58d..2aa5c666432 100644 --- a/include/configs/huawei_hg556a.h +++ b/include/configs/huawei_hg556a.h @@ -8,5 +8,4 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/netgear_cg3100d.h b/include/configs/netgear_cg3100d.h index d541e9cee83..e5a96015197 100644 --- a/include/configs/netgear_cg3100d.h +++ b/include/configs/netgear_cg3100d.h @@ -6,5 +6,4 @@ #include #include -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/netgear_dgnd3700v2.h b/include/configs/netgear_dgnd3700v2.h index 9edaec9bff5..3baa17ae618 100644 --- a/include/configs/netgear_dgnd3700v2.h +++ b/include/configs/netgear_dgnd3700v2.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2018 Álvaro Fernández Rojas */ #include @@ -8,5 +8,4 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/sagem_f@st1704.h b/include/configs/sagem_f@st1704.h index 7171dc6760d..5a526d9d8b3 100644 --- a/include/configs/sagem_f@st1704.h +++ b/include/configs/sagem_f@st1704.h @@ -6,5 +6,4 @@ #include #include -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/sfr_nb4_ser.h b/include/configs/sfr_nb4_ser.h index 1c9bee6d58d..2aa5c666432 100644 --- a/include/configs/sfr_nb4_ser.h +++ b/include/configs/sfr_nb4_ser.h @@ -8,5 +8,4 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_ENV_SIZE (8 * 1024) - +#define CONFIG_ENV_SIZE SZ_8K -- cgit v1.3.1 From f923c758e058e57b58e0ee780df4724fa023a958 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Fri, 30 Aug 2019 12:00:42 +0200 Subject: bmips: correct name characters MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas --- arch/mips/dts/brcm,bcm6362.dtsi | 2 +- arch/mips/dts/netgear,dgnd3700v2.dts | 2 +- board/netgear/dgnd3700v2/MAINTAINERS | 2 +- board/netgear/dgnd3700v2/dgnd3700v2.c | 2 +- include/dt-bindings/clock/bcm6362-clock.h | 2 +- include/dt-bindings/power-domain/bcm6362-power-domain.h | 2 +- include/dt-bindings/reset/bcm6362-reset.h | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/arch/mips/dts/brcm,bcm6362.dtsi b/arch/mips/dts/brcm,bcm6362.dtsi index 23c47963c34..71598f97b33 100644 --- a/arch/mips/dts/brcm,bcm6362.dtsi +++ b/arch/mips/dts/brcm,bcm6362.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2018 Álvaro Fernández Rojas */ #include diff --git a/arch/mips/dts/netgear,dgnd3700v2.dts b/arch/mips/dts/netgear,dgnd3700v2.dts index 2b72491f0b2..88fca647cde 100644 --- a/arch/mips/dts/netgear,dgnd3700v2.dts +++ b/arch/mips/dts/netgear,dgnd3700v2.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2018 Álvaro Fernández Rojas */ /dts-v1/; diff --git a/board/netgear/dgnd3700v2/MAINTAINERS b/board/netgear/dgnd3700v2/MAINTAINERS index 998077b69be..aaa51c177ea 100644 --- a/board/netgear/dgnd3700v2/MAINTAINERS +++ b/board/netgear/dgnd3700v2/MAINTAINERS @@ -1,5 +1,5 @@ NETGEAR DGND3700V2 BOARD -M: Álvaro Fernández Rojas +M: Álvaro Fernández Rojas S: Maintained F: board/netgear/dgnd3700v2/ F: include/configs/netgear_dgnd3700v2.h diff --git a/board/netgear/dgnd3700v2/dgnd3700v2.c b/board/netgear/dgnd3700v2/dgnd3700v2.c index f8fc70e28d3..6840a21001c 100644 --- a/board/netgear/dgnd3700v2/dgnd3700v2.c +++ b/board/netgear/dgnd3700v2/dgnd3700v2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2018 Álvaro Fernández Rojas */ #include diff --git a/include/dt-bindings/clock/bcm6362-clock.h b/include/dt-bindings/clock/bcm6362-clock.h index fed04e6b5f0..d3770c50490 100644 --- a/include/dt-bindings/clock/bcm6362-clock.h +++ b/include/dt-bindings/clock/bcm6362-clock.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2018 Álvaro Fernández Rojas * * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h */ diff --git a/include/dt-bindings/power-domain/bcm6362-power-domain.h b/include/dt-bindings/power-domain/bcm6362-power-domain.h index ddc123ea886..1a708a9ad23 100644 --- a/include/dt-bindings/power-domain/bcm6362-power-domain.h +++ b/include/dt-bindings/power-domain/bcm6362-power-domain.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2018 Álvaro Fernández Rojas */ #ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6362_H diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h index 6e257ce78f2..8202e499190 100644 --- a/include/dt-bindings/reset/bcm6362-reset.h +++ b/include/dt-bindings/reset/bcm6362-reset.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2018 Álvaro Fernández Rojas * * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h */ -- cgit v1.3.1 From 77ed3c42fee219fb50bca154b1ae36dbca8fc2e0 Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Wed, 25 Sep 2019 17:45:21 +0800 Subject: clk: add clock driver for MediaTek MT76x8 platform This patch adds a clock driver for MediaTek MT7628/7688 SoC. It provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Signed-off-by: Weijie Gao --- drivers/clk/Makefile | 1 + drivers/clk/mtmips/Makefile | 3 + drivers/clk/mtmips/clk-mt7628.c | 158 +++++++++++++++++++++++++++++++++ include/dt-bindings/clock/mt7628-clk.h | 37 ++++++++ 4 files changed, 199 insertions(+) create mode 100644 drivers/clk/mtmips/Makefile create mode 100644 drivers/clk/mtmips/clk-mt7628.c create mode 100644 include/dt-bindings/clock/mt7628-clk.h (limited to 'include') diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 8de67774680..06131edb9fe 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -16,6 +16,7 @@ obj-y += imx/ obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ +obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ obj-$(CONFIG_ARCH_MESON) += meson/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_SOCFPGA) += altera/ diff --git a/drivers/clk/mtmips/Makefile b/drivers/clk/mtmips/Makefile new file mode 100644 index 00000000000..e1938418dae --- /dev/null +++ b/drivers/clk/mtmips/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o diff --git a/drivers/clk/mtmips/clk-mt7628.c b/drivers/clk/mtmips/clk-mt7628.c new file mode 100644 index 00000000000..35780de8c49 --- /dev/null +++ b/drivers/clk/mtmips/clk-mt7628.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao + */ + +#include +#include +#include +#include +#include +#include + +/* SYSCFG0 */ +#define XTAL_40M_SEL BIT(6) + +/* CLKCFG0 */ +#define CLKCFG0_REG 0x0 +#define PERI_CLK_FROM_XTAL_SEL BIT(4) +#define CPU_PLL_FROM_BBP BIT(1) +#define CPU_PLL_FROM_XTAL BIT(0) + +/* CLKCFG1 */ +#define CLKCFG1_REG 0x4 + +#define CLK_SRC_CPU -1 +#define CLK_SRC_CPU_D2 -2 +#define CLK_SRC_SYS -3 +#define CLK_SRC_XTAL -4 +#define CLK_SRC_PERI -5 + +struct mt7628_clk_priv { + void __iomem *base; + int cpu_clk; + int sys_clk; + int xtal_clk; +}; + +static const int mt7628_clks[] = { + [CLK_SYS] = CLK_SRC_SYS, + [CLK_CPU] = CLK_SRC_CPU, + [CLK_XTAL] = CLK_SRC_XTAL, + [CLK_PWM] = CLK_SRC_PERI, + [CLK_MIPS_CNT] = CLK_SRC_CPU_D2, + [CLK_UART2] = CLK_SRC_PERI, + [CLK_UART1] = CLK_SRC_PERI, + [CLK_UART0] = CLK_SRC_PERI, + [CLK_SPI] = CLK_SRC_SYS, + [CLK_I2C] = CLK_SRC_PERI, +}; + +static ulong mt7628_clk_get_rate(struct clk *clk) +{ + struct mt7628_clk_priv *priv = dev_get_priv(clk->dev); + u32 val; + + if (clk->id >= ARRAY_SIZE(mt7628_clks)) + return 0; + + switch (mt7628_clks[clk->id]) { + case CLK_SRC_CPU: + return priv->cpu_clk; + case CLK_SRC_CPU_D2: + return priv->cpu_clk / 2; + case CLK_SRC_SYS: + return priv->sys_clk; + case CLK_SRC_XTAL: + return priv->xtal_clk; + case CLK_SRC_PERI: + val = readl(priv->base + CLKCFG0_REG); + if (val & PERI_CLK_FROM_XTAL_SEL) + return priv->xtal_clk; + else + return 40000000; + default: + return mt7628_clks[clk->id]; + } +} + +static int mt7628_clk_enable(struct clk *clk) +{ + struct mt7628_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id > 31) + return -1; + + setbits_32(priv->base + CLKCFG1_REG, BIT(clk->id)); + + return 0; +} + +static int mt7628_clk_disable(struct clk *clk) +{ + struct mt7628_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id > 31) + return -1; + + clrbits_32(priv->base + CLKCFG1_REG, BIT(clk->id)); + + return 0; +} + +const struct clk_ops mt7628_clk_ops = { + .enable = mt7628_clk_enable, + .disable = mt7628_clk_disable, + .get_rate = mt7628_clk_get_rate, +}; + +static int mt7628_clk_probe(struct udevice *dev) +{ + struct mt7628_clk_priv *priv = dev_get_priv(dev); + void __iomem *syscfg_base; + u32 val; + + priv->base = (void __iomem *)dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; + + syscfg_base = (void __iomem *)dev_remap_addr_index(dev, 1); + if (!syscfg_base) + return -EINVAL; + + val = readl(syscfg_base); + if (val & XTAL_40M_SEL) + priv->xtal_clk = 40000000; + else + priv->xtal_clk = 25000000; + + val = readl(priv->base + CLKCFG0_REG); + if (val & CPU_PLL_FROM_BBP) + priv->cpu_clk = 480000000; + else if (val & CPU_PLL_FROM_XTAL) + priv->cpu_clk = priv->xtal_clk; + else if (priv->xtal_clk == 40000000) + priv->cpu_clk = 580000000; /* (xtal_freq / 2) * 29 */ + else + priv->cpu_clk = 575000000; /* xtal_freq * 23 */ + + priv->sys_clk = priv->cpu_clk / 3; + + return 0; +} + +static const struct udevice_id mt7628_clk_ids[] = { + { .compatible = "mediatek,mt7628-clk" }, + { } +}; + +U_BOOT_DRIVER(mt7628_clk) = { + .name = "mt7628-clk", + .id = UCLASS_CLK, + .of_match = mt7628_clk_ids, + .probe = mt7628_clk_probe, + .priv_auto_alloc_size = sizeof(struct mt7628_clk_priv), + .ops = &mt7628_clk_ops, +}; diff --git a/include/dt-bindings/clock/mt7628-clk.h b/include/dt-bindings/clock/mt7628-clk.h new file mode 100644 index 00000000000..b5866fdc0e3 --- /dev/null +++ b/include/dt-bindings/clock/mt7628-clk.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * Author: Weijie Gao + */ + +#ifndef _DT_BINDINGS_MT7628_CLK_H_ +#define _DT_BINDINGS_MT7628_CLK_H_ + +/* Base clocks */ +#define CLK_SYS 34 +#define CLK_CPU 33 +#define CLK_XTAL 32 + +/* Peripheral clocks */ +#define CLK_PWM 31 +#define CLK_SDXC 30 +#define CLK_CRYPTO 29 +#define CLK_MIPS_CNT 28 +#define CLK_PCIE 26 +#define CLK_UPHY 25 +#define CLK_ETH 23 +#define CLK_UART2 20 +#define CLK_UART1 19 +#define CLK_SPI 18 +#define CLK_I2S 17 +#define CLK_I2C 16 +#define CLK_GDMA 14 +#define CLK_PIO 13 +#define CLK_UART0 12 +#define CLK_PCM 11 +#define CLK_MC 10 +#define CLK_INTC 9 +#define CLK_TIMER 8 + +#endif /* _DT_BINDINGS_MT7628_CLK_H_ */ -- cgit v1.3.1 From f7ae6b682c42a82a38ebeb3ea4a20f23ca623563 Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Wed, 25 Sep 2019 17:45:29 +0800 Subject: reset: add reset controller driver for MediaTek MIPS platform This patch adds reset controller driver for MediaTek MIPS platform and header file for mt7628. Signed-off-by: Weijie Gao --- drivers/reset/Kconfig | 7 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-mtmips.c | 82 ++++++++++++++++++++++++++++++++ include/dt-bindings/reset/mt7628-reset.h | 36 ++++++++++++++ 4 files changed, 126 insertions(+) create mode 100644 drivers/reset/reset-mtmips.c create mode 100644 include/dt-bindings/reset/mt7628-reset.h (limited to 'include') diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 976f3a701c5..cff00820e48 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -113,6 +113,13 @@ config RESET_MEDIATEK help Support for reset controller on MediaTek SoCs. +config RESET_MTMIPS + bool "Reset controller driver for MediaTek MIPS platform" + depends on DM_RESET && ARCH_MTMIPS + default y + help + Support for reset controller on MediaTek MIPS platform. + config RESET_SUNXI bool "RESET support for Allwinner SoCs" depends on DM_RESET && ARCH_SUNXI diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index f5875fce099..8102d8db291 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o +obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o diff --git a/drivers/reset/reset-mtmips.c b/drivers/reset/reset-mtmips.c new file mode 100644 index 00000000000..59734565d77 --- /dev/null +++ b/drivers/reset/reset-mtmips.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao + */ + +#include +#include +#include +#include +#include + +struct mtmips_reset_priv { + void __iomem *base; +}; + +static int mtmips_reset_request(struct reset_ctl *reset_ctl) +{ + return 0; +} + +static int mtmips_reset_free(struct reset_ctl *reset_ctl) +{ + return 0; +} + +static int mtmips_reset_assert(struct reset_ctl *reset_ctl) +{ + struct mtmips_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + setbits_32(priv->base, BIT(reset_ctl->id)); + + return 0; +} + +static int mtmips_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct mtmips_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + clrbits_32(priv->base, BIT(reset_ctl->id)); + + return 0; +} + +static const struct reset_ops mtmips_reset_ops = { + .request = mtmips_reset_request, + .free = mtmips_reset_free, + .rst_assert = mtmips_reset_assert, + .rst_deassert = mtmips_reset_deassert, +}; + +static int mtmips_reset_probe(struct udevice *dev) +{ + return 0; +} + +static int mtmips_reset_ofdata_to_platdata(struct udevice *dev) +{ + struct mtmips_reset_priv *priv = dev_get_priv(dev); + + priv->base = (void __iomem *)dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; + + return 0; +} + +static const struct udevice_id mtmips_reset_ids[] = { + { .compatible = "mediatek,mtmips-reset" }, + { } +}; + +U_BOOT_DRIVER(mtmips_reset) = { + .name = "mtmips-reset", + .id = UCLASS_RESET, + .of_match = mtmips_reset_ids, + .ofdata_to_platdata = mtmips_reset_ofdata_to_platdata, + .probe = mtmips_reset_probe, + .priv_auto_alloc_size = sizeof(struct mtmips_reset_priv), + .ops = &mtmips_reset_ops, +}; diff --git a/include/dt-bindings/reset/mt7628-reset.h b/include/dt-bindings/reset/mt7628-reset.h new file mode 100644 index 00000000000..2a674c1ea72 --- /dev/null +++ b/include/dt-bindings/reset/mt7628-reset.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * Author: Weijie Gao + */ + +#ifndef _DT_BINDINGS_MT7628_RESET_H_ +#define _DT_BINDINGS_MT7628_RESET_H_ + +#define MT7628_PWM_RST 31 +#define MT7628_SDXC_RST 30 +#define MT7628_CRYPTO_RST 29 +#define MT7628_AUX_STCK_RST 28 +#define MT7628_PCIE_RST 26 +#define MT7628_EPHY_RST 24 +#define MT7628_ETH_RST 23 +#define MT7628_UPHY_RST 22 +#define MT7628_UART2_RST 20 +#define MT7628_UART1_RST 19 +#define MT7628_SPI_RST 18 +#define MT7628_I2S_RST 17 +#define MT7628_I2C_RST 16 +#define MT7628_GDMA_RST 14 +#define MT7628_PIO_RST 13 +#define MT7628_UART0_RST 12 +#define MT7628_PCM_RST 11 +#define MT7628_MC_RST 10 +#define MT7628_INT_RST 9 +#define MT7628_TIMER_RST 8 +#define MT7628_HIF_RST 5 +#define MT7628_WIFI_RST 4 +#define MT7628_SPIS_RST 3 +#define MT7628_SYS_RST 0 + +#endif /* _DT_BINDINGS_MT7628_RESET_H_ */ -- cgit v1.3.1 From 443a206386eada780c9a63026af23ffcf943c0b4 Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Wed, 25 Sep 2019 17:45:42 +0800 Subject: mips: mtmips: change baudrate table for all boards This patch changes baudrate table for all boards preparing for using mtk highspeed uart driver. Signed-off-by: Weijie Gao --- include/configs/gardena-smart-gateway-mt7688.h | 2 +- include/configs/linkit-smart-7688.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index b3b89d2ab9e..e83a96ad5e1 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -22,7 +22,7 @@ /* UART */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ - 230400, 500000, 1500000 } + 230400, 460800, 921600 } /* RAM */ #define CONFIG_SYS_MEMTEST_START 0x80100000 diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 2adf38545a0..4d30d98abfa 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -22,7 +22,7 @@ /* UART */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ - 230400, 500000, 1500000 } + 230400, 460800, 921600 } /* RAM */ #define CONFIG_SYS_MEMTEST_START 0x80100000 -- cgit v1.3.1