From 19c8fc77e1d3ff45d3ea60e4355039a3a54d4a93 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 12 May 2018 11:56:10 +0200 Subject: fdt: Add another Altera Arria10 clock init compatible The DT bindings for the Arria10 clock init have changed, add another compatible to make them work with U-Boot until a proper clock driver gets written. Signed-off-by: Marek Vasut Cc: Tom Rini Cc: Chin Liang See Cc: Dinh Nguyen --- lib/fdtdec.c | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 69bf12623e0..f4e8dbf699a 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -72,6 +72,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"), COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"), COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"), + COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init") }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- cgit v1.3.1