From 20ecfbe93175e84dbf597d39a6ddeed29099dd73 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 2 Mar 2021 09:36:23 -0500 Subject: configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini --- scripts/config_whitelist.txt | 51 -------------------------------------------- 1 file changed, 51 deletions(-) (limited to 'scripts') diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c8c87900ce8..e98185c0642 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -78,7 +78,6 @@ CONFIG_AT91_GPIO_PULLUP CONFIG_AT91_LED CONFIG_AT91_WANTS_COMMON_PHY CONFIG_ATAPI -CONFIG_ATM CONFIG_ATMEL_LCD CONFIG_ATMEL_LCD_BGR555 CONFIG_ATMEL_LCD_RGB565 @@ -615,8 +614,6 @@ CONFIG_HAS_ETH0 CONFIG_HAS_ETH1 CONFIG_HAS_ETH2 CONFIG_HAS_ETH3 -CONFIG_HAS_ETH5 -CONFIG_HAS_ETH7 CONFIG_HAS_FEC CONFIG_HAS_FSL_DR_USB CONFIG_HAS_FSL_MPH_USB @@ -1276,7 +1273,6 @@ CONFIG_POST_WATCHDOG CONFIG_POWER CONFIG_POWER_FSL CONFIG_POWER_FSL_MC13892 -CONFIG_POWER_FSL_MC34704 CONFIG_POWER_HI6553 CONFIG_POWER_I2C CONFIG_POWER_LTC3676 @@ -1387,7 +1383,6 @@ CONFIG_RTC_DS1388 CONFIG_RTC_DS1388_TCR_VAL CONFIG_RTC_DS3231 CONFIG_RTC_FTRTC010 -CONFIG_RTC_IMXDI CONFIG_RTC_M41T11 CONFIG_RTC_MC13XXX CONFIG_RTC_MCFRRTC @@ -1696,7 +1691,6 @@ CONFIG_SYS_BAUDRATE_TABLE CONFIG_SYS_BCSR CONFIG_SYS_BCSR_ADDR CONFIG_SYS_BCSR_BASE -CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_SIZE CONFIG_SYS_BD_REV CONFIG_SYS_BFTIC3_BASE @@ -1968,8 +1962,6 @@ CONFIG_SYS_DDRTC CONFIG_SYS_DDRUA CONFIG_SYS_DDR_BLOCK1_SIZE CONFIG_SYS_DDR_BLOCK2_BASE -CONFIG_SYS_DDR_CDR_1 -CONFIG_SYS_DDR_CDR_2 CONFIG_SYS_DDR_CFG_1A CONFIG_SYS_DDR_CFG_1B CONFIG_SYS_DDR_CFG_2 @@ -1986,7 +1978,6 @@ CONFIG_SYS_DDR_CONFIG CONFIG_SYS_DDR_CONFIG_2 CONFIG_SYS_DDR_CONFIG_256 CONFIG_SYS_DDR_CONTROL -CONFIG_SYS_DDR_CONTROL2 CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CPO CONFIG_SYS_DDR_CS0_BNDS @@ -2000,8 +1991,6 @@ CONFIG_SYS_DDR_CS2_CONFIG CONFIG_SYS_DDR_CS3_BNDS CONFIG_SYS_DDR_CS3_CONFIG CONFIG_SYS_DDR_DATA_INIT -CONFIG_SYS_DDR_ERR_DIS -CONFIG_SYS_DDR_ERR_INT_EN CONFIG_SYS_DDR_INIT_ADDR CONFIG_SYS_DDR_INIT_EXT_ADDR CONFIG_SYS_DDR_INTERVAL @@ -2027,21 +2016,14 @@ CONFIG_SYS_DDR_MODE_2_900 CONFIG_SYS_DDR_MODE_CONTROL CONFIG_SYS_DDR_MODE_CTL CONFIG_SYS_DDR_MODE_WEAK -CONFIG_SYS_DDR_OCD_CTRL -CONFIG_SYS_DDR_OCD_STATUS CONFIG_SYS_DDR_RAW_TIMING CONFIG_SYS_DDR_RCW_1 CONFIG_SYS_DDR_RCW_2 -CONFIG_SYS_DDR_SBE CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_CFG CONFIG_SYS_DDR_SDRAM_CFG2 -CONFIG_SYS_DDR_SDRAM_CFG_2 CONFIG_SYS_DDR_SDRAM_CLK_CNTL -CONFIG_SYS_DDR_SDRAM_INTERVAL -CONFIG_SYS_DDR_SDRAM_MODE -CONFIG_SYS_DDR_SDRAM_MODE_2 CONFIG_SYS_DDR_SIZE CONFIG_SYS_DDR_SR_CNTR CONFIG_SYS_DDR_TIMING_0 @@ -2818,7 +2800,6 @@ CONFIG_SYS_LBC0_BASE CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC1_BASE CONFIG_SYS_LBC1_BASE_PHYS -CONFIG_SYS_LBCR_ADDR CONFIG_SYS_LBC_ADDR CONFIG_SYS_LBC_CACHE_BASE CONFIG_SYS_LBC_FLASH_BASE @@ -2894,8 +2875,6 @@ CONFIG_SYS_MAX_MTD_BANKS CONFIG_SYS_MAX_NAND_CHIPS CONFIG_SYS_MAX_NAND_DEVICE CONFIG_SYS_MAX_PCI_EPS -CONFIG_SYS_MB862xx_CCF -CONFIG_SYS_MB862xx_MMR CONFIG_SYS_MBAR CONFIG_SYS_MBAR2 CONFIG_SYS_MCATT0_VAL @@ -3099,7 +3078,6 @@ CONFIG_SYS_NAND_REGS_BASE CONFIG_SYS_NAND_SELECT_DEVICE CONFIG_SYS_NAND_SIZE CONFIG_SYS_NAND_SPL_KERNEL_OFFS -CONFIG_SYS_NAND_SPL_SIZE CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_NAND_U_BOOT_RELOC CONFIG_SYS_NAND_U_BOOT_RELOC_SP @@ -3700,8 +3678,6 @@ CONFIG_SYS_UART_PORT CONFIG_SYS_UBOOT_BASE CONFIG_SYS_UBOOT_END CONFIG_SYS_UBOOT_START -CONFIG_SYS_UCC_RGMII_MODE -CONFIG_SYS_UCC_RMII_MODE CONFIG_SYS_UDELAY_BASE CONFIG_SYS_UEC CONFIG_SYS_UEC1_ETH_TYPE @@ -3718,34 +3694,8 @@ CONFIG_SYS_UEC2_PHY_ADDR CONFIG_SYS_UEC2_RX_CLK CONFIG_SYS_UEC2_TX_CLK CONFIG_SYS_UEC2_UCC_NUM -CONFIG_SYS_UEC3_ETH_TYPE -CONFIG_SYS_UEC3_INTERFACE_SPEED -CONFIG_SYS_UEC3_INTERFACE_TYPE CONFIG_SYS_UEC3_PHY_ADDR -CONFIG_SYS_UEC3_RX_CLK -CONFIG_SYS_UEC3_TX_CLK -CONFIG_SYS_UEC3_UCC_NUM -CONFIG_SYS_UEC4_ETH_TYPE -CONFIG_SYS_UEC4_INTERFACE_SPEED -CONFIG_SYS_UEC4_INTERFACE_TYPE CONFIG_SYS_UEC4_PHY_ADDR -CONFIG_SYS_UEC4_RX_CLK -CONFIG_SYS_UEC4_TX_CLK -CONFIG_SYS_UEC4_UCC_NUM -CONFIG_SYS_UEC6_ETH_TYPE -CONFIG_SYS_UEC6_INTERFACE_SPEED -CONFIG_SYS_UEC6_INTERFACE_TYPE -CONFIG_SYS_UEC6_PHY_ADDR -CONFIG_SYS_UEC6_RX_CLK -CONFIG_SYS_UEC6_TX_CLK -CONFIG_SYS_UEC6_UCC_NUM -CONFIG_SYS_UEC8_ETH_TYPE -CONFIG_SYS_UEC8_INTERFACE_SPEED -CONFIG_SYS_UEC8_INTERFACE_TYPE -CONFIG_SYS_UEC8_PHY_ADDR -CONFIG_SYS_UEC8_RX_CLK -CONFIG_SYS_UEC8_TX_CLK -CONFIG_SYS_UEC8_UCC_NUM CONFIG_SYS_UECx_PHY_ADDR CONFIG_SYS_UHC0_EHCI_BASE CONFIG_SYS_UHC1_EHCI_BASE @@ -3931,7 +3881,6 @@ CONFIG_USB_BOOTING CONFIG_USB_DEVICE CONFIG_USB_DEV_BASE CONFIG_USB_DEV_PULLUP_GPIO -CONFIG_USB_DWC2_REG_ADDR CONFIG_USB_EHCI_ARMADA100 CONFIG_USB_EHCI_BASE CONFIG_USB_EHCI_BASE_LIST -- cgit v1.2.3 From 504debcd8c1f4d86682ed8f3c7472284a2b6e822 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Thu, 11 Feb 2021 13:28:49 +0100 Subject: configs: fsl: move bootrom specific defines to Kconfig Moves below bootrom specific defines to Kconfig: CONFIG_SYS_FSL_BOOTROM_BASE CONFIG_SYS_FSL_BOOTROM_SIZE Signed-off-by: Rajesh Bhagat Reviewed-by: Priyanka Jain --- scripts/config_whitelist.txt | 2 -- 1 file changed, 2 deletions(-) (limited to 'scripts') diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e98185c0642..3ba2781e5a3 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2251,8 +2251,6 @@ CONFIG_SYS_FSL_AIOP1_SIZE CONFIG_SYS_FSL_B4860QDS_XFI_ERR CONFIG_SYS_FSL_BMAN_ADDR CONFIG_SYS_FSL_BMAN_OFFSET -CONFIG_SYS_FSL_BOOTROM_BASE -CONFIG_SYS_FSL_BOOTROM_SIZE CONFIG_SYS_FSL_CCSR_BASE CONFIG_SYS_FSL_CCSR_GUR_BE CONFIG_SYS_FSL_CCSR_GUR_LE -- cgit v1.2.3 From c8c0170f192e975c85aadb8ebcfb4d1ac3cfc5f2 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 15 Feb 2021 09:46:14 +0100 Subject: configs: fsl: move via specific defines to Kconfig Moves below via specific defines to Kconfig: CONFIG_FSL_VIA Signed-off-by: Rajesh Bhagat [Rebased] Signed-off-by: Priyanka Jain --- scripts/config_whitelist.txt | 1 - 1 file changed, 1 deletion(-) (limited to 'scripts') diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 3ba2781e5a3..e793cd1169f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -551,7 +551,6 @@ CONFIG_FSL_SERDES2 CONFIG_FSL_SGMII_RISER CONFIG_FSL_TBCLK_EXTRA_DIV CONFIG_FSL_TRUST_ARCH_v1 -CONFIG_FSL_VIA CONFIG_FSMC_NAND_BASE CONFIG_FSMTDBLK CONFIG_FSNOTIFY -- cgit v1.2.3 From 9773ebcfbca23c7d6fe1dc202913b005bc23cc89 Mon Sep 17 00:00:00 2001 From: Dalon Westergreen Date: Mon, 1 Mar 2021 20:04:16 +0800 Subject: Makefile: socfpga: Add target to generate hex output for combined spl and dtb Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel SOCFPGA SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex" is hex formatted spl with and offset of CONFIG_SPL_TEXT_BASE. It combines the spl image and dtb. "u-boot-spl-dtb.hex" is needed to generate the final configuration bitstream for Intel SOCFPGA SOC64 devices. Signed-off-by: Dalon Westergreen Signed-off-by: Siew Chin Lim --- scripts/Makefile.spl | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'scripts') diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index ea4e045769c..1fd63efdfd3 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -229,6 +229,8 @@ ifneq ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),) INPUTS-y += $(obj)/$(SPL_BIN).sfp endif +INPUTS-$(CONFIG_TARGET_SOCFPGA_SOC64) += $(obj)/u-boot-spl-dtb.hex + ifdef CONFIG_ARCH_SUNXI INPUTS-y += $(obj)/sunxi-spl.bin @@ -389,6 +391,11 @@ $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE MKIMAGEFLAGS_sunxi-spl.bin = -T sunxi_egon \ -n $(CONFIG_DEFAULT_DEVICE_TREE) +OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE) + +$(obj)/u-boot-spl-dtb.hex: $(obj)/u-boot-spl-dtb.bin FORCE + $(call if_changed,objcopy) + $(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE $(call if_changed,mkimage) -- cgit v1.2.3 From 15942805b7efe47e186d8b30ec378666561ad1f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 5 Mar 2021 15:52:42 +0100 Subject: arm: mvebu: a38x: Remove dead code ARMADA_39X MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Config option ARMADA_39X is never set so remove all dead code hidden under ifdef CONFIG_ARMADA_39X blocks. Also remove useless checks for CONFIG_ARMADA_38X define as this macro is always defined for a38x code path. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- scripts/config_whitelist.txt | 1 - 1 file changed, 1 deletion(-) (limited to 'scripts') diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e793cd1169f..819e362e5b5 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -43,7 +43,6 @@ CONFIG_ARC_MMU_VER CONFIG_ARMADA100 CONFIG_ARMADA100_FEC CONFIG_ARMADA168 -CONFIG_ARMADA_39X CONFIG_ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_MAX_SIZE CONFIG_ARMV7_SECURE_RESERVE_SIZE -- cgit v1.2.3 From 6ad0769c8e76e4abe321f59061ad8e35d950bca3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 15 Mar 2021 10:50:47 -0400 Subject: configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini --- scripts/config_whitelist.txt | 1 - 1 file changed, 1 deletion(-) (limited to 'scripts') diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 819e362e5b5..43295eec7d4 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3941,7 +3941,6 @@ CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP -CONFIG_VID CONFIG_VIDEO_BCM2835 CONFIG_VIDEO_BMP_LOGO CONFIG_VIDEO_CORALP -- cgit v1.2.3