From 63b2316c5c4ba0e47d1f69ef1372db4fd89b6bf5 Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Fri, 11 Aug 2017 11:09:14 +0530 Subject: fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar Signed-off-by: Prabhakar Kushwaha [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun --- scripts/config_whitelist.txt | 1 - 1 file changed, 1 deletion(-) (limited to 'scripts') diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 9ce0c3f039f..9619db69283 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2435,7 +2435,6 @@ CONFIG_SYS_CACHE_STASHING CONFIG_SYS_CADMUS_BASE_REG CONFIG_SYS_CBSIZE CONFIG_SYS_CCCR -CONFIG_SYS_CCI400_ADDR CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_HIGH -- cgit v1.2.3