From 84b124db3584d8b3f1a42c1506983323bce9983f Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@kernel.org>
Date: Tue, 23 Apr 2019 16:55:03 -0500
Subject: dm: cache: Create a uclass for cache

The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.

Add a uclass and a test for cache.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 test/dm/cache.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 test/dm/cache.c

(limited to 'test')

diff --git a/test/dm/cache.c b/test/dm/cache.c
new file mode 100644
index 00000000000..d4144aab76f
--- /dev/null
+++ b/test/dm/cache.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+
+static int dm_test_reset(struct unit_test_state *uts)
+{
+	struct udevice *dev_cache;
+	struct cache_info;
+
+	ut_assertok(uclass_get_device(UCLASS_CACHE, 0, &dev_cache));
+	ut_assertok(cache_get_info(dev, &info));
+
+	return 0;
+}
+DM_TEST(dm_test_reset, DM_TESTF_SCAN_FDT);
-- 
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