// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2026 MediaTek Inc.
 * Author: Macpaul Lin <macpaul.lin@mediatek.com>
 */

#include <dt-bindings/clock/mediatek,mt8189-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "mediatek,mt8189";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
	};

	clk26m: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x000>;
			enable-method = "psci";
			capacity-dmips-mhz = <282>;
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <282>;
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x200>;
			enable-method = "psci";
			capacity-dmips-mhz = <282>;
		};

		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x300>;
			enable-method = "psci";
			capacity-dmips-mhz = <282>;
		};

		cpu4: cpu@400 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x400>;
			enable-method = "psci";
			capacity-dmips-mhz = <282>;
		};

		cpu5: cpu@500 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x500>;
			enable-method = "psci";
			capacity-dmips-mhz = <282>;
		};

		cpu6: cpu@600 {
			device_type = "cpu";
			compatible = "arm,cortex-a78";
			reg = <0x600>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
		};

		cpu7: cpu@700 {
			device_type = "cpu";
			compatible = "arm,cortex-a78";
			reg = <0x700>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};

				core4 {
					cpu = <&cpu4>;
				};

				core5 {
					cpu = <&cpu5>;
				};

				core6 {
					cpu = <&cpu6>;
				};

				core7 {
					cpu = <&cpu7>;
				};
			};
		};
	};

	memory: memory@40000000 {
		device_type = "memory";
		/* This memory size is filled in by the bootloader */
		reg = <0 0x40000000 0 0>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		watchdog: watchdog@1c00a000 {
			compatible = "mediatek,mt8391-wdt",
				     "mediatek,wdt";
			reg = <0 0x1c00a000 0 0x100>;
			status = "disabled";
		};

		gic: interrupt-controller@c000000 {
			compatible = "arm,gic-v3";
			reg = <0 0xc000000 0 0x40000>, /* distributor */
			      <0 0xc040000 0 0x200000>; /* redistributor */
			interrupt-parent = <&gic>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
			interrupt-controller;
			#interrupt-cells = <4>;
			#redistributor-regions = <1>;

			ppi-partitions {
				ppi_cluster0: interrupt-partition-0 {
					affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
				};

				ppi_cluster1: interrupt-partition-1 {
					affinity = <&cpu6 &cpu7>;
				};
			};
		};

		uart0: serial@11001000 {
			compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart";
			reg = <0 0x11001000 0 0x1000>;
			interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART0>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		mmc0: mmc@11230000 {
			compatible = "mediatek,mt8189-mmc";
			reg = <0 0x11230000 0 0x10000>,
			      <0 0x11e70000 0 0x1000>;
			clocks = <&topckgen_clk CLK_TOP_MSDC50_0_SEL>,
				 <&pericfg_ao_clk CLK_PERAO_MSDC0_H>,
				 <&pericfg_ao_clk CLK_PERAO_MSDC0>;
			clock-names = "source", "hclk", "source_cg";
			interrupts = <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH 0>;
			status = "disabled";
		};

		mmc1: mmc@11240000 {
			compatible = "mediatek,mt8189-mmc";
			reg = <0 0x11240000 0 0x1000>,
			      <0 0x11d80000 0 0x1000>;
			clocks = <&topckgen_clk CLK_TOP_MSDC30_1_SEL>,
				 <&pericfg_ao_clk CLK_PERAO_MSDC1_H>,
				 <&pericfg_ao_clk CLK_PERAO_MSDC1>;
			clock-names = "source", "hclk", "source_cg";
			interrupts = <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH 0>;
			status = "disabled";
		};

		clock-controller@1000c000 {
			compatible = "mediatek,mt8189-apmixedsys", "syscon";
			reg = <0 0x1000c000 0 0x1000>;
			#clock-cells = <1>;
		};

		clock-controller@14000000 {
			compatible = "mediatek,mt8189-dispsys", "syscon";
			reg = <0 0x14000000 0 0x1000>;
			#clock-cells = <1>;
		};

		clock-controller@1e980000 {
			compatible = "mediatek,mt8189-gce-d", "syscon";
			reg = <0 0x1e980000 0 0x1000>;
			#clock-cells = <1>;
		};

		clock-controller@1e990000 {
			compatible = "mediatek,mt8189-gce-m", "syscon";
			reg = <0 0x1e990000 0 0x1000>;
			#clock-cells = <1>;
		};

		clock-controller@1e800000 {
			compatible = "mediatek,mt8189-mm-infra", "syscon";
			reg = <0 0x1e800000 0 0x1000>;
			#clock-cells = <1>;
		};

		pericfg_ao_clk: clock-controller@11036000 {
			compatible = "mediatek,mt8189-peri-ao", "syscon";
			reg = <0 0x11036000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		topckgen_clk: clock-controller@10000000 {
			compatible = "mediatek,mt8189-topckgen", "syscon";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		pio: pinctrl@10005000 {
			compatible = "mediatek,mt8189-pinctrl";
			reg = <0 0x10005000 0 0x1000>,
			      <0 0x11b50000 0 0x1000>,
			      <0 0x11c50000 0 0x1000>,
			      <0 0x11c60000 0 0x1000>,
			      <0 0x11d20000 0 0x1000>,
			      <0 0x11d30000 0 0x1000>,
			      <0 0x11d40000 0 0x1000>,
			      <0 0x11e20000 0 0x1000>,
			      <0 0x11e30000 0 0x1000>,
			      <0 0x11f20000 0 0x1000>,
			      <0 0x11ce0000 0 0x1000>,
			      <0 0x11de0000 0 0x1000>,
			      <0 0x11e60000 0 0x1000>,
			      <0 0x1c01e000 0 0x1000>,
			      <0 0x11f00000 0 0x1000>;
			reg-names = "base",
				    "lm",
				    "rb0",
				    "rb1",
				    "bm0",
				    "bm1",
				    "bm2",
				    "lt0",
				    "lt1",
				    "rt",
				    "eint0",
				    "eint1",
				    "eint2",
				    "eint3",
				    "eint4";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pio 0 0 182>;
			interrupt-controller;
			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
			#interrupt-cells = <2>;
		};

		pwrap: pwrap@1cc04000 {
			compatible = "mediatek,mt8189-pwrap", "mediatek,mt8195-pwrap", "syscon";
			reg = <0 0x1cc04000 0 0x1000>;
			reg-names = "pwrap";
			assigned-clocks = <&vlpckgen_clk CLK_VLP_CK_PWRAP_ULPOSC_SEL>;
			assigned-clock-parents = <&topckgen_clk CLK_TOP_OSC_D10>;
			clocks =  <&vlpcfg_ao_clk CLK_VLPCFG_REG_PMIF_SPMI_M_SYS>,
				  <&vlpcfg_ao_clk CLK_VLPCFG_REG_PMIF_SPMI_M_TMR>;
			clock-names = "spi", "wrap";
			interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
		};

		vlpcfg_ao_clk: clock-controller@1c00c000 {
			compatible = "mediatek,mt8189-vlpcfg-ao", "syscon";
			reg = <0 0x1c00c000 0 0x1000>;
			#clock-cells = <1>;
		};

		vlpckgen_clk: clock-controller@1c012000 {
			compatible = "mediatek,mt8189-vlpckgen", "syscon";
			reg = <0 0x1c012000 0 0x1000>;
			#clock-cells = <1>;
		};
	};
};