// SPDX-License-Identifier: GPL-2.0-or-later /* * (C) Copyright 2024 - Analog Devices, Inc. */ / { gic: interrupt-controller@310B2000 { compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x310B2000 0x1000>, <0x310B4000 0x100>; }; soc { mmc: mmc0@31010000 { compatible = "snps,dw-mshc"; reg = <0x31010000 0x400>; pinctrl-names = "default"; pinctrl-0 = <&mmc_default>; bus-width = <4>; fifo-depth = <128>; clock-names = "biu", "ciu"; max-frequency = <52000000>; status = "disabled"; }; usb0: musb@310c1000 { compatible = "adi,sc5xx-musb"; reg = <0x310c1000 0x390>; interrupts = , ; interrupt-names = "mc", "dma"; status = "okay"; }; }; }; &timer0 { clocks = <&clk ADSP_SC57X_CLK_CGU0_SCLK0>; }; &pinctrl0 { mmc_default: mmc_pins { adi,pins = , , , , , , , , , , ; }; eth0_default: eth0_pins { adi,pins = , , , , , , , , , , , , , ; }; uart0_default: uart0_pins { bootph-pre-ram; adi,pins = , ; }; spi2_default: spi2_pins { adi,pins = , , , , , ; }; }; &pinctrl0 { adi,npins = <92>; }; &gpio0 { adi,ngpios = <92>; }; &clk { compatible = "adi,sc57x-clocks"; }; &uart0 { clocks = <&clk ADSP_SC57X_CLK_CGU0_SCLK0>; }; &spi2 { clocks = <&clk ADSP_SC57X_CLK_CGU0_SCLK1>; reg = <0x31044000 0x1000>; }; &wdog { clocks = <&clk ADSP_SC57X_CLK_CGU0_SCLK0>; }; ð0 { reg = <0x3100C000 0x1000>; }; &mmc { clocks = <&dummy>, <&clk ADSP_SC57X_CLK_CGU0_SCLK0>; }; &i2c0 { clocks = <&clk ADSP_SC57X_CLK_CGU0_SCLK0>; }; &i2c1 { clocks = <&clk ADSP_SC57X_CLK_CGU0_SCLK0>; }; &i2c2 { clocks = <&clk ADSP_SC57X_CLK_CGU0_SCLK0>; };