if ARCH_OMAP2PLUS choice prompt "OMAP2+ platform select" default OMAP34XX config OMAP34XX bool "OMAP34XX SoC" select ARM_CORTEX_A8_CVE_2017_5715 select ARM_ERRATA_430973 select ARM_ERRATA_454179 select ARM_ERRATA_621766 select ARM_ERRATA_725233 select SPL_USE_TINY_PRINTF if SPL imply NAND_OMAP_GPMC imply SPL_FS_EXT4 imply SPL_FS_FAT imply SPL_GPIO imply SPL_I2C imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBDISK_SUPPORT imply SPL_LIBGENERIC_SUPPORT imply SPL_MMC imply SPL_NAND_SUPPORT imply SPL_OMAP3_ID_NAND imply SPL_POWER imply SPL_SERIAL imply SYS_I2C_OMAP24XX imply SYS_THUMB_BUILD imply TWL4030_POWER config OMAP54XX bool "OMAP54XX SoC" select ARM_CORTEX_A15_CVE_2017_5715 select ARM_ERRATA_798870 select DM_EVENT select SYS_THUMB_BUILD imply NAND_OMAP_ELM imply NAND_OMAP_GPMC imply SPL_DISPLAY_PRINT imply SPL_ENV_SUPPORT imply SPL_FS_EXT4 imply SPL_FS_FAT imply SPL_GPIO imply SPL_I2C imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBDISK_SUPPORT imply SPL_LIBGENERIC_SUPPORT imply SPL_MMC imply SPL_NAND_AM33XX_BCH imply SPL_NAND_AM33XX_BCH imply SPL_NAND_SUPPORT imply SPL_POWER imply SPL_SERIAL imply SYS_I2C_OMAP24XX config AM43XX bool "AM43XX SoC" select SPECIFY_CONSOLE_INDEX select SYS_L2_PL310 if !SYS_L2CACHE_OFF imply NAND_OMAP_ELM imply NAND_OMAP_GPMC imply SPL_DM imply SPL_DM_SEQ_ALIAS imply SPL_NAND_AM33XX_BCH imply SPL_NAND_SUPPORT imply SPL_OF_CONTROL imply SPL_OF_TRANSLATE imply SPL_SEPARATE_BSS imply SPL_SYS_MALLOC_SIMPLE imply SYS_I2C_OMAP24XX imply SYS_THUMB_BUILD help Support for AM43xx SOC from Texas Instruments. The AM43xx high performance SOC features a Cortex-A9 ARM core, a quad core PRU-ICSS for industrial Ethernet protocols, dual camera support, optional 3D graphics and an optional customer programmable secure boot. config AM33XX bool "AM33XX SoC" select ARM_CORTEX_A8_CVE_2017_5715 select DM_EVENT select SPECIFY_CONSOLE_INDEX imply NAND_OMAP_ELM imply NAND_OMAP_GPMC imply SKIP_LOWLEVEL_INIT imply SPL_NAND_AM33XX_BCH imply SPL_NAND_SUPPORT imply SYS_I2C_OMAP24XX imply SYS_THUMB_BUILD imply SPL_USE_TINY_PRINTF help Support for AM335x SOC from Texas Instruments. The AM335x high performance SOC features a Cortex-A8 ARM core, a dual core PRU-ICSS for industrial Ethernet protocols, optional 3D graphics and an optional customer programmable secure boot. endchoice config SYS_MPUCLK int "MPU CLK speed" depends on AM33XX default 500 help Defines the MPU clock speed (in MHz). config SYS_OMAP_ABE_SYSCK bool config TI_SECURE_EMIF_REGION_START hex "Reserved EMIF region start address" depends on TI_SECURE_DEVICE default 0x0 help Reserved EMIF region start address. Set to "0" to auto-select to be at the end of the external memory region. config TI_SECURE_EMIF_TOTAL_REGION_SIZE hex "Reserved EMIF region size" depends on TI_SECURE_DEVICE default 0x0 help Total reserved EMIF region size. Default is 0, which means no reserved EMIF region on secure devices. config TI_SECURE_EMIF_PROTECTED_REGION_SIZE hex "Size of protected region within reserved EMIF region" depends on TI_SECURE_DEVICE default 0x0 help This config option is used to specify the size of the portion of the total reserved EMIF region set aside for secure OS needs that will be protected using hardware memory firewalls. This value must be smaller than the TI_SECURE_EMIF_TOTAL_REGION_SIZE value. config SYS_AUTOMATIC_SDRAM_DETECTION bool choice depends on OMAP54XX prompt "Static or dynamic DDR timing calculations" default SYS_EMIF_PRECALCULATED_TIMING_REGS help For the DDR timing information we can either dynamically determine the timings to use or use pre-determined timings (based on using the dynamic method). Default to the static timing information. config SYS_EMIF_PRECALCULATED_TIMING_REGS bool "Use precalcualted timing values" config SYS_DEFAULT_LPDDR2_TIMINGS bool "Use default LPDDR2 timing values" select SYS_AUTOMATIC_SDRAM_DETECTION endchoice config SPL_AM33XX_MMCSD_MULTIPLE bool "Support multiple locations of next boot phase" depends on AM33XX depends on SPL_SYS_MMCSD_RAW_MODE depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR help The boot ROM on the am33xx looks for the first stage bootloader at several hard-coded offsets in the mmc device (0, 128K, 256K, 384K) and uses the first location which has a valid header. This can be used to implement failsafe update of that first stage (SPL). But in order for the update of the whole bootloader to be failsafe, SPL must load U-Boot proper from a location dependent on where SPL itself was loaded from. This option allows you to specify four different offsets corresponding to the different places where SPL could have been loaded from. if SPL_AM33XX_MMCSD_MULTIPLE config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_0K hex "Address on the MMC to load U-Boot from when SPL was loaded from offset 0K" default SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_128K hex "Address on the MMC to load U-Boot from when SPL was loaded from offset 128K" default SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_256K hex "Address on the MMC to load U-Boot from when SPL was loaded from offset 256K" default SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_384K hex "Address on the MMC to load U-Boot from when SPL was loaded from offset 384K" default SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR endif source "arch/arm/mach-omap2/omap3/Kconfig" source "arch/arm/mach-omap2/omap5/Kconfig" source "arch/arm/mach-omap2/am33xx/Kconfig" source "board/BuR/brxre1/Kconfig" source "board/BuR/brsmarc1/Kconfig" source "board/BuR/brppt1/Kconfig" source "board/siemens/draco/Kconfig" source "board/siemens/pxm2/Kconfig" source "board/siemens/rut/Kconfig" source "board/ti/am43xx/Kconfig" source "board/ti/am335x/Kconfig" source "board/compulab/cm_t43/Kconfig" source "board/phytec/phycore_am335x_r2/Kconfig" endif