// SPDX-License-Identifier: GPL-2.0 /* * MediaTek clock driver for MT8188 SoC * * Copyright (C) 2025 BayLibre, SAS * Copyright (c) 2025 MediaTek Inc. * Authors: Julien Masson * Garmin Chang */ #include #include #include #include #include #include "clk-mtk.h" #define MT8188_PLL_FMAX (3800UL * MHZ) #define MT8188_PLL_FMIN (1500UL * MHZ) enum { CLK_PAD_CLK32K, CLK_PAD_CLK26M, CLK_PAD_CLK13M, }; static const ulong ext_clock_rates[] = { [CLK_PAD_CLK32K] = 32000, [CLK_PAD_CLK26M] = 26 * MHZ, [CLK_PAD_CLK13M] = 13 * MHZ, }; /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ .id = _id, \ .reg = _reg, \ .pwr_reg = _pwr_reg, \ .en_mask = _en_mask, \ .rst_bar_mask = BIT(23), \ .fmin = MT8188_PLL_FMIN, \ .fmax = MT8188_PLL_FMAX, \ .flags = _flags, \ .pcwbits = _pcwbits, \ .pcwibits = 8, \ .pd_reg = _pd_reg, \ .pd_shift = _pd_shift, \ .pcw_reg = _pcw_reg, \ .pcw_shift = _pcw_shift, \ } static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ETHPLL, 0x044C, 0x0458, 0, 0, 22, 0x0450, 24, 0x0450, 0), PLL(CLK_APMIXED_MSDCPLL, 0x0514, 0x0520, 0, 0, 22, 0x0518, 24, 0x0518, 0), PLL(CLK_APMIXED_TVDPLL1, 0x0524, 0x0530, 0, 0, 22, 0x0528, 24, 0x0528, 0), PLL(CLK_APMIXED_TVDPLL2, 0x0534, 0x0540, 0, 0, 22, 0x0538, 24, 0x0538, 0), PLL(CLK_APMIXED_MMPLL, 0x0544, 0x0550, 0xff000000, CLK_PLL_HAVE_RST_BAR, 22, 0x0548, 24, 0x0548, 0), PLL(CLK_APMIXED_MAINPLL, 0x045C, 0x0468, 0xff000000, CLK_PLL_HAVE_RST_BAR, 22, 0x0460, 24, 0x0460, 0), PLL(CLK_APMIXED_IMGPLL, 0x0554, 0x0560, 0, 0, 22, 0x0558, 24, 0x0558, 0), PLL(CLK_APMIXED_UNIVPLL, 0x0504, 0x0510, 0xff000000, CLK_PLL_HAVE_RST_BAR, 22, 0x0508, 24, 0x0508, 0), PLL(CLK_APMIXED_ADSPPLL, 0x042C, 0x0438, 0, 0, 22, 0x0430, 24, 0x0430, 0), PLL(CLK_APMIXED_APLL1, 0x0304, 0x0314, 0, 0, 32, 0x0308, 24, 0x030C, 0), PLL(CLK_APMIXED_APLL2, 0x0318, 0x0328, 0, 0, 32, 0x031C, 24, 0x0320, 0), PLL(CLK_APMIXED_APLL3, 0x032C, 0x033C, 0, 0, 32, 0x0330, 24, 0x0334, 0), PLL(CLK_APMIXED_APLL4, 0x0404, 0x0414, 0, 0, 32, 0x0408, 24, 0x040C, 0), PLL(CLK_APMIXED_APLL5, 0x0418, 0x0428, 0, 0, 32, 0x041C, 24, 0x0420, 0), PLL(CLK_APMIXED_MFGPLL, 0x0340, 0x034C, 0, 0, 22, 0x0344, 24, 0x0344, 0), }; static const struct mtk_clk_tree mt8188_apmixedsys_clk_tree = { .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, .num_plls = ARRAY_SIZE(apmixed_plls), }; #define FIXED_CLK0(_id, _rate) \ FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_ULPOSC1, 260000000), FIXED_CLK0(CLK_TOP_MPHONE_SLAVE_BCK, 49152000), FIXED_CLK0(CLK_TOP_PAD_FPC, 50000000), FIXED_CLK0(CLK_TOP_466M_FMEM, 533000000), FIXED_CLK0(CLK_TOP_PEXTP_PIPE, 250000000), FIXED_CLK0(CLK_TOP_DSI_PHY, 500000000), }; #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) #define FACTOR1(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3), FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4), FACTOR1(CLK_TOP_MAINPLL_D4_D2, CLK_TOP_MAINPLL_D4, 1, 2), FACTOR1(CLK_TOP_MAINPLL_D4_D4, CLK_TOP_MAINPLL_D4, 1, 4), FACTOR1(CLK_TOP_MAINPLL_D4_D8, CLK_TOP_MAINPLL_D4, 1, 8), FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), FACTOR1(CLK_TOP_MAINPLL_D5_D2, CLK_TOP_MAINPLL_D5, 1, 2), FACTOR1(CLK_TOP_MAINPLL_D5_D4, CLK_TOP_MAINPLL_D5, 1, 4), FACTOR1(CLK_TOP_MAINPLL_D5_D8, CLK_TOP_MAINPLL_D5, 1, 8), FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6), FACTOR1(CLK_TOP_MAINPLL_D6_D2, CLK_TOP_MAINPLL_D6, 1, 2), FACTOR1(CLK_TOP_MAINPLL_D6_D4, CLK_TOP_MAINPLL_D6, 1, 4), FACTOR1(CLK_TOP_MAINPLL_D6_D8, CLK_TOP_MAINPLL_D6, 1, 8), FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), FACTOR1(CLK_TOP_MAINPLL_D7_D2, CLK_TOP_MAINPLL_D7, 1, 2), FACTOR1(CLK_TOP_MAINPLL_D7_D4, CLK_TOP_MAINPLL_D7, 1, 4), FACTOR1(CLK_TOP_MAINPLL_D7_D8, CLK_TOP_MAINPLL_D7, 1, 8), FACTOR0(CLK_TOP_MAINPLL_D9, CLK_APMIXED_MAINPLL, 1, 9), FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2), FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3), FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4), FACTOR1(CLK_TOP_UNIVPLL_D4_D2, CLK_TOP_UNIVPLL_D4, 1, 2), FACTOR1(CLK_TOP_UNIVPLL_D4_D4, CLK_TOP_UNIVPLL_D4, 1, 4), FACTOR1(CLK_TOP_UNIVPLL_D4_D8, CLK_TOP_UNIVPLL_D4, 1, 8), FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5), FACTOR1(CLK_TOP_UNIVPLL_D5_D2, CLK_TOP_UNIVPLL_D5, 1, 2), FACTOR1(CLK_TOP_UNIVPLL_D5_D4, CLK_TOP_UNIVPLL_D5, 1, 4), FACTOR1(CLK_TOP_UNIVPLL_D5_D8, CLK_TOP_UNIVPLL_D5, 1, 8), FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6), FACTOR1(CLK_TOP_UNIVPLL_D6_D2, CLK_TOP_UNIVPLL_D6, 1, 2), FACTOR1(CLK_TOP_UNIVPLL_D6_D4, CLK_TOP_UNIVPLL_D6, 1, 4), FACTOR1(CLK_TOP_UNIVPLL_D6_D8, CLK_TOP_UNIVPLL_D6, 1, 8), FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7), FACTOR0(CLK_TOP_UNIVPLL_192M, CLK_APMIXED_UNIVPLL, 1, 13), FACTOR1(CLK_TOP_UNIVPLL_192M_D4, CLK_TOP_UNIVPLL_192M, 1, 4), FACTOR1(CLK_TOP_UNIVPLL_192M_D8, CLK_TOP_UNIVPLL_192M, 1, 8), FACTOR1(CLK_TOP_UNIVPLL_192M_D10, CLK_TOP_UNIVPLL_192M, 1, 10), FACTOR1(CLK_TOP_UNIVPLL_192M_D16, CLK_TOP_UNIVPLL_192M, 1, 16), FACTOR1(CLK_TOP_UNIVPLL_192M_D32, CLK_TOP_UNIVPLL_192M, 1, 32), FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3), FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4), FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3), FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), FACTOR0(CLK_TOP_APLL3_D4, CLK_APMIXED_APLL3, 1, 4), FACTOR0(CLK_TOP_APLL4_D4, CLK_APMIXED_APLL4, 1, 4), FACTOR0(CLK_TOP_APLL5_D4, CLK_APMIXED_APLL5, 1, 4), FACTOR0(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4), FACTOR1(CLK_TOP_MMPLL_D4_D2, CLK_TOP_MMPLL_D4, 1, 2), FACTOR0(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5), FACTOR1(CLK_TOP_MMPLL_D5_D2, CLK_TOP_MMPLL_D5, 1, 2), FACTOR1(CLK_TOP_MMPLL_D5_D4, CLK_TOP_MMPLL_D5, 1, 4), FACTOR0(CLK_TOP_MMPLL_D6, CLK_APMIXED_MMPLL, 1, 6), FACTOR1(CLK_TOP_MMPLL_D6_D2, CLK_TOP_MMPLL_D6, 1, 2), FACTOR0(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7), FACTOR0(CLK_TOP_MMPLL_D9, CLK_APMIXED_MMPLL, 1, 9), FACTOR0(CLK_TOP_TVDPLL1_D2, CLK_APMIXED_TVDPLL1, 1, 2), FACTOR0(CLK_TOP_TVDPLL1_D4, CLK_APMIXED_TVDPLL1, 1, 4), FACTOR0(CLK_TOP_TVDPLL1_D8, CLK_APMIXED_TVDPLL1, 1, 8), FACTOR0(CLK_TOP_TVDPLL1_D16, CLK_APMIXED_TVDPLL1, 1, 16), FACTOR0(CLK_TOP_TVDPLL2_D2, CLK_APMIXED_TVDPLL2, 1, 2), FACTOR0(CLK_TOP_TVDPLL2_D4, CLK_APMIXED_TVDPLL2, 1, 4), FACTOR0(CLK_TOP_TVDPLL2_D8, CLK_APMIXED_TVDPLL2, 1, 8), FACTOR0(CLK_TOP_TVDPLL2_D16, CLK_APMIXED_TVDPLL2, 1, 16), FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), FACTOR0(CLK_TOP_MSDCPLL_D16, CLK_APMIXED_MSDCPLL, 1, 16), FACTOR0(CLK_TOP_ETHPLL_D2, CLK_APMIXED_ETHPLL, 1, 2), FACTOR0(CLK_TOP_ETHPLL_D4, CLK_APMIXED_ETHPLL, 1, 4), FACTOR0(CLK_TOP_ETHPLL_D8, CLK_APMIXED_ETHPLL, 1, 8), FACTOR0(CLK_TOP_ETHPLL_D10, CLK_APMIXED_ETHPLL, 1, 10), FACTOR0(CLK_TOP_ADSPPLL_D2, CLK_APMIXED_ADSPPLL, 1, 2), FACTOR0(CLK_TOP_ADSPPLL_D4, CLK_APMIXED_ADSPPLL, 1, 4), FACTOR0(CLK_TOP_ADSPPLL_D8, CLK_APMIXED_ADSPPLL, 1, 8), FACTOR1(CLK_TOP_ULPOSC1_D2, CLK_TOP_ULPOSC1, 1, 2), FACTOR1(CLK_TOP_ULPOSC1_D4, CLK_TOP_ULPOSC1, 1, 4), FACTOR1(CLK_TOP_ULPOSC1_D8, CLK_TOP_ULPOSC1, 1, 8), FACTOR1(CLK_TOP_ULPOSC1_D7, CLK_TOP_ULPOSC1, 1, 7), FACTOR1(CLK_TOP_ULPOSC1_D10, CLK_TOP_ULPOSC1, 1, 10), FACTOR1(CLK_TOP_ULPOSC1_D16, CLK_TOP_ULPOSC1, 1, 16), }; static const struct mtk_parent axi_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_ULPOSC1_D4), }; static const struct mtk_parent spm_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ULPOSC1_D10), TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), EXT_PARENT(CLK_PAD_CLK32K), }; static const struct mtk_parent scp_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D3), TOP_PARENT(CLK_TOP_MAINPLL_D3), }; static const struct mtk_parent bus_aximem_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6), }; static const struct mtk_parent vpp_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MMPLL_D4_D2), TOP_PARENT(CLK_TOP_MMPLL_D7), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D5), TOP_PARENT(CLK_TOP_TVDPLL1), TOP_PARENT(CLK_TOP_TVDPLL2), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D4), }; static const struct mtk_parent ethdr_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MMPLL_D4_D2), TOP_PARENT(CLK_TOP_MMPLL_D7), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D5_D4), TOP_PARENT(CLK_TOP_TVDPLL1), TOP_PARENT(CLK_TOP_TVDPLL2), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D4), }; static const struct mtk_parent ipe_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), APMIXED_PARENT(CLK_APMIXED_IMGPLL), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_MMPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), TOP_PARENT(CLK_TOP_MAINPLL_D7), }; static const struct mtk_parent cam_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_TVDPLL1), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MMPLL_D7), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), APMIXED_PARENT(CLK_APMIXED_IMGPLL), }; static const struct mtk_parent ccu_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_MMPLL_D6), TOP_PARENT(CLK_TOP_MMPLL_D7), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; static const struct mtk_parent ccu_ahb_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_MMPLL_D6), TOP_PARENT(CLK_TOP_MMPLL_D7), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; static const struct mtk_parent img_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), APMIXED_PARENT(CLK_APMIXED_IMGPLL), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5), TOP_PARENT(CLK_TOP_MMPLL_D6), TOP_PARENT(CLK_TOP_MMPLL_D7), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_MMPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent camtm_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), }; static const struct mtk_parent dsp_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; static const struct mtk_parent dsp1_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5), TOP_PARENT(CLK_TOP_MMPLL_D5), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; static const struct mtk_parent dsp2_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5), TOP_PARENT(CLK_TOP_MMPLL_D5), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; static const struct mtk_parent dsp3_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5), TOP_PARENT(CLK_TOP_MMPLL_D5), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; static const struct mtk_parent dsp4_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; static const struct mtk_parent dsp5_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; static const struct mtk_parent dsp6_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; static const struct mtk_parent dsp7_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_MAINPLL_D3), TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; static const struct mtk_parent mfg_core_tmp_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; static const struct mtk_parent camtg_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), }; static const struct mtk_parent camtg2_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), }; static const struct mtk_parent camtg3_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), }; static const struct mtk_parent uart_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; static const struct mtk_parent spi_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D5_D4), TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), }; static const struct mtk_parent msdc5hclk_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), }; static const struct mtk_parent msdc50_0_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), APMIXED_PARENT(CLK_APMIXED_MSDCPLL), TOP_PARENT(CLK_TOP_MSDCPLL_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), }; static const struct mtk_parent msdc30_1_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; static const struct mtk_parent msdc30_2_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; static const struct mtk_parent intdir_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D4), }; static const struct mtk_parent aud_intbus_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), }; static const struct mtk_parent audio_h_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D7), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), }; static const struct mtk_parent pwrap_ulposc_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ULPOSC1_D10), TOP_PARENT(CLK_TOP_ULPOSC1_D7), TOP_PARENT(CLK_TOP_ULPOSC1_D8), TOP_PARENT(CLK_TOP_ULPOSC1_D16), TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D8), TOP_PARENT(CLK_TOP_TVDPLL1_D16), }; static const struct mtk_parent atb_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; static const struct mtk_parent sspm_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MAINPLL_D9), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), }; /* * Both DP/eDP can be parented to TVDPLL1 and TVDPLL2, but we force using * TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate * in dual output case, which would lead to corruption of functionality loss. */ static const struct mtk_parent dp_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_TVDPLL2_D2), TOP_PARENT(CLK_TOP_TVDPLL2_D4), TOP_PARENT(CLK_TOP_TVDPLL2_D8), TOP_PARENT(CLK_TOP_TVDPLL2_D16), }; static const struct mtk_parent edp_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_TVDPLL1_D2), TOP_PARENT(CLK_TOP_TVDPLL1_D4), TOP_PARENT(CLK_TOP_TVDPLL1_D8), TOP_PARENT(CLK_TOP_TVDPLL1_D16), }; static const struct mtk_parent dpi_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_TVDPLL1_D2), TOP_PARENT(CLK_TOP_TVDPLL2_D2), TOP_PARENT(CLK_TOP_TVDPLL1_D4), TOP_PARENT(CLK_TOP_TVDPLL2_D4), TOP_PARENT(CLK_TOP_TVDPLL1_D8), TOP_PARENT(CLK_TOP_TVDPLL2_D8), TOP_PARENT(CLK_TOP_TVDPLL1_D16), TOP_PARENT(CLK_TOP_TVDPLL2_D16), }; static const struct mtk_parent disp_pwm0_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_ULPOSC1_D2), TOP_PARENT(CLK_TOP_ULPOSC1_D4), TOP_PARENT(CLK_TOP_ULPOSC1_D16), TOP_PARENT(CLK_TOP_ETHPLL_D4), }; static const struct mtk_parent disp_pwm1_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_ULPOSC1_D2), TOP_PARENT(CLK_TOP_ULPOSC1_D4), TOP_PARENT(CLK_TOP_ULPOSC1_D16), }; static const struct mtk_parent usb_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent ssusb_xhci_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent usb_2p_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent ssusb_xhci_2p_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent usb_3p_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent ssusb_xhci_3p_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent i2c_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), }; static const struct mtk_parent seninf_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D7), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MMPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; static const struct mtk_parent seninf1_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D7), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MMPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; static const struct mtk_parent gcpu_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MMPLL_D5_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; static const struct mtk_parent venc_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MMPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MMPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_MMPLL_D9), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D5), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5), }; static const struct mtk_parent vdec_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MMPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D5), TOP_PARENT(CLK_TOP_UNIVPLL_D5), TOP_PARENT(CLK_TOP_MMPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_TVDPLL2), TOP_PARENT(CLK_TOP_UNIVPLL_D4), APMIXED_PARENT(CLK_APMIXED_IMGPLL), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MMPLL_D9), }; static const struct mtk_parent pwm_parents[] = { EXT_PARENT(CLK_PAD_CLK32K), EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), }; static const struct mtk_parent mcupm_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), }; static const struct mtk_parent spmi_p_mst_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_ULPOSC1_D8), TOP_PARENT(CLK_TOP_ULPOSC1_D10), TOP_PARENT(CLK_TOP_ULPOSC1_D16), TOP_PARENT(CLK_TOP_ULPOSC1_D7), EXT_PARENT(CLK_PAD_CLK32K), TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), }; static const struct mtk_parent spmi_m_mst_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_ULPOSC1_D8), TOP_PARENT(CLK_TOP_ULPOSC1_D10), TOP_PARENT(CLK_TOP_ULPOSC1_D16), TOP_PARENT(CLK_TOP_ULPOSC1_D7), EXT_PARENT(CLK_PAD_CLK32K), TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), }; static const struct mtk_parent dvfsrc_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ULPOSC1_D10), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), TOP_PARENT(CLK_TOP_MSDCPLL_D16), }; static const struct mtk_parent tl_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), }; static const struct mtk_parent aes_msdcfde_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D6), }; static const struct mtk_parent dsi_occ_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), }; static const struct mtk_parent wpe_vpp_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), TOP_PARENT(CLK_TOP_MMPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_MMPLL_D7), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D5), TOP_PARENT(CLK_TOP_UNIVPLL_D5), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_TVDPLL1), TOP_PARENT(CLK_TOP_UNIVPLL_D4), }; static const struct mtk_parent hdcp_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), }; static const struct mtk_parent hdcp_24m_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; static const struct mtk_parent hdmi_apb_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; static const struct mtk_parent snps_eth_250m_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ETHPLL_D2), }; static const struct mtk_parent snps_eth_62p4m_ptp_parents[] = { TOP_PARENT(CLK_TOP_APLL2_D3), TOP_PARENT(CLK_TOP_APLL1_D3), EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ETHPLL_D8), }; static const struct mtk_parent snps_eth_50m_rmii_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_ETHPLL_D10), }; static const struct mtk_parent adsp_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D4), TOP_PARENT(CLK_TOP_ULPOSC1_D2), TOP_PARENT(CLK_TOP_ULPOSC1), APMIXED_PARENT(CLK_APMIXED_ADSPPLL), TOP_PARENT(CLK_TOP_ADSPPLL_D2), TOP_PARENT(CLK_TOP_ADSPPLL_D4), TOP_PARENT(CLK_TOP_ADSPPLL_D8), }; static const struct mtk_parent audio_local_bus_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D7), TOP_PARENT(CLK_TOP_MAINPLL_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6), TOP_PARENT(CLK_TOP_ULPOSC1), TOP_PARENT(CLK_TOP_ULPOSC1_D4), TOP_PARENT(CLK_TOP_ULPOSC1_D2), }; static const struct mtk_parent asm_h_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; static const struct mtk_parent asm_l_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; static const struct mtk_parent apll1_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1_D4), }; static const struct mtk_parent apll2_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL2_D4), }; static const struct mtk_parent apll3_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL3_D4), }; static const struct mtk_parent apll4_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL4_D4), }; static const struct mtk_parent apll5_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL5_D4), }; static const struct mtk_parent i2so1_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), TOP_PARENT(CLK_TOP_APLL3), TOP_PARENT(CLK_TOP_APLL4), TOP_PARENT(CLK_TOP_APLL5), }; static const struct mtk_parent i2so2_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), TOP_PARENT(CLK_TOP_APLL3), TOP_PARENT(CLK_TOP_APLL4), TOP_PARENT(CLK_TOP_APLL5), }; static const struct mtk_parent i2si1_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), TOP_PARENT(CLK_TOP_APLL3), TOP_PARENT(CLK_TOP_APLL4), TOP_PARENT(CLK_TOP_APLL5), }; static const struct mtk_parent i2si2_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), TOP_PARENT(CLK_TOP_APLL3), TOP_PARENT(CLK_TOP_APLL4), TOP_PARENT(CLK_TOP_APLL5), }; static const struct mtk_parent dptx_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), TOP_PARENT(CLK_TOP_APLL3), TOP_PARENT(CLK_TOP_APLL4), TOP_PARENT(CLK_TOP_APLL5), }; static const struct mtk_parent aud_iec_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1), TOP_PARENT(CLK_TOP_APLL2), TOP_PARENT(CLK_TOP_APLL3), TOP_PARENT(CLK_TOP_APLL4), TOP_PARENT(CLK_TOP_APLL5), }; static const struct mtk_parent a1sys_hp_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL1_D4), }; static const struct mtk_parent a2sys_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL2_D4), }; static const struct mtk_parent a3sys_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL3_D4), TOP_PARENT(CLK_TOP_APLL4_D4), TOP_PARENT(CLK_TOP_APLL5_D4), }; static const struct mtk_parent a4sys_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_APLL3_D4), TOP_PARENT(CLK_TOP_APLL4_D4), TOP_PARENT(CLK_TOP_APLL5_D4), }; static const struct mtk_parent ecc_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_MAINPLL_D6), TOP_PARENT(CLK_TOP_UNIVPLL_D6), }; static const struct mtk_parent spinor_parents[] = { EXT_PARENT(CLK_PAD_CLK26M), EXT_PARENT(CLK_PAD_CLK13M), TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; static const struct mtk_parent ulposc_parents[] = { TOP_PARENT(CLK_TOP_ULPOSC1), TOP_PARENT(CLK_TOP_ETHPLL_D2), TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), TOP_PARENT(CLK_TOP_ETHPLL_D10), }; static const struct mtk_parent srck_parents[] = { TOP_PARENT(CLK_TOP_ULPOSC1_D10), EXT_PARENT(CLK_PAD_CLK26M), }; static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ MUX_GATE(CLK_TOP_AXI, axi_parents, 0x020, 0, 4, 7), MUX_GATE(CLK_TOP_SPM, spm_parents, 0x020, 8, 4, 15), MUX_GATE(CLK_TOP_SCP, scp_parents, 0x020, 16, 4, 23), MUX_GATE(CLK_TOP_BUS_AXIMEM, bus_aximem_parents, 0x020, 24, 4, 31), /* CLK_CFG_1 */ MUX_GATE(CLK_TOP_VPP, vpp_parents, 0x02C, 0, 4, 7), MUX_GATE(CLK_TOP_ETHDR, ethdr_parents, 0x02C, 8, 4, 15), MUX_GATE(CLK_TOP_IPE, ipe_parents, 0x02C, 16, 4, 23), MUX_GATE(CLK_TOP_CAM, cam_parents, 0x02C, 24, 4, 31), /* CLK_CFG_2 */ MUX_GATE(CLK_TOP_CCU, ccu_parents, 0x038, 0, 4, 7), MUX_GATE(CLK_TOP_CCU_AHB, ccu_ahb_parents, 0x038, 8, 4, 15), MUX_GATE(CLK_TOP_IMG, img_parents, 0x038, 16, 4, 23), MUX_GATE(CLK_TOP_CAMTM, camtm_parents, 0x038, 24, 4, 31), /* CLK_CFG_3 */ MUX_GATE(CLK_TOP_DSP, dsp_parents, 0x044, 0, 4, 7), MUX_GATE(CLK_TOP_DSP1, dsp1_parents, 0x044, 8, 4, 15), MUX_GATE(CLK_TOP_DSP2, dsp2_parents, 0x044, 16, 4, 23), MUX_GATE(CLK_TOP_DSP3, dsp3_parents, 0x044, 24, 4, 31), /* CLK_CFG_4 */ MUX_GATE(CLK_TOP_DSP4, dsp4_parents, 0x050, 0, 4, 7), MUX_GATE(CLK_TOP_DSP5, dsp5_parents, 0x050, 8, 4, 15), MUX_GATE(CLK_TOP_DSP6, dsp6_parents, 0x050, 16, 4, 23), MUX_GATE(CLK_TOP_DSP7, dsp7_parents, 0x050, 24, 4, 31), /* CLK_CFG_5 */ MUX_GATE(CLK_TOP_MFG_CORE_TMP, mfg_core_tmp_parents, 0x05C, 0, 4, 7), MUX_GATE(CLK_TOP_CAMTG, camtg_parents, 0x05C, 8, 4, 15), MUX_GATE(CLK_TOP_CAMTG2, camtg2_parents, 0x05C, 16, 4, 23), MUX_GATE(CLK_TOP_CAMTG3, camtg3_parents, 0x05C, 24, 4, 31), /* CLK_CFG_6 */ MUX_GATE(CLK_TOP_UART, uart_parents, 0x068, 0, 4, 7), MUX_GATE(CLK_TOP_SPI, spi_parents, 0x068, 8, 4, 15), MUX_GATE(CLK_TOP_MSDC50_0_HCLK, msdc5hclk_parents, 0x068, 16, 4, 23), MUX_GATE(CLK_TOP_MSDC50_0, msdc50_0_parents, 0x068, 24, 4, 31), /* CLK_CFG_7 */ MUX_GATE(CLK_TOP_MSDC30_1, msdc30_1_parents, 0x074, 0, 4, 7), MUX_GATE(CLK_TOP_MSDC30_2, msdc30_2_parents, 0x074, 8, 4, 15), MUX_GATE(CLK_TOP_INTDIR, intdir_parents, 0x074, 16, 4, 23), MUX_GATE(CLK_TOP_AUD_INTBUS, aud_intbus_parents, 0x074, 24, 4, 31), /* CLK_CFG_8 */ MUX_GATE(CLK_TOP_AUDIO_H, audio_h_parents, 0x080, 0, 4, 7), MUX_GATE(CLK_TOP_PWRAP_ULPOSC, pwrap_ulposc_parents, 0x080, 8, 4, 15), MUX_GATE(CLK_TOP_ATB, atb_parents, 0x080, 16, 4, 23), MUX_GATE(CLK_TOP_SSPM, sspm_parents, 0x080, 24, 4, 31), /* CLK_CFG_9 */ MUX_GATE(CLK_TOP_DP, dp_parents, 0x08C, 0, 4, 7), MUX_GATE(CLK_TOP_EDP, edp_parents, 0x08C, 8, 4, 15), MUX_GATE(CLK_TOP_DPI, dpi_parents, 0x08C, 16, 4, 23), MUX_GATE(CLK_TOP_DISP_PWM0, disp_pwm0_parents, 0x08C, 24, 4, 31), /* CLK_CFG_10 */ MUX_GATE(CLK_TOP_DISP_PWM1, disp_pwm1_parents, 0x098, 0, 4, 7), MUX_GATE(CLK_TOP_USB_TOP, usb_parents, 0x098, 8, 4, 15), MUX_GATE(CLK_TOP_SSUSB_XHCI, ssusb_xhci_parents, 0x098, 16, 4, 23), MUX_GATE(CLK_TOP_USB_TOP_2P, usb_2p_parents, 0x098, 24, 4, 31), /* CLK_CFG_11 */ MUX_GATE(CLK_TOP_SSUSB_XHCI_2P, ssusb_xhci_2p_parents, 0x0A4, 0, 4, 7), MUX_GATE(CLK_TOP_USB_TOP_3P, usb_3p_parents, 0x0A4, 8, 4, 15), MUX_GATE(CLK_TOP_SSUSB_XHCI_3P, ssusb_xhci_3p_parents, 0x0A4, 16, 4, 23), MUX_GATE(CLK_TOP_I2C, i2c_parents, 0x0A4, 24, 4, 31), /* CLK_CFG_12 */ MUX_GATE(CLK_TOP_SENINF, seninf_parents, 0x0B0, 0, 4, 7), MUX_GATE(CLK_TOP_SENINF1, seninf1_parents, 0x0B0, 8, 4, 15), MUX_GATE(CLK_TOP_GCPU, gcpu_parents, 0x0B0, 16, 4, 23), MUX_GATE(CLK_TOP_VENC, venc_parents, 0x0B0, 24, 4, 31), /* CLK_CFG_13 */ MUX_GATE(CLK_TOP_VDEC, vdec_parents, 0x0BC, 0, 4, 7), MUX_GATE(CLK_TOP_PWM, pwm_parents, 0x0BC, 8, 4, 15), MUX_GATE(CLK_TOP_MCUPM, mcupm_parents, 0x0BC, 16, 4, 23), MUX_GATE(CLK_TOP_SPMI_P_MST, spmi_p_mst_parents, 0x0BC, 24, 4, 31), /* CLK_CFG_14 */ MUX_GATE(CLK_TOP_SPMI_M_MST, spmi_m_mst_parents, 0x0C8, 0, 4, 7), MUX_GATE(CLK_TOP_DVFSRC, dvfsrc_parents, 0x0C8, 8, 4, 15), MUX_GATE(CLK_TOP_TL, tl_parents, 0x0C8, 16, 4, 23), MUX_GATE(CLK_TOP_AES_MSDCFDE, aes_msdcfde_parents, 0x0C8, 24, 4, 31), /* CLK_CFG_15 */ MUX_GATE(CLK_TOP_DSI_OCC, dsi_occ_parents, 0x0D4, 0, 4, 7), MUX_GATE(CLK_TOP_WPE_VPP, wpe_vpp_parents, 0x0D4, 8, 4, 15), MUX_GATE(CLK_TOP_HDCP, hdcp_parents, 0x0D4, 16, 4, 23), MUX_GATE(CLK_TOP_HDCP_24M, hdcp_24m_parents, 0x0D4, 24, 4, 31), /* CLK_CFG_16 */ MUX_GATE(CLK_TOP_HDMI_APB, hdmi_apb_parents, 0x0E0, 0, 4, 7), MUX_GATE(CLK_TOP_SNPS_ETH_250M, snps_eth_250m_parents, 0x0E0, 8, 4, 15), MUX_GATE(CLK_TOP_SNPS_ETH_62P4M_PTP, snps_eth_62p4m_ptp_parents, 0x0E0, 16, 4, 23), MUX_GATE(CLK_TOP_SNPS_ETH_50M_RMII, snps_eth_50m_rmii_parents, 0x0E0, 24, 4, 31), /* CLK_CFG_17 */ MUX_GATE(CLK_TOP_ADSP, adsp_parents, 0x0EC, 0, 4, 7), MUX_GATE(CLK_TOP_AUDIO_LOCAL_BUS, audio_local_bus_parents, 0x0EC, 8, 4, 15), MUX_GATE(CLK_TOP_ASM_H, asm_h_parents, 0x0EC, 16, 4, 23), MUX_GATE(CLK_TOP_ASM_L, asm_l_parents, 0x0EC, 24, 4, 31), /* CLK_CFG_18 */ MUX_GATE(CLK_TOP_APLL1, apll1_parents, 0x0F8, 0, 4, 7), MUX_GATE(CLK_TOP_APLL2, apll2_parents, 0x0F8, 8, 4, 15), MUX_GATE(CLK_TOP_APLL3, apll3_parents, 0x0F8, 16, 4, 23), MUX_GATE(CLK_TOP_APLL4, apll4_parents, 0x0F8, 24, 4, 31), /* CLK_CFG_19 */ MUX_GATE(CLK_TOP_APLL5, apll5_parents, 0x0104, 0, 4, 7), MUX_GATE(CLK_TOP_I2SO1, i2so1_parents, 0x0104, 8, 4, 15), MUX_GATE(CLK_TOP_I2SO2, i2so2_parents, 0x0104, 16, 4, 23), MUX_GATE(CLK_TOP_I2SI1, i2si1_parents, 0x0104, 24, 4, 31), /* CLK_CFG_20 */ MUX_GATE(CLK_TOP_I2SI2, i2si2_parents, 0x0110, 0, 4, 7), MUX_GATE(CLK_TOP_DPTX, dptx_parents, 0x0110, 8, 4, 15), MUX_GATE(CLK_TOP_AUD_IEC, aud_iec_parents, 0x0110, 16, 4, 23), MUX_GATE(CLK_TOP_A1SYS_HP, a1sys_hp_parents, 0x0110, 24, 4, 31), /* CLK_CFG_21 */ MUX_GATE(CLK_TOP_A2SYS, a2sys_parents, 0x011C, 0, 4, 7), MUX_GATE(CLK_TOP_A3SYS, a3sys_parents, 0x011C, 8, 4, 15), MUX_GATE(CLK_TOP_A4SYS, a4sys_parents, 0x011C, 16, 4, 23), MUX_GATE(CLK_TOP_ECC, ecc_parents, 0x011C, 24, 4, 31), /* CLK_CFG_22 */ MUX_GATE(CLK_TOP_SPINOR, spinor_parents, 0x0128, 0, 4, 7), MUX_GATE(CLK_TOP_ULPOSC, ulposc_parents, 0x0128, 8, 4, 15), MUX_GATE(CLK_TOP_SRCK, srck_parents, 0x0128, 16, 4, 23), }; static const int mt8188_id_top_offs_map[] = { [0 ... CLK_TOP_NR_CLK - 1] = -1, /* FIXED */ [CLK_TOP_ULPOSC1] = 0, [CLK_TOP_MPHONE_SLAVE_BCK] = 1, [CLK_TOP_PAD_FPC] = 2, [CLK_TOP_466M_FMEM] = 3, [CLK_TOP_PEXTP_PIPE] = 4, [CLK_TOP_DSI_PHY] = 5, /* FACTOR */ [CLK_TOP_MAINPLL_D3] = 6, [CLK_TOP_MAINPLL_D4] = 7, [CLK_TOP_MAINPLL_D4_D2] = 8, [CLK_TOP_MAINPLL_D4_D4] = 9, [CLK_TOP_MAINPLL_D4_D8] = 10, [CLK_TOP_MAINPLL_D5] = 11, [CLK_TOP_MAINPLL_D5_D2] = 12, [CLK_TOP_MAINPLL_D5_D4] = 13, [CLK_TOP_MAINPLL_D5_D8] = 14, [CLK_TOP_MAINPLL_D6] = 15, [CLK_TOP_MAINPLL_D6_D2] = 16, [CLK_TOP_MAINPLL_D6_D4] = 17, [CLK_TOP_MAINPLL_D6_D8] = 18, [CLK_TOP_MAINPLL_D7] = 19, [CLK_TOP_MAINPLL_D7_D2] = 20, [CLK_TOP_MAINPLL_D7_D4] = 21, [CLK_TOP_MAINPLL_D7_D8] = 22, [CLK_TOP_MAINPLL_D9] = 23, [CLK_TOP_UNIVPLL_D2] = 24, [CLK_TOP_UNIVPLL_D3] = 25, [CLK_TOP_UNIVPLL_D4] = 26, [CLK_TOP_UNIVPLL_D4_D2] = 27, [CLK_TOP_UNIVPLL_D4_D4] = 28, [CLK_TOP_UNIVPLL_D4_D8] = 29, [CLK_TOP_UNIVPLL_D5] = 30, [CLK_TOP_UNIVPLL_D5_D2] = 31, [CLK_TOP_UNIVPLL_D5_D4] = 32, [CLK_TOP_UNIVPLL_D5_D8] = 33, [CLK_TOP_UNIVPLL_D6] = 34, [CLK_TOP_UNIVPLL_D6_D2] = 35, [CLK_TOP_UNIVPLL_D6_D4] = 36, [CLK_TOP_UNIVPLL_D6_D8] = 37, [CLK_TOP_UNIVPLL_D7] = 38, [CLK_TOP_UNIVPLL_192M] = 39, [CLK_TOP_UNIVPLL_192M_D4] = 40, [CLK_TOP_UNIVPLL_192M_D8] = 41, [CLK_TOP_UNIVPLL_192M_D10] = 42, [CLK_TOP_UNIVPLL_192M_D16] = 43, [CLK_TOP_UNIVPLL_192M_D32] = 44, [CLK_TOP_APLL1_D3] = 45, [CLK_TOP_APLL1_D4] = 46, [CLK_TOP_APLL2_D3] = 47, [CLK_TOP_APLL2_D4] = 48, [CLK_TOP_APLL3_D4] = 49, [CLK_TOP_APLL4_D4] = 50, [CLK_TOP_APLL5_D4] = 51, [CLK_TOP_MMPLL_D4] = 52, [CLK_TOP_MMPLL_D4_D2] = 53, [CLK_TOP_MMPLL_D5] = 54, [CLK_TOP_MMPLL_D5_D2] = 55, [CLK_TOP_MMPLL_D5_D4] = 56, [CLK_TOP_MMPLL_D6] = 57, [CLK_TOP_MMPLL_D6_D2] = 58, [CLK_TOP_MMPLL_D7] = 59, [CLK_TOP_MMPLL_D9] = 60, [CLK_TOP_TVDPLL1_D2] = 61, [CLK_TOP_TVDPLL1_D4] = 62, [CLK_TOP_TVDPLL1_D8] = 63, [CLK_TOP_TVDPLL1_D16] = 64, [CLK_TOP_TVDPLL2_D2] = 65, [CLK_TOP_TVDPLL2_D4] = 66, [CLK_TOP_TVDPLL2_D8] = 67, [CLK_TOP_TVDPLL2_D16] = 68, [CLK_TOP_MSDCPLL_D2] = 69, [CLK_TOP_MSDCPLL_D16] = 70, [CLK_TOP_ETHPLL_D2] = 71, [CLK_TOP_ETHPLL_D4] = 72, [CLK_TOP_ETHPLL_D8] = 73, [CLK_TOP_ETHPLL_D10] = 74, [CLK_TOP_ADSPPLL_D2] = 75, [CLK_TOP_ADSPPLL_D4] = 76, [CLK_TOP_ADSPPLL_D8] = 77, [CLK_TOP_ULPOSC1_D2] = 78, [CLK_TOP_ULPOSC1_D4] = 79, [CLK_TOP_ULPOSC1_D8] = 80, [CLK_TOP_ULPOSC1_D7] = 81, [CLK_TOP_ULPOSC1_D10] = 82, [CLK_TOP_ULPOSC1_D16] = 83, /* MUX */ [CLK_TOP_AXI] = 84, [CLK_TOP_SPM] = 85, [CLK_TOP_SCP] = 86, [CLK_TOP_BUS_AXIMEM] = 87, [CLK_TOP_VPP] = 88, [CLK_TOP_ETHDR] = 89, [CLK_TOP_IPE] = 90, [CLK_TOP_CAM] = 91, [CLK_TOP_CCU] = 92, [CLK_TOP_CCU_AHB] = 93, [CLK_TOP_IMG] = 94, [CLK_TOP_CAMTM] = 95, [CLK_TOP_DSP] = 96, [CLK_TOP_DSP1] = 97, [CLK_TOP_DSP2] = 98, [CLK_TOP_DSP3] = 99, [CLK_TOP_DSP4] = 100, [CLK_TOP_DSP5] = 101, [CLK_TOP_DSP6] = 102, [CLK_TOP_DSP7] = 103, [CLK_TOP_MFG_CORE_TMP] = 104, [CLK_TOP_CAMTG] = 105, [CLK_TOP_CAMTG2] = 106, [CLK_TOP_CAMTG3] = 107, [CLK_TOP_UART] = 108, [CLK_TOP_SPI] = 109, [CLK_TOP_MSDC50_0_HCLK] = 110, [CLK_TOP_MSDC50_0] = 111, [CLK_TOP_MSDC30_1] = 112, [CLK_TOP_MSDC30_2] = 113, [CLK_TOP_INTDIR] = 114, [CLK_TOP_AUD_INTBUS] = 115, [CLK_TOP_AUDIO_H] = 116, [CLK_TOP_PWRAP_ULPOSC] = 117, [CLK_TOP_ATB] = 118, [CLK_TOP_SSPM] = 119, [CLK_TOP_DP] = 120, [CLK_TOP_EDP] = 121, [CLK_TOP_DPI] = 122, [CLK_TOP_DISP_PWM0] = 123, [CLK_TOP_DISP_PWM1] = 124, [CLK_TOP_USB_TOP] = 125, [CLK_TOP_SSUSB_XHCI] = 126, [CLK_TOP_USB_TOP_2P] = 127, [CLK_TOP_SSUSB_XHCI_2P] = 128, [CLK_TOP_USB_TOP_3P] = 129, [CLK_TOP_SSUSB_XHCI_3P] = 130, [CLK_TOP_I2C] = 131, [CLK_TOP_SENINF] = 132, [CLK_TOP_SENINF1] = 133, [CLK_TOP_GCPU] = 134, [CLK_TOP_VENC] = 135, [CLK_TOP_VDEC] = 136, [CLK_TOP_PWM] = 137, [CLK_TOP_MCUPM] = 138, [CLK_TOP_SPMI_P_MST] = 139, [CLK_TOP_SPMI_M_MST] = 140, [CLK_TOP_DVFSRC] = 141, [CLK_TOP_TL] = 142, [CLK_TOP_AES_MSDCFDE] = 143, [CLK_TOP_DSI_OCC] = 144, [CLK_TOP_WPE_VPP] = 145, [CLK_TOP_HDCP] = 146, [CLK_TOP_HDCP_24M] = 147, [CLK_TOP_HDMI_APB] = 148, [CLK_TOP_SNPS_ETH_250M] = 149, [CLK_TOP_SNPS_ETH_62P4M_PTP] = 150, [CLK_TOP_SNPS_ETH_50M_RMII] = 151, [CLK_TOP_ADSP] = 152, [CLK_TOP_AUDIO_LOCAL_BUS] = 153, [CLK_TOP_ASM_H] = 154, [CLK_TOP_ASM_L] = 155, [CLK_TOP_APLL1] = 156, [CLK_TOP_APLL2] = 157, [CLK_TOP_APLL3] = 158, [CLK_TOP_APLL4] = 159, [CLK_TOP_APLL5] = 160, [CLK_TOP_I2SO1] = 161, [CLK_TOP_I2SO2] = 162, [CLK_TOP_I2SI1] = 163, [CLK_TOP_I2SI2] = 164, [CLK_TOP_DPTX] = 165, [CLK_TOP_AUD_IEC] = 166, [CLK_TOP_A1SYS_HP] = 167, [CLK_TOP_A2SYS] = 168, [CLK_TOP_A3SYS] = 169, [CLK_TOP_A4SYS] = 170, [CLK_TOP_ECC] = 171, [CLK_TOP_SPINOR] = 172, [CLK_TOP_ULPOSC] = 173, [CLK_TOP_SRCK] = 174, /* GATE */ [CLK_TOP_CFGREG_CLOCK_EN_VPP0] = 175, [CLK_TOP_CFGREG_CLOCK_EN_VPP1] = 176, [CLK_TOP_CFGREG_CLOCK_EN_VDO0] = 177, [CLK_TOP_CFGREG_CLOCK_EN_VDO1] = 178, [CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS] = 179, [CLK_TOP_CFGREG_F26M_VPP0] = 180, [CLK_TOP_CFGREG_F26M_VPP1] = 181, [CLK_TOP_CFGREG_F26M_VDO0] = 182, [CLK_TOP_CFGREG_F26M_VDO1] = 183, [CLK_TOP_CFGREG_AUD_F26M_AUD] = 184, [CLK_TOP_CFGREG_UNIPLL_SES] = 185, [CLK_TOP_CFGREG_F_PCIE_PHY_REF] = 186, [CLK_TOP_SSUSB_TOP_REF] = 187, [CLK_TOP_SSUSB_PHY_REF] = 188, [CLK_TOP_SSUSB_TOP_P1_REF] = 189, [CLK_TOP_SSUSB_PHY_P1_REF] = 190, [CLK_TOP_SSUSB_TOP_P2_REF] = 191, [CLK_TOP_SSUSB_PHY_P2_REF] = 192, [CLK_TOP_SSUSB_TOP_P3_REF] = 193, [CLK_TOP_SSUSB_PHY_P3_REF] = 194, }; static const struct mtk_gate_regs top0_cg_regs = { .set_ofs = 0x238, .clr_ofs = 0x238, .sta_ofs = 0x238, }; static const struct mtk_gate_regs top1_cg_regs = { .set_ofs = 0x250, .clr_ofs = 0x250, .sta_ofs = 0x250, }; #define GATE_TOP0(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &top0_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \ } #define GATE_TOP0E(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &top0_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_EXT, \ } #define GATE_TOP1(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &top1_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT, \ } static const struct mtk_gate topckgen_cg_clks[] = { /* TOP0 */ GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP0, CLK_TOP_VPP, 0), GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP1, CLK_TOP_VPP, 1), GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO0, CLK_TOP_VPP, 2), GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO1, CLK_TOP_VPP, 3), GATE_TOP0(CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS, CLK_TOP_VPP, 4), GATE_TOP0E(CLK_TOP_CFGREG_F26M_VPP0, CLK_PAD_CLK26M, 5), GATE_TOP0E(CLK_TOP_CFGREG_F26M_VPP1, CLK_PAD_CLK26M, 6), GATE_TOP0E(CLK_TOP_CFGREG_F26M_VDO0, CLK_PAD_CLK26M, 7), GATE_TOP0E(CLK_TOP_CFGREG_F26M_VDO1, CLK_PAD_CLK26M, 8), GATE_TOP0E(CLK_TOP_CFGREG_AUD_F26M_AUD, CLK_PAD_CLK26M, 9), GATE_TOP0(CLK_TOP_CFGREG_UNIPLL_SES, CLK_TOP_UNIVPLL_D2, 15), GATE_TOP0E(CLK_TOP_CFGREG_F_PCIE_PHY_REF, CLK_PAD_CLK26M, 18), /* TOP1 */ GATE_TOP1(CLK_TOP_SSUSB_TOP_REF, CLK_PAD_CLK26M, 0), GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, CLK_PAD_CLK26M, 1), GATE_TOP1(CLK_TOP_SSUSB_TOP_P1_REF, CLK_PAD_CLK26M, 2), GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, CLK_PAD_CLK26M, 3), GATE_TOP1(CLK_TOP_SSUSB_TOP_P2_REF, CLK_PAD_CLK26M, 4), GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, CLK_PAD_CLK26M, 5), GATE_TOP1(CLK_TOP_SSUSB_TOP_P3_REF, CLK_PAD_CLK26M, 6), GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, CLK_PAD_CLK26M, 7), }; static const struct mtk_clk_tree mt8188_topckgen_clk_tree = { .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .id_offs_map = mt8188_id_top_offs_map, .id_offs_map_size = ARRAY_SIZE(mt8188_id_top_offs_map), .fdivs_offs = mt8188_id_top_offs_map[CLK_TOP_MAINPLL_D3], .muxes_offs = mt8188_id_top_offs_map[CLK_TOP_AXI], .gates_offs = mt8188_id_top_offs_map[CLK_TOP_CFGREG_CLOCK_EN_VPP0], .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, .gates = topckgen_cg_clks, .num_fclks = ARRAY_SIZE(top_fixed_clks), .num_fdivs = ARRAY_SIZE(top_fixed_divs), .num_muxes = ARRAY_SIZE(top_muxes), .num_gates = ARRAY_SIZE(topckgen_cg_clks), }; static const struct mtk_gate_regs infra_ao0_cg_regs = { .set_ofs = 0x80, .clr_ofs = 0x84, .sta_ofs = 0x90, }; static const struct mtk_gate_regs infra_ao1_cg_regs = { .set_ofs = 0x88, .clr_ofs = 0x8c, .sta_ofs = 0x94, }; static const struct mtk_gate_regs infra_ao2_cg_regs = { .set_ofs = 0xa4, .clr_ofs = 0xa8, .sta_ofs = 0xac, }; static const struct mtk_gate_regs infra_ao3_cg_regs = { .set_ofs = 0xc0, .clr_ofs = 0xc4, .sta_ofs = 0xc8, }; static const struct mtk_gate_regs infra_ao4_cg_regs = { .set_ofs = 0xe0, .clr_ofs = 0xe4, .sta_ofs = 0xe8, }; #define GATE_INFRA_AO0(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &infra_ao0_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } #define GATE_INFRA_AO0E(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &infra_ao0_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ } #define GATE_INFRA_AO1(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &infra_ao1_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } #define GATE_INFRA_AO1E(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &infra_ao1_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ } #define GATE_INFRA_AO2(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &infra_ao2_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } #define GATE_INFRA_AO2E(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &infra_ao2_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ } #define GATE_INFRA_AO3(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &infra_ao3_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } #define GATE_INFRA_AO3E(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &infra_ao3_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ } #define GATE_INFRA_AO4(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &infra_ao4_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } static const struct mtk_gate infracfg_ao_clks[] = { /* INFRA_AO0 */ GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, CLK_TOP_PWRAP_ULPOSC, 0), GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, CLK_TOP_PWRAP_ULPOSC, 1), GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, CLK_TOP_PWRAP_ULPOSC, 2), GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, CLK_TOP_PWRAP_ULPOSC, 3), /* infra_ao_sej is main clock is for secure engine with JTAG support */ GATE_INFRA_AO0(CLK_INFRA_AO_SEJ, CLK_TOP_AXI, 5), GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, CLK_TOP_AXI, 6), GATE_INFRA_AO0(CLK_INFRA_AO_GCE, CLK_TOP_AXI, 8), GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, CLK_TOP_AXI, 9), GATE_INFRA_AO0(CLK_INFRA_AO_THERM, CLK_TOP_AXI, 10), GATE_INFRA_AO0(CLK_INFRA_AO_PWM_HCLK, CLK_TOP_AXI, 15), GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, CLK_TOP_PWM, 16), GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, CLK_TOP_PWM, 17), GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, CLK_TOP_PWM, 18), GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, CLK_TOP_PWM, 19), GATE_INFRA_AO0(CLK_INFRA_AO_PWM, CLK_TOP_PWM, 21), GATE_INFRA_AO0(CLK_INFRA_AO_UART0, CLK_TOP_UART, 22), GATE_INFRA_AO0(CLK_INFRA_AO_UART1, CLK_TOP_UART, 23), GATE_INFRA_AO0(CLK_INFRA_AO_UART2, CLK_TOP_UART, 24), GATE_INFRA_AO0(CLK_INFRA_AO_UART3, CLK_TOP_UART, 25), GATE_INFRA_AO0(CLK_INFRA_AO_UART4, CLK_TOP_UART, 26), GATE_INFRA_AO0E(CLK_INFRA_AO_GCE_26M, CLK_PAD_CLK26M, 27), GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, CLK_TOP_PAD_FPC, 28), GATE_INFRA_AO0(CLK_INFRA_AO_UART5, CLK_TOP_UART, 29), /* INFRA_AO1 */ GATE_INFRA_AO1E(CLK_INFRA_AO_HDMI_26M, CLK_PAD_CLK26M, 0), GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, CLK_TOP_SPI, 1), GATE_INFRA_AO1E(CLK_INFRA_AO_MSDC0, CLK_PAD_CLK26M, 2), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, CLK_TOP_AXI, 4), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC2, CLK_TOP_AXI, 5), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, CLK_TOP_MSDC50_0, 6), /* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux. */ GATE_INFRA_AO1E(CLK_INFRA_AO_DVFSRC, CLK_PAD_CLK26M, 7), GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, CLK_TOP_AXI, 9), GATE_INFRA_AO1E(CLK_INFRA_AO_AUXADC, CLK_PAD_CLK26M, 10), GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, CLK_TOP_AXI, 11), GATE_INFRA_AO1E(CLK_INFRA_AO_HDMI_32K, CLK_PAD_CLK32K, 12), GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_HCLK, CLK_TOP_AXI, 13), GATE_INFRA_AO1E(CLK_INFRA_AO_PCIE_TL_26M, CLK_PAD_CLK26M, 15), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, CLK_TOP_MSDC30_1, 16), GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_BCLK, CLK_TOP_AXI, 17), GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, CLK_TOP_TL, 18), /* infra_ao_dapc is for device access permission control module */ GATE_INFRA_AO1(CLK_INFRA_AO_DEVICE_APC, CLK_TOP_AXI, 20), GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_HCLK, CLK_TOP_AXI, 23), GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, CLK_TOP_AXI, 24), GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, CLK_TOP_AXI, 25), GATE_INFRA_AO1E(CLK_INFRA_AO_PCIE_TL_32K, CLK_PAD_CLK32K, 26), GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, CLK_TOP_AXI, 29), GATE_INFRA_AO1E(CLK_INFRA_AO_DRAMC_F26M, CLK_PAD_CLK26M, 31), /* INFRA_AO2 */ GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, CLK_TOP_AXI, 0), GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, CLK_TOP_DISP_PWM0, 2), GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, CLK_TOP_AXI, 3), GATE_INFRA_AO2E(CLK_INFRA_AO_AUDIO_26M_BCLK, CLK_PAD_CLK26M, 4), GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, CLK_TOP_SPI, 6), GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, CLK_TOP_SPI, 9), GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, CLK_TOP_SPI, 10), GATE_INFRA_AO2(CLK_INFRA_AO_FSSPM, CLK_TOP_SSPM, 15), GATE_INFRA_AO2(CLK_INFRA_AO_SSPM_BUS_HCLK, CLK_TOP_AXI, 17), GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_BCLK, CLK_TOP_AXI, 18), GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, CLK_TOP_SPI, 25), GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, CLK_TOP_SPI, 26), GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, CLK_TOP_AXI, 27), /* INFRA_AO3 */ GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, CLK_TOP_MSDC50_0, 0), GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, CLK_TOP_MSDC50_0, 1), GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, CLK_TOP_MSDC50_0, 2), GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, CLK_TOP_AXI, 5), GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, CLK_TOP_MSDC50_0, 7), GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, CLK_TOP_MSDC50_0, 8), GATE_INFRA_AO3(CLK_INFRA_AO_MSDC30_2, CLK_TOP_MSDC30_2, 9), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, CLK_TOP_GCPU, 10), GATE_INFRA_AO3E(CLK_INFRA_AO_PCIE_PERI_26M, CLK_PAD_CLK26M, 15), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_BCLK, CLK_TOP_AXI, 16), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_BCLK, CLK_TOP_AXI, 17), GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, CLK_TOP_DISP_PWM1, 20), GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, CLK_TOP_MSDC50_0, 24), /* infra_ao_dapc_sync is for device access permission control module */ GATE_INFRA_AO3(CLK_INFRA_AO_DEVICE_APC_SYNC, CLK_TOP_AXI, 25), GATE_INFRA_AO3E(CLK_INFRA_AO_PCIE_P1_PERI_26M, CLK_PAD_CLK26M, 26), /* INFRA_AO4 */ /* infra_ao_133m_mclk_set/infra_ao_66m_mclk_set are main clocks of peripheral */ GATE_INFRA_AO4(CLK_INFRA_AO_133M_MCLK_CK, CLK_TOP_AXI, 0), GATE_INFRA_AO4(CLK_INFRA_AO_66M_MCLK_CK, CLK_TOP_AXI, 1), GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, CLK_TOP_PEXTP_PIPE, 7), GATE_INFRA_AO4(CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P, CLK_TOP_AES_MSDCFDE, 18), }; static const struct mtk_clk_tree mt8188_infracfg_ao_clk_tree = { .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static const struct mtk_gate_regs peri_ao_cg_regs = { .set_ofs = 0x10, .clr_ofs = 0x14, .sta_ofs = 0x18, }; #define GATE_PERI_AO(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &peri_ao_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } #define GATE_PERI_AOE(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &peri_ao_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ } static const struct mtk_gate pericfg_ao_clks[] = { GATE_PERI_AO(CLK_PERI_AO_ETHERNET, CLK_TOP_AXI, 0), GATE_PERI_AO(CLK_PERI_AO_ETHERNET_BUS, CLK_TOP_AXI, 1), GATE_PERI_AO(CLK_PERI_AO_FLASHIF_BUS, CLK_TOP_AXI, 3), GATE_PERI_AOE(CLK_PERI_AO_FLASHIF_26M, CLK_PAD_CLK26M, 4), GATE_PERI_AO(CLK_PERI_AO_FLASHIFLASHCK, CLK_TOP_SPINOR, 5), GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_BUS, CLK_TOP_USB_TOP_2P, 9), GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_XHCI, CLK_TOP_SSUSB_XHCI_2P, 10), GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_BUS, CLK_TOP_USB_TOP_3P, 11), GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_XHCI, CLK_TOP_SSUSB_XHCI_3P, 12), GATE_PERI_AO(CLK_PERI_AO_SSUSB_BUS, CLK_TOP_USB_TOP, 13), GATE_PERI_AO(CLK_PERI_AO_SSUSB_XHCI, CLK_TOP_SSUSB_XHCI, 14), GATE_PERI_AO(CLK_PERI_AO_ETHERNET_MAC, CLK_TOP_SNPS_ETH_250M, 16), }; static const struct mtk_clk_tree mt8188_pericfg_ao_clk_tree = { .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static const struct mtk_gate_regs imp_iic_wrap_cg_regs = { .set_ofs = 0xe08, .clr_ofs = 0xe04, .sta_ofs = 0xe00, }; #define GATE_IMP_IIC_WRAP(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ .regs = &imp_iic_wrap_cg_regs, \ .shift = _shift, \ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } static const struct mtk_gate imp_iic_wrap_c_clks[] = { GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0, CLK_TOP_I2C, 0), GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2, CLK_TOP_I2C, 1), GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3, CLK_TOP_I2C, 2), }; static const struct mtk_gate imp_iic_wrap_w_clks[] = { GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1, CLK_TOP_I2C, 0), GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4, CLK_TOP_I2C, 1), }; static const struct mtk_gate imp_iic_wrap_en_clks[] = { GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5, CLK_TOP_I2C, 0), GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6, CLK_TOP_I2C, 1), }; const struct mtk_clk_tree mt8188_imp_iic_wrap_c_clk_tree = { .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; const struct mtk_clk_tree mt8188_imp_iic_wrap_w_clk_tree = { .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; const struct mtk_clk_tree mt8188_imp_iic_wrap_en_clk_tree = { .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static int mt8188_apmixedsys_probe(struct udevice *dev) { return mtk_common_clk_init(dev, &mt8188_apmixedsys_clk_tree); } static int mt8188_topckgen_probe(struct udevice *dev) { return mtk_common_clk_init(dev, &mt8188_topckgen_clk_tree); } static int mt8188_infracfg_ao_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8188_infracfg_ao_clk_tree, infracfg_ao_clks, ARRAY_SIZE(infracfg_ao_clks), 0); } static int mt8188_pericfg_ao_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8188_pericfg_ao_clk_tree, pericfg_ao_clks, ARRAY_SIZE(pericfg_ao_clks), 0); } static int mt8188_imp_iic_wrap_c_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8188_imp_iic_wrap_c_clk_tree, imp_iic_wrap_c_clks, ARRAY_SIZE(imp_iic_wrap_c_clks), 0); } static int mt8188_imp_iic_wrap_w_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8188_imp_iic_wrap_w_clk_tree, imp_iic_wrap_w_clks, ARRAY_SIZE(imp_iic_wrap_w_clks), 0); } static int mt8188_imp_iic_wrap_en_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8188_imp_iic_wrap_en_clk_tree, imp_iic_wrap_en_clks, ARRAY_SIZE(imp_iic_wrap_en_clks), 0); } static const struct udevice_id mt8188_apmixed_compat[] = { { .compatible = "mediatek,mt8188-apmixedsys", }, { } }; static const struct udevice_id mt8188_topckgen_compat[] = { { .compatible = "mediatek,mt8188-topckgen", }, { } }; static const struct udevice_id mt8188_infracfg_ao_compat[] = { { .compatible = "mediatek,mt8188-infracfg-ao", }, { } }; static const struct udevice_id mt8188_pericfg_ao_compat[] = { { .compatible = "mediatek,mt8188-pericfg-ao", }, { } }; static const struct udevice_id mt8188_imp_iic_wrap_c_compat[] = { { .compatible = "mediatek,mt8188-imp-iic-wrap-c", }, { } }; static const struct udevice_id mt8188_imp_iic_wrap_w_compat[] = { { .compatible = "mediatek,mt8188-imp-iic-wrap-w", }, { } }; static const struct udevice_id mt8188_imp_iic_wrap_en_compat[] = { { .compatible = "mediatek,mt8188-imp-iic-wrap-en", }, { } }; U_BOOT_DRIVER(mtk_clk_apmixedsys) = { .name = "mt8188-apmixedsys", .id = UCLASS_CLK, .of_match = mt8188_apmixed_compat, .probe = mt8188_apmixedsys_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_apmixedsys_ops, .flags = DM_FLAG_PRE_RELOC, }; U_BOOT_DRIVER(mtk_clk_topckgen) = { .name = "mt8188-topckgen", .id = UCLASS_CLK, .of_match = mt8188_topckgen_compat, .probe = mt8188_topckgen_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_topckgen_ops, .flags = DM_FLAG_PRE_RELOC, }; U_BOOT_DRIVER(mtk_clk_infracfg_ao) = { .name = "mt8188-infracfg-ao", .id = UCLASS_CLK, .of_match = mt8188_infracfg_ao_compat, .probe = mt8188_infracfg_ao_probe, .priv_auto = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, .flags = DM_FLAG_PRE_RELOC, }; U_BOOT_DRIVER(mtk_clk_pericfg_ao) = { .name = "mt8188-pericfg-ao", .id = UCLASS_CLK, .of_match = mt8188_pericfg_ao_compat, .probe = mt8188_pericfg_ao_probe, .priv_auto = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, .flags = DM_FLAG_PRE_RELOC, }; U_BOOT_DRIVER(mtk_clk_imp_iic_wrap_c) = { .name = "mt8188-imp_iic_wrap_c", .id = UCLASS_CLK, .of_match = mt8188_imp_iic_wrap_c_compat, .probe = mt8188_imp_iic_wrap_c_probe, .priv_auto = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, .flags = DM_FLAG_PRE_RELOC, }; U_BOOT_DRIVER(mtk_clk_imp_iic_wrap_w) = { .name = "mt8188-imp_iic_wrap_w", .id = UCLASS_CLK, .of_match = mt8188_imp_iic_wrap_w_compat, .probe = mt8188_imp_iic_wrap_w_probe, .priv_auto = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, .flags = DM_FLAG_PRE_RELOC, }; U_BOOT_DRIVER(mtk_clk_imp_iic_wrap_en) = { .name = "mt8188-imp_iic_wrap_en", .id = UCLASS_CLK, .of_match = mt8188_imp_iic_wrap_en_compat, .probe = mt8188_imp_iic_wrap_en_probe, .priv_auto = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, .flags = DM_FLAG_PRE_RELOC, };