// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2024 AIROHA Inc * Author: Christian Marangi */ #include #include #include /* SCU*/ #define AIROHA_SCU_PDIDR 0x5c #define AIROHA_SCU_PRODUCT_ID GENMASK(15, 0) #define AIROHA_SCU_WAN_CONF 0x70 #define AIROHA_SCU_ETH_MAC_SEL BIT(24) #define AIROHA_SCU_ETH_MAC_SEL_XFI FIELD_PREP_CONST(AIROHA_SCU_ETH_MAC_SEL, 0x0) #define AIROHA_SCU_ETH_MAC_SEL_PON FIELD_PREP_CONST(AIROHA_SCU_ETH_MAC_SEL, 0x1) #define AIROHA_SCU_WAN_SEL GENMASK(7, 0) #define AIROHA_SCU_WAN_SEL_SGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10) #define AIROHA_SCU_WAN_SEL_HSGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11) #define AIROHA_SCU_WAN_SEL_USXGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12) #define AIROHA_SCU_SSR3 0x94 #define AIROHA_SCU_ETH_XSI_SEL GENMASK(14, 13) #define AIROHA_SCU_ETH_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1) #define AIROHA_SCU_ETH_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2) #define AIROHA_SCU_SSTR 0x9c #define AIROHA_SCU_PON_XSI_SEL GENMASK(10, 9) #define AIROHA_SCU_PON_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1) #define AIROHA_SCU_PON_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2) /* XFI_MAC */ #define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG 0x0 #define AIROHA_PCS_XFI_RX_FRAG_LEN GENMASK(26, 22) #define AIROHA_PCS_XFI_TX_FRAG_LEN GENMASK(21, 17) #define AIROHA_PCS_XFI_IPG_NUM GENMASK(15, 10) #define AIROHA_PCS_XFI_TX_FC_EN BIT(5) #define AIROHA_PCS_XFI_RX_FC_EN BIT(4) #define AIROHA_PCS_XFI_RXMPI_STOP BIT(3) #define AIROHA_PCS_XFI_RXMBI_STOP BIT(2) #define AIROHA_PCS_XFI_TXMPI_STOP BIT(1) #define AIROHA_PCS_XFI_TXMBI_STOP BIT(0) #define AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST 0x10 #define AIROHA_PCS_XFI_MAC_LOGIC_RST BIT(0) #define AIROHA_PCS_XFI_MAC_XFI_MACADDRH 0x60 #define AIROHA_PCS_XFI_MAC_MACADDRH GENMASK(15, 0) #define AIROHA_PCS_XFI_MAC_XFI_MACADDRL 0x64 #define AIROHA_PCS_XFI_MAC_MACADDRL GENMASK(31, 0) #define AIROHA_PCS_XFI_MAC_XFI_CNT_CLR 0x100 #define AIROHA_PCS_XFI_GLB_CNT_CLR BIT(0) /* HSGMII_AN */ #define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0 0x0 #define AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE BIT(12) #define AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART BIT(9) #define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1 0x4 /* BMSR */ #define AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6) #define AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5) #define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4) #define AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3) #define AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2) #define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4 0x10 #define AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0) #define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5 0x14 /* LPA */ #define AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0) #define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11 0x2c #define AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER GENMASK(19, 0) #define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13 0x34 #define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8) #define AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0) #define AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5) #define AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4) #define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2) #define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2) #define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1) #define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0) #define AIROHA_PCS_HSGMII_AN_SIDEBAND_EN BIT(1) #define AIROHA_PCS_HSGMII_AN_SGMII_EN BIT(0) #define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60 #define AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE BIT(0) /* HSGMII_PCS */ #define AIROHA_PCS_HSGMII_PCS_CTROL_1 0x0 #define AIROHA_PCS_TBI_10B_MODE BIT(30) #define AIROHA_PCS_SGMII_SEND_AN_ERR_EN BIT(24) #define AIROHA_PCS_REMOTE_FAULT_DIS BIT(12) #define AIROHA_PCS_HSGMII_PCS_CTROL_3 0x8 #define AIROHA_PCS_HSGMII_PCS_LINK_STSTIME GENMASK(19, 0) #define AIROHA_PCS_HSGMII_PCS_CTROL_6 0x14 #define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14) #define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13) #define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12) #define AIROHA_PCS_HSGMII_PCS_MAC_MODE BIT(8) #define AIROHA_PCS_HSGMII_PCS_TX_ENABLE BIT(4) #define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2) #define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0) #define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1) #define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2) #define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT BIT(1) #define AIROHA_PCS_HSGMII_PCS_MODE2_EN BIT(0) #define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20 #define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11) #define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10) #define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9) #define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8) #define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5) #define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT BIT(4) #define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3) #define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2) #define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1) #define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT BIT(0) #define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24 #define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4) #define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0) #define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1) #define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2) #define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0) #define ARIOHA_PCS_HSGMII_PCS_STATE_2 0x104 #define AIROHA_PCS_HSGMII_PCS_RX_SYNC BIT(5) #define AIROHA_PCS_HSGMII_PCS_AN_DONE BIT(0) #define AIROHA_PCS_HSGMII_PCS_INT_STATE 0x15c #define AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4) #define AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS BIT(3) #define AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2) #define AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC BIT(1) #define AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE BIT(0) /* MULTI_SGMII */ #define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0 0x14 #define AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0 BIT(0) #define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18 #define AIROHA_PCS_LINK_MODE_P0 GENMASK(5, 4) #define AIROHA_PCS_LINK_MODE_P0_2_5G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3) #define AIROHA_PCS_LINK_MODE_P0_1G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2) #define AIROHA_PCS_LINK_MODE_P0_100M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1) #define AIROHA_PCS_LINK_MODE_P0_10M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0) #define AIROHA_PCS_FORCE_SPD_MODE_P0 BIT(2) #define AIROHA_PCS_FORCE_LINKDOWN_P0 BIT(1) #define AIROHA_PCS_FORCE_LINKUP_P0 BIT(0) #define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0 0x100 #define AIROHA_PCS_HSGMII_XFI_SEL BIT(28) #define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL 0x14c #define AIROHA_PCS_HSGMII_PCS_INT BIT(0) #define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15 0x43c #define AIROHA_PCS_LINK_STS_P0 BIT(3) #define AIROHA_PCS_SPEED_STS_P0 GENMASK(2, 0) #define AIROHA_PCS_SPEED_STS_P0_1G FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2) #define AIROHA_PCS_SPEED_STS_P0_100M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1) #define AIROHA_PCS_SPEED_STS_P0_10M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0) #define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18 0x448 #define AIROHA_PCS_P0_SGMII_IS_10 BIT(2) #define AIROHA_PCS_P0_SGMII_IS_100 BIT(1) #define AIROHA_PCS_P0_SGMII_IS_1000 BIT(0) /* HSGMII_RATE_ADP */ #define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0 0x0 #define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27) #define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26) #define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN BIT(4) #define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN BIT(0) #define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1 0x4 #define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16) #define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24) #define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6 0x18 #define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0) #define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8 0x20 #define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0) #define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11 0x2c #define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8) #define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12) #define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0) #define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1) #define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2) #define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4) #define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6) #define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0 0x100 #define AIROHA_PCS_HSGMII_P0_DIS_MII_MODE BIT(31) /* USXGMII */ #define AIROHA_PCS_USXGMII_PCS_CTROL_1 0x0 #define AIROHA_PCS_USXGMII_SPEED_SEL_H BIT(13) #define AIROHA_PCS_USXGMII_PCS_STUS_1 0x30 #define AIROHA_PCS_USXGMII_RX_LINK_STUS BIT(12) #define AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3) #define AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2) #define AIROHA_PCS_USXGMII_PCS_BLK_LK BIT(0) #define AIROHA_PCS_USGMII_VENDOR_DEFINE_116 0x22c #define AIROHA_PCS_USXGMII_PCS_CTRL_0 0x2c0 #define AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN BIT(24) #define AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN BIT(16) #define AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN BIT(8) #define AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN BIT(0) #define AIROHA_PCS_USXGMII_PCS_CTRL_1 0x2c4 #define AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN BIT(24) #define AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN BIT(16) #define AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8) #define AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN BIT(0) #define AIROHA_PCS_USXGMII_PCS_CTRL_2 0x2c8 #define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24) #define AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN BIT(16) #define AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN BIT(8) #define AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN BIT(0) #define AIROHA_PCS_USXGMII_PCS_CTRL_3 0x2cc #define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24) #define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16) #define AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN BIT(8) #define AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN BIT(0) #define AIROHA_PCS_USXGMII_PCS_INT_STA_2 0x2d8 #define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24) #define AIROHA_PCS_USXGMII_R_TYPE_E_INT BIT(16) #define AIROHA_PCS_USXGMII_R_TYPE_T_INT BIT(8) #define AIROHA_PCS_USXGMII_R_TYPE_D_INT BIT(0) #define AIROHA_PCS_USXGMII_PCS_INT_STA_3 0x2dc #define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24) #define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16) #define AIROHA_PCS_USXGMII_LINK_UP_ST_INT BIT(8) #define AIROHA_PCS_USXGMII_HI_BER_ST_INT BIT(0) #define AIROHA_PCS_USXGMII_PCS_CTRL_4 0x2e0 #define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0) #define AIROHA_PCS_USXGMII_PCS_INT_STA_4 0x2e4 #define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0) #define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0 0x2f8 #define AIROHA_PCS_USXGMII_AN_RESTART BIT(8) #define AIROHA_PCS_USXGMII_AN_ENABLE BIT(0) #define AIROHA_PCS_USXGMII_PCS_AN_STATS_0 0x310 #define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE GENMASK(30, 28) #define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0) #define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1) #define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2) #define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3) #define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4) #define AIROHA_PCS_USXGMII_PARTNER_ABILITY GENMASK(15, 0) #define AIROHA_PCS_USXGMII_PCS_AN_STATS_2 0x318 #define AIROHA_PCS_USXGMII_PCS_AN_COMPLETE BIT(24) #define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6 0x31c #define AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0) #define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7 0x320 #define AIROHA_PCS_USXGMII_XFI_MODE_TX_SEL BIT(20) #define AIROHA_PCS_USXGMII_XFI_MODE_RX_SEL BIT(16) #define AIROHA_PCS_USXGMII_RATE_UPDATE_MODE BIT(12) #define AIROHA_PCS_USXGMII_MODE GENMASK(10, 8) #define AIROHA_PCS_USXGMII_MODE_10000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x0) #define AIROHA_PCS_USXGMII_MODE_5000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x1) #define AIROHA_PCS_USXGMII_MODE_2500 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x2) #define AIROHA_PCS_USXGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x3) #define AIROHA_PCS_USXGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x4) #define AN7583_PCS_USXGMII_RTL_MODIFIED 0x334 #define AIROHA_PCS_USXGMII_MODIFIED_RX_GB_OUT_VLD BIT(25) /* PMA_PHYA */ #define AIROHA_PCS_ANA_PXP_CMN_EN 0x0 #define AIROHA_PCS_ANA_CMN_VREFSEL GENMASK(18, 16) #define AIROHA_PCS_ANA_CMN_VREFSEL_8V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x0) #define AIROHA_PCS_ANA_CMN_VREFSEL_8_25V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x1) #define AIROHA_PCS_ANA_CMN_VREFSEL_8_5V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x2) #define AIROHA_PCS_ANA_CMN_VREFSEL_8_75V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x3) #define AIROHA_PCS_ANA_CMN_VREFSEL_9V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x4) #define AIROHA_PCS_ANA_CMN_VREFSEL_9_25V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x5) #define AIROHA_PCS_ANA_CMN_VREFSEL_9_5V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x6) #define AIROHA_PCS_ANA_CMN_VREFSEL_9_75V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x7) #define AIROHA_PCS_ANA_CMN_VREFSEL GENMASK(18, 16) /* GENMASK(2, 0) input selection from 0 to 7 * BIT(3) OPAMP and path EN * BIT(4) Current path measurement * BIT(5) voltage/current path to PAD */ #define AIROHA_PCS_ANA_CMN_MPXSELTOP_DC GENMASK(13, 8) #define AIROHA_PCS_ANA_CMN_EN BIT(0) #define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN 0x4 #define AIROHA_PCS_ANA_JCPLL_CHP_IOFST GENMASK(29, 24) #define AIROHA_PCS_ANA_JCPLL_CHP_IBIAS GENMASK(21, 16) #define AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN BIT(8) #define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR 0x8 #define AIROHA_PCS_ANA_JCPLL_LPF_BWR GENMASK(28, 24) #define AIROHA_PCS_ANA_JCPLL_LPF_BP GENMASK(20, 16) #define AIROHA_PCS_ANA_JCPLL_LPF_BC GENMASK(12, 8) #define AIROHA_PCS_ANA_JCPLL_LPF_BR GENMASK(4, 0) #define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC 0xc #define AIROHA_PCS_ANA_JCPLL_KBAND_DIV GENMASK(26, 24) #define AIROHA_PCS_ANA_JCPLL_KBAND_CODE GENMASK(23, 16) #define AIROHA_PCS_ANA_JCPLL_KBAND_OPTION BIT(8) #define AIROHA_PCS_ANA_JCPLL_LPF_BWC GENMASK(4, 0) #define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC 0x10 #define AIROHA_PCS_ANA_JCPLL_KBAND_KS GENMASK(17, 16) #define AIROHA_PCS_ANA_JCPLL_KBAND_KF GENMASK(9, 8) #define AIROHA_PCS_ANA_JCPLL_KBAND_KFC GENMASK(1, 0) #define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14 #define AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 BIT(24) #define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0) #define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x0) #define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x1) #define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x2) #define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x3) #define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY 0x1c #define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS GENMASK(25, 24) #define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x0) #define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x1) #define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x2) #define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x3) #define AIROHA_PCS_ANA_JCPLL_SDM_DI_EN BIT(16) #define AIROHA_PCS_ANA_JCPLL_PLL_RSTB BIT(8) #define AIROHA_PCS_ANA_JCPLL_RST_DLY GENMASK(2, 0) #define AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x1) #define AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x2) #define AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x3) #define AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x4) #define AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x5) #define AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x6) #define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM 0x20 #define AIROHA_PCS_ANA_JCPLL_SDM_OUT BIT(24) #define AIROHA_PCS_ANA_JCPLL_SDM_ORD GENMASK(17, 16) #define AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0) #define AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x1) #define AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x2) #define AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x3) #define AIROHA_PCS_ANA_JCPLL_SDM_MODE GENMASK(9, 8) #define AIROHA_PCS_ANA_JCPLL_SDM_IFM BIT(0) #define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN 0x24 #define AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF GENMASK(28, 24) #define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN GENMASK(18, 16) #define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x0) #define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x1) #define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x2) #define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x3) #define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x4) #define AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN BIT(8) #define AIROHA_PCS_ANA_JCPLL_SDM_HREN BIT(0) #define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN 0x28 #define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24) #define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x0) #define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x1) #define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x2) #define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x3) #define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x4) #define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x6) #define AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN BIT(16) #define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24) #define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV 0x2c #define AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR GENMASK(26, 24) #define AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN BIT(16) #define AIROHA_PCS_ANA_JCPLL_VCO_CFIX GENMASK(9, 8) #define AIROHA_PCS_ANA_JCPLL_VCODIV GENMASK(1, 0) #define AIROHA_PCS_ANA_JCPLL_VCODIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x0) #define AIROHA_PCS_ANA_JCPLL_VCODIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x1) #define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR 0x30 #define AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI BIT(17) #define AIROHA_PCS_ANA_JCPLL_SSC_EN BIT(16) #define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8) #define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3) #define AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR GENMASK(2, 0) #define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN 0x34 #define AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 GENMASK(23, 8) #define AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN BIT(0) #define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA 0x38 #define AIROHA_PCS_ANA_JCPLL_SSC_PERIOD GENMASK(31, 16) #define AIROHA_PCS_ANA_JCPLL_SSC_DELTA GENMASK(15, 0) #define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H 0x48 #define AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF GENMASK(20, 16) #define AIROHA_PCS_ANA_JCPLL_SPARE_L GENMASK(15, 8) #define AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5)) #define AIROHA_PCS_ANA_PXP_JCPLL_FREQ_MEAS_EN 0x4c #define AIROHA_PCS_ANA_TXPLL_IB_EXT_EN BIT(24) #define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS 0x50 #define AIROHA_PCS_ANA_TXPLL_LPF_BC GENMASK(28, 24) #define AIROHA_PCS_ANA_TXPLL_LPF_BR GENMASK(20, 16) #define AIROHA_PCS_ANA_TXPLL_CHP_IOFST GENMASK(13, 8) #define AIROHA_PCS_ANA_TXPLL_CHP_IBIAS GENMASK(5, 0) #define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP 0x54 #define AIROHA_PCS_ANA_TXPLL_KBAND_OPTION BIT(24) #define AIROHA_PCS_ANA_TXPLL_LPF_BWC GENMASK(20, 16) #define AIROHA_PCS_ANA_TXPLL_LPF_BWR GENMASK(12, 8) #define AIROHA_PCS_ANA_TXPLL_LPF_BP GENMASK(4, 0) #define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE 0x58 #define AIROHA_PCS_ANA_TXPLL_KBAND_KF GENMASK(25, 24) #define AIROHA_PCS_ANA_TXPLL_KBAND_KFC GENMASK(17, 16) #define AIROHA_PCS_ANA_TXPLL_KBAND_DIV GENMASK(10, 8) #define AIROHA_PCS_ANA_TXPLL_KBAND_CODE GENMASK(7, 0) #define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS 0x5c #define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE GENMASK(17, 16) #define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x0) #define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x1) #define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x2) #define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x3) #define AIROHA_PCS_ANA_TXPLL_POSTDIV_EN BIT(8) #define AIROHA_PCS_ANA_TXPLL_KBAND_KS GENMASK(1, 0) #define AIROHA_PCS_ANA_PXP_TXPLL_PHY_CK1_EN 0x60 #define AIROHA_PCS_ANA_TXPLL_PHY_CK2_EN BIT(8) #define AIROHA_PCS_ANA_TXPLL_PHY_CK1_EN BIT(0) #define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL 0x64 #define AIROHA_PCS_ANA_TXPLL_PLL_RSTB BIT(24) #define AIROHA_PCS_ANA_TXPLL_RST_DLY GENMASK(18, 16) #define AIROHA_PCS_ANA_TXPLL_REFIN_DIV GENMASK(9, 8) #define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x0) #define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x1) #define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x2) #define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x3) #define AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL BIT(0) #define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN 0x68 #define AIROHA_PCS_ANA_TXPLL_SDM_MODE GENMASK(25, 24) #define AIROHA_PCS_ANA_TXPLL_SDM_IFM BIT(16) #define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS GENMASK(9, 8) #define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x0) #define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x1) #define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x2) #define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x3) #define AIROHA_PCS_ANA_TXPLL_SDM_DI_EN BIT(0) #define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD 0x6c #define AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN BIT(24) #define AIROHA_PCS_ANA_TXPLL_SDM_HREN BIT(16) #define AIROHA_PCS_ANA_TXPLL_SDM_OUT BIT(8) #define AIROHA_PCS_ANA_TXPLL_SDM_ORD GENMASK(1, 0) #define AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x0) #define AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x1) #define AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x2) #define AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x3) #define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN 0x70 #define AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF GENMASK(12, 8) #define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN GENMASK(2, 0) #define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x0) #define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x1) #define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x2) #define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x3) #define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x4) #define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN 0x74 #define AIROHA_PCS_ANA_TXPLL_VCO_CFIX GENMASK(25, 24) #define AIROHA_PCS_ANA_TXPLL_VCODIV GENMASK(17, 16) #define AIROHA_PCS_ANA_TXPLL_VCODIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x0) #define AIROHA_PCS_ANA_TXPLL_VCODIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x1) #define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW GENMASK(10, 8) #define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x0) #define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x1) #define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x2) #define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x3) #define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x4) #define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x6) #define AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN BIT(0) #define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN 0x78 #define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27) #define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24) #define AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR GENMASK(18, 16) #define AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR GENMASK(10, 8) #define AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN BIT(0) #define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN 0x7c #define AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN BIT(16) #define AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI BIT(8) #define AIROHA_PCS_ANA_TXPLL_SSC_EN BIT(0) #define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1 0x80 #define AIROHA_PCS_ANA_TXPLL_SSC_DELTA GENMASK(31, 16) #define AIROHA_PCS_ANA_TXPLL_SSC_DELTA1 GENMASK(15, 0) #define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD 0x84 #define AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT GENMASK(25, 24) #define AIROHA_PCS_ANA_TXPLL_LDO_OUT GENMASK(17, 16) #define AIROHA_PCS_ANA_TXPLL_SSC_PERIOD GENMASK(15, 0) #define AIROHA_PCS_ANA_PXP_TXPLL_VTP_EN 0x88 #define AIROHA_PCS_ANA_TXPLL_VTP GENMASK(10, 8) #define AIROHA_PCS_ANA_TXPLL_VTP_EN BIT(0) #define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF 0x94 #define AIROHA_PCS_ANA_TXPLL_POSTDIV_D256_EN BIT(25) /* 0: 128 1: 256 */ #define AIROHA_PCS_ANA_TXPLL_VCO_KBAND_MEAS_EN BIT(24) #define AIROHA_PCS_ANA_TXPLL_FREQ_MEAS_EN BIT(16) #define AIROHA_PCS_ANA_TXPLL_VREF_SEL BIT(8) #define AIROHA_PCS_ANA_TXPLL_VREF_SEL_VBG FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VREF_SEL, 0x0) #define AIROHA_PCS_ANA_TXPLL_VREF_SEL_AVDD FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VREF_SEL, 0x1) #define AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF GENMASK(4, 0) #define AN7583_PCS_ANA_PXP_TXPLL_CHP_DOUBLE_EN 0x98 #define AIROHA_PCS_ANA_TXPLL_SPARE_L BIT(0) /* ICHP_DOUBLE */ #define AIROHA_PCS_ANA_PXP_PLL_MONCLK_SEL 0xa0 #define AIROHA_PCS_ANA_TDC_AUTOEN BIT(24) #define AIROHA_PCS_ANA_PXP_TDC_SYNC_CK_SEL 0xa8 #define AIROHA_PCS_ANA_PLL_LDO_CKDRV_VSEL GENMASK(17, 16) #define AIROHA_PCS_ANA_PLL_LDO_CKDRV_EN BIT(8) #define AIROHA_PCS_ANA_PXP_TX_TXLBRC_EN 0xc0 #define AIROHA_PCS_ANA_TX_TERMCAL_VREF_L GENMASK(26, 24) #define AIROHA_PCS_ANA_TX_TERMCAL_VREF_H GENMASK(18, 16) #define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN 0xc4 #define AIROHA_PCS_ANA_TX_DMEDGEGEN_EN BIT(24) #define AIROHA_PCS_ANA_TX_CKLDO_EN BIT(0) #define AIROHA_PCS_ANA_PXP_TX_TERMCAL_SELPN 0xc8 #define AIROHA_PCS_ANA_TX_TDC_CK_SEL GENMASK(17, 16) #define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL 0xcc #define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE BIT(24) #define AIROHA_PCS_ANA_RX_PHY_CK_SEL BIT(16) #define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_PR FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_PHY_CK_SEL, 0x0) #define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_DES FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_PHY_CK_SEL, 0x1) #define AIROHA_PCS_ANA_RX_BUSBIT_SEL_FORCE BIT(8) #define AIROHA_PCS_ANA_RX_BUSBIT_SEL BIT(0) #define AIROHA_PCS_ANA_RX_BUSBIT_SEL_8BIT FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_BUSBIT_SEL, 0x0) #define AIROHA_PCS_ANA_RX_BUSBIT_SEL_16BIT FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_BUSBIT_SEL, 0x1) #define AIROHA_PCS_ANA_PXP_RX_REV_0 0xd4 #define AIROHA_PCS_ANA_RX_REV_1 GENMASK(31, 16) #define AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28) #define AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24) #define AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20) #define AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK GENMASK(19, 18) #define AIROHA_PCS_ANA_REV_1_FECUR_PWDB BIT(16) #define AIROHA_PCS_ANA_RX_REV_0 GENMASK(15, 0) #define AIROHA_PCS_ANA_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12) #define AIROHA_PCS_ANA_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11) #define AIROHA_PCS_ANA_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10) #define AIROHA_PCS_ANA_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8) #define AIROHA_PCS_ANA_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6) #define AIROHA_PCS_ANA_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4) #define AIROHA_PCS_ANA_REV_0_VOS_PNINV GENMASK(3, 2) #define AIROHA_PCS_ANA_REV_0_PLEYEBD4 BIT(1) #define AIROHA_PCS_ANA_REV_0_PLEYE_XOR_MON_EN BIT(0) #define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV 0xd8 #define AIROHA_PCS_ANA_RX_TDC_CK_SEL BIT(24) #define AIROHA_PCS_ANA_RX_PHYCK_RSTB BIT(16) #define AIROHA_PCS_ANA_RX_PHYCK_SEL GENMASK(9, 8) #define AIROHA_PCS_ANA_RX_PHYCK_DIV GENMASK(7, 0) #define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc #define AIROHA_PCS_ANA_CDR_PD_EDGE_DIS BIT(8) #define AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV BIT(0) #define AIROHA_PCS_ANA_PXP_CDR_LPF_BOT_LIM 0xe0 #define AIROHA_PCS_ANA_CDR_LPF_BOT_LIM GENMASK(18, 0) #define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO 0xe8 #define AIROHA_PCS_ANA_CDR_LPF_TOP_LIM GENMASK(26, 8) #define AIROHA_PCS_ANA_CDR_LPF_RATIO GENMASK(1, 0) #define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE 0xf4 #define AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF BIT(24) #define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC 0xf8 #define AIROHA_PCS_ANA_CDR_PR_KBAND_DIV GENMASK(26, 24) #define AIROHA_PCS_ANA_CDR_PR_BETA_SEL GENMASK(19, 16) #define AIROHA_PCS_ANA_CDR_PR_VCOADC_OS GENMASK(11, 8) #define AIROHA_PCS_ANA_CDR_PR_BETA_DAC GENMASK(6, 0) #define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc #define AIROHA_PCS_ANA_CDR_PR_FBKSEL GENMASK(25, 24) #define AIROHA_PCS_ANA_CDR_PR_DAC_BAND GENMASK(20, 16) #define AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL GENMASK(10, 8) #define AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL GENMASK(2, 0) #define AIROHA_PCS_ANA_PXP_CDR_PR_CKREF_DIV 0x100 #define AIROHA_PCS_ANA_CDR_PR_RSTB_BYPASS BIT(16) #define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV GENMASK(1, 0) #define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x0) #define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x1) #define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x2) #define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_X FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x3) #define AIROHA_PCS_ANA_PXP_CDR_PR_TDC_REF_SEL 0x108 #define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1 GENMASK(25, 24) #define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x0) #define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x1) #define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x2) #define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_X FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x3) #define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN 0x10c #define AIROHA_PCS_ANA_RX_DAC_MON GENMASK(28, 24) #define AIROHA_PCS_ANA_CDR_PR_CAP_EN BIT(19) #define AIROHA_PCS_ANA_CDR_BUF_IN_SR GENMASK(18, 16) #define AIROHA_PCS_ANA_CDR_PR_XFICK_EN BIT(2) #define AIROHA_PCS_ANA_CDR_PR_MONDPI_EN BIT(1) #define AIROHA_PCS_ANA_CDR_PR_MONDPR_EN BIT(0) #define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE 0x110 #define AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL GENMASK(25, 24) #define AIROHA_PCS_ANA_RX_DAC_RANGE_EYE GENMASK(9, 8) #define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH 0x114 #define AIROHA_PCS_ANA_RX_FE_50OHMS_SEL GENMASK(25, 24) #define AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL GENMASK(20, 16) #define AIROHA_PCS_ANA_RX_SIGDET_PEAK GENMASK(9, 8) #define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN 0x118 #define AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN BIT(24) #define AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN BIT(16) #define AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN BIT(8) #define AIROHA_PCS_ANA_RX_FE_EQ_HZEN BIT(0) #define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB 0x11c #define AIROHA_PCS_ANA_FE_VCM_GEN_PWDB BIT(0) #define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW 0x120 #define AIROHA_PCS_ANA_RX_OSCAL_FORCE GENMASK(17, 8) #define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(0)) #define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(1)) #define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(2)) #define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(3)) #define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(4)) #define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(5)) #define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(6)) #define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(7)) #define AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(8)) #define AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(9)) #define AIROHA_PCS_ANA_PXP_AEQ_CFORCE 0x13c #define AIROHA_PCS_ANA_AEQ_OFORCE GENMASK(19, 8) #define AIROHA_PCS_ANA_AEQ_OFORCE_SAOS FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(0)) #define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(1)) #define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(2)) #define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(3)) #define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(4)) #define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(5)) #define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(6)) #define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(7)) #define AIROHA_PCS_ANA_AEQ_OFORCE_VGA FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(8)) #define AIROHA_PCS_ANA_AEQ_OFORCE_CTLE FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(9)) #define AIROHA_PCS_ANA_AEQ_OFORCE_ATT FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(10)) #define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144 #define AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ BIT(24) #define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ 0x148 #define AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ BIT(24) #define AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ BIT(16) #define AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ BIT(8) #define AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ BIT(0) /* PMA_PHYD */ #define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0 0x0 #define AIROHA_PCS_PMA_SW_LCPLL_EN BIT(24) #define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1 0x4 #define AIROHA_PCS_PMA_LCPLL_CK_STB_TIMER GENMASK(31, 24) #define AIROHA_PCS_PMA_LCPLL_PCW_MAN_LOAD_TIMER GENMASK(23, 16) #define AIROHA_PCS_PMA_LCPLL_EN_TIMER GENMASK(15, 8) #define AIROHA_PCS_PMA_LCPLL_MAN_PWDB BIT(0) #define AIROHA_PCS_PMA_LCPLL_TDC_PW_0 0x10 #define AIROHA_PCS_PMA_LCPLL_TDC_DIG_PWDB BIT(0) #define AIROHA_PCS_PMA_LCPLL_TDC_PW_5 0x24 #define AIROHA_PCS_PMA_LCPLL_TDC_SYNC_IN_MODE BIT(24) #define AIROHA_PCS_PMA_LCPLL_AUTOK_TDC BIT(16) #define AIROHA_PCS_PMA_LCPLL_TDC_FLT_0 0x28 #define AIROHA_PCS_PMA_LCPLL_KI GENMASK(10, 8) #define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC GENMASK(1, 0) #define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_32 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x0) #define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_16 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x1) #define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x2) #define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x3) #define AIROHA_PCS_PMA_LCPLL_TDC_FLT_1 0x2c #define AIROHA_PCS_PMA_LCPLL_A_TDC GENMASK(11, 8) #define AIROHA_PCS_PMA_LCPLL_GPON_SEL BIT(0) #define AIROHA_PCS_PMA_LCPLL_GPON_SEL_FROM_EPON FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_GPON_SEL, 0x0) #define AIROHA_PCS_PMA_LCPLL_GPON_SEL_FROM_GPON FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_GPON_SEL, 0x1) #define AIROHA_PCS_PMA_LCPLL_TDC_FLT_3 0x34 #define AIROHA_PCS_PMA_LCPLL_NCPO_LOAD BIT(8) #define AIROHA_PCS_PMA_LCPLL_NCPO_SHIFT GENMASK(1, 0) #define AIROHA_PCS_PMA_LCPLL_TDC_FLT_5 0x3c #define AIROHA_PCS_PMA_LCPLL_TDC_AUTOPW_NCPO BIT(16) #define AIROHA_PCS_PMA_LCPLL_TDC_FLT_6 0x40 #define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY GENMASK(9, 8) #define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x0) #define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D1 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x1) #define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D2 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x2) #define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D3 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x3) #define AIROHA_PCS_PMA_LCPLL_TDC_PCW_1 0x48 #define AIROHA_PCS_PMA_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0) #define AIROHA_PCS_PMA_LCPLL_TDC_PCW_2 0x4c #define AIROHA_PCS_PMA_LCPLL_PON_HRDDS_PCW_NCPO_EPON GENMASK(30, 0) #define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_0 0x68 #define AIROHA_PCS_PMA_X_MAX GENMASK(26, 16) #define AIROHA_PCS_PMA_X_MIN GENMASK(10, 0) #define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_1 0x6c #define AIROHA_PCS_PMA_INDEX_MODE BIT(16) #define AIROHA_PCS_PMA_Y_MAX GENMASK(14, 8) #define AIROHA_PCS_PMA_Y_MIN GENMASK(6, 0) #define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_2 0x70 #define AIROHA_PCS_PMA_EYEDUR GENMASK(19, 0) #define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_3 0x74 #define AIROHA_PCS_PMA_EYE_NEXTPTS BIT(16) #define AIROHA_PCS_PMA_EYE_NEXTPTS_TOGGLE BIT(8) #define AIROHA_PCS_PMA_EYE_NEXTPTS_SEL BIT(0) #define AIROHA_PCS_PMA_RX_EYE_TOP_EYEOPENING_CTRL_0 0x78 #define AIROHA_PCS_PMA_EYECNT_VTH GENMASK(15, 8) #define AIROHA_PCS_PMA_EYECNT_HTH GENMASK(7, 0) #define AIROHA_PCS_PMA_RX_EYE_TOP_EYEOPENING_CTRL_1 0x7c #define AIROHA_PCS_PMA_EO_VTH GENMASK(23, 16) #define AIROHA_PCS_PMA_EO_HTH GENMASK(10, 0) #define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_0 0x80 #define AIROHA_PCS_PMA_EYE_MASK GENMASK(31, 24) #define AIROHA_PCS_PMA_CNTFOREVER BIT(16) #define AIROHA_PCS_PMA_CNTLEN GENMASK(9, 0) #define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1 0x84 #define AIROHA_PCS_PMA_FORCE_EYEDUR_INIT_B BIT(24) #define AIROHA_PCS_PMA_FORCE_EYEDUR_EN BIT(16) #define AIROHA_PCS_PMA_DISB_EYEDUR_INIT_B BIT(8) #define AIROHA_PCS_PMA_DISB_EYEDUR_EN BIT(0) #define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2 0x88 #define AIROHA_PCS_PMA_DATA_SHIFT BIT(8) #define AIROHA_PCS_PMA_EYECNT_FAST BIT(0) #define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0 0x8c #define AIROHA_PCS_PMA_RX_OS_START GENMASK(23, 8) #define AIROHA_PCS_PMA_OSC_SPEED_OPT GENMASK(2, 0) #define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0) #define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1) #define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2) #define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3) #define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4) #define AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5) #define AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6) #define AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7) #define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1 0x90 #define AIROHA_PCS_PMA_RX_PICAL_END GENMASK(31, 16) #define AIROHA_PCS_PMA_RX_PICAL_START GENMASK(15, 0) #define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2 0x94 #define AIROHA_PCS_PMA_RX_PDOS_END GENMASK(31, 16) #define AIROHA_PCS_PMA_RX_PDOS_START GENMASK(15, 0) #define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3 0x98 #define AIROHA_PCS_PMA_RX_FEOS_END GENMASK(31, 16) #define AIROHA_PCS_PMA_RX_FEOS_START GENMASK(15, 0) #define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4 0x9c #define AIROHA_PCS_PMA_RX_SDCAL_END GENMASK(31, 16) #define AIROHA_PCS_PMA_RX_SDCAL_START GENMASK(15, 0) #define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5 0x100 #define AIROHA_PCS_PMA_RX_RDY GENMASK(31, 16) #define AIROHA_PCS_PMA_RX_BLWC_RDY_EN GENMASK(15, 0) #define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6 0x104 #define AIROHA_PCS_PMA_RX_OS_END GENMASK(15, 0) #define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0 0x108 #define AIROHA_PCS_PMA_DISB_RX_FEOS_EN BIT(24) #define AIROHA_PCS_PMA_DISB_RX_PDOS_EN BIT(16) #define AIROHA_PCS_PMA_DISB_RX_PICAL_EN BIT(8) #define AIROHA_PCS_PMA_DISB_RX_OS_EN BIT(0) #define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c #define AIROHA_PCS_PMA_DISB_RX_RDY BIT(24) #define AIROHA_PCS_PMA_DISB_RX_BLWC_EN BIT(16) #define AIROHA_PCS_PMA_DISB_RX_OS_RDY BIT(8) #define AIROHA_PCS_PMA_DISB_RX_SDCAL_EN BIT(0) #define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0 0x110 #define AIROHA_PCS_PMA_FORCE_RX_FEOS_EN BIT(24) #define AIROHA_PCS_PMA_FORCE_RX_PDOS_EN BIT(16) #define AIROHA_PCS_PMA_FORCE_RX_PICAL_EN BIT(8) #define AIROHA_PCS_PMA_FORCE_RX_OS_EN BIT(0) #define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114 #define AIROHA_PCS_PMA_FORCE_RX_RDY BIT(24) #define AIROHA_PCS_PMA_FORCE_RX_BLWC_EN BIT(16) #define AIROHA_PCS_PMA_FORCE_RX_OS_RDY BIT(8) #define AIROHA_PCS_PMA_FORCE_RX_SDCAL_EN BIT(0) #define AIROHA_PCS_PMA_PHY_EQ_CTRL_0 0x118 #define AIROHA_PCS_PMA_VEO_MASK GENMASK(31, 24) #define AIROHA_PCS_PMA_HEO_MASK GENMASK(18, 8) #define AIROHA_PCS_PMA_EQ_EN_DELAY GENMASK(7, 0) #define AIROHA_PCS_PMA_PHY_EQ_CTRL_1 0x11c #define AIROHA_PCS_PMA_B_ZERO_SEL BIT(24) #define AIROHA_PCS_PMA_HEO_EMPHASIS BIT(16) #define AIROHA_PCS_PMA_A_MGAIN BIT(8) #define AIROHA_PCS_PMA_A_LGAIN BIT(0) #define AIROHA_PCS_PMA_PHY_EQ_CTRL_2 0x120 #define AIROHA_PCS_PMA_EQ_DEBUG_SEL GENMASK(17, 16) #define AIROHA_PCS_PMA_FOM_NUM_ORDER GENMASK(12, 8) #define AIROHA_PCS_PMA_A_SEL GENMASK(1, 0) #define AIROHA_PCS_PMA_SS_RX_FEOS 0x144 #define AIROHA_PCS_PMA_EQ_FORCE_BLWC_FREEZE BIT(8) #define AIROHA_PCS_PMA_LFSEL GENMASK(7, 0) #define AIROHA_PCS_PMA_SS_RX_BLWC 0x148 #define AIROHA_PCS_PMA_EQ_BLWC_CNT_BOT_LIM GENMASK(29, 23) #define AIROHA_PCS_PMA_EQ_BLWC_CNT_TOP_LIM GENMASK(22, 16) #define AIROHA_PCS_PMA_EQ_BLWC_GAIN GENMASK(11, 8) #define AIROHA_PCS_PMA_EQ_BLWC_POL BIT(0) #define AIROHA_PCS_PMA_EQ_BLWC_POL_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_EQ_BLWC_POL, 0x0) #define AIROHA_PCS_PMA_EQ_BLWC_POL_INVERSION FIELD_PREP_CONST(AIROHA_PCS_PMA_EQ_BLWC_POL, 0x1) #define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1 0x14c #define AIROHA_PCS_PMA_UNLOCK_CYCLECNT GENMASK(31, 16) #define AIROHA_PCS_PMA_LOCK_CYCLECNT GENMASK(15, 0) #define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2 0x150 #define AIROHA_PCS_PMA_LOCK_TARGET_END GENMASK(31, 16) #define AIROHA_PCS_PMA_LOCK_TARGET_BEG GENMASK(15, 0) #define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3 0x154 #define AIROHA_PCS_PMA_UNLOCK_TARGET_END GENMASK(31, 16) #define AIROHA_PCS_PMA_UNLOCK_TARGET_BEG GENMASK(15, 0) #define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4 0x158 #define AIROHA_PCS_PMA_LOCK_UNLOCKTH GENMASK(15, 12) #define AIROHA_PCS_PMA_LOCK_LOCKTH GENMASK(11, 8) #define AIROHA_PCS_PMA_FREQLOCK_DET_EN GENMASK(2, 0) #define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0) #define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1) #define AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2) #define AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3) #define AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7) #define AIROHA_PCS_PMA_RX_PI_CAL 0x15c #define AIROHA_PCS_PMA_KPGAIN GENMASK(10, 8) #define AIROHA_PCS_PMA_RX_CAL1 0x160 #define AIROHA_PCS_PMA_CAL_CYC GENMASK(25, 24) #define AIROHA_PCS_PMA_CAL_CYC_63 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x0) #define AIROHA_PCS_PMA_CAL_CYC_15 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x1) #define AIROHA_PCS_PMA_CAL_CYC_31 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x2) #define AIROHA_PCS_PMA_CAL_CYC_127 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x3) #define AIROHA_PCS_PMA_CAL_STB GENMASK(17, 16) #define AIROHA_PCS_PMA_CAL_STB_5US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x0) #define AIROHA_PCS_PMA_CAL_STB_8US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x1) #define AIROHA_PCS_PMA_CAL_STB_16US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x2) #define AIROHA_PCS_PMA_CAL_STB_32US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x3) #define AIROHA_PCS_PMA_CAL_1US_SET GENMASK(15, 8) #define AIROHA_PCS_PMA_SIM_FAST_EN BIT(0) #define AIROHA_PCS_PMA_RX_CAL2 0x164 #define AIROHA_PCS_PMA_CAL_CYC_TIME GENMASK(17, 16) #define AIROHA_PCS_PMA_CAL_OUT_OS GENMASK(11, 8) #define AIROHA_PCS_PMA_CAL_OS_PULSE BIT(0) #define AIROHA_PCS_PMA_SS_RX_SIGDET_1 0x16c #define AIROHA_PCS_PMA_SIGDET_EN BIT(0) #define AIROHA_PCS_PMA_RX_FLL_0 0x170 #define AIROHA_PCS_PMA_KBAND_KFC GENMASK(25, 24) #define AIROHA_PCS_PMA_KBAND_KFC_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x0) #define AIROHA_PCS_PMA_KBAND_KFC_16 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x1) #define AIROHA_PCS_PMA_KBAND_KFC_32 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x2) #define AIROHA_PCS_PMA_KBAND_KFC_64 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x3) #define AIROHA_PCS_PMA_FPKDIV GENMASK(18, 8) #define AIROHA_PCS_PMA_KBAND_PREDIV GENMASK(2, 0) #define AIROHA_PCS_PMA_KBAND_PREDIV_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x0) #define AIROHA_PCS_PMA_KBAND_PREDIV_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x1) #define AIROHA_PCS_PMA_KBAND_PREDIV_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x2) #define AIROHA_PCS_PMA_KBAND_PREDIV_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x3) #define AIROHA_PCS_PMA_RX_FLL_1 0x174 #define AIROHA_PCS_PMA_SYMBOL_WD GENMASK(26, 24) #define AIROHA_PCS_PMA_SETTLE_TIME_SEL GENMASK(18, 16) #define AIROHA_PCS_PMA_LPATH_IDAC GENMASK(10, 0) #define AIROHA_PCS_PMA_RX_FLL_2 0x178 #define AIROHA_PCS_PMA_CK_RATE GENMASK(18, 16) #define AIROHA_PCS_PMA_CK_RATE_20 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0) #define AIROHA_PCS_PMA_CK_RATE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1) #define AIROHA_PCS_PMA_CK_RATE_5 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2) #define AIROHA_PCS_PMA_AMP GENMASK(10, 8) #define AIROHA_PCS_PMA_PRBS_SEL GENMASK(2, 0) #define AIROHA_PCS_PMA_RX_FLL_5 0x184 #define AIROHA_PCS_PMA_FLL_IDAC_MIN GENMASK(26, 16) #define AIROHA_PCS_PMA_FLL_IDAC_MAX GENMASK(10, 0) #define AIROHA_PCS_PMA_RX_FLL_6 0x188 #define AIROHA_PCS_PMA_LNX_SW_FLL_4_LATCH_EN BIT(24) #define AIROHA_PCS_PMA_LNX_SW_FLL_3_LATCH_EN BIT(16) #define AIROHA_PCS_PMA_LNX_SW_FLL_2_LATCH_EN BIT(8) #define AIROHA_PCS_PMA_LNX_SW_FLL_1_LATCH_EN BIT(0) #define AIROHA_PCS_PMA_RX_FLL_B 0x19c #define AIROHA_PCS_PMA_LOAD_EN BIT(0) #define AIROHA_PCS_PMA_RX_PDOS_CTRL_0 0x200 #define AIROHA_PCS_PMA_SAP_SEL GENMASK(18, 16) #define AIROHA_PCS_PMA_SAP_SEL_SHIFT_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x0) #define AIROHA_PCS_PMA_SAP_SEL_SHIFT_7 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x1) #define AIROHA_PCS_PMA_SAP_SEL_SHIFT_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x2) #define AIROHA_PCS_PMA_SAP_SEL_SHIFT_9 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x3) #define AIROHA_PCS_PMA_SAP_SEL_SHIFT_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x4) #define AIROHA_PCS_PMA_EYE_BLWC_ADD BIT(8) #define AIROHA_PCS_PMA_DATA_BLWC_ADD BIT(0) #define AIROHA_PCS_PMA_RX_RESET_0 0x204 #define AIROHA_PCS_PMA_CAL_RST_B BIT(24) #define AIROHA_PCS_PMA_EQ_PI_CAL_RST_B BIT(16) #define AIROHA_PCS_PMA_FEOS_RST_B BIT(8) #define AIROHA_PCS_PMA_RX_RESET_1 0x208 #define AIROHA_PCS_PMA_SIGDET_RST_B BIT(8) #define AIROHA_PCS_PMA_PDOS_RST_B BIT(0) #define AIROHA_PCS_PMA_RX_DEBUG_0 0x20c #define AIROHA_PCS_PMA_RO_TOGGLE BIT(24) #define AIROHA_PCS_PMA_BISTCTL_CONTROL 0x210 #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL GENMASK(4, 0) /* AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x0) */ #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS7 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x1) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS9 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x2) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS15 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x3) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS23 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x4) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS31 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x5) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_HFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x6) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_MFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x7) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x8) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_5_LFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x9) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xa) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_7 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xb) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_8_LFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xc) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_9 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xd) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xe) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_11 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xf) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PROG_80 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x10) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x11) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x12) #define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS11 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x13) #define AIROHA_PCS_PMA_BISTCTL_ALIGN_PAT 0x214 #define AIROHA_PCS_PMA_BISTCTL_POLLUTION 0x220 #define AIROHA_PCS_PMA_BIST_TX_DATA_POLLUTION_LATCH BIT(16) #define AIROHA_PCS_PMA_BISTCTL_PRBS_INITIAL_SEED 0x224 #define AIROHA_PCS_PMA_BISTCTL_PRBS_FAIL_THRESHOLD 0x230 #define AIROHA_PCS_PMA_BISTCTL_PRBS_FAIL_THRESHOLD_MASK GENMASK(15, 0) #define AIROHA_PCS_PMA_RX_TORGS_DEBUG_2 0x23c #define AIROHA_PCS_PMA_PI_CAL_DATA_OUT GENMASK(22, 16) #define AIROHA_PCS_PMA_RX_TORGS_DEBUG_5 0x248 #define AIROHA_PCS_PMA_VEO_RDY BIT(24) #define AIROHA_PCS_PMA_HEO_RDY BIT(16) #define AIROHA_PCS_PMA_RX_TORGS_DEBUG_9 0x258 #define AIROHA_PCS_PMA_EO_Y_DONE BIT(24) #define AIROHA_PCS_PMA_EO_X_DONE BIT(16) #define AIROHA_PCS_PMA_RX_TORGS_DEBUG_10 0x25c #define AIROHA_PCS_PMA_EYE_EL GENMASK(26, 16) #define AIROHA_PCS_PMA_EYE_ER GENMASK(10, 0) #define AIROHA_PCS_PMA_TX_RST_B 0x260 #define AIROHA_PCS_PMA_TXCALIB_RST_B BIT(8) #define AIROHA_PCS_PMA_TX_TOP_RST_B BIT(0) #define AIROHA_PCS_PMA_TX_CALIB_0 0x264 #define AIROHA_PCS_PMA_TXCALIB_FORCE_TERMP_SEL GENMASK(25, 24) #define AIROHA_PCS_PMA_TXCALIB_FORCE_TERMP_SEL_EN BIT(16) #define AIROHA_PCS_PMA_RX_TORGS_DEBUG_11 0x290 #define AIROHA_PCS_PMA_EYE_EB GENMASK(14, 8) #define AIROHA_PCS_PMA_EYE_EU GENMASK(6, 0) #define AIROHA_PCS_PMA_RX_FORCE_MODE_0 0x294 #define AIROHA_PCS_PMA_FORCE_DA_XPON_CDR_LPF_RSTB BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_XPON_RX_FE_GAIN_CTRL GENMASK(1, 0) #define AIROHA_PCS_PMA_RX_DISB_MODE_0 0x300 #define AIROHA_PCS_PMA_DISB_DA_XPON_CDR_LPF_RSTB BIT(24) #define AIROHA_PCS_PMA_DISB_DA_XPON_RX_FE_GAIN_CTRL BIT(0) #define AIROHA_PCS_PMA_RX_DISB_MODE_1 0x304 #define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_E0 BIT(24) #define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_D1 BIT(16) #define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_D0 BIT(8) #define AIROHA_PCS_PMA_RX_DISB_MODE_2 0x308 #define AIROHA_PCS_PMA_DISB_DA_XPON_CDR_PR_PIEYE BIT(24) #define AIROHA_PCS_PMA_DISB_DA_XPON_RX_FE_VOS BIT(16) #define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_EYE BIT(8) #define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_E1 BIT(0) #define AIROHA_PCS_PMA_RX_FORCE_MODE_3 0x30c #define AIROHA_PCS_PMA_FORCE_EQ_PI_CAL_RDY BIT(0) #define AIROHA_PCS_PMA_RX_FORCE_MODE_6 0x318 #define AIROHA_PCS_PMA_FORCE_RX_OR_PICAL_EN BIT(8) #define AIROHA_PCS_PMA_FORCE_EYECNT_RDY BIT(0) #define AIROHA_PCS_PMA_RX_DISB_MODE_3 0x31c #define AIROHA_PCS_PMA_DISB_RQ_PI_CAL_RDY BIT(0) #define AIROHA_PCS_PMA_RX_DISB_MODE_4 0x320 #define AIROHA_PCS_PMA_DISB_BLWC_OFFSET BIT(24) #define AIROHA_PCS_PMA_RX_DISB_MODE_5 0x324 #define AIROHA_PCS_PMA_DISB_RX_OR_PICAL_EN BIT(24) #define AIROHA_PCS_PMA_DISB_EYECNT_RDY BIT(16) #define AIROHA_PCS_PMA_RX_FORCE_MODE_7 0x328 #define AIROHA_PCS_PMA_FORCE_PDOS_RX_RST_B BIT(16) #define AIROHA_PCS_PMA_FORCE_RX_AND_PICAL_RSTB BIT(8) #define AIROHA_PCS_PMA_FORCE_REF_AND_PICAL_RSTB BIT(0) #define AIROHA_PCS_PMA_RX_FORCE_MODE_8 0x32c #define AIROHA_PCS_PMA_FORCE_EYECNT_RX_RST_B BIT(24) #define AIROHA_PCS_PMA_FORCE_FEOS_RX_RST_B BIT(16) #define AIROHA_PCS_PMA_FORCE_SDCAL_REF_RST_B BIT(8) #define AIROHA_PCS_PMA_FORCE_BLWC_RX_RST_B BIT(0) #define AIROHA_PCS_PMA_RX_FORCE_MODE_9 0x330 #define AIROHA_PCS_PMA_FORCE_EYE_TOP_EN BIT(16) #define AIROHA_PCS_PMA_FORCE_EYE_RESET_PLU_O BIT(8) #define AIROHA_PCS_PMA_FORCE_FBCK_LOCK BIT(0) #define AIROHA_PCS_PMA_RX_DISB_MODE_6 0x334 #define AIROHA_PCS_PMA_DISB_PDOS_RX_RST_B BIT(16) #define AIROHA_PCS_PMA_DISB_RX_AND_PICAL_RSTB BIT(8) #define AIROHA_PCS_PMA_DISB_REF_AND_PICAL_RSTB BIT(0) #define AIROHA_PCS_PMA_RX_DISB_MODE_7 0x338 #define AIROHA_PCS_PMA_DISB_EYECNT_RX_RST_B BIT(24) #define AIROHA_PCS_PMA_DISB_FEOS_RX_RST_B BIT(16) #define AIROHA_PCS_PMA_DISB_SDCAL_REF_RST_B BIT(8) #define AIROHA_PCS_PMA_DISB_BLWC_RX_RST_B BIT(0) #define AIROHA_PCS_PMA_RX_DISB_MODE_8 0x33c #define AIROHA_PCS_PMA_DISB_EYE_TOP_EN BIT(16) #define AIROHA_PCS_PMA_DISB_EYE_RESET_PLU_O BIT(8) #define AIROHA_PCS_PMA_DISB_FBCK_LOCK BIT(0) #define AIROHA_PCS_PMA_SS_BIST_1 0x344 #define AIROHA_PCS_PMA_LNX_BISTCTL_BIT_ERROR_RST_SEL BIT(24) #define AIROHA_PCS_PMA_ANLT_PX_LNX_LT_LOS BIT(0) #define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0 0x34c #define AIROHA_PCS_PMA_XPON_CDR_PD_PWDB BIT(24) #define AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB BIT(16) #define AIROHA_PCS_PMA_XPON_CDR_PW_PWDB BIT(8) #define AIROHA_PCS_PMA_XPON_RX_FE_PWDB BIT(0) #define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1 0x350 #define AIROHA_PCS_PMA_RX_SIDGET_PWDB BIT(0) #define AIROHA_PCS_PMA_DIG_RESERVE_0 0x360 #define AIROHA_PCS_PMA_XPON_RX_RESERVED_1 0x374 #define AIROHA_PCS_PMA_XPON_RX_RATE_CTRL GENMASK(1, 0) #define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0 0x38c #define AIROHA_PCS_PMA_RX_SYS_EN_SEL GENMASK(1, 0) #define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0 0x390 #define AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT GENMASK(15, 0) #define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1 0x394 #define AIROHA_PCS_PMA_PLL_LOCK_TARGET_END GENMASK(31, 16) #define AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG GENMASK(15, 0) #define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3 0x39c #define AIROHA_PCS_PMA_PLL_LOCK_LOCKTH GENMASK(11, 8) #define AIROHA_PCS_PMA_ADD_CLKPATH_RST_0 0x410 #define AIROHA_PCS_PMA_CLKPATH_RSTB_CK BIT(8) #define AIROHA_PCS_PMA_CLKPATH_RST_EN BIT(0) #define AIROHA_PCS_PMA_ADD_XPON_MODE_1 0x414 #define AIROHA_PCS_PMA_TX_BIST_GEN_EN BIT(16) #define AIROHA_PCS_PMA_R2T_MODE BIT(8) #define AIROHA_PCS_PMA_ADD_RX2ANA_1 0x424 #define AIROHA_PCS_PMA_RX_DAC_E0 GENMASK(30, 24) #define AIROHA_PCS_PMA_RX_DAC_D1 GENMASK(22, 16) #define AIROHA_PCS_PMA_RX_DAC_D0 GENMASK(14, 8) #define AIROHA_PCS_PMA_RX_DAC_EYE GENMASK(6, 0) #define AIROHA_PCS_PMA_ADD_RX2ANA_2 0x428 #define AIROHA_PCS_PMA_RX_FEOS_OUT GENMASK(13, 8) #define AIROHA_PCS_PMA_RX_DAC_E1 GENMASK(6, 0) #define AIROHA_PCS_PMA_PON_TX_COUNTER_0 0x440 #define AIROHA_PCS_PMA_TXCALIB_5US GENMASK(31, 16) #define AIROHA_PCS_PMA_TXCALIB_50US GENMASK(15, 0) #define AIROHA_PCS_PMA_PON_TX_COUNTER_1 0x444 #define AIROHA_PCS_PMA_TX_HSDATA_EN_WAIT GENMASK(31, 16) #define AIROHA_PCS_PMA_TX_CK_EN_WAIT GENMASK(15, 0) #define AIROHA_PCS_PMA_PON_TX_COUNTER_2 0x448 #define AIROHA_PCS_PMA_TX_SERDES_RDY_WAIT GENMASK(31, 16) #define AIROHA_PCS_PMA_TX_POWER_ON_WAIT GENMASK(15, 0) #define AIROHA_PCS_PMA_SW_RST_SET 0x460 #define AIROHA_PCS_PMA_SW_XFI_RXMAC_RST_N BIT(17) #define AIROHA_PCS_PMA_SW_XFI_TXMAC_RST_N BIT(16) #define AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N BIT(11) #define AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N BIT(10) #define AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N BIT(9) #define AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N BIT(8) #define AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N BIT(7) #define AIROHA_PCS_PMA_SW_TX_FIFO_RST_N BIT(6) #define AIROHA_PCS_PMA_SW_REF_RST_N BIT(5) #define AIROHA_PCS_PMA_SW_ALLPCS_RST_N BIT(4) #define AIROHA_PCS_PMA_SW_PMA_RST_N BIT(3) #define AIROHA_PCS_PMA_SW_TX_RST_N BIT(2) #define AIROHA_PCS_PMA_SW_RX_RST_N BIT(1) #define AIROHA_PCS_PMA_SW_RX_FIFO_RST_N BIT(0) #define AIROHA_PCS_PMA_TX_DLY_CTRL 0x468 #define AIROHA_PCS_PMA_OUTBEN_DATA_MODE GENMASK(30, 28) #define AIROHA_PCS_PMA_TX_BEN_EXTEN_FTUNE GENMASK(23, 16) #define AIROHA_PCS_PMA_TX_DLY_BEN_FTUNE GENMASK(14, 8) #define AIROHA_PCS_PMA_TX_DLY_DATA_FTUNE GENMASK(6, 0) #define AIROHA_PCS_PMA_XPON_INT_EN_3 0x474 #define AIROHA_PCS_PMA_RX_SIGDET_INT_EN BIT(16) #define AIROHA_PCS_PMA_XPON_INT_STA_3 0x47c #define AIROHA_PCS_PMA_RX_SIGDET_INT BIT(16) #define AIROHA_PCS_PMA_RX_EXTRAL_CTRL 0x48c /* 4ref_ck step: * - 0x1 4ref_ck * - 0x2 8ref_ck * - 0x3 12ref_ck * ... */ #define AIROHA_PCS_PMA_L2D_TRIG_EQ_EN_TIME GENMASK(15, 8) #define AIROHA_PCS_PMA_OS_RDY_LATCH BIT(1) #define AIROHA_PCS_PMA_DISB_LEQ BIT(0) #define AIROHA_PCS_PMA_RX_FREQDET 0x530 #define AIROHA_PCS_PMA_FL_OUT GENMASK(31, 16) #define AIROHA_PCS_PMA_FBCK_LOCK BIT(0) #define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL 0x580 #define AIROHA_PCS_PMA_PON_TX_RATE_CTRL GENMASK(1, 0) #define AIROHA_PCS_PMA_MD32_MEM_CLK_CTRL 0x60c #define AIROHA_PCS_PMA_MD32PM_CK_SEL GENMASK(31, 0) #define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN 0x768 #define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL GENMASK(19, 16) #define AIROHA_PCS_PMA_PXP_AEQ_SPEED 0x76c #define AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_OSR_SEL GENMASK(17, 16) #define AIROHA_PCS_PMA_PXP_TX_FIR_C0B 0x778 #define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 GENMASK(20, 16) #define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B GENMASK(5, 0) #define AIROHA_PCS_PMA_PXP_TX_TERM_SEL 0x77c #define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16) #define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL GENMASK(2, 0) #define AIROHA_PCS_PMA_PXP_TX_FIR_C1 0x780 #define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 GENMASK(20, 16) #define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1 GENMASK(5, 0) #define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL 0x784 #define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE GENMASK(22, 16) #define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0) #define AIROHA_PCS_PMA_PXP_CDR_PR_FLL_COR 0x790 #define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_DAC_EYE BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_RX_DAC_EYE GENMASK(22, 16) #define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC 0x794 #define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24) #define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16) #define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC GENMASK(10, 0) #define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8) #define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW 0x798 #define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW GENMASK(30, 0) #define AIROHA_PCS_PMA_PXP_RX_FE_VOS 0x79c #define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16) #define AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_FE_VOS GENMASK(5, 0) #define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW 0x800 #define AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW GENMASK(30, 0) #define AIROHA_PCS_PMA_PXP_AEQ_BYPASS 0x80c #define AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON BIT(16) #define AIROHA_PCS_PMA_PXP_AEQ_RSTB 0x814 #define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL BIT(16) #define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA 0x818 #define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB BIT(16) #define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0) #define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB 0x81c #define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16) #define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0) #define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN 0x820 #define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16) #define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0) #define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB 0x824 #define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB BIT(16) #define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0) #define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN 0x828 #define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN BIT(16) #define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0) #define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN_RSTB 0x83c #define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_CKON BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_CKON BIT(16) #define AIROHA_PCS_PMA_PXP_RX_OSCAL_EN 0x840 #define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_RSTB BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_RSTB BIT(16) #define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_EN BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_EN BIT(0) #define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B 0x84c #define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16) #define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B BIT(0) #define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN 0x854 #define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN BIT(16) #define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0) #define AIROHA_PCS_PMA_PXP_TXPLL_KBAND_LOAD_EN 0x858 #define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_KBAND_LOAD_EN BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_TXPLL_KBAND_LOAD_EN BIT(0) #define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW_CHG 0x864 #define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW_CHG BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW_CHG BIT(0) #define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN 0x874 #define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL BIT(16) #define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL 0x88c #define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0) #define AIROHA_PCS_PMA_PXP_RX_FE_PWDB 0x894 #define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24) #define AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN BIT(16) #define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB BIT(0) #define AIROHA_PCS_PMA_PXP_RX_SIGDET_CAL_EN 0x898 #define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_CAL_EN BIT(8) #define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_CAL_EN BIT(0) #define AIROHA_PCS_PMA_DIG_RESERVE_12 0x8b8 #define AIROHA_PCS_PMA_RESERVE_12_FEOS_0 BIT(0) #define AIROHA_PCS_PMA_DIG_RESERVE_24 0x8fc #define AIROHA_PCS_PMA_FORCE_RX_GEARBOX BIT(12) #define AIROHA_PCS_PMA_FORCE_SEL_RX_GEARBOX BIT(8) #define AIROHA_PCS_MAX_CALIBRATION_TRY 50 #define AIROHA_PCS_MAX_NUM_RSTS 2 enum pon_eo_buf_vals { EYE_EU, EYE_EB, DAC_D0, DAC_D1, DAC_E0, DAC_E1, DAC_EYE, FEOS, EO_BUF_MAX, }; enum xfi_port_type { AIROHA_PCS_ETH, AIROHA_PCS_PON, }; struct airoha_pcs_priv { struct udevice *dev; const struct airoha_pcs_match_data *data; phy_interface_t interface; struct regmap *scu; struct regmap *xfi_mac; struct regmap *hsgmii_an; struct regmap *hsgmii_pcs; struct regmap *hsgmii_rate_adp; struct regmap *multi_sgmii; struct regmap *usxgmii_pcs; struct regmap *xfi_pma; struct regmap *xfi_ana; struct reset_ctl *xfi_rst; struct reset_ctl_bulk rsts; bool manual_rx_calib; }; struct airoha_pcs_match_data { enum xfi_port_type port_type; bool hibernation_workaround; bool usxgmii_ber_time_fixup; bool usxgmii_rx_gb_out_vld_tweak; bool usxgmii_xfi_mode_sel; int (*bringup)(struct airoha_pcs_priv *priv, phy_interface_t interface); void (*link_up)(struct airoha_pcs_priv *priv); }; void airoha_pcs_pre_config(struct udevice *dev, phy_interface_t interface); int airoha_pcs_post_config(struct udevice *dev, phy_interface_t interface); int airoha_pcs_config(struct udevice *dev, bool neg_mode, phy_interface_t interface, const unsigned long *advertising, bool permit_pause_to_mac); void airoha_pcs_link_up(struct udevice *dev, unsigned int neg_mode, phy_interface_t interface, int speed, int duplex); void airoha_pcs_link_down(struct udevice *dev); #ifdef CONFIG_PCS_AIROHA_AN7581 int an7581_pcs_bringup(struct airoha_pcs_priv *priv, phy_interface_t interface); void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv); #else static inline int an7581_pcs_bringup(struct airoha_pcs_priv *priv, phy_interface_t interface) { return -EOPNOTSUPP; } static inline void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv) { } #endif