/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2025 NXP */ #ifndef __NXP_XSPI_H #define __NXP_XSPI_H /* XSPI Register defination */ #define XSPI_MCR 0x0 #define XSPI_MCR_CKN_FA_EN_MASK BIT(26) #define XSPI_MCR_CKN_FA_EN_SHIFT 26 #define XSPI_MCR_DQS_FA_SEL_MASK GENMASK(25, 24) #define XSPI_MCR_DQS_FA_SEL_SHIFT 24 #define XSPI_MCR_DQS_FA_SEL(x) ((x) << 24) #define XSPI_MCR_ISD3FA_MASK BIT(17) #define XSPI_MCR_ISD3FA_SHIFT 17 #define XSPI_MCR_ISD3FA_MASK BIT(17) #define XSPI_MCR_ISD3FA_SHIFT 17 #define XSPI_MCR_ISD2FA_MASK BIT(16) #define XSPI_MCR_ISD2FA_SHIFT 16 #define XSPI_MCR_DOZE_MASK BIT(15) #define XSPI_MCR_DOZE_SHIFT 15 #define XSPI_MCR_MDIS_MASK BIT(14) #define XSPI_MCR_MDIS_SHIFT 14 #define XSPI_MCR_DLPEN_MASK BIT(12) #define XSPI_MCR_DLPEN_SHIFT 12 #define XSPI_MCR_CLR_TXF_MASK BIT(11) #define XSPI_MCR_CLR_TXF_SHIFT 11 #define XSPI_MCR_CLR_RXF_MASK BIT(10) #define XSPI_MCR_CLR_RXF_SHIFT 10 #define XSPI_MCR_IPS_TG_RST_MASK BIT(9) #define XSPI_MCR_IPS_TG_RST_SHIFT 9 #define XSPI_MCR_VAR_LAT_EN_MASK BIT(8) #define XSPI_MCR_VAR_LAT_EN_SHIFT 8 #define XSPI_MCR_DDR_EN_MASK BIT(7) #define XSPI_MCR_DDR_EN_SHIFT 7 #define XSPI_MCR_DQS_EN_MASK BIT(6) #define XSPI_MCR_DQS_EN_SHIFT 6 #define XSPI_MCR_DQS_LAT_EN_MASK BIT(5) #define XSPI_MCR_DQS_LAT_EN_SHIFT 5 #define XSPI_MCR_DQS_OUT_EN_MASK BIT(4) #define XSPI_MCR_DQS_OUT_EN_SHIFT 4 #define XSPI_MCR_END_CFG_MASK GENMASK(3, 2) #define XSPI_MCR_END_CFG_SHIFT 2 #define XSPI_MCR_END_CFG(x) ((x) << 2) #define XSPI_MCR_SWRSTHD_MASK BIT(1) #define XSPI_MCR_SWRSTHD_SHIFT 1 #define XSPI_MCR_SWRSTSD_MASK BIT(0) #define XSPI_MCR_SWRSTSD_SHIFT 0 #define XSPI_IPCR 0x8U #define XSPI_IPCR_SEQID_MASK GENMASK(27, 24) #define XSPI_IPCR_SEQID_SHIFT 24 #define XSPI_IPCR_SEQID(x) ((x) << 24) #define XSPI_IPCR_IDATSZ_MASK GENMASK(14, 0) #define XSPI_IPCR_IDATSZ_SHIFT 0 #define XSPI_IPCR_IDATSZ(x) ((x) << 0) #define XSPI_FLSHCR 0xCU #define XSPI_FLSHCR_TDH_MASK GENMASK(17, 16) #define XSPI_FLSHCR_TDH_SHIFT 16 #define XSPI_FLSHCR_TDH(x) ((x) << 16) #define XSPI_FLSHCR_TCSH_MASK GENMASK(11, 8) #define XSPI_FLSHCR_TCSH_SHIFT 8 #define XSPI_FLSHCR_TCSH(x) ((x) << 8) #define XSPI_FLSHCR_TCSS_MASK GENMASK(3, 0) #define XSPI_FLSHCR_TCSS_SHIFT 0 #define XSPI_FLSHCR_TCSS(x) ((x) << 0) #define XSPI_BUF0CR 0x010U #define XSPI_BUF0CR_HP_EN_MASK BIT(31) #define XSPI_BUF0CR_HP_EN_SHIFT 31 #define XSPI_BUF0CR_SUB_DIV_EN_MASK BIT(30) #define XSPI_BUF0CR_SUB_DIV_EN_SHIFT 30 #define XSPI_BUF0CR_SUBBUF2_DIV_MASK GENMASK(29, 27) #define XSPI_BUF0CR_SUBBUF2_DIV_SHIFT 27 #define XSPI_BUF0CR_SUBBUF2_DIV(x) ((x) << 27) #define XSPI_BUF0CR_SUBBUF1_DIV_MASK GENMASK(26, 24) #define XSPI_BUF0CR_SUBBUF1_DIV_SHIFT 24 #define XSPI_BUF0CR_SUBBUF1_DIV(x) ((x) << 24) #define XSPI_BUF0CR_SUBBUF0_DIV_MASK GENMASK(23, 21) #define XSPI_BUF0CR_SUBBUF0_DIV_SHIFT 21 #define XSPI_BUF0CR_SUBBUF0_DIV(x) ((x) << 21) #define XSPI_BUF0CR_ADATSZ_MASK GENMASK(17, 8) #define XSPI_BUF0CR_ADATSZ_SHIFT 8 #define XSPI_BUF0CR_ADATSZ(x) ((x) << 8) #define XSPI_BUF0CR_MSTRID_MASK GENMASK(3, 0) #define XSPI_BUF0CR_MSTRID_SHIFT 0 #define XSPI_BUF0CR_MSTRID(x) ((x) << 0) #define XSPI_BUF1CR 0x014U #define XSPI_BUF2CR 0x018U #define XSPI_BUF3CR 0x1CU #define XSPI_BUF3CR_ALLMST_MASK BIT(31) #define XSPI_BUF3CR_ALLMST_SHIFT 31 #define XSPI_BUF3CR_SUB_DIV_EN_MASK BIT(30) #define XSPI_BUF3CR_SUB_DIV_EN_SHIFT 30 #define XSPI_BUF3CR_SUBBUF2_DIV_MASK GENMASK(29, 27) #define XSPI_BUF3CR_SUBBUF2_DIV_SHIFT 27 #define XSPI_BUF3CR_SUBBUF2_DIV(x) ((x) << 27) #define XSPI_BUF3CR_SUBBUF1_DIV_MASK GENMASK(26, 24) #define XSPI_BUF3CR_SUBBUF1_DIV_SHIFT 24 #define XSPI_BUF3CR_SUBBUF1_DIV(x) ((x) << 24) #define XSPI_BUF3CR_SUBBUF0_DIV_MASK GENMASK(23, 21) #define XSPI_BUF3CR_SUBBUF0_DIV_SHIFT 21 #define XSPI_BUF3CR_SUBBUF0_DIV(x) ((x) << 21) #define XSPI_BUF3CR_ADATSZ_MASK GENMASK(17, 8) #define XSPI_BUF3CR_ADATSZ_SHIFT 8 #define XSPI_BUF3CR_ADATSZ(x) ((x) << 8) #define XSPI_BUF3CR_MSTRID_MASK GENMASK(3, 0) #define XSPI_BUF3CR_MSTRID_SHIFT 0 #define XSPI_BUF3CR_MSTRID(x) ((x) << 0) #define XSPI_BUF0IND 0x030U #define XSPI_BUF0IND_TPINDX_MASK GENMASK(12, 3) #define XSPI_BUF0IND_TPINDX_SHIFT 3 #define XSPI_BUF0IND_TPINDX(x) ((x) << 3) #define XSPI_BUF1IND 0x034U #define XSPI_BUF2IND 0x038U #define XSPI_AWRCR 0x50 #define XSPI_AWRCR_PPW_WR_DIS_MASK BIT(15) #define XSPI_AWRCR_PPW_WR_DIS_SHIFT 15 #define XSPI_AWRCR_PPW_RD_DIS_MASK BIT(14) #define XSPI_AWRCR_PPW_RD_DIS_SHIFT 14 #define XSPI_DLLCRA 0x60U #define XSPI_DLLCRA_DLLEN_MASK BIT(31) #define XSPI_DLLCRA_DLLEN_SHIFT 31 #define XSPI_DLLCRA_FREQEN_MASK BIT(30) #define XSPI_DLLCRA_FREQEN_SHIFT 30 #define XSPI_DLLCRA_DLL_REFCNTR_MASK GENMASK(27, 24) #define XSPI_DLLCRA_DLL_REFCNTR_SHIFT 24 #define XSPI_DLLCRA_DLL_REFCNTR(x) ((x) << 24) #define XSPI_DLLCRA_DLLRES_MASK GENMASK(23, 20) #define XSPI_DLLCRA_DLLRES_SHIFT 20 #define XSPI_DLLCRA_DLLRES(x) ((x) << 20) #define XSPI_DLLCRA_SLV_FINE_OFFSET_MASK GENMASK(19, 16) #define XSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT 16 #define XSPI_DLLCRA_SLV_FINE_OFFSET(x) ((x) << 16) #define XSPI_DLLCRA_SLV_DLY_OFFSET_MASK GENMASK(14, 12) #define XSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT 12 #define XSPI_DLLCRA_SLV_DLY_OFFSET(x) ((x) << 12) #define XSPI_DLLCRA_SLV_DLY_COARSE_MASK GENMASK(11, 8) #define XSPI_DLLCRA_SLV_DLY_COARSE_SHIFT 8 #define XSPI_DLLCRA_SLV_DLY_COARSE(x) ((x) << 8) #define XSPI_DLLCRA_SLV_DLY_FINE_MASK GENMASK(7, 5) #define XSPI_DLLCRA_SLV_DLY_FINE_SHIFT 5 #define XSPI_DLLCRA_SLV_DLY_FINE(x) ((x) << 5) #define XSPI_DLLCRA_DLL_CDL8_MASK BIT(4) #define XSPI_DLLCRA_DLL_CDL8_SHIFT 4 #define XSPI_DLLCRA_SLAVE_AUTO_UPDT_MASK BIT(3) #define XSPI_DLLCRA_SLAVE_AUTO_UPDT_SHIFT 3 #define XSPI_DLLCRA_SLV_EN_MASK BIT(2) #define XSPI_DLLCRA_SLV_EN_SHIFT 2 #define XSPI_DLLCRA_SLV_DLL_BYPASS_MASK BIT(1) #define XSPI_DLLCRA_SLV_DLL_BYPASS_SHIFT 1 #define XSPI_DLLCRA_SLV_UPD_MASK BIT(0) #define XSPI_DLLCRA_SLV_UPD_SHIFT 0 #define XSPI_SFACR 0x104U #define XSPI_SFACR_FORCE_A10_MASK BIT(22) #define XSPI_SFACR_FORCE_A10_SHIFT 22 #define XSPI_SFACR_WA_4B_EN_MASK BIT(21) #define XSPI_SFACR_WA_4B_EN_SHIFT 21 #define XSPI_SFACR_CAS_INTRLVD_MASK BIT(20) #define XSPI_SFACR_CAS_INTRLVD_SHIFT 20 #define XSPI_SFACR_RX_BP_EN_MASK BIT(18) #define XSPI_SFACR_RX_BP_EN_SHIFT 18 #define XSPI_SFACR_BYTE_SWAP_MASK BIT(17) #define XSPI_SFACR_BYTE_SWAP_SHIFT 17 #define XSPI_SFACR_WA_MASK BIT(16) #define XSPI_SFACR_WA_SHIFT 16 #define XSPI_SFACR_PPWB_MASK GENMASK(12, 8) #define XSPI_SFACR_PPWB_SHIFT 8 #define XSPI_SFACR_PPWB(x) ((x) << 8) #define XSPI_SFACR_CAS_MASK GENMASK(3, 0) #define XSPI_SFACR_CAS_SHIFT 0 #define XSPI_SFACR_CAS(x) ((x) << 0) #define XSPI_SFAR 0x100U #define XSPI_SFAR_SFADR_MASK GENMASK(31, 0) #define XSPI_SFAR_SFADR_SHIFT 0 #define XSPI_SFAR_SFADR(x) ((x) << 0) #define XSPI_SMPR 0x108U #define XSPI_SMPR_DLLFSMPFA_MASK GENMASK(26, 24) #define XSPI_SMPR_DLLFSMPFA_SHIFT 24 #define XSPI_SMPR_DLLFSMPFA(x) ((x) << 24) #define XSPI_SMPR_FSDLY_MASK BIT(6) #define XSPI_SMPR_FSDLY_SHIFT 6 #define XSPI_SMPR_FSPHS_MASK BIT(5) #define XSPI_SMPR_FSPHS_SHIFT 5 #define XSPI_RBSR 0x10CU #define XSPI_RBSR_RDCTR_MASK GENMASK(31, 16) #define XSPI_RBSR_RDCTR_SHIFT 16 #define XSPI_RBSR_RDCTR(x) ((x) << 16) #define XSPI_RBSR_RDBFL_MASK GENMASK(8, 0) #define XSPI_RBSR_RDBFL_SHIFT 0 #define XSPI_RBSR_RDBFL(x) ((x) << 0) #define XSPI_RBCT 0x110U #define XSPI_RBCT_WMRK_MASK GENMASK(8, 0) #define XSPI_RBCT_WMRK_SHIFT 0 #define XSPI_RBCT_WMRK(x) ((x) << 0) #define XSPI_DLLSR 0x12CU #define XSPI_DLLSR_DLLA_LOCK_MASK BIT(15) #define XSPI_DLLSR_DLLA_LOCK_SHIFT 15 #define XSPI_DLLSR_SLVA_LOCK_MASK BIT(14) #define XSPI_DLLSR_SLVA_LOCK_SHIFT 14 #define XSPI_DLLSR_DLLA_RANGE_ERR_MASK BIT(13) #define XSPI_DLLSR_DLLA_RANGE_ERR_SHIFT 13 #define XSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK BIT(12) #define XSPI_DLLSR_DLLA_FINE_UNDERFLOW_SHIFT 12 #define XSPI_DLLSR_DLLA_SLV_FINE_VAL_MASK GENMASK(7, 4) #define XSPI_DLLSR_DLLA_SLV_FINE_VAL_SHIFT 4 #define XSPI_DLLSR_DLLA_SLV_FINE_VAL(x) ((x) << 4) #define XSPI_DLLSR_DLLA_SLV_COARSE_VAL_MASK GENMASK(3, 0) #define XSPI_DLLSR_DLLA_SLV_COARSE_VAL_SHIFT 0 #define XSPI_DLLSR_DLLA_SLV_COARSE_VAL(x) ((x) << 0) #define XSPI_DLCR 0x130U #define XSPI_DLCR_DL_NONDLP_FLSH_MASK BIT(24) #define XSPI_DLCR_DL_NONDLP_FLSH_SHIFT 24 #define XSPI_DLCR_DLP_SEL_FA_MASK GENMASK(15, 14) #define XSPI_DLCR_DLP_SEL_FA_SHIFT 14 #define XSPI_DLCR_DLP_SEL_FA(x) ((x) << 14) #define XSPI_TBSR 0x150U #define XSPI_TBSR_TRCTR_MASK GENMASK(31, 16) #define XSPI_TBSR_TRCTR_SHIFT 16 #define XSPI_TBSR_TRCTR(x) ((x) << 16) #define XSPI_TBSR_TRBFL_MASK GENMASK(8, 0) #define XSPI_TBSR_TRBFL_SHIFT 0 #define XSPI_TBSR_TRBFL(x) ((x) << 0) #define XSPI_TBDR 0x154U #define XSPI_TBDR_TXDATA_MASK GENMASK(31, 0) #define XSPI_TBDR_TXDATA_SHIFT 0 #define XSPI_TBDR_TXDATA(x) ((x) << 0) #define XSPI_TBCT 0x158U #define XSPI_TBCT_WMRK_MASK GENMASK(7, 0) #define XSPI_TBCT_WMRK_SHIFT 0 #define XSPI_TBCT_WMRK(x) ((x) << 0) #define XSPI_SR 0x15CU #define XSPI_SR_TXFULL_MASK BIT(27) #define XSPI_SR_TXFULL_SHIFT 27 #define XSPI_SR_TXDMA_MASK BIT(26) #define XSPI_SR_TXDMA_SHIFT 26 #define XSPI_SR_TXWA_MASK BIT(25) #define XSPI_SR_TXWA_SHIFT 25 #define XSPI_SR_TXNE_MASK BIT(24) #define XSPI_SR_TXNE_SHIFT 24 #define XSPI_SR_RXDMA_MASK BIT(23) #define XSPI_SR_RXDMA_SHIFT 23 #define XSPI_SR_ARB_STATE_MASK GENMASK(22, 20) #define XSPI_SR_ARB_STATE_SHIFT 20 #define XSPI_SR_ARB_STATE(x) ((x) << 20) #define XSPI_SR_RXFULL_MASK BIT(19) #define XSPI_SR_RXFULL_SHIFT 19 #define XSPI_SR_RXWE_MASK BIT(16) #define XSPI_SR_RXWE_SHIFT 16 #define XSPI_SR_ARB_LCK_MASK BIT(15) #define XSPI_SR_ARB_LCK_SHIFT 15 #define XSPI_SR_AHBnFUL_MASK GENMASK(14, 11) #define XSPI_SR_AHBnFUL_SHIFT 11 #define XSPI_SR_AHBnFUL(x) ((x) << 11) #define XSPI_SR_AHBnNE_MASK GENMASK(10, 7) #define XSPI_SR_AHBnNE_SHIFT 7 #define XSPI_SR_AHBnNE(x) ((x) << 7) #define XSPI_SR_AHBTRN_MASK BIT(6) #define XSPI_SR_AHBTRN_SHIFT 6 #define XSPI_SR_AWRACC_MASK BIT(4) #define XSPI_SR_AWRACC_SHIFT 4 #define XSPI_SR_AHB_ACC_MASK BIT(2) #define XSPI_SR_AHB_ACC_SHIFT 2 #define XSPI_SR_IP_ACC_MASK BIT(1) #define XSPI_SR_IP_ACC_SHIFT 1 #define XSPI_SR_BUSY_MASK BIT(0) #define XSPI_SR_BUSY_SHIFT 0 #define XSPI_FR 0x160U #define XSPI_FR_DLPFF_MASK BIT(31) #define XSPI_FR_DLPFF_SHIFT 31 #define XSPI_FR_DLLABRT_MASK BIT(28) #define XSPI_FR_DLLABRT_SHIFT 28 #define XSPI_FR_TBFF_MASK BIT(27) #define XSPI_FR_TBFF_SHIFT 27 #define XSPI_FR_TBUF_MASK BIT(26) #define XSPI_FR_TBUF_SHIFT 26 #define XSPI_FR_DLLUNLCK_MASK BIT(24) #define XSPI_FR_DLLUNLCK_SHIFT 24 #define XSPI_FR_ILLINE_MASK BIT(23) #define XSPI_FR_ILLINE_SHIFT 23 #define XSPI_FR_RBOF_MASK BIT(17) #define XSPI_FR_RBOF_SHIFT 17 #define XSPI_FR_RBDF_MASK BIT(16) #define XSPI_FR_RBDF_SHIFT 16 #define XSPI_FR_AAEF_MASK BIT(15) #define XSPI_FR_AAEF_SHIFT 15 #define XSPI_FR_AITEF_MASK BIT(14) #define XSPI_FR_AITEF_SHIFT 14 #define XSPI_FR_AIBSEF_MASK BIT(13) #define XSPI_FR_AIBSEF_SHIFT 13 #define XSPI_FR_ABOF_MASK BIT(12) #define XSPI_FR_ABOF_SHIFT 12 #define XSPI_FR_CRCAEF_MASK BIT(10) #define XSPI_FR_CRCAEF_SHIFT 10 #define XSPI_FR_PPWF_MASK BIT(8) #define XSPI_FR_PPWF_SHIFT 8 #define XSPI_FR_IPIEF_MASK BIT(6) #define XSPI_FR_IPIEF_SHIFT 6 #define XSPI_FR_IPEDERR_MASK BIT(5) #define XSPI_FR_IPEDERR_SHIFT 5 #define XSPI_FR_PERFOVF_MASK BIT(2) #define XSPI_FR_PERFOVF_SHIFT 2 #define XSPI_FR_RDADDR_MASK BIT(1) #define XSPI_FR_RDADDR_SHIFT 1 #define XSPI_FR_TFF_MASK BIT(0) #define XSPI_FR_TFF_SHIFT 0 #define XSPI_SFA1AD 0x180U #define XSPI_SFA1AD_TPAD_MASK GENMASK(31, 10) #define XSPI_SFA1AD_TPAD_SHIFT 10 #define XSPI_SFA1AD_TPAD(x) ((x) << 10) #define XSPI_SFA2AD 0x184U #define XSPI_DLPR 0x190U #define XSPI_DLPR_DLPV_MASK GENMASK(31, 0) #define XSPI_DLPR_DLPV_SHIFT 0 #define XSPI_DLPR_DLPV(x) ((x) << 0) #define XSPI_RBDR 0x200U #define XSPI_LUTKEY 0x300U #define XSPI_LCKCR 0x304U #define XSPI_LCKCR_UNLOCK_MASK BIT(1) #define XSPI_LCKCR_UNLOCK_SHIFT 1 #define XSPI_LCKCR_LOCK_MASK BIT(0) #define XSPI_LCKCR_LOCK_SHIFT 0 #define XSPI_LUT 0x310 #define XSPI_BFGENCR 0x20 #define XSPI_BFGENCR_SEQID_WR_MASK GENMASK(31, 28) #define XSPI_BFGENCR_SEQID_WR_SHIFT 28 #define XSPI_BFGENCR_SEQID_WR(x) ((x) << 28) #define XSPI_BFGENCR_ALIGN_MASK GENMASK(23, 22) #define XSPI_BFGENCR_ALIGN_SHIFT 22 #define XSPI_BFGENCR_ALIGN(x) ((x) << 22) #define XSPI_BFGENCR_WR_FLUSH_EN_MASK BIT(21) #define XSPI_BFGENCR_WR_FLUSH_EN_SHIFT 21 #define XSPI_BFGENCR_PPWF_CLR_MASK BIT(20) #define XSPI_BFGENCR_PPWF_CLR_SHIFT 20 #define XSPI_BFGENCR_SEQID_WR_EN_MASK BIT(17) #define XSPI_BFGENCR_SEQID_WR_EN_SHIFT 17 #define XSPI_BFGENCR_SEQID_MASK GENMASK(15, 12) #define XSPI_BFGENCR_SEQID_SHIFT 12 #define XSPI_BFGENCR_SEQID(x) ((x) << 12) #define XSPI_BFGENCR_AHBSSIZE_MASK GENMASK(10, 9) #define XSPI_BFGENCR_AHBSSIZE_SHIFT 9 #define XSPI_BFGENCR_AHBSSIZE(x) ((x) << 9) #define XSPI_BFGENCR_SPLITEN_MASK BIT(8) #define XSPI_BFGENCR_SPLITEN_SHIFT 8 #define XSPI_BFGENCR_SEQID_RDSR_MASK GENMASK(3, 0) #define XSPI_BFGENCR_SEQID_RDSR_SHIFT 0 #define XSPI_BFGENCR_SEQID_RDSR(x) ((x) << 0) #define XSPI_FRAD0_WORD2 0x808U #define XSPI_FRAD0_WORD2_EALO_MASK GENMASK(29, 24) #define XSPI_FRAD0_WORD2_EALO_SHIFT 24 #define XSPI_FRAD0_WORD2_EALO(x) ((x) << 24) #define XSPI_FRAD0_WORD2_MD4ACP_MASK GENMASK(14, 12) #define XSPI_FRAD0_WORD2_MD4ACP_SHIFT 12 #define XSPI_FRAD0_WORD2_MD4ACP(x) ((x) << 12) #define XSPI_FRAD0_WORD2_MD3ACP_MASK GENMASK(11, 9) #define XSPI_FRAD0_WORD2_MD3ACP_SHIFT 9 #define XSPI_FRAD0_WORD2_MD3ACP(x) ((x) << 9) #define XSPI_FRAD0_WORD2_MD2ACP_MASK GENMASK(8, 6) #define XSPI_FRAD0_WORD2_MD2ACP_SHIFT 6 #define XSPI_FRAD0_WORD2_MD2ACP(x) ((x) << 6) #define XSPI_FRAD0_WORD2_MD1ACP_MASK GENMASK(5, 3) #define XSPI_FRAD0_WORD2_MD1ACP_SHIFT 3 #define XSPI_FRAD0_WORD2_MD1ACP(x) ((x) << 3) #define XSPI_FRAD0_WORD2_MD0ACP_MASK GENMASK(2, 0) #define XSPI_FRAD0_WORD2_MD0ACP_SHIFT 0 #define XSPI_FRAD0_WORD2_MD0ACP(x) ((x) << 0) #define XSPI_FRAD1_WORD2 0x828U #define XSPI_FRAD2_WORD2 0x848U #define XSPI_FRAD3_WORD2 0x868U #define XSPI_FRAD4_WORD2 0x888U #define XSPI_FRAD5_WORD2 0x8A8U #define XSPI_FRAD6_WORD2 0x8C8U #define XSPI_FRAD7_WORD2 0x8E8U #define XSPI_FRAD8_WORD2 0x988U #define XSPI_FRAD9_WORD2 0x9A8U #define XSPI_FRAD10_WORD2 0x9C8U #define XSPI_FRAD11_WORD2 0x9E8U #define XSPI_FRAD12_WORD2 0xA08U #define XSPI_FRAD13_WORD2 0xA28U #define XSPI_FRAD14_WORD2 0xA48U #define XSPI_FRAD15_WORD2 0xA68U #define XSPI_FRAD0_WORD3 0x80CU #define XSPI_FRAD0_WORD3_VLD_MASK BIT(31) #define XSPI_FRAD0_WORD3_VLD_SHIFT 31 #define XSPI_FRAD0_WORD3_LOCK_MASK GENMASK(30, 29) #define XSPI_FRAD0_WORD3_LOCK_SHIFT 29 #define XSPI_FRAD0_WORD3_LOCK(x) ((x) << 29) #define XSPI_FRAD0_WORD3_EAL_MASK GENMASK(25, 24) #define XSPI_FRAD0_WORD3_EAL_SHIFT 24 #define XSPI_FRAD0_WORD3_EAL(x) ((x) << 24) #define XSPI_FRAD1_WORD3 0x82CU #define XSPI_FRAD2_WORD3 0x84CU #define XSPI_FRAD3_WORD3 0x86CU #define XSPI_FRAD4_WORD3 0x88CU #define XSPI_FRAD5_WORD3 0x8ACU #define XSPI_FRAD6_WORD3 0x8CCU #define XSPI_FRAD7_WORD3 0x8ECU #define XSPI_FRAD8_WORD3 0x98CU #define XSPI_FRAD9_WORD3 0x9ACU #define XSPI_FRAD10_WORD3 0x9CCU #define XSPI_FRAD11_WORD3 0x9ECU #define XSPI_FRAD12_WORD3 0xA0CU #define XSPI_FRAD13_WORD3 0xA2CU #define XSPI_FRAD14_WORD3 0xA4CU #define XSPI_FRAD15_WORD3 0xA6CU #define XSPI_TG0MDAD 0x900U #define XSPI_TG0MDAD_VLD_MASK BIT(31) #define XSPI_TG0MDAD_VLD_SHIFT 31 #define XSPI_TG0MDAD_LCK_MASK BIT(29) #define XSPI_TG0MDAD_LCK_SHIFT 29 #define XSPI_TG0MDAD_SA_MASK GENMASK(15, 14) #define XSPI_TG0MDAD_SA_SHIFT 14 #define XSPI_TG0MDAD_SA(x) ((x) << 14) #define XSPI_TG0MDAD_MASKTYPE_MASK BIT(12) #define XSPI_TG0MDAD_MASKTYPE_SHIFT 12 #define XSPI_TG0MDAD_MASK_MASK GENMASK(11, 6) #define XSPI_TG0MDAD_MASK_SHIFT 6 #define XSPI_TG0MDAD_MASK(x) ((x) << 6) #define XSPI_TG0MDAD_MIDMATCH_MASK GENMASK(5, 0) #define XSPI_TG0MDAD_MIDMATCH_SHIFT 0 #define XSPI_TG0MDAD_MIDMATCH(x) ((x) << 0) #define XSPI_TG1MDAD 0x910U #define XSPI_MGC 0x920 #define XSPI_MGC_GVLD_MASK BIT(31) #define XSPI_MGC_GVLD_SHIFT 31 #define XSPI_MGC_GVLDMDAD_MASK BIT(29) #define XSPI_MGC_GVLDMDAD_SHIFT 29 #define XSPI_MGC_GVLDFRAD_MASK BIT(27) #define XSPI_MGC_GVLDFRAD_SHIFT 27 #define XSPI_MGC_TG1_FIX_PRIO_MASK BIT(16) #define XSPI_MGC_TG1_FIX_PRIO_SHIFT 16 #define XSPI_MGC_GCLCK_MASK GENMASK(11, 10) #define XSPI_MGC_GCLCK_SHIFT 10 #define XSPI_MGC_GCLCK(x) ((x) << 10) #define XSPI_MGC_GCLCKMID_MASK GENMASK(5, 0) #define XSPI_MGC_GCLCKMID_SHIFT 0 #define XSPI_MGC_GCLCKMID(x) ((x) << 0) #define XSPI_MTO 0x928 #define XSPI_MTO_SFP_ACC_TO_MASK GENMASK(31, 0) #define XSPI_MTO_SFP_ACC_TO_SHIFT 0 #define XSPI_MTO_SFP_ACC_TO(x) ((x) << 0) #define XSPI_TG2MDAD_EXT 0x940U #define XSPI_TG2MDAD_EXT_VLD_MASK BIT(31) #define XSPI_TG2MDAD_EXT_VLD_SHIFT 31 #define XSPI_TG2MDAD_EXT_LCK_MASK BIT(29) #define XSPI_TG2MDAD_EXT_LCK_SHIFT 29 #define XSPI_TG2MDAD_EXT_SA_MASK GENMASK(15, 14) #define XSPI_TG2MDAD_EXT_SA_SHIFT 14 #define XSPI_TG2MDAD_EXT_SA(x) ((x) << 14) #define XSPI_TG2MDAD_EXT_MASKTYPE_MASK BIT(12) #define XSPI_TG2MDAD_EXT_MASKTYPE_SHIFT 12 #define XSPI_TG2MDAD_EXT_MASK_MASK GENMASK(11, 6) #define XSPI_TG2MDAD_EXT_MASK_SHIFT 6 #define XSPI_TG2MDAD_EXT_MASK(x) ((x) << 6) #define XSPI_TG2MDAD_EXT_MIDMATCH_MASK GENMASK(5, 0) #define XSPI_TG2MDAD_EXT_MIDMATCH_SHIFT 0 #define XSPI_TG2MDAD_EXT_MIDMATCH(x) ((x) << 0) #define XSPI_TG3MDAD_EXT 0x944U #define XSPI_TG4MDAD_EXT 0x948U #define XSPI_SFP_TG_IPCR 0x958U #define XSPI_SFP_TG_IPCR_SEQID_MASK GENMASK(27, 24) #define XSPI_SFP_TG_IPCR_SEQID_SHIFT 24 #define XSPI_SFP_TG_IPCR_SEQID(x) ((x) << 24) #define XSPI_SFP_TG_IPCR_ARB_UNLOCK_MASK BIT(23) #define XSPI_SFP_TG_IPCR_ARB_UNLOCK_SHIFT 23 #define XSPI_SFP_TG_IPCR_ARB_LOCK_MASK BIT(22) #define XSPI_SFP_TG_IPCR_ARB_LOCK_SHIFT 22 #define XSPI_SFP_TG_IPCR_IDATSZ_MASK GENMASK(15, 0) #define XSPI_SFP_TG_IPCR_IDATSZ_SHIFT 0 #define XSPI_SFP_TG_IPCR_IDATSZ(x) ((x) << 0) #define XSPI_SFP_TG_SFAR 0x95CU /* XSPI Register defination end */ /* xspi data structure */ struct nxp_xspi_devtype_data { unsigned int rxfifo; unsigned int rx_buf_size; unsigned int txfifo; unsigned int ahb_buf_size; unsigned int quirks; }; struct nxp_xspi { struct udevice *dev; u32 iobase; u32 ahb_addr; u32 a1_size; u32 a2_size; struct { bool gmid; u8 env; } config; struct clk clk; struct nxp_xspi_devtype_data *devtype_data; unsigned long support_max_rate; int selected; bool dtr; }; /* xspi data structure end */ /********* XSPI CMD definitions ***************************/ #define CMD_SDR 0x01U #define CMD_DDR 0x11U #define RADDR_SDR 0x02U #define RADDR_DDR 0x0AU #define CADDR_SDR 0x12U #define CADDR_DDR 0x13U #define MODE2_SDR 0x05U #define MODE2_DDR 0x0CU #define MODE4_SDR 0x06U #define MODE4_DDR 0x0DU #define MODE8_SDR 0x04U #define MODE8_DDR 0x0BU #define WRITE_SDR 0x08U #define WRITE_DDR 0x0FU #define READ_SDR 0x07U #define READ_DDR 0x0EU #define DATA_LEARN 0x10U #define DUMMY_CYCLE 0x03U #define JMP_ON_CS 0x09U #define JMP_TO_SEQ 0x14U #define CMD_STOP 0U /********* XSPI PAD definitions ************/ #define XSPI_1PAD 0U #define XSPI_2PAD 1U #define XSPI_4PAD 2U #define XSPI_8PAD 3U #define DEFAULT_XMIT_SIZE 0x40U #define ENV_ADDR_SIZE SZ_64K #define XSPI_LUT_KEY_VAL 0x5AF05AF0UL #define xspi_get_reg_field(x, env, reg_name, field_name) \ ({ \ u32 reg; \ reg = xspi_readl_offset(x, env, reg_name); \ reg &= XSPI_##reg_name##_##field_name##_MASK; \ reg = reg >> XSPI_##reg_name##_##field_name##_SHIFT; \ reg; \ }) #define xspi_set_reg_field(x, env, val, reg_name, field_name) \ do { \ u32 reg; \ reg = xspi_readl_offset(x, env, reg_name); \ reg &= ~XSPI_##reg_name##_##field_name##_MASK; \ reg |= (val << XSPI_##reg_name##_##field_name##_SHIFT); \ xspi_writel_offset(x, env, reg, reg_name); \ } while (0) #define xspi_writel_offset(x, env, val, offset) \ do { \ out_le32((void __iomem *)(uintptr_t)x->iobase + \ (env * ENV_ADDR_SIZE) + XSPI_##offset, val); \ } while (0) #define xspi_readl_offset(x, env, offset) ({ \ u32 reg; \ reg = in_le32((void __iomem *)(uintptr_t)x->iobase + \ (env * ENV_ADDR_SIZE) + XSPI_##offset); \ reg; \ }) #define POLL_TOUT 5000 #define CMD_LUT_FOR_IP_CMD 1 #define CMD_LUT_FOR_AHB_CMD 0 /* * Calculate number of required PAD bits for LUT register. * * The pad stands for the number of IO lines [0:7]. * For example, the octal read needs eight IO lines, * so you should use LUT_PAD(8). This macro * returns 3 i.e. use eight (2^3) IP lines for read. */ #define LUT_PAD(x) (fls(x) - 1) /* * Macro for constructing the LUT entries with the following * register layout: * * --------------------------------------------------- * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | * --------------------------------------------------- */ #define PAD_SHIFT 8 #define INSTR_SHIFT 10 #define OPRND_SHIFT 16 /* Macros for constructing the LUT register. */ #define LUT_DEF(idx, ins, pad, opr) \ ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \ (opr)) << (((idx) % 2) * OPRND_SHIFT)) #endif