// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2026 Rockchip Electronics Co., Ltd.
 */

#include <dt-bindings/clock/rockchip,rv1103b-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	compatible = "rockchip,rv1103b";

	interrupt-parent = <&gic>;

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			clocks = <&cru ARMCLK>;
			device_type = "cpu";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		clock-frequency = <24000000>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	xin24m: oscillator-24m {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
		#clock-cells = <0>;
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rv1103b-pinctrl";
		rockchip,grf = <&ioc>;
		ranges;
		#address-cells = <1>;
		#size-cells = <1>;

		gpio0: gpio@20520000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20520000 0x200>;
			clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>;
			gpio-controller;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@20d80000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20d80000 0x200>;
			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
			gpio-controller;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@20840000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20840000 0x200>;
			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
			gpio-controller;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		cru: clock-controller@20000000 {
			compatible = "rockchip,rv1103b-cru";
			reg = <0x20000000 0x81000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pmu_grf: syscon@20160000 {
			compatible = "rockchip,rv1103b-pmu-grf", "syscon", "simple-mfd";
			reg = <0x20160000 0x1000>;

			reboot_mode: reboot-mode {
				compatible = "syscon-reboot-mode";
				offset = <0x200>;
				mode-normal = <BOOT_NORMAL>;
				mode-recovery = <BOOT_RECOVERY>;
				mode-bootloader = <BOOT_FASTBOOT>;
				mode-loader = <BOOT_BL_DOWNLOAD>;
			};
		};

		ioc: syscon@20170000 {
			compatible = "rockchip,rv1103b-ioc", "syscon";
			reg = <0x20170000 0x60000>;
		};

		gic: interrupt-controller@20411000 {
			compatible = "arm,gic-400";
			reg = <0x20411000 0x1000>,
			      <0x20412000 0x2000>,
			      <0x20414000 0x2000>,
			      <0x20416000 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
			interrupt-controller;
			#interrupt-cells = <3>;
			#address-cells = <0>;
		};

		uart0: serial@20540000 {
			compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart";
			reg = <0x20540000 0x100>;
			clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&uart0m0_xfer>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		sdmmc1: mmc@20650000 {
			compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc";
			reg = <0x20650000 0x4000>;
			clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x100>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			max-frequency = <150000000>;
			pinctrl-names = "default";
			pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
			status = "disabled";
		};

		uart1: serial@20870000 {
			compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart";
			reg = <0x20870000 0x100>;
			clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&uart1m0_xfer>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart2: serial@20880000 {
			compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart";
			reg = <0x20880000 0x100>;
			clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&uart2m0_xfer>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		sdmmc0: mmc@20d20000 {
			compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc";
			reg = <0x20d20000 0x4000>;
			clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x100>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			max-frequency = <150000000>;
			pinctrl-names = "default";
			pinctrl-0 = <&sdmmc0_det &sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4>;
			status = "disabled";
		};

		emmc: mmc@20d30000 {
			compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc";
			reg = <0x20d30000 0x4000>;
			clocks = <&cru HCLK_EMMC>, <&cru CCLK_EMMC>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x100>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
			max-frequency = <150000000>;
			pinctrl-names = "default";
			pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>;
			status = "disabled";
		};

		fspi0: spi@20d40000 {
			compatible = "rockchip,sfc";
			reg = <0x20d40000 0x4000>;
			clocks = <&cru SCLK_SFC_2X>, <&cru HCLK_SFC>;
			clock-names = "clk_sfc", "hclk_sfc";
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&fspi_bus4 &fspi_cs0 &fspi_clk>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		system_sram: sram@210f6000 {
			compatible = "mmio-sram";
			reg = <0x210f6000 0x8000>;
			ranges = <0 0x210f6000 0x8000>;
			#address-cells = <1>;
			#size-cells = <1>;
		};
	};
};

#include "rv1103b-pinctrl.dtsi"