// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright Altera Corporation (C) 2026. All rights reserved.
 */

#include "socfpga_stratix10_socdk.dtsi"

/ {
	model = "SoCFPGA Stratix 10 SoCDK eMMC daughter board";
	compatible = "altr,socfpga-stratix10-socdk-emmc",
			"altr,socfpga-stratix10-socdk",
			"altr,socfpga-stratix10";
};

&gmac2 {
	status = "okay";
	/* PHY delays is configured via skew properties */
	phy-mode = "rgmii";
	phy-handle = <&phy0>;

	max-frame-size = <9000>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@4 {
			reg = <4>;

			txd0-skew-ps = <0>; /* -420ps */
			txd1-skew-ps = <0>; /* -420ps */
			txd2-skew-ps = <0>; /* -420ps */
			txd3-skew-ps = <0>; /* -420ps */
			rxd0-skew-ps = <420>; /* 0ps */
			rxd1-skew-ps = <420>; /* 0ps */
			rxd2-skew-ps = <420>; /* 0ps */
			rxd3-skew-ps = <420>; /* 0ps */
			txen-skew-ps = <0>; /* -420ps */
			txc-skew-ps = <900>; /* 0ps */
			rxdv-skew-ps = <420>; /* 0ps */
			rxc-skew-ps = <1680>; /* 780ps */
		};
	};
};

&mmc {
	status = "okay";
	cap-mmc-highspeed;
	broken-cd;
	bus-width = <4>;
	clk-phase-sd-hs = <0>, <135>;
};

&i2c2 {
	status = "okay";
	clock-frequency = <100000>;
	i2c-sda-falling-time-ns = <890>;  /* hcnt */
	i2c-scl-falling-time-ns = <890>;  /* lcnt */

	adc@14 {
		compatible = "lltc,ltc2497";
		reg = <0x14>;
		vref-supply = <&ref_033v>;
	};

	temp@4c {
		compatible = "maxim,max1619";
		reg = <0x4c>;
	};

	eeprom@51 {
		compatible = "atmel,24c32";
		reg = <0x51>;
		pagesize = <32>;
	};

	rtc@68 {
		compatible = "dallas,ds1339";
		reg = <0x68>;
	};
};