/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/*
 * Copyright 2025 NXP
 */

#ifndef __CLOCK_IMX952_H__
#define __CLOCK_IMX952_H__

/* Clock Source */
#define IMX952_CLK_EXT			0
#define IMX952_CLK_OSC32K		1
#define IMX952_CLK_OSC24M		2
#define IMX952_CLK_FRO			3
#define IMX952_CLK_SYSPLL1_VCO		4
#define IMX952_CLK_SYSPLL1_PFD0_UNGATED	5
#define IMX952_CLK_SYSPLL1_PFD0		6
#define IMX952_CLK_SYSPLL1_PFD0_DIV2	7
#define IMX952_CLK_SYSPLL1_PFD1_UNGATED	8
#define IMX952_CLK_SYSPLL1_PFD1		9
#define IMX952_CLK_SYSPLL1_PFD1_DIV2	10
#define IMX952_CLK_SYSPLL1_PFD2_UNGATED	11
#define IMX952_CLK_SYSPLL1_PFD2		12
#define IMX952_CLK_SYSPLL1_PFD2_DIV2	13
#define IMX952_CLK_AUDIOPLL1_VCO	14
#define IMX952_CLK_AUDIOPLL1		15
#define IMX952_CLK_AUDIOPLL2_VCO	16
#define IMX952_CLK_AUDIOPLL2		17
#define IMX952_CLK_VIDEOPLL1_VCO	18
#define IMX952_CLK_VIDEOPLL1		19
#define IMX952_CLK_SRC_RESERVED20	20
#define IMX952_CLK_SYSPLL1_PFD3_UNGATED	21
#define IMX952_CLK_SYSPLL1_PFD3		22
#define IMX952_CLK_SYSPLL1_PFD3_DIV2	23
#define IMX952_CLK_ARMPLL_VCO		24
#define IMX952_CLK_ARMPLL_PFD0_UNGATED	25
#define IMX952_CLK_ARMPLL_PFD0		26
#define IMX952_CLK_ARMPLL_PFD1_UNGATED	27
#define IMX952_CLK_ARMPLL_PFD1		28
#define IMX952_CLK_ARMPLL_PFD2_UNGATED	29
#define IMX952_CLK_ARMPLL_PFD2		30
#define IMX952_CLK_ARMPLL_PFD3_UNGATED	31
#define IMX952_CLK_ARMPLL_PFD3		32
#define IMX952_CLK_DRAMPLL_VCO		33
#define IMX952_CLK_DRAMPLL		34
#define IMX952_CLK_HSIOPLL_VCO		35
#define IMX952_CLK_HSIOPLL		36
#define IMX952_CLK_LDBPLL_VCO		37
#define IMX952_CLK_LDBPLL		38
#define IMX952_CLK_EXT1			39
#define IMX952_CLK_EXT2			40

/* Clock ROOT */
#define IMX952_CLK_ADC			41
#define IMX952_CLK_RESERVED1		42
#define IMX952_CLK_BUSAON		43
#define IMX952_CLK_CAN1			44
#define IMX952_CLK_RESERVED4		45
#define IMX952_CLK_I3C1SLOW		46
#define IMX952_CLK_LPI2C1		47
#define IMX952_CLK_LPI2C2		48
#define IMX952_CLK_LPSPI1		49
#define IMX952_CLK_LPSPI2		50
#define IMX952_CLK_LPTMR1		51
#define IMX952_CLK_LPUART1		52
#define IMX952_CLK_LPUART2		53
#define IMX952_CLK_M33			54
#define IMX952_CLK_M33SYSTICK		55
#define IMX952_CLK_RESERVED15		56
#define IMX952_CLK_PDM			57
#define IMX952_CLK_SAI1			58
#define IMX952_CLK_RESERVED18		59
#define IMX952_CLK_TPM2			60
#define IMX952_CLK_RESERVED20		61
#define IMX952_CLK_CAMAPB		62
#define IMX952_CLK_CAMAXI		63
#define IMX952_CLK_CAMCM0		64
#define IMX952_CLK_CAMISI		65
#define IMX952_CLK_CAMPHYCFG		66
#define IMX952_CLK_MIPIPHYPLLBYPASS	67
#define IMX952_CLK_RESERVED27		68
#define IMX952_CLK_MIPITESTBYTE		69
#define IMX952_CLK_A55			70
#define IMX952_CLK_A55MTRBUS		71
#define IMX952_CLK_A55PERIPH		72
#define IMX952_CLK_DRAMALT		73
#define IMX952_CLK_DRAMAPB		74
#define IMX952_CLK_DISPAPB		75
#define IMX952_CLK_DISPAXI		76
#define IMX952_CLK_DISPLPSPI		77
#define IMX952_CLK_DISPOCRAM		78
#define IMX952_CLK_DISPPHYCFG		79
#define IMX952_CLK_DISP1PIX		80
#define IMX952_CLK_DISPCDPHYAPB		81
#define IMX952_CLK_RESERVED41		82
#define IMX952_CLK_GPUAPB		83
#define IMX952_CLK_GPU			84
#define IMX952_CLK_HSIOACSCAN480M	85
#define IMX952_CLK_HSIOACSCAN80M	86
#define IMX952_CLK_HSIO			87
#define IMX952_CLK_HSIOPCIEAUX		88
#define IMX952_CLK_HSIOPCIETEST160M	89
#define IMX952_CLK_HSIOPCIETEST400M	90
#define IMX952_CLK_HSIOPCIETEST500M	91
#define IMX952_CLK_HSIOUSBTEST50M	92
#define IMX952_CLK_HSIOUSBTEST60M	93
#define IMX952_CLK_BUSM7		94
#define IMX952_CLK_M7			95
#define IMX952_CLK_M7SYSTICK		96
#define IMX952_CLK_BUSNETCMIX		97
#define IMX952_CLK_ENET			98
#define IMX952_CLK_ENETPHYTEST200M	99
#define IMX952_CLK_ENETPHYTEST500M	100
#define IMX952_CLK_ENETPHYTEST667M	101
#define IMX952_CLK_ENETREF		102
#define IMX952_CLK_ENETTIMER1		103
#define IMX952_CLK_RESERVED63		104
#define IMX952_CLK_SAI2			105
#define IMX952_CLK_NOCAPB		106
#define IMX952_CLK_NOC			107
#define IMX952_CLK_NPUAPB		108
#define IMX952_CLK_NPU			109
#define IMX952_CLK_CCMCKO1		110
#define IMX952_CLK_CCMCKO2		111
#define IMX952_CLK_CCMCKO3		112
#define IMX952_CLK_CCMCKO4		113
#define IMX952_CLK_VPUAPB		114
#define IMX952_CLK_VPU			115
#define IMX952_CLK_RESERVED75		116
#define IMX952_CLK_RESERVED76		117
#define IMX952_CLK_AUDIOXCVR		118
#define IMX952_CLK_BUSWAKEUP		119
#define IMX952_CLK_CAN2			120
#define IMX952_CLK_CAN3			121
#define IMX952_CLK_CAN4			122
#define IMX952_CLK_CAN5			123
#define IMX952_CLK_FLEXIO1		124
#define IMX952_CLK_FLEXIO2		125
#define IMX952_CLK_XSPI1		126
#define IMX952_CLK_RESERVED86		127
#define IMX952_CLK_I3C2SLOW		128
#define IMX952_CLK_LPI2C3		129
#define IMX952_CLK_LPI2C4		130
#define IMX952_CLK_LPI2C5		131
#define IMX952_CLK_LPI2C6		132
#define IMX952_CLK_LPI2C7		133
#define IMX952_CLK_LPI2C8		134
#define IMX952_CLK_LPSPI3		135
#define IMX952_CLK_LPSPI4		136
#define IMX952_CLK_LPSPI5		137
#define IMX952_CLK_LPSPI6		138
#define IMX952_CLK_LPSPI7		139
#define IMX952_CLK_LPSPI8		140
#define IMX952_CLK_LPTMR2		141
#define IMX952_CLK_LPUART3		142
#define IMX952_CLK_LPUART4		143
#define IMX952_CLK_LPUART5		144
#define IMX952_CLK_LPUART6		145
#define IMX952_CLK_LPUART7		146
#define IMX952_CLK_LPUART8		147
#define IMX952_CLK_SAI3			148
#define IMX952_CLK_SAI4			149
#define IMX952_CLK_SAI5			150
#define IMX952_CLK_SPDIF		151
#define IMX952_CLK_SWOTRACE		152
#define IMX952_CLK_TPM4			153
#define IMX952_CLK_TPM5			154
#define IMX952_CLK_TPM6			155
#define IMX952_CLK_MIPIPHYDFT400	156
#define IMX952_CLK_MIPIPHYDFT540	157
#define IMX952_CLK_USDHC1		158
#define IMX952_CLK_USDHC2		159
#define IMX952_CLK_USDHC3		160
#define IMX952_CLK_V2XPK		161
#define IMX952_CLK_WAKEUPAXI		162
#define IMX952_CLK_XSPISLVROOT		163
#define IMX952_CLK_AUDMIX1		164
#define IMX952_CLK_ASRC1		165
#define IMX952_CLK_ASRC2		166
#define IMX952_CLK_GPT1			167
#define IMX952_CLK_GPT2			168
#define IMX952_CLK_GPT3			169
#define IMX952_CLK_GPT4			170

/* Clock GPR SEL */
#define IMX952_CLK_GPR_SEL_EXT		171
#define IMX952_CLK_GPR_SEL_A55C0	172
#define IMX952_CLK_GPR_SEL_A55C1	173
#define IMX952_CLK_GPR_SEL_A55C2	174
#define IMX952_CLK_GPR_SEL_A55C3	175
#define IMX952_CLK_GPR_SEL_A55P		176
#define IMX952_CLK_GPR_SEL_DRAM		177
#define IMX952_CLK_GPR_SEL_TEMPSENSE	178

/* Clock CGC */
#define IMX952_CLK_CGC_NPU		179
#define IMX952_CLK_CGC_GPU		180
#define IMX952_CLK_CGC_CAMISI		181
#define IMX952_CLK_CGC_CAMISP		182
#define IMX952_CLK_CGC_CAMCSI0		183
#define IMX952_CLK_CGC_CAMCSI1		184
#define IMX952_CLK_CGC_CAMOCRAM		185
#define IMX952_CLK_CGC_HSIOUSB		186
#define IMX952_CLK_CGC_HSIOPCIE		187
#define IMX952_CLK_CGC_DISPOCRAM	188
#define IMX952_CLK_CGC_DISPSEERIS	189
#define IMX952_CLK_CGC_DISPDSI		190
#define IMX952_CLK_CGC_NOCGIC		191
#define IMX952_CLK_CGC_NOCOCRAM		192
#define IMX952_CLK_CGC_NETC		193
#define IMX952_CLK_CGC_VPUENC		194
#define IMX952_CLK_CGC_VPUJPEGENC	195
#define IMX952_CLK_CGC_VPUJPEGDEC	196
#define IMX952_CLK_CGC_VPUDEC		197

#endif