// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * NXP S32N79 SoC
 *
 * Copyright 2026 NXP
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cis-bus {
		compatible = "simple-bus";
		ranges = <0x4f200000 0x0 0x4f200000 0xc00000>;
		#address-cells = <1>;
		#size-cells = <1>;

		gic: interrupt-controller@4f200000 {
			compatible = "arm,gic-v3";
			reg = <0x4f200000 0x10000>, /* GIC Dist */
			      <0x4f260000 0x100000>;
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <1>;
			/* GICR (RD_base + SGI_base) */
			ranges;

			its: msi-controller@4f240000 {
				compatible = "arm,gic-v3-its";
				reg = <0x4f240000 0x20000>;
				#msi-cells = <1>;
				msi-controller;
			};
		};

		smmu: iommu@4fc00000 {
			compatible = "arm,smmu-v3";
			reg = <0x4fc00000 0x200000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
			#iommu-cells = <1>;
			dma-coherent;
			status = "disabled";
		};
	};

	coss-bus {
		compatible = "simple-bus";
		ranges = <0x4a000000 0x0 0x4a000000 0xff0000>,
			 <0x4e000000 0x0 0x4e000000 0x1000000>;
		#address-cells = <1>;
		#size-cells = <1>;

		uart0: serial@4a030000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x4a030000 0x1000>;
			interrupt-parent = <&irqsteer_coss>;
			interrupts = <264>;
			clocks = <&clks 0x9a>, <&clks 0x9a>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		uart5: serial@4a060000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x4a060000 0x1000>;
			interrupt-parent = <&irqsteer_coss>;
			interrupts = <269>;
			clocks = <&clks 0x9a>, <&clks 0x9a>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		uart6: serial@4aa30000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x4aa30000 0x1000>;
			interrupt-parent = <&irqsteer_coss>;
			interrupts = <270>;
			clocks = <&clks 0x9a>, <&clks 0x9a>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		uart7: serial@4aa40000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x4aa40000 0x1000>;
			interrupt-parent = <&irqsteer_coss>;
			interrupts = <271>;
			clocks = <&clks 0x9a>, <&clks 0x9a>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		irqsteer_coss: interrupt-controller@4ed00000 {
			compatible = "nxp,s32n79-irqsteer";
			reg = <0x4ed00000 0x10000>;
			#interrupt-cells = <1>;
			interrupt-controller;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 0x9a>;
			clock-names = "ipg";
			fsl,channel = <0>;
			fsl,num-irqs = <512>;
			status = "disabled";
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu2>;
				};

				core1 {
					cpu = <&cpu3>;
				};
			};

			cluster2 {
				core0 {
					cpu = <&cpu4>;
				};

				core1 {
					cpu = <&cpu5>;
				};
			};

			cluster3 {
				core0 {
					cpu = <&cpu6>;
				};

				core1 {
					cpu = <&cpu7>;
				};
			};
		};

		l2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-size = <524288>;
			cache-unified;
			next-level-cache = <&l3_0>;
		};

		l2_1: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-size = <524288>;
			cache-unified;
			next-level-cache = <&l3_1>;
		};

		l2_2: l2-cache2 {
			compatible = "cache";
			cache-level = <2>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-size = <524288>;
			cache-unified;
			next-level-cache = <&l3_2>;
		};

		l2_3: l2-cache3 {
			compatible = "cache";
			cache-level = <2>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-size = <524288>;
			cache-unified;
			next-level-cache = <&l3_3>;
		};

		l3_0: l3-cache0 {
			compatible = "cache";
			cache-level = <3>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-size = <1048576>;
			cache-unified;
		};

		l3_1: l3-cache1 {
			compatible = "cache";
			cache-level = <3>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-size = <1048576>;
			cache-unified;
		};

		l3_2: l3-cache2 {
			compatible = "cache";
			cache-level = <3>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-size = <1048576>;
			cache-unified;
		};

		l3_3: l3-cache3 {
			compatible = "cache";
			cache-level = <3>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-size = <1048576>;
			cache-unified;
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a78ae";
			reg = <0x0>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&l2_0>;
		};

		cpu1: cpu@100 {
			compatible = "arm,cortex-a78ae";
			reg = <0x100>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&l2_0>;
		};

		cpu2: cpu@10000 {
			compatible = "arm,cortex-a78ae";
			reg = <0x10000>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&l2_1>;
		};

		cpu3: cpu@10100 {
			compatible = "arm,cortex-a78ae";
			reg = <0x10100>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&l2_1>;
		};

		cpu4: cpu@20000 {
			compatible = "arm,cortex-a78ae";
			reg = <0x20000>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&l2_2>;
		};

		cpu5: cpu@20100 {
			compatible = "arm,cortex-a78ae";
			reg = <0x20100>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&l2_2>;
		};

		cpu6: cpu@30000 {
			compatible = "arm,cortex-a78ae";
			reg = <0x30000>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&l2_3>;
		};

		cpu7: cpu@30100 {
			compatible = "arm,cortex-a78ae";
			reg = <0x30100>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&l2_3>;
		};
	};

	firmware {
		psci {
			compatible = "arm,psci-1.0";
			method = "smc";
		};

		scmi: scmi {
			compatible = "arm,scmi-smc";
			#address-cells = <1>;
			#size-cells = <0>;
			shmem = <&scmi_shbuf>;
			arm,smc-id = <0xc20000fe>;
			status = "okay";

			clks: protocol@14 {
				reg = <0x14>;
				#clock-cells = <1>;
			};
		};
	};

	fss-bus {
		compatible = "simple-bus";
		ranges = <0x5b490000 0x0 0x5b490000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		usdhc0: mmc@5b490000 {
			compatible = "nxp,s32n79-usdhc";
			reg = <0x5b490000 0x1000>;
			interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 0x58>, <&clks 0x50>, <&clks 0x5f>;
			clock-names = "ipg", "ahb", "per";
			bus-width = <8>;
			status = "disabled";
		};
	};

	pmu: pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};
};