// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include #include "monaco.dtsi" #include "monaco-pmics.dtsi" / { /* This comes from a PMIC handled within the SAIL domain */ vreg_s2s: vreg-s2s { compatible = "regulator-fixed"; regulator-name = "vreg_s2s"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; }; &apps_rsc { regulators-0 { compatible = "qcom,pmm8654au-rpmh-regulators"; qcom,pmic-id = "a"; vreg_l3a: ldo3 { regulator-name = "vreg_l3a"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; regulator-always-on; }; vreg_l4a: ldo4 { regulator-name = "vreg_l4a"; regulator-min-microvolt = <880000>; regulator-max-microvolt = <912000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; }; vreg_l5a: ldo5 { regulator-name = "vreg_l5a"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; }; vreg_l6a: ldo6 { regulator-name = "vreg_l6a"; regulator-min-microvolt = <880000>; regulator-max-microvolt = <912000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; }; vreg_l7a: ldo7 { regulator-name = "vreg_l7a"; regulator-min-microvolt = <880000>; regulator-max-microvolt = <912000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; }; vreg_l8a: ldo8 { regulator-name = "vreg_l8a"; regulator-min-microvolt = <2504000>; regulator-max-microvolt = <2960000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; }; vreg_l9a: ldo9 { regulator-name = "vreg_l9a"; regulator-min-microvolt = <2970000>; regulator-max-microvolt = <3072000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; }; }; regulators-1 { compatible = "qcom,pmm8654au-rpmh-regulators"; qcom,pmic-id = "c"; vreg_s5c: smps5 { /* LPDDR VDD2H */ regulator-name = "vreg_s5c"; regulator-min-microvolt = <1104000>; regulator-max-microvolt = <1104000>; regulator-initial-mode = ; }; vreg_l1c: ldo1 { /* LPDDR VDDQ */ regulator-name = "vreg_l1c"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <512000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; }; vreg_l2c: ldo2 { /* LPDDR VDD2L */ regulator-name = "vreg_l2c"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <904000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; }; vreg_l4c: ldo4 { regulator-name = "vreg_l4c"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; }; vreg_l7c: ldo7 { regulator-name = "vreg_l7c"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; }; vreg_l8c: ldo8 { /* LPDDR VDD1 */ regulator-name = "vreg_l8c"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; }; vreg_l9c: ldo9 { /* QFPROM */ regulator-name = "vreg_l9c"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; }; }; }; &mdss_dp0 { pinctrl-0 = <&dp_hpd>; pinctrl-names = "default"; }; &mdss_dp0_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l4a>; }; &mdss_dsi0 { vdda-supply = <&vreg_l5a>; }; &mdss_dsi0_phy { vdds-supply = <&vreg_l4a>; }; &gpi_dma0 { status = "okay"; }; &gpi_dma1 { status = "okay"; }; &gpu { status = "okay"; }; &gpu_zap_shader { firmware-name = "qcom/qcs8300/a623_zap.mbn"; }; &iris { status = "okay"; }; /* PCIe0 Gen4 x2 */ &pcie0 { iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, <0x100 &pcie_smmu 0x0001 0x1>, <0x200 &pcie_smmu 0x0007 0x1>, <0x208 &pcie_smmu 0x0002 0x1>, <0x210 &pcie_smmu 0x0003 0x1>, <0x218 &pcie_smmu 0x0004 0x1>, <0x300 &pcie_smmu 0x0005 0x1>, <0x400 &pcie_smmu 0x0006 0x1>; status = "okay"; }; &pcie0_phy { vdda-phy-supply = <&vreg_l6a>; vdda-pll-supply = <&vreg_l5a>; status = "okay"; }; /* PCIe1 Gen4 x4 */ &pcie1 { status = "okay"; }; &pcie1_phy { vdda-phy-supply = <&vreg_l6a>; vdda-pll-supply = <&vreg_l5a>; status = "okay"; }; &qupv3_id_0 { firmware-name = "qcom/qcs8300/qupv3fw.elf"; status = "okay"; }; &qupv3_id_1 { firmware-name = "qcom/qcs8300/qupv3fw.elf"; status = "okay"; }; /* There is a HW/FW issue preventing proper REFGEN hardware voting * for the USB2 HS PHY. As a workaround, we force REFGEN to stay * always‑on in software, matching initial bootloader config. */ &refgen { regulator-always-on; }; &remoteproc_adsp { firmware-name = "qcom/qcs8300/adsp.mbn"; status = "okay"; }; &remoteproc_cdsp { firmware-name = "qcom/qcs8300/cdsp0.mbn"; status = "okay"; }; &remoteproc_gpdsp { firmware-name = "qcom/qcs8300/gpdsp0.mbn"; status = "okay"; }; /* OnSom eMMC */ &sdhc_1 { vmmc-supply = <&vreg_l8a>; vqmmc-supply = <&vreg_s2s>; bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; no-sd; no-sdio; non-removable; status = "okay"; }; /* Ethernet/SGMII */ &serdes0 { phy-supply = <&vreg_l5a>; status = "okay"; }; &tlmm { dp_hpd: dp-hpd-state { pins = "gpio94"; function = "edp0_hot"; bias-disable; }; }; /* USB0 HS + SS */ &usb_1_hsphy { vdda-pll-supply = <&vreg_l7a>; vdda18-supply = <&vreg_l7c>; vdda33-supply = <&vreg_l9a>; status = "okay"; }; &usb_qmpphy { vdda-phy-supply = <&vreg_l7a>; vdda-pll-supply = <&vreg_l5a>; status = "okay"; }; /* USB1 HS */ &usb_2_hsphy { vdda-pll-supply = <&vreg_l7a>; vdda18-supply = <&vreg_l7c>; vdda33-supply = <&vreg_l9a>; status = "okay"; };