/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (c) 2024 Linaro Limited * Author: Raymond Mao */ #ifndef _SMBIOS_DEF_H_ #define _SMBIOS_DEF_H_ /* * BIOS characteristics */ #define BIOS_CHARACTERISTICS_PCI_SUPPORTED 0x80 /* BIT(7) */ #define BIOS_CHARACTERISTICS_UPGRADEABLE 0x800 /* BIT(11) */ #define BIOS_CHARACTERISTICS_SELECTABLE_BOOT 0x10000 /* BIT(16) */ #define BIOS_CHARACTERISTICS_EXT1_ACPI 1 /* BIT(0) */ #define BIOS_CHARACTERISTICS_EXT2_UEFI 8 /* BIT(3) */ #define BIOS_CHARACTERISTICS_EXT2_TARGET 4 /* BIT(2) */ /* * System Information */ #define SMBIOS_WAKEUP_TYPE_RESERVED 0 #define SMBIOS_WAKEUP_TYPE_OTHER 1 #define SMBIOS_WAKEUP_TYPE_UNKNOWN 2 #define SMBIOS_WAKEUP_TYPE_APM_TIMER 3 #define SMBIOS_WAKEUP_TYPE_MODEM_RING 4 #define SMBIOS_WAKEUP_TYPE_LAN_REMOTE 5 #define SMBIOS_WAKEUP_TYPE_POWER_SWITCH 6 #define SMBIOS_WAKEUP_TYPE_PCI_PME 7 #define SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED 8 /* * Baseboard Information */ #define SMBIOS_BOARD_FEAT_HOST_BOARD 1 /* BIT(0) */ #define SMBIOS_BOARD_FEAT_REQ_AUX 2 /* BIT(1) */ #define SMBIOS_BOARD_FEAT_REMOVABLE 4 /* BIT(2) */ #define SMBIOS_BOARD_FEAT_REPLACEABLE 8 /* BIT(3) */ #define SMBIOS_BOARD_FEAT_HOT_SWAPPABLE 16 /* BIT(4) */ #define SMBIOS_BOARD_TYPE_UNKNOWN 1 #define SMBIOS_BOARD_TYPE_OTHER 2 #define SMBIOS_BOARD_TYPE_SERVER_BLADE 3 #define SMBIOS_BOARD_TYPE_CON_SWITCH 4 #define SMBIOS_BOARD_TYPE_SM_MODULE 5 #define SMBIOS_BOARD_TYPE_PROCESSOR_MODULE 6 #define SMBIOS_BOARD_TYPE_IO_MODULE 7 #define SMBIOS_BOARD_TYPE_MEM_MODULE 8 #define SMBIOS_BOARD_TYPE_DAUGHTER_BOARD 9 #define SMBIOS_BOARD_TYPE_MOTHERBOARD 10 #define SMBIOS_BOARD_TYPE_PROC_MEM_MODULE 11 #define SMBIOS_BOARD_TYPE_PROC_IO_MODULE 12 #define SMBIOS_BOARD_TYPE_INTERCON 13 /* * System Enclosure or Chassis */ #define SMBIOS_ENCLOSURE_UNKNOWN 2 #define SMBIOS_ENCLOSURE_DESKTOP 3 #define SMBIOS_STATE_OTHER 1 #define SMBIOS_STATE_UNKNOWN 2 #define SMBIOS_STATE_SAFE 3 #define SMBIOS_STATE_WARNING 4 #define SMBIOS_STATE_CRITICAL 5 #define SMBIOS_STATE_NONRECOVERABLE 6 #define SMBIOS_SECURITY_OTHER 1 #define SMBIOS_SECURITY_UNKNOWN 2 #define SMBIOS_SECURITY_NONE 3 #define SMBIOS_SECURITY_EXTINT_LOCK 4 #define SMBIOS_SECURITY_EXTINT_EN 5 #define SMBIOS_ENCLOSURE_OEM_UND 0 #define SMBIOS_ENCLOSURE_HEIGHT_UND 0 #define SMBIOS_POWCORD_NUM_UND 0 #define SMBIOS_ELEMENT_TYPE_SELECT 0x80 /* BIT(7) */ /* * Processor Information */ #define SMBIOS_PROCESSOR_TYPE_OTHER 1 #define SMBIOS_PROCESSOR_TYPE_UNKNOWN 2 #define SMBIOS_PROCESSOR_TYPE_CENTRAL 3 #define SMBIOS_PROCESSOR_TYPE_MATH 4 #define SMBIOS_PROCESSOR_TYPE_DSP 5 #define SMBIOS_PROCESSOR_TYPE_VIDEO 6 #define SMBIOS_PROCESSOR_STATUS_UNKNOWN 0 #define SMBIOS_PROCESSOR_STATUS_ENABLED 1 #define SMBIOS_PROCESSOR_STATUS_DISABLED_USER 2 #define SMBIOS_PROCESSOR_STATUS_DISABLED_BIOS 3 #define SMBIOS_PROCESSOR_STATUS_IDLE 4 #define SMBIOS_PROCESSOR_STATUS_OTHER 7 #define SMBIOS_PROCESSOR_UPGRADE_OTHER 1 #define SMBIOS_PROCESSOR_UPGRADE_UNKNOWN 2 #define SMBIOS_PROCESSOR_UPGRADE_NONE 6 #define SMBIOS_PROCESSOR_FAMILY_OTHER 1 #define SMBIOS_PROCESSOR_FAMILY_UNKNOWN 2 #define SMBIOS_PROCESSOR_FAMILY_RSVD 255 #define SMBIOS_PROCESSOR_FAMILY_ARMV7 256 #define SMBIOS_PROCESSOR_FAMILY_ARMV8 257 #define SMBIOS_PROCESSOR_FAMILY_RV32 512 #define SMBIOS_PROCESSOR_FAMILY_RV64 513 #define SMBIOS_PROCESSOR_FAMILY_EXT 0xfe /* Processor Characteristics */ #define SMBIOS_PROCESSOR_RSVD 1 /* BIT(0) */ #define SMBIOS_PROCESSOR_UND 2 /* BIT(1) */ #define SMBIOS_PROCESSOR_64BIT 4 /* BIT(2) */ #define SMBIOS_PROCESSOR_MULTICORE 8 /* BIT(3) */ #define SMBIOS_PROCESSOR_HWTHREAD 16 /* BIT(4) */ #define SMBIOS_PROCESSOR_EXEC_PROT 32 /* BIT(5) */ #define SMBIOS_PROCESSOR_ENH_VIRT 64 /* BIT(6) */ #define SMBIOS_PROCESSOR_POW_CON 0x80 /* BIT(7) */ #define SMBIOS_PROCESSOR_128BIT 0x100 /* BIT(8) */ #define SMBIOS_PROCESSOR_ARM64_SOCID 0x200 /* BIT(9) */ /* * Cache Information */ #define SMBIOS_CACHE_SIZE_EXT_KB (2047 * 1024) /* 2047 MiB */ #define SMBIOS_CACHE_HANDLE_NONE 0xffff /* System Cache Type */ #define SMBIOS_CACHE_SYSCACHE_TYPE_OTHER 1 #define SMBIOS_CACHE_SYSCACHE_TYPE_UNKNOWN 2 #define SMBIOS_CACHE_SYSCACHE_TYPE_INST 3 #define SMBIOS_CACHE_SYSCACHE_TYPE_DATA 4 #define SMBIOS_CACHE_SYSCACHE_TYPE_UNIFIED 5 /* Cache Speed */ #define SMBIOS_CACHE_SPEED_UNKNOWN 0 /* SRAM Type */ #define SMBIOS_CACHE_SRAM_TYPE_UNKNOWN 2 /* BIT(1) */ /* Error Correction Type */ #define SMBIOS_CACHE_ERRCORR_OTHER 1 #define SMBIOS_CACHE_ERRCORR_UNKNOWN 2 #define SMBIOS_CACHE_ERRCORR_NONE 3 #define SMBIOS_CACHE_ERRCORR_PARITY 4 #define SMBIOS_CACHE_ERRCORR_SBITECC 5 #define SMBIOS_CACHE_ERRCORR_MBITECC 6 /* Cache Configuration */ #define SMBIOS_CACHE_LEVEL_1 0 #define SMBIOS_CACHE_LEVEL_2 1 #define SMBIOS_CACHE_LEVEL_3 2 #define SMBIOS_CACHE_LEVEL_4 3 #define SMBIOS_CACHE_LEVEL_5 4 #define SMBIOS_CACHE_LEVEL_6 5 #define SMBIOS_CACHE_LEVEL_7 6 #define SMBIOS_CACHE_LEVEL_8 7 #define SMBIOS_CACHE_SOCKETED 8 /* BIT(3) */ #define SMBIOS_CACHE_LOCATE_EXTERNAL 32 /* BIT(5) */ #define SMBIOS_CACHE_LOCATE_RESERVED 64 /* BIT(6) */ #define SMBIOS_CACHE_LOCATE_UNKNOWN 96 /* (BIT(5) | BIT(6)) */ #define SMBIOS_CACHE_ENABLED 0x80 /* BIT(7) */ #define SMBIOS_CACHE_OP_WB 0x100 /* BIT(8), Write Back */ #define SMBIOS_CACHE_OP_VAR 0x200 /* BIT(9), Varies with Memory Address */ #define SMBIOS_CACHE_OP_UND 0x300 /* (BIT(8) | BIT(9)), Unknown*/ /* Cache Granularity */ #define SMBIOS_CACHE_GRANU_1K 0 #define SMBIOS_CACHE_GRANU_64K 1 /* Cache Associativity */ #define SMBIOS_CACHE_ASSOC_OTHER 1 #define SMBIOS_CACHE_ASSOC_UNKNOWN 2 #define SMBIOS_CACHE_ASSOC_DMAPPED 3 #define SMBIOS_CACHE_ASSOC_2WAY 4 #define SMBIOS_CACHE_ASSOC_4WAY 5 #define SMBIOS_CACHE_ASSOC_FULLY 6 #define SMBIOS_CACHE_ASSOC_8WAY 7 #define SMBIOS_CACHE_ASSOC_16WAY 8 #define SMBIOS_CACHE_ASSOC_12WAY 9 #define SMBIOS_CACHE_ASSOC_24WAY 10 #define SMBIOS_CACHE_ASSOC_32WAY 11 #define SMBIOS_CACHE_ASSOC_48WAY 12 #define SMBIOS_CACHE_ASSOC_64WAY 13 #define SMBIOS_CACHE_ASSOC_20WAY 14 /* * System Slot */ /* Slot Type */ #define SMBIOS_SYSSLOT_TYPE_OTHER 1 #define SMBIOS_SYSSLOT_TYPE_UNKNOWN 2 #define SMBIOS_SYSSLOT_TYPE_ISA 3 /* ISA */ #define SMBIOS_SYSSLOT_TYPE_PCI 6 /* PCI */ #define SMBIOS_SYSSLOT_TYPE_PCMCIA 7 /* PCMCIA */ #define SMBIOS_SYSSLOT_TYPE_PCIE 0xa5 /* PCI Express */ #define SMBIOS_SYSSLOT_TYPE_PCIEX1 0xa6 /* PCI Express x1 */ #define SMBIOS_SYSSLOT_TYPE_PCIEX2 0xa7 /* PCI Express x2 */ #define SMBIOS_SYSSLOT_TYPE_PCIEX4 0xa8 /* PCI Express x4 */ #define SMBIOS_SYSSLOT_TYPE_PCIEX8 0xa9 /* PCI Express x8 */ #define SMBIOS_SYSSLOT_TYPE_PCIEX16 0xaa /* PCI Express x16 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN2 0xab /* PCI Express Gen 2 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X1 0xac /* PCI Express Gen 2 x1 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X2 0xad /* PCI Express Gen 2 x2 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X4 0xae /* PCI Express Gen 2 x4 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X8 0xaf /* PCI Express Gen 2 x8 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X16 0xb0 /* PCI Express Gen 2 x16 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN3 0xb1 /* PCI Express Gen 3 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X1 0xb2 /* PCI Express Gen 3 x1 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X2 0xb3 /* PCI Express Gen 3 x2 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X4 0xb4 /* PCI Express Gen 3 x4 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X8 0xb5 /* PCI Express Gen 3 x8 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X16 0xb6 /* PCI Express Gen 3 x16 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN4 0xb8 /* PCI Express Gen 4 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X1 0xb9 /* PCI Express Gen 4 x1 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X2 0xba /* PCI Express Gen 4 x2 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X4 0xbb /* PCI Express Gen 4 x4 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X8 0xbc /* PCI Express Gen 4 x8 */ #define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X16 0xbd /* PCI Express Gen 4 x16 */ /* Slot Data Bus Width */ #define SMBIOS_SYSSLOT_WIDTH_OTHER 1 #define SMBIOS_SYSSLOT_WIDTH_UNKNOWN 2 #define SMBIOS_SYSSLOT_WIDTH_8BIT 3 #define SMBIOS_SYSSLOT_WIDTH_16BIT 4 #define SMBIOS_SYSSLOT_WIDTH_32BIT 5 #define SMBIOS_SYSSLOT_WIDTH_64BIT 6 #define SMBIOS_SYSSLOT_WIDTH_128BIT 7 #define SMBIOS_SYSSLOT_WIDTH_1X 8 #define SMBIOS_SYSSLOT_WIDTH_2X 9 #define SMBIOS_SYSSLOT_WIDTH_4X 10 #define SMBIOS_SYSSLOT_WIDTH_8X 11 #define SMBIOS_SYSSLOT_WIDTH_12X 12 #define SMBIOS_SYSSLOT_WIDTH_16X 13 #define SMBIOS_SYSSLOT_WIDTH_32X 14 /* Current Usage */ #define SMBIOS_SYSSLOT_USAGE_OTHER 1 #define SMBIOS_SYSSLOT_USAGE_UNKNOWN 2 #define SMBIOS_SYSSLOT_USAGE_AVAILABLE 3 #define SMBIOS_SYSSLOT_USAGE_INUSE 4 #define SMBIOS_SYSSLOT_USAGE_NA 5 /* Slot Length */ #define SMBIOS_SYSSLOT_LENG_OTHER 1 #define SMBIOS_SYSSLOT_LENG_UNKNOWN 2 #define SMBIOS_SYSSLOT_LENG_SHORT 3 #define SMBIOS_SYSSLOT_LENG_LONG 4 #define SMBIOS_SYSSLOT_LENG_2_5INDRV 5 #define SMBIOS_SYSSLOT_LENG_3_5INDRV 6 /* Slot Characteristics 1 */ #define SMBIOS_SYSSLOT_CHAR_UND 1 /* BIT(0) */ #define SMBIOS_SYSSLOT_CHAR_5V 2 /* BIT(1) */ #define SMBIOS_SYSSLOT_CHAR_3_3V 4 /* BIT(2) */ #define SMBIOS_SYSSLOT_CHAR_SHARED 8 /* BIT(3) */ #define SMBIOS_SYSSLOT_CHAR_PCCARD16 16 /* BIT(4) */ #define SMBIOS_SYSSLOT_CHAR_PCCARDBUS 32 /* BIT(5) */ #define SMBIOS_SYSSLOT_CHAR_PCCARDZV 64 /* BIT(6) */ #define SMBIOS_SYSSLOT_CHAR_PCCARDMRR 0x80 /* BIT(7) */ /* Slot Characteristics 2 */ #define SMBIOS_SYSSLOT_CHAR_PCIPME 1 /* BIT(0) */ #define SMBIOS_SYSSLOT_CHAR_HOTPLUG 2 /* BIT(1) */ #define SMBIOS_SYSSLOT_CHAR_PCISMB 4 /* BIT(2) */ #define SMBIOS_SYSSLOT_CHAR_PCIBIF 8 /* BIT(3) */ #define SMBIOS_SYSSLOT_CHAR_ASYNCRM 16 /* BIT(4) */ #define SMBIOS_SYSSLOT_CHAR_FBCXL1 32 /* BIT(5) */ #define SMBIOS_SYSSLOT_CHAR_FBCXL2 64 /* BIT(6) */ #define SMBIOS_SYSSLOT_CHAR_FBCXL3 0x80 /* BIT(7) */ /* Slot segment group number */ #define SMBIOS_SYSSLOT_SGGNUM_UND 0 /* Physical Memory Array */ /* Location */ #define SMBIOS_MA_LOCATION_OTHER 1 #define SMBIOS_MA_LOCATION_UNKNOWN 2 #define SMBIOS_MA_LOCATION_MOTHERBOARD 3 /* Use */ #define SMBIOS_MA_USE_OTHER 1 #define SMBIOS_MA_USE_UNKNOWN 2 #define SMBIOS_MA_USE_SYSTEM 3 #define SMBIOS_MA_USE_VIDEO 4 #define SMBIOS_MA_USE_FLASH 5 #define SMBIOS_MA_USE_NVRAM 6 #define SMBIOS_MA_USE_CACHE 7 /* Error Correction Type */ #define SMBIOS_MA_ERRCORR_OTHER 1 #define SMBIOS_MA_ERRCORR_UNKNOWN 2 #define SMBIOS_MA_ERRCORR_NONE 3 #define SMBIOS_MA_ERRCORR_PARITY 4 #define SMBIOS_MA_ERRCORR_SBITECC 5 #define SMBIOS_MA_ERRCORR_MBITECC 6 #define SMBIOS_MA_ERRCORR_CRC 7 /* Error Information Handle */ #define SMBIOS_MA_ERRINFO_NONE 0xFFFE #define SMBIOS_MA_ERRINFO_NOERR 0xFFFF /* Memory Device */ /* Size */ #define SMBIOS_MD_SIZE_UNKNOWN 0xFFFF #define SMBIOS_MD_SIZE_EXT 0x7FFF /* Form Factor */ #define SMBIOS_MD_FF_OTHER 1 #define SMBIOS_MD_FF_UNKNOWN 2 #define SMBIOS_MD_FF_SIMM 3 #define SMBIOS_MD_FF_SIP 4 #define SMBIOS_MD_FF_CHIP 5 #define SMBIOS_MD_FF_DIP 6 #define SMBIOS_MD_FF_ZIP 7 #define SMBIOS_MD_FF_PROPCARD 8 #define SMBIOS_MD_FF_DIMM 9 #define SMBIOS_MD_FF_TSOP 10 #define SMBIOS_MD_FF_ROC 11 #define SMBIOS_MD_FF_RIMM 12 #define SMBIOS_MD_FF_SODIMM 13 #define SMBIOS_MD_FF_SRIMM 14 #define SMBIOS_MD_FF_FBDIMM 15 #define SMBIOS_MD_FF_DIE 16 /* Device set */ #define SMBIOS_MD_DEVSET_NONE 0 #define SMBIOS_MD_DEVSET_UNKNOWN 0xFF /* Speed */ #define SMBIOS_MD_SPEED_UNKNOWN 0 #define SMBIOS_MD_SPEED_EXT 0xFFFF /* Attributes */ #define SMBIOS_MD_ATTR_RANK_UNKNOWN 0 /* Configured Memory Speed */ #define SMBIOS_MD_CONFSPEED_UNKNOWN 0 #define SMBIOS_MD_CONFSPEED_EXT 0xFFFF /* Voltage */ #define SMBIOS_MD_VOLTAGE_UNKNOWN 0 /* Type */ #define SMBIOS_MD_TYPE_OTHER 1 #define SMBIOS_MD_TYPE_UNKNOWN 2 #define SMBIOS_MD_TYPE_DRAM 3 #define SMBIOS_MD_TYPE_EDRAM 4 #define SMBIOS_MD_TYPE_VRAM 5 #define SMBIOS_MD_TYPE_SRAM 6 #define SMBIOS_MD_TYPE_RAM 7 #define SMBIOS_MD_TYPE_ROM 8 #define SMBIOS_MD_TYPE_FLASH 9 #define SMBIOS_MD_TYPE_EEPROM 10 #define SMBIOS_MD_TYPE_FEPROM 11 #define SMBIOS_MD_TYPE_EPROM 12 #define SMBIOS_MD_TYPE_CDRAM 13 #define SMBIOS_MD_TYPE_3DRAM 14 #define SMBIOS_MD_TYPE_SDRAM 15 #define SMBIOS_MD_TYPE_SGRAM 16 #define SMBIOS_MD_TYPE_RDRAM 17 #define SMBIOS_MD_TYPE_DDR 18 #define SMBIOS_MD_TYPE_DDR2 19 #define SMBIOS_MD_TYPE_DDR2FBD 20 #define SMBIOS_MD_TYPE_RSVD1 21 #define SMBIOS_MD_TYPE_RSVD2 22 #define SMBIOS_MD_TYPE_DSVD3 23 #define SMBIOS_MD_TYPE_DDR3 24 #define SMBIOS_MD_TYPE_FBD2 25 #define SMBIOS_MD_TYPE_DDR4 26 #define SMBIOS_MD_TYPE_LPDDR 27 #define SMBIOS_MD_TYPE_LPDDR2 28 #define SMBIOS_MD_TYPE_LPDDR3 29 #define SMBIOS_MD_TYPE_LPDDR4 30 #define SMBIOS_MD_TYPE_LNVD 31 #define SMBIOS_MD_TYPE_HBM 32 #define SMBIOS_MD_TYPE_HBM2 33 #define SMBIOS_MD_TYPE_DDR5 34 #define SMBIOS_MD_TYPE_LPDDR5 35 #define SMBIOS_MD_TYPE_HBM3 36 /* Type Detail */ #define SMBIOS_MD_TD_RSVD 1 /* BIT(0), set to 0 */ #define SMBIOS_MD_TD_OTHER 2 /* BIT(1) */ #define SMBIOS_MD_TD_UNKNOWN 4 /* BIT(2) */ #define SMBIOS_MD_TD_FP 8 /* BIT(3) */ #define SMBIOS_MD_TD_SC 0x10 /* BIT(4) */ #define SMBIOS_MD_TD_PS 0x20 /* BIT(5) */ #define SMBIOS_MD_TD_RAMBUS 0x40 /* BIT(6) */ #define SMBIOS_MD_TD_SYNC 0x80 /* BIT(7) */ #define SMBIOS_MD_TD_CMOS 0x100 /* BIT(8) */ #define SMBIOS_MD_TD_EDO 0x200 /* BIT(9) */ #define SMBIOS_MD_TD_WINDRAM 0x400 /* BIT(10) */ #define SMBIOS_MD_TD_CACHEDRAM 0x800 /* BIT(11) */ #define SMBIOS_MD_TD_NV 0x1000 /* BIT(12) */ #define SMBIOS_MD_TD_RGSTD 0x2000 /* BIT(13) */ #define SMBIOS_MD_TD_UNRGSTD 0x4000 /* BIT(14) */ #define SMBIOS_MD_TD_LRDIMM 0x8000 /* BIT(15) */ /* Technology */ #define SMBIOS_MD_TECH_OTHER 1 #define SMBIOS_MD_TECH_UNKNOWN 2 #define SMBIOS_MD_TECH_DRAM 3 #define SMBIOS_MD_TECH_NVDIMMN 4 #define SMBIOS_MD_TECH_NVDIMMF 5 #define SMBIOS_MD_TECH_NVDIMMP 6 #define SMBIOS_MD_TECH_OPTANE 7 /* Operating Mode Capability */ #define SMBIOS_MD_OPMC_RSVD 1 /* BIT(0), set to 0 */ #define SMBIOS_MD_OPMC_OTHER 2 /* BIT(1) */ #define SMBIOS_MD_OPMC_UNKNOWN 4 /* BIT(2) */ #define SMBIOS_MD_OPMC_VM 8 /* BIT(3) */ #define SMBIOS_MD_OPMC_BYTEAPM 0x10 /* BIT(4) */ #define SMBIOS_MD_OPMC_BLKAPM 0x20 /* BIT(5) */ /* Bit 6:15 Reserved, set to 0 */ /* Non-volatile / Volatile / Cache / Logical portion Size */ #define SMBIOS_MD_PORT_SIZE_NONE 0 #define SMBIOS_MD_PORT_SIZE_UNKNOWN_HI 0xFFFFFFFF #define SMBIOS_MD_PORT_SIZE_UNKNOWN_LO 0xFFFFFFFF #define SMBIOS_MS_PORT_SIZE_UNKNOWN 0xFFFFFFFFFFFFFFFF /* Error Information Handle */ #define SMBIOS_MD_ERRINFO_NONE 0xFFFE #define SMBIOS_MD_ERRINFO_NOERR 0xFFFF /* Memory Array Mapped Address */ /* Partition Width */ #define SMBIOS_MAMA_PW_DEF 1 /* not partitioned */ #endif /* _SMBIOS_DEF_H_ */