path: root/arch/arm/mach-sc5xx/Kconfig

# SPDX-License-Identifier: GPL-2.0-or-later
#
# (C) Copyright 2022 - Analog Devices, Inc.
#
# Written by Timesys Corporation
#

# All 32-bit platforms require SYS_ARM_CACHE_WRITETHROUGH
# But it is ignored if selected here, so it must be in the defconfig

if ARCH_SC5XX

config SYS_VENDOR
	default "adi"

choice
	prompt "SC5xx SoC Select"
	help
	  Selects which series of Analog Devices SC5xx chips to support.

config SC57X
	bool "SC57x series"
	select COMMON_CLK_ADI_SC57X
	select CPU_V7A
	select TARGET_SC573_EZKIT

config SC58X
	bool "SC58x series"
	select COMMON_CLK_ADI_SC58X
	select CPU_V7A

config SC59X
	bool "SC59x 32-bit series"
	select COMMON_CLK_ADI_SC594
	select CPU_V7A
	select NOP_PHY if PHY

config SC59X_64
	bool "SC59x 64-bit series"
	select ARM64
	select COMMON_CLK_ADI_SC598
	select GICV3
	select GICV3_SUPPORT_GIC600
	select GIC_600_CLEAR_RDPD
	select MMC_SDHCI_ADMA_FORCE_32BIT
	select NOP_PHY if PHY

endchoice

if SC57X

config TARGET_SC573_EZKIT
	bool "Support SC573-EZKIT"

endif

if SC58X

choice
	prompt "SC58x board select"

config TARGET_SC584_EZKIT
	bool
	prompt "SC584-EZKIT"
	select ADI_USE_DDR2

config TARGET_SC589_MINI
	bool
	prompt "SC589-MINI"

config TARGET_SC589_EZKIT
	bool
	prompt "SC589-EZKIT"

endchoice

endif

if SC59X

choice
	prompt "SC59x 32-bit board select"

config TARGET_SC594_SOM_EZLITE
	bool
	prompt "SC594-SOM with SOMCRR-EZLITE"
	select ADI_CARRIER_SOMCRR_EZLITE

config TARGET_SC594_SOM_EZKIT
	bool
	prompt "SC594-SOM with SOMCRR-EZKIT"
	select ADI_CARRIER_SOMCRR_EZKIT

endchoice

endif

if SC59X_64

choice
	prompt "SC59x 64-bit board select"

config TARGET_SC598_SOM_EZLITE
	bool
	prompt "SC598-SOM with SOMCRR-EZLITE"
	select ADI_CARRIER_SOMCRR_EZLITE

config TARGET_SC598_SOM_EZKIT
	bool
	prompt "SC598-SOM with SOMCRR-EZKIT"
	select ADI_CARRIER_SOMCRR_EZKIT

endchoice

endif

config SC5XX_UBOOT_SPL_OFFSET
	hex "SPL offset"
	default 0x0
	help
	  The default offset where the SPL is located.

config SC5XX_UBOOT_OFFSET
	hex "U-Boot offset"
	default 0x40000
	help
	  The default offset where u-boot is located.

config SC5XX_FITIMAGE_OFFSET
	hex "FitImage offset"
	default 0x1a0000
	help
	  The default offset where the fitImage is located.

config SC5XX_ROOTFS_OFFSET
	hex "RootFS offset"
	default 0x102000
	help
	  The default offset where the rootfs is located.

config SC5XX_LOADADDR
	hex "Load address"
	default 0x90000000
	help
	  The default load address for u-boot.

menu "Binman configuration"
config SC5XX_USE_BINMAN
	bool "Use binman for final image"
	select BINMAN
	help
	  If you wish to use binman to assemble an image, say 'Y' here.
	  This will enable binman-specific sections in the device tree.

config SC5XX_BINMAN_FILENAME
	string "Image name"
	default "sc5xx-image.img"
	depends on SC5XX_USE_BINMAN
	help
	  The name of the image that will be created by binman.
	  This is used to create the final image.

config SC5XX_FITIMAGE_NAME
	string "FitImage name"
	default "fitImage"
	depends on SC5XX_USE_BINMAN
	help
	  The name of the fitImage to be packed by binman.
	  This is used to create the final image.

config SC5XX_ROOTFS_NAME
	string "RootFS name"
	default "rootfs"
	depends on SC5XX_USE_BINMAN
	help
	  The name of the rootfs to be packed by binman.
	  This is used to create the final image.
endmenu

config ADI_IMAGE
	string "ADI fitImage type"
	help
	  The image built by the ADI ADSP Linux build system.
	  Is one of tiny, minimal, full.

config SC_BCODE
	int "SC5XX SPI BCODE select"
	default 1
	range 0 15
	help
	  This sets the BCODE option for the generated LDR file. The BCODE
	  is only used in SPI boots (QSPI/OSPI) but is set with no impact
	  in other boot modes so that one LDR file may be reused from any
	  boot media. The interpretation of this value is SoC and boot mode
	  specific, so you must refer to the HRM to interpret it.

config SC_BOOT_SPI_BUS
	int "sc5xx spi boot bus"
	default 2
	range 0 4
	help
	  This is the SPI peripheral number to use for booting, X in the
	  expression `sf probe X:Y`

config SC_BOOT_SPI_SSEL
	int "sc5xx spi boot chipselect"
	default 1
	range 0 6
	help
	  This is the SPI chip select number to use for booting, Y in the
	  expression `sf probe X:Y`

config SC_BOOT_OSPI_BUS
	int "sc5xx ospi boot bus"
	default 0
	help
	  This is the OSPI peripheral number to use for booting, X in the
	  expression `sf probe X:Y`

config SC_BOOT_OSPI_SSEL
	int "sc5xx ospi boot chipselect"
	default 0
	help
	  This is the OSPI chip select number to use for booting, Y in the
	  expression `sf probe X:Y`

config SYS_BOOTM_LEN
	hex
	default 0x1800000

config SYS_FLASH_BASE
	hex
	default 0x60000000

config SYS_MALLOC_F_LEN
	default 0x14000

config SYS_LOAD_ADDR
	hex
	default 0x0

config SYS_MALLOC_LEN
	hex
	default 1048576

config UART_CONSOLE
	int
	default 0

config UART4_SERIAL
	bool
	depends on DM_SERIAL
	default y

config WDT_ADI
	bool
	default y

config WATCHDOG_TIMEOUT_MSECS
	int
	default 30000

config DW_PORTS
	int
	default 1

config ADI_BUG_EZKHW21
	bool "SC584 EZKIT phy bug workaround"
	depends on SC58X
	help
	  This workaround affects the SC584 EZKIT and addresses bug EZKHW21.
	  It disables gigabit ethernet mode and limits the board to 100 Mbps

choice
	prompt "Analog Devices SOM Carrier Board Variant"
	depends on (SC59X || SC59X_64)
	default ADI_CARRIER_SOMCRR_EZKIT
	help
	  Select the specific EV-SOMCRR carrier board that you are using.
	  Using a SOM without a carrier board is not supported.

config ADI_CARRIER_SOMCRR_EZKIT
	bool "Support the EV-SOMCRR-EZKIT"
	help
	  Say y to include support for the EV-SOMCRR-EZKIT carrier board,
	  which is compatible with the SC594 and SC598 SOMs.

config ADI_CARRIER_SOMCRR_EZLITE
	bool "Support the EV-SOMCRR-EZLITE"
	help
	  Say y to include support for the EV-SOMCRR-EZLITE carrier board,
	  which is compatible with the SC594 and SC598 SOMs.

endchoice

config ADI_SPL_FORCE_BMODE
	int "Force the SPL to use this BMODE device during next boot stage"
	default 0
	range 0 9
	depends on SPL
	help
	  Force the SPL to use this BMODE device during next boot stage.
	  For example, if booting via QSPI, we can force the second stage
	  Of the boot process to use other peripherals via:
	  1 = QSPI -> QSPI
	  5 = QSPI -> OSPI
	  6 = QSPI -> eMMC

config ADI_USE_DMC0
	bool "Configure DMC0"
	default y
	help
	  During hardware initialization, channel 0 of the DMC will be
	  initialized. Select this if you have DMC0 connected to external
	  DDR memory. This is expected to be true for every board using
	  an SC5xx SoC.

config ADI_USE_DMC1
	bool "Configure DMC1"
	help
	  During hardware initialization, channel 1 of the DMC will be
	  initialized. Not all processors have a DMC1. Select this if your
	  SoC has DMC1 and you have it connected to external DDR memory.

config ADI_USE_DDR2
	bool "Configure DMC for DDR2 mode"
	help
	  Configure the DMC in DDR2 mode. The default is DDR3 and not all
	  parts may actually support DDR2. Please consult the manual for
	  the SoC that you are using to determine if DDR2 mode is supported.
	  This also requires that DDR2 memory is present on the board or it
	  will probably cause strange failure.

menu "Clock configuration"

config CGU0_DF_DIV
	int "CGU0_DF_DIV"
	range 0 1
	help
	  Select 0 to pass CLKIN to PLL
	  Select 1 to pass CLKIN/2 to PLL

config CGU0_VCO_MULT
	int "CGU0_VCO_MULT"
	range 0 127
	help
	  VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL
	  A value of 0 means 128

config CGU0_CCLK_DIV
	int "CGU0_CCLK_DIV"
	range 0 31
	help
	  CCLK_DIV controls the core clock divider
	  A value of 0 means 32
	  CCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / CCLK_DIV

config CGU0_SCLK_DIV
	int "CGU0_SCLK_DIV"
	range 0 31
	help
	  SCLK_DIV controls the system clock divider
	  A value of 0 means 32
	  SCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / SYSCLK_DIV

config CGU0_SCLK0_DIV
	int "CGU0_SCLK0_DIV"
	range 0 7
	help
	  A value of 0 means 8
	  SCLK0 = SCLK / SCLK0_DIV

config CGU0_SCLK1_DIV
	int "CGU0_SCLK1_DIV"
	depends on (SC57X || SC58X)
	range 0 7
	help
	  A value of 0 means 8
	  SCLK1 = SCLK / SCLK1_DIV

config CGU0_DCLK_DIV
	int "CGU0_DCLK_DIV"
	range 0 31
	help
	  DCLK_DIV controls the DDR clock divider
	  A value of 0 means 32
	  DCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / DCLK_DIV

config CGU0_OCLK_DIV
	int "CGU0_OCLK_DIV"
	range 0 127
	help
	  OCLK_DIV controls the output clock divider
	  A value of 0 means 128
	  OCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / OCLK_DIV

config CGU0_DIV_S1SELEX
	int "CGU0_DIV_S1SELEX"
	depends on !SC57X && !SC58X
	range 0 255
	help
	  CGU0 SCLK1 Extended divisor register.
	  A value of 0 means 256.
	  SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX

config CGU0_CLKOUTSEL
	int "CGU0_CLKOUTSEL"
	default 0
	range 0 31
	help
	  Select signal driven through CLKOUT pin multiplexer.
	  This value varies on each SOC. Refer to
	  CGU_CLKOUTSEL.CLKOUTSEL in the Hardware Reference Manual
	  for values applicable to each SOC.
	  Commonly, values 0 and 1 select CLKIN0 or CLKIN1 respectively.

config CGU1_PLL3_DDRCLK
	bool "DDRCLK From 3rd PLL"
	depends on SC59X_64
	help
	  3rd PLL output is connected to DMC block when set.
	  When cleared, DDR clock is CLKO3 output of CDU.

config CGU1_PLL3_VCO_MSEL
	int "CGU0_PLL3_VCO_MSEL"
	depends on CGU1_PLL3_DDRCLK
	range 1 128
	help
	  PLL multiplier value for the 3rd PLL.
	  DCLK = (CLKIN * PLL3_VCO_MSEL) / PLL3_DCLK_DIV

config CGU1_PLL3_DCLK_DIV
	int "CGU0_PLL3_DCLK_DIV"
	depends on CGU1_PLL3_DDRCLK
	range 1 32
	help
	  PLL divider value for the 3rd PLL.
	  DCLK = (CLKIN * PLL3_VCO_MSEL) / PLL3_DCLK_DIV

config CGU1_DF_DIV
	int "CGU1_DF_DIV"
	range 0 1
	help
	  Select 0 to pass CLKIN to PLL
	  Select 1 to pass CLKIN/2 to PLL

config CGU1_VCO_MULT
	int "CGU1_VCO_MULT"
	range 0 127
	help
	  VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL
	  A value of 0 means 128

config CGU1_CCLK_DIV
	int "CGU1_CCLK_DIV"
	range 0 31
	help
	  CCLK_DIV controls the core clock divider
	  A value of 0 means 32
	  CCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / CCLK_DIV

config CGU1_SCLK_DIV
	int "CGU1_SCLK_DIV"
	range 0 31
	help
	  SCLK_DIV controls the system clock divider
	  A value of 0 means 32
	  SCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / SYSCLK_DIV

config CGU1_SCLK0_DIV
	int "CGU1_SCLK0_DIV"
	depends on (SC57X || SC58X || SC59X)
	range 0 7
	help
	  A value of 0 means 8
	  SCLK0 = SCLK / SCLK0_DIV

config CGU1_SCLK1_DIV
	int "CGU1_SCLK1_DIV"
	depends on (SC57X || SC58X)
	range 0 7
	help
	  A value of 0 means 8
	  SCLK1 = SCLK / SCLK1_DIV

config CGU1_DCLK_DIV
	int "CGU1_DCLK_DIV"
	range 0 31
	help
	  DCLK_DIV controls the DDR clock divider
	  A value of 0 means 32
	  DCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / DCLK_DIV

config CGU1_OCLK_DIV
	int "CGU1_OCLK_DIV"
	range 0 127
	help
	  OCLK_DIV controls the output clock divider
	  A value of 0 means 128
	  OCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / OCLK_DIV

config CGU1_DIV_S0SELEX
	int "CGU1_DIV_S0SELEX"
	depends on !SC57X && !SC58X && !SC59X
	range 0 255
	help
	  CGU1 SCLK0 Extended divisor register.
	  A value of 0 means 256.
	  SCLK0 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S0SELEX

config CGU1_DIV_S1SELEX
	int "CGU1_DIV_S1SELEX"
	depends on !SC57X && !SC58X
	range 0 255
	help
	  CGU1 SCLK1 Extended divisor register.
	  A value of 0 means 256.
	  SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX

config CDU0_CGU1_CLKIN
	int "CDU0 CGU1 CLKINn Select"
	default 0
	range 0 1
	help
	  Selects source clock for CGU1.
	  0 for CLKIN0
	  1 for CLKIN1

config CDU0_CLKO0
	int "CDU0_CLKO0"
	range 1 7
	help
	  Clock source select. Refer to SOC Hardware Reference Manual

config CDU0_CLKO1
	int "CDU0_CLKO1"
	range 1 7
	help
	  Clock source select. Refer to SOC Hardware Reference Manual

config CDU0_CLKO2
	int "CDU0_CLKO2"
	range 1 7
	help
	  Clock source select. Refer to SOC Hardware Reference Manual

config CDU0_CLKO3
	int "CDU0_CLKO3"
	range 1 7
	help
	  Clock source select. Refer to SOC Hardware Reference Manual

config CDU0_CLKO4
	int "CDU0_CLKO4"
	range 1 7
	help
	  Clock source select. Refer to SOC Hardware Reference Manual

config CDU0_CLKO5
	int "CDU0_CLKO5"
	range 1 7
	help
	  Clock source select. Refer to SOC Hardware Reference Manual

config CDU0_CLKO6
	int "CDU0_CLKO6"
	range 1 7
	help
	  Clock source select. Refer to SOC Hardware Reference Manual

config CDU0_CLKO7
	int "CDU0_CLKO7"
	range 1 7
	help
	  Clock source select. Refer to SOC Hardware Reference Manual

config CDU0_CLKO8
	int "CDU0_CLKO8"
	range 1 7
	help
	  Clock source select. Refer to SOC Hardware Reference Manual

config CDU0_CLKO9
	int "CDU0_CLKO9"
	range 1 7
	help
	  Clock source select. Refer to SOC Hardware Reference Manual

config CDU0_CLKO10
	int "CDU0_CLKO10"
	range 1 7
	depends on (SC59X || SC59X_64)
	help
	  Clock source select. Refer to SOC Hardware Reference Manual

config CDU0_CLKO12
	int "CDU0_CLKO12"
	range 1 7
	depends on (SC59X || SC59X_64)
	help
	  Clock source select. Refer to SOC Hardware Reference Manual

config CDU0_CLKO13
	int "CDU0_CLKO13"
	range 1 7
	depends on SC59X_64
	help
	  Clock source select. Refer to SOC Hardware Reference Manual

config CDU0_CLKO14
	int "CDU0_CLKO14"
	range 1 7
	depends on SC59X_64
	help
	  Clock source select. Refer to SOC Hardware Reference Manual

endmenu

config ADI_GPIO
	bool
	default y

config PINCTRL_ADI
	bool
	default y

source "board/adi/sc598-som-ezkit/Kconfig"
source "board/adi/sc598-som-ezlite/Kconfig"
source "board/adi/sc594-som-ezkit/Kconfig"
source "board/adi/sc594-som-ezlite/Kconfig"
source "board/adi/sc589-ezkit/Kconfig"
source "board/adi/sc589-mini/Kconfig"
source "board/adi/sc584-ezkit/Kconfig"
source "board/adi/sc573-ezkit/Kconfig"

endif