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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
#include <config.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <hang.h>
#include <init.h>
#include <log.h>
#include <power/pmic.h>
#include <power/pca9450.h>
#include <spl.h>
#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION)
#include "../common/imx8m_som_detection.h"
#endif
#define EEPROM_ADDR 0x51
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
}
void spl_dram_init(void)
{
#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION)
int ret;
ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
if (!ret) {
ret = phytec_imx8m_detect(NULL);
if (!ret)
phytec_print_som_info(NULL);
}
#endif
ddr_init(&dram_timing);
}
int power_init_board(void)
{
struct udevice *dev;
int ret;
ret = pmic_get("pmic@25", &dev);
if (ret == -ENODEV) {
puts("No pmic@25\n");
return 0;
}
if (ret < 0)
return ret;
/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
/* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
/* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
/* Set WDOG_B_CFG to cold reset */
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
return 0;
}
void spl_board_init(void)
{
arch_misc_init();
/* Set GIC clock to 500Mhz for OD VDD_SOC. */
clock_enable(CCGR_GIC, 0);
clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
clock_enable(CCGR_GIC, 1);
}
int board_fit_config_name_match(const char *name)
{
return 0;
}
void board_init_f(ulong dummy)
{
int ret;
arch_cpu_init();
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
enable_tzc380();
power_init_board();
/* DDR initialization */
spl_dram_init();
}
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